# 
# $Id: Makefile.flags 146 2011-02-01 20:57:54Z rosiere $
# 
# [ Description ]
# 

ifeq ($(origin MORPHEO_TYPE), undefined)
        $(error "variable MORPHEO_TYPE is undefined");
endif

#-----[ Simulator ]----------------------------------------
SIMULATOR_SYSTEMC		?= systemc
SIMULATOR_VHDL                  ?= modelsim

# 4 simulators for systemC :
# systemc			-         supported - SystemC 2.2.0
# systemcass 			-         supported - SystemCASS
# systemcass_deps		- not yet supported - Systemcass, and use port dependency information instead of sensitivity list
# modelsim                      - not yet supported - Co simulation SystemC/VHDL with Modelsim

# 1 simulator for VHDL
# modelsim 			-         supported

#-----[ Flags ]--------------------------------------------

# If you add a MORPHEO_FLAGS, add name in array "type_list" in file "environment.sh"

MORPHEO_systemc_FLAGS		=	-DSYSTEMC		\
					-DSTATISTICS		\
					-DTRANSLATION

MORPHEO_vhdl_FLAGS		=	-DVHDL			\
					-DTRANSLATION

MORPHEO_cosim_FLAGS		=	-DSYSTEMC		\
					-DSTATISTICS		\
					-DVHDL			\
					-DTRANSLATION

MORPHEO_debug_FLAGS		=	-DSYSTEMC		\
					-DDEBUG=DEBUG_FUNC	\
					-DVHDL

MORPHEO_debug_systemc_FLAGS	=	-DSYSTEMC		\
					-DDEBUG=DEBUG_FUNC

MORPHEO_FLAGS			= $(MORPHEO_$(MORPHEO_TYPE)_FLAGS)

#                       | systemc | vhdl | cosim | debug | debug_systemc
#-----------------------+---------+------+-------+-------+---------------
# TRANSLATION		| X       | X    | X     |       |   
# SYSTEMC		| X       |      | X     | X     |  X
# STATISTICS		| X       |      | X     |       |  
# VHDL			|         | X    | X     | X     |   
# VHDL_TESTBENCH	|         |      |       |       |   
# VHDL_TESTBENCH_ASSERT	|         |      |       |       |   
# DEBUG           	|         |      |       | X     |  X
# DEBUG_MEMORY_LEAK	|         |      |       |       |   
# DEBUG_SIGNAL		|         |      |       |       |   
# POSITION		|         |      |       |       |   
# PRINT_COLOR		|         |      |       |       |   

# Flags :
# TRANSLATION	                              - Translate message
# SYSTEMC                                     - To generate a systemc's model
# STATISTICS            (need SYSTEMC)        - In the simulation, generate a statistics's file
# VHDL                                        - To generate a vhdl's    models
# VHDL_TESTBENCH        (need SYSTEMC)        - In the simulation, generate two testbench's file (input and ouput) to validate the vhdl's model
# VHDL_TESTBENCH_ASSERT (need VHDL_TESTBENCH) - In the simulation, generate in  testbench's file an serie of assert
# DEBUG={level}                               - Print Debug Message
# DEBUG_MEMORY_LEAK                           -
# DEBUG_SIGNAL                                -
# POSITION                                    - To generate a position's files     (it's input of viewer)
# PRINT_COLOR                                 - Print with colors