| 1 | {{{ |
| 2 | #!/usr/bin/env python |
| 3 | |
| 4 | import dsx |
| 5 | import soclib |
| 6 | |
| 7 | def VgmnNoirqMono(): |
| 8 | pf = soclib.Architecture(cell_size = 4, |
| 9 | plen_size = 8, |
| 10 | addr_size = 32, |
| 11 | rerror_size = 1, |
| 12 | clen_size = 1, |
| 13 | rflag_size = 1, |
| 14 | srcid_size = 8, |
| 15 | pktid_size = 1, |
| 16 | trdid_size = 1, |
| 17 | wrplen_size = 1 |
| 18 | ) |
| 19 | mt = pf.create('common:mapping_table', |
| 20 | 'mapping_table', |
| 21 | addr_bits = [8], |
| 22 | srcid_bits = [8], |
| 23 | cacheability_mask = 0xc00000) |
| 24 | pf.create('common:loader', 'loader') |
| 25 | |
| 26 | vgmn = pf.create('caba:vci_vgmn', 'vgmn0', *** remplir ***) |
| 27 | |
| 28 | cpu = pf.create('caba:vci_xcache_wrapper', 'cpu0', |
| 29 | iss_t = "common:mips32el", |
| 30 | ident = 0, |
| 31 | icache_ways = 1, |
| 32 | icache_sets = 16, |
| 33 | icache_words = 8, |
| 34 | dcache_ways = 1, |
| 35 | dcache_sets = 16, |
| 36 | dcache_words = 8) |
| 37 | |
| 38 | vgmn.to_initiator.new() // cpu.vci |
| 39 | |
| 40 | # Generation des coprocesseurs, commentée pour l'instant |
| 41 | # # Ici, on récupère l'implémentation matérielle de tg, qui va |
| 42 | # # nous permettre d'instancier le coprocesseur et son controlleur |
| 43 | # |
| 44 | # tg = dsx.TaskModel.getByName('tg').getImpl(soclib.HwTask) |
| 45 | # # La création nous retourne les deux composants crées. |
| 46 | # ctrl, coproc = tg.instanciate(pf, 'tg0') |
| 47 | # # Il reste à donner une adresse au controlleur, et le connecter |
| 48 | # # à l'interconnect (attention il a deux ports) |
| 49 | # ctrl.addSegment('tg_ctrl', 0x70400000, 0x100, False) |
| 50 | # ctrl.vci_initiator // vgmn.to_initiator.new() |
| 51 | # ctrl.vci_target // vgmn.to_target.new() |
| 52 | # |
| 53 | # # pareil avec ramdac |
| 54 | # ramdac = dsx.TaskModel.getByName('ramdac').getImpl(soclib.HwTask) |
| 55 | # ctrl, coproc = ramdac.instanciate(pf, 'ramdac0') |
| 56 | # ctrl.addSegment('ramdac_ctrl', 0x71400000, 0x100, False) |
| 57 | # ctrl.vci_initiator // vgmn.to_initiator.new() |
| 58 | # ctrl.vci_target // vgmn.to_target.new() |
| 59 | |
| 60 | |
| 61 | for i in range(2): |
| 62 | ram = pf.create('caba:vci_ram', 'ram%d'%i) |
| 63 | base = 0x10000000*i+0x10000000 |
| 64 | ram.addSegment('cram%d'%i, base, 0x100000, True) |
| 65 | ram.addSegment('uram%d'%i, base + 0x400000, 0x100000, False) |
| 66 | ram.vci // vgmn.to_target.new() |
| 67 | ram.addSegment('boot', *** remplir ***) # Mips boot address, 0x1000 octets, cacheable |
| 68 | ram.addSegment('excep', *** remplir ***) # Mips exception address, 0x1000 octets, cacheable |
| 69 | |
| 70 | tty = pf.create('caba:vci_multi_tty', 'tty0', names = ['tty0']) |
| 71 | tty.addSegment('tty0', 0x90400000, 0x20, False) |
| 72 | tty.vci // vgmn.to_target.new() |
| 73 | |
| 74 | return pf |
| 75 | |
| 76 | # This is a python quirk to generate the platform |
| 77 | # if this file is directly called, but only export |
| 78 | # methods if imported from somewhere else |
| 79 | |
| 80 | if __name__ == '__main__': |
| 81 | VgmnNoirqMono().generate(soclib.PfDriver()) |
| 82 | }}} |