Welcome to SystemCASS trac page

SystemCASS is a ​SystemC simulator cycle accurate, bit accurate.
This simulator is 15 times faster than OSCI's simulator (SystemC 2.1.v1).

Why is SystemCASS faster ?

During simulator initialization, SystemCASS builds a signal dependency graph according to the architecture to simulate. The scheduler relies on this graph to compute a fully statically scheduling.
SystemCASS is a evolution of CASS simulator developped by Frédéric Pétrot and Denis Hommais.

Which harware components can I use with ?

SystemCASS is a SystemC API, respecting LRM specifications. SystemC core language is supported.

However, SystemCASS supports only one clock and hardware components have to fit the FSM modeling approach. Each hardware component should contain three function kinds :

• Transition function;
• Moore generation function;
• Mealy generation function.

Transition function writes new states and depends on inputs. This kind of function is sensitive to positive clock edge.

Moore generation function writes new values to outputs and depends only on internal states. This kind of function is sensitive to negative clock edge.

Mealy generation function, also called combinational function, writes new values to outputs and depends on internal states and/or inputs. This kind of function is sensitive to negative clock edge and given inputs.

Download

• SystemCASS archive
• SVN repository

Bibliography

	​Ordonnancement statique versus événementiel (French)
	​Fast Cycle Accurate Simulator To Simulate Event-Driven Behavior
	​Fast Functional SystemC Simulator Using Static Scheduling

Enjoy!
SystemCASS Team