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source: branches/MESI/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h @ 686

Last change on this file since 686 was 686, checked in by haoliu, 10 years ago
MESI cosmetic in vci_cc_vcache_wrapper and vci_mem_cache bug fixed for LLSC
File size: 55.8 KB

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1	/* -- c++ --
2	* File : vci_mem_cache.h
3	* Date : 26/10/2008
4	* Copyright : UPMC / LIP6
5	* Authors : Alain Greiner / Eric Guthmuller
6	*
7	* SOCLIB_LGPL_HEADER_BEGIN
8	*
9	* This file is part of SoCLib, GNU LGPLv2.1.
10	*
11	* SoCLib is free software; you can redistribute it and/or modify it
12	* under the terms of the GNU Lesser General Public License as published
13	* by the Free Software Foundation; version 2.1 of the License.
14	*
15	* SoCLib is distributed in the hope that it will be useful, but
16	* WITHOUT ANY WARRANTY; without even the implied warranty of
17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18	* Lesser General Public License for more details.
19	*
20	* You should have received a copy of the GNU Lesser General Public
21	* License along with SoCLib; if not, write to the Free Software
22	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
23	* 02110-1301 USA
24	*
25	* SOCLIB_LGPL_HEADER_END
26	*
27	* Maintainers: alain.greiner@lip6.fr
28	* eric.guthmuller@polytechnique.edu
29	* cesar.fuguet-tortolero@lip6.fr
30	* alexandre.joannou@lip6.fr
31	*/
32
33	#ifndef SOCLIB_CABA_MEM_CACHE_H
34	#define SOCLIB_CABA_MEM_CACHE_H
35
36	#include <inttypes.h>
37	#include <systemc>
38	#include <list>
39	#include <cassert>
40	#include "arithmetics.h"
41	#include "alloc_elems.h"
42	#include "caba_base_module.h"
43	#include "vci_target.h"
44	#include "vci_initiator.h"
45	#include "generic_fifo.h"
46	#include "mapping_table.h"
47	#include "int_tab.h"
48	#include "generic_llsc_global_table.h"
49	#include "mem_cache_directory.h"
50	#include "xram_transaction.h"
51	#include "update_tab.h"
52	#include "dspin_interface.h"
53	#include "dspin_dhccp_param.h"
54
55	#define TRT_ENTRIES 4 // Number of entries in TRT
56	#define UPT_ENTRIES 4 // Number of entries in UPT
57	#define IVT_ENTRIES 4 // Number of entries in IVT
58	#define HEAP_ENTRIES 1024 // Number of entries in HEAP
59
60	namespace soclib { namespace caba {
61
62	using namespace sc_core;
63
64	template<typename vci_param_int,
65	typename vci_param_ext,
66	size_t dspin_in_width,
67	size_t dspin_out_width>
68	class VciMemCache
69	: public soclib::caba::BaseModule
70	{
71	typedef typename vci_param_int::fast_addr_t addr_t;
72	typedef typename sc_dt::sc_uint<64> wide_data_t;
73	typedef uint32_t data_t;
74	typedef uint32_t tag_t;
75	typedef uint32_t be_t;
76	typedef uint32_t copy_t;
77
78	/* States of the TGT_CMD fsm */
79	enum tgt_cmd_fsm_state_e
80	{
81	TGT_CMD_IDLE,
82	TGT_CMD_READ,
83	TGT_CMD_WRITE,
84	TGT_CMD_CAS,
85	TGT_CMD_ERROR,
86	TGT_CMD_CONFIG
87	};
88
89	/* States of the TGT_RSP fsm */
90	enum tgt_rsp_fsm_state_e
91	{
92	TGT_RSP_CONFIG_IDLE,
93	TGT_RSP_TGT_CMD_IDLE,
94	TGT_RSP_READ_IDLE,
95	TGT_RSP_WRITE_IDLE,
96	TGT_RSP_CAS_IDLE,
97	TGT_RSP_XRAM_IDLE,
98	TGT_RSP_MULTI_ACK_IDLE,
99	TGT_RSP_CLEANUP_IDLE,
100	TGT_RSP_CONFIG,
101	TGT_RSP_TGT_CMD,
102	TGT_RSP_READ,
103	TGT_RSP_WRITE,
104	TGT_RSP_CLEANUP,
105	TGT_RSP_CAS,
106	TGT_RSP_XRAM,
107	TGT_RSP_MULTI_ACK
108	};
109
110	/* States of the DSPIN_TGT fsm */
111	enum cc_receive_fsm_state_e
112	{
113	CC_RECEIVE_IDLE,
114	CC_RECEIVE_CLEANUP,
115	CC_RECEIVE_CLEANUP_EOP,
116	CC_RECEIVE_MULTI_ACK
117	};
118
119	/* States of the CC_SEND fsm */
120	enum cc_send_fsm_state_e
121	{
122	CC_SEND_CONFIG_IDLE,
123	CC_SEND_WRITE_IDLE,
124	CC_SEND_XRAM_RSP_IDLE,
125	CC_SEND_CAS_IDLE,
126	CC_SEND_READ_IDLE,
127	CC_SEND_CONFIG_INVAL_HEADER,
128	CC_SEND_CONFIG_INVAL_NLINE,
129	CC_SEND_CONFIG_BRDCAST_HEADER,
130	CC_SEND_CONFIG_BRDCAST_NLINE,
131	CC_SEND_XRAM_RSP_INVAL_HEADER,
132	CC_SEND_XRAM_RSP_INVAL_NLINE,
133	CC_SEND_XRAM_RSP_BRDCAST_HEADER,
134	CC_SEND_XRAM_RSP_BRDCAST_NLINE,
135	CC_SEND_READ_BRDCAST_HEADER,
136	CC_SEND_READ_BRDCAST_NLINE,
137	CC_SEND_READ_MULTI_HEADER,
138	CC_SEND_READ_MULTI_NLINE,
139	CC_SEND_WRITE_BRDCAST_HEADER,
140	CC_SEND_WRITE_BRDCAST_NLINE,
141	CC_SEND_WRITE_INVAL_HEADER,
142	CC_SEND_WRITE_INVAL_NLINE,
143	CC_SEND_CAS_BRDCAST_HEADER,
144	CC_SEND_CAS_BRDCAST_NLINE,
145	CC_SEND_CAS_INVAL_HEADER,
146	CC_SEND_CAS_INVAL_NLINE
147	};
148
149	/* States of the MULTI_ACK fsm */
150	enum multi_ack_fsm_state_e
151	{
152	MULTI_ACK_IDLE,
153	MULTI_ACK_GET_DATA,
154	MULTI_ACK_IVT_LOCK,
155	MULTI_ACK_IVT_CLEAR,
156	MULTI_ACK_DIR_REQ,
157	MULTI_ACK_DIR_LOCK,
158	MULTI_ACK_DIR_UPDT,
159	MULTI_ACK_RSP,
160	MULTI_ACK_HEAP_REQ,
161	MULTI_ACK_HEAP_LOCK,
162	MULTI_ACK_HEAP_WRITE,
163	MULTI_ACK_IVT_CHANGE
164	};
165
166	/* States of the CONFIG fsm */
167	enum config_fsm_state_e
168	{
169	CONFIG_IDLE,
170	CONFIG_LOOP,
171	CONFIG_WAIT,
172	CONFIG_RSP,
173	CONFIG_DIR_REQ,
174	CONFIG_DIR_ACCESS,
175	CONFIG_IVT_LOCK,
176	CONFIG_BC_SEND,
177	CONFIG_INVAL_SEND,
178	CONFIG_HEAP_REQ,
179	CONFIG_HEAP_SCAN,
180	CONFIG_HEAP_LAST,
181	CONFIG_TRT_LOCK,
182	CONFIG_TRT_SET,
183	CONFIG_PUT_REQ
184	};
185
186	/* States of the READ fsm */
187	enum read_fsm_state_e
188	{
189	READ_IDLE,
190	READ_DIR_REQ,
191	READ_DIR_LOCK,
192	READ_IVT_INVAL_LOCK,
193	READ_INVAL_HEAP_REQ,
194	READ_INVAL_HEAP_ERASE,
195	READ_INVAL_HEAP_LAST,
196	READ_IVT_UPDT_LOCK,
197	READ_WAIT,
198	READ_DIR_HIT,
199	READ_HEAP_REQ,
200	READ_HEAP_LOCK,
201	READ_HEAP_WRITE,
202	READ_HEAP_ERASE,
203	READ_HEAP_LAST,
204	READ_RSP,
205	READ_TRT_LOCK,
206	READ_TRT_SET,
207	READ_TRT_REQ
208	};
209
210	/* States of the WRITE fsm */
211	enum write_fsm_state_e
212	{
213	WRITE_IDLE,
214	WRITE_NEXT,
215	WRITE_DIR_REQ,
216	WRITE_DIR_LOCK,
217	WRITE_DIR_HIT,
218	WRITE_HEAP_REQ,
219	WRITE_HEAP_ERASE,
220	WRITE_HEAP_LAST,
221	WRITE_RSP,
222	WRITE_MISS_TRT_LOCK,
223	WRITE_WAIT,
224	WRITE_MISS_TRT_SET,
225	WRITE_MISS_TRT_DATA,
226	WRITE_MISS_XRAM_REQ,
227	WRITE_INVAL_IVT_LOCK,
228	WRITE_INVAL_CC_SEND
229	};
230
231	/* States of the IXR_RSP fsm */
232	enum ixr_rsp_fsm_state_e
233	{
234	IXR_RSP_IDLE,
235	IXR_RSP_ACK,
236	IXR_RSP_TRT_ERASE,
237	IXR_RSP_TRT_READ
238	};
239
240	/* States of the XRAM_RSP fsm */
241	enum xram_rsp_fsm_state_e
242	{
243	XRAM_RSP_IDLE,
244	XRAM_RSP_TRT_COPY,
245	XRAM_RSP_TRT_DIRTY,
246	XRAM_RSP_DIR_LOCK,
247	XRAM_RSP_DIR_UPDT,
248	XRAM_RSP_DIR_RSP,
249	XRAM_RSP_IVT_LOCK,
250	XRAM_RSP_INVAL_WAIT,
251	XRAM_RSP_INVAL,
252	XRAM_RSP_WRITE_DIRTY,
253	XRAM_RSP_HEAP_REQ,
254	XRAM_RSP_HEAP_ERASE,
255	XRAM_RSP_HEAP_LAST,
256	XRAM_RSP_ERROR_ERASE,
257	XRAM_RSP_ERROR_RSP
258	};
259
260	/* States of the IXR_CMD fsm */
261	enum ixr_cmd_fsm_state_e
262	{
263	IXR_CMD_READ_IDLE,
264	IXR_CMD_WRITE_IDLE,
265	IXR_CMD_CAS_IDLE,
266	IXR_CMD_XRAM_IDLE,
267	IXR_CMD_CLEANUP_IDLE,
268	IXR_CMD_CONFIG_IDLE,
269	IXR_CMD_READ_TRT,
270	IXR_CMD_WRITE_TRT,
271	IXR_CMD_CAS_TRT,
272	IXR_CMD_XRAM_TRT,
273	IXR_CMD_CLEANUP_TRT,
274	IXR_CMD_CONFIG_TRT,
275	IXR_CMD_READ_SEND,
276	IXR_CMD_WRITE_SEND,
277	IXR_CMD_CAS_SEND,
278	IXR_CMD_XRAM_SEND,
279	IXR_CMD_CLEANUP_DATA_SEND,
280	IXR_CMD_CONFIG_SEND
281	};
282
283	/* States of the CAS fsm */
284	enum cas_fsm_state_e
285	{
286	CAS_IDLE,
287	CAS_DIR_REQ,
288	CAS_DIR_LOCK,
289	CAS_DIR_HIT_READ,
290	CAS_DIR_HIT_COMPARE,
291	CAS_DIR_HIT_WRITE,
292	CAS_MULTI_INVAL_IVT_LOCK,
293	CAS_WAIT,
294	CAS_MULTI_INVAL_HEAP_LOCK,
295	CAS_MULTI_INVAL_REQ,
296	CAS_HEAP_NEXT,
297	CAS_HEAP_LAST,
298	CAS_BC_TRT_LOCK,
299	CAS_BC_IVT_LOCK,
300	CAS_BC_DIR_INVAL,
301	CAS_BC_CC_SEND,
302	CAS_BC_XRAM_REQ,
303	CAS_RSP_FAIL,
304	CAS_RSP_SUCCESS,
305	CAS_MISS_TRT_LOCK,
306	CAS_MISS_TRT_SET,
307	CAS_MISS_XRAM_REQ
308	};
309
310	/* States of the CLEANUP fsm */
311	enum cleanup_fsm_state_e
312	{
313	CLEANUP_IDLE,
314	CLEANUP_GET_NLINE,
315	CLEANUP_GET_DATA,
316	CLEANUP_DIR_REQ,
317	CLEANUP_DIR_LOCK,
318	CLEANUP_DIR_WRITE,
319	CLEANUP_LOCKED_IVT_LOCK,
320	CLEANUP_LOCKED_IVT_DECREMENT,
321	CLEANUP_LOCKED_IVT_CLEAR,
322	CLEANUP_LOCKED_RSP,
323	CLEANUP_HEAP_REQ,
324	CLEANUP_HEAP_LOCK,
325	CLEANUP_HEAP_SEARCH,
326	CLEANUP_HEAP_CLEAN,
327	CLEANUP_HEAP_FREE,
328	CLEANUP_MISS_IVT_LOCK,
329	CLEANUP_MISS_IVT_DECREMENT,
330	CLEANUP_MISS_IVT_CLEAR,
331	CLEANUP_MISS_RSP,
332	CLEANUP_MISS_IXR_REQ,
333	CLEANUP_WAIT,
334	CLEANUP_SEND_CLACK
335	};
336
337	/* States of the ALLOC_DIR fsm */
338	enum alloc_dir_fsm_state_e
339	{
340	ALLOC_DIR_RESET,
341	ALLOC_DIR_READ,
342	ALLOC_DIR_WRITE,
343	ALLOC_DIR_CAS,
344	ALLOC_DIR_CLEANUP,
345	ALLOC_DIR_XRAM_RSP,
346	ALLOC_DIR_MULTI_ACK,
347	ALLOC_DIR_CONFIG
348	};
349
350	/* States of the ALLOC_TRT fsm */
351	enum alloc_trt_fsm_state_e
352	{
353	ALLOC_TRT_READ,
354	ALLOC_TRT_WRITE,
355	ALLOC_TRT_CAS,
356	ALLOC_TRT_XRAM_RSP,
357	ALLOC_TRT_IXR_RSP,
358	ALLOC_TRT_CLEANUP,
359	ALLOC_TRT_IXR_CMD,
360	ALLOC_TRT_CONFIG
361	};
362
363	// /* States of the ALLOC_UPT fsm */
364	// enum alloc_upt_fsm_state_e
365	// {
366	// ALLOC_UPT_WRITE,
367	// ALLOC_UPT_CAS,
368	// ALLOC_UPT_MULTI_ACK
369	// };
370	//
371	/* States of the ALLOC_IVT fsm */
372	enum alloc_ivt_fsm_state_e
373	{
374	ALLOC_IVT_WRITE,
375	ALLOC_IVT_READ,
376	ALLOC_IVT_XRAM_RSP,
377	ALLOC_IVT_CLEANUP,
378	ALLOC_IVT_CAS,
379	ALLOC_IVT_CONFIG,
380	ALLOC_IVT_MULTI_ACK
381	};
382
383	/* States of the ALLOC_HEAP fsm */
384	enum alloc_heap_fsm_state_e
385	{
386	ALLOC_HEAP_RESET,
387	ALLOC_HEAP_READ,
388	ALLOC_HEAP_WRITE,
389	ALLOC_HEAP_CAS,
390	ALLOC_HEAP_CLEANUP,
391	ALLOC_HEAP_MULTI_ACK,
392	ALLOC_HEAP_XRAM_RSP,
393	ALLOC_HEAP_CONFIG
394	};
395
396	/* transaction type, pktid field */
397	enum transaction_type_e
398	{
399	// b3 unused
400	// b2 READ / NOT READ
401	// Si READ
402	// b1 DATA / INS
403	// b0 UNC / MISS
404	// Si NOT READ
405	// b1 accÃšs table llsc type SW / other
406	// b2 WRITE/CAS/LL/SC
407	TYPE_DATA_UNC = 0x0,
408	TYPE_READ_DATA_MISS = 0x1,
409	TYPE_READ_INS_UNC = 0x2,
410	TYPE_READ_INS_MISS = 0x3,
411	TYPE_WRITE = 0x4,
412	TYPE_CAS = 0x5,
413	TYPE_LL = 0x6,
414	TYPE_SC = 0x7
415	};
416
417	/* SC return values */
418	enum sc_status_type_e
419	{
420	SC_SUCCESS = 0x00000000,
421	SC_FAIL = 0x00000001
422	};
423
424	// debug variables
425	bool m_debug;
426	size_t m_debug_previous_valid;
427	size_t m_debug_previous_count;
428	bool m_debug_previous_dirty;
429	data_t * m_debug_previous_data;
430	data_t * m_debug_data;
431
432	// instrumentation counters
433	uint32_t m_cpt_cycles; // Counter of cycles
434
435	// Counters accessible in software (not yet but eventually)
436	uint32_t m_cpt_reset_count; // Last cycle at which counters have been reset
437	uint32_t m_cpt_read_local; // Number of local READ transactions
438	uint32_t m_cpt_read_remote; // number of remote READ transactions
439	uint32_t m_cpt_read_cost; // Number of (flits * distance) for READs
440
441	uint32_t m_cpt_write_local; // Number of local WRITE transactions
442	uint32_t m_cpt_write_remote; // number of remote WRITE transactions
443	uint32_t m_cpt_write_flits_local; // number of flits for local WRITEs
444	uint32_t m_cpt_write_flits_remote; // number of flits for remote WRITEs
445	uint32_t m_cpt_write_cost; // Number of (flits * distance) for WRITEs
446
447	uint32_t m_cpt_ll_local; // Number of local LL transactions
448	uint32_t m_cpt_ll_remote; // number of remote LL transactions
449	uint32_t m_cpt_ll_cost; // Number of (flits * distance) for LLs
450
451	uint32_t m_cpt_sc_local; // Number of local SC transactions
452	uint32_t m_cpt_sc_remote; // number of remote SC transactions
453	uint32_t m_cpt_sc_cost; // Number of (flits * distance) for SCs
454
455	uint32_t m_cpt_cas_local; // Number of local SC transactions
456	uint32_t m_cpt_cas_remote; // number of remote SC transactions
457	uint32_t m_cpt_cas_cost; // Number of (flits * distance) for SCs
458
459	uint32_t m_cpt_update; // Number of requests causing an UPDATE
460	uint32_t m_cpt_update_local; // Number of local UPDATE transactions
461	uint32_t m_cpt_update_remote; // Number of remote UPDATE transactions
462	uint32_t m_cpt_update_cost; // Number of (flits * distance) for UPDT
463
464	uint32_t m_cpt_minval; // Number of requests causing M_INV
465	uint32_t m_cpt_minval_local; // Number of local M_INV transactions
466	uint32_t m_cpt_minval_remote; // Number of remote M_INV transactions
467	uint32_t m_cpt_minval_cost; // Number of (flits * distance) for M_INV
468
469	uint32_t m_cpt_binval; // Number of BROADCAST INVAL
470
471	uint32_t m_cpt_cleanup_local; // Number of local CLEANUP transactions
472	uint32_t m_cpt_cleanup_remote; // Number of remote CLEANUP transactions
473	uint32_t m_cpt_cleanup_cost; // Number of (flits * distance) for CLEANUPs
474
475	// Counters not accessible by software
476	uint32_t m_cpt_read_miss; // Number of MISS READ
477	uint32_t m_cpt_write_miss; // Number of MISS WRITE
478	uint32_t m_cpt_write_dirty; // Cumulated length for WRITE transactions
479	uint32_t m_cpt_write_broadcast;// Number of BROADCAST INVAL because write
480
481	uint32_t m_cpt_trt_rb; // Read blocked by a hit in trt
482	uint32_t m_cpt_trt_full; // Transaction blocked due to a full trt
483
484	uint32_t m_cpt_read_fsm_dir_lock; // wait DIR LOCK
485	uint32_t m_cpt_read_fsm_n_dir_lock; // NB DIR LOCK
486	uint32_t m_cpt_write_fsm_dir_lock; // wait DIR LOCK
487	uint32_t m_cpt_write_fsm_n_dir_lock; // NB DIR LOCK
488	uint32_t m_cpt_xram_rsp_fsm_dir_lock; // wait DIR LOCK
489	uint32_t m_cpt_xram_rsp_fsm_n_dir_lock; // NB DIR LOCK
490	uint32_t m_cpt_cas_fsm_dir_lock; // wait DIR LOCK
491	uint32_t m_cpt_cas_fsm_n_dir_lock; // NB DIR LOCK
492	uint32_t m_cpt_cleanup_fsm_dir_lock; // wait DIR LOCK
493	uint32_t m_cpt_cleanup_fsm_n_dir_lock; // NB DIR LOCK
494
495	uint32_t m_cpt_dir_unused; // NB cycles DIR LOCK unused
496	uint32_t m_cpt_read_fsm_dir_used; // NB cycles DIR LOCK used
497	uint32_t m_cpt_write_fsm_dir_used; // NB cycles DIR LOCK used
498	uint32_t m_cpt_cas_fsm_dir_used; // NB cycles DIR LOCK used
499	uint32_t m_cpt_xram_rsp_fsm_dir_used; // NB cycles DIR LOCK used
500	uint32_t m_cpt_cleanup_fsm_dir_used; // NB cycles DIR LOCK used
501
502	uint32_t m_cpt_read_fsm_trt_lock; // wait TRT LOCK
503	uint32_t m_cpt_write_fsm_trt_lock; // wait TRT LOCK
504	uint32_t m_cpt_cas_fsm_trt_lock; // wait TRT LOCK
505	uint32_t m_cpt_xram_rsp_fsm_trt_lock; // wait TRT LOCK
506	uint32_t m_cpt_ixr_fsm_trt_lock; // wait TRT LOCK
507
508	uint32_t m_cpt_read_fsm_n_trt_lock; // NB TRT LOCK
509	uint32_t m_cpt_write_fsm_n_trt_lock; // NB TRT LOCK
510	uint32_t m_cpt_cas_fsm_n_trt_lock; // NB TRT LOCK
511	uint32_t m_cpt_xram_rsp_fsm_n_trt_lock; // NB TRT LOCK
512	uint32_t m_cpt_ixr_fsm_n_trt_lock; // NB TRT LOCK
513
514	uint32_t m_cpt_read_fsm_trt_used; // NB cycles TRT LOCK used
515	uint32_t m_cpt_write_fsm_trt_used; // NB cycles TRT LOCK used
516	uint32_t m_cpt_cas_fsm_trt_used; // NB cycles TRT LOCK used
517	uint32_t m_cpt_xram_rsp_fsm_trt_used; // NB cycles TRT LOCK used
518	uint32_t m_cpt_ixr_fsm_trt_used; // NB cycles TRT LOCK used
519
520	uint32_t m_cpt_trt_unused; // NB cycles TRT LOCK unused
521
522	uint32_t m_cpt_write_fsm_upt_lock; // wait UPT LOCK
523	uint32_t m_cpt_xram_rsp_fsm_upt_lock; // wait UPT LOCK
524	uint32_t m_cpt_multi_ack_fsm_upt_lock; // wait UPT LOCK
525	uint32_t m_cpt_cleanup_fsm_ivt_lock; // wait UPT LOCK
526	uint32_t m_cpt_cas_fsm_upt_lock; // wait UPT LOCK
527
528	uint32_t m_cpt_write_fsm_n_upt_lock; // NB UPT LOCK
529	uint32_t m_cpt_xram_rsp_fsm_n_upt_lock; // NB UPT LOCK
530	uint32_t m_cpt_multi_ack_fsm_n_upt_lock; // NB UPT LOCK
531	uint32_t m_cpt_cleanup_fsm_n_upt_lock; // NB UPT LOCK
532	uint32_t m_cpt_cas_fsm_n_upt_lock; // NB UPT LOCK
533
534	uint32_t m_cpt_write_fsm_upt_used; // NB cycles UPT LOCK used
535	uint32_t m_cpt_xram_rsp_fsm_upt_used; // NB cycles UPT LOCK used
536	uint32_t m_cpt_multi_ack_fsm_upt_used; // NB cycles UPT LOCK used
537	uint32_t m_cpt_cleanup_fsm_ivt_used; // NB cycles UPT LOCK used
538	uint32_t m_cpt_cas_fsm_upt_used; // NB cycles UPT LOCK used
539
540	uint32_t m_cpt_ivt_unused; // NB cycles UPT LOCK unused
541	uint32_t m_cpt_upt_unused; // NB cycles UPT LOCK unused
542
543	uint32_t m_cpt_read_fsm_heap_lock; // wait HEAP LOCK
544	uint32_t m_cpt_write_fsm_heap_lock; // wait HEAP LOCK
545	uint32_t m_cpt_cas_fsm_heap_lock; // wait HEAP LOCK
546	uint32_t m_cpt_cleanup_fsm_heap_lock; // wait HEAP LOCK
547	uint32_t m_cpt_xram_rsp_fsm_heap_lock; // wait HEAP LOCK
548
549	uint32_t m_cpt_read_fsm_n_heap_lock; // NB HEAP LOCK
550	uint32_t m_cpt_write_fsm_n_heap_lock; // NB HEAP LOCK
551	uint32_t m_cpt_cas_fsm_n_heap_lock; // NB HEAP LOCK
552	uint32_t m_cpt_cleanup_fsm_n_heap_lock; // NB HEAP LOCK
553	uint32_t m_cpt_xram_rsp_fsm_n_heap_lock; // NB HEAP LOCK
554
555	uint32_t m_cpt_read_fsm_heap_used; // NB cycles HEAP LOCK used
556	uint32_t m_cpt_write_fsm_heap_used; // NB cycles HEAP LOCK used
557	uint32_t m_cpt_cas_fsm_heap_used; // NB cycles HEAP LOCK used
558	uint32_t m_cpt_cleanup_fsm_heap_used; // NB cycles HEAP LOCK used
559	uint32_t m_cpt_xram_rsp_fsm_heap_used; // NB cycles HEAP LOCK used
560
561	uint32_t m_cpt_heap_unused; // NB cycles HEAP LOCK unused
562
563	//RWT
564	uint32_t m_cpt_cleanup_data;
565	uint32_t m_cpt_ncc_to_cc_read; // NB change from NCC to CC caused by a READ
566	uint32_t m_cpt_ncc_to_cc_write; // NB change from NCC to CC caused by a WRITE
567	uint32_t m_cpt_ncc_to_cc; // NB change from NCC to CC
568
569	uint32_t m_cpt_read_data_unc;
570	uint32_t m_cpt_read_data_miss_CC;
571	uint32_t m_cpt_read_ins_unc;
572	uint32_t m_cpt_read_ins_miss;
573	uint32_t m_cpt_read_ll_CC;
574	uint32_t m_cpt_read_data_miss_NCC;
575	uint32_t m_cpt_read_ll_NCC;
576	uint32_t m_cpt_read_WTF;
577
578	uint32_t m_cpt_update_flits; // Number of flits for UPDATEs
579	uint32_t m_cpt_inval_cost; // Number of (flits * distance) for INVALs
580
581	uint32_t m_cpt_get;
582	uint32_t m_cpt_put;
583
584	size_t m_prev_count;
585
586	protected:
587
588	SC_HAS_PROCESS(VciMemCache);
589
590	public:
591	sc_in<bool> p_clk;
592	sc_in<bool> p_resetn;
593	sc_in<bool> p_irq;
594	soclib::caba::VciTarget<vci_param_int> p_vci_tgt;
595	soclib::caba::VciInitiator<vci_param_ext> p_vci_ixr;
596	soclib::caba::DspinInput<dspin_in_width> p_dspin_p2m;
597	soclib::caba::DspinOutput<dspin_out_width> p_dspin_m2p;
598	soclib::caba::DspinOutput<dspin_out_width> p_dspin_clack;
599
600	#if MONITOR_MEMCACHE_FSM == 1
601	sc_out<int> p_read_fsm;
602	sc_out<int> p_write_fsm;
603	sc_out<int> p_xram_rsp_fsm;
604	sc_out<int> p_cas_fsm;
605	sc_out<int> p_cleanup_fsm;
606	sc_out<int> p_config_fsm;
607	sc_out<int> p_alloc_heap_fsm;
608	sc_out<int> p_alloc_dir_fsm;
609	sc_out<int> p_alloc_trt_fsm;
610	sc_out<int> p_alloc_upt_fsm;
611	sc_out<int> p_alloc_ivt_fsm;
612	sc_out<int> p_tgt_cmd_fsm;
613	sc_out<int> p_tgt_rsp_fsm;
614	sc_out<int> p_ixr_cmd_fsm;
615	sc_out<int> p_ixr_rsp_fsm;
616	sc_out<int> p_cc_send_fsm;
617	sc_out<int> p_cc_receive_fsm;
618	sc_out<int> p_multi_ack_fsm;
619	#endif
620
621	VciMemCache(
622	sc_module_name name, // Instance Name
623	const soclib::common::MappingTable &mtp, // Mapping table INT network
624	const soclib::common::MappingTable &mtx, // Mapping table RAM network
625	const soclib::common::IntTab &srcid_x, // global index RAM network
626	const soclib::common::IntTab &tgtid_d, // global index INT network
627	const size_t cc_global_id, // global index CC network
628	const size_t x_width, // X width in platform
629	const size_t y_width, // Y width in platform
630	const size_t nways, // Number of ways per set
631	const size_t nsets, // Number of sets
632	const size_t nwords, // Number of words per line
633	const size_t max_copies, // max number of copies
634	const size_t heap_size=HEAP_ENTRIES,
635	const size_t trt_lines=TRT_ENTRIES,
636	const size_t upt_lines=UPT_ENTRIES,
637	const size_t ivt_lines=IVT_ENTRIES,
638	const size_t debug_start_cycle=0,
639	const bool debug_ok=false );
640
641	~VciMemCache();
642
643	void reset_counters();
644	void print_stats(bool activity_counters, bool stats);
645	void print_trace( size_t detailled = 0 );
646	void cache_monitor(addr_t addr);
647	void start_monitor(addr_t addr, addr_t length);
648	void stop_monitor();
649
650	private:
651
652	void transition();
653	void genMoore();
654	void check_monitor(addr_t addr, data_t data, bool read);
655	uint32_t req_distance(uint32_t req_srcid);
656	bool is_local_req(uint32_t req_srcid);
657	int read_instrumentation(uint32_t regr, uint32_t & rdata);
658
659	// Component attributes
660	std::list<soclib::common::Segment> m_seglist; // segments allocated
661	size_t m_nseg; // number of segments
662	soclib::common::Segment **m_seg; // array of segments pointers
663	size_t m_seg_config; // config segment index
664	const size_t m_srcid_x; // global index on RAM network
665	const size_t m_initiators; // Number of initiators
666	const size_t m_heap_size; // Size of the heap
667	const size_t m_ways; // Number of ways in a set
668	const size_t m_sets; // Number of cache sets
669	const size_t m_words; // Number of words in a line
670	const size_t m_cc_global_id; // global_index on cc network
671	const size_t m_xwidth; // number of x bits in platform
672	const size_t m_ywidth; // number of y bits in platform
673	size_t m_debug_start_cycle;
674	bool m_debug_ok;
675	uint32_t m_trt_lines;
676	TransactionTab m_trt; // xram transaction table
677	uint32_t m_upt_lines;
678	UpdateTab m_upt; // pending update
679	UpdateTab m_ivt; // pending invalidate
680	CacheDirectory m_cache_directory; // data cache directory
681	CacheData m_cache_data; // data array[set][way][word]
682	HeapDirectory m_heap; // heap for copies
683	size_t m_max_copies; // max number of copies in heap
684	GenericLLSCGlobalTable
685	< 32 , // number of slots
686	4096, // number of processors in the system
687	8000, // registration life (# of LL operations)
688	addr_t > m_llsc_table; // ll/sc registration table
689
690	// adress masks
691	const soclib::common::AddressMaskingTable<addr_t> m_x;
692	const soclib::common::AddressMaskingTable<addr_t> m_y;
693	const soclib::common::AddressMaskingTable<addr_t> m_z;
694	const soclib::common::AddressMaskingTable<addr_t> m_nline;
695
696	// broadcast address
697	uint32_t m_broadcast_boundaries;
698
699	// configuration interface constants
700	const uint32_t m_config_addr_mask;
701	const uint32_t m_config_regr_width;
702	const uint32_t m_config_func_width;
703	const uint32_t m_config_regr_idx_mask;
704	const uint32_t m_config_func_idx_mask;
705
706	// Fifo between TGT_CMD fsm and READ fsm
707	GenericFifo<addr_t> m_cmd_read_addr_fifo;
708	GenericFifo<size_t> m_cmd_read_length_fifo;
709	GenericFifo<size_t> m_cmd_read_srcid_fifo;
710	GenericFifo<size_t> m_cmd_read_trdid_fifo;
711	GenericFifo<size_t> m_cmd_read_pktid_fifo;
712
713	// Fifo between TGT_CMD fsm and WRITE fsm
714	GenericFifo<addr_t> m_cmd_write_addr_fifo;
715	GenericFifo<bool> m_cmd_write_eop_fifo;
716	GenericFifo<size_t> m_cmd_write_srcid_fifo;
717	GenericFifo<size_t> m_cmd_write_trdid_fifo;
718	GenericFifo<size_t> m_cmd_write_pktid_fifo;
719	GenericFifo<data_t> m_cmd_write_data_fifo;
720	GenericFifo<be_t> m_cmd_write_be_fifo;
721
722	// Fifo between TGT_CMD fsm and CAS fsm
723	GenericFifo<addr_t> m_cmd_cas_addr_fifo;
724	GenericFifo<bool> m_cmd_cas_eop_fifo;
725	GenericFifo<size_t> m_cmd_cas_srcid_fifo;
726	GenericFifo<size_t> m_cmd_cas_trdid_fifo;
727	GenericFifo<size_t> m_cmd_cas_pktid_fifo;
728	GenericFifo<data_t> m_cmd_cas_wdata_fifo;
729
730	// Fifo between CC_RECEIVE fsm and CLEANUP fsm
731	GenericFifo<uint64_t> m_cc_receive_to_cleanup_fifo;
732
733	// Fifo between CC_RECEIVE fsm and MULTI_ACK fsm
734	GenericFifo<uint64_t> m_cc_receive_to_multi_ack_fifo;
735
736	// Buffer between TGT_CMD fsm and TGT_RSP fsm
737	// (segmentation violation response request)
738	sc_signal<bool> r_tgt_cmd_to_tgt_rsp_req;
739
740	sc_signal<uint32_t> r_tgt_cmd_to_tgt_rsp_rdata;
741	sc_signal<size_t> r_tgt_cmd_to_tgt_rsp_error;
742	sc_signal<size_t> r_tgt_cmd_to_tgt_rsp_srcid;
743	sc_signal<size_t> r_tgt_cmd_to_tgt_rsp_trdid;
744	sc_signal<size_t> r_tgt_cmd_to_tgt_rsp_pktid;
745
746	sc_signal<addr_t> r_tgt_cmd_config_addr;
747	sc_signal<size_t> r_tgt_cmd_config_cmd;
748
749	//////////////////////////////////////////////////
750	// Registers controlled by the TGT_CMD fsm
751	//////////////////////////////////////////////////
752
753	sc_signal<int> r_tgt_cmd_fsm;
754
755	///////////////////////////////////////////////////////
756	// Registers controlled by the CONFIG fsm
757	///////////////////////////////////////////////////////
758
759	sc_signal<int> r_config_fsm; // FSM state
760	sc_signal<bool> r_config_lock; // lock protecting exclusive access
761	sc_signal<int> r_config_cmd; // config request type
762	sc_signal<addr_t> r_config_address; // target buffer physical address
763	sc_signal<size_t> r_config_srcid; // config request srcid
764	sc_signal<size_t> r_config_trdid; // config request trdid
765	sc_signal<size_t> r_config_pktid; // config request pktid
766	sc_signal<size_t> r_config_cmd_lines; // number of lines to be handled
767	sc_signal<size_t> r_config_rsp_lines; // number of lines not completed
768	sc_signal<size_t> r_config_dir_way; // DIR: selected way
769	sc_signal<bool> r_config_dir_lock; // DIR: locked entry
770	sc_signal<size_t> r_config_dir_count; // DIR: number of copies
771	sc_signal<bool> r_config_dir_is_cnt; // DIR: counter mode (broadcast)
772	sc_signal<size_t> r_config_dir_copy_srcid; // DIR: first copy SRCID
773	sc_signal<bool> r_config_dir_copy_inst; // DIR: first copy L1 type
774	sc_signal<size_t> r_config_dir_ptr; // DIR: index of next copy in HEAP
775	sc_signal<size_t> r_config_dir_state; // DIR: dir state
776	sc_signal<size_t> r_config_heap_next; // current pointer to scan HEAP
777	sc_signal<size_t> r_config_trt_index; // selected entry in TRT
778	sc_signal<size_t> r_config_ivt_index; // selected entry in IVT
779
780	// Buffer between CONFIG fsm and IXR_CMD fsm
781	sc_signal<bool> r_config_to_ixr_cmd_req; // valid request
782	sc_signal<size_t> r_config_to_ixr_cmd_index; // TRT index
783
784	// Buffer between CONFIG fsm and TGT_RSP fsm (send a done response to L1 cache)
785	sc_signal<bool> r_config_to_tgt_rsp_req; // valid request
786	sc_signal<bool> r_config_to_tgt_rsp_error; // error response
787	sc_signal<size_t> r_config_to_tgt_rsp_srcid; // Transaction srcid
788	sc_signal<size_t> r_config_to_tgt_rsp_trdid; // Transaction trdid
789	sc_signal<size_t> r_config_to_tgt_rsp_pktid; // Transaction pktid
790
791	// Buffer between CONFIG fsm and CC_SEND fsm (multi-inval / broadcast-inval)
792	sc_signal<bool> r_config_to_cc_send_multi_req; // multi-inval request
793	sc_signal<bool> r_config_to_cc_send_brdcast_req; // broadcast-inval request
794	sc_signal<addr_t> r_config_to_cc_send_nline; // line index
795	sc_signal<size_t> r_config_to_cc_send_trdid; // UPT index
796	GenericFifo<bool> m_config_to_cc_send_inst_fifo; // fifo for the L1 type
797	GenericFifo<size_t> m_config_to_cc_send_srcid_fifo; // fifo for owners srcid
798
799	///////////////////////////////////////////////////////
800	// Registers controlled by the READ fsm
801	///////////////////////////////////////////////////////
802
803	sc_signal<int> r_read_fsm; // FSM state
804	sc_signal<size_t> r_read_copy; // Srcid of the first copy
805	sc_signal<size_t> r_read_copy_cache; // Srcid of the first copy
806	sc_signal<bool> r_read_copy_inst; // Type of the first copy
807	sc_signal<tag_t> r_read_tag; // cache line tag (in directory)
808	sc_signal<bool> r_read_is_cnt; // is_cnt bit (in directory)
809	sc_signal<bool> r_read_lock; // lock bit (in directory)
810	sc_signal<bool> r_read_dirty; // dirty bit (in directory)
811	sc_signal<size_t> r_read_count; // number of copies
812	sc_signal<size_t> r_read_ptr; // pointer to the heap
813	sc_signal<data_t> * r_read_data; // data (one cache line)
814	sc_signal<size_t> r_read_way; // associative way (in cache)
815	sc_signal<size_t> r_read_trt_index; // Transaction Table index
816	sc_signal<size_t> r_read_next_ptr; // Next entry to point to
817	sc_signal<bool> r_read_last_free; // Last free entry
818	sc_signal<addr_t> r_read_ll_key; // LL key from llsc_global_table
819
820
821
822	sc_signal<bool> r_read_ll_done;
823	sc_signal<bool> r_read_need_block;
824	sc_signal<size_t> r_read_state;
825	// Buffer between READ fsm and IXR_CMD fsm
826	sc_signal<bool> r_read_to_ixr_cmd_req; // valid request
827	sc_signal<size_t> r_read_to_ixr_cmd_index; // TRT index
828
829	// Buffer between READ fsm and TGT_RSP fsm (send a hit read response to L1 cache)
830	sc_signal<bool> r_read_to_tgt_rsp_req; // valid request
831	sc_signal<size_t> r_read_to_tgt_rsp_srcid; // Transaction srcid
832	sc_signal<size_t> r_read_to_tgt_rsp_trdid; // Transaction trdid
833	sc_signal<size_t> r_read_to_tgt_rsp_pktid; // Transaction pktid
834	sc_signal<data_t> * r_read_to_tgt_rsp_data; // data (one cache line)
835	sc_signal<size_t> r_read_to_tgt_rsp_word; // first word of the response
836	sc_signal<size_t> r_read_to_tgt_rsp_length; // length of the response
837	sc_signal<addr_t> r_read_to_tgt_rsp_ll_key; // LL key from llsc_global_table
838
839	//RWT: Buffer between READ fsm and CC_SEND fsm (send inval)
840	sc_signal<bool> r_read_to_cc_send_req;
841	sc_signal<size_t> r_read_to_cc_send_dest;
842	sc_signal<addr_t> r_read_to_cc_send_nline;
843	sc_signal<bool> r_read_to_cc_send_inst;
844	sc_signal<size_t> r_read_to_cc_send_srcid;
845	sc_signal<size_t> r_read_to_cc_send_ivt_index;
846	sc_signal<bool> r_read_to_cc_send_multi_req; // multi inval
847	sc_signal<bool> r_read_to_cc_send_brdcast_req; // bd inval
848	sc_signal<bool> r_read_to_cc_send_type; //cc inval or cc updt
849	sc_signal<bool> r_read_to_cc_send_is_shared; //line is or not shared
850
851	//RWT: Buffer between READ fsm and CLEANUP fsm (wait for the data coming from L1 cache)
852	sc_signal<bool> r_read_to_cleanup_req; // valid request
853	sc_signal<addr_t> r_read_to_cleanup_nline; // cache line index
854	sc_signal<size_t> r_read_to_cleanup_srcid;
855	sc_signal<size_t> r_read_to_cleanup_length;
856	sc_signal<size_t> r_read_to_cleanup_first_word;
857	sc_signal<bool> r_read_to_cleanup_cached_read;
858	sc_signal<bool> r_read_to_cleanup_is_ll;
859	sc_signal<addr_t> r_read_to_cleanup_addr;
860	sc_signal<addr_t> r_read_to_cleanup_ll_key;
861
862	sc_signal<bool> r_read_to_multi_ack_req; // valid request
863	sc_signal<addr_t> r_read_to_multi_ack_nline; // cache line index
864	sc_signal<size_t> r_read_to_multi_ack_first_word;
865	sc_signal<bool> r_read_to_multi_ack_length;
866	sc_signal<addr_t> r_read_to_multi_ack_ll_key;
867
868
869	GenericFifo<bool> m_read_to_cc_send_inst_fifo; // fifo for the L1 type
870	GenericFifo<size_t> m_read_to_cc_send_srcid_fifo; // fifo for owners srcid
871
872
873
874	sc_signal<bool> r_multi_ack_need_data; // cc_updt rsp with data
875	sc_signal<size_t> r_multi_ack_data_index;
876	sc_signal<size_t> r_multi_ack_ivt_index;
877	sc_signal<size_t> r_multi_ack_set;
878	sc_signal<size_t> r_multi_ack_way;
879	sc_signal<size_t> r_multi_ack_count;
880	sc_signal<bool> r_multi_ack_rsp;
881	sc_signal<bool> r_multi_ack_rsp_shared;
882
883	sc_signal<size_t> r_multi_ack_copy; // Srcid of the first copy
884	sc_signal<bool> r_multi_ack_copy_inst; // Type of the first copy
885	sc_signal<tag_t> r_multi_ack_tag; // cache line tag (in directory)
886	sc_signal<bool> r_multi_ack_lock; // lock bit (in directory)
887	sc_signal<bool> r_multi_ack_dirty; // dirty bit (in directory)
888	sc_signal<data_t> * r_multi_ack_data; // data (one cache line)
889	sc_signal<size_t> r_multi_ack_to_tgt_rsp_word;
890	sc_signal<size_t> r_multi_ack_to_tgt_rsp_length;
891	sc_signal<size_t> r_multi_ack_to_tgt_ll_key;
892
893	sc_signal<bool> r_multi_ack_last_free;
894	sc_signal<bool> r_multi_ack_miss_updt;
895	sc_signal<size_t> r_multi_ack_next_ptr;
896
897	sc_signal<bool> r_read_shared; // State of the cache slot after transaction
898
899
900	sc_signal<data_t> * r_debug_data; // data (one cache line)
901	///////////////////////////////////////////////////////////////
902	// Registers controlled by the WRITE fsm
903	///////////////////////////////////////////////////////////////
904
905	sc_signal<int> r_write_fsm; // FSM state
906	sc_signal<size_t> r_write_state;
907	sc_signal<addr_t> r_write_address; // first word address
908	sc_signal<size_t> r_write_word_index; // first word index in line
909	sc_signal<size_t> r_write_word_count; // number of words in line
910	sc_signal<size_t> r_write_srcid; // transaction srcid
911	sc_signal<size_t> r_write_trdid; // transaction trdid
912	sc_signal<size_t> r_write_pktid; // transaction pktid
913	sc_signal<data_t> * r_write_data; // data (one cache line)
914	sc_signal<be_t> * r_write_be; // one byte enable per word
915	sc_signal<bool> r_write_byte; // (BE != 0X0) and (BE != 0xF)
916	sc_signal<bool> r_write_is_cnt; // is_cnt bit (in directory)
917	sc_signal<bool> r_write_lock; // lock bit (in directory)
918	sc_signal<tag_t> r_write_tag; // cache line tag (in directory)
919	sc_signal<size_t> r_write_copy; // first owner of the line
920	sc_signal<size_t> r_write_copy_cache; // first owner of the line
921	sc_signal<bool> r_write_copy_inst; // is this owner a ICache ?
922	sc_signal<size_t> r_write_count; // number of copies
923	sc_signal<size_t> r_write_ptr; // pointer to the heap
924	sc_signal<size_t> r_write_next_ptr; // next pointer to the heap
925	sc_signal<bool> r_write_to_dec; // need to decrement update counter
926	sc_signal<size_t> r_write_way; // way of the line
927	sc_signal<size_t> r_write_trt_index; // index in Transaction Table
928	sc_signal<size_t> r_write_upt_index; // index in Update Table
929	sc_signal<bool> r_write_sc_fail; // sc command failed
930	sc_signal<data_t> r_write_sc_key; // sc command key
931	sc_signal<bool> r_write_bc_data_we; // Write enable for data buffer
932	sc_signal<bool> r_write_inval_trt_send;
933	sc_signal<bool> r_write_data_we;
934
935	// Buffer between WRITE fsm and TGT_RSP fsm (acknowledge a write command from L1)
936	sc_signal<bool> r_write_to_tgt_rsp_req; // valid request
937	sc_signal<size_t> r_write_to_tgt_rsp_srcid; // transaction srcid
938	sc_signal<size_t> r_write_to_tgt_rsp_trdid; // transaction trdid
939	sc_signal<size_t> r_write_to_tgt_rsp_pktid; // transaction pktid
940	sc_signal<bool> r_write_to_tgt_rsp_sc_fail; // sc command failed
941
942	// Buffer between WRITE fsm and IXR_CMD fsm
943	sc_signal<bool> r_write_to_ixr_cmd_req; // valid request
944	sc_signal<size_t> r_write_to_ixr_cmd_index; // TRT index
945
946	// Buffer between WRITE fsm and CC_SEND fsm (Update/Invalidate L1 caches)
947	sc_signal<bool> r_write_to_cc_send_multi_req; // valid multicast request
948	sc_signal<bool> r_write_to_cc_send_brdcast_req; // valid brdcast request
949	sc_signal<addr_t> r_write_to_cc_send_nline; // cache line index
950	sc_signal<size_t> r_write_to_cc_send_trdid; // index in Update Table
951	sc_signal<data_t> * r_write_to_cleanup_data; // data (one cache line)
952	sc_signal<be_t> * r_write_to_cleanup_be; // word enable
953	sc_signal<size_t> r_write_to_cc_send_count; // number of words in line
954	sc_signal<size_t> r_write_to_cc_send_index; // index of first word in line
955	GenericFifo<bool> m_write_to_cc_send_inst_fifo; // fifo for the L1 type
956	GenericFifo<size_t> m_write_to_cc_send_srcid_fifo; // fifo for srcids
957
958	// Buffer between WRITE fsm and MULTI_ACK fsm (Decrement UPT entry)
959	sc_signal<bool> r_write_to_multi_ack_req; // valid request
960	sc_signal<size_t> r_write_to_multi_ack_upt_index; // index in update table
961
962	// RWT: Buffer between WRITE fsm and CLEANUP fsm (change slot state)
963	sc_signal<bool> r_write_to_cleanup_req; // valid request
964	sc_signal<addr_t> r_write_to_cleanup_nline; // cache line index
965
966	// RWT
967	sc_signal<bool> r_write_coherent; // cache slot state after transaction
968
969	//Buffer between WRITE fsm and CC_SEND fsm (INVAL for RWT)
970	sc_signal<bool> r_write_to_cc_send_req;
971	sc_signal<size_t> r_write_to_cc_send_dest;
972
973
974	/////////////////////////////////////////////////////////
975	// Registers controlled by MULTI_ACK fsm
976	//////////////////////////////////////////////////////////
977
978	sc_signal<int> r_multi_ack_fsm; // FSM state
979	sc_signal<size_t> r_multi_ack_upt_index; // index in the Update Table
980	sc_signal<size_t> r_multi_ack_srcid; // pending write srcid
981	sc_signal<size_t> r_multi_ack_trdid; // pending write trdid
982	sc_signal<size_t> r_multi_ack_pktid; // pending write pktid
983	sc_signal<addr_t> r_multi_ack_nline; // pending write nline
984
985	// Buffer between MULTI_ACK fsm and TGT_RSP fsm (complete write/update transaction)
986	sc_signal<bool> r_multi_ack_to_tgt_rsp_req; // valid request
987	sc_signal<size_t> r_multi_ack_to_tgt_rsp_srcid; // Transaction srcid
988	sc_signal<size_t> r_multi_ack_to_tgt_rsp_trdid; // Transaction trdid
989	sc_signal<size_t> r_multi_ack_to_tgt_rsp_pktid; // Transaction pktid
990
991	///////////////////////////////////////////////////////
992	// Registers controlled by CLEANUP fsm
993	///////////////////////////////////////////////////////
994
995	sc_signal<int> r_cleanup_fsm; // FSM state
996	sc_signal<size_t> r_cleanup_srcid; // transaction srcid
997	sc_signal<bool> r_cleanup_inst; // Instruction or Data ?
998	sc_signal<size_t> r_cleanup_way_index; // L1 Cache Way index
999	sc_signal<addr_t> r_cleanup_nline; // cache line index
1000
1001
1002	sc_signal<copy_t> r_cleanup_copy; // first copy
1003	sc_signal<copy_t> r_cleanup_copy_cache; // first copy
1004	sc_signal<size_t> r_cleanup_copy_inst; // type of the first copy
1005	sc_signal<copy_t> r_cleanup_count; // number of copies
1006	sc_signal<size_t> r_cleanup_ptr; // pointer to the heap
1007	sc_signal<size_t> r_cleanup_prev_ptr; // previous pointer to the heap
1008	sc_signal<size_t> r_cleanup_prev_srcid; // srcid of previous heap entry
1009	sc_signal<size_t> r_cleanup_prev_cache_id; // srcid of previous heap entry
1010	sc_signal<bool> r_cleanup_prev_inst; // inst bit of previous heap entry
1011	sc_signal<size_t> r_cleanup_next_ptr; // next pointer to the heap
1012	sc_signal<tag_t> r_cleanup_tag; // cache line tag (in directory)
1013	sc_signal<bool> r_cleanup_is_cnt; // inst bit (in directory)
1014	sc_signal<bool> r_cleanup_lock; // lock bit (in directory)
1015	sc_signal<bool> r_cleanup_dirty; // dirty bit (in directory)
1016	sc_signal<size_t> r_cleanup_way; // associative way (in cache)
1017
1018	sc_signal<size_t> r_cleanup_locked_srcid; // srcid of write rsp
1019	sc_signal<size_t> r_cleanup_locked_trdid; // trdid of write rsp
1020	sc_signal<size_t> r_cleanup_locked_pktid; // pktid of write rsp
1021	sc_signal<size_t> r_cleanup_locked_index; // ivt index
1022	sc_signal<bool> r_cleanup_locked_is_updt;
1023	sc_signal<bool> r_cleanup_locked_is_changed;
1024	sc_signal<bool> r_cleanup_locked_is_read;
1025
1026	sc_signal<size_t> r_cleanup_miss_srcid; // srcid of write rsp
1027	sc_signal<size_t> r_cleanup_miss_trdid; // trdid of write rsp
1028	sc_signal<size_t> r_cleanup_miss_pktid; // pktid of write rsp
1029	sc_signal<size_t> r_cleanup_miss_index; // ivt index
1030	sc_signal<bool> r_cleanup_miss_need_rsp; // write response required
1031	sc_signal<bool> r_cleanup_miss_need_ack; // config acknowledge required
1032
1033
1034	// Buffer between CLEANUP fsm and TGT_RSP fsm (acknowledge a write command from L1)
1035	sc_signal<bool> r_cleanup_to_tgt_rsp_req; // valid request
1036	sc_signal<size_t> r_cleanup_to_tgt_rsp_srcid; // transaction srcid
1037	sc_signal<size_t> r_cleanup_to_tgt_rsp_trdid; // transaction trdid
1038	sc_signal<size_t> r_cleanup_to_tgt_rsp_pktid; // transaction pktid
1039	sc_signal<addr_t> r_cleanup_to_tgt_rsp_ll_key;
1040	sc_signal<addr_t> r_cleanup_to_tgt_rsp_nline;
1041
1042	sc_signal<bool> r_cleanup_to_tgt_rsp_type;
1043	sc_signal<data_t> * r_cleanup_to_tgt_rsp_data;
1044	sc_signal<size_t> r_cleanup_to_tgt_rsp_length;
1045	sc_signal<size_t> r_cleanup_to_tgt_rsp_first_word;
1046
1047	sc_signal<data_t> * r_multi_ack_to_tgt_rsp_data;
1048	///////////////////////////////////////////////////////
1049	// Registers controlled by CAS fsm
1050	///////////////////////////////////////////////////////
1051
1052	sc_signal<int> r_cas_fsm; // FSM state
1053	sc_signal<data_t> r_cas_wdata; // write data word
1054	sc_signal<data_t> * r_cas_rdata; // read data word
1055	sc_signal<uint32_t> r_cas_lfsr; // lfsr for random introducing
1056	sc_signal<size_t> r_cas_cpt; // size of command
1057	sc_signal<copy_t> r_cas_copy; // Srcid of the first copy
1058	sc_signal<copy_t> r_cas_copy_cache; // Srcid of the first copy
1059	sc_signal<bool> r_cas_copy_inst; // Type of the first copy
1060	sc_signal<size_t> r_cas_count; // number of copies
1061	sc_signal<size_t> r_cas_ptr; // pointer to the heap
1062	sc_signal<size_t> r_cas_next_ptr; // next pointer to the heap
1063	sc_signal<bool> r_cas_is_cnt; // is_cnt bit (in directory)
1064	sc_signal<bool> r_cas_dirty; // dirty bit (in directory)
1065	sc_signal<size_t> r_cas_way; // way in directory
1066	sc_signal<size_t> r_cas_set; // set in directory
1067	sc_signal<data_t> r_cas_tag; // cache line tag (in directory)
1068	sc_signal<size_t> r_cas_trt_index; // Transaction Table index
1069	sc_signal<size_t> r_cas_ivt_index; // Update Table index
1070	sc_signal<data_t> * r_cas_data; // cache line data
1071
1072	sc_signal<bool> r_cas_coherent;
1073	sc_signal<size_t> r_cas_state;
1074
1075	// Buffer between CAS fsm and IXR_CMD fsm (XRAM write)
1076	sc_signal<bool> r_cas_to_ixr_cmd_req; // valid request
1077	sc_signal<size_t> r_cas_to_ixr_cmd_index; // TRT index
1078
1079	// Buffer between CAS fsm and TGT_RSP fsm
1080	sc_signal<bool> r_cas_to_tgt_rsp_req; // valid request
1081	sc_signal<data_t> r_cas_to_tgt_rsp_data; // read data word
1082	sc_signal<size_t> r_cas_to_tgt_rsp_srcid; // Transaction srcid
1083	sc_signal<size_t> r_cas_to_tgt_rsp_trdid; // Transaction trdid
1084	sc_signal<size_t> r_cas_to_tgt_rsp_pktid; // Transaction pktid
1085
1086	// Buffer between CAS fsm and CC_SEND fsm (Update/Invalidate L1 caches)
1087	sc_signal<bool> r_cas_to_cc_send_multi_req; // valid request
1088	sc_signal<bool> r_cas_to_cc_send_brdcast_req; // brdcast request
1089	sc_signal<addr_t> r_cas_to_cc_send_nline; // cache line index
1090	sc_signal<size_t> r_cas_to_cc_send_trdid; // index in Update Table
1091	sc_signal<data_t> r_cas_to_cc_send_wdata; // data (one word)
1092	sc_signal<bool> r_cas_to_cc_send_is_long; // it is a 64 bits CAS
1093	sc_signal<data_t> r_cas_to_cc_send_wdata_high; // data high (one word)
1094	sc_signal<size_t> r_cas_to_cc_send_index; // index of the word in line
1095	GenericFifo<bool> m_cas_to_cc_send_inst_fifo; // fifo for the L1 type
1096	GenericFifo<size_t> m_cas_to_cc_send_srcid_fifo; // fifo for srcids
1097
1098	sc_signal<bool> r_cas_to_cleanup_req;
1099	sc_signal<addr_t> r_cas_to_cleanup_nline;
1100	////////////////////////////////////////////////////
1101	// Registers controlled by the IXR_RSP fsm
1102	////////////////////////////////////////////////////
1103
1104	sc_signal<int> r_ixr_rsp_fsm; // FSM state
1105	sc_signal<size_t> r_ixr_rsp_trt_index; // TRT entry index
1106	sc_signal<size_t> r_ixr_rsp_cpt; // word counter
1107
1108	// Buffer between IXR_RSP fsm and CONFIG fsm (response from the XRAM)
1109	sc_signal<bool> r_ixr_rsp_to_config_ack; // one single bit
1110
1111	// Buffer between IXR_RSP fsm and XRAM_RSP fsm (response from the XRAM)
1112	sc_signal<bool> * r_ixr_rsp_to_xram_rsp_rok; // one bit per TRT entry
1113
1114	////////////////////////////////////////////////////
1115	// Registers controlled by the XRAM_RSP fsm
1116	////////////////////////////////////////////////////
1117
1118	sc_signal<int> r_xram_rsp_fsm; // FSM state
1119	sc_signal<size_t> r_xram_rsp_trt_index; // TRT entry index
1120	TransactionTabEntry r_xram_rsp_trt_buf; // TRT entry local buffer
1121	sc_signal<bool> r_xram_rsp_victim_inval; // victim line invalidate
1122	sc_signal<bool> r_xram_rsp_victim_is_cnt; // victim line inst bit
1123	sc_signal<bool> r_xram_rsp_victim_dirty; // victim line dirty bit
1124	sc_signal<size_t> r_xram_rsp_victim_way; // victim line way
1125	sc_signal<size_t> r_xram_rsp_victim_set; // victim line set
1126	sc_signal<addr_t> r_xram_rsp_victim_nline; // victim line index
1127	sc_signal<copy_t> r_xram_rsp_victim_copy; // victim line first copy
1128	sc_signal<copy_t> r_xram_rsp_victim_copy_cache; // victim line first copy
1129	sc_signal<bool> r_xram_rsp_victim_copy_inst; // victim line type of first copy
1130	sc_signal<size_t> r_xram_rsp_victim_count; // victim line number of copies
1131	sc_signal<size_t> r_xram_rsp_victim_ptr; // victim line pointer to the heap
1132	sc_signal<data_t> * r_xram_rsp_victim_data; // victim line data
1133	sc_signal<size_t> r_xram_rsp_ivt_index; // IVT entry index
1134	sc_signal<size_t> r_xram_rsp_next_ptr; // Next pointer to the heap
1135	sc_signal<size_t> r_xram_rsp_victim_state;
1136
1137	// Buffer between XRAM_RSP fsm and TGT_RSP fsm (response to L1 cache)
1138	sc_signal<bool> r_xram_rsp_to_tgt_rsp_req; // Valid request
1139	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_srcid; // Transaction srcid
1140	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_trdid; // Transaction trdid
1141	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_pktid; // Transaction pktid
1142	sc_signal<data_t> * r_xram_rsp_to_tgt_rsp_data; // data (one cache line)
1143	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_word; // first word index
1144	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_length; // length of the response
1145	sc_signal<bool> r_xram_rsp_to_tgt_rsp_rerror; // send error to requester
1146	sc_signal<addr_t> r_xram_rsp_to_tgt_rsp_ll_key; // LL key from llsc_global_table
1147
1148	// Buffer between XRAM_RSP fsm and CC_SEND fsm (Inval L1 Caches)
1149	sc_signal<bool> r_xram_rsp_to_cc_send_multi_req; // Valid request
1150	sc_signal<bool> r_xram_rsp_to_cc_send_brdcast_req; // Broadcast request
1151	sc_signal<addr_t> r_xram_rsp_to_cc_send_nline; // cache line index;
1152	sc_signal<size_t> r_xram_rsp_to_cc_send_trdid; // index of UPT entry
1153	GenericFifo<bool> m_xram_rsp_to_cc_send_inst_fifo; // fifo for the L1 type
1154	GenericFifo<size_t> m_xram_rsp_to_cc_send_srcid_fifo; // fifo for srcids
1155
1156	// Buffer between XRAM_RSP fsm and IXR_CMD fsm
1157	sc_signal<bool> r_xram_rsp_to_ixr_cmd_req; // Valid request
1158	sc_signal<size_t> r_xram_rsp_to_ixr_cmd_index; // TRT index
1159
1160	//RWT
1161	sc_signal<bool> r_xram_rsp_victim_coherent; // victim's cache slot state
1162	sc_signal<bool> r_xram_rsp_coherent; // coherence of the read
1163	////////////////////////////////////////////////////
1164	// Registers controlled by the IXR_CMD fsm
1165	////////////////////////////////////////////////////
1166
1167	sc_signal<int> r_ixr_cmd_fsm;
1168	sc_signal<size_t> r_ixr_cmd_word; // word index for a put
1169	sc_signal<size_t> r_ixr_cmd_trdid; // TRT index value
1170	sc_signal<addr_t> r_ixr_cmd_address; // address to XRAM
1171	sc_signal<data_t> * r_ixr_cmd_wdata; // cache line buffer
1172	sc_signal<bool> r_ixr_cmd_get; // transaction type (PUT/GET)
1173
1174	////////////////////////////////////////////////////
1175	// Registers controlled by TGT_RSP fsm
1176	////////////////////////////////////////////////////
1177
1178	sc_signal<int> r_tgt_rsp_fsm;
1179	sc_signal<size_t> r_tgt_rsp_cpt;
1180	sc_signal<bool> r_tgt_rsp_key_sent;
1181
1182	////////////////////////////////////////////////////
1183	// Registers controlled by CC_SEND fsm
1184	////////////////////////////////////////////////////
1185
1186	sc_signal<int> r_cc_send_fsm;
1187	sc_signal<size_t> r_cc_send_cpt;
1188	sc_signal<bool> r_cc_send_inst;
1189
1190	////////////////////////////////////////////////////
1191	// Registers controlled by CC_RECEIVE fsm
1192	////////////////////////////////////////////////////
1193
1194	sc_signal<int> r_cc_receive_fsm;
1195
1196	////////////////////////////////////////////////////
1197	// Registers controlled by ALLOC_DIR fsm
1198	////////////////////////////////////////////////////
1199
1200	sc_signal<int> r_alloc_dir_fsm;
1201	sc_signal<unsigned> r_alloc_dir_reset_cpt;
1202
1203	////////////////////////////////////////////////////
1204	// Registers controlled by ALLOC_TRT fsm
1205	////////////////////////////////////////////////////
1206
1207	sc_signal<int> r_alloc_trt_fsm;
1208
1209	////////////////////////////////////////////////////
1210	// Registers controlled by ALLOC_UPT fsm
1211	////////////////////////////////////////////////////
1212
1213	// sc_signal<int> r_alloc_upt_fsm;
1214
1215	////////////////////////////////////////////////////
1216	// Registers controlled by ALLOC_IVT fsm
1217	////////////////////////////////////////////////////
1218
1219	sc_signal<int> r_alloc_ivt_fsm;
1220
1221	////////////////////////////////////////////////////
1222	// Registers controlled by ALLOC_HEAP fsm
1223	////////////////////////////////////////////////////
1224
1225	sc_signal<int> r_alloc_heap_fsm;
1226	sc_signal<unsigned> r_alloc_heap_reset_cpt;
1227
1228
1229	////////////////////////////////////////////////////
1230	// REGISTERS FOR ODCCP
1231	////////////////////////////////////////////////////
1232
1233	sc_signal<uint32_t> r_cleanup_data_index;
1234	sc_signal<uint32_t> r_cleanup_trdid;
1235	sc_signal<uint32_t> r_cleanup_state;
1236	sc_signal<uint32_t> r_cleanup_pktid;
1237	sc_signal<bool> r_cleanup_coherent;
1238	sc_signal<data_t> *r_cleanup_data;
1239	sc_signal<data_t> *r_cleanup_old_data;
1240	sc_signal<bool> r_cleanup_contains_data;
1241
1242	sc_signal<bool> r_cleanup_ncc;
1243	sc_signal<bool> r_cleanup_to_ixr_cmd_ncc_l1_dirty;
1244	sc_signal<bool> r_xram_rsp_to_ixr_cmd_inval_ncc_pending;
1245
1246	sc_signal<bool> r_cleanup_to_ixr_cmd_req;
1247	sc_signal<data_t> *r_cleanup_to_ixr_cmd_data;
1248	sc_signal<uint32_t> r_cleanup_to_ixr_cmd_srcid;
1249	sc_signal<uint32_t> r_cleanup_to_ixr_cmd_index;
1250	sc_signal<uint32_t> r_cleanup_to_ixr_cmd_pktid;
1251	sc_signal<addr_t> r_cleanup_to_ixr_cmd_nline;
1252	}; // end class VciMemCache
1253
1254	}}
1255
1256	#endif
1257
1258	// Local Variables:
1259	// tab-width: 2
1260	// c-basic-offset: 2
1261	// c-file-offsets:((innamespace . 0)(inline-open . 0))
1262	// indent-tabs-mode: nil
1263	// End:
1264
1265	// vim: filetype=cpp:expandtab:shiftwidth=2:tabstop=2:softtabstop=2
1266

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