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source: branches/MESI/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h @ 719

Last change on this file since 719 was 719, checked in by haoliu, 10 years ago

MESI: some modifications have been done for the MESI protocol in MAY for

some counters have been updated in component memcache and cc_vcache
fixed a bug in memcache (in WRITE FSM)

File size: 56.0 KB

Line
1	/* -- c++ --
2	* File : vci_mem_cache.h
3	* Date : 26/10/2008
4	* Copyright : UPMC / LIP6
5	* Authors : Alain Greiner / Eric Guthmuller
6	*
7	* SOCLIB_LGPL_HEADER_BEGIN
8	*
9	* This file is part of SoCLib, GNU LGPLv2.1.
10	*
11	* SoCLib is free software; you can redistribute it and/or modify it
12	* under the terms of the GNU Lesser General Public License as published
13	* by the Free Software Foundation; version 2.1 of the License.
14	*
15	* SoCLib is distributed in the hope that it will be useful, but
16	* WITHOUT ANY WARRANTY; without even the implied warranty of
17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18	* Lesser General Public License for more details.
19	*
20	* You should have received a copy of the GNU Lesser General Public
21	* License along with SoCLib; if not, write to the Free Software
22	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
23	* 02110-1301 USA
24	*
25	* SOCLIB_LGPL_HEADER_END
26	*
27	* Maintainers: alain.greiner@lip6.fr
28	* eric.guthmuller@polytechnique.edu
29	* cesar.fuguet-tortolero@lip6.fr
30	* alexandre.joannou@lip6.fr
31	*/
32
33	#ifndef SOCLIB_CABA_MEM_CACHE_H
34	#define SOCLIB_CABA_MEM_CACHE_H
35
36	#include <inttypes.h>
37	#include <systemc>
38	#include <list>
39	#include <cassert>
40	#include "arithmetics.h"
41	#include "alloc_elems.h"
42	#include "caba_base_module.h"
43	#include "vci_target.h"
44	#include "vci_initiator.h"
45	#include "generic_fifo.h"
46	#include "mapping_table.h"
47	#include "int_tab.h"
48	#include "generic_llsc_global_table.h"
49	#include "mem_cache_directory.h"
50	#include "xram_transaction.h"
51	#include "update_tab.h"
52	#include "dspin_interface.h"
53	#include "dspin_dhccp_param.h"
54
55	#define TRT_ENTRIES 4 // Number of entries in TRT
56	#define UPT_ENTRIES 4 // Number of entries in UPT
57	#define IVT_ENTRIES 4 // Number of entries in IVT
58	#define HEAP_ENTRIES 1024 // Number of entries in HEAP
59
60	namespace soclib { namespace caba {
61
62	using namespace sc_core;
63
64	template<typename vci_param_int,
65	typename vci_param_ext,
66	size_t dspin_in_width,
67	size_t dspin_out_width>
68	class VciMemCache
69	: public soclib::caba::BaseModule
70	{
71	typedef typename vci_param_int::fast_addr_t addr_t;
72	typedef typename sc_dt::sc_uint<64> wide_data_t;
73	typedef uint32_t data_t;
74	typedef uint32_t tag_t;
75	typedef uint32_t be_t;
76	typedef uint32_t copy_t;
77
78	/* States of the TGT_CMD fsm */
79	enum tgt_cmd_fsm_state_e
80	{
81	TGT_CMD_IDLE,
82	TGT_CMD_READ,
83	TGT_CMD_WRITE,
84	TGT_CMD_CAS,
85	TGT_CMD_ERROR,
86	TGT_CMD_CONFIG
87	};
88
89	/* States of the TGT_RSP fsm */
90	enum tgt_rsp_fsm_state_e
91	{
92	TGT_RSP_CONFIG_IDLE,
93	TGT_RSP_TGT_CMD_IDLE,
94	TGT_RSP_READ_IDLE,
95	TGT_RSP_WRITE_IDLE,
96	TGT_RSP_CAS_IDLE,
97	TGT_RSP_XRAM_IDLE,
98	TGT_RSP_MULTI_ACK_IDLE,
99	TGT_RSP_CLEANUP_IDLE,
100	TGT_RSP_CONFIG,
101	TGT_RSP_TGT_CMD,
102	TGT_RSP_READ,
103	TGT_RSP_WRITE,
104	TGT_RSP_CLEANUP,
105	TGT_RSP_CAS,
106	TGT_RSP_XRAM,
107	TGT_RSP_MULTI_ACK
108	};
109
110	/* States of the DSPIN_TGT fsm */
111	enum cc_receive_fsm_state_e
112	{
113	CC_RECEIVE_IDLE,
114	CC_RECEIVE_CLEANUP,
115	CC_RECEIVE_CLEANUP_EOP,
116	CC_RECEIVE_MULTI_ACK
117	};
118
119	/* States of the CC_SEND fsm */
120	enum cc_send_fsm_state_e
121	{
122	CC_SEND_CONFIG_IDLE,
123	CC_SEND_WRITE_IDLE,
124	CC_SEND_XRAM_RSP_IDLE,
125	CC_SEND_CAS_IDLE,
126	CC_SEND_READ_IDLE,
127	CC_SEND_CONFIG_INVAL_HEADER,
128	CC_SEND_CONFIG_INVAL_NLINE,
129	CC_SEND_CONFIG_BRDCAST_HEADER,
130	CC_SEND_CONFIG_BRDCAST_NLINE,
131	CC_SEND_XRAM_RSP_INVAL_HEADER,
132	CC_SEND_XRAM_RSP_INVAL_NLINE,
133	CC_SEND_XRAM_RSP_BRDCAST_HEADER,
134	CC_SEND_XRAM_RSP_BRDCAST_NLINE,
135	CC_SEND_READ_BRDCAST_HEADER,
136	CC_SEND_READ_BRDCAST_NLINE,
137	CC_SEND_READ_MULTI_HEADER,
138	CC_SEND_READ_MULTI_NLINE,
139	CC_SEND_WRITE_BRDCAST_HEADER,
140	CC_SEND_WRITE_BRDCAST_NLINE,
141	CC_SEND_WRITE_INVAL_HEADER,
142	CC_SEND_WRITE_INVAL_NLINE,
143	CC_SEND_CAS_BRDCAST_HEADER,
144	CC_SEND_CAS_BRDCAST_NLINE,
145	CC_SEND_CAS_INVAL_HEADER,
146	CC_SEND_CAS_INVAL_NLINE
147	};
148
149	/* States of the MULTI_ACK fsm */
150	enum multi_ack_fsm_state_e
151	{
152	MULTI_ACK_IDLE,
153	MULTI_ACK_GET_DATA,
154	MULTI_ACK_IVT_LOCK,
155	MULTI_ACK_IVT_CLEAR,
156	MULTI_ACK_DIR_REQ,
157	MULTI_ACK_DIR_LOCK,
158	MULTI_ACK_DIR_UPDT,
159	MULTI_ACK_RSP,
160	MULTI_ACK_HEAP_REQ,
161	MULTI_ACK_HEAP_LOCK,
162	MULTI_ACK_HEAP_WRITE,
163	MULTI_ACK_IVT_CHANGE
164	};
165
166	/* States of the CONFIG fsm */
167	enum config_fsm_state_e
168	{
169	CONFIG_IDLE,
170	CONFIG_LOOP,
171	CONFIG_WAIT,
172	CONFIG_RSP,
173	CONFIG_DIR_REQ,
174	CONFIG_DIR_ACCESS,
175	CONFIG_IVT_LOCK,
176	CONFIG_BC_SEND,
177	CONFIG_INVAL_SEND,
178	CONFIG_HEAP_REQ,
179	CONFIG_HEAP_SCAN,
180	CONFIG_HEAP_LAST,
181	CONFIG_TRT_LOCK,
182	CONFIG_TRT_SET,
183	CONFIG_PUT_REQ
184	};
185
186	/* States of the READ fsm */
187	enum read_fsm_state_e
188	{
189	READ_IDLE,
190	READ_DIR_REQ,
191	READ_DIR_LOCK,
192	READ_IVT_INVAL_LOCK,
193	READ_INVAL_HEAP_REQ,
194	READ_INVAL_HEAP_ERASE,
195	READ_INVAL_HEAP_LAST,
196	READ_IVT_UPDT_LOCK,
197	READ_WAIT,
198	READ_DIR_HIT,
199	READ_HEAP_REQ,
200	READ_HEAP_LOCK,
201	READ_HEAP_WRITE,
202	READ_HEAP_ERASE,
203	READ_HEAP_LAST,
204	READ_RSP,
205	READ_TRT_LOCK,
206	READ_TRT_SET,
207	READ_TRT_REQ
208	};
209
210	/* States of the WRITE fsm */
211	enum write_fsm_state_e
212	{
213	WRITE_IDLE,
214	WRITE_NEXT,
215	WRITE_DIR_REQ,
216	WRITE_DIR_LOCK,
217	WRITE_DIR_HIT,
218	WRITE_HEAP_REQ,
219	WRITE_HEAP_ERASE,
220	WRITE_HEAP_LAST,
221	WRITE_RSP,
222	WRITE_MISS_TRT_LOCK,
223	WRITE_WAIT,
224	WRITE_MISS_TRT_SET,
225	WRITE_MISS_TRT_DATA,
226	WRITE_MISS_XRAM_REQ,
227	WRITE_INVAL_IVT_LOCK,
228	WRITE_INVAL_CC_SEND
229	};
230
231	/* States of the IXR_RSP fsm */
232	enum ixr_rsp_fsm_state_e
233	{
234	IXR_RSP_IDLE,
235	IXR_RSP_ACK,
236	IXR_RSP_TRT_ERASE,
237	IXR_RSP_TRT_READ
238	};
239
240	/* States of the XRAM_RSP fsm */
241	enum xram_rsp_fsm_state_e
242	{
243	XRAM_RSP_IDLE,
244	XRAM_RSP_TRT_COPY,
245	XRAM_RSP_TRT_DIRTY,
246	XRAM_RSP_DIR_LOCK,
247	XRAM_RSP_DIR_UPDT,
248	XRAM_RSP_DIR_RSP,
249	XRAM_RSP_IVT_LOCK,
250	XRAM_RSP_INVAL_WAIT,
251	XRAM_RSP_INVAL,
252	XRAM_RSP_WRITE_DIRTY,
253	XRAM_RSP_HEAP_REQ,
254	XRAM_RSP_HEAP_ERASE,
255	XRAM_RSP_HEAP_LAST,
256	XRAM_RSP_ERROR_ERASE,
257	XRAM_RSP_ERROR_RSP
258	};
259
260	/* States of the IXR_CMD fsm */
261	enum ixr_cmd_fsm_state_e
262	{
263	IXR_CMD_READ_IDLE,
264	IXR_CMD_WRITE_IDLE,
265	IXR_CMD_CAS_IDLE,
266	IXR_CMD_XRAM_IDLE,
267	IXR_CMD_CLEANUP_IDLE,
268	IXR_CMD_CONFIG_IDLE,
269	IXR_CMD_READ_TRT,
270	IXR_CMD_WRITE_TRT,
271	IXR_CMD_CAS_TRT,
272	IXR_CMD_XRAM_TRT,
273	IXR_CMD_CLEANUP_TRT,
274	IXR_CMD_CONFIG_TRT,
275	IXR_CMD_READ_SEND,
276	IXR_CMD_WRITE_SEND,
277	IXR_CMD_CAS_SEND,
278	IXR_CMD_XRAM_SEND,
279	IXR_CMD_CLEANUP_DATA_SEND,
280	IXR_CMD_CONFIG_SEND
281	};
282
283	/* States of the CAS fsm */
284	enum cas_fsm_state_e
285	{
286	CAS_IDLE,
287	CAS_DIR_REQ,
288	CAS_DIR_LOCK,
289	CAS_DIR_HIT_READ,
290	CAS_DIR_HIT_COMPARE,
291	CAS_DIR_HIT_WRITE,
292	CAS_INVAL_IVT_LOCK,
293	CAS_WAIT,
294	CAS_MULTI_INVAL_HEAP_LOCK,
295	CAS_MULTI_INVAL_REQ,
296	CAS_HEAP_NEXT,
297	CAS_HEAP_LAST,
298	CAS_RSP_FAIL,
299	CAS_RSP_SUCCESS,
300	CAS_MISS_TRT_LOCK,
301	CAS_MISS_TRT_SET,
302	CAS_MISS_XRAM_REQ
303	};
304
305	/* States of the CLEANUP fsm */
306	enum cleanup_fsm_state_e
307	{
308	CLEANUP_IDLE,
309	CLEANUP_GET_NLINE,
310	CLEANUP_GET_DATA,
311	CLEANUP_DIR_REQ,
312	CLEANUP_DIR_LOCK,
313	CLEANUP_DIR_WRITE,
314	CLEANUP_LOCKED_IVT_LOCK,
315	CLEANUP_LOCKED_IVT_DECREMENT,
316	CLEANUP_LOCKED_IVT_CLEAR,
317	CLEANUP_LOCKED_RSP,
318	CLEANUP_HEAP_REQ,
319	CLEANUP_HEAP_LOCK,
320	CLEANUP_HEAP_SEARCH,
321	CLEANUP_HEAP_CLEAN,
322	CLEANUP_HEAP_FREE,
323	CLEANUP_MISS_IVT_LOCK,
324	CLEANUP_MISS_IVT_DECREMENT,
325	CLEANUP_MISS_IVT_CLEAR,
326	CLEANUP_MISS_RSP,
327	CLEANUP_MISS_IXR_REQ,
328	CLEANUP_WAIT,
329	CLEANUP_SEND_CLACK
330	};
331
332	/* States of the ALLOC_DIR fsm */
333	enum alloc_dir_fsm_state_e
334	{
335	ALLOC_DIR_RESET,
336	ALLOC_DIR_READ,
337	ALLOC_DIR_WRITE,
338	ALLOC_DIR_CAS,
339	ALLOC_DIR_CLEANUP,
340	ALLOC_DIR_XRAM_RSP,
341	ALLOC_DIR_MULTI_ACK,
342	ALLOC_DIR_CONFIG
343	};
344
345	/* States of the ALLOC_TRT fsm */
346	enum alloc_trt_fsm_state_e
347	{
348	ALLOC_TRT_READ,
349	ALLOC_TRT_WRITE,
350	ALLOC_TRT_CAS,
351	ALLOC_TRT_XRAM_RSP,
352	ALLOC_TRT_IXR_RSP,
353	ALLOC_TRT_CLEANUP,
354	ALLOC_TRT_IXR_CMD,
355	ALLOC_TRT_CONFIG
356	};
357
358	/* States of the ALLOC_IVT fsm */
359	enum alloc_ivt_fsm_state_e
360	{
361	ALLOC_IVT_WRITE,
362	ALLOC_IVT_READ,
363	ALLOC_IVT_XRAM_RSP,
364	ALLOC_IVT_CLEANUP,
365	ALLOC_IVT_CAS,
366	ALLOC_IVT_CONFIG,
367	ALLOC_IVT_MULTI_ACK
368	};
369
370	/* States of the ALLOC_HEAP fsm */
371	enum alloc_heap_fsm_state_e
372	{
373	ALLOC_HEAP_RESET,
374	ALLOC_HEAP_READ,
375	ALLOC_HEAP_WRITE,
376	ALLOC_HEAP_CAS,
377	ALLOC_HEAP_CLEANUP,
378	ALLOC_HEAP_MULTI_ACK,
379	ALLOC_HEAP_XRAM_RSP,
380	ALLOC_HEAP_CONFIG
381	};
382
383	/* transaction type, pktid field */
384	enum transaction_type_e
385	{
386	// b3 unused
387	// b2 READ / NOT READ
388	// Si READ
389	// b1 DATA / INS
390	// b0 UNC / MISS
391	// Si NOT READ
392	// b1 accÃšs table llsc type SW / other
393	// b2 WRITE/CAS/LL/SC
394	TYPE_DATA_UNC = 0x0,
395	TYPE_READ_DATA_MISS = 0x1,
396	TYPE_READ_INS_UNC = 0x2,
397	TYPE_READ_INS_MISS = 0x3,
398	TYPE_WRITE = 0x4,
399	TYPE_CAS = 0x5,
400	TYPE_LL = 0x6,
401	TYPE_SC = 0x7
402	};
403
404	/* SC return values */
405	enum sc_status_type_e
406	{
407	SC_SUCCESS = 0x00000000,
408	SC_FAIL = 0x00000001
409	};
410
411	// debug variables
412	bool m_debug;
413	size_t m_debug_previous_valid;
414	size_t m_debug_previous_count;
415	bool m_debug_previous_dirty;
416	data_t * m_debug_previous_data;
417	data_t * m_debug_data;
418
419	// instrumentation counters
420	uint32_t m_cpt_cycles; // Counter of cycles
421
422	// Counters accessible in software (not yet but eventually)
423	uint32_t m_cpt_reset_count; // Last cycle at which counters have been reset
424	uint32_t m_cpt_read_miss_local; // Number of local READ transactions
425	uint32_t m_cpt_read_miss_remote; // number of remote READ transactions
426	uint32_t m_cpt_read_miss_cost; // Number of (flits * distance) for READs
427
428	uint32_t m_cpt_getm_miss_local; // Number of local getm miss transactions
429	uint32_t m_cpt_getm_miss_remote; // number of remote getm miss transactions
430
431	uint32_t m_cpt_getm_hit_local; // Number of local getm hit transactions
432	uint32_t m_cpt_getm_hit_remote; // number of remote getm hit transactions
433	uint32_t m_cpt_getm_cost; // Number of (flits * distance) for getm
434
435	uint32_t m_cpt_write_local; // Number of local WRITE transactions
436	uint32_t m_cpt_write_remote; // number of remote WRITE transactions
437	uint32_t m_cpt_write_flits_local; // number of flits for local WRITEs
438	uint32_t m_cpt_write_flits_remote; // number of flits for remote WRITEs
439	uint32_t m_cpt_write_cost; // Number of (flits * distance) for WRITEs
440
441	uint32_t m_cpt_ll_local; // Number of local LL transactions
442	uint32_t m_cpt_ll_remote; // number of remote LL transactions
443	uint32_t m_cpt_ll_cost; // Number of (flits * distance) for LLs
444
445	uint32_t m_cpt_sc_local; // Number of local SC transactions
446	uint32_t m_cpt_sc_remote; // number of remote SC transactions
447	uint32_t m_cpt_sc_cost; // Number of (flits * distance) for SCs
448
449	uint32_t m_cpt_cas_local; // Number of local SC transactions
450	uint32_t m_cpt_cas_remote; // number of remote SC transactions
451	uint32_t m_cpt_cas_cost; // Number of (flits * distance) for SCs
452
453	uint32_t m_cpt_update; // Number of requests causing an UPDATE
454	uint32_t m_cpt_update_local; // Number of local UPDATE transactions
455	uint32_t m_cpt_update_remote; // Number of remote UPDATE transactions
456	uint32_t m_cpt_update_cost; // Number of (flits * distance) for UPDT
457
458	uint32_t m_cpt_minval; // Number of requests causing M_INV
459	uint32_t m_cpt_minval_local; // Number of local M_INV transactions
460	uint32_t m_cpt_minval_remote; // Number of remote M_INV transactions
461	uint32_t m_cpt_minval_cost; // Number of (flits * distance) for M_INV
462
463	uint32_t m_cpt_binval; // Number of BROADCAST INVAL
464
465	uint32_t m_cpt_cleanup_local; // Number of local CLEANUP transactions
466	uint32_t m_cpt_cleanup_remote; // Number of remote CLEANUP transactions
467	uint32_t m_cpt_cleanup_with_data;
468	uint32_t m_cpt_cleanup_cost; // Number of (flits * distance) for CLEANUPs
469
470	uint32_t m_cpt_multi_ack_miss; // Number of local CLEANUP transactions
471	uint32_t m_cpt_multi_ack_hit; // Number of local CLEANUP transactions
472	uint32_t m_cpt_multi_ack_hit_with_data; // Number of remote CLEANUP transactions
473
474	// Counters not accessible by software
475	uint32_t m_cpt_read_miss; // Number of MISS READ
476	uint32_t m_cpt_getm_miss; // Number of getm miss
477	uint32_t m_cpt_getm_broadcast; // Number of BROADCAST INVAL because getm
478	uint32_t m_cpt_getm_minval; // Number of MULTI INVAL because getm
479	uint32_t m_cpt_write_miss; // Number of MISS WRITE
480	uint32_t m_cpt_write_dirty; // Cumulated length for WRITE transactions
481	uint32_t m_cpt_write_broadcast;// Number of BROADCAST INVAL because write
482	uint32_t m_cpt_write_minval; // Number of MULTI INVAL because write
483	uint32_t m_cpt_cas_broadcast; // Number of BROADCAST INVAL because cas
484	uint32_t m_cpt_cas_minval; // Number of MULTI INVAL because cas
485	uint32_t m_cpt_cas_miss;
486
487	uint32_t m_cpt_read_locked_rb; // Read blocked by a locked ligne
488	uint32_t m_cpt_cas_locked_rb; // cas blocked by a locked ligne
489	uint32_t m_cpt_write_locked_rb; // wt blocked by a locked ligne
490
491	uint32_t m_cpt_trt_rb; // Read blocked by a hit in trt
492	uint32_t m_cpt_trt_full; // Transaction blocked due to a full trt
493	uint32_t m_cpt_put;
494	uint32_t m_cpt_get;
495
496	uint32_t m_cpt_read_fsm_dir_lock; // wait DIR LOCK
497	uint32_t m_cpt_read_fsm_n_dir_lock; // NB DIR LOCK
498	uint32_t m_cpt_write_fsm_dir_lock; // wait DIR LOCK
499	uint32_t m_cpt_write_fsm_n_dir_lock; // NB DIR LOCK
500	uint32_t m_cpt_xram_rsp_fsm_dir_lock; // wait DIR LOCK
501	uint32_t m_cpt_xram_rsp_fsm_n_dir_lock; // NB DIR LOCK
502	uint32_t m_cpt_cas_fsm_dir_lock; // wait DIR LOCK
503	uint32_t m_cpt_cas_fsm_n_dir_lock; // NB DIR LOCK
504	uint32_t m_cpt_cleanup_fsm_dir_lock; // wait DIR LOCK
505	uint32_t m_cpt_cleanup_fsm_n_dir_lock; // NB DIR LOCK
506	uint32_t m_cpt_multi_ack_fsm_dir_lock; // wait DIR LOCK
507	uint32_t m_cpt_multi_ack_fsm_n_dir_lock; // NB DIR LOCK
508
509	uint32_t m_cpt_dir_unused; // NB cycles DIR LOCK unused
510	uint32_t m_cpt_read_fsm_dir_used; // NB cycles DIR LOCK used
511	uint32_t m_cpt_write_fsm_dir_used; // NB cycles DIR LOCK used
512	uint32_t m_cpt_cas_fsm_dir_used; // NB cycles DIR LOCK used
513	uint32_t m_cpt_xram_rsp_fsm_dir_used; // NB cycles DIR LOCK used
514	uint32_t m_cpt_cleanup_fsm_dir_used; // NB cycles DIR LOCK used
515	uint32_t m_cpt_multi_ack_fsm_dir_used; // NB cycles DIR LOCK used
516
517	uint32_t m_cpt_read_fsm_trt_lock; // wait TRT LOCK
518	uint32_t m_cpt_write_fsm_trt_lock; // wait TRT LOCK
519	uint32_t m_cpt_cas_fsm_trt_lock; // wait TRT LOCK
520	uint32_t m_cpt_xram_rsp_fsm_trt_lock; // wait TRT LOCK
521	uint32_t m_cpt_ixr_fsm_trt_lock; // wait TRT LOCK
522
523	uint32_t m_cpt_read_fsm_n_trt_lock; // NB TRT LOCK
524	uint32_t m_cpt_write_fsm_n_trt_lock; // NB TRT LOCK
525	uint32_t m_cpt_cas_fsm_n_trt_lock; // NB TRT LOCK
526	uint32_t m_cpt_xram_rsp_fsm_n_trt_lock; // NB TRT LOCK
527	uint32_t m_cpt_ixr_cmd_fsm_n_trt_lock; // NB TRT LOCK
528	uint32_t m_cpt_ixr_rsp_fsm_n_trt_lock; // NB TRT LOCK
529
530	uint32_t m_cpt_read_fsm_trt_used; // NB cycles TRT LOCK used
531	uint32_t m_cpt_write_fsm_trt_used; // NB cycles TRT LOCK used
532	uint32_t m_cpt_cas_fsm_trt_used; // NB cycles TRT LOCK used
533	uint32_t m_cpt_xram_rsp_fsm_trt_used; // NB cycles TRT LOCK used
534	uint32_t m_cpt_ixr_cmd_fsm_trt_used; // NB cycles TRT LOCK used
535	uint32_t m_cpt_ixr_rsp_fsm_trt_used; // NB cycles TRT LOCK used
536	uint32_t m_cpt_cleanup_fsm_trt_used; // NB cycles TRT LOCK used
537
538	uint32_t m_cpt_trt_unused; // NB cycles TRT LOCK unused
539
540	uint32_t m_cpt_cleanup_fsm_ivt_lock; // wait ivt LOCK
541	uint32_t m_cpt_cleanup_fsm_n_ivt_lock; // NB cycles UPT LOCK used
542
543	uint32_t m_cpt_multi_ack_fsm_ivt_lock; // wait ivt LOCK
544	uint32_t m_cpt_multi_ack_fsm_n_ivt_lock; // NB cycles UPT LOCK used
545
546	uint32_t m_cpt_ivt_unused; // NB cycles UPT LOCK unused
547
548	uint32_t m_cpt_read_fsm_heap_lock; // wait HEAP LOCK
549	uint32_t m_cpt_write_fsm_heap_lock; // wait HEAP LOCK
550	uint32_t m_cpt_cas_fsm_heap_lock; // wait HEAP LOCK
551	uint32_t m_cpt_cleanup_fsm_heap_lock; // wait HEAP LOCK
552	uint32_t m_cpt_xram_rsp_fsm_heap_lock; // wait HEAP LOCK
553	uint32_t m_cpt_multi_ack_fsm_heap_lock; // wait HEAP LOCK
554
555	uint32_t m_cpt_read_fsm_n_heap_lock; // NB HEAP LOCK
556	uint32_t m_cpt_write_fsm_n_heap_lock; // NB HEAP LOCK
557	uint32_t m_cpt_cas_fsm_n_heap_lock; // NB HEAP LOCK
558	uint32_t m_cpt_cleanup_fsm_n_heap_lock; // NB HEAP LOCK
559	uint32_t m_cpt_xram_rsp_fsm_n_heap_lock; // NB HEAP LOCK
560	uint32_t m_cpt_multi_ack_fsm_n_heap_lock; // NB HEAP LOCK
561
562	uint32_t m_cpt_read_fsm_heap_used; // NB cycles HEAP LOCK used
563	uint32_t m_cpt_write_fsm_heap_used; // NB cycles HEAP LOCK used
564	uint32_t m_cpt_cas_fsm_heap_used; // NB cycles HEAP LOCK used
565	uint32_t m_cpt_cleanup_fsm_heap_used; // NB cycles HEAP LOCK used
566	uint32_t m_cpt_xram_rsp_fsm_heap_used; // NB cycles HEAP LOCK used
567	uint32_t m_cpt_multi_ack_fsm_heap_used; // NB cycles HEAP LOCK used
568
569	uint32_t m_cpt_heap_unused; // NB cycles HEAP LOCK unused
570	uint32_t m_cpt_slot_inval;
571
572	protected:
573
574	SC_HAS_PROCESS(VciMemCache);
575
576	public:
577	sc_in<bool> p_clk;
578	sc_in<bool> p_resetn;
579	sc_in<bool> p_irq;
580	soclib::caba::VciTarget<vci_param_int> p_vci_tgt;
581	soclib::caba::VciInitiator<vci_param_ext> p_vci_ixr;
582	soclib::caba::DspinInput<dspin_in_width> p_dspin_p2m;
583	soclib::caba::DspinOutput<dspin_out_width> p_dspin_m2p;
584	soclib::caba::DspinOutput<dspin_out_width> p_dspin_clack;
585
586	#if MONITOR_MEMCACHE_FSM == 1
587	sc_out<int> p_read_fsm;
588	sc_out<int> p_write_fsm;
589	sc_out<int> p_xram_rsp_fsm;
590	sc_out<int> p_cas_fsm;
591	sc_out<int> p_cleanup_fsm;
592	sc_out<int> p_config_fsm;
593	sc_out<int> p_alloc_heap_fsm;
594	sc_out<int> p_alloc_dir_fsm;
595	sc_out<int> p_alloc_trt_fsm;
596	sc_out<int> p_alloc_upt_fsm;
597	sc_out<int> p_alloc_ivt_fsm;
598	sc_out<int> p_tgt_cmd_fsm;
599	sc_out<int> p_tgt_rsp_fsm;
600	sc_out<int> p_ixr_cmd_fsm;
601	sc_out<int> p_ixr_rsp_fsm;
602	sc_out<int> p_cc_send_fsm;
603	sc_out<int> p_cc_receive_fsm;
604	sc_out<int> p_multi_ack_fsm;
605	#endif
606
607	VciMemCache(
608	sc_module_name name, // Instance Name
609	const soclib::common::MappingTable &mtp, // Mapping table INT network
610	const soclib::common::MappingTable &mtx, // Mapping table RAM network
611	const soclib::common::IntTab &srcid_x, // global index RAM network
612	const soclib::common::IntTab &tgtid_d, // global index INT network
613	const size_t cc_global_id, // global index CC network
614	const size_t x_width, // X width in platform
615	const size_t y_width, // Y width in platform
616	const size_t nways, // Number of ways per set
617	const size_t nsets, // Number of sets
618	const size_t nwords, // Number of words per line
619	const size_t max_copies, // max number of copies
620	const size_t heap_size=HEAP_ENTRIES,
621	const size_t trt_lines=TRT_ENTRIES,
622	const size_t upt_lines=UPT_ENTRIES,
623	const size_t ivt_lines=IVT_ENTRIES,
624	const size_t debug_start_cycle=0,
625	const bool debug_ok=false );
626
627	~VciMemCache();
628
629	void reset_counters();
630	void print_stats(bool activity_counters, bool stats);
631	void print_trace( size_t detailled = 0 );
632	void cache_monitor(addr_t addr);
633	void start_monitor(addr_t addr, addr_t length);
634	void stop_monitor();
635
636	private:
637
638	void transition();
639	void genMoore();
640	void check_monitor(addr_t addr, data_t data, bool read);
641	uint32_t req_distance(uint32_t req_srcid);
642	bool is_local_req(uint32_t req_srcid);
643	int read_instrumentation(uint32_t regr, uint32_t & rdata);
644
645	// Component attributes
646	std::list<soclib::common::Segment> m_seglist; // segments allocated
647	size_t m_nseg; // number of segments
648	soclib::common::Segment **m_seg; // array of segments pointers
649	size_t m_seg_config; // config segment index
650	const size_t m_srcid_x; // global index on RAM network
651	const size_t m_initiators; // Number of initiators
652	const size_t m_heap_size; // Size of the heap
653	const size_t m_ways; // Number of ways in a set
654	const size_t m_sets; // Number of cache sets
655	const size_t m_words; // Number of words in a line
656	const size_t m_cc_global_id; // global_index on cc network
657	const size_t m_xwidth; // number of x bits in platform
658	const size_t m_ywidth; // number of y bits in platform
659	size_t m_debug_start_cycle;
660	bool m_debug_ok;
661	uint32_t m_trt_lines;
662	TransactionTab m_trt; // xram transaction table
663	uint32_t m_upt_lines;
664	UpdateTab m_upt; // pending update
665	UpdateTab m_ivt; // pending invalidate
666	CacheDirectory m_cache_directory; // data cache directory
667	CacheData m_cache_data; // data array[set][way][word]
668	HeapDirectory m_heap; // heap for copies
669	size_t m_max_copies; // max number of copies in heap
670	GenericLLSCGlobalTable
671	< 32 , // number of slots
672	4096, // number of processors in the system
673	8000, // registration life (# of LL operations)
674	addr_t > m_llsc_table; // ll/sc registration table
675
676	// adress masks
677	const soclib::common::AddressMaskingTable<addr_t> m_x;
678	const soclib::common::AddressMaskingTable<addr_t> m_y;
679	const soclib::common::AddressMaskingTable<addr_t> m_z;
680	const soclib::common::AddressMaskingTable<addr_t> m_nline;
681
682	// broadcast address
683	uint32_t m_broadcast_boundaries;
684
685	// configuration interface constants
686	const uint32_t m_config_addr_mask;
687	const uint32_t m_config_regr_width;
688	const uint32_t m_config_func_width;
689	const uint32_t m_config_regr_idx_mask;
690	const uint32_t m_config_func_idx_mask;
691
692	// Fifo between TGT_CMD fsm and READ fsm
693	GenericFifo<addr_t> m_cmd_read_addr_fifo;
694	GenericFifo<size_t> m_cmd_read_length_fifo;
695	GenericFifo<size_t> m_cmd_read_srcid_fifo;
696	GenericFifo<size_t> m_cmd_read_trdid_fifo;
697	GenericFifo<size_t> m_cmd_read_pktid_fifo;
698
699	// Fifo between TGT_CMD fsm and WRITE fsm
700	GenericFifo<addr_t> m_cmd_write_addr_fifo;
701	GenericFifo<bool> m_cmd_write_eop_fifo;
702	GenericFifo<size_t> m_cmd_write_srcid_fifo;
703	GenericFifo<size_t> m_cmd_write_trdid_fifo;
704	GenericFifo<size_t> m_cmd_write_pktid_fifo;
705	GenericFifo<data_t> m_cmd_write_data_fifo;
706	GenericFifo<be_t> m_cmd_write_be_fifo;
707
708	// Fifo between TGT_CMD fsm and CAS fsm
709	GenericFifo<addr_t> m_cmd_cas_addr_fifo;
710	GenericFifo<bool> m_cmd_cas_eop_fifo;
711	GenericFifo<size_t> m_cmd_cas_srcid_fifo;
712	GenericFifo<size_t> m_cmd_cas_trdid_fifo;
713	GenericFifo<size_t> m_cmd_cas_pktid_fifo;
714	GenericFifo<data_t> m_cmd_cas_wdata_fifo;
715
716	// Fifo between CC_RECEIVE fsm and CLEANUP fsm
717	GenericFifo<uint64_t> m_cc_receive_to_cleanup_fifo;
718
719	// Fifo between CC_RECEIVE fsm and MULTI_ACK fsm
720	GenericFifo<uint64_t> m_cc_receive_to_multi_ack_fifo;
721
722	// Buffer between TGT_CMD fsm and TGT_RSP fsm
723	// (segmentation violation response request)
724	sc_signal<bool> r_tgt_cmd_to_tgt_rsp_req;
725
726	sc_signal<uint32_t> r_tgt_cmd_to_tgt_rsp_rdata;
727	sc_signal<size_t> r_tgt_cmd_to_tgt_rsp_error;
728	sc_signal<size_t> r_tgt_cmd_to_tgt_rsp_srcid;
729	sc_signal<size_t> r_tgt_cmd_to_tgt_rsp_trdid;
730	sc_signal<size_t> r_tgt_cmd_to_tgt_rsp_pktid;
731
732	sc_signal<addr_t> r_tgt_cmd_config_addr;
733	sc_signal<size_t> r_tgt_cmd_config_cmd;
734
735	//////////////////////////////////////////////////
736	// Registers controlled by the TGT_CMD fsm
737	//////////////////////////////////////////////////
738
739	sc_signal<int> r_tgt_cmd_fsm;
740
741	///////////////////////////////////////////////////////
742	// Registers controlled by the CONFIG fsm
743	///////////////////////////////////////////////////////
744
745	sc_signal<int> r_config_fsm; // FSM state
746	sc_signal<bool> r_config_lock; // lock protecting exclusive access
747	sc_signal<int> r_config_cmd; // config request type
748	sc_signal<addr_t> r_config_address; // target buffer physical address
749	sc_signal<size_t> r_config_srcid; // config request srcid
750	sc_signal<size_t> r_config_trdid; // config request trdid
751	sc_signal<size_t> r_config_pktid; // config request pktid
752	sc_signal<size_t> r_config_cmd_lines; // number of lines to be handled
753	sc_signal<size_t> r_config_rsp_lines; // number of lines not completed
754	sc_signal<size_t> r_config_dir_way; // DIR: selected way
755	sc_signal<bool> r_config_dir_lock; // DIR: locked entry
756	sc_signal<size_t> r_config_dir_count; // DIR: number of copies
757	sc_signal<bool> r_config_dir_is_cnt; // DIR: counter mode (broadcast)
758	sc_signal<size_t> r_config_dir_copy_srcid; // DIR: first copy SRCID
759	sc_signal<bool> r_config_dir_copy_inst; // DIR: first copy L1 type
760	sc_signal<size_t> r_config_dir_ptr; // DIR: index of next copy in HEAP
761	sc_signal<size_t> r_config_dir_state; // DIR: dir state
762	sc_signal<size_t> r_config_heap_next; // current pointer to scan HEAP
763	sc_signal<size_t> r_config_trt_index; // selected entry in TRT
764	sc_signal<size_t> r_config_ivt_index; // selected entry in IVT
765
766	// Buffer between CONFIG fsm and IXR_CMD fsm
767	sc_signal<bool> r_config_to_ixr_cmd_req; // valid request
768	sc_signal<size_t> r_config_to_ixr_cmd_index; // TRT index
769
770	// Buffer between CONFIG fsm and TGT_RSP fsm (send a done response to L1 cache)
771	sc_signal<bool> r_config_to_tgt_rsp_req; // valid request
772	sc_signal<bool> r_config_to_tgt_rsp_error; // error response
773	sc_signal<size_t> r_config_to_tgt_rsp_srcid; // Transaction srcid
774	sc_signal<size_t> r_config_to_tgt_rsp_trdid; // Transaction trdid
775	sc_signal<size_t> r_config_to_tgt_rsp_pktid; // Transaction pktid
776
777	// Buffer between CONFIG fsm and CC_SEND fsm (multi-inval / broadcast-inval)
778	sc_signal<bool> r_config_to_cc_send_multi_req; // multi-inval request
779	sc_signal<bool> r_config_to_cc_send_brdcast_req; // broadcast-inval request
780	sc_signal<addr_t> r_config_to_cc_send_nline; // line index
781	sc_signal<size_t> r_config_to_cc_send_trdid; // UPT index
782	GenericFifo<bool> m_config_to_cc_send_inst_fifo; // fifo for the L1 type
783	GenericFifo<size_t> m_config_to_cc_send_srcid_fifo; // fifo for owners srcid
784
785	///////////////////////////////////////////////////////
786	// Registers controlled by the READ fsm
787	///////////////////////////////////////////////////////
788
789	sc_signal<int> r_read_fsm; // FSM state
790	sc_signal<size_t> r_read_copy; // Srcid of the first copy
791	sc_signal<size_t> r_read_copy_cache; // Srcid of the first copy
792	sc_signal<bool> r_read_copy_inst; // Type of the first copy
793	sc_signal<tag_t> r_read_tag; // cache line tag (in directory)
794	sc_signal<bool> r_read_is_cnt; // is_cnt bit (in directory)
795	sc_signal<bool> r_read_lock; // lock bit (in directory)
796	sc_signal<bool> r_read_dirty; // dirty bit (in directory)
797	sc_signal<size_t> r_read_count; // number of copies
798	sc_signal<size_t> r_read_ptr; // pointer to the heap
799	sc_signal<data_t> * r_read_data; // data (one cache line)
800	sc_signal<size_t> r_read_way; // associative way (in cache)
801	sc_signal<size_t> r_read_trt_index; // Transaction Table index
802	sc_signal<size_t> r_read_next_ptr; // Next entry to point to
803	sc_signal<bool> r_read_last_free; // Last free entry
804	sc_signal<addr_t> r_read_ll_key; // LL key from llsc_global_table
805
806
807
808	sc_signal<bool> r_read_ll_done;
809	sc_signal<bool> r_read_need_block;
810	sc_signal<size_t> r_read_state;
811	// Buffer between READ fsm and IXR_CMD fsm
812	sc_signal<bool> r_read_to_ixr_cmd_req; // valid request
813	sc_signal<size_t> r_read_to_ixr_cmd_index; // TRT index
814
815	// Buffer between READ fsm and TGT_RSP fsm (send a hit read response to L1 cache)
816	sc_signal<bool> r_read_to_tgt_rsp_req; // valid request
817	sc_signal<size_t> r_read_to_tgt_rsp_srcid; // Transaction srcid
818	sc_signal<size_t> r_read_to_tgt_rsp_trdid; // Transaction trdid
819	sc_signal<size_t> r_read_to_tgt_rsp_pktid; // Transaction pktid
820	sc_signal<data_t> * r_read_to_tgt_rsp_data; // data (one cache line)
821	sc_signal<size_t> r_read_to_tgt_rsp_word; // first word of the response
822	sc_signal<size_t> r_read_to_tgt_rsp_length; // length of the response
823	sc_signal<addr_t> r_read_to_tgt_rsp_ll_key; // LL key from llsc_global_table
824
825	//RWT: Buffer between READ fsm and CC_SEND fsm (send inval)
826	sc_signal<bool> r_read_to_cc_send_req;
827	sc_signal<size_t> r_read_to_cc_send_dest;
828	sc_signal<addr_t> r_read_to_cc_send_nline;
829	sc_signal<bool> r_read_to_cc_send_inst;
830	sc_signal<size_t> r_read_to_cc_send_srcid;
831	sc_signal<size_t> r_read_to_cc_send_ivt_index;
832	sc_signal<bool> r_read_to_cc_send_multi_req; // multi inval
833	sc_signal<bool> r_read_to_cc_send_brdcast_req; // bd inval
834	sc_signal<bool> r_read_to_cc_send_type; //cc inval or cc updt
835	sc_signal<bool> r_read_to_cc_send_is_shared; //line is or not shared
836
837	//RWT: Buffer between READ fsm and CLEANUP fsm (wait for the data coming from L1 cache)
838	sc_signal<bool> r_read_to_cleanup_req; // valid request
839	sc_signal<addr_t> r_read_to_cleanup_nline; // cache line index
840	sc_signal<size_t> r_read_to_cleanup_srcid;
841	sc_signal<size_t> r_read_to_cleanup_length;
842	sc_signal<size_t> r_read_to_cleanup_first_word;
843	sc_signal<bool> r_read_to_cleanup_cached_read;
844	sc_signal<bool> r_read_to_cleanup_is_ll;
845	sc_signal<addr_t> r_read_to_cleanup_addr;
846	sc_signal<addr_t> r_read_to_cleanup_ll_key;
847
848	sc_signal<bool> r_read_to_multi_ack_req; // valid request
849	sc_signal<addr_t> r_read_to_multi_ack_nline; // cache line index
850	sc_signal<size_t> r_read_to_multi_ack_first_word;
851	sc_signal<bool> r_read_to_multi_ack_length;
852	sc_signal<addr_t> r_read_to_multi_ack_ll_key;
853
854
855	GenericFifo<bool> m_read_to_cc_send_inst_fifo; // fifo for the L1 type
856	GenericFifo<size_t> m_read_to_cc_send_srcid_fifo; // fifo for owners srcid
857
858
859
860	sc_signal<bool> r_multi_ack_need_data; // cc_updt rsp with data
861	sc_signal<size_t> r_multi_ack_data_index;
862	sc_signal<size_t> r_multi_ack_ivt_index;
863	sc_signal<size_t> r_multi_ack_set;
864	sc_signal<size_t> r_multi_ack_way;
865	sc_signal<size_t> r_multi_ack_count;
866	sc_signal<bool> r_multi_ack_rsp;
867	sc_signal<bool> r_multi_ack_rsp_shared;
868
869	sc_signal<size_t> r_multi_ack_copy; // Srcid of the first copy
870	sc_signal<bool> r_multi_ack_copy_inst; // Type of the first copy
871	sc_signal<tag_t> r_multi_ack_tag; // cache line tag (in directory)
872	sc_signal<bool> r_multi_ack_lock; // lock bit (in directory)
873	sc_signal<bool> r_multi_ack_dirty; // dirty bit (in directory)
874	sc_signal<data_t> * r_multi_ack_data; // data (one cache line)
875	sc_signal<size_t> r_multi_ack_to_tgt_rsp_word;
876	sc_signal<size_t> r_multi_ack_to_tgt_rsp_length;
877	sc_signal<size_t> r_multi_ack_to_tgt_ll_key;
878
879	sc_signal<bool> r_multi_ack_last_free;
880	sc_signal<bool> r_multi_ack_miss_updt;
881	sc_signal<size_t> r_multi_ack_next_ptr;
882
883	sc_signal<bool> r_read_shared; // State of the cache slot after transaction
884
885
886	sc_signal<data_t> * r_debug_data; // data (one cache line)
887	///////////////////////////////////////////////////////////////
888	// Registers controlled by the WRITE fsm
889	///////////////////////////////////////////////////////////////
890
891	sc_signal<int> r_write_fsm; // FSM state
892	sc_signal<size_t> r_write_state;
893	sc_signal<addr_t> r_write_address; // first word address
894	sc_signal<size_t> r_write_word_index; // first word index in line
895	sc_signal<size_t> r_write_word_count; // number of words in line
896	sc_signal<size_t> r_write_srcid; // transaction srcid
897	sc_signal<size_t> r_write_trdid; // transaction trdid
898	sc_signal<size_t> r_write_pktid; // transaction pktid
899	sc_signal<data_t> * r_write_data; // data (one cache line)
900	sc_signal<be_t> * r_write_be; // one byte enable per word
901	sc_signal<bool> r_write_byte; // (BE != 0X0) and (BE != 0xF)
902	sc_signal<bool> r_write_is_cnt; // is_cnt bit (in directory)
903	sc_signal<bool> r_write_lock; // lock bit (in directory)
904	sc_signal<tag_t> r_write_tag; // cache line tag (in directory)
905	sc_signal<size_t> r_write_copy; // first owner of the line
906	sc_signal<size_t> r_write_copy_cache; // first owner of the line
907	sc_signal<bool> r_write_copy_inst; // is this owner a ICache ?
908	sc_signal<size_t> r_write_count; // number of copies
909	sc_signal<size_t> r_write_ptr; // pointer to the heap
910	sc_signal<size_t> r_write_next_ptr; // next pointer to the heap
911	sc_signal<bool> r_write_to_dec; // need to decrement update counter
912	sc_signal<size_t> r_write_way; // way of the line
913	sc_signal<size_t> r_write_trt_index; // index in Transaction Table
914	sc_signal<size_t> r_write_upt_index; // index in Update Table
915	sc_signal<bool> r_write_sc_fail; // sc command failed
916	sc_signal<data_t> r_write_sc_key; // sc command key
917	sc_signal<bool> r_write_bc_data_we; // Write enable for data buffer
918	sc_signal<bool> r_write_inval_trt_send;
919	sc_signal<bool> r_write_data_we;
920
921	// Buffer between WRITE fsm and TGT_RSP fsm (acknowledge a write command from L1)
922	sc_signal<bool> r_write_to_tgt_rsp_req; // valid request
923	sc_signal<size_t> r_write_to_tgt_rsp_srcid; // transaction srcid
924	sc_signal<size_t> r_write_to_tgt_rsp_trdid; // transaction trdid
925	sc_signal<size_t> r_write_to_tgt_rsp_pktid; // transaction pktid
926	sc_signal<bool> r_write_to_tgt_rsp_sc_fail; // sc command failed
927
928	// Buffer between WRITE fsm and IXR_CMD fsm
929	sc_signal<bool> r_write_to_ixr_cmd_req; // valid request
930	sc_signal<size_t> r_write_to_ixr_cmd_index; // TRT index
931
932	// Buffer between WRITE fsm and CC_SEND fsm (Update/Invalidate L1 caches)
933	sc_signal<bool> r_write_to_cc_send_multi_req; // valid multicast request
934	sc_signal<bool> r_write_to_cc_send_brdcast_req; // valid brdcast request
935	sc_signal<addr_t> r_write_to_cc_send_nline; // cache line index
936	sc_signal<size_t> r_write_to_cc_send_trdid; // index in Update Table
937	sc_signal<data_t> * r_write_to_cleanup_data; // data (one cache line)
938	sc_signal<be_t> * r_write_to_cleanup_be; // word enable
939	sc_signal<size_t> r_write_to_cc_send_count; // number of words in line
940	sc_signal<size_t> r_write_to_cc_send_index; // index of first word in line
941	GenericFifo<bool> m_write_to_cc_send_inst_fifo; // fifo for the L1 type
942	GenericFifo<size_t> m_write_to_cc_send_srcid_fifo; // fifo for srcids
943
944	// Buffer between WRITE fsm and MULTI_ACK fsm (Decrement UPT entry)
945	sc_signal<bool> r_write_to_multi_ack_req; // valid request
946	sc_signal<size_t> r_write_to_multi_ack_upt_index; // index in update table
947
948	// RWT: Buffer between WRITE fsm and CLEANUP fsm (change slot state)
949	sc_signal<bool> r_write_to_cleanup_req; // valid request
950	sc_signal<addr_t> r_write_to_cleanup_nline; // cache line index
951
952	// RWT
953	sc_signal<bool> r_write_coherent; // cache slot state after transaction
954
955	//Buffer between WRITE fsm and CC_SEND fsm (INVAL for RWT)
956	sc_signal<bool> r_write_to_cc_send_req;
957	sc_signal<size_t> r_write_to_cc_send_dest;
958
959
960	/////////////////////////////////////////////////////////
961	// Registers controlled by MULTI_ACK fsm
962	//////////////////////////////////////////////////////////
963
964	sc_signal<int> r_multi_ack_fsm; // FSM state
965	sc_signal<size_t> r_multi_ack_upt_index; // index in the Update Table
966	sc_signal<size_t> r_multi_ack_srcid; // pending write srcid
967	sc_signal<size_t> r_multi_ack_trdid; // pending write trdid
968	sc_signal<size_t> r_multi_ack_pktid; // pending write pktid
969	sc_signal<addr_t> r_multi_ack_nline; // pending write nline
970
971	// Buffer between MULTI_ACK fsm and TGT_RSP fsm (complete write/update transaction)
972	sc_signal<bool> r_multi_ack_to_tgt_rsp_req; // valid request
973	sc_signal<size_t> r_multi_ack_to_tgt_rsp_srcid; // Transaction srcid
974	sc_signal<size_t> r_multi_ack_to_tgt_rsp_trdid; // Transaction trdid
975	sc_signal<size_t> r_multi_ack_to_tgt_rsp_pktid; // Transaction pktid
976
977	///////////////////////////////////////////////////////
978	// Registers controlled by CLEANUP fsm
979	///////////////////////////////////////////////////////
980
981	sc_signal<int> r_cleanup_fsm; // FSM state
982	sc_signal<size_t> r_cleanup_srcid; // transaction srcid
983	sc_signal<bool> r_cleanup_inst; // Instruction or Data ?
984	sc_signal<size_t> r_cleanup_way_index; // L1 Cache Way index
985	sc_signal<addr_t> r_cleanup_nline; // cache line index
986
987
988	sc_signal<copy_t> r_cleanup_copy; // first copy
989	sc_signal<copy_t> r_cleanup_copy_cache; // first copy
990	sc_signal<size_t> r_cleanup_copy_inst; // type of the first copy
991	sc_signal<copy_t> r_cleanup_count; // number of copies
992	sc_signal<size_t> r_cleanup_ptr; // pointer to the heap
993	sc_signal<size_t> r_cleanup_prev_ptr; // previous pointer to the heap
994	sc_signal<size_t> r_cleanup_prev_srcid; // srcid of previous heap entry
995	sc_signal<size_t> r_cleanup_prev_cache_id; // srcid of previous heap entry
996	sc_signal<bool> r_cleanup_prev_inst; // inst bit of previous heap entry
997	sc_signal<size_t> r_cleanup_next_ptr; // next pointer to the heap
998	sc_signal<tag_t> r_cleanup_tag; // cache line tag (in directory)
999	sc_signal<bool> r_cleanup_is_cnt; // inst bit (in directory)
1000	sc_signal<bool> r_cleanup_lock; // lock bit (in directory)
1001	sc_signal<bool> r_cleanup_dirty; // dirty bit (in directory)
1002	sc_signal<size_t> r_cleanup_way; // associative way (in cache)
1003
1004	sc_signal<size_t> r_cleanup_locked_srcid; // srcid of write rsp
1005	sc_signal<size_t> r_cleanup_locked_trdid; // trdid of write rsp
1006	sc_signal<size_t> r_cleanup_locked_pktid; // pktid of write rsp
1007	sc_signal<size_t> r_cleanup_locked_index; // ivt index
1008	sc_signal<bool> r_cleanup_locked_is_updt;
1009	sc_signal<bool> r_cleanup_locked_is_changed;
1010	sc_signal<bool> r_cleanup_locked_is_read;
1011
1012	sc_signal<size_t> r_cleanup_miss_srcid; // srcid of write rsp
1013	sc_signal<size_t> r_cleanup_miss_trdid; // trdid of write rsp
1014	sc_signal<size_t> r_cleanup_miss_pktid; // pktid of write rsp
1015	sc_signal<size_t> r_cleanup_miss_index; // ivt index
1016	sc_signal<bool> r_cleanup_miss_need_rsp; // write response required
1017	sc_signal<bool> r_cleanup_miss_need_ack; // config acknowledge required
1018
1019
1020	// Buffer between CLEANUP fsm and TGT_RSP fsm (acknowledge a write command from L1)
1021	sc_signal<bool> r_cleanup_to_tgt_rsp_req; // valid request
1022	sc_signal<size_t> r_cleanup_to_tgt_rsp_srcid; // transaction srcid
1023	sc_signal<size_t> r_cleanup_to_tgt_rsp_trdid; // transaction trdid
1024	sc_signal<size_t> r_cleanup_to_tgt_rsp_pktid; // transaction pktid
1025	sc_signal<addr_t> r_cleanup_to_tgt_rsp_ll_key;
1026	sc_signal<addr_t> r_cleanup_to_tgt_rsp_nline;
1027
1028	sc_signal<bool> r_cleanup_to_tgt_rsp_type;
1029	sc_signal<data_t> * r_cleanup_to_tgt_rsp_data;
1030	sc_signal<size_t> r_cleanup_to_tgt_rsp_length;
1031	sc_signal<size_t> r_cleanup_to_tgt_rsp_first_word;
1032
1033	sc_signal<data_t> * r_multi_ack_to_tgt_rsp_data;
1034	///////////////////////////////////////////////////////
1035	// Registers controlled by CAS fsm
1036	///////////////////////////////////////////////////////
1037
1038	sc_signal<int> r_cas_fsm; // FSM state
1039	sc_signal<data_t> r_cas_wdata; // write data word
1040	sc_signal<data_t> * r_cas_rdata; // read data word
1041	sc_signal<uint32_t> r_cas_lfsr; // lfsr for random introducing
1042	sc_signal<size_t> r_cas_cpt; // size of command
1043	sc_signal<copy_t> r_cas_copy; // Srcid of the first copy
1044	sc_signal<copy_t> r_cas_copy_cache; // Srcid of the first copy
1045	sc_signal<bool> r_cas_copy_inst; // Type of the first copy
1046	sc_signal<size_t> r_cas_count; // number of copies
1047	sc_signal<size_t> r_cas_ptr; // pointer to the heap
1048	sc_signal<size_t> r_cas_next_ptr; // next pointer to the heap
1049	sc_signal<bool> r_cas_is_cnt; // is_cnt bit (in directory)
1050	sc_signal<bool> r_cas_dirty; // dirty bit (in directory)
1051	sc_signal<size_t> r_cas_way; // way in directory
1052	sc_signal<size_t> r_cas_set; // set in directory
1053	sc_signal<data_t> r_cas_tag; // cache line tag (in directory)
1054	sc_signal<size_t> r_cas_trt_index; // Transaction Table index
1055	sc_signal<size_t> r_cas_ivt_index; // Update Table index
1056	sc_signal<data_t> * r_cas_data; // cache line data
1057
1058	sc_signal<bool> r_cas_coherent;
1059	sc_signal<size_t> r_cas_state;
1060
1061	// Buffer between CAS fsm and IXR_CMD fsm (XRAM write)
1062	sc_signal<bool> r_cas_to_ixr_cmd_req; // valid request
1063	sc_signal<size_t> r_cas_to_ixr_cmd_index; // TRT index
1064
1065	// Buffer between CAS fsm and TGT_RSP fsm
1066	sc_signal<bool> r_cas_to_tgt_rsp_req; // valid request
1067	sc_signal<data_t> r_cas_to_tgt_rsp_data; // read data word
1068	sc_signal<size_t> r_cas_to_tgt_rsp_srcid; // Transaction srcid
1069	sc_signal<size_t> r_cas_to_tgt_rsp_trdid; // Transaction trdid
1070	sc_signal<size_t> r_cas_to_tgt_rsp_pktid; // Transaction pktid
1071
1072	// Buffer between CAS fsm and CC_SEND fsm (Update/Invalidate L1 caches)
1073	sc_signal<bool> r_cas_to_cc_send_multi_req; // valid request
1074	sc_signal<bool> r_cas_to_cc_send_brdcast_req; // brdcast request
1075	sc_signal<addr_t> r_cas_to_cc_send_nline; // cache line index
1076	sc_signal<size_t> r_cas_to_cc_send_trdid; // index in Update Table
1077	sc_signal<data_t> r_cas_to_cc_send_wdata; // data (one word)
1078	sc_signal<bool> r_cas_to_cc_send_is_long; // it is a 64 bits CAS
1079	sc_signal<data_t> r_cas_to_cc_send_wdata_high; // data high (one word)
1080	sc_signal<size_t> r_cas_to_cc_send_index; // index of the word in line
1081	GenericFifo<bool> m_cas_to_cc_send_inst_fifo; // fifo for the L1 type
1082	GenericFifo<size_t> m_cas_to_cc_send_srcid_fifo; // fifo for srcids
1083
1084	sc_signal<bool> r_cas_to_cleanup_req;
1085	sc_signal<addr_t> r_cas_to_cleanup_nline;
1086	////////////////////////////////////////////////////
1087	// Registers controlled by the IXR_RSP fsm
1088	////////////////////////////////////////////////////
1089
1090	sc_signal<int> r_ixr_rsp_fsm; // FSM state
1091	sc_signal<size_t> r_ixr_rsp_trt_index; // TRT entry index
1092	sc_signal<size_t> r_ixr_rsp_cpt; // word counter
1093
1094	// Buffer between IXR_RSP fsm and CONFIG fsm (response from the XRAM)
1095	sc_signal<bool> r_ixr_rsp_to_config_ack; // one single bit
1096
1097	// Buffer between IXR_RSP fsm and XRAM_RSP fsm (response from the XRAM)
1098	sc_signal<bool> * r_ixr_rsp_to_xram_rsp_rok; // one bit per TRT entry
1099
1100	////////////////////////////////////////////////////
1101	// Registers controlled by the XRAM_RSP fsm
1102	////////////////////////////////////////////////////
1103
1104	sc_signal<int> r_xram_rsp_fsm; // FSM state
1105	sc_signal<size_t> r_xram_rsp_trt_index; // TRT entry index
1106	TransactionTabEntry r_xram_rsp_trt_buf; // TRT entry local buffer
1107	sc_signal<bool> r_xram_rsp_victim_inval; // victim line invalidate
1108	sc_signal<bool> r_xram_rsp_victim_is_cnt; // victim line inst bit
1109	sc_signal<bool> r_xram_rsp_victim_dirty; // victim line dirty bit
1110	sc_signal<size_t> r_xram_rsp_victim_way; // victim line way
1111	sc_signal<size_t> r_xram_rsp_victim_set; // victim line set
1112	sc_signal<addr_t> r_xram_rsp_victim_nline; // victim line index
1113	sc_signal<copy_t> r_xram_rsp_victim_copy; // victim line first copy
1114	sc_signal<copy_t> r_xram_rsp_victim_copy_cache; // victim line first copy
1115	sc_signal<bool> r_xram_rsp_victim_copy_inst; // victim line type of first copy
1116	sc_signal<size_t> r_xram_rsp_victim_count; // victim line number of copies
1117	sc_signal<size_t> r_xram_rsp_victim_ptr; // victim line pointer to the heap
1118	sc_signal<data_t> * r_xram_rsp_victim_data; // victim line data
1119	sc_signal<size_t> r_xram_rsp_ivt_index; // IVT entry index
1120	sc_signal<size_t> r_xram_rsp_next_ptr; // Next pointer to the heap
1121	sc_signal<size_t> r_xram_rsp_victim_state;
1122
1123	// Buffer between XRAM_RSP fsm and TGT_RSP fsm (response to L1 cache)
1124	sc_signal<bool> r_xram_rsp_to_tgt_rsp_req; // Valid request
1125	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_srcid; // Transaction srcid
1126	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_trdid; // Transaction trdid
1127	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_pktid; // Transaction pktid
1128	sc_signal<data_t> * r_xram_rsp_to_tgt_rsp_data; // data (one cache line)
1129	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_word; // first word index
1130	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_length; // length of the response
1131	sc_signal<bool> r_xram_rsp_to_tgt_rsp_rerror; // send error to requester
1132	sc_signal<addr_t> r_xram_rsp_to_tgt_rsp_ll_key; // LL key from llsc_global_table
1133
1134	// Buffer between XRAM_RSP fsm and CC_SEND fsm (Inval L1 Caches)
1135	sc_signal<bool> r_xram_rsp_to_cc_send_multi_req; // Valid request
1136	sc_signal<bool> r_xram_rsp_to_cc_send_brdcast_req; // Broadcast request
1137	sc_signal<addr_t> r_xram_rsp_to_cc_send_nline; // cache line index;
1138	sc_signal<size_t> r_xram_rsp_to_cc_send_trdid; // index of UPT entry
1139	GenericFifo<bool> m_xram_rsp_to_cc_send_inst_fifo; // fifo for the L1 type
1140	GenericFifo<size_t> m_xram_rsp_to_cc_send_srcid_fifo; // fifo for srcids
1141
1142	// Buffer between XRAM_RSP fsm and IXR_CMD fsm
1143	sc_signal<bool> r_xram_rsp_to_ixr_cmd_req; // Valid request
1144	sc_signal<size_t> r_xram_rsp_to_ixr_cmd_index; // TRT index
1145
1146	//RWT
1147	sc_signal<bool> r_xram_rsp_victim_coherent; // victim's cache slot state
1148	sc_signal<bool> r_xram_rsp_coherent; // coherence of the read
1149	////////////////////////////////////////////////////
1150	// Registers controlled by the IXR_CMD fsm
1151	////////////////////////////////////////////////////
1152
1153	sc_signal<int> r_ixr_cmd_fsm;
1154	sc_signal<size_t> r_ixr_cmd_word; // word index for a put
1155	sc_signal<size_t> r_ixr_cmd_trdid; // TRT index value
1156	sc_signal<addr_t> r_ixr_cmd_address; // address to XRAM
1157	sc_signal<data_t> * r_ixr_cmd_wdata; // cache line buffer
1158	sc_signal<bool> r_ixr_cmd_get; // transaction type (PUT/GET)
1159
1160	////////////////////////////////////////////////////
1161	// Registers controlled by TGT_RSP fsm
1162	////////////////////////////////////////////////////
1163
1164	sc_signal<int> r_tgt_rsp_fsm;
1165	sc_signal<size_t> r_tgt_rsp_cpt;
1166	sc_signal<bool> r_tgt_rsp_key_sent;
1167
1168	////////////////////////////////////////////////////
1169	// Registers controlled by CC_SEND fsm
1170	////////////////////////////////////////////////////
1171
1172	sc_signal<int> r_cc_send_fsm;
1173	sc_signal<size_t> r_cc_send_cpt;
1174	sc_signal<bool> r_cc_send_inst;
1175
1176	////////////////////////////////////////////////////
1177	// Registers controlled by CC_RECEIVE fsm
1178	////////////////////////////////////////////////////
1179
1180	sc_signal<int> r_cc_receive_fsm;
1181
1182	////////////////////////////////////////////////////
1183	// Registers controlled by ALLOC_DIR fsm
1184	////////////////////////////////////////////////////
1185
1186	sc_signal<int> r_alloc_dir_fsm;
1187	sc_signal<unsigned> r_alloc_dir_reset_cpt;
1188
1189	////////////////////////////////////////////////////
1190	// Registers controlled by ALLOC_TRT fsm
1191	////////////////////////////////////////////////////
1192
1193	sc_signal<int> r_alloc_trt_fsm;
1194
1195	////////////////////////////////////////////////////
1196	// Registers controlled by ALLOC_UPT fsm
1197	////////////////////////////////////////////////////
1198
1199	// sc_signal<int> r_alloc_upt_fsm;
1200
1201	////////////////////////////////////////////////////
1202	// Registers controlled by ALLOC_IVT fsm
1203	////////////////////////////////////////////////////
1204
1205	sc_signal<int> r_alloc_ivt_fsm;
1206
1207	////////////////////////////////////////////////////
1208	// Registers controlled by ALLOC_HEAP fsm
1209	////////////////////////////////////////////////////
1210
1211	sc_signal<int> r_alloc_heap_fsm;
1212	sc_signal<unsigned> r_alloc_heap_reset_cpt;
1213
1214
1215	////////////////////////////////////////////////////
1216	// REGISTERS FOR ODCCP
1217	////////////////////////////////////////////////////
1218
1219	sc_signal<uint32_t> r_cleanup_data_index;
1220	sc_signal<uint32_t> r_cleanup_trdid;
1221	sc_signal<uint32_t> r_cleanup_state;
1222	sc_signal<uint32_t> r_cleanup_pktid;
1223	sc_signal<bool> r_cleanup_coherent;
1224	sc_signal<data_t> *r_cleanup_data;
1225	sc_signal<data_t> *r_cleanup_old_data;
1226	sc_signal<bool> r_cleanup_contains_data;
1227
1228	sc_signal<bool> r_cleanup_ncc;
1229	sc_signal<bool> r_cleanup_to_ixr_cmd_ncc_l1_dirty;
1230	sc_signal<bool> r_xram_rsp_to_ixr_cmd_inval_ncc_pending;
1231
1232	sc_signal<bool> r_cleanup_to_ixr_cmd_req;
1233	sc_signal<data_t> *r_cleanup_to_ixr_cmd_data;
1234	sc_signal<uint32_t> r_cleanup_to_ixr_cmd_srcid;
1235	sc_signal<uint32_t> r_cleanup_to_ixr_cmd_index;
1236	sc_signal<uint32_t> r_cleanup_to_ixr_cmd_pktid;
1237	sc_signal<addr_t> r_cleanup_to_ixr_cmd_nline;
1238	}; // end class VciMemCache
1239
1240	}}
1241
1242	#endif
1243
1244	// Local Variables:
1245	// tab-width: 2
1246	// c-basic-offset: 2
1247	// c-file-offsets:((innamespace . 0)(inline-open . 0))
1248	// indent-tabs-mode: nil
1249	// End:
1250
1251	// vim: filetype=cpp:expandtab:shiftwidth=2:tabstop=2:softtabstop=2
1252

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