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source: branches/MESI/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h @ 785

Last change on this file since 785 was 785, checked in by meunier, 10 years ago

MESI branch:

Cosmetic
Changing counters definitions and tags
Renaming dspin_dhccp_param to dspin_hmesi_param

File size: 50.4 KB

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1	/* -- c++ --
2	* File : vci_mem_cache.h
3	* Date : 26/10/2008
4	* Copyright : UPMC / LIP6
5	* Authors : Alain Greiner / Eric Guthmuller
6	*
7	* SOCLIB_LGPL_HEADER_BEGIN
8	*
9	* This file is part of SoCLib, GNU LGPLv2.1.
10	*
11	* SoCLib is free software; you can redistribute it and/or modify it
12	* under the terms of the GNU Lesser General Public License as published
13	* by the Free Software Foundation; version 2.1 of the License.
14	*
15	* SoCLib is distributed in the hope that it will be useful, but
16	* WITHOUT ANY WARRANTY; without even the implied warranty of
17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18	* Lesser General Public License for more details.
19	*
20	* You should have received a copy of the GNU Lesser General Public
21	* License along with SoCLib; if not, write to the Free Software
22	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
23	* 02110-1301 USA
24	*
25	* SOCLIB_LGPL_HEADER_END
26	*
27	* Maintainers: alain.greiner@lip6.fr
28	* eric.guthmuller@polytechnique.edu
29	* cesar.fuguet-tortolero@lip6.fr
30	* alexandre.joannou@lip6.fr
31	*/
32
33	#ifndef SOCLIB_CABA_MEM_CACHE_H
34	#define SOCLIB_CABA_MEM_CACHE_H
35
36	#include <inttypes.h>
37	#include <systemc>
38	#include <list>
39	#include <cassert>
40
41	#include "arithmetics.h"
42	#include "alloc_elems.h"
43	#include "caba_base_module.h"
44	#include "vci_target.h"
45	#include "vci_initiator.h"
46	#include "generic_fifo.h"
47	#include "mapping_table.h"
48	#include "int_tab.h"
49	#include "generic_llsc_global_table.h"
50	#include "mem_cache_directory.h"
51	#include "xram_transaction.h"
52	#include "update_tab.h"
53	#include "dspin_interface.h"
54	#include "dspin_hmesi_param.h"
55
56	#define TRT_ENTRIES 4 // Number of entries in TRT
57	#define UPT_ENTRIES 4 // Number of entries in UPT
58	#define IVT_ENTRIES 4 // Number of entries in IVT
59	#define HEAP_ENTRIES 1024 // Number of entries in HEAP
60
61	namespace soclib { namespace caba {
62
63	using namespace sc_core;
64
65	template<typename vci_param_int,
66	typename vci_param_ext,
67	size_t dspin_in_width,
68	size_t dspin_out_width>
69	class VciMemCache
70	: public soclib::caba::BaseModule
71	{
72	typedef typename vci_param_int::fast_addr_t addr_t;
73	typedef typename sc_dt::sc_uint<64> wide_data_t;
74	typedef uint32_t data_t;
75	typedef uint32_t tag_t;
76	typedef uint32_t be_t;
77	typedef uint32_t copy_t;
78
79	/* States of the TGT_CMD fsm */
80	enum tgt_cmd_fsm_state_e
81	{
82	TGT_CMD_IDLE,
83	TGT_CMD_READ,
84	TGT_CMD_WRITE,
85	TGT_CMD_CAS,
86	TGT_CMD_ERROR,
87	TGT_CMD_CONFIG
88	};
89
90	/* States of the TGT_RSP fsm */
91	enum tgt_rsp_fsm_state_e
92	{
93	TGT_RSP_CONFIG_IDLE,
94	TGT_RSP_TGT_CMD_IDLE,
95	TGT_RSP_READ_IDLE,
96	TGT_RSP_WRITE_IDLE,
97	TGT_RSP_CAS_IDLE,
98	TGT_RSP_XRAM_IDLE,
99	TGT_RSP_MULTI_ACK_IDLE,
100	TGT_RSP_CLEANUP_IDLE,
101	TGT_RSP_CONFIG,
102	TGT_RSP_TGT_CMD,
103	TGT_RSP_READ,
104	TGT_RSP_WRITE,
105	TGT_RSP_CLEANUP,
106	TGT_RSP_CAS,
107	TGT_RSP_XRAM,
108	TGT_RSP_MULTI_ACK
109	};
110
111	/* States of the DSPIN_TGT fsm */
112	enum cc_receive_fsm_state_e
113	{
114	CC_RECEIVE_IDLE,
115	CC_RECEIVE_CLEANUP,
116	CC_RECEIVE_CLEANUP_EOP,
117	CC_RECEIVE_MULTI_ACK
118	};
119
120	/* States of the CC_SEND fsm */
121	enum cc_send_fsm_state_e
122	{
123	CC_SEND_CONFIG_IDLE,
124	CC_SEND_WRITE_IDLE,
125	CC_SEND_XRAM_RSP_IDLE,
126	CC_SEND_CAS_IDLE,
127	CC_SEND_READ_IDLE,
128	CC_SEND_CONFIG_INVAL_HEADER,
129	CC_SEND_CONFIG_INVAL_NLINE,
130	CC_SEND_CONFIG_BRDCAST_HEADER,
131	CC_SEND_CONFIG_BRDCAST_NLINE,
132	CC_SEND_XRAM_RSP_INVAL_HEADER,
133	CC_SEND_XRAM_RSP_INVAL_NLINE,
134	CC_SEND_XRAM_RSP_BRDCAST_HEADER,
135	CC_SEND_XRAM_RSP_BRDCAST_NLINE,
136	CC_SEND_READ_BRDCAST_HEADER,
137	CC_SEND_READ_BRDCAST_NLINE,
138	CC_SEND_READ_MULTI_HEADER,
139	CC_SEND_READ_MULTI_NLINE,
140	CC_SEND_WRITE_BRDCAST_HEADER,
141	CC_SEND_WRITE_BRDCAST_NLINE,
142	CC_SEND_WRITE_INVAL_HEADER,
143	CC_SEND_WRITE_INVAL_NLINE,
144	CC_SEND_CAS_BRDCAST_HEADER,
145	CC_SEND_CAS_BRDCAST_NLINE,
146	CC_SEND_CAS_INVAL_HEADER,
147	CC_SEND_CAS_INVAL_NLINE
148	};
149
150	/* States of the MULTI_ACK fsm */
151	enum multi_ack_fsm_state_e
152	{
153	MULTI_ACK_IDLE,
154	MULTI_ACK_GET_DATA,
155	MULTI_ACK_IVT_LOCK,
156	MULTI_ACK_IVT_CLEAR,
157	MULTI_ACK_DIR_REQ,
158	MULTI_ACK_DIR_LOCK,
159	MULTI_ACK_DIR_UPDT,
160	MULTI_ACK_RSP,
161	MULTI_ACK_HEAP_REQ,
162	MULTI_ACK_HEAP_LOCK,
163	MULTI_ACK_HEAP_WRITE,
164	MULTI_ACK_IVT_CHANGE
165	};
166
167	/* States of the CONFIG fsm */
168	enum config_fsm_state_e
169	{
170	CONFIG_IDLE,
171	CONFIG_LOOP,
172	CONFIG_WAIT,
173	CONFIG_RSP,
174	CONFIG_DIR_REQ,
175	CONFIG_DIR_ACCESS,
176	CONFIG_IVT_LOCK,
177	CONFIG_BC_SEND,
178	CONFIG_INVAL_SEND,
179	CONFIG_HEAP_REQ,
180	CONFIG_HEAP_SCAN,
181	CONFIG_HEAP_LAST,
182	CONFIG_TRT_LOCK,
183	CONFIG_TRT_SET,
184	CONFIG_PUT_REQ
185	};
186
187	/* States of the READ fsm */
188	enum read_fsm_state_e
189	{
190	READ_IDLE,
191	READ_DIR_REQ,
192	READ_DIR_LOCK,
193	READ_IVT_INVAL_LOCK,
194	READ_INVAL_HEAP_REQ,
195	READ_INVAL_HEAP_ERASE,
196	READ_INVAL_HEAP_LAST,
197	READ_IVT_UPDT_LOCK,
198	READ_WAIT,
199	READ_DIR_HIT,
200	READ_HEAP_REQ,
201	READ_HEAP_LOCK,
202	READ_HEAP_WRITE,
203	READ_HEAP_ERASE,
204	READ_HEAP_LAST,
205	READ_RSP,
206	READ_TRT_LOCK,
207	READ_TRT_SET,
208	READ_TRT_REQ
209	};
210
211	/* States of the WRITE fsm */
212	enum write_fsm_state_e
213	{
214	WRITE_IDLE,
215	WRITE_NEXT,
216	WRITE_DIR_REQ,
217	WRITE_DIR_LOCK,
218	WRITE_DIR_HIT,
219	WRITE_HEAP_REQ,
220	WRITE_HEAP_ERASE,
221	WRITE_HEAP_LAST,
222	WRITE_RSP,
223	WRITE_MISS_TRT_LOCK,
224	WRITE_WAIT,
225	WRITE_MISS_TRT_SET,
226	WRITE_MISS_TRT_DATA,
227	WRITE_MISS_XRAM_REQ,
228	WRITE_INVAL_IVT_LOCK,
229	WRITE_INVAL_CC_SEND
230	};
231
232	/* States of the IXR_RSP fsm */
233	enum ixr_rsp_fsm_state_e
234	{
235	IXR_RSP_IDLE,
236	IXR_RSP_ACK,
237	IXR_RSP_TRT_ERASE,
238	IXR_RSP_TRT_READ
239	};
240
241	/* States of the XRAM_RSP fsm */
242	enum xram_rsp_fsm_state_e
243	{
244	XRAM_RSP_IDLE,
245	XRAM_RSP_TRT_COPY,
246	XRAM_RSP_TRT_DIRTY,
247	XRAM_RSP_DIR_LOCK,
248	XRAM_RSP_DIR_UPDT,
249	XRAM_RSP_DIR_RSP,
250	XRAM_RSP_IVT_LOCK,
251	XRAM_RSP_INVAL_WAIT,
252	XRAM_RSP_INVAL,
253	XRAM_RSP_WRITE_DIRTY,
254	XRAM_RSP_HEAP_REQ,
255	XRAM_RSP_HEAP_ERASE,
256	XRAM_RSP_HEAP_LAST,
257	XRAM_RSP_ERROR_ERASE,
258	XRAM_RSP_ERROR_RSP
259	};
260
261	/* States of the IXR_CMD fsm */
262	enum ixr_cmd_fsm_state_e
263	{
264	IXR_CMD_READ_IDLE,
265	IXR_CMD_WRITE_IDLE,
266	IXR_CMD_CAS_IDLE,
267	IXR_CMD_XRAM_IDLE,
268	IXR_CMD_CLEANUP_IDLE,
269	IXR_CMD_CONFIG_IDLE,
270	IXR_CMD_READ_TRT,
271	IXR_CMD_WRITE_TRT,
272	IXR_CMD_CAS_TRT,
273	IXR_CMD_XRAM_TRT,
274	IXR_CMD_CLEANUP_TRT,
275	IXR_CMD_CONFIG_TRT,
276	IXR_CMD_READ_SEND,
277	IXR_CMD_WRITE_SEND,
278	IXR_CMD_CAS_SEND,
279	IXR_CMD_XRAM_SEND,
280	IXR_CMD_CLEANUP_DATA_SEND,
281	IXR_CMD_CONFIG_SEND
282	};
283
284	/* States of the CAS fsm */
285	enum cas_fsm_state_e
286	{
287	CAS_IDLE,
288	CAS_DIR_REQ,
289	CAS_DIR_LOCK,
290	CAS_DIR_HIT_READ,
291	CAS_DIR_HIT_COMPARE,
292	CAS_DIR_HIT_WRITE,
293	CAS_INVAL_IVT_LOCK,
294	CAS_WAIT,
295	CAS_MULTI_INVAL_HEAP_LOCK,
296	CAS_MULTI_INVAL_REQ,
297	CAS_HEAP_NEXT,
298	CAS_HEAP_LAST,
299	CAS_RSP_FAIL,
300	CAS_RSP_SUCCESS,
301	CAS_MISS_TRT_LOCK,
302	CAS_MISS_TRT_SET,
303	CAS_MISS_XRAM_REQ
304	};
305
306	/* States of the CLEANUP fsm */
307	enum cleanup_fsm_state_e
308	{
309	CLEANUP_IDLE,
310	CLEANUP_GET_NLINE,
311	CLEANUP_GET_DATA,
312	CLEANUP_DIR_REQ,
313	CLEANUP_DIR_LOCK,
314	CLEANUP_DIR_WRITE,
315	CLEANUP_LOCKED_IVT_LOCK,
316	CLEANUP_LOCKED_IVT_DECREMENT,
317	CLEANUP_LOCKED_IVT_CLEAR,
318	CLEANUP_LOCKED_RSP,
319	CLEANUP_HEAP_REQ,
320	CLEANUP_HEAP_LOCK,
321	CLEANUP_HEAP_SEARCH,
322	CLEANUP_HEAP_CLEAN,
323	CLEANUP_HEAP_FREE,
324	CLEANUP_MISS_IVT_LOCK,
325	CLEANUP_MISS_IVT_DECREMENT,
326	CLEANUP_MISS_IVT_CLEAR,
327	CLEANUP_MISS_RSP,
328	CLEANUP_MISS_IXR_REQ,
329	CLEANUP_WAIT,
330	CLEANUP_SEND_CLACK
331	};
332
333	/* States of the ALLOC_DIR fsm */
334	enum alloc_dir_fsm_state_e
335	{
336	ALLOC_DIR_RESET,
337	ALLOC_DIR_READ,
338	ALLOC_DIR_WRITE,
339	ALLOC_DIR_CAS,
340	ALLOC_DIR_CLEANUP,
341	ALLOC_DIR_XRAM_RSP,
342	ALLOC_DIR_MULTI_ACK,
343	ALLOC_DIR_CONFIG
344	};
345
346	/* States of the ALLOC_TRT fsm */
347	enum alloc_trt_fsm_state_e
348	{
349	ALLOC_TRT_READ,
350	ALLOC_TRT_WRITE,
351	ALLOC_TRT_CAS,
352	ALLOC_TRT_XRAM_RSP,
353	ALLOC_TRT_IXR_RSP,
354	ALLOC_TRT_CLEANUP,
355	ALLOC_TRT_IXR_CMD,
356	ALLOC_TRT_CONFIG
357	};
358
359	/* States of the ALLOC_IVT fsm */
360	enum alloc_ivt_fsm_state_e
361	{
362	ALLOC_IVT_WRITE,
363	ALLOC_IVT_READ,
364	ALLOC_IVT_XRAM_RSP,
365	ALLOC_IVT_CLEANUP,
366	ALLOC_IVT_CAS,
367	ALLOC_IVT_CONFIG,
368	ALLOC_IVT_MULTI_ACK
369	};
370
371	/* States of the ALLOC_HEAP fsm */
372	enum alloc_heap_fsm_state_e
373	{
374	ALLOC_HEAP_RESET,
375	ALLOC_HEAP_READ,
376	ALLOC_HEAP_WRITE,
377	ALLOC_HEAP_CAS,
378	ALLOC_HEAP_CLEANUP,
379	ALLOC_HEAP_MULTI_ACK,
380	ALLOC_HEAP_XRAM_RSP,
381	ALLOC_HEAP_CONFIG
382	};
383
384	/* transaction type, pktid field */
385	enum transaction_type_e
386	{
387	// b3 unused
388	// b2 READ / NOT READ
389	// Si READ
390	// b1 DATA / INS
391	// b0 UNC / MISS
392	// Si NOT READ
393	// b1 accÃšs table llsc type SW / other
394	// b2 WRITE/CAS/LL/SC
395	TYPE_DATA_UNC = 0x0,
396	TYPE_READ_DATA_MISS = 0x1,
397	TYPE_READ_INS_UNC = 0x2,
398	TYPE_READ_INS_MISS = 0x3,
399	TYPE_WRITE = 0x4,
400	TYPE_CAS = 0x5,
401	TYPE_LL = 0x6,
402	TYPE_SC = 0x7
403	};
404
405	/* SC return values */
406	enum sc_status_type_e
407	{
408	SC_SUCCESS = 0x00000000,
409	SC_FAIL = 0x00000001
410	};
411
412	// debug variables
413	bool m_debug;
414	size_t m_debug_previous_valid;
415	size_t m_debug_previous_count;
416	bool m_debug_previous_dirty;
417	data_t * m_debug_previous_data;
418	data_t * m_debug_data;
419
420	// instrumentation counters
421	uint32_t m_cpt_cycles; // Counter of cycles
422
423	// Counters
424	// (*) = Counters accessible in software
425	uint32_t m_cpt_reset_count; // Last cycle at which counters have been reset
426
427	uint32_t m_cpt_read_local; // Number of local READ transactions (*)
428	uint32_t m_cpt_read_remote; // number of remote READ transactions (*)
429	uint32_t m_cpt_read_cost; // Number of (flits * distance) for READs (*)
430
431	uint32_t m_cpt_write_local; // Number of local WRITE transactions
432	uint32_t m_cpt_write_remote; // number of remote WRITE transactions
433	uint32_t m_cpt_write_flits_local; // number of flits for local WRITEs (*)
434	uint32_t m_cpt_write_flits_remote; // number of flits for remote WRITEs (*)
435	uint32_t m_cpt_write_cost; // Number of (flits * distance) for WRITEs (*)
436
437	uint32_t m_cpt_ll_local; // Number of local LL transactions (*)
438	uint32_t m_cpt_ll_remote; // number of remote LL transactions (*)
439	uint32_t m_cpt_ll_cost; // Number of (flits * distance) for LLs (*)
440
441	uint32_t m_cpt_sc_local; // Number of local SC transactions (*)
442	uint32_t m_cpt_sc_remote; // number of remote SC transactions (*)
443	uint32_t m_cpt_sc_cost; // Number of (flits * distance) for SCs (*)
444
445	uint32_t m_cpt_cas_local; // Number of local SC transactions (*)
446	uint32_t m_cpt_cas_remote; // number of remote SC transactions (*)
447	uint32_t m_cpt_cas_cost; // Number of (flits * distance) for SCs (*)
448
449	uint32_t m_cpt_minval; // Number of requests causing M_INV (*)
450	uint32_t m_cpt_minval_local; // Number of local M_INV transactions (*)
451	uint32_t m_cpt_minval_remote; // Number of remote M_INV transactions (*)
452	uint32_t m_cpt_minval_cost; // Number of (flits * distance) for M_INV (*)
453
454	uint32_t m_cpt_binval; // Number of BROADCAST INVAL (*)
455	uint32_t m_cpt_write_broadcast;// Number of BROADCAST INVAL caused by write
456	uint32_t m_cpt_getm_broadcast; // Number of BROADCAST INVAL caused by getm
457
458	uint32_t m_cpt_cleanup_local; // Number of local CLEANUP transactions (*)
459	uint32_t m_cpt_cleanup_remote; // Number of remote CLEANUP transactions (*)
460	uint32_t m_cpt_cleanup_cost; // Number of (flits * distance) for CLEANUPs (*)
461	uint32_t m_cpt_cleanup_data_local; //
462	uint32_t m_cpt_cleanup_data_remote; //
463	uint32_t m_cpt_cleanup_data_cost; //
464
465	uint32_t m_cpt_read_miss; // Number of MISS READ
466	uint32_t m_cpt_write_miss; // Number of MISS WRITE
467	uint32_t m_cpt_write_dirty; // Cumulated length for WRITE transactions
468	uint32_t m_cpt_getm_miss; // Number of getm miss
469
470	uint32_t m_cpt_getm_local; // Number of local getm miss transactions
471	uint32_t m_cpt_getm_remote; // number of remote getm miss transactions
472	uint32_t m_cpt_getm_cost; // Number of (flits * distance) for getm
473
474	uint32_t m_cpt_inval_ro_local; // Number of local INVAL RO (*)
475	uint32_t m_cpt_inval_ro_remote; // Number of local INVAL RO (*)
476	uint32_t m_cpt_inval_ro_cost; // Cost for INVAL RO (*)
477
478	uint32_t m_cpt_trt_rb; // Read blocked by a hit in trt
479	uint32_t m_cpt_trt_full; // Transaction blocked due to a full trt
480	uint32_t m_cpt_put;
481	uint32_t m_cpt_get;
482
483	uint32_t m_cpt_heap_unused; // NB cycles HEAP LOCK unused
484	uint32_t m_cpt_slot_inval;
485
486	protected:
487
488	SC_HAS_PROCESS(VciMemCache);
489
490	public:
491	sc_in<bool> p_clk;
492	sc_in<bool> p_resetn;
493	sc_in<bool> p_irq;
494	soclib::caba::VciTarget<vci_param_int> p_vci_tgt;
495	soclib::caba::VciInitiator<vci_param_ext> p_vci_ixr;
496	soclib::caba::DspinInput<dspin_in_width> p_dspin_p2m;
497	soclib::caba::DspinOutput<dspin_out_width> p_dspin_m2p;
498	soclib::caba::DspinOutput<dspin_out_width> p_dspin_clack;
499
500	#if MONITOR_MEMCACHE_FSM == 1
501	sc_out<int> p_read_fsm;
502	sc_out<int> p_write_fsm;
503	sc_out<int> p_xram_rsp_fsm;
504	sc_out<int> p_cas_fsm;
505	sc_out<int> p_cleanup_fsm;
506	sc_out<int> p_config_fsm;
507	sc_out<int> p_alloc_heap_fsm;
508	sc_out<int> p_alloc_dir_fsm;
509	sc_out<int> p_alloc_trt_fsm;
510	sc_out<int> p_alloc_upt_fsm;
511	sc_out<int> p_alloc_ivt_fsm;
512	sc_out<int> p_tgt_cmd_fsm;
513	sc_out<int> p_tgt_rsp_fsm;
514	sc_out<int> p_ixr_cmd_fsm;
515	sc_out<int> p_ixr_rsp_fsm;
516	sc_out<int> p_cc_send_fsm;
517	sc_out<int> p_cc_receive_fsm;
518	sc_out<int> p_multi_ack_fsm;
519	#endif
520
521	VciMemCache(
522	sc_module_name name, // Instance Name
523	const soclib::common::MappingTable &mtp, // Mapping table INT network
524	const soclib::common::MappingTable &mtx, // Mapping table RAM network
525	const soclib::common::IntTab &srcid_x, // global index RAM network
526	const soclib::common::IntTab &tgtid_d, // global index INT network
527	const size_t x_width, // X width in platform
528	const size_t y_width, // Y width in platform
529	const size_t nways, // Number of ways per set
530	const size_t nsets, // Number of sets
531	const size_t nwords, // Number of words per line
532	const size_t max_copies, // max number of copies
533	const size_t heap_size=HEAP_ENTRIES,
534	const size_t trt_lines=TRT_ENTRIES,
535	const size_t upt_lines=UPT_ENTRIES,
536	const size_t ivt_lines=IVT_ENTRIES,
537	const size_t debug_start_cycle=0,
538	const bool debug_ok=false );
539
540	~VciMemCache();
541
542	void reset_counters();
543	void print_stats(bool activity_counters, bool stats);
544	void print_trace( size_t detailled = 0 );
545	void cache_monitor(addr_t addr);
546	void start_monitor(addr_t addr, addr_t length);
547	void stop_monitor();
548
549	private:
550
551	void transition();
552	void genMoore();
553	void check_monitor(addr_t addr, data_t data, bool read);
554	uint32_t req_distance(uint32_t req_srcid);
555	bool is_local_req(uint32_t req_srcid);
556	int read_instrumentation(uint32_t regr, uint32_t & rdata);
557
558	// Component attributes
559	std::list<soclib::common::Segment> m_seglist; // segments allocated
560	size_t m_nseg; // number of segments
561	soclib::common::Segment **m_seg; // array of segments pointers
562	size_t m_seg_config; // config segment index
563	const size_t m_srcid_x; // global index on RAM network
564	const size_t m_initiators; // Number of initiators
565	const size_t m_heap_size; // Size of the heap
566	const size_t m_ways; // Number of ways in a set
567	const size_t m_sets; // Number of cache sets
568	const size_t m_words; // Number of words in a line
569	size_t m_x_self; // X self coordinate
570	size_t m_y_self; // Y self coordinate
571	const size_t m_x_width; // number of x bits in platform
572	const size_t m_y_width; // number of y bits in platform
573	size_t m_debug_start_cycle;
574	bool m_debug_ok;
575	uint32_t m_trt_lines;
576	TransactionTab m_trt; // xram transaction table
577	uint32_t m_upt_lines;
578	UpdateTab m_upt; // pending update
579	UpdateTab m_ivt; // pending invalidate
580	CacheDirectory m_cache_directory; // data cache directory
581	CacheData m_cache_data; // data array[set][way][word]
582	HeapDirectory m_heap; // heap for copies
583	size_t m_max_copies; // max number of copies in heap
584	GenericLLSCGlobalTable
585	< 32 , // number of slots
586	4096, // number of processors in the system
587	8000, // registration life (# of LL operations)
588	addr_t > m_llsc_table; // ll/sc registration table
589
590	// adress masks
591	const soclib::common::AddressMaskingTable<addr_t> m_x;
592	const soclib::common::AddressMaskingTable<addr_t> m_y;
593	const soclib::common::AddressMaskingTable<addr_t> m_z;
594	const soclib::common::AddressMaskingTable<addr_t> m_nline;
595
596	// broadcast address
597	uint32_t m_broadcast_boundaries;
598
599	// configuration interface constants
600	const uint32_t m_config_addr_mask;
601	const uint32_t m_config_regr_width;
602	const uint32_t m_config_func_width;
603	const uint32_t m_config_regr_idx_mask;
604	const uint32_t m_config_func_idx_mask;
605
606	// Fifo between TGT_CMD fsm and READ fsm
607	GenericFifo<addr_t> m_cmd_read_addr_fifo;
608	GenericFifo<size_t> m_cmd_read_length_fifo;
609	GenericFifo<size_t> m_cmd_read_srcid_fifo;
610	GenericFifo<size_t> m_cmd_read_trdid_fifo;
611	GenericFifo<size_t> m_cmd_read_pktid_fifo;
612
613	// Fifo between TGT_CMD fsm and WRITE fsm
614	GenericFifo<addr_t> m_cmd_write_addr_fifo;
615	GenericFifo<bool> m_cmd_write_eop_fifo;
616	GenericFifo<size_t> m_cmd_write_srcid_fifo;
617	GenericFifo<size_t> m_cmd_write_trdid_fifo;
618	GenericFifo<size_t> m_cmd_write_pktid_fifo;
619	GenericFifo<data_t> m_cmd_write_data_fifo;
620	GenericFifo<be_t> m_cmd_write_be_fifo;
621
622	// Fifo between TGT_CMD fsm and CAS fsm
623	GenericFifo<addr_t> m_cmd_cas_addr_fifo;
624	GenericFifo<bool> m_cmd_cas_eop_fifo;
625	GenericFifo<size_t> m_cmd_cas_srcid_fifo;
626	GenericFifo<size_t> m_cmd_cas_trdid_fifo;
627	GenericFifo<size_t> m_cmd_cas_pktid_fifo;
628	GenericFifo<data_t> m_cmd_cas_wdata_fifo;
629
630	// Fifo between CC_RECEIVE fsm and CLEANUP fsm
631	GenericFifo<uint64_t> m_cc_receive_to_cleanup_fifo;
632
633	// Fifo between CC_RECEIVE fsm and MULTI_ACK fsm
634	GenericFifo<uint64_t> m_cc_receive_to_multi_ack_fifo;
635
636	// Buffer between TGT_CMD fsm and TGT_RSP fsm
637	// (segmentation violation response request)
638	sc_signal<bool> r_tgt_cmd_to_tgt_rsp_req;
639
640	sc_signal<uint32_t> r_tgt_cmd_to_tgt_rsp_rdata;
641	sc_signal<size_t> r_tgt_cmd_to_tgt_rsp_error;
642	sc_signal<size_t> r_tgt_cmd_to_tgt_rsp_srcid;
643	sc_signal<size_t> r_tgt_cmd_to_tgt_rsp_trdid;
644	sc_signal<size_t> r_tgt_cmd_to_tgt_rsp_pktid;
645
646	sc_signal<addr_t> r_tgt_cmd_config_addr;
647	sc_signal<size_t> r_tgt_cmd_config_cmd;
648
649	//////////////////////////////////////////////////
650	// Registers controlled by the TGT_CMD fsm
651	//////////////////////////////////////////////////
652
653	sc_signal<int> r_tgt_cmd_fsm;
654
655	///////////////////////////////////////////////////////
656	// Registers controlled by the CONFIG fsm
657	///////////////////////////////////////////////////////
658
659	sc_signal<int> r_config_fsm; // FSM state
660	sc_signal<bool> r_config_lock; // lock protecting exclusive access
661	sc_signal<int> r_config_cmd; // config request type
662	sc_signal<addr_t> r_config_address; // target buffer physical address
663	sc_signal<size_t> r_config_srcid; // config request srcid
664	sc_signal<size_t> r_config_trdid; // config request trdid
665	sc_signal<size_t> r_config_pktid; // config request pktid
666	sc_signal<size_t> r_config_cmd_lines; // number of lines to be handled
667	sc_signal<size_t> r_config_rsp_lines; // number of lines not completed
668	sc_signal<size_t> r_config_dir_way; // DIR: selected way
669	sc_signal<bool> r_config_dir_lock; // DIR: locked entry
670	sc_signal<size_t> r_config_dir_count; // DIR: number of copies
671	sc_signal<bool> r_config_dir_is_cnt; // DIR: counter mode (broadcast)
672	sc_signal<size_t> r_config_dir_copy_srcid; // DIR: first copy SRCID
673	sc_signal<bool> r_config_dir_copy_inst; // DIR: first copy L1 type
674	sc_signal<size_t> r_config_dir_ptr; // DIR: index of next copy in HEAP
675	sc_signal<size_t> r_config_dir_state; // DIR: dir state
676	sc_signal<size_t> r_config_heap_next; // current pointer to scan HEAP
677	sc_signal<size_t> r_config_trt_index; // selected entry in TRT
678	sc_signal<size_t> r_config_ivt_index; // selected entry in IVT
679
680	// Buffer between CONFIG fsm and IXR_CMD fsm
681	sc_signal<bool> r_config_to_ixr_cmd_req; // valid request
682	sc_signal<size_t> r_config_to_ixr_cmd_index; // TRT index
683
684	// Buffer between CONFIG fsm and TGT_RSP fsm (send a done response to L1 cache)
685	sc_signal<bool> r_config_to_tgt_rsp_req; // valid request
686	sc_signal<bool> r_config_to_tgt_rsp_error; // error response
687	sc_signal<size_t> r_config_to_tgt_rsp_srcid; // Transaction srcid
688	sc_signal<size_t> r_config_to_tgt_rsp_trdid; // Transaction trdid
689	sc_signal<size_t> r_config_to_tgt_rsp_pktid; // Transaction pktid
690
691	// Buffer between CONFIG fsm and CC_SEND fsm (multi-inval / broadcast-inval)
692	sc_signal<bool> r_config_to_cc_send_multi_req; // multi-inval request
693	sc_signal<bool> r_config_to_cc_send_brdcast_req; // broadcast-inval request
694	sc_signal<addr_t> r_config_to_cc_send_nline; // line index
695	sc_signal<size_t> r_config_to_cc_send_trdid; // UPT index
696	GenericFifo<bool> m_config_to_cc_send_inst_fifo; // fifo for the L1 type
697	GenericFifo<size_t> m_config_to_cc_send_srcid_fifo; // fifo for owners srcid
698
699	///////////////////////////////////////////////////////
700	// Registers controlled by the READ fsm
701	///////////////////////////////////////////////////////
702
703	sc_signal<int> r_read_fsm; // FSM state
704	sc_signal<size_t> r_read_copy; // Srcid of the first copy
705	sc_signal<size_t> r_read_copy_cache; // Srcid of the first copy
706	sc_signal<bool> r_read_copy_inst; // Type of the first copy
707	sc_signal<tag_t> r_read_tag; // cache line tag (in directory)
708	sc_signal<bool> r_read_is_cnt; // is_cnt bit (in directory)
709	sc_signal<bool> r_read_lock; // lock bit (in directory)
710	sc_signal<bool> r_read_dirty; // dirty bit (in directory)
711	sc_signal<size_t> r_read_count; // number of copies
712	sc_signal<size_t> r_read_ptr; // pointer to the heap
713	sc_signal<data_t> * r_read_data; // data (one cache line)
714	sc_signal<size_t> r_read_way; // associative way (in cache)
715	sc_signal<size_t> r_read_trt_index; // Transaction Table index
716	sc_signal<size_t> r_read_next_ptr; // Next entry to point to
717	sc_signal<bool> r_read_last_free; // Last free entry
718	sc_signal<addr_t> r_read_ll_key; // LL key from llsc_global_table
719
720
721
722	sc_signal<bool> r_read_ll_done;
723	sc_signal<bool> r_read_need_block;
724	sc_signal<size_t> r_read_state;
725	// Buffer between READ fsm and IXR_CMD fsm
726	sc_signal<bool> r_read_to_ixr_cmd_req; // valid request
727	sc_signal<size_t> r_read_to_ixr_cmd_index; // TRT index
728
729	// Buffer between READ fsm and TGT_RSP fsm (send a hit read response to L1 cache)
730	sc_signal<bool> r_read_to_tgt_rsp_req; // valid request
731	sc_signal<size_t> r_read_to_tgt_rsp_srcid; // Transaction srcid
732	sc_signal<size_t> r_read_to_tgt_rsp_trdid; // Transaction trdid
733	sc_signal<size_t> r_read_to_tgt_rsp_pktid; // Transaction pktid
734	sc_signal<data_t> * r_read_to_tgt_rsp_data; // data (one cache line)
735	sc_signal<size_t> r_read_to_tgt_rsp_word; // first word of the response
736	sc_signal<size_t> r_read_to_tgt_rsp_length; // length of the response
737	sc_signal<addr_t> r_read_to_tgt_rsp_ll_key; // LL key from llsc_global_table
738
739	//RWT: Buffer between READ fsm and CC_SEND fsm (send inval)
740	sc_signal<bool> r_read_to_cc_send_req;
741	sc_signal<size_t> r_read_to_cc_send_dest;
742	sc_signal<addr_t> r_read_to_cc_send_nline;
743	sc_signal<bool> r_read_to_cc_send_inst;
744	sc_signal<size_t> r_read_to_cc_send_srcid;
745	sc_signal<size_t> r_read_to_cc_send_ivt_index;
746	sc_signal<bool> r_read_to_cc_send_multi_req; // multi inval
747	sc_signal<bool> r_read_to_cc_send_brdcast_req; // bd inval
748	sc_signal<bool> r_read_to_cc_send_type; //cc inval or cc updt
749	sc_signal<bool> r_read_to_cc_send_is_shared; //line is or not shared
750
751	//RWT: Buffer between READ fsm and CLEANUP fsm (wait for the data coming from L1 cache)
752	sc_signal<bool> r_read_to_cleanup_req; // valid request
753	sc_signal<addr_t> r_read_to_cleanup_nline; // cache line index
754	sc_signal<size_t> r_read_to_cleanup_srcid;
755	sc_signal<size_t> r_read_to_cleanup_length;
756	sc_signal<size_t> r_read_to_cleanup_first_word;
757	sc_signal<bool> r_read_to_cleanup_cached_read;
758	sc_signal<bool> r_read_to_cleanup_is_ll;
759	sc_signal<addr_t> r_read_to_cleanup_addr;
760	sc_signal<addr_t> r_read_to_cleanup_ll_key;
761
762	sc_signal<bool> r_read_to_multi_ack_req; // valid request
763	sc_signal<addr_t> r_read_to_multi_ack_nline; // cache line index
764	sc_signal<size_t> r_read_to_multi_ack_first_word;
765	sc_signal<bool> r_read_to_multi_ack_length;
766	sc_signal<addr_t> r_read_to_multi_ack_ll_key;
767
768
769	GenericFifo<bool> m_read_to_cc_send_inst_fifo; // fifo for the L1 type
770	GenericFifo<size_t> m_read_to_cc_send_srcid_fifo; // fifo for owners srcid
771
772
773
774	sc_signal<bool> r_multi_ack_need_data; // cc_updt rsp with data
775	sc_signal<size_t> r_multi_ack_data_index;
776	sc_signal<size_t> r_multi_ack_ivt_index;
777	sc_signal<size_t> r_multi_ack_set;
778	sc_signal<size_t> r_multi_ack_way;
779	sc_signal<size_t> r_multi_ack_count;
780	sc_signal<bool> r_multi_ack_rsp;
781	sc_signal<bool> r_multi_ack_rsp_shared;
782
783	sc_signal<size_t> r_multi_ack_copy; // Srcid of the first copy
784	sc_signal<bool> r_multi_ack_copy_inst; // Type of the first copy
785	sc_signal<tag_t> r_multi_ack_tag; // cache line tag (in directory)
786	sc_signal<bool> r_multi_ack_lock; // lock bit (in directory)
787	sc_signal<bool> r_multi_ack_dirty; // dirty bit (in directory)
788	sc_signal<data_t> * r_multi_ack_data; // data (one cache line)
789	sc_signal<size_t> r_multi_ack_to_tgt_rsp_word;
790	sc_signal<size_t> r_multi_ack_to_tgt_rsp_length;
791	sc_signal<size_t> r_multi_ack_to_tgt_ll_key;
792
793	sc_signal<bool> r_multi_ack_last_free;
794	sc_signal<bool> r_multi_ack_miss_updt;
795	sc_signal<size_t> r_multi_ack_next_ptr;
796
797	sc_signal<bool> r_read_shared; // State of the cache slot after transaction
798
799
800	sc_signal<data_t> * r_debug_data; // data (one cache line)
801	///////////////////////////////////////////////////////////////
802	// Registers controlled by the WRITE fsm
803	///////////////////////////////////////////////////////////////
804
805	sc_signal<int> r_write_fsm; // FSM state
806	sc_signal<size_t> r_write_state;
807	sc_signal<addr_t> r_write_address; // first word address
808	sc_signal<size_t> r_write_word_index; // first word index in line
809	sc_signal<size_t> r_write_word_count; // number of words in line
810	sc_signal<size_t> r_write_srcid; // transaction srcid
811	sc_signal<size_t> r_write_trdid; // transaction trdid
812	sc_signal<size_t> r_write_pktid; // transaction pktid
813	sc_signal<data_t> * r_write_data; // data (one cache line)
814	sc_signal<be_t> * r_write_be; // one byte enable per word
815	sc_signal<bool> r_write_byte; // (BE != 0X0) and (BE != 0xF)
816	sc_signal<bool> r_write_is_cnt; // is_cnt bit (in directory)
817	sc_signal<bool> r_write_lock; // lock bit (in directory)
818	sc_signal<tag_t> r_write_tag; // cache line tag (in directory)
819	sc_signal<size_t> r_write_copy; // first owner of the line
820	sc_signal<size_t> r_write_copy_cache; // first owner of the line
821	sc_signal<bool> r_write_copy_inst; // is this owner a ICache ?
822	sc_signal<size_t> r_write_count; // number of copies
823	sc_signal<size_t> r_write_ptr; // pointer to the heap
824	sc_signal<size_t> r_write_next_ptr; // next pointer to the heap
825	sc_signal<bool> r_write_to_dec; // need to decrement update counter
826	sc_signal<size_t> r_write_way; // way of the line
827	sc_signal<size_t> r_write_trt_index; // index in Transaction Table
828	sc_signal<size_t> r_write_upt_index; // index in Update Table
829	sc_signal<bool> r_write_sc_fail; // sc command failed
830	sc_signal<data_t> r_write_sc_key; // sc command key
831	sc_signal<bool> r_write_bc_data_we; // Write enable for data buffer
832	sc_signal<bool> r_write_inval_trt_send;
833	sc_signal<bool> r_write_data_we;
834
835	// Buffer between WRITE fsm and TGT_RSP fsm (acknowledge a write command from L1)
836	sc_signal<bool> r_write_to_tgt_rsp_req; // valid request
837	sc_signal<size_t> r_write_to_tgt_rsp_srcid; // transaction srcid
838	sc_signal<size_t> r_write_to_tgt_rsp_trdid; // transaction trdid
839	sc_signal<size_t> r_write_to_tgt_rsp_pktid; // transaction pktid
840	sc_signal<bool> r_write_to_tgt_rsp_sc_fail; // sc command failed
841
842	// Buffer between WRITE fsm and IXR_CMD fsm
843	sc_signal<bool> r_write_to_ixr_cmd_req; // valid request
844	sc_signal<size_t> r_write_to_ixr_cmd_index; // TRT index
845
846	// Buffer between WRITE fsm and CC_SEND fsm (Update/Invalidate L1 caches)
847	sc_signal<bool> r_write_to_cc_send_multi_req; // valid multicast request
848	sc_signal<bool> r_write_to_cc_send_brdcast_req; // valid brdcast request
849	sc_signal<addr_t> r_write_to_cc_send_nline; // cache line index
850	sc_signal<size_t> r_write_to_cc_send_trdid; // index in Update Table
851	sc_signal<data_t> * r_write_to_cleanup_data; // data (one cache line)
852	sc_signal<be_t> * r_write_to_cleanup_be; // word enable
853	sc_signal<size_t> r_write_to_cc_send_count; // number of words in line
854	sc_signal<size_t> r_write_to_cc_send_index; // index of first word in line
855	GenericFifo<bool> m_write_to_cc_send_inst_fifo; // fifo for the L1 type
856	GenericFifo<size_t> m_write_to_cc_send_srcid_fifo; // fifo for srcids
857
858	// Buffer between WRITE fsm and MULTI_ACK fsm (Decrement UPT entry)
859	sc_signal<bool> r_write_to_multi_ack_req; // valid request
860	sc_signal<size_t> r_write_to_multi_ack_upt_index; // index in update table
861
862	// RWT: Buffer between WRITE fsm and CLEANUP fsm (change slot state)
863	sc_signal<bool> r_write_to_cleanup_req; // valid request
864	sc_signal<addr_t> r_write_to_cleanup_nline; // cache line index
865
866	// RWT
867	sc_signal<bool> r_write_coherent; // cache slot state after transaction
868
869	//Buffer between WRITE fsm and CC_SEND fsm (INVAL for RWT)
870	sc_signal<bool> r_write_to_cc_send_req;
871	sc_signal<size_t> r_write_to_cc_send_dest;
872
873
874	/////////////////////////////////////////////////////////
875	// Registers controlled by MULTI_ACK fsm
876	//////////////////////////////////////////////////////////
877
878	sc_signal<int> r_multi_ack_fsm; // FSM state
879	sc_signal<size_t> r_multi_ack_upt_index; // index in the Update Table
880	sc_signal<size_t> r_multi_ack_srcid; // pending write srcid
881	sc_signal<size_t> r_multi_ack_trdid; // pending write trdid
882	sc_signal<size_t> r_multi_ack_pktid; // pending write pktid
883	sc_signal<addr_t> r_multi_ack_nline; // pending write nline
884
885	// Buffer between MULTI_ACK fsm and TGT_RSP fsm (complete write/update transaction)
886	sc_signal<bool> r_multi_ack_to_tgt_rsp_req; // valid request
887	sc_signal<size_t> r_multi_ack_to_tgt_rsp_srcid; // Transaction srcid
888	sc_signal<size_t> r_multi_ack_to_tgt_rsp_trdid; // Transaction trdid
889	sc_signal<size_t> r_multi_ack_to_tgt_rsp_pktid; // Transaction pktid
890
891	///////////////////////////////////////////////////////
892	// Registers controlled by CLEANUP fsm
893	///////////////////////////////////////////////////////
894
895	sc_signal<int> r_cleanup_fsm; // FSM state
896	sc_signal<size_t> r_cleanup_srcid; // transaction srcid
897	sc_signal<bool> r_cleanup_inst; // Instruction or Data ?
898	sc_signal<size_t> r_cleanup_way_index; // L1 Cache Way index
899	sc_signal<addr_t> r_cleanup_nline; // cache line index
900
901
902	sc_signal<copy_t> r_cleanup_copy; // first copy
903	sc_signal<copy_t> r_cleanup_copy_cache; // first copy
904	sc_signal<size_t> r_cleanup_copy_inst; // type of the first copy
905	sc_signal<copy_t> r_cleanup_count; // number of copies
906	sc_signal<size_t> r_cleanup_ptr; // pointer to the heap
907	sc_signal<size_t> r_cleanup_prev_ptr; // previous pointer to the heap
908	sc_signal<size_t> r_cleanup_prev_srcid; // srcid of previous heap entry
909	sc_signal<size_t> r_cleanup_prev_cache_id; // srcid of previous heap entry
910	sc_signal<bool> r_cleanup_prev_inst; // inst bit of previous heap entry
911	sc_signal<size_t> r_cleanup_next_ptr; // next pointer to the heap
912	sc_signal<tag_t> r_cleanup_tag; // cache line tag (in directory)
913	sc_signal<bool> r_cleanup_is_cnt; // inst bit (in directory)
914	sc_signal<bool> r_cleanup_lock; // lock bit (in directory)
915	sc_signal<bool> r_cleanup_dirty; // dirty bit (in directory)
916	sc_signal<size_t> r_cleanup_way; // associative way (in cache)
917
918	sc_signal<size_t> r_cleanup_locked_srcid; // srcid of write rsp
919	sc_signal<size_t> r_cleanup_locked_trdid; // trdid of write rsp
920	sc_signal<size_t> r_cleanup_locked_pktid; // pktid of write rsp
921	sc_signal<size_t> r_cleanup_locked_index; // ivt index
922	sc_signal<bool> r_cleanup_locked_is_updt;
923	sc_signal<bool> r_cleanup_locked_is_changed;
924	sc_signal<bool> r_cleanup_locked_is_read;
925
926	sc_signal<size_t> r_cleanup_miss_srcid; // srcid of write rsp
927	sc_signal<size_t> r_cleanup_miss_trdid; // trdid of write rsp
928	sc_signal<size_t> r_cleanup_miss_pktid; // pktid of write rsp
929	sc_signal<size_t> r_cleanup_miss_index; // ivt index
930	sc_signal<bool> r_cleanup_miss_need_rsp; // write response required
931	sc_signal<bool> r_cleanup_miss_need_ack; // config acknowledge required
932
933
934	// Buffer between CLEANUP fsm and TGT_RSP fsm (acknowledge a write command from L1)
935	sc_signal<bool> r_cleanup_to_tgt_rsp_req; // valid request
936	sc_signal<size_t> r_cleanup_to_tgt_rsp_srcid; // transaction srcid
937	sc_signal<size_t> r_cleanup_to_tgt_rsp_trdid; // transaction trdid
938	sc_signal<size_t> r_cleanup_to_tgt_rsp_pktid; // transaction pktid
939	sc_signal<addr_t> r_cleanup_to_tgt_rsp_ll_key;
940	sc_signal<addr_t> r_cleanup_to_tgt_rsp_nline;
941
942	sc_signal<bool> r_cleanup_to_tgt_rsp_type;
943	sc_signal<data_t> * r_cleanup_to_tgt_rsp_data;
944	sc_signal<size_t> r_cleanup_to_tgt_rsp_length;
945	sc_signal<size_t> r_cleanup_to_tgt_rsp_first_word;
946
947	sc_signal<data_t> * r_multi_ack_to_tgt_rsp_data;
948	///////////////////////////////////////////////////////
949	// Registers controlled by CAS fsm
950	///////////////////////////////////////////////////////
951
952	sc_signal<int> r_cas_fsm; // FSM state
953	sc_signal<data_t> r_cas_wdata; // write data word
954	sc_signal<data_t> * r_cas_rdata; // read data word
955	sc_signal<uint32_t> r_cas_lfsr; // lfsr for random introducing
956	sc_signal<size_t> r_cas_cpt; // size of command
957	sc_signal<copy_t> r_cas_copy; // Srcid of the first copy
958	sc_signal<copy_t> r_cas_copy_cache; // Srcid of the first copy
959	sc_signal<bool> r_cas_copy_inst; // Type of the first copy
960	sc_signal<size_t> r_cas_count; // number of copies
961	sc_signal<size_t> r_cas_ptr; // pointer to the heap
962	sc_signal<size_t> r_cas_next_ptr; // next pointer to the heap
963	sc_signal<bool> r_cas_is_cnt; // is_cnt bit (in directory)
964	sc_signal<bool> r_cas_dirty; // dirty bit (in directory)
965	sc_signal<size_t> r_cas_way; // way in directory
966	sc_signal<size_t> r_cas_set; // set in directory
967	sc_signal<data_t> r_cas_tag; // cache line tag (in directory)
968	sc_signal<size_t> r_cas_trt_index; // Transaction Table index
969	sc_signal<size_t> r_cas_ivt_index; // Update Table index
970	sc_signal<data_t> * r_cas_data; // cache line data
971
972	sc_signal<bool> r_cas_coherent;
973	sc_signal<size_t> r_cas_state;
974
975	// Buffer between CAS fsm and IXR_CMD fsm (XRAM write)
976	sc_signal<bool> r_cas_to_ixr_cmd_req; // valid request
977	sc_signal<size_t> r_cas_to_ixr_cmd_index; // TRT index
978
979	// Buffer between CAS fsm and TGT_RSP fsm
980	sc_signal<bool> r_cas_to_tgt_rsp_req; // valid request
981	sc_signal<data_t> r_cas_to_tgt_rsp_data; // read data word
982	sc_signal<size_t> r_cas_to_tgt_rsp_srcid; // Transaction srcid
983	sc_signal<size_t> r_cas_to_tgt_rsp_trdid; // Transaction trdid
984	sc_signal<size_t> r_cas_to_tgt_rsp_pktid; // Transaction pktid
985
986	// Buffer between CAS fsm and CC_SEND fsm (Update/Invalidate L1 caches)
987	sc_signal<bool> r_cas_to_cc_send_multi_req; // valid request
988	sc_signal<bool> r_cas_to_cc_send_brdcast_req; // brdcast request
989	sc_signal<addr_t> r_cas_to_cc_send_nline; // cache line index
990	sc_signal<size_t> r_cas_to_cc_send_trdid; // index in Update Table
991	sc_signal<data_t> r_cas_to_cc_send_wdata; // data (one word)
992	sc_signal<bool> r_cas_to_cc_send_is_long; // it is a 64 bits CAS
993	sc_signal<data_t> r_cas_to_cc_send_wdata_high; // data high (one word)
994	sc_signal<size_t> r_cas_to_cc_send_index; // index of the word in line
995	GenericFifo<bool> m_cas_to_cc_send_inst_fifo; // fifo for the L1 type
996	GenericFifo<size_t> m_cas_to_cc_send_srcid_fifo; // fifo for srcids
997
998	sc_signal<bool> r_cas_to_cleanup_req;
999	sc_signal<addr_t> r_cas_to_cleanup_nline;
1000	////////////////////////////////////////////////////
1001	// Registers controlled by the IXR_RSP fsm
1002	////////////////////////////////////////////////////
1003
1004	sc_signal<int> r_ixr_rsp_fsm; // FSM state
1005	sc_signal<size_t> r_ixr_rsp_trt_index; // TRT entry index
1006	sc_signal<size_t> r_ixr_rsp_cpt; // word counter
1007
1008	// Buffer between IXR_RSP fsm and CONFIG fsm (response from the XRAM)
1009	sc_signal<bool> r_ixr_rsp_to_config_ack; // one single bit
1010
1011	// Buffer between IXR_RSP fsm and XRAM_RSP fsm (response from the XRAM)
1012	sc_signal<bool> * r_ixr_rsp_to_xram_rsp_rok; // one bit per TRT entry
1013
1014	////////////////////////////////////////////////////
1015	// Registers controlled by the XRAM_RSP fsm
1016	////////////////////////////////////////////////////
1017
1018	sc_signal<int> r_xram_rsp_fsm; // FSM state
1019	sc_signal<size_t> r_xram_rsp_trt_index; // TRT entry index
1020	TransactionTabEntry r_xram_rsp_trt_buf; // TRT entry local buffer
1021	sc_signal<bool> r_xram_rsp_victim_inval; // victim line invalidate
1022	sc_signal<bool> r_xram_rsp_victim_is_cnt; // victim line inst bit
1023	sc_signal<bool> r_xram_rsp_victim_dirty; // victim line dirty bit
1024	sc_signal<size_t> r_xram_rsp_victim_way; // victim line way
1025	sc_signal<size_t> r_xram_rsp_victim_set; // victim line set
1026	sc_signal<addr_t> r_xram_rsp_victim_nline; // victim line index
1027	sc_signal<copy_t> r_xram_rsp_victim_copy; // victim line first copy
1028	sc_signal<copy_t> r_xram_rsp_victim_copy_cache; // victim line first copy
1029	sc_signal<bool> r_xram_rsp_victim_copy_inst; // victim line type of first copy
1030	sc_signal<size_t> r_xram_rsp_victim_count; // victim line number of copies
1031	sc_signal<size_t> r_xram_rsp_victim_ptr; // victim line pointer to the heap
1032	sc_signal<data_t> * r_xram_rsp_victim_data; // victim line data
1033	sc_signal<size_t> r_xram_rsp_ivt_index; // IVT entry index
1034	sc_signal<size_t> r_xram_rsp_next_ptr; // Next pointer to the heap
1035	sc_signal<size_t> r_xram_rsp_victim_state;
1036
1037	// Buffer between XRAM_RSP fsm and TGT_RSP fsm (response to L1 cache)
1038	sc_signal<bool> r_xram_rsp_to_tgt_rsp_req; // Valid request
1039	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_srcid; // Transaction srcid
1040	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_trdid; // Transaction trdid
1041	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_pktid; // Transaction pktid
1042	sc_signal<data_t> * r_xram_rsp_to_tgt_rsp_data; // data (one cache line)
1043	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_word; // first word index
1044	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_length; // length of the response
1045	sc_signal<bool> r_xram_rsp_to_tgt_rsp_rerror; // send error to requester
1046	sc_signal<addr_t> r_xram_rsp_to_tgt_rsp_ll_key; // LL key from llsc_global_table
1047
1048	// Buffer between XRAM_RSP fsm and CC_SEND fsm (Inval L1 Caches)
1049	sc_signal<bool> r_xram_rsp_to_cc_send_multi_req; // Valid request
1050	sc_signal<bool> r_xram_rsp_to_cc_send_brdcast_req; // Broadcast request
1051	sc_signal<addr_t> r_xram_rsp_to_cc_send_nline; // cache line index;
1052	sc_signal<size_t> r_xram_rsp_to_cc_send_trdid; // index of UPT entry
1053	GenericFifo<bool> m_xram_rsp_to_cc_send_inst_fifo; // fifo for the L1 type
1054	GenericFifo<size_t> m_xram_rsp_to_cc_send_srcid_fifo; // fifo for srcids
1055
1056	// Buffer between XRAM_RSP fsm and IXR_CMD fsm
1057	sc_signal<bool> r_xram_rsp_to_ixr_cmd_req; // Valid request
1058	sc_signal<size_t> r_xram_rsp_to_ixr_cmd_index; // TRT index
1059
1060	//RWT
1061	sc_signal<bool> r_xram_rsp_victim_coherent; // victim's cache slot state
1062	sc_signal<bool> r_xram_rsp_coherent; // coherence of the read
1063	////////////////////////////////////////////////////
1064	// Registers controlled by the IXR_CMD fsm
1065	////////////////////////////////////////////////////
1066
1067	sc_signal<int> r_ixr_cmd_fsm;
1068	sc_signal<size_t> r_ixr_cmd_word; // word index for a put
1069	sc_signal<size_t> r_ixr_cmd_trdid; // TRT index value
1070	sc_signal<addr_t> r_ixr_cmd_address; // address to XRAM
1071	sc_signal<data_t> * r_ixr_cmd_wdata; // cache line buffer
1072	sc_signal<bool> r_ixr_cmd_get; // transaction type (PUT/GET)
1073
1074	////////////////////////////////////////////////////
1075	// Registers controlled by TGT_RSP fsm
1076	////////////////////////////////////////////////////
1077
1078	sc_signal<int> r_tgt_rsp_fsm;
1079	sc_signal<size_t> r_tgt_rsp_cpt;
1080	sc_signal<bool> r_tgt_rsp_key_sent;
1081
1082	////////////////////////////////////////////////////
1083	// Registers controlled by CC_SEND fsm
1084	////////////////////////////////////////////////////
1085
1086	sc_signal<int> r_cc_send_fsm;
1087	sc_signal<size_t> r_cc_send_cpt;
1088	sc_signal<bool> r_cc_send_inst;
1089
1090	////////////////////////////////////////////////////
1091	// Registers controlled by CC_RECEIVE fsm
1092	////////////////////////////////////////////////////
1093
1094	sc_signal<int> r_cc_receive_fsm;
1095
1096	////////////////////////////////////////////////////
1097	// Registers controlled by ALLOC_DIR fsm
1098	////////////////////////////////////////////////////
1099
1100	sc_signal<int> r_alloc_dir_fsm;
1101	sc_signal<unsigned> r_alloc_dir_reset_cpt;
1102
1103	////////////////////////////////////////////////////
1104	// Registers controlled by ALLOC_TRT fsm
1105	////////////////////////////////////////////////////
1106
1107	sc_signal<int> r_alloc_trt_fsm;
1108
1109	////////////////////////////////////////////////////
1110	// Registers controlled by ALLOC_UPT fsm
1111	////////////////////////////////////////////////////
1112
1113	// sc_signal<int> r_alloc_upt_fsm;
1114
1115	////////////////////////////////////////////////////
1116	// Registers controlled by ALLOC_IVT fsm
1117	////////////////////////////////////////////////////
1118
1119	sc_signal<int> r_alloc_ivt_fsm;
1120
1121	////////////////////////////////////////////////////
1122	// Registers controlled by ALLOC_HEAP fsm
1123	////////////////////////////////////////////////////
1124
1125	sc_signal<int> r_alloc_heap_fsm;
1126	sc_signal<unsigned> r_alloc_heap_reset_cpt;
1127
1128
1129	////////////////////////////////////////////////////
1130	// REGISTERS FOR ODCCP
1131	////////////////////////////////////////////////////
1132
1133	sc_signal<uint32_t> r_cleanup_data_index;
1134	sc_signal<uint32_t> r_cleanup_trdid;
1135	sc_signal<uint32_t> r_cleanup_state;
1136	sc_signal<uint32_t> r_cleanup_pktid;
1137	sc_signal<bool> r_cleanup_coherent;
1138	sc_signal<data_t> *r_cleanup_data;
1139	sc_signal<data_t> *r_cleanup_old_data;
1140	sc_signal<bool> r_cleanup_contains_data;
1141
1142	sc_signal<bool> r_cleanup_ncc;
1143	sc_signal<bool> r_cleanup_to_ixr_cmd_ncc_l1_dirty;
1144	sc_signal<bool> r_xram_rsp_to_ixr_cmd_inval_ncc_pending;
1145
1146	sc_signal<bool> r_cleanup_to_ixr_cmd_req;
1147	sc_signal<data_t> *r_cleanup_to_ixr_cmd_data;
1148	sc_signal<uint32_t> r_cleanup_to_ixr_cmd_srcid;
1149	sc_signal<uint32_t> r_cleanup_to_ixr_cmd_index;
1150	sc_signal<uint32_t> r_cleanup_to_ixr_cmd_pktid;
1151	sc_signal<addr_t> r_cleanup_to_ixr_cmd_nline;
1152	}; // end class VciMemCache
1153
1154	}}
1155
1156	#endif
1157
1158	// Local Variables:
1159	// tab-width: 2
1160	// c-basic-offset: 2
1161	// c-file-offsets:((innamespace . 0)(inline-open . 0))
1162	// indent-tabs-mode: nil
1163	// End:
1164
1165	// vim: filetype=cpp:expandtab:shiftwidth=2:tabstop=2:softtabstop=2
1166

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