source: branches/ODCCP/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h @ 452

Last change on this file since 452 was 452, checked in by devigne, 11 years ago

Introduction of ODCCP branch
New components :
-dspin_odccp_param (Cleanup Data)
-generic_tlb_odccp (flag CC)
-generic_cache_odccp (STATE : VALID_CC and VALID_NCC)
-vci_cc_vcache_wrapper (Hybrid cache Write-Through / Write-Back,

Cleanup Data, new pktid TYPE_READ_MISS_NO_COHERENT)

-vci_mem_cache (Support for Cleanup Data, Bit coherent for directory entry)

File size: 36.5 KB
Line 
1/* -*- c++ -*-
2 *
3 * File : vci_cc_vcache_wrapper.h
4 * Copyright (c) UPMC, Lip6, SoC
5 * Authors : Alain GREINER, Yang GAO
6 * Date : 27/11/2011
7 *
8 * SOCLIB_LGPL_HEADER_BEGIN
9 *
10 * This file is part of SoCLib, GNU LGPLv2.1.
11 *
12 * SoCLib is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU Lesser General Public License as published
14 * by the Free Software Foundation; version 2.1 of the License.
15 *
16 * SoCLib is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
19 * Lesser General Public License for more details.
20 *
21 * You should have received a copy of the GNU Lesser General Public
22 * License along with SoCLib; if not, write to the Free Software
23 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
24 * 02110-1301 USA
25 *
26 * SOCLIB_LGPL_HEADER_END
27 *
28 * Maintainers: cesar.fuguet-tortolero@lip6.fr
29 *              alexandre.joannou@lip6.fr
30 */
31
32#ifndef SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER_H
33#define SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER_H
34
35#include <inttypes.h>
36#include <systemc>
37#include "caba_base_module.h"
38#include "multi_write_buffer.h"
39#include "generic_fifo.h"
40#include "generic_tlb.h"
41#include "generic_cache.h"
42#include "vci_initiator.h"
43#include "dspin_interface.h"
44#include "dspin_dhccp_param.h"
45#include "mapping_table.h"
46#include "static_assert.h"
47#include "iss2.h"
48
49#define LLSC_TIMEOUT    10000
50
51namespace soclib {
52namespace caba {
53
54using namespace sc_core;
55
56////////////////////////////////////////////
57template<typename vci_param, 
58         size_t   dspin_in_width,
59         size_t   dspin_out_width,
60         typename iss_t>
61class VciCcVCacheWrapper
62////////////////////////////////////////////
63    : public soclib::caba::BaseModule
64{
65
66    typedef typename vci_param::fast_addr_t  paddr_t;
67
68    enum icache_fsm_state_e
69    {
70        ICACHE_IDLE,
71        // handling XTN processor requests
72        ICACHE_XTN_TLB_FLUSH,
73        ICACHE_XTN_CACHE_FLUSH,
74        ICACHE_XTN_CACHE_FLUSH_GO,
75        ICACHE_XTN_TLB_INVAL,
76        ICACHE_XTN_CACHE_INVAL_VA,
77        ICACHE_XTN_CACHE_INVAL_PA,
78        ICACHE_XTN_CACHE_INVAL_GO,
79        // handling tlb miss
80        ICACHE_TLB_WAIT,
81        // handling cache miss
82        ICACHE_MISS_SELECT,
83        ICACHE_MISS_CLEAN,
84        ICACHE_MISS_WAIT,
85        ICACHE_MISS_DATA_UPDT,
86        ICACHE_MISS_DIR_UPDT,
87        // handling unc read
88        ICACHE_UNC_WAIT,
89        // handling coherence requests
90        ICACHE_CC_CHECK,
91        ICACHE_CC_INVAL,
92        ICACHE_CC_UPDT,
93        ICACHE_CC_BROADCAST,
94        ICACHE_CC_SEND_WAIT,
95    };
96
97    enum dcache_fsm_state_e
98    {
99        DCACHE_IDLE,
100        // handling itlb & dtlb miss
101        DCACHE_TLB_MISS,
102        DCACHE_TLB_PTE1_GET,
103        DCACHE_TLB_PTE1_SELECT,
104        DCACHE_TLB_PTE1_UPDT,
105        DCACHE_TLB_PTE2_GET,
106        DCACHE_TLB_PTE2_SELECT,
107        DCACHE_TLB_PTE2_UPDT,
108        DCACHE_TLB_LR_UPDT,
109        DCACHE_TLB_LR_WAIT,
110        DCACHE_TLB_RETURN,
111            // handling processor XTN requests
112        DCACHE_XTN_SWITCH,
113        DCACHE_XTN_SYNC,
114        DCACHE_XTN_IC_INVAL_VA,
115        DCACHE_XTN_IC_FLUSH,
116        DCACHE_XTN_IC_INVAL_PA,
117        DCACHE_XTN_IT_INVAL,
118        DCACHE_XTN_DC_FLUSH,
119        DCACHE_XTN_DC_FLUSH_DATA,
120        DCACHE_XTN_DC_FLUSH_GO,
121        DCACHE_XTN_DC_INVAL_VA,
122        DCACHE_XTN_DC_INVAL_PA,
123        DCACHE_XTN_DC_INVAL_END,
124        DCACHE_XTN_DC_INVAL_GO,
125        DCACHE_XTN_DC_INVAL_DATA,
126        DCACHE_XTN_DT_INVAL,
127        //handling dirty bit update
128        DCACHE_DIRTY_GET_PTE,
129        DCACHE_DIRTY_WAIT,
130            // handling processor miss requests
131        DCACHE_MISS_SELECT,
132        DCACHE_MISS_CLEAN,
133        DCACHE_MISS_DATA,
134        DCACHE_MISS_WAIT,
135        DCACHE_MISS_DATA_UPDT,
136        DCACHE_MISS_DIR_UPDT,
137        // handling processor unc, ll and sc requests
138        DCACHE_UNC_WAIT,
139        DCACHE_LL_WAIT,
140        DCACHE_SC_WAIT,
141        // handling coherence requests
142        DCACHE_CC_CHECK,
143        DCACHE_CC_INVAL_DATA,
144        DCACHE_CC_INVAL,
145        DCACHE_CC_UPDT,
146        DCACHE_CC_BROADCAST,
147        DCACHE_CC_SEND_WAIT,
148        // handling TLB inval (after a coherence or XTN request)
149        DCACHE_INVAL_TLB_SCAN,
150    };
151
152    enum cmd_fsm_state_e
153    {
154        CMD_IDLE,
155        CMD_INS_MISS,
156        CMD_INS_UNC,
157        CMD_DATA_MISS,
158        CMD_DATA_UNC,
159        CMD_DATA_WRITE,
160        CMD_DATA_LL,
161        CMD_DATA_SC,
162        CMD_DATA_CAS,
163    };
164
165    enum rsp_fsm_state_e
166    {
167        RSP_IDLE,
168        RSP_INS_MISS,
169        RSP_INS_UNC,
170        RSP_DATA_MISS,
171        RSP_DATA_UNC,
172        RSP_DATA_LL,
173        RSP_DATA_WRITE,
174    };
175
176    enum cc_receive_fsm_state_e
177    {
178        CC_RECEIVE_IDLE,
179        CC_RECEIVE_CLACK,
180        CC_RECEIVE_BRDCAST_HEADER,
181        CC_RECEIVE_BRDCAST_NLINE,
182        CC_RECEIVE_INVAL_HEADER,
183        CC_RECEIVE_INVAL_NLINE,
184        CC_RECEIVE_UPDT_HEADER,
185        CC_RECEIVE_UPDT_NLINE,
186        CC_RECEIVE_UPDT_DATA,
187    };
188
189    enum cc_send_fsm_state_e
190    {
191        CC_SEND_IDLE,
192        CC_SEND_CLEANUP_1,
193        CC_SEND_CLEANUP_2,
194        CC_SEND_CLEANUP_DATA_UPDT,
195        CC_SEND_MULTI_ACK,
196    };
197
198    /* transaction type, pktid field */
199    enum transaction_type_e
200    {
201        // b3 ODCCP/RWT : COHERENT/NO COHERENT
202        // b2 READ / NOT READ
203        // if READ
204        //  b1 DATA / INS
205        //  b0 UNC / MISS
206        // else
207        //  b1 accÚs table llsc type SW / other
208        //  b2 WRITE/CAS/LL/SC
209        TYPE_READ_DATA_UNC                      = 0x0,
210        TYPE_READ_DATA_MISS                     = 0x1,
211        TYPE_READ_INS_UNC                       = 0x2,
212        TYPE_READ_INS_MISS                      = 0x3,
213        TYPE_WRITE                              = 0x4,
214        TYPE_CAS                                = 0x5,
215        TYPE_LL                                 = 0x6,
216        TYPE_SC                                 = 0x7,
217        TYPE_READ_DATA_MISS_NO_COHERENT         = 0x9
218    };
219
220    /* SC return values */
221    enum sc_status_type_e
222    {
223        SC_SUCCESS  =   0x00000000,
224        SC_FAIL     =   0x00000001
225    };
226
227    // cc_send_type
228    typedef enum 
229    {
230        CC_TYPE_CLEANUP,
231        CC_TYPE_MULTI_ACK,
232    } cc_send_t;
233
234    // cc_receive_type
235    typedef enum 
236    {
237        CC_TYPE_CLACK,
238        CC_TYPE_BRDCAST,
239        CC_TYPE_INVAL,
240        CC_TYPE_UPDT,
241    } cc_receive_t;
242
243    // TLB Mode : ITLB / DTLB / ICACHE / DCACHE
244    enum 
245    {
246        INS_TLB_MASK    = 0x8,
247        DATA_TLB_MASK   = 0x4,
248        INS_CACHE_MASK  = 0x2,
249        DATA_CACHE_MASK = 0x1,
250    };
251
252    // Error Type
253    enum mmu_error_type_e
254    {
255        MMU_NONE                      = 0x0000, // None
256        MMU_WRITE_PT1_UNMAPPED        = 0x0001, // Write & Page fault on PT1
257        MMU_WRITE_PT2_UNMAPPED        = 0x0002, // Write & Page fault on PT2
258        MMU_WRITE_PRIVILEGE_VIOLATION = 0x0004, // Write & Protected access in user mode
259        MMU_WRITE_ACCES_VIOLATION     = 0x0008, // Write to non writable page
260        MMU_WRITE_UNDEFINED_XTN       = 0x0020, // Write & undefined external access
261        MMU_WRITE_PT1_ILLEGAL_ACCESS  = 0x0040, // Write & Bus Error accessing PT1
262        MMU_WRITE_PT2_ILLEGAL_ACCESS  = 0x0080, // Write & Bus Error accessing PT2
263        MMU_WRITE_DATA_ILLEGAL_ACCESS = 0x0100, // Write & Bus Error in cache access
264        MMU_READ_PT1_UNMAPPED         = 0x1001, // Read & Page fault on PT1
265        MMU_READ_PT2_UNMAPPED         = 0x1002, // Read & Page fault on PT2
266        MMU_READ_PRIVILEGE_VIOLATION  = 0x1004, // Read & Protected access in user mode
267        MMU_READ_EXEC_VIOLATION       = 0x1010, // Read & Exec access to a non exec page
268        MMU_READ_UNDEFINED_XTN        = 0x1020, // Read & Undefined external access
269        MMU_READ_PT1_ILLEGAL_ACCESS   = 0x1040, // Read & Bus Error accessing PT1
270        MMU_READ_PT2_ILLEGAL_ACCESS   = 0x1080, // Read & Bus Error accessing PT2
271        MMU_READ_DATA_ILLEGAL_ACCESS  = 0x1100, // Read & Bus Error in cache access
272    };
273
274    // miss types for data cache
275    enum dcache_miss_type_e
276    {
277        PTE1_MISS,
278        PTE2_MISS,
279        PROC_MISS,
280    };
281
282    enum transaction_type_d_e
283    {
284        // b0 : 1 if cached
285        // b1 : 1 if instruction
286        TYPE_DATA_UNC     = 0x0,
287        TYPE_DATA_MISS    = 0x1,
288        TYPE_INS_UNC      = 0x2,
289        TYPE_INS_MISS     = 0x3,
290    };
291
292    //////////////////MODIFIED////////////////
293    enum content_line_cache_status_e
294    {
295        LINE_CACHE_DATA_NOT_DIRTY,
296        LINE_CACHE_DATA_DIRTY,
297        LINE_CACHE_IN_TLB,
298        LINE_CACHE_CONTAINS_PTD,
299    };
300    //////////////////////////////////////////
301
302public:
303    sc_in<bool>                                 p_clk;
304    sc_in<bool>                                 p_resetn;
305    sc_in<bool>                                 p_irq[iss_t::n_irq];
306    soclib::caba::VciInitiator<vci_param>       p_vci;
307    soclib::caba::DspinInput <dspin_in_width>   p_dspin_in;
308    soclib::caba::DspinOutput<dspin_out_width>  p_dspin_out;
309
310private:
311
312    // STRUCTURAL PARAMETERS
313    soclib::common::AddressDecodingTable<uint32_t, bool> m_cacheability_table;
314
315    const size_t                        m_srcid;
316    const size_t                        m_cc_global_id;
317    const size_t                        m_nline_width;
318    const size_t                                                m_itlb_ways;
319    const size_t                                                m_itlb_sets;
320    const size_t                                                m_dtlb_ways;
321    const size_t                                                m_dtlb_sets;
322    const size_t                                                m_icache_ways;
323    const size_t                                                m_icache_sets;
324    const paddr_t                                               m_icache_yzmask;
325    const size_t                                                m_icache_words;
326    const size_t                                                m_dcache_ways;
327    const size_t                                                m_dcache_sets;
328    const paddr_t                                               m_dcache_yzmask;
329    const size_t                                                m_dcache_words;
330    const size_t                        m_x_width;
331    const size_t                        m_y_width;
332    const size_t                        m_proc_id;
333    const uint32_t                                              m_max_frozen_cycles;
334    const size_t                                                m_paddr_nbits;
335    uint32_t                            m_debug_start_cycle;
336    bool                                m_debug_ok;
337
338    ////////////////////////////////////////
339    // Communication with processor ISS
340    ////////////////////////////////////////
341    typename iss_t::InstructionRequest  m_ireq;
342    typename iss_t::InstructionResponse m_irsp;
343    typename iss_t::DataRequest         m_dreq;
344    typename iss_t::DataResponse        m_drsp;
345
346    /////////////////////////////////////////////
347    // debug variables
348    /////////////////////////////////////////////
349    bool                                m_debug_previous_i_hit;
350    bool                                m_debug_previous_d_hit;
351    bool                                m_debug_activated;
352
353    ///////////////////////////////
354    // Software visible REGISTERS
355    ///////////////////////////////
356    sc_signal<uint32_t>     r_mmu_ptpr;                 // page table pointer register
357    sc_signal<uint32_t>     r_mmu_mode;                 // mmu mode register
358    sc_signal<uint32_t>     r_mmu_word_lo;              // mmu misc data low
359    sc_signal<uint32_t>     r_mmu_word_hi;              // mmu misc data hight
360    sc_signal<uint32_t>     r_mmu_ibvar;                // mmu bad instruction address
361    sc_signal<uint32_t>     r_mmu_dbvar;                // mmu bad data address
362    sc_signal<uint32_t>     r_mmu_ietr;                 // mmu instruction error type
363    sc_signal<uint32_t>     r_mmu_detr;                 // mmu data error type
364    uint32_t                r_mmu_params;                       // read-only
365    uint32_t                r_mmu_release;                      // read_only
366
367
368    //////////////////////////////
369    // ICACHE FSM REGISTERS
370    //////////////////////////////
371    sc_signal<int>          r_icache_fsm;               // state register
372    sc_signal<int>          r_icache_fsm_save;          // return state for coherence op
373    sc_signal<paddr_t>      r_icache_vci_paddr;         // physical address
374    sc_signal<uint32_t>     r_icache_vaddr_save;        // virtual address from processor
375
376    // icache miss handling
377    sc_signal<size_t>       r_icache_miss_way;              // selected way for cache update
378    sc_signal<size_t>       r_icache_miss_set;              // selected set for cache update
379    sc_signal<size_t>       r_icache_miss_word;             // word index ( cache update)
380    sc_signal<bool>         r_icache_miss_inval;        // coherence request matching a miss
381    sc_signal<bool>         r_icache_miss_clack;        // waiting for a cleanup acknowledge
382
383    // coherence request handling
384    sc_signal<size_t>       r_icache_cc_way;                // selected way for cc update/inval
385    sc_signal<size_t>       r_icache_cc_set;                // selected set for cc update/inval
386    sc_signal<size_t>       r_icache_cc_word;               // word counter for cc update
387    sc_signal<bool>         r_icache_cc_need_write;     // activate the cache for writing
388
389    // icache flush handling
390    sc_signal<size_t>       r_icache_flush_count;           // slot counter used for cache flush
391
392    // communication between ICACHE FSM and VCI_CMD FSM
393    sc_signal<bool>         r_icache_miss_req;           // cached read miss
394    sc_signal<bool>         r_icache_unc_req;            // uncached read miss
395
396    // communication between ICACHE FSM and DCACHE FSM
397    sc_signal<bool>             r_icache_tlb_miss_req;       // (set icache/reset dcache)
398    sc_signal<bool>         r_icache_tlb_rsp_error;      // tlb miss response error
399
400    // communication between ICACHE FSM and CC_SEND FSM
401    sc_signal<bool>         r_icache_cc_send_req;           // ICACHE cc_send request
402    sc_signal<int>          r_icache_cc_send_type;          // ICACHE cc_send request type
403    sc_signal<paddr_t>      r_icache_cc_send_nline;         // ICACHE cc_send nline
404    sc_signal<size_t>       r_icache_cc_send_way;           // ICACHE cc_send way
405    sc_signal<size_t>       r_icache_cc_send_updt_tab_idx;  // ICACHE cc_send update table index
406
407    ///////////////////////////////
408    // DCACHE FSM REGISTERS
409    ///////////////////////////////
410    sc_signal<int>          r_dcache_fsm;               // state register
411    sc_signal<int>          r_dcache_fsm_cc_save;       // return state for coherence op
412    sc_signal<int>          r_dcache_fsm_scan_save;     // return state for tlb scan op
413    // registers written in P0 stage (used in P1 stage)
414    sc_signal<bool>         r_dcache_wbuf_req;          // WBUF must be written in P1 stage
415    sc_signal<bool>         r_dcache_updt_req;          // DCACHE must be updated in P1 stage
416    sc_signal<uint32_t>     r_dcache_save_vaddr;        // virtual address (from proc)
417    sc_signal<uint32_t>     r_dcache_save_wdata;        // write data (from proc)
418    sc_signal<uint32_t>     r_dcache_save_be;           // byte enable (from proc)
419    sc_signal<paddr_t>      r_dcache_save_paddr;        // physical address
420    sc_signal<bool>         r_dcache_save_cacheable;    // address cacheable
421    sc_signal<size_t>       r_dcache_save_cache_way;    // selected way (from dcache)
422    sc_signal<size_t>       r_dcache_save_cache_set;    // selected set (from dcache)
423    sc_signal<size_t>       r_dcache_save_cache_word;   // selected word (from dcache)
424    // registers used by the Dirty bit sub-fsm
425    sc_signal<paddr_t>      r_dcache_dirty_paddr;       // PTE physical address
426    sc_signal<size_t>       r_dcache_dirty_way;         // way to invalidate in dcache
427    sc_signal<size_t>       r_dcache_dirty_set;         // set to invalidate in dcache
428
429    // communication between DCACHE FSM and VCI_CMD FSM
430    sc_signal<paddr_t>      r_dcache_vci_paddr;             // physical address for VCI command
431    sc_signal<bool>         r_dcache_vci_miss_req;      // read miss request
432    sc_signal<bool>         r_dcache_vci_unc_req;       // uncacheable read request
433    sc_signal<uint32_t>     r_dcache_vci_unc_be;        // uncacheable read byte enable
434    sc_signal<bool>         r_dcache_vci_cas_req;       // atomic write request CAS
435    sc_signal<uint32_t>     r_dcache_vci_cas_old;       // previous data value for a CAS
436    sc_signal<uint32_t>     r_dcache_vci_cas_new;       // new data value for a CAS
437    sc_signal<bool>         r_dcache_vci_ll_req;        // atomic read request LL
438    sc_signal<bool>         r_dcache_vci_sc_req;        // atomic write request SC
439    sc_signal<uint32_t>     r_dcache_vci_sc_data;       // SC data (command)
440
441    // register used for XTN inval
442    sc_signal<size_t>       r_dcache_xtn_way;               // selected way (from dcache)
443    sc_signal<size_t>       r_dcache_xtn_set;               // selected set (from dcache)
444
445    // write buffer state extension
446    sc_signal<bool>         r_dcache_pending_unc_write; // pending uncacheable write in WBUF
447
448    // handling dcache miss
449    sc_signal<int>              r_dcache_miss_type;                 // depending on the requester
450    sc_signal<size_t>       r_dcache_miss_word;             // word index for cache update
451    sc_signal<size_t>       r_dcache_miss_way;              // selected way for cache update
452    sc_signal<size_t>       r_dcache_miss_set;              // selected set for cache update
453    sc_signal<bool>         r_dcache_miss_inval;        // coherence request matching a miss
454    sc_signal<bool>         r_dcache_miss_clack;        // waiting for a cleanup acknowledge
455
456    // handling coherence requests
457    sc_signal<size_t>       r_dcache_cc_way;                // selected way for cc update/inval
458    sc_signal<size_t>       r_dcache_cc_set;                // selected set for cc update/inval
459    sc_signal<size_t>       r_dcache_cc_word;               // word counter for cc update
460    sc_signal<bool>         r_dcache_cc_need_write;     // activate the cache for writing
461
462    // dcache flush handling
463    sc_signal<size_t>       r_dcache_flush_count;           // slot counter used for cache flush
464
465    // ll response handling
466    sc_signal<size_t>       r_dcache_ll_rsp_count;          // flit counter used for ll rsp
467
468    // used by the TLB miss sub-fsm
469    sc_signal<uint32_t>     r_dcache_tlb_vaddr;             // virtual address for a tlb miss
470    sc_signal<bool>         r_dcache_tlb_ins;               // target tlb (itlb if true)
471    sc_signal<paddr_t>      r_dcache_tlb_paddr;             // physical address of pte
472    sc_signal<uint32_t>     r_dcache_tlb_pte_flags;         // pte1 or first word of pte2
473    sc_signal<uint32_t>     r_dcache_tlb_pte_ppn;           // second word of pte2
474    sc_signal<size_t>       r_dcache_tlb_cache_way;         // selected way in dcache
475    sc_signal<size_t>       r_dcache_tlb_cache_set;         // selected set in dcache
476    sc_signal<size_t>       r_dcache_tlb_cache_word;    // selected word in dcache
477    sc_signal<size_t>       r_dcache_tlb_way;               // selected way in tlb
478    sc_signal<size_t>       r_dcache_tlb_set;               // selected set in tlb
479
480    // ITLB and DTLB invalidation
481    sc_signal<paddr_t>      r_dcache_tlb_inval_line;    // line index
482    sc_signal<size_t>       r_dcache_tlb_inval_set;     // tlb set counter
483
484    // communication between DCACHE FSM and ICACHE FSM
485    sc_signal<bool>         r_dcache_xtn_req;           // xtn request (caused by processor)
486    sc_signal<int>          r_dcache_xtn_opcode;        // xtn request type
487
488    // communication between DCACHE FSM and CC_SEND FSM
489    sc_signal<bool>         r_dcache_cc_send_req;           // DCACHE cc_send request
490    sc_signal<int>          r_dcache_cc_send_type;          // DCACHE cc_send request type
491    sc_signal<paddr_t>      r_dcache_cc_send_nline;         // DCACHE cc_send nline
492    sc_signal<size_t>       r_dcache_cc_send_way;           // DCACHE cc_send way
493    sc_signal<size_t>       r_dcache_cc_send_updt_tab_idx;  // DCACHE cc_send update table index
494   
495    // special registers for ODCCP/RWT
496    sc_signal<bool>         r_dcache_cc_cleanup_updt_data;          // Register for cleanup with data (wb updt)
497    sc_signal<bool>         r_dcache_cleanup_ncc;                   // Register for cleanup no coherent
498    sc_signal<bool>         r_dcache_miss_victim_no_coherence;      // Register for victim in no coherence mode
499    sc_signal<bool>         r_dcache_line_no_coherence;             // Register for line current in no coherence mode
500    sc_signal<bool>         r_dcache_miss_no_coherent;              // Register for miss on NCC line
501    sc_signal<bool>         r_vci_rsp_read_data_miss_no_coherent;   // Read miss rsp on line NCC
502    sc_signal<uint32_t>     r_cc_send_cpt_word;
503
504    sc_signal<uint32_t>     r_dcache_miss_data_cpt;                 // Cpt a word to read for sending Cleanup with data (MISS STATE)
505    sc_signal<paddr_t>      r_dcache_miss_data_addr;                // Addr for read word for sending Cleanup with data (MISS STATE)
506   
507    sc_signal<int>          r_dcache_xtn_state;
508    sc_signal<paddr_t>      r_dcache_xtn_data_addr;                 // Cpt a word to read for sending Cleanup with data (XTN DC INVAL STATE)
509    sc_signal<uint32_t>     r_dcache_xtn_data_cpt;                  // Addr for read word for sending Cleanup with data (XTN DC INVAL STATE)
510   
511    sc_signal<paddr_t>      r_dcache_cc_inval_addr;                 // Cpt a word to read for sending Cleanup with data (CC INVAL STATE)
512    sc_signal<uint32_t>     r_dcache_cc_inval_data_cpt;             // Addr for read word for sending Cleanup with data (CC INVAL STATE)
513    sc_signal<int>          r_dcache_cc_state;
514   
515    sc_signal<paddr_t>      r_dcache_xtn_flush_addr_data;           // Cpt a word to read for sending Cleanup with data (XTN DC FLUSH STATE)
516    sc_signal<uint32_t>     r_dcache_xtn_flush_data_cpt;            // Addr for read word for sending Cleanup with data (XTN DC FLUSH STATE)
517   
518    /*STATS DIRTY*/
519    bool *dirty_stats;
520    uint32_t m_cpt_words_dirty;     // total number of words dirty when we send a cleanup with data
521   
522    //////////////
523    GenericFifo<uint32_t>   r_cc_send_data_fifo;                    // Fifo for save data value (before sending cleanup with data)
524    // dcache directory extension
525    ///////////////////////////MODIFIED///////////////////////////////////////////////////
526    //bool                    *r_dcache_in_tlb;           // copy exist in dtlb or itlb
527    //bool                    *r_dcache_contains_ptd;     // cache line contains a PTD
528    int                     *r_dcache_content_state;    // content state of one cache line
529    //////////////////////////////////////////////////////////////////////////////////////
530
531    // Physical address extension for data access
532    sc_signal<uint32_t>     r_dcache_paddr_ext;             // CP2 register (if vci_address > 32)
533
534    ///////////////////////////////////
535    // VCI_CMD FSM REGISTERS
536    ///////////////////////////////////
537    sc_signal<int>          r_vci_cmd_fsm;
538    sc_signal<size_t>       r_vci_cmd_min;                      // used for write bursts
539    sc_signal<size_t>       r_vci_cmd_max;                      // used for write bursts
540    sc_signal<size_t>       r_vci_cmd_cpt;                      // used for write bursts
541    sc_signal<bool>         r_vci_cmd_imiss_prio;               // round-robin between imiss & dmiss
542
543    ///////////////////////////////////
544    // VCI_RSP FSM REGISTERS
545    ///////////////////////////////////
546    sc_signal<int>          r_vci_rsp_fsm;
547    sc_signal<size_t>       r_vci_rsp_cpt;
548    sc_signal<bool>         r_vci_rsp_ins_error;
549    sc_signal<bool>         r_vci_rsp_data_error;
550    GenericFifo<uint32_t>   r_vci_rsp_fifo_icache;              // response FIFO to ICACHE FSM
551    GenericFifo<uint32_t>   r_vci_rsp_fifo_dcache;              // response FIFO to DCACHE FSM
552   
553
554    ///////////////////////////////////
555    //  CC_SEND FSM REGISTER
556    ///////////////////////////////////
557    sc_signal<int>          r_cc_send_fsm;                  // state register
558    sc_signal<bool>         r_cc_send_last_client;          // 0 dcache / 1 icache
559
560    ///////////////////////////////////
561    //  CC_RECEIVE FSM REGISTER
562    ///////////////////////////////////
563    sc_signal<int>          r_cc_receive_fsm;               // state register
564    sc_signal<bool>         r_cc_receive_data_ins;          // request to : 0 dcache / 1 icache
565
566    // communication between CC_RECEIVE FSM and ICACHE/DCACHE FSM
567    sc_signal<size_t>       r_cc_receive_word_idx;          // word index
568    GenericFifo<uint32_t>   r_cc_receive_updt_fifo_be;
569    GenericFifo<uint32_t>   r_cc_receive_updt_fifo_data;
570    GenericFifo<bool>       r_cc_receive_updt_fifo_eop;
571
572    // communication between CC_RECEIVE FSM and ICACHE FSM
573    sc_signal<bool>         r_cc_receive_icache_req;        // cc_receive to icache request
574    sc_signal<int>          r_cc_receive_icache_type;       // cc_receive type of request
575    sc_signal<size_t>       r_cc_receive_icache_way;        // cc_receive to icache way
576    sc_signal<size_t>       r_cc_receive_icache_set;        // cc_receive to icache set
577    sc_signal<size_t>       r_cc_receive_icache_updt_tab_idx;  // cc_receive update table index
578    sc_signal<paddr_t>      r_cc_receive_icache_nline;      // cache line physical address
579
580    // communication between CC_RECEIVE FSM and DCACHE FSM
581    sc_signal<bool>         r_cc_receive_dcache_req;        // cc_receive to dcache request
582    sc_signal<int>          r_cc_receive_dcache_type;       // cc_receive type of request
583    sc_signal<size_t>       r_cc_receive_dcache_way;        // cc_receive to dcache way
584    sc_signal<size_t>       r_cc_receive_dcache_set;        // cc_receive to dcache set
585    sc_signal<size_t>       r_cc_receive_dcache_updt_tab_idx;  // cc_receive update table index
586    sc_signal<paddr_t>      r_cc_receive_dcache_nline;      // cache line physical address
587
588    //////////////////////////////////////////////////////////////////
589    // processor, write buffer, caches , TLBs
590    //////////////////////////////////////////////////////////////////
591
592    iss_t                       r_iss;
593    MultiWriteBuffer<paddr_t>   r_wbuf;
594    GenericCache<paddr_t>       r_icache;
595    GenericCache<paddr_t>       r_dcache;
596    GenericTlb<paddr_t>         r_itlb;
597    GenericTlb<paddr_t>         r_dtlb;
598
599    //////////////////////////////////////////////////////////////////
600    // llsc registration buffer
601    //////////////////////////////////////////////////////////////////
602
603    sc_signal<paddr_t>                     r_dcache_llsc_paddr;
604    sc_signal<uint32_t>                    r_dcache_llsc_key;
605    sc_signal<uint32_t>                    r_dcache_llsc_count;
606    sc_signal<bool>                        r_dcache_llsc_valid;
607
608    ////////////////////////////////
609    // Activity counters
610    ////////////////////////////////
611    uint32_t m_cpt_dcache_data_read;        // DCACHE DATA READ
612    uint32_t m_cpt_dcache_data_write;       // DCACHE DATA WRITE
613    uint32_t m_cpt_dcache_dir_read;         // DCACHE DIR READ
614    uint32_t m_cpt_dcache_dir_write;        // DCACHE DIR WRITE
615
616    uint32_t m_cpt_icache_data_read;        // ICACHE DATA READ
617    uint32_t m_cpt_icache_data_write;       // ICACHE DATA WRITE
618    uint32_t m_cpt_icache_dir_read;         // ICACHE DIR READ
619    uint32_t m_cpt_icache_dir_write;        // ICACHE DIR WRITE
620
621    uint32_t m_cpt_frz_cycles;              // number of cycles where the cpu is frozen
622    uint32_t m_cpt_total_cycles;                // total number of cycles
623
624    // Cache activity counters
625    uint32_t m_cpt_data_read;               // total number of read data
626    uint32_t m_cpt_data_write;              // total number of write data
627    uint32_t m_cpt_data_write_back;         // total number of write NCC
628    uint32_t m_cpt_data_cleanup;            // total number of flits cleanup data
629    uint32_t m_cpt_data_cleanup_dirty;      // total number of cleanup data dirty
630    uint32_t m_cpt_data_sc;
631    uint32_t m_cpt_data_write_miss_ncc;     // total number of write NCC miss
632    uint32_t m_cpt_data_miss;               // number of read miss
633    uint32_t m_cpt_ins_miss;                // number of instruction miss
634    uint32_t m_cpt_unc_read;                // number of read uncached
635    uint32_t m_cpt_write_cached;            // number of cached write
636    uint32_t m_cpt_ins_read;                // number of instruction read
637    uint32_t m_cpt_ins_spc_miss;            // number of speculative instruction miss
638
639    uint32_t m_cost_write_frz;              // number of frozen cycles related to write buffer
640    uint32_t m_cost_data_miss_frz;          // number of frozen cycles related to data miss
641    uint32_t m_cost_unc_read_frz;           // number of frozen cycles related to uncached read
642    uint32_t m_cost_ins_miss_frz;           // number of frozen cycles related to ins miss
643
644    uint32_t m_cpt_imiss_transaction;       // number of VCI instruction miss transactions
645    uint32_t m_cpt_dmiss_transaction;       // number of VCI data miss transactions
646    uint32_t m_cpt_unc_transaction;         // number of VCI uncached read transactions
647    uint32_t m_cpt_write_transaction;       // number of VCI write transactions
648    uint32_t m_cpt_icache_unc_transaction;
649
650    uint32_t m_cost_imiss_transaction;      // cumulated duration for VCI IMISS transactions
651    uint32_t m_cost_dmiss_transaction;      // cumulated duration for VCI DMISS transactions
652    uint32_t m_cost_unc_transaction;        // cumulated duration for VCI UNC transactions
653    uint32_t m_cost_write_transaction;      // cumulated duration for VCI WRITE transactions
654    uint32_t m_cost_icache_unc_transaction; // cumulated duration for VCI IUNC transactions
655    uint32_t m_length_write_transaction;    // cumulated length for VCI WRITE transactions
656
657    // TLB activity counters
658    uint32_t m_cpt_ins_tlb_read;            // number of instruction tlb read
659    uint32_t m_cpt_ins_tlb_miss;            // number of instruction tlb miss
660    uint32_t m_cpt_ins_tlb_update_acc;      // number of instruction tlb update
661    uint32_t m_cpt_ins_tlb_occup_cache;     // number of instruction tlb occupy data cache line
662    uint32_t m_cpt_ins_tlb_hit_dcache;      // number of instruction tlb hit in data cache
663
664    uint32_t m_cpt_data_tlb_read;           // number of data tlb read
665    uint32_t m_cpt_data_tlb_miss;           // number of data tlb miss
666    uint32_t m_cpt_data_tlb_update_acc;     // number of data tlb update
667    uint32_t m_cpt_data_tlb_update_dirty;   // number of data tlb update dirty
668    uint32_t m_cpt_data_tlb_hit_dcache;     // number of data tlb hit in data cache
669    uint32_t m_cpt_data_tlb_occup_cache;    // number of data tlb occupy data cache line
670    uint32_t m_cpt_tlb_occup_dcache;
671
672    uint32_t m_cost_ins_tlb_miss_frz;       // number of frozen cycles related to instruction tlb miss
673    uint32_t m_cost_data_tlb_miss_frz;      // number of frozen cycles related to data tlb miss
674    uint32_t m_cost_ins_tlb_update_acc_frz;    // number of frozen cycles related to instruction tlb update acc
675    uint32_t m_cost_data_tlb_update_acc_frz;   // number of frozen cycles related to data tlb update acc
676    uint32_t m_cost_data_tlb_update_dirty_frz; // number of frozen cycles related to data tlb update dirty
677    uint32_t m_cost_ins_tlb_occup_cache_frz;   // number of frozen cycles related to instruction tlb miss operate in dcache
678    uint32_t m_cost_data_tlb_occup_cache_frz;  // number of frozen cycles related to data tlb miss operate in dcache
679
680    uint32_t m_cpt_itlbmiss_transaction;       // number of itlb miss transactions
681    uint32_t m_cpt_itlb_ll_transaction;        // number of itlb ll acc transactions
682    uint32_t m_cpt_itlb_sc_transaction;        // number of itlb sc acc transactions
683    uint32_t m_cpt_dtlbmiss_transaction;       // number of dtlb miss transactions
684    uint32_t m_cpt_dtlb_ll_transaction;        // number of dtlb ll acc transactions
685    uint32_t m_cpt_dtlb_sc_transaction;        // number of dtlb sc acc transactions
686    uint32_t m_cpt_dtlb_ll_dirty_transaction;  // number of dtlb ll dirty transactions
687    uint32_t m_cpt_dtlb_sc_dirty_transaction;  // number of dtlb sc dirty transactions
688
689    uint32_t m_cost_itlbmiss_transaction;       // cumulated duration for VCI instruction TLB miss transactions
690    uint32_t m_cost_itlb_ll_transaction;        // cumulated duration for VCI instruction TLB ll acc transactions
691    uint32_t m_cost_itlb_sc_transaction;        // cumulated duration for VCI instruction TLB sc acc transactions
692    uint32_t m_cost_dtlbmiss_transaction;       // cumulated duration for VCI data TLB miss transactions
693    uint32_t m_cost_dtlb_ll_transaction;        // cumulated duration for VCI data TLB ll acc transactions
694    uint32_t m_cost_dtlb_sc_transaction;        // cumulated duration for VCI data TLB sc acc transactions
695    uint32_t m_cost_dtlb_ll_dirty_transaction;  // cumulated duration for VCI data TLB ll dirty transactions
696    uint32_t m_cost_dtlb_sc_dirty_transaction;  // cumulated duration for VCI data TLB sc dirty transactions
697
698    // coherence activity counters
699    uint32_t m_cpt_cc_update_icache;            // number of coherence update instruction commands
700    uint32_t m_cpt_cc_update_dcache;            // number of coherence update data commands
701    uint32_t m_cpt_cc_inval_icache;             // number of coherence inval instruction commands
702    uint32_t m_cpt_cc_inval_dcache;             // number of coherence inval data commands
703    uint32_t m_cpt_cc_broadcast;                // number of coherence broadcast commands
704
705    uint32_t m_cost_updt_data_frz;              // number of frozen cycles related to coherence update data packets
706    uint32_t m_cost_inval_ins_frz;              // number of frozen cycles related to coherence inval instruction packets
707    uint32_t m_cost_inval_data_frz;             // number of frozen cycles related to coherence inval data packets
708    uint32_t m_cost_broadcast_frz;              // number of frozen cycles related to coherence broadcast packets
709
710    uint32_t m_cpt_cc_cleanup_ins;              // number of coherence cleanup packets
711    uint32_t m_cpt_cc_cleanup_data;             // number of coherence cleanup packets
712
713    uint32_t m_cpt_icleanup_transaction;        // number of instruction cleanup transactions
714    uint32_t m_cpt_dcleanup_transaction;        // number of instructinumber of data cleanup transactions
715    uint32_t m_cost_icleanup_transaction;       // cumulated duration for VCI instruction cleanup transactions
716    uint32_t m_cost_dcleanup_transaction;       // cumulated duration for VCI data cleanup transactions
717
718    uint32_t m_cost_ins_tlb_inval_frz;      // number of frozen cycles related to checking ins tlb invalidate
719    uint32_t m_cpt_ins_tlb_inval;           // number of ins tlb invalidate
720
721    uint32_t m_cost_data_tlb_inval_frz;     // number of frozen cycles related to checking data tlb invalidate
722    uint32_t m_cpt_data_tlb_inval;          // number of data tlb invalidate
723
724    // FSM activity counters
725    uint32_t m_cpt_fsm_icache     [64];
726    uint32_t m_cpt_fsm_dcache     [64];
727    uint32_t m_cpt_fsm_cmd        [64];
728    uint32_t m_cpt_fsm_rsp        [64];
729    uint32_t m_cpt_fsm_cc_receive [64];
730    uint32_t m_cpt_fsm_cc_send    [64];
731
732    uint32_t m_cpt_stop_simulation;             // used to stop simulation if frozen
733    bool     m_monitor_ok;                      // used to debug cache output 
734    uint32_t m_monitor_base;               
735    uint32_t m_monitor_length;             
736
737protected:
738    SC_HAS_PROCESS(VciCcVCacheWrapper);
739
740public:
741    VciCcVCacheWrapper(
742        sc_module_name                      name,
743        const int                           proc_id,
744        const soclib::common::MappingTable  &mtd,
745        const soclib::common::IntTab        &srcid,
746        const size_t                        cc_global_id,
747        const size_t                        itlb_ways,
748        const size_t                        itlb_sets,
749        const size_t                        dtlb_ways,
750        const size_t                        dtlb_sets,
751        const size_t                        icache_ways,
752        const size_t                        icache_sets,
753        const size_t                        icache_words,
754        const size_t                        dcache_ways,
755        const size_t                        dcache_sets,
756        const size_t                        dcache_words,
757        const size_t                        wbuf_nlines,
758        const size_t                        wbuf_nwords,
759        const size_t                        x_width,
760        const size_t                        y_width,
761        const uint32_t                      max_frozen_cycles,
762        const uint32_t                      debug_start_cycle,
763        const bool                          debug_ok );
764
765    ~VciCcVCacheWrapper();
766
767    void print_cpi();
768    void print_stats();
769    void clear_stats();
770    void print_trace(size_t mode = 0);
771    void cache_monitor(paddr_t addr);
772    void start_monitor(paddr_t,paddr_t);
773    void stop_monitor();
774    inline void iss_set_debug_mask(uint v) 
775    {
776            r_iss.set_debug_mask(v);
777    }
778
779private:
780    void transition();
781    void genMoore();
782
783    soclib_static_assert((int)iss_t::SC_ATOMIC == (int)vci_param::STORE_COND_ATOMIC);
784    soclib_static_assert((int)iss_t::SC_NOT_ATOMIC == (int)vci_param::STORE_COND_NOT_ATOMIC);
785};
786
787}}
788
789#endif /* SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER_H */
790
791// Local Variables:
792// tab-width: 4
793// c-basic-offset: 4
794// c-file-offsets:((innamespace . 0)(inline-open . 0))
795// indent-tabs-mode: nil
796// End:
797
798// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
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