source: branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h @ 771

Last change on this file since 771 was 771, checked in by meunier, 10 years ago

RWT Branch:

  • Renamed module caba:generic_cache_tsar to caba:generic_cache_tsar_rwt
  • Renamed module caba:dspin_dhccp_param to caba:dspin_rwt_param
  • cosmetic in generic_cache.h
File size: 37.5 KB
RevLine 
[331]1/* -*- c++ -*-
[346]2 *
[331]3 * File : vci_cc_vcache_wrapper.h
4 * Copyright (c) UPMC, Lip6, SoC
5 * Authors : Alain GREINER, Yang GAO
6 * Date : 27/11/2011
7 *
8 * SOCLIB_LGPL_HEADER_BEGIN
9 *
10 * This file is part of SoCLib, GNU LGPLv2.1.
11 *
12 * SoCLib is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU Lesser General Public License as published
14 * by the Free Software Foundation; version 2.1 of the License.
15 *
16 * SoCLib is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
19 * Lesser General Public License for more details.
20 *
21 * You should have received a copy of the GNU Lesser General Public
22 * License along with SoCLib; if not, write to the Free Software
23 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
24 * 02110-1301 USA
25 *
26 * SOCLIB_LGPL_HEADER_END
27 *
28 * Maintainers: cesar.fuguet-tortolero@lip6.fr
29 *              alexandre.joannou@lip6.fr
30 */
31
32#ifndef SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER_H
33#define SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER_H
34
35#include <inttypes.h>
36#include <systemc>
[771]37
[331]38#include "caba_base_module.h"
39#include "multi_write_buffer.h"
40#include "generic_fifo.h"
41#include "generic_tlb.h"
42#include "generic_cache.h"
43#include "vci_initiator.h"
44#include "dspin_interface.h"
[771]45#include "dspin_rwt_param.h"
[331]46#include "mapping_table.h"
47#include "static_assert.h"
48#include "iss2.h"
49
50#define LLSC_TIMEOUT    10000
51
52namespace soclib {
53namespace caba {
54
55using namespace sc_core;
56
57////////////////////////////////////////////
[386]58template<typename vci_param, 
59         size_t   dspin_in_width,
60         size_t   dspin_out_width,
61         typename iss_t>
[331]62class VciCcVCacheWrapper
63////////////////////////////////////////////
64    : public soclib::caba::BaseModule
65{
66
[394]67    typedef typename vci_param::fast_addr_t  paddr_t;
[331]68
[394]69    enum icache_fsm_state_e
70    {
[331]71        ICACHE_IDLE,
72        // handling XTN processor requests
73        ICACHE_XTN_TLB_FLUSH,
74        ICACHE_XTN_CACHE_FLUSH,
75        ICACHE_XTN_CACHE_FLUSH_GO,
76        ICACHE_XTN_TLB_INVAL,
77        ICACHE_XTN_CACHE_INVAL_VA,
78        ICACHE_XTN_CACHE_INVAL_PA,
79        ICACHE_XTN_CACHE_INVAL_GO,
80        // handling tlb miss
81        ICACHE_TLB_WAIT,
82        // handling cache miss
83        ICACHE_MISS_SELECT,
84        ICACHE_MISS_CLEAN,
85        ICACHE_MISS_WAIT,
86        ICACHE_MISS_DATA_UPDT,
87        ICACHE_MISS_DIR_UPDT,
88        // handling unc read
89        ICACHE_UNC_WAIT,
90        // handling coherence requests
91        ICACHE_CC_CHECK,
[468]92        ICACHE_CC_UPDT,
[331]93        ICACHE_CC_INVAL,
94    };
95
[394]96    enum dcache_fsm_state_e
97    {
[331]98        DCACHE_IDLE,
99        // handling itlb & dtlb miss
100        DCACHE_TLB_MISS,
101        DCACHE_TLB_PTE1_GET,
102        DCACHE_TLB_PTE1_SELECT,
103        DCACHE_TLB_PTE1_UPDT,
104        DCACHE_TLB_PTE2_GET,
105        DCACHE_TLB_PTE2_SELECT,
106        DCACHE_TLB_PTE2_UPDT,
107        DCACHE_TLB_LR_UPDT,
108        DCACHE_TLB_LR_WAIT,
109        DCACHE_TLB_RETURN,
110            // handling processor XTN requests
111        DCACHE_XTN_SWITCH,
112        DCACHE_XTN_SYNC,
113        DCACHE_XTN_IC_INVAL_VA,
114        DCACHE_XTN_IC_FLUSH,
115        DCACHE_XTN_IC_INVAL_PA,
116        DCACHE_XTN_IT_INVAL,
117        DCACHE_XTN_DC_FLUSH,
[477]118        DCACHE_XTN_DC_FLUSH_DATA,
[331]119        DCACHE_XTN_DC_FLUSH_GO,
120        DCACHE_XTN_DC_INVAL_VA,
121        DCACHE_XTN_DC_INVAL_PA,
122        DCACHE_XTN_DC_INVAL_END,
123        DCACHE_XTN_DC_INVAL_GO,
[477]124        DCACHE_XTN_DC_INVAL_DATA,
[331]125        DCACHE_XTN_DT_INVAL,
126        //handling dirty bit update
127        DCACHE_DIRTY_GET_PTE,
128        DCACHE_DIRTY_WAIT,
129            // handling processor miss requests
130        DCACHE_MISS_SELECT,
131        DCACHE_MISS_CLEAN,
[477]132        DCACHE_MISS_DATA,
[331]133        DCACHE_MISS_WAIT,
134        DCACHE_MISS_DATA_UPDT,
135        DCACHE_MISS_DIR_UPDT,
136        // handling processor unc, ll and sc requests
137        DCACHE_UNC_WAIT,
138        DCACHE_LL_WAIT,
139        DCACHE_SC_WAIT,
140        // handling coherence requests
141        DCACHE_CC_CHECK,
[468]142        DCACHE_CC_UPDT,
[331]143        DCACHE_CC_INVAL,
[477]144        DCACHE_CC_INVAL_DATA,
[331]145        // handling TLB inval (after a coherence or XTN request)
146        DCACHE_INVAL_TLB_SCAN,
147    };
148
[394]149    enum cmd_fsm_state_e
150    {
[331]151        CMD_IDLE,
152        CMD_INS_MISS,
153        CMD_INS_UNC,
154        CMD_DATA_MISS,
[646]155        CMD_DATA_UNC_READ,
156        CMD_DATA_UNC_WRITE,
[331]157        CMD_DATA_WRITE,
158        CMD_DATA_LL,
159        CMD_DATA_SC,
160        CMD_DATA_CAS,
161    };
162
[394]163    enum rsp_fsm_state_e
164    {
[331]165        RSP_IDLE,
166        RSP_INS_MISS,
167        RSP_INS_UNC,
168        RSP_DATA_MISS,
169        RSP_DATA_UNC,
170        RSP_DATA_LL,
171        RSP_DATA_WRITE,
172    };
173
[394]174    enum cc_receive_fsm_state_e
175    {
[331]176        CC_RECEIVE_IDLE,
177        CC_RECEIVE_BRDCAST_HEADER,
178        CC_RECEIVE_BRDCAST_NLINE,
[468]179        CC_RECEIVE_INS_INVAL_HEADER,
180        CC_RECEIVE_INS_INVAL_NLINE,
181        CC_RECEIVE_INS_UPDT_HEADER,
182        CC_RECEIVE_INS_UPDT_NLINE,
[615]183        CC_RECEIVE_INS_UPDT_DATA,
[468]184        CC_RECEIVE_DATA_INVAL_HEADER,
185        CC_RECEIVE_DATA_INVAL_NLINE,
186        CC_RECEIVE_DATA_UPDT_HEADER,
187        CC_RECEIVE_DATA_UPDT_NLINE,
188        CC_RECEIVE_DATA_UPDT_DATA,
[331]189    };
190
[394]191    enum cc_send_fsm_state_e
192    {
[331]193        CC_SEND_IDLE,
194        CC_SEND_CLEANUP_1,
195        CC_SEND_CLEANUP_2,
[477]196        CC_SEND_CLEANUP_DATA_UPDT,
[331]197        CC_SEND_MULTI_ACK,
198    };
199
200    /* transaction type, pktid field */
201    enum transaction_type_e
202    {
203        // b3 unused
204        // b2 READ / NOT READ
205        // if READ
206        //  b1 DATA / INS
207        //  b0 UNC / MISS
208        // else
209        //  b1 accÚs table llsc type SW / other
210        //  b2 WRITE/CAS/LL/SC
[646]211        TYPE_DATA_UNC               = 0x0,
[331]212        TYPE_READ_DATA_MISS         = 0x1,
213        TYPE_READ_INS_UNC           = 0x2,
214        TYPE_READ_INS_MISS          = 0x3,
215        TYPE_WRITE                  = 0x4,
216        TYPE_CAS                    = 0x5,
217        TYPE_LL                     = 0x6,
218        TYPE_SC                     = 0x7
219    };
220
221    /* SC return values */
222    enum sc_status_type_e
223    {
224        SC_SUCCESS  =   0x00000000,
225        SC_FAIL     =   0x00000001
226    };
227
228    // cc_send_type
[394]229    typedef enum 
230    {
[331]231        CC_TYPE_CLEANUP,
232        CC_TYPE_MULTI_ACK,
233    } cc_send_t;
234
235    // cc_receive_type
[394]236    typedef enum 
237    {
[331]238        CC_TYPE_CLACK,
239        CC_TYPE_BRDCAST,
240        CC_TYPE_INVAL,
241        CC_TYPE_UPDT,
242    } cc_receive_t;
243
244    // TLB Mode : ITLB / DTLB / ICACHE / DCACHE
[394]245    enum 
246    {
[331]247        INS_TLB_MASK    = 0x8,
248        DATA_TLB_MASK   = 0x4,
249        INS_CACHE_MASK  = 0x2,
250        DATA_CACHE_MASK = 0x1,
251    };
252
253    // Error Type
254    enum mmu_error_type_e
255    {
256        MMU_NONE                      = 0x0000, // None
257        MMU_WRITE_PT1_UNMAPPED        = 0x0001, // Write & Page fault on PT1
258        MMU_WRITE_PT2_UNMAPPED        = 0x0002, // Write & Page fault on PT2
259        MMU_WRITE_PRIVILEGE_VIOLATION = 0x0004, // Write & Protected access in user mode
260        MMU_WRITE_ACCES_VIOLATION     = 0x0008, // Write to non writable page
261        MMU_WRITE_UNDEFINED_XTN       = 0x0020, // Write & undefined external access
262        MMU_WRITE_PT1_ILLEGAL_ACCESS  = 0x0040, // Write & Bus Error accessing PT1
263        MMU_WRITE_PT2_ILLEGAL_ACCESS  = 0x0080, // Write & Bus Error accessing PT2
264        MMU_WRITE_DATA_ILLEGAL_ACCESS = 0x0100, // Write & Bus Error in cache access
265        MMU_READ_PT1_UNMAPPED         = 0x1001, // Read & Page fault on PT1
266        MMU_READ_PT2_UNMAPPED         = 0x1002, // Read & Page fault on PT2
267        MMU_READ_PRIVILEGE_VIOLATION  = 0x1004, // Read & Protected access in user mode
268        MMU_READ_EXEC_VIOLATION       = 0x1010, // Read & Exec access to a non exec page
269        MMU_READ_UNDEFINED_XTN        = 0x1020, // Read & Undefined external access
270        MMU_READ_PT1_ILLEGAL_ACCESS   = 0x1040, // Read & Bus Error accessing PT1
271        MMU_READ_PT2_ILLEGAL_ACCESS   = 0x1080, // Read & Bus Error accessing PT2
272        MMU_READ_DATA_ILLEGAL_ACCESS  = 0x1100, // Read & Bus Error in cache access
273    };
274
275    // miss types for data cache
276    enum dcache_miss_type_e
277    {
278        PTE1_MISS,
279        PTE2_MISS,
280        PROC_MISS,
281    };
282
283
[767]284    // cache line status
[477]285    enum content_line_cache_status_e
286    {
287        LINE_CACHE_DATA_NOT_DIRTY,
288        LINE_CACHE_DATA_DIRTY,
289        LINE_CACHE_IN_TLB,
290        LINE_CACHE_CONTAINS_PTD,
291    };
292    //////////////////////////////////////////
293
[331]294public:
[468]295    sc_in<bool>                                p_clk;
296    sc_in<bool>                                p_resetn;
297    sc_in<bool>                                p_irq[iss_t::n_irq];
298    soclib::caba::VciInitiator<vci_param>      p_vci;
299    soclib::caba::DspinInput<dspin_in_width>   p_dspin_m2p;
300    soclib::caba::DspinOutput<dspin_out_width> p_dspin_p2m;
301    soclib::caba::DspinInput<dspin_in_width>   p_dspin_clack;
[331]302
303private:
304
305    // STRUCTURAL PARAMETERS
[577]306    soclib::common::AddressDecodingTable<uint64_t, bool> m_cacheability_table;
[331]307
[394]308    const size_t                        m_srcid;
[346]309    const size_t                        m_cc_global_id;
310    const size_t                        m_nline_width;
[331]311    const size_t                                                m_itlb_ways;
312    const size_t                                                m_itlb_sets;
313    const size_t                                                m_dtlb_ways;
314    const size_t                                                m_dtlb_sets;
315    const size_t                                                m_icache_ways;
316    const size_t                                                m_icache_sets;
317    const paddr_t                                               m_icache_yzmask;
318    const size_t                                                m_icache_words;
319    const size_t                                                m_dcache_ways;
320    const size_t                                                m_dcache_sets;
321    const paddr_t                                               m_dcache_yzmask;
322    const size_t                                                m_dcache_words;
323    const size_t                        m_x_width;
324    const size_t                        m_y_width;
325    const size_t                        m_proc_id;
326    const uint32_t                                              m_max_frozen_cycles;
327    const size_t                                                m_paddr_nbits;
[346]328    uint32_t                            m_debug_start_cycle;
329    bool                                m_debug_ok;
[331]330
331    ////////////////////////////////////////
332    // Communication with processor ISS
333    ////////////////////////////////////////
334    typename iss_t::InstructionRequest  m_ireq;
335    typename iss_t::InstructionResponse m_irsp;
336    typename iss_t::DataRequest         m_dreq;
337    typename iss_t::DataResponse        m_drsp;
338
339    /////////////////////////////////////////////
[394]340    // debug variables
[331]341    /////////////////////////////////////////////
[394]342    bool                                m_debug_previous_i_hit;
343    bool                                m_debug_previous_d_hit;
344    bool                                m_debug_activated;
[331]345
346    ///////////////////////////////
347    // Software visible REGISTERS
348    ///////////////////////////////
349    sc_signal<uint32_t>     r_mmu_ptpr;                 // page table pointer register
350    sc_signal<uint32_t>     r_mmu_mode;                 // mmu mode register
351    sc_signal<uint32_t>     r_mmu_word_lo;              // mmu misc data low
352    sc_signal<uint32_t>     r_mmu_word_hi;              // mmu misc data hight
353    sc_signal<uint32_t>     r_mmu_ibvar;                // mmu bad instruction address
354    sc_signal<uint32_t>     r_mmu_dbvar;                // mmu bad data address
355    sc_signal<uint32_t>     r_mmu_ietr;                 // mmu instruction error type
356    sc_signal<uint32_t>     r_mmu_detr;                 // mmu data error type
357    uint32_t                r_mmu_params;                       // read-only
358    uint32_t                r_mmu_release;                      // read_only
359
360
361    //////////////////////////////
362    // ICACHE FSM REGISTERS
363    //////////////////////////////
364    sc_signal<int>          r_icache_fsm;               // state register
365    sc_signal<int>          r_icache_fsm_save;          // return state for coherence op
366    sc_signal<paddr_t>      r_icache_vci_paddr;         // physical address
367    sc_signal<uint32_t>     r_icache_vaddr_save;        // virtual address from processor
368
369    // icache miss handling
370    sc_signal<size_t>       r_icache_miss_way;              // selected way for cache update
371    sc_signal<size_t>       r_icache_miss_set;              // selected set for cache update
372    sc_signal<size_t>       r_icache_miss_word;             // word index ( cache update)
373    sc_signal<bool>         r_icache_miss_inval;        // coherence request matching a miss
374    sc_signal<bool>         r_icache_miss_clack;        // waiting for a cleanup acknowledge
375
376    // coherence request handling
377    sc_signal<size_t>       r_icache_cc_way;                // selected way for cc update/inval
378    sc_signal<size_t>       r_icache_cc_set;                // selected set for cc update/inval
379    sc_signal<size_t>       r_icache_cc_word;               // word counter for cc update
380    sc_signal<bool>         r_icache_cc_need_write;     // activate the cache for writing
381
[468]382    // coherence clack handling
383    sc_signal<bool>         r_icache_clack_req;         // clack request
384    sc_signal<size_t>       r_icache_clack_way;             // clack way
385    sc_signal<size_t>       r_icache_clack_set;             // clack set
386
[331]387    // icache flush handling
388    sc_signal<size_t>       r_icache_flush_count;           // slot counter used for cache flush
389
390    // communication between ICACHE FSM and VCI_CMD FSM
391    sc_signal<bool>         r_icache_miss_req;           // cached read miss
392    sc_signal<bool>         r_icache_unc_req;            // uncached read miss
393
394    // communication between ICACHE FSM and DCACHE FSM
395    sc_signal<bool>             r_icache_tlb_miss_req;       // (set icache/reset dcache)
396    sc_signal<bool>         r_icache_tlb_rsp_error;      // tlb miss response error
397
[495]398
[331]399    // communication between ICACHE FSM and CC_SEND FSM
400    sc_signal<bool>         r_icache_cc_send_req;           // ICACHE cc_send request
[477]401    sc_signal<int>          r_icache_cc_send_type;          // ICACHE cc_send request type
[331]402    sc_signal<paddr_t>      r_icache_cc_send_nline;         // ICACHE cc_send nline
403    sc_signal<size_t>       r_icache_cc_send_way;           // ICACHE cc_send way
404    sc_signal<size_t>       r_icache_cc_send_updt_tab_idx;  // ICACHE cc_send update table index
[577]405   
406    // Filp-Flop in ICACHE FSM for saving the cleanup victim request
407    sc_signal<bool>         r_icache_cleanup_victim_req; 
408    sc_signal<paddr_t>      r_icache_cleanup_victim_nline;
[331]409
410    ///////////////////////////////
411    // DCACHE FSM REGISTERS
412    ///////////////////////////////
413    sc_signal<int>          r_dcache_fsm;               // state register
414    sc_signal<int>          r_dcache_fsm_cc_save;       // return state for coherence op
415    sc_signal<int>          r_dcache_fsm_scan_save;     // return state for tlb scan op
416    // registers written in P0 stage (used in P1 stage)
417    sc_signal<bool>         r_dcache_wbuf_req;          // WBUF must be written in P1 stage
418    sc_signal<bool>         r_dcache_updt_req;          // DCACHE must be updated in P1 stage
419    sc_signal<uint32_t>     r_dcache_save_vaddr;        // virtual address (from proc)
420    sc_signal<uint32_t>     r_dcache_save_wdata;        // write data (from proc)
[394]421    sc_signal<uint32_t>     r_dcache_save_be;           // byte enable (from proc)
[331]422    sc_signal<paddr_t>      r_dcache_save_paddr;        // physical address
423    sc_signal<size_t>       r_dcache_save_cache_way;    // selected way (from dcache)
424    sc_signal<size_t>       r_dcache_save_cache_set;    // selected set (from dcache)
425    sc_signal<size_t>       r_dcache_save_cache_word;   // selected word (from dcache)
426    // registers used by the Dirty bit sub-fsm
427    sc_signal<paddr_t>      r_dcache_dirty_paddr;       // PTE physical address
428    sc_signal<size_t>       r_dcache_dirty_way;         // way to invalidate in dcache
429    sc_signal<size_t>       r_dcache_dirty_set;         // set to invalidate in dcache
430
431    // communication between DCACHE FSM and VCI_CMD FSM
432    sc_signal<paddr_t>      r_dcache_vci_paddr;             // physical address for VCI command
[646]433    sc_signal<uint32_t>     r_dcache_vci_wdata;             // write unc data for VCI command
[331]434    sc_signal<bool>         r_dcache_vci_miss_req;      // read miss request
[646]435    sc_signal<bool>         r_dcache_vci_unc_req;       // uncacheable request (read/write)
436    sc_signal<uint32_t>     r_dcache_vci_unc_be;        // uncacheable byte enable
437    sc_signal<uint32_t>     r_dcache_vci_unc_write;     // uncacheable data write request
[331]438    sc_signal<bool>         r_dcache_vci_cas_req;       // atomic write request CAS
439    sc_signal<uint32_t>     r_dcache_vci_cas_old;       // previous data value for a CAS
440    sc_signal<uint32_t>     r_dcache_vci_cas_new;       // new data value for a CAS
441    sc_signal<bool>         r_dcache_vci_ll_req;        // atomic read request LL
442    sc_signal<bool>         r_dcache_vci_sc_req;        // atomic write request SC
[394]443    sc_signal<uint32_t>     r_dcache_vci_sc_data;       // SC data (command)
[331]444
[477]445    //RWT: local cas
446    sc_signal<bool>         r_cas_islocal;
447    sc_signal<size_t>       r_cas_local_way;
448    sc_signal<size_t>       r_cas_local_set;
449    sc_signal<size_t>       r_cas_local_word;
450
[331]451    // register used for XTN inval
452    sc_signal<size_t>       r_dcache_xtn_way;               // selected way (from dcache)
453    sc_signal<size_t>       r_dcache_xtn_set;               // selected set (from dcache)
454
455    // handling dcache miss
456    sc_signal<int>              r_dcache_miss_type;                 // depending on the requester
457    sc_signal<size_t>       r_dcache_miss_word;             // word index for cache update
458    sc_signal<size_t>       r_dcache_miss_way;              // selected way for cache update
459    sc_signal<size_t>       r_dcache_miss_set;              // selected set for cache update
460    sc_signal<bool>         r_dcache_miss_inval;        // coherence request matching a miss
461    sc_signal<bool>         r_dcache_miss_clack;        // waiting for a cleanup acknowledge
462
463    // handling coherence requests
464    sc_signal<size_t>       r_dcache_cc_way;                // selected way for cc update/inval
465    sc_signal<size_t>       r_dcache_cc_set;                // selected set for cc update/inval
[477]466    sc_signal<int>          r_dcache_cc_state;          // state of selected cache slot
[331]467    sc_signal<size_t>       r_dcache_cc_word;               // word counter for cc update
468    sc_signal<bool>         r_dcache_cc_need_write;     // activate the cache for writing
[477]469    sc_signal<paddr_t>      r_dcache_cc_inval_addr;     // address for a cleanup transaction
470    sc_signal<uint32_t>     r_dcache_cc_inval_data_cpt; 
[331]471
[468]472    // coherence clack handling
473    sc_signal<bool>         r_dcache_clack_req;         // clack request
474    sc_signal<size_t>       r_dcache_clack_way;             // clack way
475    sc_signal<size_t>       r_dcache_clack_set;             // clack set
476
[331]477    // dcache flush handling
478    sc_signal<size_t>       r_dcache_flush_count;           // slot counter used for cache flush
479
480    // ll response handling
481    sc_signal<size_t>       r_dcache_ll_rsp_count;          // flit counter used for ll rsp
482
483    // used by the TLB miss sub-fsm
484    sc_signal<uint32_t>     r_dcache_tlb_vaddr;             // virtual address for a tlb miss
485    sc_signal<bool>         r_dcache_tlb_ins;               // target tlb (itlb if true)
486    sc_signal<paddr_t>      r_dcache_tlb_paddr;             // physical address of pte
487    sc_signal<uint32_t>     r_dcache_tlb_pte_flags;         // pte1 or first word of pte2
488    sc_signal<uint32_t>     r_dcache_tlb_pte_ppn;           // second word of pte2
489    sc_signal<size_t>       r_dcache_tlb_cache_way;         // selected way in dcache
490    sc_signal<size_t>       r_dcache_tlb_cache_set;         // selected set in dcache
491    sc_signal<size_t>       r_dcache_tlb_cache_word;    // selected word in dcache
492    sc_signal<size_t>       r_dcache_tlb_way;               // selected way in tlb
493    sc_signal<size_t>       r_dcache_tlb_set;               // selected set in tlb
494
495    // ITLB and DTLB invalidation
496    sc_signal<paddr_t>      r_dcache_tlb_inval_line;    // line index
497    sc_signal<size_t>       r_dcache_tlb_inval_set;     // tlb set counter
498
499    // communication between DCACHE FSM and ICACHE FSM
500    sc_signal<bool>         r_dcache_xtn_req;           // xtn request (caused by processor)
501    sc_signal<int>          r_dcache_xtn_opcode;        // xtn request type
502
[495]503    // Filp-Flop in DCACHE FSM for saving the cleanup victim request
504    sc_signal<bool>         r_dcache_cleanup_victim_req; 
505    sc_signal<bool>         r_dcache_cleanup_victim_line_ncc; 
506    sc_signal<bool>         r_dcache_cleanup_victim_updt_data; 
507    sc_signal<paddr_t>      r_dcache_cleanup_victim_nline;
508
[331]509    // communication between DCACHE FSM and CC_SEND FSM
510    sc_signal<bool>         r_dcache_cc_send_req;           // DCACHE cc_send request
[477]511    sc_signal<int>          r_dcache_cc_send_type;          // DCACHE cc_send request type
[331]512    sc_signal<paddr_t>      r_dcache_cc_send_nline;         // DCACHE cc_send nline
513    sc_signal<size_t>       r_dcache_cc_send_way;           // DCACHE cc_send way
514    sc_signal<size_t>       r_dcache_cc_send_updt_tab_idx;  // DCACHE cc_send update table index
[477]515   
[767]516    // special registers for RWT
517    sc_signal<bool>         r_dcache_cc_cleanup_updt_data;     // Register for cleanup with data (wb updt)
518    sc_signal<bool>         r_dcache_cc_cleanup_line_ncc;      // Register for cleanup with data (wb updt)
519    sc_signal<bool>         r_dcache_miss_victim_no_coherence; // Register for victim in no coherence mode
520    sc_signal<bool>         r_dcache_line_no_coherence;        // Register for line current in no coherence mode
[477]521    sc_signal<bool>         r_dcache_dirty_save;             
522    sc_signal<uint32_t>     r_cc_send_cpt_word;
523    sc_signal<uint32_t>     r_dcache_miss_data_cpt;
524    sc_signal<paddr_t>      r_dcache_miss_data_addr;
525    sc_signal<uint32_t>     r_dcache_xtn_flush_data_cpt;
526    sc_signal<paddr_t>      r_dcache_xtn_flush_addr_data;
527    sc_signal<int>          r_dcache_xtn_state;
528    sc_signal<paddr_t>      r_dcache_xtn_data_addr;
529    sc_signal<uint32_t>     r_dcache_xtn_data_cpt;
[767]530    sc_signal<bool>         r_dcache_read_state;
531
[331]532    // dcache directory extension
[645]533    int                     *r_dcache_content_state; // content state of one cache line
[767]534    // Stats
535    int                     *r_dcache_dirty_word;    // use for compute number of words dirty per cleanup_data
536    bool                    *r_dcache_zombi_ncc;     // use for compute number of blocked write on ncc zombi line
[477]537    //////////////////////////////////////////////////////////////////////////////////////
[331]538
[767]539    ///////////////////////////////////
[394]540    // Physical address extension for data access
541    sc_signal<uint32_t>     r_dcache_paddr_ext;             // CP2 register (if vci_address > 32)
542
[331]543    ///////////////////////////////////
544    // VCI_CMD FSM REGISTERS
545    ///////////////////////////////////
546    sc_signal<int>          r_vci_cmd_fsm;
[394]547    sc_signal<size_t>       r_vci_cmd_min;                      // used for write bursts
548    sc_signal<size_t>       r_vci_cmd_max;                      // used for write bursts
549    sc_signal<size_t>       r_vci_cmd_cpt;                      // used for write bursts
550    sc_signal<bool>         r_vci_cmd_imiss_prio;               // round-robin between imiss & dmiss
[331]551
552    ///////////////////////////////////
553    // VCI_RSP FSM REGISTERS
554    ///////////////////////////////////
555    sc_signal<int>          r_vci_rsp_fsm;
556    sc_signal<size_t>       r_vci_rsp_cpt;
557    sc_signal<bool>         r_vci_rsp_ins_error;
558    sc_signal<bool>         r_vci_rsp_data_error;
[394]559    GenericFifo<uint32_t>   r_vci_rsp_fifo_icache;              // response FIFO to ICACHE FSM
560    GenericFifo<uint32_t>   r_vci_rsp_fifo_dcache;              // response FIFO to DCACHE FSM
[477]561   
[331]562
[477]563    //RWT
564    GenericFifo<bool>       r_vci_rsp_fifo_rpktid;
565    GenericFifo<uint32_t>   r_cc_send_data_fifo;   
566
[331]567    ///////////////////////////////////
568    //  CC_SEND FSM REGISTER
569    ///////////////////////////////////
[394]570    sc_signal<int>          r_cc_send_fsm;                  // state register
571    sc_signal<bool>         r_cc_send_last_client;          // 0 dcache / 1 icache
[331]572
573    ///////////////////////////////////
574    //  CC_RECEIVE FSM REGISTER
575    ///////////////////////////////////
[394]576    sc_signal<int>          r_cc_receive_fsm;               // state register
577    sc_signal<bool>         r_cc_receive_data_ins;          // request to : 0 dcache / 1 icache
[331]578
[394]579    // communication between CC_RECEIVE FSM and ICACHE/DCACHE FSM
580    sc_signal<size_t>       r_cc_receive_word_idx;          // word index
[331]581    GenericFifo<uint32_t>   r_cc_receive_updt_fifo_be;
582    GenericFifo<uint32_t>   r_cc_receive_updt_fifo_data;
583    GenericFifo<bool>       r_cc_receive_updt_fifo_eop;
584
585    // communication between CC_RECEIVE FSM and ICACHE FSM
[394]586    sc_signal<bool>         r_cc_receive_icache_req;        // cc_receive to icache request
[477]587    sc_signal<int>          r_cc_receive_icache_type;       // cc_receive type of request
[394]588    sc_signal<size_t>       r_cc_receive_icache_way;        // cc_receive to icache way
589    sc_signal<size_t>       r_cc_receive_icache_set;        // cc_receive to icache set
[331]590    sc_signal<size_t>       r_cc_receive_icache_updt_tab_idx;  // cc_receive update table index
[394]591    sc_signal<paddr_t>      r_cc_receive_icache_nline;      // cache line physical address
[331]592
593    // communication between CC_RECEIVE FSM and DCACHE FSM
[604]594    sc_signal<bool>         r_cc_receive_dcache_req;              // cc_receive to dcache request
595    sc_signal<int>          r_cc_receive_dcache_type;             // cc_receive type of request
596    sc_signal<size_t>       r_cc_receive_dcache_way;              // cc_receive to dcache way
597    sc_signal<size_t>       r_cc_receive_dcache_set;              // cc_receive to dcache set
598    sc_signal<size_t>       r_cc_receive_dcache_updt_tab_idx;     // cc_receive update table index
599    sc_signal<paddr_t>      r_cc_receive_dcache_nline;            // cache line physical address
600    sc_signal<bool>         r_cc_receive_dcache_inval_is_config;  // inval from memcache is config
[331]601
[468]602    ///////////////////////////////////
603    //  DSPIN CLACK INTERFACE REGISTER
604    ///////////////////////////////////
605    sc_signal<bool>         r_dspin_clack_req;
606    sc_signal<uint64_t>     r_dspin_clack_flit;
607   
[331]608    //////////////////////////////////////////////////////////////////
609    // processor, write buffer, caches , TLBs
610    //////////////////////////////////////////////////////////////////
611
612    iss_t                       r_iss;
613    MultiWriteBuffer<paddr_t>   r_wbuf;
614    GenericCache<paddr_t>       r_icache;
615    GenericCache<paddr_t>       r_dcache;
616    GenericTlb<paddr_t>         r_itlb;
617    GenericTlb<paddr_t>         r_dtlb;
618
619    //////////////////////////////////////////////////////////////////
620    // llsc registration buffer
621    //////////////////////////////////////////////////////////////////
622
623    sc_signal<paddr_t>                     r_dcache_llsc_paddr;
624    sc_signal<uint32_t>                    r_dcache_llsc_key;
625    sc_signal<uint32_t>                    r_dcache_llsc_count;
626    sc_signal<bool>                        r_dcache_llsc_valid;
627
[513]628   
629    sc_signal<bool>                        r_cache_frozen;
630
[331]631    ////////////////////////////////
632    // Activity counters
633    ////////////////////////////////
[645]634    uint32_t m_cpt_dcache_data_read;           // DCACHE DATA READ
635    uint32_t m_cpt_dcache_data_write;          // DCACHE DATA WRITE
636    uint32_t m_cpt_dcache_dir_read;            // DCACHE DIR READ
637    uint32_t m_cpt_dcache_dir_write;           // DCACHE DIR WRITE
[331]638
[645]639    uint32_t m_cpt_icache_data_read;           // ICACHE DATA READ
640    uint32_t m_cpt_icache_data_write;          // ICACHE DATA WRITE
641    uint32_t m_cpt_icache_dir_read;            // ICACHE DIR READ
642    uint32_t m_cpt_icache_dir_write;           // ICACHE DIR WRITE
[331]643
[645]644    uint32_t m_cpt_frz_cycles;                 // number of cycles where the cpu is frozen
645    uint32_t m_cpt_total_cycles;                   // total number of cycles
[331]646
647    // Cache activity counters
[645]648    uint32_t m_cpt_data_read;                  // total number of read data
649    uint32_t m_cpt_data_write;                 // total number of write data
[477]650    uint32_t m_cpt_data_write_back;
651    uint32_t m_cpt_data_cleanup;
652    uint32_t m_cpt_data_sc;
[645]653    uint32_t m_cpt_data_miss;                  // number of read miss
654    uint32_t m_cpt_ins_miss;                   // number of instruction miss
655    uint32_t m_cpt_unc_read;                   // number of read uncached
656    uint32_t m_cpt_write_cached;               // number of cached write
657    uint32_t m_cpt_ins_read;                   // number of instruction read
658    uint32_t m_cpt_ins_spc_miss;               // number of speculative instruction miss
[331]659
[645]660    uint32_t m_cost_write_frz;                 // number of frozen cycles related to write buffer
661    uint32_t m_cost_data_miss_frz;             // number of frozen cycles related to data miss
662    uint32_t m_cost_unc_read_frz;              // number of frozen cycles related to uncached read
663    uint32_t m_cost_ins_miss_frz;              // number of frozen cycles related to ins miss
[331]664
[645]665    uint32_t m_cpt_imiss_transaction;          // number of VCI instruction miss transactions
666    uint32_t m_cpt_dmiss_transaction;          // number of VCI data miss transactions
667    uint32_t m_cpt_unc_transaction;            // number of VCI uncached read transactions
668    uint32_t m_cpt_dunc_transaction;           // number of VCI uncached read transactions
669    uint32_t m_cpt_ll_transaction;             // number of VCI uncached read transactions
670    uint32_t m_cpt_write_transaction;          // number of VCI write transactions
[331]671    uint32_t m_cpt_icache_unc_transaction;
672
[645]673    uint32_t m_cost_imiss_transaction;         // cumulated duration for VCI IMISS transactions
674    uint32_t m_cost_dmiss_transaction;         // cumulated duration for VCI DMISS transactions
675    uint32_t m_cost_unc_transaction;           // cumulated duration for VCI UNC transactions
676    uint32_t m_cost_write_transaction;         // cumulated duration for VCI WRITE transactions
677    uint32_t m_cost_icache_unc_transaction;    // cumulated duration for VCI IUNC transactions
678    uint32_t m_length_write_transaction;       // cumulated length for VCI WRITE transactions
[331]679
680    // TLB activity counters
[645]681    uint32_t m_cpt_ins_tlb_read;               // number of instruction tlb read
682    uint32_t m_cpt_ins_tlb_miss;               // number of instruction tlb miss
683    uint32_t m_cpt_ins_tlb_update_acc;         // number of instruction tlb update
684    uint32_t m_cpt_ins_tlb_occup_cache;        // number of instruction tlb occupy data cache line
685    uint32_t m_cpt_ins_tlb_hit_dcache;         // number of instruction tlb hit in data cache
[331]686
[645]687    uint32_t m_cpt_data_tlb_read;              // number of data tlb read
688    uint32_t m_cpt_data_tlb_miss;              // number of data tlb miss
689    uint32_t m_cpt_data_tlb_update_acc;        // number of data tlb update
690    uint32_t m_cpt_data_tlb_update_dirty;      // number of data tlb update dirty
691    uint32_t m_cpt_data_tlb_hit_dcache;        // number of data tlb hit in data cache
692    uint32_t m_cpt_data_tlb_occup_cache;       // number of data tlb occupy data cache line
[331]693    uint32_t m_cpt_tlb_occup_dcache;
694
[645]695    uint32_t m_cost_ins_tlb_miss_frz;          // number of frozen cycles related to instruction tlb miss
696    uint32_t m_cost_data_tlb_miss_frz;         // number of frozen cycles related to data tlb miss
[331]697    uint32_t m_cost_ins_tlb_update_acc_frz;    // number of frozen cycles related to instruction tlb update acc
698    uint32_t m_cost_data_tlb_update_acc_frz;   // number of frozen cycles related to data tlb update acc
699    uint32_t m_cost_data_tlb_update_dirty_frz; // number of frozen cycles related to data tlb update dirty
700    uint32_t m_cost_ins_tlb_occup_cache_frz;   // number of frozen cycles related to instruction tlb miss operate in dcache
701    uint32_t m_cost_data_tlb_occup_cache_frz;  // number of frozen cycles related to data tlb miss operate in dcache
702
703    uint32_t m_cpt_itlbmiss_transaction;       // number of itlb miss transactions
704    uint32_t m_cpt_itlb_ll_transaction;        // number of itlb ll acc transactions
705    uint32_t m_cpt_itlb_sc_transaction;        // number of itlb sc acc transactions
706    uint32_t m_cpt_dtlbmiss_transaction;       // number of dtlb miss transactions
707    uint32_t m_cpt_dtlb_ll_transaction;        // number of dtlb ll acc transactions
708    uint32_t m_cpt_dtlb_sc_transaction;        // number of dtlb sc acc transactions
709    uint32_t m_cpt_dtlb_ll_dirty_transaction;  // number of dtlb ll dirty transactions
710    uint32_t m_cpt_dtlb_sc_dirty_transaction;  // number of dtlb sc dirty transactions
711
[645]712    uint32_t m_cost_itlbmiss_transaction;      // cumulated duration for VCI instruction TLB miss transactions
713    uint32_t m_cost_itlb_ll_transaction;       // cumulated duration for VCI instruction TLB ll acc transactions
714    uint32_t m_cost_itlb_sc_transaction;       // cumulated duration for VCI instruction TLB sc acc transactions
715    uint32_t m_cost_dtlbmiss_transaction;      // cumulated duration for VCI data TLB miss transactions
716    uint32_t m_cost_dtlb_ll_transaction;       // cumulated duration for VCI data TLB ll acc transactions
717    uint32_t m_cost_dtlb_sc_transaction;       // cumulated duration for VCI data TLB sc acc transactions
718    uint32_t m_cost_dtlb_ll_dirty_transaction; // cumulated duration for VCI data TLB ll dirty transactions
719    uint32_t m_cost_dtlb_sc_dirty_transaction; // cumulated duration for VCI data TLB sc dirty transactions
[331]720
721    // coherence activity counters
[645]722    uint32_t m_cpt_cc_update_icache;           // number of coherence update instruction commands
723    uint32_t m_cpt_cc_update_dcache;           // number of coherence update data commands
724    uint32_t m_cpt_cc_inval_icache;            // number of coherence inval instruction commands
725    uint32_t m_cpt_cc_inval_dcache;            // number of coherence inval data commands
726    uint32_t m_cpt_cc_broadcast;               // number of coherence broadcast commands
[331]727
[645]728    uint32_t m_cost_updt_data_frz;             // number of frozen cycles related to coherence update data packets
729    uint32_t m_cost_inval_ins_frz;             // number of frozen cycles related to coherence inval instruction packets
730    uint32_t m_cost_inval_data_frz;            // number of frozen cycles related to coherence inval data packets
731    uint32_t m_cost_broadcast_frz;             // number of frozen cycles related to coherence broadcast packets
[331]732
[645]733    uint32_t m_cpt_cc_cleanup_ins;             // number of coherence cleanup packets
734    uint32_t m_cpt_cc_cleanup_data;            // number of coherence cleanup packets
735    uint32_t m_cpt_cleanup_data_not_dirty;     // number of total cleanup data without extra data flits
736    uint32_t m_cpt_cleanup_data_dirty_word;    // number of total words dirty in cleanup data
737    uint32_t m_cpt_data_write_miss;            // number of total write miss
738    uint32_t m_cpt_data_write_on_zombi;        // number of frozen cycles related to blocked write on line NCC/CC ZOMBI
739    uint32_t m_cpt_data_write_on_zombi_ncc;    // number of frozen cycles related to blocked write on line NCC ZOMBI
[331]740
[645]741    uint32_t m_cpt_icleanup_transaction;       // number of instruction cleanup transactions
742    uint32_t m_cpt_dcleanup_transaction;       // number of instructinumber of data cleanup transactions
743    uint32_t m_cost_icleanup_transaction;      // cumulated duration for VCI instruction cleanup transactions
744    uint32_t m_cost_dcleanup_transaction;      // cumulated duration for VCI data cleanup transactions
[331]745
[645]746    uint32_t m_cost_ins_tlb_inval_frz;         // number of frozen cycles related to checking ins tlb invalidate
747    uint32_t m_cpt_ins_tlb_inval;              // number of ins tlb invalidate
[331]748
[645]749    uint32_t m_cost_data_tlb_inval_frz;        // number of frozen cycles related to checking data tlb invalidate
750    uint32_t m_cpt_data_tlb_inval;             // number of data tlb invalidate
[331]751
752    // FSM activity counters
753    uint32_t m_cpt_fsm_icache     [64];
754    uint32_t m_cpt_fsm_dcache     [64];
755    uint32_t m_cpt_fsm_cmd        [64];
756    uint32_t m_cpt_fsm_rsp        [64];
757    uint32_t m_cpt_fsm_cc_receive [64];
758    uint32_t m_cpt_fsm_cc_send    [64];
759
760    uint32_t m_cpt_stop_simulation;             // used to stop simulation if frozen
[432]761    bool     m_monitor_ok;                      // used to debug cache output 
762    uint32_t m_monitor_base;               
763    uint32_t m_monitor_length;             
[331]764
765protected:
766    SC_HAS_PROCESS(VciCcVCacheWrapper);
767
768public:
769    VciCcVCacheWrapper(
[346]770        sc_module_name                      name,
771        const int                           proc_id,
772        const soclib::common::MappingTable  &mtd,
773        const soclib::common::IntTab        &srcid,
774        const size_t                        cc_global_id,
775        const size_t                        itlb_ways,
776        const size_t                        itlb_sets,
777        const size_t                        dtlb_ways,
778        const size_t                        dtlb_sets,
779        const size_t                        icache_ways,
780        const size_t                        icache_sets,
781        const size_t                        icache_words,
782        const size_t                        dcache_ways,
783        const size_t                        dcache_sets,
784        const size_t                        dcache_words,
785        const size_t                        wbuf_nlines,
786        const size_t                        wbuf_nwords,
787        const size_t                        x_width,
788        const size_t                        y_width,
789        const uint32_t                      max_frozen_cycles,
790        const uint32_t                      debug_start_cycle,
791        const bool                          debug_ok );
[331]792
793    ~VciCcVCacheWrapper();
794
795    void print_cpi();
796    void print_stats();
797    void clear_stats();
798    void print_trace(size_t mode = 0);
[513]799    bool frozen();
[331]800    void cache_monitor(paddr_t addr);
[423]801    void start_monitor(paddr_t,paddr_t);
802    void stop_monitor();
[394]803    inline void iss_set_debug_mask(uint v) 
804    {
805            r_iss.set_debug_mask(v);
[331]806    }
807
808private:
809    void transition();
810    void genMoore();
811
812    soclib_static_assert((int)iss_t::SC_ATOMIC == (int)vci_param::STORE_COND_ATOMIC);
813    soclib_static_assert((int)iss_t::SC_NOT_ATOMIC == (int)vci_param::STORE_COND_NOT_ATOMIC);
814};
815
816}}
817
818#endif /* SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER_H */
819
820// Local Variables:
821// tab-width: 4
822// c-basic-offset: 4
823// c-file-offsets:((innamespace . 0)(inline-open . 0))
824// indent-tabs-mode: nil
825// End:
826
827// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
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