source: branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h @ 604

Last change on this file since 604 was 604, checked in by devigne, 9 years ago

Merge with the latest trunk (concurrent access to a register CONFIG_FSM)
Modification processing software invalidations to memcache level.

When a software memcache invalidation, it does not write the dirty data in the
XRAM (and therefore does not reserve space in the TRT). This poses a problem
when processing CLEANUP_DATA on a line NCC because CLEANUP_FSM expects to find
a placeholder in the TRT.

To overcome this problem, the flit DSPIN a multi-inval now contains a bit to
indicate that the invalidation from a control configuration (software
invalidation level memcache).

At the reception of this message invalidation in the L1 cache, it retrieves the
value of the field DSPIN IS_CONFIG. When processing invalidation (
DCACHE_CC_INVAL ), the value of this field is checked. Two scenarios are
possible:

  • 1st case : The INVAL concerns a line NCC but not from a software invalidation (IS_CONFIG = 0), the CLEANUP sent then follows the classical treatment of invalidation of a line NCC (sends a CLEANUP_NCC with or without data).
  • 2nd case : The INVAL provides a line NCC from a software invalidation (IS_CONFIG = 1) : same treatment as was CLEANUP line CC.

Thus in the case of interest (software invalidation on a line NCC), the CLEANUP
received by the memcache will be treated as one line CC.

File size: 37.3 KB
Line 
1/* -*- c++ -*-
2 *
3 * File : vci_cc_vcache_wrapper.h
4 * Copyright (c) UPMC, Lip6, SoC
5 * Authors : Alain GREINER, Yang GAO
6 * Date : 27/11/2011
7 *
8 * SOCLIB_LGPL_HEADER_BEGIN
9 *
10 * This file is part of SoCLib, GNU LGPLv2.1.
11 *
12 * SoCLib is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU Lesser General Public License as published
14 * by the Free Software Foundation; version 2.1 of the License.
15 *
16 * SoCLib is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
19 * Lesser General Public License for more details.
20 *
21 * You should have received a copy of the GNU Lesser General Public
22 * License along with SoCLib; if not, write to the Free Software
23 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
24 * 02110-1301 USA
25 *
26 * SOCLIB_LGPL_HEADER_END
27 *
28 * Maintainers: cesar.fuguet-tortolero@lip6.fr
29 *              alexandre.joannou@lip6.fr
30 */
31
32#ifndef SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER_H
33#define SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER_H
34
35#include <inttypes.h>
36#include <systemc>
37#include "caba_base_module.h"
38#include "multi_write_buffer.h"
39#include "generic_fifo.h"
40#include "generic_tlb.h"
41#include "generic_cache.h"
42#include "vci_initiator.h"
43#include "dspin_interface.h"
44#include "dspin_dhccp_param.h"
45#include "mapping_table.h"
46#include "static_assert.h"
47#include "iss2.h"
48
49#define LLSC_TIMEOUT    10000
50
51namespace soclib {
52namespace caba {
53
54using namespace sc_core;
55
56////////////////////////////////////////////
57template<typename vci_param, 
58         size_t   dspin_in_width,
59         size_t   dspin_out_width,
60         typename iss_t>
61class VciCcVCacheWrapper
62////////////////////////////////////////////
63    : public soclib::caba::BaseModule
64{
65
66    typedef typename vci_param::fast_addr_t  paddr_t;
67
68    enum icache_fsm_state_e
69    {
70        ICACHE_IDLE,
71        // handling XTN processor requests
72        ICACHE_XTN_TLB_FLUSH,
73        ICACHE_XTN_CACHE_FLUSH,
74        ICACHE_XTN_CACHE_FLUSH_GO,
75        ICACHE_XTN_TLB_INVAL,
76        ICACHE_XTN_CACHE_INVAL_VA,
77        ICACHE_XTN_CACHE_INVAL_PA,
78        ICACHE_XTN_CACHE_INVAL_GO,
79        // handling tlb miss
80        ICACHE_TLB_WAIT,
81        // handling cache miss
82        ICACHE_MISS_SELECT,
83        ICACHE_MISS_CLEAN,
84        ICACHE_MISS_WAIT,
85        ICACHE_MISS_DATA_UPDT,
86        ICACHE_MISS_DIR_UPDT,
87        // handling unc read
88        ICACHE_UNC_WAIT,
89        // handling coherence requests
90        ICACHE_CC_CHECK,
91        ICACHE_CC_UPDT,
92        ICACHE_CC_INVAL,
93    };
94
95    enum dcache_fsm_state_e
96    {
97        DCACHE_IDLE,
98        // handling itlb & dtlb miss
99        DCACHE_TLB_MISS,
100        DCACHE_TLB_PTE1_GET,
101        DCACHE_TLB_PTE1_SELECT,
102        DCACHE_TLB_PTE1_UPDT,
103        DCACHE_TLB_PTE2_GET,
104        DCACHE_TLB_PTE2_SELECT,
105        DCACHE_TLB_PTE2_UPDT,
106        DCACHE_TLB_LR_UPDT,
107        DCACHE_TLB_LR_WAIT,
108        DCACHE_TLB_RETURN,
109            // handling processor XTN requests
110        DCACHE_XTN_SWITCH,
111        DCACHE_XTN_SYNC,
112        DCACHE_XTN_IC_INVAL_VA,
113        DCACHE_XTN_IC_FLUSH,
114        DCACHE_XTN_IC_INVAL_PA,
115        DCACHE_XTN_IT_INVAL,
116        DCACHE_XTN_DC_FLUSH,
117        DCACHE_XTN_DC_FLUSH_DATA,
118        DCACHE_XTN_DC_FLUSH_GO,
119        DCACHE_XTN_DC_INVAL_VA,
120        DCACHE_XTN_DC_INVAL_PA,
121        DCACHE_XTN_DC_INVAL_END,
122        DCACHE_XTN_DC_INVAL_GO,
123        DCACHE_XTN_DC_INVAL_DATA,
124        DCACHE_XTN_DT_INVAL,
125        //handling dirty bit update
126        DCACHE_DIRTY_GET_PTE,
127        DCACHE_DIRTY_WAIT,
128            // handling processor miss requests
129        DCACHE_MISS_SELECT,
130        DCACHE_MISS_CLEAN,
131        DCACHE_MISS_DATA,
132        DCACHE_MISS_WAIT,
133        DCACHE_MISS_DATA_UPDT,
134        DCACHE_MISS_DIR_UPDT,
135        // handling processor unc, ll and sc requests
136        DCACHE_UNC_WAIT,
137        DCACHE_LL_WAIT,
138        DCACHE_SC_WAIT,
139        // handling coherence requests
140        DCACHE_CC_CHECK,
141        DCACHE_CC_UPDT,
142        DCACHE_CC_INVAL,
143        DCACHE_CC_INVAL_DATA,
144        // handling TLB inval (after a coherence or XTN request)
145        DCACHE_INVAL_TLB_SCAN,
146    };
147
148    enum cmd_fsm_state_e
149    {
150        CMD_IDLE,
151        CMD_INS_MISS,
152        CMD_INS_UNC,
153        CMD_DATA_MISS,
154        CMD_DATA_UNC,
155        CMD_DATA_WRITE,
156        CMD_DATA_LL,
157        CMD_DATA_SC,
158        CMD_DATA_CAS,
159    };
160
161    enum rsp_fsm_state_e
162    {
163        RSP_IDLE,
164        RSP_INS_MISS,
165        RSP_INS_UNC,
166        RSP_DATA_MISS,
167        RSP_DATA_UNC,
168        RSP_DATA_LL,
169        RSP_DATA_WRITE,
170    };
171
172    enum cc_receive_fsm_state_e
173    {
174        CC_RECEIVE_IDLE,
175        CC_RECEIVE_BRDCAST_HEADER,
176        CC_RECEIVE_BRDCAST_NLINE,
177        CC_RECEIVE_INS_INVAL_HEADER,
178        CC_RECEIVE_INS_INVAL_NLINE,
179        CC_RECEIVE_INS_UPDT_HEADER,
180        CC_RECEIVE_INS_UPDT_NLINE,
181        CC_RECEIVE_DATA_INVAL_HEADER,
182        CC_RECEIVE_DATA_INVAL_NLINE,
183        CC_RECEIVE_DATA_UPDT_HEADER,
184        CC_RECEIVE_DATA_UPDT_NLINE,
185        CC_RECEIVE_INS_UPDT_DATA,
186        CC_RECEIVE_DATA_UPDT_DATA,
187    };
188
189    enum cc_send_fsm_state_e
190    {
191        CC_SEND_IDLE,
192        CC_SEND_CLEANUP_1,
193        CC_SEND_CLEANUP_2,
194        CC_SEND_CLEANUP_DATA_UPDT,
195        CC_SEND_MULTI_ACK,
196    };
197
198    /* transaction type, pktid field */
199    enum transaction_type_e
200    {
201        // b3 unused
202        // b2 READ / NOT READ
203        // if READ
204        //  b1 DATA / INS
205        //  b0 UNC / MISS
206        // else
207        //  b1 accÚs table llsc type SW / other
208        //  b2 WRITE/CAS/LL/SC
209        TYPE_READ_DATA_UNC          = 0x0,
210        TYPE_READ_DATA_MISS         = 0x1,
211        TYPE_READ_INS_UNC           = 0x2,
212        TYPE_READ_INS_MISS          = 0x3,
213        TYPE_WRITE                  = 0x4,
214        TYPE_CAS                    = 0x5,
215        TYPE_LL                     = 0x6,
216        TYPE_SC                     = 0x7
217    };
218
219    /* SC return values */
220    enum sc_status_type_e
221    {
222        SC_SUCCESS  =   0x00000000,
223        SC_FAIL     =   0x00000001
224    };
225
226    // cc_send_type
227    typedef enum 
228    {
229        CC_TYPE_CLEANUP,
230        CC_TYPE_MULTI_ACK,
231    } cc_send_t;
232
233    // cc_receive_type
234    typedef enum 
235    {
236        CC_TYPE_CLACK,
237        CC_TYPE_BRDCAST,
238        CC_TYPE_INVAL,
239        CC_TYPE_UPDT,
240    } cc_receive_t;
241
242    // TLB Mode : ITLB / DTLB / ICACHE / DCACHE
243    enum 
244    {
245        INS_TLB_MASK    = 0x8,
246        DATA_TLB_MASK   = 0x4,
247        INS_CACHE_MASK  = 0x2,
248        DATA_CACHE_MASK = 0x1,
249    };
250
251    // Error Type
252    enum mmu_error_type_e
253    {
254        MMU_NONE                      = 0x0000, // None
255        MMU_WRITE_PT1_UNMAPPED        = 0x0001, // Write & Page fault on PT1
256        MMU_WRITE_PT2_UNMAPPED        = 0x0002, // Write & Page fault on PT2
257        MMU_WRITE_PRIVILEGE_VIOLATION = 0x0004, // Write & Protected access in user mode
258        MMU_WRITE_ACCES_VIOLATION     = 0x0008, // Write to non writable page
259        MMU_WRITE_UNDEFINED_XTN       = 0x0020, // Write & undefined external access
260        MMU_WRITE_PT1_ILLEGAL_ACCESS  = 0x0040, // Write & Bus Error accessing PT1
261        MMU_WRITE_PT2_ILLEGAL_ACCESS  = 0x0080, // Write & Bus Error accessing PT2
262        MMU_WRITE_DATA_ILLEGAL_ACCESS = 0x0100, // Write & Bus Error in cache access
263        MMU_READ_PT1_UNMAPPED         = 0x1001, // Read & Page fault on PT1
264        MMU_READ_PT2_UNMAPPED         = 0x1002, // Read & Page fault on PT2
265        MMU_READ_PRIVILEGE_VIOLATION  = 0x1004, // Read & Protected access in user mode
266        MMU_READ_EXEC_VIOLATION       = 0x1010, // Read & Exec access to a non exec page
267        MMU_READ_UNDEFINED_XTN        = 0x1020, // Read & Undefined external access
268        MMU_READ_PT1_ILLEGAL_ACCESS   = 0x1040, // Read & Bus Error accessing PT1
269        MMU_READ_PT2_ILLEGAL_ACCESS   = 0x1080, // Read & Bus Error accessing PT2
270        MMU_READ_DATA_ILLEGAL_ACCESS  = 0x1100, // Read & Bus Error in cache access
271    };
272
273    // miss types for data cache
274    enum dcache_miss_type_e
275    {
276        PTE1_MISS,
277        PTE2_MISS,
278        PROC_MISS,
279    };
280
281    enum transaction_type_d_e
282    {
283        // b0 : 1 if cached
284        // b1 : 1 if instruction
285        TYPE_DATA_UNC     = 0x0,
286        TYPE_DATA_MISS    = 0x1,
287        TYPE_INS_UNC      = 0x2,
288        TYPE_INS_MISS     = 0x3,
289    };
290
291    //////////////////MODIFIED////////////////
292    enum content_line_cache_status_e
293    {
294        LINE_CACHE_DATA_NOT_DIRTY,
295        LINE_CACHE_DATA_DIRTY,
296        LINE_CACHE_IN_TLB,
297        LINE_CACHE_CONTAINS_PTD,
298    };
299    //////////////////////////////////////////
300
301public:
302    sc_in<bool>                                p_clk;
303    sc_in<bool>                                p_resetn;
304    sc_in<bool>                                p_irq[iss_t::n_irq];
305    soclib::caba::VciInitiator<vci_param>      p_vci;
306    soclib::caba::DspinInput<dspin_in_width>   p_dspin_m2p;
307    soclib::caba::DspinOutput<dspin_out_width> p_dspin_p2m;
308    soclib::caba::DspinInput<dspin_in_width>   p_dspin_clack;
309
310private:
311
312    // STRUCTURAL PARAMETERS
313    soclib::common::AddressDecodingTable<uint64_t, bool> m_cacheability_table;
314
315    const size_t                        m_srcid;
316    const size_t                        m_cc_global_id;
317    const size_t                        m_nline_width;
318    const size_t                                                m_itlb_ways;
319    const size_t                                                m_itlb_sets;
320    const size_t                                                m_dtlb_ways;
321    const size_t                                                m_dtlb_sets;
322    const size_t                                                m_icache_ways;
323    const size_t                                                m_icache_sets;
324    const paddr_t                                               m_icache_yzmask;
325    const size_t                                                m_icache_words;
326    const size_t                                                m_dcache_ways;
327    const size_t                                                m_dcache_sets;
328    const paddr_t                                               m_dcache_yzmask;
329    const size_t                                                m_dcache_words;
330    const size_t                        m_x_width;
331    const size_t                        m_y_width;
332    const size_t                        m_proc_id;
333    const uint32_t                                              m_max_frozen_cycles;
334    const size_t                                                m_paddr_nbits;
335    uint32_t                            m_debug_start_cycle;
336    bool                                m_debug_ok;
337
338    ////////////////////////////////////////
339    // Communication with processor ISS
340    ////////////////////////////////////////
341    typename iss_t::InstructionRequest  m_ireq;
342    typename iss_t::InstructionResponse m_irsp;
343    typename iss_t::DataRequest         m_dreq;
344    typename iss_t::DataResponse        m_drsp;
345
346    /////////////////////////////////////////////
347    // debug variables
348    /////////////////////////////////////////////
349    bool                                m_debug_previous_i_hit;
350    bool                                m_debug_previous_d_hit;
351    bool                                m_debug_activated;
352
353    ///////////////////////////////
354    // Software visible REGISTERS
355    ///////////////////////////////
356    sc_signal<uint32_t>     r_mmu_ptpr;                 // page table pointer register
357    sc_signal<uint32_t>     r_mmu_mode;                 // mmu mode register
358    sc_signal<uint32_t>     r_mmu_word_lo;              // mmu misc data low
359    sc_signal<uint32_t>     r_mmu_word_hi;              // mmu misc data hight
360    sc_signal<uint32_t>     r_mmu_ibvar;                // mmu bad instruction address
361    sc_signal<uint32_t>     r_mmu_dbvar;                // mmu bad data address
362    sc_signal<uint32_t>     r_mmu_ietr;                 // mmu instruction error type
363    sc_signal<uint32_t>     r_mmu_detr;                 // mmu data error type
364    uint32_t                r_mmu_params;                       // read-only
365    uint32_t                r_mmu_release;                      // read_only
366
367
368    //////////////////////////////
369    // ICACHE FSM REGISTERS
370    //////////////////////////////
371    sc_signal<int>          r_icache_fsm;               // state register
372    sc_signal<int>          r_icache_fsm_save;          // return state for coherence op
373    sc_signal<paddr_t>      r_icache_vci_paddr;         // physical address
374    sc_signal<uint32_t>     r_icache_vaddr_save;        // virtual address from processor
375
376    // icache miss handling
377    sc_signal<size_t>       r_icache_miss_way;              // selected way for cache update
378    sc_signal<size_t>       r_icache_miss_set;              // selected set for cache update
379    sc_signal<size_t>       r_icache_miss_word;             // word index ( cache update)
380    sc_signal<bool>         r_icache_miss_inval;        // coherence request matching a miss
381    sc_signal<bool>         r_icache_miss_clack;        // waiting for a cleanup acknowledge
382
383    // coherence request handling
384    sc_signal<size_t>       r_icache_cc_way;                // selected way for cc update/inval
385    sc_signal<size_t>       r_icache_cc_set;                // selected set for cc update/inval
386    sc_signal<size_t>       r_icache_cc_word;               // word counter for cc update
387    sc_signal<bool>         r_icache_cc_need_write;     // activate the cache for writing
388
389    // coherence clack handling
390    sc_signal<bool>         r_icache_clack_req;         // clack request
391    sc_signal<size_t>       r_icache_clack_way;             // clack way
392    sc_signal<size_t>       r_icache_clack_set;             // clack set
393
394    // icache flush handling
395    sc_signal<size_t>       r_icache_flush_count;           // slot counter used for cache flush
396
397    // communication between ICACHE FSM and VCI_CMD FSM
398    sc_signal<bool>         r_icache_miss_req;           // cached read miss
399    sc_signal<bool>         r_icache_unc_req;            // uncached read miss
400
401    // communication between ICACHE FSM and DCACHE FSM
402    sc_signal<bool>             r_icache_tlb_miss_req;       // (set icache/reset dcache)
403    sc_signal<bool>         r_icache_tlb_rsp_error;      // tlb miss response error
404
405
406    // communication between ICACHE FSM and CC_SEND FSM
407    sc_signal<bool>         r_icache_cc_send_req;           // ICACHE cc_send request
408    sc_signal<int>          r_icache_cc_send_type;          // ICACHE cc_send request type
409    sc_signal<paddr_t>      r_icache_cc_send_nline;         // ICACHE cc_send nline
410    sc_signal<size_t>       r_icache_cc_send_way;           // ICACHE cc_send way
411    sc_signal<size_t>       r_icache_cc_send_updt_tab_idx;  // ICACHE cc_send update table index
412   
413    // Filp-Flop in ICACHE FSM for saving the cleanup victim request
414    sc_signal<bool>         r_icache_cleanup_victim_req; 
415    sc_signal<paddr_t>      r_icache_cleanup_victim_nline;
416
417    ///////////////////////////////
418    // DCACHE FSM REGISTERS
419    ///////////////////////////////
420    sc_signal<int>          r_dcache_fsm;               // state register
421    sc_signal<int>          r_dcache_fsm_cc_save;       // return state for coherence op
422    sc_signal<int>          r_dcache_fsm_scan_save;     // return state for tlb scan op
423    // registers written in P0 stage (used in P1 stage)
424    sc_signal<bool>         r_dcache_wbuf_req;          // WBUF must be written in P1 stage
425    sc_signal<bool>         r_dcache_updt_req;          // DCACHE must be updated in P1 stage
426    sc_signal<uint32_t>     r_dcache_save_vaddr;        // virtual address (from proc)
427    sc_signal<uint32_t>     r_dcache_save_wdata;        // write data (from proc)
428    sc_signal<uint32_t>     r_dcache_save_be;           // byte enable (from proc)
429    sc_signal<paddr_t>      r_dcache_save_paddr;        // physical address
430    sc_signal<bool>         r_dcache_save_cacheable;    // address cacheable
431    sc_signal<size_t>       r_dcache_save_cache_way;    // selected way (from dcache)
432    sc_signal<size_t>       r_dcache_save_cache_set;    // selected set (from dcache)
433    sc_signal<size_t>       r_dcache_save_cache_word;   // selected word (from dcache)
434    // registers used by the Dirty bit sub-fsm
435    sc_signal<paddr_t>      r_dcache_dirty_paddr;       // PTE physical address
436    sc_signal<size_t>       r_dcache_dirty_way;         // way to invalidate in dcache
437    sc_signal<size_t>       r_dcache_dirty_set;         // set to invalidate in dcache
438
439    // communication between DCACHE FSM and VCI_CMD FSM
440    sc_signal<paddr_t>      r_dcache_vci_paddr;             // physical address for VCI command
441    sc_signal<bool>         r_dcache_vci_miss_req;      // read miss request
442    sc_signal<bool>         r_dcache_vci_unc_req;       // uncacheable read request
443    sc_signal<uint32_t>     r_dcache_vci_unc_be;        // uncacheable read byte enable
444    sc_signal<bool>         r_dcache_vci_cas_req;       // atomic write request CAS
445    sc_signal<uint32_t>     r_dcache_vci_cas_old;       // previous data value for a CAS
446    sc_signal<uint32_t>     r_dcache_vci_cas_new;       // new data value for a CAS
447    sc_signal<bool>         r_dcache_vci_ll_req;        // atomic read request LL
448    sc_signal<bool>         r_dcache_vci_sc_req;        // atomic write request SC
449    sc_signal<uint32_t>     r_dcache_vci_sc_data;       // SC data (command)
450
451    //RWT: local cas
452    sc_signal<bool>         r_cas_islocal;
453    sc_signal<size_t>       r_cas_local_way;
454    sc_signal<size_t>       r_cas_local_set;
455    sc_signal<size_t>       r_cas_local_word;
456
457    // register used for XTN inval
458    sc_signal<size_t>       r_dcache_xtn_way;               // selected way (from dcache)
459    sc_signal<size_t>       r_dcache_xtn_set;               // selected set (from dcache)
460
461    // write buffer state extension
462    sc_signal<bool>         r_dcache_pending_unc_write; // pending uncacheable write in WBUF
463
464    // handling dcache miss
465    sc_signal<int>              r_dcache_miss_type;                 // depending on the requester
466    sc_signal<size_t>       r_dcache_miss_word;             // word index for cache update
467    sc_signal<size_t>       r_dcache_miss_way;              // selected way for cache update
468    sc_signal<size_t>       r_dcache_miss_set;              // selected set for cache update
469    sc_signal<bool>         r_dcache_miss_inval;        // coherence request matching a miss
470    sc_signal<bool>         r_dcache_miss_clack;        // waiting for a cleanup acknowledge
471
472    // handling coherence requests
473    sc_signal<size_t>       r_dcache_cc_way;                // selected way for cc update/inval
474    sc_signal<size_t>       r_dcache_cc_set;                // selected set for cc update/inval
475    sc_signal<int>          r_dcache_cc_state;          // state of selected cache slot
476    sc_signal<size_t>       r_dcache_cc_word;               // word counter for cc update
477    sc_signal<bool>         r_dcache_cc_need_write;     // activate the cache for writing
478    sc_signal<paddr_t>      r_dcache_cc_inval_addr;     // address for a cleanup transaction
479    sc_signal<uint32_t>     r_dcache_cc_inval_data_cpt; 
480
481    // coherence clack handling
482    sc_signal<bool>         r_dcache_clack_req;         // clack request
483    sc_signal<size_t>       r_dcache_clack_way;             // clack way
484    sc_signal<size_t>       r_dcache_clack_set;             // clack set
485
486    // dcache flush handling
487    sc_signal<size_t>       r_dcache_flush_count;           // slot counter used for cache flush
488
489    // ll response handling
490    sc_signal<size_t>       r_dcache_ll_rsp_count;          // flit counter used for ll rsp
491
492    // used by the TLB miss sub-fsm
493    sc_signal<uint32_t>     r_dcache_tlb_vaddr;             // virtual address for a tlb miss
494    sc_signal<bool>         r_dcache_tlb_ins;               // target tlb (itlb if true)
495    sc_signal<paddr_t>      r_dcache_tlb_paddr;             // physical address of pte
496    sc_signal<uint32_t>     r_dcache_tlb_pte_flags;         // pte1 or first word of pte2
497    sc_signal<uint32_t>     r_dcache_tlb_pte_ppn;           // second word of pte2
498    sc_signal<size_t>       r_dcache_tlb_cache_way;         // selected way in dcache
499    sc_signal<size_t>       r_dcache_tlb_cache_set;         // selected set in dcache
500    sc_signal<size_t>       r_dcache_tlb_cache_word;    // selected word in dcache
501    sc_signal<size_t>       r_dcache_tlb_way;               // selected way in tlb
502    sc_signal<size_t>       r_dcache_tlb_set;               // selected set in tlb
503
504    // ITLB and DTLB invalidation
505    sc_signal<paddr_t>      r_dcache_tlb_inval_line;    // line index
506    sc_signal<size_t>       r_dcache_tlb_inval_set;     // tlb set counter
507
508    // communication between DCACHE FSM and ICACHE FSM
509    sc_signal<bool>         r_dcache_xtn_req;           // xtn request (caused by processor)
510    sc_signal<int>          r_dcache_xtn_opcode;        // xtn request type
511
512    // Filp-Flop in DCACHE FSM for saving the cleanup victim request
513    sc_signal<bool>         r_dcache_cleanup_victim_req; 
514    sc_signal<bool>         r_dcache_cleanup_victim_line_ncc; 
515    sc_signal<bool>         r_dcache_cleanup_victim_updt_data; 
516    sc_signal<paddr_t>      r_dcache_cleanup_victim_nline;
517
518    // communication between DCACHE FSM and CC_SEND FSM
519    sc_signal<bool>         r_dcache_cc_send_req;           // DCACHE cc_send request
520    sc_signal<int>          r_dcache_cc_send_type;          // DCACHE cc_send request type
521    sc_signal<paddr_t>      r_dcache_cc_send_nline;         // DCACHE cc_send nline
522    sc_signal<size_t>       r_dcache_cc_send_way;           // DCACHE cc_send way
523    sc_signal<size_t>       r_dcache_cc_send_updt_tab_idx;  // DCACHE cc_send update table index
524   
525    // special registers for ODCCP/RWT
526    sc_signal<bool>         r_dcache_cc_cleanup_updt_data;          // Register for cleanup with data (wb updt)
527    sc_signal<bool>         r_dcache_cc_cleanup_line_ncc;          // Register for cleanup with data (wb updt)
528    sc_signal<bool>         r_dcache_miss_victim_no_coherence;      // Register for victim in no coherence mode
529    sc_signal<bool>         r_dcache_line_no_coherence;             // Register for line current in no coherence mode
530    sc_signal<bool>         r_dcache_dirty_save;             
531    sc_signal<uint32_t>     r_cc_send_cpt_word;
532    sc_signal<uint32_t>     r_dcache_miss_data_cpt;
533    sc_signal<paddr_t>      r_dcache_miss_data_addr;
534    sc_signal<uint32_t>     r_dcache_xtn_flush_data_cpt;
535    sc_signal<paddr_t>      r_dcache_xtn_flush_addr_data;
536    sc_signal<int>          r_dcache_xtn_state;
537    sc_signal<paddr_t>      r_dcache_xtn_data_addr;
538    sc_signal<uint32_t>     r_dcache_xtn_data_cpt;
539    // dcache directory extension
540    ///////////////////////////MODIFIED///////////////////////////////////////////////////
541    //bool                    *r_dcache_in_tlb;           // copy exist in dtlb or itlb
542    //bool                    *r_dcache_contains_ptd;     // cache line contains a PTD
543    int                     *r_dcache_content_state;    // content state of one cache line
544    int                     *r_dcache_dirty_word;    // content state of one cache line
545    //////////////////////////////////////////////////////////////////////////////////////
546
547    //RWT
548    sc_signal<bool>         r_dcache_read_state;
549   
550     ///////////////////////////////////
551    // Physical address extension for data access
552    sc_signal<uint32_t>     r_dcache_paddr_ext;             // CP2 register (if vci_address > 32)
553
554    ///////////////////////////////////
555    // VCI_CMD FSM REGISTERS
556    ///////////////////////////////////
557    sc_signal<int>          r_vci_cmd_fsm;
558    sc_signal<size_t>       r_vci_cmd_min;                      // used for write bursts
559    sc_signal<size_t>       r_vci_cmd_max;                      // used for write bursts
560    sc_signal<size_t>       r_vci_cmd_cpt;                      // used for write bursts
561    sc_signal<bool>         r_vci_cmd_imiss_prio;               // round-robin between imiss & dmiss
562
563    ///////////////////////////////////
564    // VCI_RSP FSM REGISTERS
565    ///////////////////////////////////
566    sc_signal<int>          r_vci_rsp_fsm;
567    sc_signal<size_t>       r_vci_rsp_cpt;
568    sc_signal<bool>         r_vci_rsp_ins_error;
569    sc_signal<bool>         r_vci_rsp_data_error;
570    GenericFifo<uint32_t>   r_vci_rsp_fifo_icache;              // response FIFO to ICACHE FSM
571    GenericFifo<uint32_t>   r_vci_rsp_fifo_dcache;              // response FIFO to DCACHE FSM
572   
573
574    //RWT
575    GenericFifo<bool>       r_vci_rsp_fifo_rpktid;
576
577    GenericFifo<uint32_t>   r_cc_send_data_fifo;   
578
579    ///////////////////////////////////
580    //  CC_SEND FSM REGISTER
581    ///////////////////////////////////
582    sc_signal<int>          r_cc_send_fsm;                  // state register
583    sc_signal<bool>         r_cc_send_last_client;          // 0 dcache / 1 icache
584
585    ///////////////////////////////////
586    //  CC_RECEIVE FSM REGISTER
587    ///////////////////////////////////
588    sc_signal<int>          r_cc_receive_fsm;               // state register
589    sc_signal<bool>         r_cc_receive_data_ins;          // request to : 0 dcache / 1 icache
590
591    // communication between CC_RECEIVE FSM and ICACHE/DCACHE FSM
592    sc_signal<size_t>       r_cc_receive_word_idx;          // word index
593    GenericFifo<uint32_t>   r_cc_receive_updt_fifo_be;
594    GenericFifo<uint32_t>   r_cc_receive_updt_fifo_data;
595    GenericFifo<bool>       r_cc_receive_updt_fifo_eop;
596
597    // communication between CC_RECEIVE FSM and ICACHE FSM
598    sc_signal<bool>         r_cc_receive_icache_req;        // cc_receive to icache request
599    sc_signal<int>          r_cc_receive_icache_type;       // cc_receive type of request
600    sc_signal<size_t>       r_cc_receive_icache_way;        // cc_receive to icache way
601    sc_signal<size_t>       r_cc_receive_icache_set;        // cc_receive to icache set
602    sc_signal<size_t>       r_cc_receive_icache_updt_tab_idx;  // cc_receive update table index
603    sc_signal<paddr_t>      r_cc_receive_icache_nline;      // cache line physical address
604
605    // communication between CC_RECEIVE FSM and DCACHE FSM
606    sc_signal<bool>         r_cc_receive_dcache_req;              // cc_receive to dcache request
607    sc_signal<int>          r_cc_receive_dcache_type;             // cc_receive type of request
608    sc_signal<size_t>       r_cc_receive_dcache_way;              // cc_receive to dcache way
609    sc_signal<size_t>       r_cc_receive_dcache_set;              // cc_receive to dcache set
610    sc_signal<size_t>       r_cc_receive_dcache_updt_tab_idx;     // cc_receive update table index
611    sc_signal<paddr_t>      r_cc_receive_dcache_nline;            // cache line physical address
612    sc_signal<bool>         r_cc_receive_dcache_inval_is_config;  // inval from memcache is config
613
614    ///////////////////////////////////
615    //  DSPIN CLACK INTERFACE REGISTER
616    ///////////////////////////////////
617    sc_signal<bool>         r_dspin_clack_req;
618    sc_signal<uint64_t>     r_dspin_clack_flit;
619   
620    //////////////////////////////////////////////////////////////////
621    // processor, write buffer, caches , TLBs
622    //////////////////////////////////////////////////////////////////
623
624    iss_t                       r_iss;
625    MultiWriteBuffer<paddr_t>   r_wbuf;
626    GenericCache<paddr_t>       r_icache;
627    GenericCache<paddr_t>       r_dcache;
628    GenericTlb<paddr_t>         r_itlb;
629    GenericTlb<paddr_t>         r_dtlb;
630
631    //////////////////////////////////////////////////////////////////
632    // llsc registration buffer
633    //////////////////////////////////////////////////////////////////
634
635    sc_signal<paddr_t>                     r_dcache_llsc_paddr;
636    sc_signal<uint32_t>                    r_dcache_llsc_key;
637    sc_signal<uint32_t>                    r_dcache_llsc_count;
638    sc_signal<bool>                        r_dcache_llsc_valid;
639
640   
641    sc_signal<bool>                        r_cache_frozen;
642
643    ////////////////////////////////
644    // Activity counters
645    ////////////////////////////////
646    uint32_t m_cpt_dcache_data_read;        // DCACHE DATA READ
647    uint32_t m_cpt_dcache_data_write;       // DCACHE DATA WRITE
648    uint32_t m_cpt_dcache_dir_read;         // DCACHE DIR READ
649    uint32_t m_cpt_dcache_dir_write;        // DCACHE DIR WRITE
650
651    uint32_t m_cpt_icache_data_read;        // ICACHE DATA READ
652    uint32_t m_cpt_icache_data_write;       // ICACHE DATA WRITE
653    uint32_t m_cpt_icache_dir_read;         // ICACHE DIR READ
654    uint32_t m_cpt_icache_dir_write;        // ICACHE DIR WRITE
655
656    uint32_t m_cpt_frz_cycles;              // number of cycles where the cpu is frozen
657    uint32_t m_cpt_total_cycles;                // total number of cycles
658
659    // Cache activity counters
660    uint32_t m_cpt_data_read;               // total number of read data
661    uint32_t m_cpt_data_write;              // total number of write data
662    uint32_t m_cpt_data_write_back;
663    uint32_t m_cpt_data_cleanup;
664    uint32_t m_cpt_data_sc;
665    uint32_t m_cpt_data_miss;               // number of read miss
666    uint32_t m_cpt_ins_miss;                // number of instruction miss
667    uint32_t m_cpt_unc_read;                // number of read uncached
668    uint32_t m_cpt_write_cached;            // number of cached write
669    uint32_t m_cpt_ins_read;                // number of instruction read
670    uint32_t m_cpt_ins_spc_miss;            // number of speculative instruction miss
671
672    uint32_t m_cost_write_frz;              // number of frozen cycles related to write buffer
673    uint32_t m_cost_data_miss_frz;          // number of frozen cycles related to data miss
674    uint32_t m_cost_unc_read_frz;           // number of frozen cycles related to uncached read
675    uint32_t m_cost_ins_miss_frz;           // number of frozen cycles related to ins miss
676
677    uint32_t m_cpt_imiss_transaction;       // number of VCI instruction miss transactions
678    uint32_t m_cpt_dmiss_transaction;       // number of VCI data miss transactions
679    uint32_t m_cpt_unc_transaction;         // number of VCI uncached read transactions
680    uint32_t m_cpt_dunc_transaction;         // number of VCI uncached read transactions
681    uint32_t m_cpt_ll_transaction;         // number of VCI uncached read transactions
682    uint32_t m_cpt_write_transaction;       // number of VCI write transactions
683    uint32_t m_cpt_icache_unc_transaction;
684
685    uint32_t m_cost_imiss_transaction;      // cumulated duration for VCI IMISS transactions
686    uint32_t m_cost_dmiss_transaction;      // cumulated duration for VCI DMISS transactions
687    uint32_t m_cost_unc_transaction;        // cumulated duration for VCI UNC transactions
688    uint32_t m_cost_write_transaction;      // cumulated duration for VCI WRITE transactions
689    uint32_t m_cost_icache_unc_transaction; // cumulated duration for VCI IUNC transactions
690    uint32_t m_length_write_transaction;    // cumulated length for VCI WRITE transactions
691
692    // TLB activity counters
693    uint32_t m_cpt_ins_tlb_read;            // number of instruction tlb read
694    uint32_t m_cpt_ins_tlb_miss;            // number of instruction tlb miss
695    uint32_t m_cpt_ins_tlb_update_acc;      // number of instruction tlb update
696    uint32_t m_cpt_ins_tlb_occup_cache;     // number of instruction tlb occupy data cache line
697    uint32_t m_cpt_ins_tlb_hit_dcache;      // number of instruction tlb hit in data cache
698
699    uint32_t m_cpt_data_tlb_read;           // number of data tlb read
700    uint32_t m_cpt_data_tlb_miss;           // number of data tlb miss
701    uint32_t m_cpt_data_tlb_update_acc;     // number of data tlb update
702    uint32_t m_cpt_data_tlb_update_dirty;   // number of data tlb update dirty
703    uint32_t m_cpt_data_tlb_hit_dcache;     // number of data tlb hit in data cache
704    uint32_t m_cpt_data_tlb_occup_cache;    // number of data tlb occupy data cache line
705    uint32_t m_cpt_tlb_occup_dcache;
706
707    uint32_t m_cost_ins_tlb_miss_frz;       // number of frozen cycles related to instruction tlb miss
708    uint32_t m_cost_data_tlb_miss_frz;      // number of frozen cycles related to data tlb miss
709    uint32_t m_cost_ins_tlb_update_acc_frz;    // number of frozen cycles related to instruction tlb update acc
710    uint32_t m_cost_data_tlb_update_acc_frz;   // number of frozen cycles related to data tlb update acc
711    uint32_t m_cost_data_tlb_update_dirty_frz; // number of frozen cycles related to data tlb update dirty
712    uint32_t m_cost_ins_tlb_occup_cache_frz;   // number of frozen cycles related to instruction tlb miss operate in dcache
713    uint32_t m_cost_data_tlb_occup_cache_frz;  // number of frozen cycles related to data tlb miss operate in dcache
714
715    uint32_t m_cpt_itlbmiss_transaction;       // number of itlb miss transactions
716    uint32_t m_cpt_itlb_ll_transaction;        // number of itlb ll acc transactions
717    uint32_t m_cpt_itlb_sc_transaction;        // number of itlb sc acc transactions
718    uint32_t m_cpt_dtlbmiss_transaction;       // number of dtlb miss transactions
719    uint32_t m_cpt_dtlb_ll_transaction;        // number of dtlb ll acc transactions
720    uint32_t m_cpt_dtlb_sc_transaction;        // number of dtlb sc acc transactions
721    uint32_t m_cpt_dtlb_ll_dirty_transaction;  // number of dtlb ll dirty transactions
722    uint32_t m_cpt_dtlb_sc_dirty_transaction;  // number of dtlb sc dirty transactions
723
724    uint32_t m_cost_itlbmiss_transaction;       // cumulated duration for VCI instruction TLB miss transactions
725    uint32_t m_cost_itlb_ll_transaction;        // cumulated duration for VCI instruction TLB ll acc transactions
726    uint32_t m_cost_itlb_sc_transaction;        // cumulated duration for VCI instruction TLB sc acc transactions
727    uint32_t m_cost_dtlbmiss_transaction;       // cumulated duration for VCI data TLB miss transactions
728    uint32_t m_cost_dtlb_ll_transaction;        // cumulated duration for VCI data TLB ll acc transactions
729    uint32_t m_cost_dtlb_sc_transaction;        // cumulated duration for VCI data TLB sc acc transactions
730    uint32_t m_cost_dtlb_ll_dirty_transaction;  // cumulated duration for VCI data TLB ll dirty transactions
731    uint32_t m_cost_dtlb_sc_dirty_transaction;  // cumulated duration for VCI data TLB sc dirty transactions
732
733    // coherence activity counters
734    uint32_t m_cpt_cc_update_icache;            // number of coherence update instruction commands
735    uint32_t m_cpt_cc_update_dcache;            // number of coherence update data commands
736    uint32_t m_cpt_cc_inval_icache;             // number of coherence inval instruction commands
737    uint32_t m_cpt_cc_inval_dcache;             // number of coherence inval data commands
738    uint32_t m_cpt_cc_broadcast;                // number of coherence broadcast commands
739
740    uint32_t m_cost_updt_data_frz;              // number of frozen cycles related to coherence update data packets
741    uint32_t m_cost_inval_ins_frz;              // number of frozen cycles related to coherence inval instruction packets
742    uint32_t m_cost_inval_data_frz;             // number of frozen cycles related to coherence inval data packets
743    uint32_t m_cost_broadcast_frz;              // number of frozen cycles related to coherence broadcast packets
744
745    uint32_t m_cpt_cc_cleanup_ins;              // number of coherence cleanup packets
746    uint32_t m_cpt_cc_cleanup_data;             // number of coherence cleanup packets
747    uint32_t m_cpt_cleanup_data_not_dirty;
748    uint32_t m_cpt_cleanup_data_dirty_word;
749
750    uint32_t m_cpt_icleanup_transaction;        // number of instruction cleanup transactions
751    uint32_t m_cpt_dcleanup_transaction;        // number of instructinumber of data cleanup transactions
752    uint32_t m_cost_icleanup_transaction;       // cumulated duration for VCI instruction cleanup transactions
753    uint32_t m_cost_dcleanup_transaction;       // cumulated duration for VCI data cleanup transactions
754
755    uint32_t m_cost_ins_tlb_inval_frz;      // number of frozen cycles related to checking ins tlb invalidate
756    uint32_t m_cpt_ins_tlb_inval;           // number of ins tlb invalidate
757
758    uint32_t m_cost_data_tlb_inval_frz;     // number of frozen cycles related to checking data tlb invalidate
759    uint32_t m_cpt_data_tlb_inval;          // number of data tlb invalidate
760
761    // FSM activity counters
762    uint32_t m_cpt_fsm_icache     [64];
763    uint32_t m_cpt_fsm_dcache     [64];
764    uint32_t m_cpt_fsm_cmd        [64];
765    uint32_t m_cpt_fsm_rsp        [64];
766    uint32_t m_cpt_fsm_cc_receive [64];
767    uint32_t m_cpt_fsm_cc_send    [64];
768
769    uint32_t m_cpt_stop_simulation;             // used to stop simulation if frozen
770    bool     m_monitor_ok;                      // used to debug cache output 
771    uint32_t m_monitor_base;               
772    uint32_t m_monitor_length;             
773
774protected:
775    SC_HAS_PROCESS(VciCcVCacheWrapper);
776
777public:
778    VciCcVCacheWrapper(
779        sc_module_name                      name,
780        const int                           proc_id,
781        const soclib::common::MappingTable  &mtd,
782        const soclib::common::IntTab        &srcid,
783        const size_t                        cc_global_id,
784        const size_t                        itlb_ways,
785        const size_t                        itlb_sets,
786        const size_t                        dtlb_ways,
787        const size_t                        dtlb_sets,
788        const size_t                        icache_ways,
789        const size_t                        icache_sets,
790        const size_t                        icache_words,
791        const size_t                        dcache_ways,
792        const size_t                        dcache_sets,
793        const size_t                        dcache_words,
794        const size_t                        wbuf_nlines,
795        const size_t                        wbuf_nwords,
796        const size_t                        x_width,
797        const size_t                        y_width,
798        const uint32_t                      max_frozen_cycles,
799        const uint32_t                      debug_start_cycle,
800        const bool                          debug_ok );
801
802    ~VciCcVCacheWrapper();
803
804    void print_cpi();
805    void print_stats();
806    void clear_stats();
807    void print_trace(size_t mode = 0);
808    bool frozen();
809    void cache_monitor(paddr_t addr);
810    void start_monitor(paddr_t,paddr_t);
811    void stop_monitor();
812    inline void iss_set_debug_mask(uint v) 
813    {
814            r_iss.set_debug_mask(v);
815    }
816
817private:
818    void transition();
819    void genMoore();
820
821    soclib_static_assert((int)iss_t::SC_ATOMIC == (int)vci_param::STORE_COND_ATOMIC);
822    soclib_static_assert((int)iss_t::SC_NOT_ATOMIC == (int)vci_param::STORE_COND_NOT_ATOMIC);
823};
824
825}}
826
827#endif /* SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER_H */
828
829// Local Variables:
830// tab-width: 4
831// c-basic-offset: 4
832// c-file-offsets:((innamespace . 0)(inline-open . 0))
833// indent-tabs-mode: nil
834// End:
835
836// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
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