source: branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h @ 646

Last change on this file since 646 was 646, checked in by haoliu, 8 years ago

(RWT) merging the lastest modification in trunk:

Modification in vci_cc_vcache_wrapper:
a) Non cacheable write request will not any more be sent by multi_write_buffer.

A write non cacheable access is retreated with a synchronous way, like the
read non cacheable access. When Cache L1 receives a write non cacheable request,
it will block the processor until the response of this request arrives.
The advantage of this method is that the cache L1 can supply the virtual address
to OS when it receives a bus error response.

b) In VCI_CMD_STATE, the unc_read request will not check the multi_write_buffer for

an matching address. But the CAS and SC request must be check this point
before sent to the target.

Modifcation in vci_mem_cache:
Change an assert in memcache for the modification in cache L1(UNC WRITE)

File size: 37.9 KB
Line 
1/* -*- c++ -*-
2 *
3 * File : vci_cc_vcache_wrapper.h
4 * Copyright (c) UPMC, Lip6, SoC
5 * Authors : Alain GREINER, Yang GAO
6 * Date : 27/11/2011
7 *
8 * SOCLIB_LGPL_HEADER_BEGIN
9 *
10 * This file is part of SoCLib, GNU LGPLv2.1.
11 *
12 * SoCLib is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU Lesser General Public License as published
14 * by the Free Software Foundation; version 2.1 of the License.
15 *
16 * SoCLib is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
19 * Lesser General Public License for more details.
20 *
21 * You should have received a copy of the GNU Lesser General Public
22 * License along with SoCLib; if not, write to the Free Software
23 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
24 * 02110-1301 USA
25 *
26 * SOCLIB_LGPL_HEADER_END
27 *
28 * Maintainers: cesar.fuguet-tortolero@lip6.fr
29 *              alexandre.joannou@lip6.fr
30 */
31
32#ifndef SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER_H
33#define SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER_H
34
35#include <inttypes.h>
36#include <systemc>
37#include "caba_base_module.h"
38#include "multi_write_buffer.h"
39#include "generic_fifo.h"
40#include "generic_tlb.h"
41#include "generic_cache.h"
42#include "vci_initiator.h"
43#include "dspin_interface.h"
44#include "dspin_dhccp_param.h"
45#include "mapping_table.h"
46#include "static_assert.h"
47#include "iss2.h"
48
49#define LLSC_TIMEOUT    10000
50
51namespace soclib {
52namespace caba {
53
54using namespace sc_core;
55
56////////////////////////////////////////////
57template<typename vci_param, 
58         size_t   dspin_in_width,
59         size_t   dspin_out_width,
60         typename iss_t>
61class VciCcVCacheWrapper
62////////////////////////////////////////////
63    : public soclib::caba::BaseModule
64{
65
66    typedef typename vci_param::fast_addr_t  paddr_t;
67
68    enum icache_fsm_state_e
69    {
70        ICACHE_IDLE,
71        // handling XTN processor requests
72        ICACHE_XTN_TLB_FLUSH,
73        ICACHE_XTN_CACHE_FLUSH,
74        ICACHE_XTN_CACHE_FLUSH_GO,
75        ICACHE_XTN_TLB_INVAL,
76        ICACHE_XTN_CACHE_INVAL_VA,
77        ICACHE_XTN_CACHE_INVAL_PA,
78        ICACHE_XTN_CACHE_INVAL_GO,
79        // handling tlb miss
80        ICACHE_TLB_WAIT,
81        // handling cache miss
82        ICACHE_MISS_SELECT,
83        ICACHE_MISS_CLEAN,
84        ICACHE_MISS_WAIT,
85        ICACHE_MISS_DATA_UPDT,
86        ICACHE_MISS_DIR_UPDT,
87        // handling unc read
88        ICACHE_UNC_WAIT,
89        // handling coherence requests
90        ICACHE_CC_CHECK,
91        ICACHE_CC_UPDT,
92        ICACHE_CC_INVAL,
93    };
94
95    enum dcache_fsm_state_e
96    {
97        DCACHE_IDLE,
98        // handling itlb & dtlb miss
99        DCACHE_TLB_MISS,
100        DCACHE_TLB_PTE1_GET,
101        DCACHE_TLB_PTE1_SELECT,
102        DCACHE_TLB_PTE1_UPDT,
103        DCACHE_TLB_PTE2_GET,
104        DCACHE_TLB_PTE2_SELECT,
105        DCACHE_TLB_PTE2_UPDT,
106        DCACHE_TLB_LR_UPDT,
107        DCACHE_TLB_LR_WAIT,
108        DCACHE_TLB_RETURN,
109            // handling processor XTN requests
110        DCACHE_XTN_SWITCH,
111        DCACHE_XTN_SYNC,
112        DCACHE_XTN_IC_INVAL_VA,
113        DCACHE_XTN_IC_FLUSH,
114        DCACHE_XTN_IC_INVAL_PA,
115        DCACHE_XTN_IT_INVAL,
116        DCACHE_XTN_DC_FLUSH,
117        DCACHE_XTN_DC_FLUSH_DATA,
118        DCACHE_XTN_DC_FLUSH_GO,
119        DCACHE_XTN_DC_INVAL_VA,
120        DCACHE_XTN_DC_INVAL_PA,
121        DCACHE_XTN_DC_INVAL_END,
122        DCACHE_XTN_DC_INVAL_GO,
123        DCACHE_XTN_DC_INVAL_DATA,
124        DCACHE_XTN_DT_INVAL,
125        //handling dirty bit update
126        DCACHE_DIRTY_GET_PTE,
127        DCACHE_DIRTY_WAIT,
128            // handling processor miss requests
129        DCACHE_MISS_SELECT,
130        DCACHE_MISS_CLEAN,
131        DCACHE_MISS_DATA,
132        DCACHE_MISS_WAIT,
133        DCACHE_MISS_DATA_UPDT,
134        DCACHE_MISS_DIR_UPDT,
135        // handling processor unc, ll and sc requests
136        DCACHE_UNC_WAIT,
137        DCACHE_LL_WAIT,
138        DCACHE_SC_WAIT,
139        // handling coherence requests
140        DCACHE_CC_CHECK,
141        DCACHE_CC_UPDT,
142        DCACHE_CC_INVAL,
143        DCACHE_CC_INVAL_DATA,
144        // handling TLB inval (after a coherence or XTN request)
145        DCACHE_INVAL_TLB_SCAN,
146    };
147
148    enum cmd_fsm_state_e
149    {
150        CMD_IDLE,
151        CMD_INS_MISS,
152        CMD_INS_UNC,
153        CMD_DATA_MISS,
154        CMD_DATA_UNC_READ,
155        CMD_DATA_UNC_WRITE,
156        CMD_DATA_WRITE,
157        CMD_DATA_LL,
158        CMD_DATA_SC,
159        CMD_DATA_CAS,
160    };
161
162    enum rsp_fsm_state_e
163    {
164        RSP_IDLE,
165        RSP_INS_MISS,
166        RSP_INS_UNC,
167        RSP_DATA_MISS,
168        RSP_DATA_UNC,
169        RSP_DATA_LL,
170        RSP_DATA_WRITE,
171    };
172
173    enum cc_receive_fsm_state_e
174    {
175        CC_RECEIVE_IDLE,
176        CC_RECEIVE_BRDCAST_HEADER,
177        CC_RECEIVE_BRDCAST_NLINE,
178        CC_RECEIVE_INS_INVAL_HEADER,
179        CC_RECEIVE_INS_INVAL_NLINE,
180        CC_RECEIVE_INS_UPDT_HEADER,
181        CC_RECEIVE_INS_UPDT_NLINE,
182        CC_RECEIVE_INS_UPDT_DATA,
183        CC_RECEIVE_DATA_INVAL_HEADER,
184        CC_RECEIVE_DATA_INVAL_NLINE,
185        CC_RECEIVE_DATA_UPDT_HEADER,
186        CC_RECEIVE_DATA_UPDT_NLINE,
187        CC_RECEIVE_DATA_UPDT_DATA,
188    };
189
190    enum cc_send_fsm_state_e
191    {
192        CC_SEND_IDLE,
193        CC_SEND_CLEANUP_1,
194        CC_SEND_CLEANUP_2,
195        CC_SEND_CLEANUP_DATA_UPDT,
196        CC_SEND_MULTI_ACK,
197    };
198
199    /* transaction type, pktid field */
200    enum transaction_type_e
201    {
202        // b3 unused
203        // b2 READ / NOT READ
204        // if READ
205        //  b1 DATA / INS
206        //  b0 UNC / MISS
207        // else
208        //  b1 accÚs table llsc type SW / other
209        //  b2 WRITE/CAS/LL/SC
210        TYPE_DATA_UNC               = 0x0,
211        TYPE_READ_DATA_MISS         = 0x1,
212        TYPE_READ_INS_UNC           = 0x2,
213        TYPE_READ_INS_MISS          = 0x3,
214        TYPE_WRITE                  = 0x4,
215        TYPE_CAS                    = 0x5,
216        TYPE_LL                     = 0x6,
217        TYPE_SC                     = 0x7
218    };
219
220    /* SC return values */
221    enum sc_status_type_e
222    {
223        SC_SUCCESS  =   0x00000000,
224        SC_FAIL     =   0x00000001
225    };
226
227    // cc_send_type
228    typedef enum 
229    {
230        CC_TYPE_CLEANUP,
231        CC_TYPE_MULTI_ACK,
232    } cc_send_t;
233
234    // cc_receive_type
235    typedef enum 
236    {
237        CC_TYPE_CLACK,
238        CC_TYPE_BRDCAST,
239        CC_TYPE_INVAL,
240        CC_TYPE_UPDT,
241    } cc_receive_t;
242
243    // TLB Mode : ITLB / DTLB / ICACHE / DCACHE
244    enum 
245    {
246        INS_TLB_MASK    = 0x8,
247        DATA_TLB_MASK   = 0x4,
248        INS_CACHE_MASK  = 0x2,
249        DATA_CACHE_MASK = 0x1,
250    };
251
252    // Error Type
253    enum mmu_error_type_e
254    {
255        MMU_NONE                      = 0x0000, // None
256        MMU_WRITE_PT1_UNMAPPED        = 0x0001, // Write & Page fault on PT1
257        MMU_WRITE_PT2_UNMAPPED        = 0x0002, // Write & Page fault on PT2
258        MMU_WRITE_PRIVILEGE_VIOLATION = 0x0004, // Write & Protected access in user mode
259        MMU_WRITE_ACCES_VIOLATION     = 0x0008, // Write to non writable page
260        MMU_WRITE_UNDEFINED_XTN       = 0x0020, // Write & undefined external access
261        MMU_WRITE_PT1_ILLEGAL_ACCESS  = 0x0040, // Write & Bus Error accessing PT1
262        MMU_WRITE_PT2_ILLEGAL_ACCESS  = 0x0080, // Write & Bus Error accessing PT2
263        MMU_WRITE_DATA_ILLEGAL_ACCESS = 0x0100, // Write & Bus Error in cache access
264        MMU_READ_PT1_UNMAPPED         = 0x1001, // Read & Page fault on PT1
265        MMU_READ_PT2_UNMAPPED         = 0x1002, // Read & Page fault on PT2
266        MMU_READ_PRIVILEGE_VIOLATION  = 0x1004, // Read & Protected access in user mode
267        MMU_READ_EXEC_VIOLATION       = 0x1010, // Read & Exec access to a non exec page
268        MMU_READ_UNDEFINED_XTN        = 0x1020, // Read & Undefined external access
269        MMU_READ_PT1_ILLEGAL_ACCESS   = 0x1040, // Read & Bus Error accessing PT1
270        MMU_READ_PT2_ILLEGAL_ACCESS   = 0x1080, // Read & Bus Error accessing PT2
271        MMU_READ_DATA_ILLEGAL_ACCESS  = 0x1100, // Read & Bus Error in cache access
272    };
273
274    // miss types for data cache
275    enum dcache_miss_type_e
276    {
277        PTE1_MISS,
278        PTE2_MISS,
279        PROC_MISS,
280    };
281
282//    enum transaction_type_d_e
283//    {
284//        // b0 : 1 if cached
285//        // b1 : 1 if instruction
286//        TYPE_DATA_UNC     = 0x0,
287//        TYPE_DATA_MISS    = 0x1,
288//        TYPE_INS_UNC      = 0x2,
289//        TYPE_INS_MISS     = 0x3,
290//    };
291
292    //////////////////MODIFIED////////////////
293    enum content_line_cache_status_e
294    {
295        LINE_CACHE_DATA_NOT_DIRTY,
296        LINE_CACHE_DATA_DIRTY,
297        LINE_CACHE_IN_TLB,
298        LINE_CACHE_CONTAINS_PTD,
299    };
300    //////////////////////////////////////////
301
302public:
303    sc_in<bool>                                p_clk;
304    sc_in<bool>                                p_resetn;
305    sc_in<bool>                                p_irq[iss_t::n_irq];
306    soclib::caba::VciInitiator<vci_param>      p_vci;
307    soclib::caba::DspinInput<dspin_in_width>   p_dspin_m2p;
308    soclib::caba::DspinOutput<dspin_out_width> p_dspin_p2m;
309    soclib::caba::DspinInput<dspin_in_width>   p_dspin_clack;
310
311private:
312
313    // STRUCTURAL PARAMETERS
314    soclib::common::AddressDecodingTable<uint64_t, bool> m_cacheability_table;
315
316    const size_t                        m_srcid;
317    const size_t                        m_cc_global_id;
318    const size_t                        m_nline_width;
319    const size_t                                                m_itlb_ways;
320    const size_t                                                m_itlb_sets;
321    const size_t                                                m_dtlb_ways;
322    const size_t                                                m_dtlb_sets;
323    const size_t                                                m_icache_ways;
324    const size_t                                                m_icache_sets;
325    const paddr_t                                               m_icache_yzmask;
326    const size_t                                                m_icache_words;
327    const size_t                                                m_dcache_ways;
328    const size_t                                                m_dcache_sets;
329    const paddr_t                                               m_dcache_yzmask;
330    const size_t                                                m_dcache_words;
331    const size_t                        m_x_width;
332    const size_t                        m_y_width;
333    const size_t                        m_proc_id;
334    const uint32_t                                              m_max_frozen_cycles;
335    const size_t                                                m_paddr_nbits;
336    uint32_t                            m_debug_start_cycle;
337    bool                                m_debug_ok;
338
339    ////////////////////////////////////////
340    // Communication with processor ISS
341    ////////////////////////////////////////
342    typename iss_t::InstructionRequest  m_ireq;
343    typename iss_t::InstructionResponse m_irsp;
344    typename iss_t::DataRequest         m_dreq;
345    typename iss_t::DataResponse        m_drsp;
346
347    /////////////////////////////////////////////
348    // debug variables
349    /////////////////////////////////////////////
350    bool                                m_debug_previous_i_hit;
351    bool                                m_debug_previous_d_hit;
352    bool                                m_debug_activated;
353
354    ///////////////////////////////
355    // Software visible REGISTERS
356    ///////////////////////////////
357    sc_signal<uint32_t>     r_mmu_ptpr;                 // page table pointer register
358    sc_signal<uint32_t>     r_mmu_mode;                 // mmu mode register
359    sc_signal<uint32_t>     r_mmu_word_lo;              // mmu misc data low
360    sc_signal<uint32_t>     r_mmu_word_hi;              // mmu misc data hight
361    sc_signal<uint32_t>     r_mmu_ibvar;                // mmu bad instruction address
362    sc_signal<uint32_t>     r_mmu_dbvar;                // mmu bad data address
363    sc_signal<uint32_t>     r_mmu_ietr;                 // mmu instruction error type
364    sc_signal<uint32_t>     r_mmu_detr;                 // mmu data error type
365    uint32_t                r_mmu_params;                       // read-only
366    uint32_t                r_mmu_release;                      // read_only
367
368
369    //////////////////////////////
370    // ICACHE FSM REGISTERS
371    //////////////////////////////
372    sc_signal<int>          r_icache_fsm;               // state register
373    sc_signal<int>          r_icache_fsm_save;          // return state for coherence op
374    sc_signal<paddr_t>      r_icache_vci_paddr;         // physical address
375    sc_signal<uint32_t>     r_icache_vaddr_save;        // virtual address from processor
376
377    // icache miss handling
378    sc_signal<size_t>       r_icache_miss_way;              // selected way for cache update
379    sc_signal<size_t>       r_icache_miss_set;              // selected set for cache update
380    sc_signal<size_t>       r_icache_miss_word;             // word index ( cache update)
381    sc_signal<bool>         r_icache_miss_inval;        // coherence request matching a miss
382    sc_signal<bool>         r_icache_miss_clack;        // waiting for a cleanup acknowledge
383
384    // coherence request handling
385    sc_signal<size_t>       r_icache_cc_way;                // selected way for cc update/inval
386    sc_signal<size_t>       r_icache_cc_set;                // selected set for cc update/inval
387    sc_signal<size_t>       r_icache_cc_word;               // word counter for cc update
388    sc_signal<bool>         r_icache_cc_need_write;     // activate the cache for writing
389
390    // coherence clack handling
391    sc_signal<bool>         r_icache_clack_req;         // clack request
392    sc_signal<size_t>       r_icache_clack_way;             // clack way
393    sc_signal<size_t>       r_icache_clack_set;             // clack set
394
395    // icache flush handling
396    sc_signal<size_t>       r_icache_flush_count;           // slot counter used for cache flush
397
398    // communication between ICACHE FSM and VCI_CMD FSM
399    sc_signal<bool>         r_icache_miss_req;           // cached read miss
400    sc_signal<bool>         r_icache_unc_req;            // uncached read miss
401
402    // communication between ICACHE FSM and DCACHE FSM
403    sc_signal<bool>             r_icache_tlb_miss_req;       // (set icache/reset dcache)
404    sc_signal<bool>         r_icache_tlb_rsp_error;      // tlb miss response error
405
406
407    // communication between ICACHE FSM and CC_SEND FSM
408    sc_signal<bool>         r_icache_cc_send_req;           // ICACHE cc_send request
409    sc_signal<int>          r_icache_cc_send_type;          // ICACHE cc_send request type
410    sc_signal<paddr_t>      r_icache_cc_send_nline;         // ICACHE cc_send nline
411    sc_signal<size_t>       r_icache_cc_send_way;           // ICACHE cc_send way
412    sc_signal<size_t>       r_icache_cc_send_updt_tab_idx;  // ICACHE cc_send update table index
413   
414    // Filp-Flop in ICACHE FSM for saving the cleanup victim request
415    sc_signal<bool>         r_icache_cleanup_victim_req; 
416    sc_signal<paddr_t>      r_icache_cleanup_victim_nline;
417
418    ///////////////////////////////
419    // DCACHE FSM REGISTERS
420    ///////////////////////////////
421    sc_signal<int>          r_dcache_fsm;               // state register
422    sc_signal<int>          r_dcache_fsm_cc_save;       // return state for coherence op
423    sc_signal<int>          r_dcache_fsm_scan_save;     // return state for tlb scan op
424    // registers written in P0 stage (used in P1 stage)
425    sc_signal<bool>         r_dcache_wbuf_req;          // WBUF must be written in P1 stage
426    sc_signal<bool>         r_dcache_updt_req;          // DCACHE must be updated in P1 stage
427    sc_signal<uint32_t>     r_dcache_save_vaddr;        // virtual address (from proc)
428    sc_signal<uint32_t>     r_dcache_save_wdata;        // write data (from proc)
429    sc_signal<uint32_t>     r_dcache_save_be;           // byte enable (from proc)
430    sc_signal<paddr_t>      r_dcache_save_paddr;        // physical address
431    sc_signal<size_t>       r_dcache_save_cache_way;    // selected way (from dcache)
432    sc_signal<size_t>       r_dcache_save_cache_set;    // selected set (from dcache)
433    sc_signal<size_t>       r_dcache_save_cache_word;   // selected word (from dcache)
434    // registers used by the Dirty bit sub-fsm
435    sc_signal<paddr_t>      r_dcache_dirty_paddr;       // PTE physical address
436    sc_signal<size_t>       r_dcache_dirty_way;         // way to invalidate in dcache
437    sc_signal<size_t>       r_dcache_dirty_set;         // set to invalidate in dcache
438
439    // communication between DCACHE FSM and VCI_CMD FSM
440    sc_signal<paddr_t>      r_dcache_vci_paddr;             // physical address for VCI command
441    sc_signal<uint32_t>     r_dcache_vci_wdata;             // write unc data for VCI command
442    sc_signal<bool>         r_dcache_vci_miss_req;      // read miss request
443    sc_signal<bool>         r_dcache_vci_unc_req;       // uncacheable request (read/write)
444    sc_signal<uint32_t>     r_dcache_vci_unc_be;        // uncacheable byte enable
445    sc_signal<uint32_t>     r_dcache_vci_unc_write;     // uncacheable data write request
446    sc_signal<bool>         r_dcache_vci_cas_req;       // atomic write request CAS
447    sc_signal<uint32_t>     r_dcache_vci_cas_old;       // previous data value for a CAS
448    sc_signal<uint32_t>     r_dcache_vci_cas_new;       // new data value for a CAS
449    sc_signal<bool>         r_dcache_vci_ll_req;        // atomic read request LL
450    sc_signal<bool>         r_dcache_vci_sc_req;        // atomic write request SC
451    sc_signal<uint32_t>     r_dcache_vci_sc_data;       // SC data (command)
452
453    //RWT: local cas
454    sc_signal<bool>         r_cas_islocal;
455    sc_signal<size_t>       r_cas_local_way;
456    sc_signal<size_t>       r_cas_local_set;
457    sc_signal<size_t>       r_cas_local_word;
458
459    // register used for XTN inval
460    sc_signal<size_t>       r_dcache_xtn_way;               // selected way (from dcache)
461    sc_signal<size_t>       r_dcache_xtn_set;               // selected set (from dcache)
462
463    // handling dcache miss
464    sc_signal<int>              r_dcache_miss_type;                 // depending on the requester
465    sc_signal<size_t>       r_dcache_miss_word;             // word index for cache update
466    sc_signal<size_t>       r_dcache_miss_way;              // selected way for cache update
467    sc_signal<size_t>       r_dcache_miss_set;              // selected set for cache update
468    sc_signal<bool>         r_dcache_miss_inval;        // coherence request matching a miss
469    sc_signal<bool>         r_dcache_miss_clack;        // waiting for a cleanup acknowledge
470
471    // handling coherence requests
472    sc_signal<size_t>       r_dcache_cc_way;                // selected way for cc update/inval
473    sc_signal<size_t>       r_dcache_cc_set;                // selected set for cc update/inval
474    sc_signal<int>          r_dcache_cc_state;          // state of selected cache slot
475    sc_signal<size_t>       r_dcache_cc_word;               // word counter for cc update
476    sc_signal<bool>         r_dcache_cc_need_write;     // activate the cache for writing
477    sc_signal<paddr_t>      r_dcache_cc_inval_addr;     // address for a cleanup transaction
478    sc_signal<uint32_t>     r_dcache_cc_inval_data_cpt; 
479
480    // coherence clack handling
481    sc_signal<bool>         r_dcache_clack_req;         // clack request
482    sc_signal<size_t>       r_dcache_clack_way;             // clack way
483    sc_signal<size_t>       r_dcache_clack_set;             // clack set
484
485    // dcache flush handling
486    sc_signal<size_t>       r_dcache_flush_count;           // slot counter used for cache flush
487
488    // ll response handling
489    sc_signal<size_t>       r_dcache_ll_rsp_count;          // flit counter used for ll rsp
490
491    // used by the TLB miss sub-fsm
492    sc_signal<uint32_t>     r_dcache_tlb_vaddr;             // virtual address for a tlb miss
493    sc_signal<bool>         r_dcache_tlb_ins;               // target tlb (itlb if true)
494    sc_signal<paddr_t>      r_dcache_tlb_paddr;             // physical address of pte
495    sc_signal<uint32_t>     r_dcache_tlb_pte_flags;         // pte1 or first word of pte2
496    sc_signal<uint32_t>     r_dcache_tlb_pte_ppn;           // second word of pte2
497    sc_signal<size_t>       r_dcache_tlb_cache_way;         // selected way in dcache
498    sc_signal<size_t>       r_dcache_tlb_cache_set;         // selected set in dcache
499    sc_signal<size_t>       r_dcache_tlb_cache_word;    // selected word in dcache
500    sc_signal<size_t>       r_dcache_tlb_way;               // selected way in tlb
501    sc_signal<size_t>       r_dcache_tlb_set;               // selected set in tlb
502
503    // ITLB and DTLB invalidation
504    sc_signal<paddr_t>      r_dcache_tlb_inval_line;    // line index
505    sc_signal<size_t>       r_dcache_tlb_inval_set;     // tlb set counter
506
507    // communication between DCACHE FSM and ICACHE FSM
508    sc_signal<bool>         r_dcache_xtn_req;           // xtn request (caused by processor)
509    sc_signal<int>          r_dcache_xtn_opcode;        // xtn request type
510
511    // Filp-Flop in DCACHE FSM for saving the cleanup victim request
512    sc_signal<bool>         r_dcache_cleanup_victim_req; 
513    sc_signal<bool>         r_dcache_cleanup_victim_line_ncc; 
514    sc_signal<bool>         r_dcache_cleanup_victim_updt_data; 
515    sc_signal<paddr_t>      r_dcache_cleanup_victim_nline;
516
517    // communication between DCACHE FSM and CC_SEND FSM
518    sc_signal<bool>         r_dcache_cc_send_req;           // DCACHE cc_send request
519    sc_signal<int>          r_dcache_cc_send_type;          // DCACHE cc_send request type
520    sc_signal<paddr_t>      r_dcache_cc_send_nline;         // DCACHE cc_send nline
521    sc_signal<size_t>       r_dcache_cc_send_way;           // DCACHE cc_send way
522    sc_signal<size_t>       r_dcache_cc_send_updt_tab_idx;  // DCACHE cc_send update table index
523   
524    // special registers for ODCCP/RWT
525    sc_signal<bool>         r_dcache_cc_cleanup_updt_data;          // Register for cleanup with data (wb updt)
526    sc_signal<bool>         r_dcache_cc_cleanup_line_ncc;          // Register for cleanup with data (wb updt)
527    sc_signal<bool>         r_dcache_miss_victim_no_coherence;      // Register for victim in no coherence mode
528    sc_signal<bool>         r_dcache_line_no_coherence;             // Register for line current in no coherence mode
529    sc_signal<bool>         r_dcache_dirty_save;             
530    sc_signal<uint32_t>     r_cc_send_cpt_word;
531    sc_signal<uint32_t>     r_dcache_miss_data_cpt;
532    sc_signal<paddr_t>      r_dcache_miss_data_addr;
533    sc_signal<uint32_t>     r_dcache_xtn_flush_data_cpt;
534    sc_signal<paddr_t>      r_dcache_xtn_flush_addr_data;
535    sc_signal<int>          r_dcache_xtn_state;
536    sc_signal<paddr_t>      r_dcache_xtn_data_addr;
537    sc_signal<uint32_t>     r_dcache_xtn_data_cpt;
538    // dcache directory extension
539    ///////////////////////////MODIFIED///////////////////////////////////////////////////
540    //bool                    *r_dcache_in_tlb;           // copy exist in dtlb or itlb
541    //bool                    *r_dcache_contains_ptd;     // cache line contains a PTD
542    int                     *r_dcache_content_state; // content state of one cache line
543    int                     *r_dcache_dirty_word;   
544    bool                    *r_dcache_zombi_ncc;     
545    //////////////////////////////////////////////////////////////////////////////////////
546
547    //RWT
548    sc_signal<bool>         r_dcache_read_state;
549   
550     ///////////////////////////////////
551    // Physical address extension for data access
552    sc_signal<uint32_t>     r_dcache_paddr_ext;             // CP2 register (if vci_address > 32)
553
554    ///////////////////////////////////
555    // VCI_CMD FSM REGISTERS
556    ///////////////////////////////////
557    sc_signal<int>          r_vci_cmd_fsm;
558    sc_signal<size_t>       r_vci_cmd_min;                      // used for write bursts
559    sc_signal<size_t>       r_vci_cmd_max;                      // used for write bursts
560    sc_signal<size_t>       r_vci_cmd_cpt;                      // used for write bursts
561    sc_signal<bool>         r_vci_cmd_imiss_prio;               // round-robin between imiss & dmiss
562
563    ///////////////////////////////////
564    // VCI_RSP FSM REGISTERS
565    ///////////////////////////////////
566    sc_signal<int>          r_vci_rsp_fsm;
567    sc_signal<size_t>       r_vci_rsp_cpt;
568    sc_signal<bool>         r_vci_rsp_ins_error;
569    sc_signal<bool>         r_vci_rsp_data_error;
570    GenericFifo<uint32_t>   r_vci_rsp_fifo_icache;              // response FIFO to ICACHE FSM
571    GenericFifo<uint32_t>   r_vci_rsp_fifo_dcache;              // response FIFO to DCACHE FSM
572   
573
574    //RWT
575    GenericFifo<bool>       r_vci_rsp_fifo_rpktid;
576
577    GenericFifo<uint32_t>   r_cc_send_data_fifo;   
578
579    ///////////////////////////////////
580    //  CC_SEND FSM REGISTER
581    ///////////////////////////////////
582    sc_signal<int>          r_cc_send_fsm;                  // state register
583    sc_signal<bool>         r_cc_send_last_client;          // 0 dcache / 1 icache
584
585    ///////////////////////////////////
586    //  CC_RECEIVE FSM REGISTER
587    ///////////////////////////////////
588    sc_signal<int>          r_cc_receive_fsm;               // state register
589    sc_signal<bool>         r_cc_receive_data_ins;          // request to : 0 dcache / 1 icache
590
591    // communication between CC_RECEIVE FSM and ICACHE/DCACHE FSM
592    sc_signal<size_t>       r_cc_receive_word_idx;          // word index
593    GenericFifo<uint32_t>   r_cc_receive_updt_fifo_be;
594    GenericFifo<uint32_t>   r_cc_receive_updt_fifo_data;
595    GenericFifo<bool>       r_cc_receive_updt_fifo_eop;
596
597    // communication between CC_RECEIVE FSM and ICACHE FSM
598    sc_signal<bool>         r_cc_receive_icache_req;        // cc_receive to icache request
599    sc_signal<int>          r_cc_receive_icache_type;       // cc_receive type of request
600    sc_signal<size_t>       r_cc_receive_icache_way;        // cc_receive to icache way
601    sc_signal<size_t>       r_cc_receive_icache_set;        // cc_receive to icache set
602    sc_signal<size_t>       r_cc_receive_icache_updt_tab_idx;  // cc_receive update table index
603    sc_signal<paddr_t>      r_cc_receive_icache_nline;      // cache line physical address
604
605    // communication between CC_RECEIVE FSM and DCACHE FSM
606    sc_signal<bool>         r_cc_receive_dcache_req;              // cc_receive to dcache request
607    sc_signal<int>          r_cc_receive_dcache_type;             // cc_receive type of request
608    sc_signal<size_t>       r_cc_receive_dcache_way;              // cc_receive to dcache way
609    sc_signal<size_t>       r_cc_receive_dcache_set;              // cc_receive to dcache set
610    sc_signal<size_t>       r_cc_receive_dcache_updt_tab_idx;     // cc_receive update table index
611    sc_signal<paddr_t>      r_cc_receive_dcache_nline;            // cache line physical address
612    sc_signal<bool>         r_cc_receive_dcache_inval_is_config;  // inval from memcache is config
613
614    ///////////////////////////////////
615    //  DSPIN CLACK INTERFACE REGISTER
616    ///////////////////////////////////
617    sc_signal<bool>         r_dspin_clack_req;
618    sc_signal<uint64_t>     r_dspin_clack_flit;
619   
620    //////////////////////////////////////////////////////////////////
621    // processor, write buffer, caches , TLBs
622    //////////////////////////////////////////////////////////////////
623
624    iss_t                       r_iss;
625    MultiWriteBuffer<paddr_t>   r_wbuf;
626    GenericCache<paddr_t>       r_icache;
627    GenericCache<paddr_t>       r_dcache;
628    GenericTlb<paddr_t>         r_itlb;
629    GenericTlb<paddr_t>         r_dtlb;
630
631    //////////////////////////////////////////////////////////////////
632    // llsc registration buffer
633    //////////////////////////////////////////////////////////////////
634
635    sc_signal<paddr_t>                     r_dcache_llsc_paddr;
636    sc_signal<uint32_t>                    r_dcache_llsc_key;
637    sc_signal<uint32_t>                    r_dcache_llsc_count;
638    sc_signal<bool>                        r_dcache_llsc_valid;
639
640   
641    sc_signal<bool>                        r_cache_frozen;
642
643    ////////////////////////////////
644    // Activity counters
645    ////////////////////////////////
646    uint32_t m_cpt_dcache_data_read;           // DCACHE DATA READ
647    uint32_t m_cpt_dcache_data_write;          // DCACHE DATA WRITE
648    uint32_t m_cpt_dcache_dir_read;            // DCACHE DIR READ
649    uint32_t m_cpt_dcache_dir_write;           // DCACHE DIR WRITE
650
651    uint32_t m_cpt_icache_data_read;           // ICACHE DATA READ
652    uint32_t m_cpt_icache_data_write;          // ICACHE DATA WRITE
653    uint32_t m_cpt_icache_dir_read;            // ICACHE DIR READ
654    uint32_t m_cpt_icache_dir_write;           // ICACHE DIR WRITE
655
656    uint32_t m_cpt_frz_cycles;                 // number of cycles where the cpu is frozen
657    uint32_t m_cpt_total_cycles;                   // total number of cycles
658
659    // Cache activity counters
660    uint32_t m_cpt_data_read;                  // total number of read data
661    uint32_t m_cpt_data_write;                 // total number of write data
662    uint32_t m_cpt_data_write_back;
663    uint32_t m_cpt_data_cleanup;
664    uint32_t m_cpt_data_sc;
665    uint32_t m_cpt_data_miss;                  // number of read miss
666    uint32_t m_cpt_ins_miss;                   // number of instruction miss
667    uint32_t m_cpt_unc_read;                   // number of read uncached
668    uint32_t m_cpt_write_cached;               // number of cached write
669    uint32_t m_cpt_ins_read;                   // number of instruction read
670    uint32_t m_cpt_ins_spc_miss;               // number of speculative instruction miss
671
672    uint32_t m_cost_write_frz;                 // number of frozen cycles related to write buffer
673    uint32_t m_cost_data_miss_frz;             // number of frozen cycles related to data miss
674    uint32_t m_cost_unc_read_frz;              // number of frozen cycles related to uncached read
675    uint32_t m_cost_ins_miss_frz;              // number of frozen cycles related to ins miss
676
677    uint32_t m_cpt_imiss_transaction;          // number of VCI instruction miss transactions
678    uint32_t m_cpt_dmiss_transaction;          // number of VCI data miss transactions
679    uint32_t m_cpt_unc_transaction;            // number of VCI uncached read transactions
680    uint32_t m_cpt_dunc_transaction;           // number of VCI uncached read transactions
681    uint32_t m_cpt_ll_transaction;             // number of VCI uncached read transactions
682    uint32_t m_cpt_write_transaction;          // number of VCI write transactions
683    uint32_t m_cpt_icache_unc_transaction;
684
685    uint32_t m_cost_imiss_transaction;         // cumulated duration for VCI IMISS transactions
686    uint32_t m_cost_dmiss_transaction;         // cumulated duration for VCI DMISS transactions
687    uint32_t m_cost_unc_transaction;           // cumulated duration for VCI UNC transactions
688    uint32_t m_cost_write_transaction;         // cumulated duration for VCI WRITE transactions
689    uint32_t m_cost_icache_unc_transaction;    // cumulated duration for VCI IUNC transactions
690    uint32_t m_length_write_transaction;       // cumulated length for VCI WRITE transactions
691
692    // TLB activity counters
693    uint32_t m_cpt_ins_tlb_read;               // number of instruction tlb read
694    uint32_t m_cpt_ins_tlb_miss;               // number of instruction tlb miss
695    uint32_t m_cpt_ins_tlb_update_acc;         // number of instruction tlb update
696    uint32_t m_cpt_ins_tlb_occup_cache;        // number of instruction tlb occupy data cache line
697    uint32_t m_cpt_ins_tlb_hit_dcache;         // number of instruction tlb hit in data cache
698
699    uint32_t m_cpt_data_tlb_read;              // number of data tlb read
700    uint32_t m_cpt_data_tlb_miss;              // number of data tlb miss
701    uint32_t m_cpt_data_tlb_update_acc;        // number of data tlb update
702    uint32_t m_cpt_data_tlb_update_dirty;      // number of data tlb update dirty
703    uint32_t m_cpt_data_tlb_hit_dcache;        // number of data tlb hit in data cache
704    uint32_t m_cpt_data_tlb_occup_cache;       // number of data tlb occupy data cache line
705    uint32_t m_cpt_tlb_occup_dcache;
706
707    uint32_t m_cost_ins_tlb_miss_frz;          // number of frozen cycles related to instruction tlb miss
708    uint32_t m_cost_data_tlb_miss_frz;         // number of frozen cycles related to data tlb miss
709    uint32_t m_cost_ins_tlb_update_acc_frz;    // number of frozen cycles related to instruction tlb update acc
710    uint32_t m_cost_data_tlb_update_acc_frz;   // number of frozen cycles related to data tlb update acc
711    uint32_t m_cost_data_tlb_update_dirty_frz; // number of frozen cycles related to data tlb update dirty
712    uint32_t m_cost_ins_tlb_occup_cache_frz;   // number of frozen cycles related to instruction tlb miss operate in dcache
713    uint32_t m_cost_data_tlb_occup_cache_frz;  // number of frozen cycles related to data tlb miss operate in dcache
714
715    uint32_t m_cpt_itlbmiss_transaction;       // number of itlb miss transactions
716    uint32_t m_cpt_itlb_ll_transaction;        // number of itlb ll acc transactions
717    uint32_t m_cpt_itlb_sc_transaction;        // number of itlb sc acc transactions
718    uint32_t m_cpt_dtlbmiss_transaction;       // number of dtlb miss transactions
719    uint32_t m_cpt_dtlb_ll_transaction;        // number of dtlb ll acc transactions
720    uint32_t m_cpt_dtlb_sc_transaction;        // number of dtlb sc acc transactions
721    uint32_t m_cpt_dtlb_ll_dirty_transaction;  // number of dtlb ll dirty transactions
722    uint32_t m_cpt_dtlb_sc_dirty_transaction;  // number of dtlb sc dirty transactions
723
724    uint32_t m_cost_itlbmiss_transaction;      // cumulated duration for VCI instruction TLB miss transactions
725    uint32_t m_cost_itlb_ll_transaction;       // cumulated duration for VCI instruction TLB ll acc transactions
726    uint32_t m_cost_itlb_sc_transaction;       // cumulated duration for VCI instruction TLB sc acc transactions
727    uint32_t m_cost_dtlbmiss_transaction;      // cumulated duration for VCI data TLB miss transactions
728    uint32_t m_cost_dtlb_ll_transaction;       // cumulated duration for VCI data TLB ll acc transactions
729    uint32_t m_cost_dtlb_sc_transaction;       // cumulated duration for VCI data TLB sc acc transactions
730    uint32_t m_cost_dtlb_ll_dirty_transaction; // cumulated duration for VCI data TLB ll dirty transactions
731    uint32_t m_cost_dtlb_sc_dirty_transaction; // cumulated duration for VCI data TLB sc dirty transactions
732
733    // coherence activity counters
734    uint32_t m_cpt_cc_update_icache;           // number of coherence update instruction commands
735    uint32_t m_cpt_cc_update_dcache;           // number of coherence update data commands
736    uint32_t m_cpt_cc_inval_icache;            // number of coherence inval instruction commands
737    uint32_t m_cpt_cc_inval_dcache;            // number of coherence inval data commands
738    uint32_t m_cpt_cc_broadcast;               // number of coherence broadcast commands
739
740    uint32_t m_cost_updt_data_frz;             // number of frozen cycles related to coherence update data packets
741    uint32_t m_cost_inval_ins_frz;             // number of frozen cycles related to coherence inval instruction packets
742    uint32_t m_cost_inval_data_frz;            // number of frozen cycles related to coherence inval data packets
743    uint32_t m_cost_broadcast_frz;             // number of frozen cycles related to coherence broadcast packets
744
745    uint32_t m_cpt_cc_cleanup_ins;             // number of coherence cleanup packets
746    uint32_t m_cpt_cc_cleanup_data;            // number of coherence cleanup packets
747    uint32_t m_cpt_cleanup_data_not_dirty;     // number of total cleanup data without extra data flits
748    uint32_t m_cpt_cleanup_data_dirty_word;    // number of total words dirty in cleanup data
749    uint32_t m_cpt_data_write_miss;            // number of total write miss
750    uint32_t m_cpt_data_write_on_zombi;        // number of frozen cycles related to blocked write on line NCC/CC ZOMBI
751    uint32_t m_cpt_data_write_on_zombi_ncc;    // number of frozen cycles related to blocked write on line NCC ZOMBI
752
753    uint32_t m_cpt_icleanup_transaction;       // number of instruction cleanup transactions
754    uint32_t m_cpt_dcleanup_transaction;       // number of instructinumber of data cleanup transactions
755    uint32_t m_cost_icleanup_transaction;      // cumulated duration for VCI instruction cleanup transactions
756    uint32_t m_cost_dcleanup_transaction;      // cumulated duration for VCI data cleanup transactions
757
758    uint32_t m_cost_ins_tlb_inval_frz;         // number of frozen cycles related to checking ins tlb invalidate
759    uint32_t m_cpt_ins_tlb_inval;              // number of ins tlb invalidate
760
761    uint32_t m_cost_data_tlb_inval_frz;        // number of frozen cycles related to checking data tlb invalidate
762    uint32_t m_cpt_data_tlb_inval;             // number of data tlb invalidate
763
764    // FSM activity counters
765    uint32_t m_cpt_fsm_icache     [64];
766    uint32_t m_cpt_fsm_dcache     [64];
767    uint32_t m_cpt_fsm_cmd        [64];
768    uint32_t m_cpt_fsm_rsp        [64];
769    uint32_t m_cpt_fsm_cc_receive [64];
770    uint32_t m_cpt_fsm_cc_send    [64];
771
772    uint32_t m_cpt_stop_simulation;             // used to stop simulation if frozen
773    bool     m_monitor_ok;                      // used to debug cache output 
774    uint32_t m_monitor_base;               
775    uint32_t m_monitor_length;             
776
777protected:
778    SC_HAS_PROCESS(VciCcVCacheWrapper);
779
780public:
781    VciCcVCacheWrapper(
782        sc_module_name                      name,
783        const int                           proc_id,
784        const soclib::common::MappingTable  &mtd,
785        const soclib::common::IntTab        &srcid,
786        const size_t                        cc_global_id,
787        const size_t                        itlb_ways,
788        const size_t                        itlb_sets,
789        const size_t                        dtlb_ways,
790        const size_t                        dtlb_sets,
791        const size_t                        icache_ways,
792        const size_t                        icache_sets,
793        const size_t                        icache_words,
794        const size_t                        dcache_ways,
795        const size_t                        dcache_sets,
796        const size_t                        dcache_words,
797        const size_t                        wbuf_nlines,
798        const size_t                        wbuf_nwords,
799        const size_t                        x_width,
800        const size_t                        y_width,
801        const uint32_t                      max_frozen_cycles,
802        const uint32_t                      debug_start_cycle,
803        const bool                          debug_ok );
804
805    ~VciCcVCacheWrapper();
806
807    void print_cpi();
808    void print_stats();
809    void clear_stats();
810    void print_trace(size_t mode = 0);
811    bool frozen();
812    void cache_monitor(paddr_t addr);
813    void start_monitor(paddr_t,paddr_t);
814    void stop_monitor();
815    inline void iss_set_debug_mask(uint v) 
816    {
817            r_iss.set_debug_mask(v);
818    }
819
820private:
821    void transition();
822    void genMoore();
823
824    soclib_static_assert((int)iss_t::SC_ATOMIC == (int)vci_param::STORE_COND_ATOMIC);
825    soclib_static_assert((int)iss_t::SC_NOT_ATOMIC == (int)vci_param::STORE_COND_NOT_ATOMIC);
826};
827
828}}
829
830#endif /* SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER_H */
831
832// Local Variables:
833// tab-width: 4
834// c-basic-offset: 4
835// c-file-offsets:((innamespace . 0)(inline-open . 0))
836// indent-tabs-mode: nil
837// End:
838
839// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
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