source: branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h @ 827

Last change on this file since 827 was 827, checked in by devigne, 9 years ago

RWT Commit : vci_cc_vcache_wrapper cosmetic

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1/* -*- c++ -*-
2 *
3 * File : vci_cc_vcache_wrapper.h
4 * Copyright (c) UPMC, Lip6, SoC
5 * Authors : Alain GREINER, Yang GAO
6 * Date : 27/11/2011
7 *
8 * SOCLIB_LGPL_HEADER_BEGIN
9 *
10 * This file is part of SoCLib, GNU LGPLv2.1.
11 *
12 * SoCLib is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU Lesser General Public License as published
14 * by the Free Software Foundation; version 2.1 of the License.
15 *
16 * SoCLib is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
19 * Lesser General Public License for more details.
20 *
21 * You should have received a copy of the GNU Lesser General Public
22 * License along with SoCLib; if not, write to the Free Software
23 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
24 * 02110-1301 USA
25 *
26 * SOCLIB_LGPL_HEADER_END
27 *
28 * Maintainers: cesar.fuguet-tortolero@lip6.fr
29 *              alexandre.joannou@lip6.fr
30 */
31
32#ifndef SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER_H
33#define SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER_H
34
35#include <inttypes.h>
36#include <systemc>
37#include "caba_base_module.h"
38#include "multi_write_buffer.h"
39#include "generic_fifo.h"
40#include "generic_tlb.h"
41#include "generic_cache.h"
42#include "vci_initiator.h"
43#include "dspin_interface.h"
44#include "dspin_rwt_param.h"
45#include "mapping_table.h"
46#include "static_assert.h"
47#include "iss2.h"
48
49#define LLSC_TIMEOUT    10000
50
51namespace soclib {
52namespace caba {
53
54using namespace sc_core;
55
56////////////////////////////////////////////
57template<typename vci_param,
58         size_t   dspin_in_width,
59         size_t   dspin_out_width,
60         typename iss_t>
61class VciCcVCacheWrapper
62////////////////////////////////////////////
63    : public soclib::caba::BaseModule
64{
65
66    typedef typename vci_param::fast_addr_t  paddr_t;
67
68    enum icache_fsm_state_e
69    {
70        ICACHE_IDLE,
71        // handling XTN processor requests
72        ICACHE_XTN_TLB_FLUSH,
73        ICACHE_XTN_CACHE_FLUSH,
74        ICACHE_XTN_CACHE_FLUSH_GO,
75        ICACHE_XTN_TLB_INVAL,
76        ICACHE_XTN_CACHE_INVAL_VA,
77        ICACHE_XTN_CACHE_INVAL_PA,
78        ICACHE_XTN_CACHE_INVAL_GO,
79        // handling tlb miss
80        ICACHE_TLB_WAIT,
81        // handling cache miss
82        ICACHE_MISS_SELECT,
83        ICACHE_MISS_CLEAN,
84        ICACHE_MISS_WAIT,
85        ICACHE_MISS_DATA_UPDT,
86        ICACHE_MISS_DIR_UPDT,
87        // handling unc read
88        ICACHE_UNC_WAIT,
89        // handling coherence requests
90        ICACHE_CC_CHECK,
91        ICACHE_CC_UPDT,
92        ICACHE_CC_INVAL,
93    };
94
95    enum dcache_fsm_state_e
96    {
97        DCACHE_IDLE,
98        // handling itlb & dtlb miss
99        DCACHE_TLB_MISS,
100        DCACHE_TLB_PTE1_GET,
101        DCACHE_TLB_PTE1_SELECT,
102        DCACHE_TLB_PTE1_UPDT,
103        DCACHE_TLB_PTE2_GET,
104        DCACHE_TLB_PTE2_SELECT,
105        DCACHE_TLB_PTE2_UPDT,
106        DCACHE_TLB_LR_UPDT,
107        DCACHE_TLB_LR_WAIT,
108        DCACHE_TLB_RETURN,
109        // handling processor XTN requests
110        DCACHE_XTN_SWITCH,
111        DCACHE_XTN_SYNC,
112        DCACHE_XTN_IC_INVAL_VA,
113        DCACHE_XTN_IC_FLUSH,
114        DCACHE_XTN_IC_INVAL_PA,
115        DCACHE_XTN_IC_PADDR_EXT,
116        DCACHE_XTN_IT_INVAL,
117        DCACHE_XTN_DC_FLUSH,
118        DCACHE_XTN_DC_FLUSH_DATA,
119        DCACHE_XTN_DC_FLUSH_GO,
120        DCACHE_XTN_DC_INVAL_VA,
121        DCACHE_XTN_DC_INVAL_PA,
122        DCACHE_XTN_DC_INVAL_END,
123        DCACHE_XTN_DC_INVAL_GO,
124        DCACHE_XTN_DC_INVAL_DATA,
125        DCACHE_XTN_DT_INVAL,
126        //handling dirty bit update
127        DCACHE_DIRTY_GET_PTE,
128        DCACHE_DIRTY_WAIT,
129        // handling processor miss requests
130        DCACHE_MISS_SELECT,
131        DCACHE_MISS_CLEAN,
132        DCACHE_MISS_DATA,
133        DCACHE_MISS_WAIT,
134        DCACHE_MISS_DATA_UPDT,
135        DCACHE_MISS_DIR_UPDT,
136        // handling processor unc, ll and sc requests
137        DCACHE_UNC_WAIT,
138        DCACHE_LL_WAIT,
139        DCACHE_SC_WAIT,
140        // handling coherence requests
141        DCACHE_CC_CHECK,
142        DCACHE_CC_UPDT,
143        DCACHE_CC_INVAL,
144        DCACHE_CC_INVAL_DATA,
145        // handling TLB inval (after a coherence or XTN request)
146        DCACHE_INVAL_TLB_SCAN,
147    };
148
149    enum cmd_fsm_state_e
150    {
151        CMD_IDLE,
152        CMD_INS_MISS,
153        CMD_INS_UNC,
154        CMD_DATA_MISS,
155        CMD_DATA_UNC_READ,
156        CMD_DATA_UNC_WRITE,
157        CMD_DATA_WRITE,
158        CMD_DATA_LL,
159        CMD_DATA_SC,
160        CMD_DATA_CAS,
161    };
162
163    enum rsp_fsm_state_e
164    {
165        RSP_IDLE,
166        RSP_INS_MISS,
167        RSP_INS_UNC,
168        RSP_DATA_MISS,
169        RSP_DATA_UNC,
170        RSP_DATA_LL,
171        RSP_DATA_WRITE,
172    };
173
174    enum cc_receive_fsm_state_e
175    {
176        CC_RECEIVE_IDLE,
177        CC_RECEIVE_BRDCAST_HEADER,
178        CC_RECEIVE_BRDCAST_NLINE,
179        CC_RECEIVE_INS_INVAL_HEADER,
180        CC_RECEIVE_INS_INVAL_NLINE,
181        CC_RECEIVE_INS_UPDT_HEADER,
182        CC_RECEIVE_INS_UPDT_NLINE,
183        CC_RECEIVE_INS_UPDT_DATA,
184        CC_RECEIVE_DATA_INVAL_HEADER,
185        CC_RECEIVE_DATA_INVAL_NLINE,
186        CC_RECEIVE_DATA_UPDT_HEADER,
187        CC_RECEIVE_DATA_UPDT_NLINE,
188        CC_RECEIVE_DATA_UPDT_DATA,
189    };
190
191    enum cc_send_fsm_state_e
192    {
193        CC_SEND_IDLE,
194        CC_SEND_CLEANUP_1,
195        CC_SEND_CLEANUP_2,
196        CC_SEND_CLEANUP_DATA_UPDT,
197        CC_SEND_MULTI_ACK,
198    };
199
200    /* transaction type, pktid field */
201    enum transaction_type_e
202    {
203        // b3 unused
204        // b2 READ / NOT READ
205        // if READ
206        //  b1 DATA / INS
207        //  b0 UNC / MISS
208        // else
209        //  b1 accÚs table llsc type SW / other
210        //  b2 WRITE/CAS/LL/SC
211        TYPE_DATA_UNC               = 0x0,
212        TYPE_READ_DATA_MISS         = 0x1,
213        TYPE_READ_INS_UNC           = 0x2,
214        TYPE_READ_INS_MISS          = 0x3,
215        TYPE_WRITE                  = 0x4,
216        TYPE_CAS                    = 0x5,
217        TYPE_LL                     = 0x6,
218        TYPE_SC                     = 0x7
219    };
220
221    /* SC return values */
222    enum sc_status_type_e
223    {
224        SC_SUCCESS  =   0x00000000,
225        SC_FAIL     =   0x00000001
226    };
227
228    // cc_send_type
229    typedef enum
230    {
231        CC_TYPE_CLEANUP,
232        CC_TYPE_MULTI_ACK,
233    } cc_send_t;
234
235    // cc_receive_type
236    typedef enum
237    {
238        CC_TYPE_CLACK,
239        CC_TYPE_BRDCAST,
240        CC_TYPE_INVAL,
241        CC_TYPE_UPDT,
242    } cc_receive_t;
243
244    // TLB Mode : ITLB / DTLB / ICACHE / DCACHE
245    enum
246    {
247        INS_TLB_MASK    = 0x8,
248        DATA_TLB_MASK   = 0x4,
249        INS_CACHE_MASK  = 0x2,
250        DATA_CACHE_MASK = 0x1,
251    };
252
253    // Error Type
254    enum mmu_error_type_e
255    {
256        MMU_NONE                      = 0x0000, // None
257        MMU_WRITE_PT1_UNMAPPED        = 0x0001, // Write & Page fault on PT1
258        MMU_WRITE_PT2_UNMAPPED        = 0x0002, // Write & Page fault on PT2
259        MMU_WRITE_PRIVILEGE_VIOLATION = 0x0004, // Write & Protected access in user mode
260        MMU_WRITE_ACCES_VIOLATION     = 0x0008, // Write to non writable page
261        MMU_WRITE_UNDEFINED_XTN       = 0x0020, // Write & undefined external access
262        MMU_WRITE_PT1_ILLEGAL_ACCESS  = 0x0040, // Write & Bus Error accessing PT1
263        MMU_WRITE_PT2_ILLEGAL_ACCESS  = 0x0080, // Write & Bus Error accessing PT2
264        MMU_WRITE_DATA_ILLEGAL_ACCESS = 0x0100, // Write & Bus Error in cache access
265        MMU_READ_PT1_UNMAPPED         = 0x1001, // Read & Page fault on PT1
266        MMU_READ_PT2_UNMAPPED         = 0x1002, // Read & Page fault on PT2
267        MMU_READ_PRIVILEGE_VIOLATION  = 0x1004, // Read & Protected access in user mode
268        MMU_READ_EXEC_VIOLATION       = 0x1010, // Read & Exec access to a non exec page
269        MMU_READ_UNDEFINED_XTN        = 0x1020, // Read & Undefined external access
270        MMU_READ_PT1_ILLEGAL_ACCESS   = 0x1040, // Read & Bus Error accessing PT1
271        MMU_READ_PT2_ILLEGAL_ACCESS   = 0x1080, // Read & Bus Error accessing PT2
272        MMU_READ_DATA_ILLEGAL_ACCESS  = 0x1100, // Read & Bus Error in cache access
273    };
274
275    // miss types for data cache
276    enum dcache_miss_type_e
277    {
278        PTE1_MISS,
279        PTE2_MISS,
280        PROC_MISS,
281    };
282
283
284    // cache line status
285    enum content_line_cache_status_e
286    {
287        LINE_CACHE_DATA_NOT_DIRTY,
288        LINE_CACHE_DATA_DIRTY,
289        LINE_CACHE_IN_TLB,
290        LINE_CACHE_CONTAINS_PTD,
291    };
292    //////////////////////////////////////////
293
294public:
295    sc_in<bool>                                p_clk;
296    sc_in<bool>                                p_resetn;
297    sc_in<bool>                                p_irq[iss_t::n_irq];
298    soclib::caba::VciInitiator<vci_param>      p_vci;
299    soclib::caba::DspinInput<dspin_in_width>   p_dspin_m2p;
300    soclib::caba::DspinOutput<dspin_out_width> p_dspin_p2m;
301    soclib::caba::DspinInput<dspin_in_width>   p_dspin_clack;
302
303private:
304
305    // STRUCTURAL PARAMETERS
306    soclib::common::AddressDecodingTable<uint64_t, bool> m_cacheability_table;
307
308    const size_t   m_srcid;
309    const size_t   m_cc_global_id;
310    const size_t   m_nline_width;
311    const size_t   m_itlb_ways;
312    const size_t   m_itlb_sets;
313    const size_t   m_dtlb_ways;
314    const size_t   m_dtlb_sets;
315    const size_t   m_icache_ways;
316    const size_t   m_icache_sets;
317    const paddr_t  m_icache_yzmask;
318    const size_t   m_icache_words;
319    const size_t   m_dcache_ways;
320    const size_t   m_dcache_sets;
321    const paddr_t  m_dcache_yzmask;
322    const size_t   m_dcache_words;
323    const size_t   m_x_width;
324    const size_t   m_y_width;
325    const size_t   m_proc_id;
326    const uint32_t m_max_frozen_cycles;
327    const size_t   m_paddr_nbits;
328    uint32_t       m_debug_start_cycle;
329    bool           m_debug_ok;
330
331    uint32_t       m_dcache_paddr_ext_reset;
332    uint32_t       m_icache_paddr_ext_reset;
333
334    ////////////////////////////////////////
335    // Communication with processor ISS
336    ////////////////////////////////////////
337    typename iss_t::InstructionRequest  m_ireq;
338    typename iss_t::InstructionResponse m_irsp;
339    typename iss_t::DataRequest         m_dreq;
340    typename iss_t::DataResponse        m_drsp;
341
342    /////////////////////////////////////////////
343    // debug variables
344    /////////////////////////////////////////////
345    bool m_debug_previous_i_hit;
346    bool m_debug_previous_d_hit;
347    bool m_debug_activated;
348
349    ///////////////////////////////
350    // Software visible REGISTERS
351    ///////////////////////////////
352    sc_signal<uint32_t> r_mmu_ptpr;    // page table pointer register
353    sc_signal<uint32_t> r_mmu_mode;    // mmu mode register
354    sc_signal<uint32_t> r_mmu_word_lo; // mmu misc data low
355    sc_signal<uint32_t> r_mmu_word_hi; // mmu misc data hight
356    sc_signal<uint32_t> r_mmu_ibvar;   // mmu bad instruction address
357    sc_signal<uint32_t> r_mmu_dbvar;   // mmu bad data address
358    sc_signal<uint32_t> r_mmu_ietr;    // mmu instruction error type
359    sc_signal<uint32_t> r_mmu_detr;    // mmu data error type
360    uint32_t            r_mmu_params;  // read-only
361    uint32_t            r_mmu_release; // read_only
362
363
364    //////////////////////////////
365    // ICACHE FSM REGISTERS
366    //////////////////////////////
367    sc_signal<int>      r_icache_fsm;        // state register
368    sc_signal<int>      r_icache_fsm_save;   // return state for coherence op
369    sc_signal<paddr_t>  r_icache_vci_paddr;  // physical address
370    sc_signal<uint32_t> r_icache_vaddr_save; // virtual address from processor
371
372    // icache miss handling
373    sc_signal<size_t>   r_icache_miss_way;   // selected way for cache update
374    sc_signal<size_t>   r_icache_miss_set;   // selected set for cache update
375    sc_signal<size_t>   r_icache_miss_word;  // word index ( cache update)
376    sc_signal<bool>     r_icache_miss_inval; // coherence request matching a miss
377    sc_signal<bool>     r_icache_miss_clack; // waiting for a cleanup acknowledge
378
379    // coherence request handling
380    sc_signal<size_t>   r_icache_cc_way;        // selected way for cc update/inval
381    sc_signal<size_t>   r_icache_cc_set;        // selected set for cc update/inval
382    sc_signal<size_t>   r_icache_cc_word;       // word counter for cc update
383    sc_signal<bool>     r_icache_cc_need_write; // activate the cache for writing
384
385    // coherence clack handling
386    sc_signal<bool>     r_icache_clack_req; // clack request
387    sc_signal<size_t>   r_icache_clack_way; // clack way
388    sc_signal<size_t>   r_icache_clack_set; // clack set
389
390    // icache flush handling
391    sc_signal<size_t>   r_icache_flush_count; // slot counter used for cache flush
392
393    // communication between ICACHE FSM and VCI_CMD FSM
394    sc_signal<bool>     r_icache_miss_req; // cached read miss
395    sc_signal<bool>     r_icache_unc_req;  // uncached read miss
396
397    // communication between ICACHE FSM and DCACHE FSM
398    sc_signal<bool>     r_icache_tlb_miss_req;  // (set icache/reset dcache)
399    sc_signal<bool>     r_icache_tlb_rsp_error; // tlb miss response error
400
401    // Flip-Flop in ICACHE FSM for saving the cleanup victim request
402    sc_signal<bool>     r_icache_cleanup_victim_req;
403    sc_signal<paddr_t>  r_icache_cleanup_victim_nline;
404
405    // communication between ICACHE FSM and CC_SEND FSM
406    sc_signal<bool>     r_icache_cc_send_req;          // ICACHE cc_send request
407    sc_signal<int>      r_icache_cc_send_type;         // ICACHE cc_send request type
408    sc_signal<paddr_t>  r_icache_cc_send_nline;        // ICACHE cc_send nline
409    sc_signal<size_t>   r_icache_cc_send_way;          // ICACHE cc_send way
410    sc_signal<size_t>   r_icache_cc_send_updt_tab_idx; // ICACHE cc_send update table index
411
412    // Physical address extension for data access
413    sc_signal<uint32_t> r_icache_paddr_ext; // CP2 register (if vci_address > 32)
414
415    ///////////////////////////////
416    // DCACHE FSM REGISTERS
417    ///////////////////////////////
418    sc_signal<int>      r_dcache_fsm;             // state register
419    sc_signal<int>      r_dcache_fsm_cc_save;     // return state for coherence op
420    sc_signal<int>      r_dcache_fsm_scan_save;   // return state for tlb scan op
421    // registers written in P0 stage (used in P1 stage)
422    sc_signal<bool>     r_dcache_wbuf_req;        // WBUF must be written in P1 stage
423    sc_signal<bool>     r_dcache_updt_req;        // DCACHE must be updated in P1 stage
424    sc_signal<uint32_t> r_dcache_save_vaddr;      // virtual address (from proc)
425    sc_signal<uint32_t> r_dcache_save_wdata;      // write data (from proc)
426    sc_signal<uint32_t> r_dcache_save_be;         // byte enable (from proc)
427    sc_signal<paddr_t>  r_dcache_save_paddr;      // physical address
428    sc_signal<size_t>   r_dcache_save_cache_way;  // selected way (from dcache)
429    sc_signal<size_t>   r_dcache_save_cache_set;  // selected set (from dcache)
430    sc_signal<size_t>   r_dcache_save_cache_word; // selected word (from dcache)
431    // registers used by the Dirty bit sub-fsm
432    sc_signal<paddr_t>  r_dcache_dirty_paddr; // PTE physical address
433    sc_signal<size_t>   r_dcache_dirty_way;   // way to invalidate in dcache
434    sc_signal<size_t>   r_dcache_dirty_set;   // set to invalidate in dcache
435
436    // communication between DCACHE FSM and VCI_CMD FSM
437    sc_signal<paddr_t>  r_dcache_vci_paddr;     // physical address for VCI command
438    sc_signal<uint32_t> r_dcache_vci_wdata;     // write unc data for VCI command
439    sc_signal<bool>     r_dcache_vci_miss_req;  // read miss request
440    sc_signal<bool>     r_dcache_vci_unc_req;   // uncacheable request (read/write)
441    sc_signal<uint32_t> r_dcache_vci_unc_be;    // uncacheable byte enable
442    sc_signal<uint32_t> r_dcache_vci_unc_write; // uncacheable data write request
443    sc_signal<bool>     r_dcache_vci_cas_req;   // atomic write request CAS
444    sc_signal<uint32_t> r_dcache_vci_cas_old;   // previous data value for a CAS
445    sc_signal<uint32_t> r_dcache_vci_cas_new;   // new data value for a CAS
446    sc_signal<bool>     r_dcache_vci_ll_req;    // atomic read request LL
447    sc_signal<bool>     r_dcache_vci_sc_req;    // atomic write request SC
448    sc_signal<uint32_t> r_dcache_vci_sc_data;   // SC data (command)
449
450    //RWT: local cas
451    sc_signal<bool>     r_cas_islocal;
452    sc_signal<size_t>   r_cas_local_way;
453    sc_signal<size_t>   r_cas_local_set;
454    sc_signal<size_t>   r_cas_local_word;
455
456    // register used for XTN inval
457    sc_signal<size_t>   r_dcache_xtn_way; // selected way (from dcache)
458    sc_signal<size_t>   r_dcache_xtn_set; // selected set (from dcache)
459
460    // handling dcache miss
461    sc_signal<int>      r_dcache_miss_type;  // depending on the requester
462    sc_signal<size_t>   r_dcache_miss_word;  // word index for cache update
463    sc_signal<size_t>   r_dcache_miss_way;   // selected way for cache update
464    sc_signal<size_t>   r_dcache_miss_set;   // selected set for cache update
465    sc_signal<bool>     r_dcache_miss_inval; // coherence request matching a miss
466    sc_signal<bool>     r_dcache_miss_clack; // waiting for a cleanup acknowledge
467
468    // handling coherence requests
469    sc_signal<size_t>   r_dcache_cc_way;        // selected way for cc update/inval
470    sc_signal<size_t>   r_dcache_cc_set;        // selected set for cc update/inval
471    sc_signal<int>      r_dcache_cc_state;      // state of selected cache slot
472    sc_signal<size_t>   r_dcache_cc_word;       // word counter for cc update
473    sc_signal<bool>     r_dcache_cc_need_write; // activate the cache for writing
474    sc_signal<paddr_t>  r_dcache_cc_inval_addr; // address for a cleanup transaction
475    sc_signal<uint32_t> r_dcache_cc_inval_data_cpt;
476
477    // coherence clack handling
478    sc_signal<bool>     r_dcache_clack_req; // clack request
479    sc_signal<size_t>   r_dcache_clack_way; // clack way
480    sc_signal<size_t>   r_dcache_clack_set; // clack set
481
482    // dcache flush handling
483    sc_signal<size_t>   r_dcache_flush_count; // slot counter used for cache flush
484
485    // ll response handling
486    sc_signal<size_t>   r_dcache_ll_rsp_count; // flit counter used for ll rsp
487
488    // used by the TLB miss sub-fsm
489    sc_signal<uint32_t> r_dcache_tlb_vaddr;      // virtual address for a tlb miss
490    sc_signal<bool>     r_dcache_tlb_ins;        // target tlb (itlb if true)
491    sc_signal<paddr_t>  r_dcache_tlb_paddr;      // physical address of pte
492    sc_signal<uint32_t> r_dcache_tlb_pte_flags;  // pte1 or first word of pte2
493    sc_signal<uint32_t> r_dcache_tlb_pte_ppn;    // second word of pte2
494    sc_signal<size_t>   r_dcache_tlb_cache_way;  // selected way in dcache
495    sc_signal<size_t>   r_dcache_tlb_cache_set;  // selected set in dcache
496    sc_signal<size_t>   r_dcache_tlb_cache_word; // selected word in dcache
497    sc_signal<size_t>   r_dcache_tlb_way;        // selected way in tlb
498    sc_signal<size_t>   r_dcache_tlb_set;        // selected set in tlb
499
500    // ITLB and DTLB invalidation
501    sc_signal<paddr_t>  r_dcache_tlb_inval_line; // line index
502    sc_signal<size_t>   r_dcache_tlb_inval_set;  // tlb set counter
503
504    // communication between DCACHE FSM and ICACHE FSM
505    sc_signal<bool>     r_dcache_xtn_req;    // xtn request (caused by processor)
506    sc_signal<int>      r_dcache_xtn_opcode; // xtn request type
507
508    // Filp-Flop in DCACHE FSM for saving the cleanup victim request
509    sc_signal<bool>     r_dcache_cleanup_victim_req;
510    sc_signal<bool>     r_dcache_cleanup_victim_line_ncc;
511    sc_signal<bool>     r_dcache_cleanup_victim_updt_data;
512    sc_signal<paddr_t>  r_dcache_cleanup_victim_nline;
513
514    // communication between DCACHE FSM and CC_SEND FSM
515    sc_signal<bool>     r_dcache_cc_send_req;          // DCACHE cc_send request
516    sc_signal<int>      r_dcache_cc_send_type;         // DCACHE cc_send request type
517    sc_signal<paddr_t>  r_dcache_cc_send_nline;        // DCACHE cc_send nline
518    sc_signal<size_t>   r_dcache_cc_send_way;          // DCACHE cc_send way
519    sc_signal<size_t>   r_dcache_cc_send_updt_tab_idx; // DCACHE cc_send update table index
520
521    // special registers for RWT
522    sc_signal<bool>     r_dcache_cc_cleanup_updt_data; // Register for cleanup with data (wb updt)
523    sc_signal<bool>     r_dcache_cc_cleanup_line_ncc;  // Register for cleanup with data (wb updt)
524    sc_signal<bool>     r_dcache_dirty_save;
525    sc_signal<uint32_t> r_cc_send_cpt_word;
526    sc_signal<uint32_t> r_dcache_miss_data_cpt;
527    sc_signal<paddr_t>  r_dcache_miss_data_addr;
528    sc_signal<uint32_t> r_dcache_xtn_flush_data_cpt;
529    sc_signal<paddr_t>  r_dcache_xtn_flush_addr_data;
530    sc_signal<int>      r_dcache_xtn_state;
531    sc_signal<paddr_t>  r_dcache_xtn_data_addr;
532    sc_signal<uint32_t> r_dcache_xtn_data_cpt;
533    sc_signal<bool>     r_dcache_read_state;
534
535    // dcache directory extension
536    int                 *r_dcache_content_state; // content state of one cache line
537    // Stats
538    int                 *r_dcache_dirty_word;    // use for compute number of words dirty per cleanup_data
539    bool                *r_dcache_zombi_ncc;     // use for compute number of blocked write on ncc zombi line
540    //////////////////////////////////////////////////////////////////////////////////////
541
542    ///////////////////////////////////
543    // Physical address extension for data access
544    sc_signal<uint32_t> r_dcache_paddr_ext; // CP2 register (if vci_address > 32)
545
546    ///////////////////////////////////
547    // VCI_CMD FSM REGISTERS
548    ///////////////////////////////////
549    sc_signal<int>      r_vci_cmd_fsm;
550    sc_signal<size_t>   r_vci_cmd_min;        // used for write bursts
551    sc_signal<size_t>   r_vci_cmd_max;        // used for write bursts
552    sc_signal<size_t>   r_vci_cmd_cpt;        // used for write bursts
553    sc_signal<bool>     r_vci_cmd_imiss_prio; // round-robin between imiss & dmiss
554
555    ///////////////////////////////////
556    // VCI_RSP FSM REGISTERS
557    ///////////////////////////////////
558    sc_signal<int>        r_vci_rsp_fsm;
559    sc_signal<size_t>     r_vci_rsp_cpt;
560    sc_signal<bool>       r_vci_rsp_ins_error;
561    sc_signal<bool>       r_vci_rsp_data_error;
562    GenericFifo<uint32_t> r_vci_rsp_fifo_icache; // response FIFO to ICACHE FSM
563    GenericFifo<uint32_t> r_vci_rsp_fifo_dcache; // response FIFO to DCACHE FSM
564
565
566    //RWT
567    GenericFifo<bool>     r_vci_rsp_fifo_rpktid;
568    GenericFifo<uint32_t> r_cc_send_data_fifo;
569
570    ///////////////////////////////////
571    //  CC_SEND FSM REGISTER
572    ///////////////////////////////////
573    sc_signal<int>        r_cc_send_fsm;         // state register
574    sc_signal<bool>       r_cc_send_last_client; // 0 dcache / 1 icache
575
576    ///////////////////////////////////
577    //  CC_RECEIVE FSM REGISTER
578    ///////////////////////////////////
579    sc_signal<int>        r_cc_receive_fsm;      // state register
580    sc_signal<bool>       r_cc_receive_data_ins; // request to : 0 dcache / 1 icache
581
582    // communication between CC_RECEIVE FSM and ICACHE/DCACHE FSM
583    sc_signal<size_t>     r_cc_receive_word_idx;       // word index
584    GenericFifo<uint32_t> r_cc_receive_updt_fifo_be;
585    GenericFifo<uint32_t> r_cc_receive_updt_fifo_data;
586    GenericFifo<bool>     r_cc_receive_updt_fifo_eop;
587
588    // communication between CC_RECEIVE FSM and ICACHE FSM
589    sc_signal<bool>       r_cc_receive_icache_req;          // cc_receive to icache request
590    sc_signal<int>        r_cc_receive_icache_type;         // cc_receive type of request
591    sc_signal<size_t>     r_cc_receive_icache_way;          // cc_receive to icache way
592    sc_signal<size_t>     r_cc_receive_icache_set;          // cc_receive to icache set
593    sc_signal<size_t>     r_cc_receive_icache_updt_tab_idx; // cc_receive update table index
594    sc_signal<paddr_t>    r_cc_receive_icache_nline;        // cache line physical address
595
596    // communication between CC_RECEIVE FSM and DCACHE FSM
597    sc_signal<bool>       r_cc_receive_dcache_req;             // cc_receive to dcache request
598    sc_signal<int>        r_cc_receive_dcache_type;            // cc_receive type of request
599    sc_signal<size_t>     r_cc_receive_dcache_way;             // cc_receive to dcache way
600    sc_signal<size_t>     r_cc_receive_dcache_set;             // cc_receive to dcache set
601    sc_signal<size_t>     r_cc_receive_dcache_updt_tab_idx;    // cc_receive update table index
602    sc_signal<paddr_t>    r_cc_receive_dcache_nline;           // cache line physical address
603    sc_signal<bool>       r_cc_receive_dcache_inval_is_config; // inval from memcache is config
604
605    ///////////////////////////////////
606    //  DSPIN CLACK INTERFACE REGISTER
607    ///////////////////////////////////
608    sc_signal<bool>       r_dspin_clack_req;
609    sc_signal<uint64_t>   r_dspin_clack_flit;
610
611    //////////////////////////////////////////////////////////////////
612    // processor, write buffer, caches , TLBs
613    //////////////////////////////////////////////////////////////////
614
615    iss_t                     r_iss;
616    MultiWriteBuffer<paddr_t> r_wbuf;
617    GenericCache<paddr_t>     r_icache;
618    GenericCache<paddr_t>     r_dcache;
619    GenericTlb<paddr_t>       r_itlb;
620    GenericTlb<paddr_t>       r_dtlb;
621
622    //////////////////////////////////////////////////////////////////
623    // llsc registration buffer
624    //////////////////////////////////////////////////////////////////
625
626    sc_signal<paddr_t>  r_dcache_llsc_paddr;
627    sc_signal<uint32_t> r_dcache_llsc_key;
628    sc_signal<uint32_t> r_dcache_llsc_count;
629    sc_signal<bool>     r_dcache_llsc_valid;
630
631    ////////////////////////////////
632    // Activity counters
633    ////////////////////////////////
634    uint32_t m_cpt_dcache_data_read;        // DCACHE DATA READ
635    uint32_t m_cpt_dcache_data_write;       // DCACHE DATA WRITE
636    uint32_t m_cpt_dcache_dir_read;         // DCACHE DIR READ
637    uint32_t m_cpt_dcache_dir_write;        // DCACHE DIR WRITE
638
639    uint32_t m_cpt_icache_data_read;        // ICACHE DATA READ
640    uint32_t m_cpt_icache_data_write;       // ICACHE DATA WRITE
641    uint32_t m_cpt_icache_dir_read;         // ICACHE DIR READ
642    uint32_t m_cpt_icache_dir_write;        // ICACHE DIR WRITE
643
644    uint32_t m_cpt_frz_cycles;              // number of cycles where the cpu is frozen
645    uint32_t m_cpt_total_cycles;            // total number of cycles
646
647    // Cache activity counters
648    uint32_t m_cpt_data_read;               // total number of read data
649    uint32_t m_cpt_data_write;              // total number of write data
650    uint32_t m_cpt_data_write_back;
651    uint32_t m_cpt_data_write_miss;         // number of total write miss
652    uint32_t m_cpt_data_write_on_zombi;     // number of frozen cycles related to blocked write on ZOMBI line
653    uint32_t m_cpt_data_write_on_zombi_ncc; // number of frozen cycles related to blocked write on NCC ZOMBI line
654    uint32_t m_cpt_data_cleanup;
655    uint32_t m_cpt_data_sc;
656    uint32_t m_cpt_dcache_miss;             // number of read miss
657    uint32_t m_cpt_icache_miss;             // number of instruction miss
658    uint32_t m_cpt_ins_read;                // number of instruction read
659
660    uint32_t m_cost_data_miss_frz;          // number of frozen cycles related to data miss
661    uint32_t m_cost_ins_miss_frz;           // number of frozen cycles related to ins miss
662
663    uint32_t m_cpt_write_transaction;       // number of VCI write transactions
664    uint32_t m_length_write_transaction;    // cumulated length for VCI WRITE transactions
665
666    // TLB activity counters
667    uint32_t m_cpt_itlb_read;               // number of instruction tlb read
668    uint32_t m_cpt_itlb_miss;               // number of instruction tlb miss
669    uint32_t m_cpt_itlb_write;              // number of instruction tlb update
670
671    uint32_t m_cpt_dtlb_read;               // number of data tlb read
672    uint32_t m_cpt_dtlb_miss;               // number of data tlb miss
673    uint32_t m_cpt_dtlb_write;              // number of data tlb update
674
675    uint32_t m_cost_ins_tlb_miss_frz;       // number of frozen cycles related to instruction tlb miss
676
677    // coherence activity counters
678    uint32_t m_cpt_cleanup_data_not_dirty;  // number of total cleanup data without extra data flits
679    uint32_t m_cpt_cleanup_data_dirty_word; // number of total words dirty in cleanup data
680
681
682
683    // counters NOT implemented
684    uint32_t m_cost_write_frz; // number of frozen cycles related to write buffer
685    uint32_t m_cost_unc_read_frz; // number of frozen cycles related to uncached read
686    uint32_t m_cpt_imiss_transaction; // number of VCI instruction miss transactions
687    uint32_t m_cpt_dmiss_transaction; // number of VCI data miss transactions
688    uint32_t m_cpt_unc_transaction; // number of VCI uncached read transactions
689    uint32_t m_cost_imiss_transaction; // cumulated duration for VCI IMISS transactions
690    uint32_t m_cost_dmiss_transaction; // cumulated duration for VCI DMISS transactions
691    uint32_t m_cost_unc_transaction; // cumulated duration for VCI UNC transactions
692    uint32_t m_cost_write_transaction; // cumulated duration for VCI WRITE transactions
693    uint32_t m_cpt_data_tlb_update_dirty; // number of data tlb update dirty
694    uint32_t m_cpt_ins_tlb_hit_dcache; // number of instruction tlb hit in data cache
695    uint32_t m_cpt_data_tlb_hit_dcache; // number of data tlb hit in data cache
696    uint32_t m_cost_data_tlb_miss_frz; // number of frozen cycles related to data tlb miss
697    uint32_t m_cost_ins_tlb_update_acc_frz; // number of frozen cycles related to instruction tlb update acc
698    uint32_t m_cost_data_tlb_update_acc_frz; // number of frozen cycles related to data tlb update acc
699    uint32_t m_cost_data_tlb_update_dirty_frz; // number of frozen cycles related to data tlb update dirty
700    uint32_t m_cpt_itlbmiss_transaction; // number of itlb miss transactions
701    uint32_t m_cpt_dtlbmiss_transaction; // number of dtlb miss transactions
702    uint32_t m_cost_itlbmiss_transaction; // cumulated duration for VCI instruction TLB miss transactions
703    uint32_t m_cost_dtlbmiss_transaction; // cumulated duration for VCI data TLB miss transactions
704    uint32_t m_cpt_cc_broadcast; // number of coherence broadcast commands
705    uint32_t m_cost_updt_data_frz; // number of frozen cycles related to coherence update data packets
706    uint32_t m_cost_inval_ins_frz; // number of frozen cycles related to coherence inval instruction packets
707    uint32_t m_cost_inval_data_frz; // number of frozen cycles related to coherence inval data packets
708    uint32_t m_cost_broadcast_frz; // number of frozen cycles related to coherence broadcast packets
709    uint32_t m_cpt_cc_cleanup_data; // number of coherence cleanup packets
710    uint32_t m_cpt_cc_cleanup_ins; // number of coherence cleanup packets
711    uint32_t m_cpt_dunc_transaction; // number of VCI uncached read transactions
712    uint32_t m_cpt_ll_transaction; // number of VCI uncached read transactions
713    uint32_t m_cpt_cc_update_dcache; // number of coherence update data commands
714    uint32_t m_cpt_cc_inval_icache; // number of coherence inval instruction commands
715    uint32_t m_cpt_cc_inval_dcache; // number of coherence inval data commands
716    uint32_t m_cpt_unc_read; // number of read uncached
717    uint32_t m_cpt_write_cached; // number of cached write
718    uint32_t m_cpt_tlb_occup_dcache;
719
720
721    // FSM activity counters
722    uint32_t m_cpt_fsm_icache     [64];
723    uint32_t m_cpt_fsm_dcache     [64];
724    uint32_t m_cpt_fsm_cmd        [64];
725    uint32_t m_cpt_fsm_rsp        [64];
726    uint32_t m_cpt_fsm_cc_receive [64];
727    uint32_t m_cpt_fsm_cc_send    [64];
728
729    uint32_t m_cpt_stop_simulation; // used to stop simulation if frozen
730    bool     m_monitor_ok;          // used to debug cache output
731    uint32_t m_monitor_base;
732    uint32_t m_monitor_length;
733
734protected:
735    SC_HAS_PROCESS(VciCcVCacheWrapper);
736
737public:
738    VciCcVCacheWrapper(
739        sc_module_name                     name,
740        const int                          proc_id,
741        const soclib::common::MappingTable &mtd,
742        const soclib::common::IntTab       &srcid,
743        const size_t                       cc_global_id,
744        const size_t                       itlb_ways,
745        const size_t                       itlb_sets,
746        const size_t                       dtlb_ways,
747        const size_t                       dtlb_sets,
748        const size_t                       icache_ways,
749        const size_t                       icache_sets,
750        const size_t                       icache_words,
751        const size_t                       dcache_ways,
752        const size_t                       dcache_sets,
753        const size_t                       dcache_words,
754        const size_t                       wbuf_nlines,
755        const size_t                       wbuf_nwords,
756        const size_t                       x_width,
757        const size_t                       y_width,
758        const uint32_t                     max_frozen_cycles,
759        const uint32_t                     debug_start_cycle,
760        const bool                         debug_ok );
761
762    ~VciCcVCacheWrapper();
763
764    void print_cpi();
765    void print_stats();
766    void clear_stats();
767    void print_trace(size_t mode = 0);
768    bool frozen();
769    void cache_monitor(paddr_t addr);
770    void start_monitor(paddr_t,paddr_t);
771    void stop_monitor();
772    inline void iss_set_debug_mask(uint v)
773    {
774        r_iss.set_debug_mask(v);
775    }
776
777    /////////////////////////////////////////////////////////////
778    // Set the m_dcache_paddr_ext_reset attribute
779    //
780    // The r_dcache_paddr_ext register will be initialized after
781    // reset with the m_dcache_paddr_ext_reset value
782    /////////////////////////////////////////////////////////////
783    inline void set_dcache_paddr_ext_reset(uint32_t v)
784    {
785        m_dcache_paddr_ext_reset = v;
786    }
787
788    /////////////////////////////////////////////////////////////
789    // Set the m_icache_paddr_ext_reset attribute
790    //
791    // The r_icache_paddr_ext register will be initialized after
792    // reset with the m_icache_paddr_ext_reset value
793    /////////////////////////////////////////////////////////////
794    inline void set_icache_paddr_ext_reset(uint32_t v)
795    {
796        m_icache_paddr_ext_reset = v;
797    }
798
799private:
800    void transition();
801    void genMoore();
802
803    soclib_static_assert((int)iss_t::SC_ATOMIC == (int)vci_param::STORE_COND_ATOMIC);
804    soclib_static_assert((int)iss_t::SC_NOT_ATOMIC == (int)vci_param::STORE_COND_NOT_ATOMIC);
805};
806
807}}
808
809#endif /* SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER_H */
810
811// Local Variables:
812// tab-width: 4
813// c-basic-offset: 4
814// c-file-offsets:((innamespace . 0)(inline-open . 0))
815// indent-tabs-mode: nil
816// End:
817
818// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
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