source: branches/RWT/modules/vci_mem_cache/caba/metadata/vci_mem_cache.sd @ 767

Last change on this file since 767 was 468, checked in by cfuguet, 9 years ago


Merging vci_mem_cache from branches/v5 to trunk [441-467]

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r441 | cfuguet | 2013-07-17 10:54:07 +0200 (Wed, 17 Jul 2013) | 14 lines

Modifications in branches/v5/vci_mem_cache:

  • Changing name of CC DSPIN ports: + p_dspin_in => p_dspin_p2m + p_dspin_out => p_dspin_m2p
  • Splitting the Update Table in two tables: + UPT (Update Table): Stores the MULTI-UPDATE transactions + IVT (Invalidate Table): Stores the MULTI/BROADCAST INVALIDATE

transactions

Each table has its own allocator FSM: r_alloc_upt and r_alloc_ivt

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r442 | cfuguet | 2013-07-17 12:13:51 +0200 (Wed, 17 Jul 2013) | 13 lines

Modifications in branches/v5/modules/vci_mem_cache:

  • Introducing third port for the CLACK network.
  • CLEANUP FSM is no more a CC_SEND FSM client.
  • CLEANUP FSM controls directly the p_dspin_clack port

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r445 | cfuguet | 2013-07-18 10:49:36 +0200 (Thu, 18 Jul 2013) | 7 lines

Bugfix in vci_mem_cache:

  • Adding missing "strings" for print_trace() function
  • Adding alloc_ivt fsm (Invalidate Table) in the

print_trace() function

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r455 | cfuguet | 2013-07-19 10:16:17 +0200 (Fri, 19 Jul 2013) | 8 lines

Merged

/trunk/modules/vci_mem_cache:449 with
/branches/v5/modules/vci_mem_cache:446.

This merge introduces into the branch the last modifications concerning
the VCI memory cache configuration interface


Merging vci_cc_vcache_wrapper from branches/v5 to trunk [444-467]

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r444 | cfuguet | 2013-07-17 14:46:46 +0200 (Wed, 17 Jul 2013) | 7 lines

Modifications in branches/v5/modules/vci_cc_vcache_wrapper:

  • Renaming FROM_MC DSPIN flits fields in M2P
  • Renaming FROM_L1 DSPIN flits fields in P2M
  • Renaming CLEANUP_ACK DSPIN flits fields in CLACK

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r446 | cfuguet | 2013-07-18 11:37:47 +0200 (Thu, 18 Jul 2013) | 13 lines

Modifications in vci_cc_vcache_wrapper:

  • Merging the states DCACHE/ICACHE_CC_BROADCAST and DCACHE/ICACHE_CC_INVAL. This is because, the BROADCAST INVALIDATE and the MULTICAST INVALIDATE are both acknowledged by a CLEANUP.
  • Adding third port for the clack coherence network.
  • Renaming the port dspin_in to dspin_m2p and the port dspin_out to dspin_p2m

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r454 | haoliu | 2013-07-19 10:15:13 +0200 (Fri, 19 Jul 2013) | 2 lines

modified CC_RECEIVE FSM and CC_CHECK FSM (icache and dcache) for new
version V5

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r461 | cfuguet | 2013-07-19 15:49:43 +0200 (Fri, 19 Jul 2013) | 9 lines

Bugfix in vci_cc_vcache_wrapper:

  • In the states DCACHE/ICACHE CC_UPDT the FSM returns to the state CC_CHECK only when the cc_send_req is occupied.

We must not return to the CC_CHECK state if not ROK of the
DATA FIFO because the counter word counter will be reset.

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r462 | cfuguet | 2013-07-19 16:26:26 +0200 (Fri, 19 Jul 2013) | 8 lines

Modification in vci_cc_vcache_wrapper:

  • Optimization in DCACHE/ICACHE CC_CHECK state. We can handle a CLACK and a CC request if the latter does a MISS match. This is because the CC request doing MISS match does not need to access the directory

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r463 | cfuguet | 2013-07-19 16:52:06 +0200 (Fri, 19 Jul 2013) | 12 lines

Modification in vci_cc_vcache_wrapper:

  • Optimization in DCACHE/ICACHE CC_CHECK state. If pending request to CC_SEND, we wait in the CC_CHECK state. Doing this, during the wait, we can handle incoming CLACK avoiding any deadlock situation.

The states CC_UPDT and CC_INVAL do not need to test anymore if
there is a pending request to CC_SEND.


Merging tsar_generic_xbar from branches/v5 to trunk [447-467]

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r447 | cfuguet | 2013-07-18 16:12:05 +0200 (Thu, 18 Jul 2013) | 8 lines

Adding tsar_generic_xbar platform in branches/v5/platforms:

  • This platform contains a third local crossbar interconnect for the CLACK network.
  • It works only in a monocluster topology

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r448 | cfuguet | 2013-07-18 17:51:18 +0200 (Thu, 18 Jul 2013) | 9 lines

Modification in branches/v5/platforms/tsar_generic_xbar:

  • Adding a DSPIN router to the platform to allow the inter-cluster communication for the CLACK commands.

With this modification, the tsar_generic_xbar platform can be used
for multi-cluster simulations

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r466 | cfuguet | 2013-07-23 17:01:49 +0200 (Tue, 23 Jul 2013) | 9 lines

Modifications in branches/v5 vci_mem_cache:

  • Replacing the third router CLACK by a third virtual channel in the new virtual_dspin_router supporting several virtual channels.

The third channel has been added in the COMMAND router.

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r467 | cfuguet | 2013-07-23 17:23:13 +0200 (Tue, 23 Jul 2013) | 5 lines

Modifications in branches/v5 tsar_generic_xbar:

  • Adding preprocessor conditional statements for ALMOS support


Merging dspin_dhccp_param from branches/v5 to trunk [377-467]

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r442 | cfuguet | 2013-07-17 12:13:51 +0200 (Wed, 17 Jul 2013) | 13 lines

Modifications in branches/v5/communication/dspin_dhccp_param:

  • Renaming FROM_MC fields in M2P
  • Renaming FROM_L1 fields in P2M
  • Renaming CLEANUP_ACK fields in CLACK
File size: 2.6 KB
Line 
1
2# -*- python -*-
3
4__id__ = "$Id: vci_mem_cache.sd 295 2013-02-14 15:05:05Z cfuguet $"
5__version__ = "$Revision: 295 $"
6
7Module('caba:vci_mem_cache',
8        classname = 'soclib::caba::VciMemCache',
9
10        tmpl_parameters = [
11            parameter.Module('vci_param_int', default = 'caba:vci_param',
12                cell_size = parameter.Reference('memc_cell_size_int')
13            ),
14            parameter.Module('vci_param_ext', default = 'caba:vci_param',
15                cell_size = parameter.Reference('memc_cell_size_ext')
16            ),
17            parameter.Int('dspin_in_width'),
18            parameter.Int('dspin_out_width'),
19        ],
20
21        header_files = [
22            '../source/include/vci_mem_cache.h',
23            '../source/include/xram_transaction.h',
24            '../source/include/mem_cache_directory.h',
25            '../source/include/update_tab.h'
26        ],
27
28        interface_files = [
29            '../../include/soclib/mem_cache.h', 
30        ],
31
32        implementation_files = [
33            '../source/src/vci_mem_cache.cpp'
34        ],
35
36        uses = [
37            Uses('caba:base_module'),
38            Uses('common:loader'),
39            Uses('common:mapping_table'),
40            Uses('caba:generic_fifo'),
41            Uses('caba:generic_llsc_global_table'),
42            Uses('caba:dspin_dhccp_param')
43        ],
44
45        ports = [
46            Port('caba:clock_in'     , 'p_clk'      , auto = 'clock' ),
47            Port('caba:bit_in'       , 'p_resetn'   , auto = 'resetn'),
48            Port('caba:vci_target'   , 'p_vci_tgt'),
49            Port('caba:vci_initiator', 'p_vci_ixr'),
50            Port('caba:dspin_input',
51                'p_dspin_p2m',
52                dspin_data_size = parameter.Reference('dspin_in_width')
53            ),
54            Port('caba:dspin_output',
55                'p_dspin_m2p',
56                dspin_data_size = parameter.Reference('dspin_out_width')
57            ),
58            Port('caba:dspin_output',
59                'p_dspin_clack',
60                dspin_data_size = parameter.Reference('dspin_out_width')
61            ),
62        ],
63
64        instance_parameters = [
65            parameter.Module('mtp', 'common:mapping_table'),
66            parameter.Module('mtc', 'common:mapping_table'),
67            parameter.Module('mtx', 'common:mapping_table'),
68            parameter.IntTab('vci_ixr_index'),
69            parameter.IntTab('vci_ini_index'),
70            parameter.IntTab('vci_tgt_index'),
71            parameter.IntTab('vci_tgt_index_cleanup'),
72            parameter.Int   ('nways'),
73            parameter.Int   ('nsets'),
74            parameter.Int   ('nwords'),
75            parameter.Int   ('heap_size'),
76        ],
77)
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