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source: branches/RWT/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h @ 611

Last change on this file since 611 was 611, checked in by almaless, 10 years ago

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/branches/ODCCP/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h	merged	eligible
/trunk/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h	merged	eligible
/branches/v5/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h	441-467

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1	/* -- c++ --
2	* File : vci_mem_cache.h
3	* Date : 26/10/2008
4	* Copyright : UPMC / LIP6
5	* Authors : Alain Greiner / Eric Guthmuller
6	*
7	* SOCLIB_LGPL_HEADER_BEGIN
8	*
9	* This file is part of SoCLib, GNU LGPLv2.1.
10	*
11	* SoCLib is free software; you can redistribute it and/or modify it
12	* under the terms of the GNU Lesser General Public License as published
13	* by the Free Software Foundation; version 2.1 of the License.
14	*
15	* SoCLib is distributed in the hope that it will be useful, but
16	* WITHOUT ANY WARRANTY; without even the implied warranty of
17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18	* Lesser General Public License for more details.
19	*
20	* You should have received a copy of the GNU Lesser General Public
21	* License along with SoCLib; if not, write to the Free Software
22	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
23	* 02110-1301 USA
24	*
25	* SOCLIB_LGPL_HEADER_END
26	*
27	* Maintainers: alain.greiner@lip6.fr
28	* eric.guthmuller@polytechnique.edu
29	* cesar.fuguet-tortolero@lip6.fr
30	* alexandre.joannou@lip6.fr
31	*/
32
33	#ifndef SOCLIB_CABA_MEM_CACHE_H
34	#define SOCLIB_CABA_MEM_CACHE_H
35
36	#include <inttypes.h>
37	#include <systemc>
38	#include <list>
39	#include <cassert>
40	#include "arithmetics.h"
41	#include "alloc_elems.h"
42	#include "caba_base_module.h"
43	#include "vci_target.h"
44	#include "vci_initiator.h"
45	#include "generic_fifo.h"
46	#include "mapping_table.h"
47	#include "int_tab.h"
48	#include "generic_llsc_global_table.h"
49	#include "mem_cache_directory.h"
50	#include "xram_transaction.h"
51	#include "update_tab.h"
52	#include "dspin_interface.h"
53	#include "dspin_dhccp_param.h"
54
55	#define TRT_ENTRIES 4 // Number of entries in TRT
56	#define UPT_ENTRIES 4 // Number of entries in UPT
57	#define IVT_ENTRIES 4 // Number of entries in IVT
58	#define HEAP_ENTRIES 1024 // Number of entries in HEAP
59
60	namespace soclib { namespace caba {
61
62	using namespace sc_core;
63
64	template<typename vci_param_int,
65	typename vci_param_ext,
66	size_t dspin_in_width,
67	size_t dspin_out_width>
68	class VciMemCache
69	: public soclib::caba::BaseModule
70	{
71	typedef typename vci_param_int::fast_addr_t addr_t;
72	typedef typename sc_dt::sc_uint<64> wide_data_t;
73	typedef uint32_t data_t;
74	typedef uint32_t tag_t;
75	typedef uint32_t be_t;
76	typedef uint32_t copy_t;
77
78	/* States of the TGT_CMD fsm */
79	enum tgt_cmd_fsm_state_e
80	{
81	TGT_CMD_IDLE,
82	TGT_CMD_READ,
83	TGT_CMD_WRITE,
84	TGT_CMD_CAS,
85	TGT_CMD_ERROR,
86	TGT_CMD_CONFIG
87	};
88
89	/* States of the TGT_RSP fsm */
90	enum tgt_rsp_fsm_state_e
91	{
92	TGT_RSP_READ_IDLE,
93	TGT_RSP_WRITE_IDLE,
94	TGT_RSP_CAS_IDLE,
95	TGT_RSP_XRAM_IDLE,
96	TGT_RSP_MULTI_ACK_IDLE,
97	TGT_RSP_CLEANUP_IDLE,
98	TGT_RSP_CONFIG_IDLE,
99	TGT_RSP_TGT_CMD_IDLE,
100	TGT_RSP_READ,
101	TGT_RSP_WRITE,
102	TGT_RSP_CAS,
103	TGT_RSP_XRAM,
104	TGT_RSP_MULTI_ACK,
105	TGT_RSP_CLEANUP,
106	TGT_RSP_CONFIG,
107	TGT_RSP_TGT_CMD
108	};
109
110	/* States of the DSPIN_TGT fsm */
111	enum cc_receive_fsm_state_e
112	{
113	CC_RECEIVE_IDLE,
114	CC_RECEIVE_CLEANUP,
115	CC_RECEIVE_CLEANUP_EOP,
116	CC_RECEIVE_MULTI_ACK
117	};
118
119	/* States of the CC_SEND fsm */
120	enum cc_send_fsm_state_e
121	{
122	CC_SEND_XRAM_RSP_IDLE,
123	CC_SEND_WRITE_IDLE,
124	CC_SEND_CAS_IDLE,
125	CC_SEND_CONFIG_IDLE,
126	CC_SEND_XRAM_RSP_BRDCAST_HEADER,
127	CC_SEND_XRAM_RSP_BRDCAST_NLINE,
128	CC_SEND_XRAM_RSP_INVAL_HEADER,
129	CC_SEND_XRAM_RSP_INVAL_NLINE,
130	CC_SEND_READ_NCC_INVAL_HEADER,
131	CC_SEND_READ_NCC_INVAL_NLINE,
132	CC_SEND_WRITE_NCC_INVAL_HEADER,
133	CC_SEND_WRITE_NCC_INVAL_NLINE,
134	CC_SEND_WRITE_BRDCAST_HEADER,
135	CC_SEND_WRITE_BRDCAST_NLINE,
136	CC_SEND_WRITE_UPDT_HEADER,
137	CC_SEND_WRITE_UPDT_NLINE,
138	CC_SEND_WRITE_UPDT_DATA,
139	CC_SEND_CAS_BRDCAST_HEADER,
140	CC_SEND_CAS_BRDCAST_NLINE,
141	CC_SEND_CAS_UPDT_HEADER,
142	CC_SEND_CAS_UPDT_NLINE,
143	CC_SEND_CAS_UPDT_DATA,
144	CC_SEND_CAS_UPDT_DATA_HIGH,
145	CC_SEND_CONFIG_INVAL_HEADER,
146	CC_SEND_CONFIG_INVAL_NLINE,
147	CC_SEND_CONFIG_BRDCAST_HEADER,
148	CC_SEND_CONFIG_BRDCAST_NLINE
149	};
150
151	/* States of the MULTI_ACK fsm */
152	enum multi_ack_fsm_state_e
153	{
154	MULTI_ACK_IDLE,
155	MULTI_ACK_UPT_LOCK,
156	MULTI_ACK_UPT_CLEAR,
157	MULTI_ACK_WRITE_RSP
158	};
159
160	/* States of the CONFIG fsm */
161	enum config_fsm_state_e
162	{
163	CONFIG_IDLE,
164	CONFIG_LOOP,
165	CONFIG_WAIT,
166	CONFIG_RSP,
167	CONFIG_DIR_REQ,
168	CONFIG_DIR_ACCESS,
169	CONFIG_IVT_LOCK,
170	CONFIG_BC_SEND,
171	CONFIG_INVAL_SEND,
172	CONFIG_HEAP_REQ,
173	CONFIG_HEAP_SCAN,
174	CONFIG_HEAP_LAST,
175	CONFIG_TRT_LOCK,
176	CONFIG_TRT_SET,
177	CONFIG_PUT_REQ
178	};
179
180	/* States of the READ fsm */
181	enum read_fsm_state_e
182	{
183	READ_IDLE,
184	READ_DIR_REQ,
185	READ_DIR_LOCK,
186	READ_IVT_LOCK,
187	READ_WAIT,
188	READ_DIR_HIT,
189	READ_HEAP_REQ,
190	READ_HEAP_LOCK,
191	READ_HEAP_WRITE,
192	READ_HEAP_ERASE,
193	READ_HEAP_LAST,
194	READ_RSP,
195	READ_TRT_LOCK,
196	READ_TRT_SET,
197	READ_TRT_REQ
198	};
199
200	/* States of the WRITE fsm */
201	enum write_fsm_state_e
202	{
203	WRITE_IDLE,
204	WRITE_NEXT,
205	WRITE_DIR_REQ,
206	WRITE_DIR_LOCK,
207	WRITE_IVT_LOCK_HIT_WB,
208	WRITE_DIR_HIT,
209	WRITE_UPT_LOCK,
210	WRITE_UPT_HEAP_LOCK,
211	WRITE_UPT_REQ,
212	WRITE_UPT_NEXT,
213	WRITE_UPT_DEC,
214	WRITE_RSP,
215	WRITE_MISS_IVT_LOCK,
216	WRITE_MISS_TRT_LOCK,
217	WRITE_MISS_TRT_DATA,
218	WRITE_MISS_TRT_SET,
219	WRITE_MISS_XRAM_REQ,
220	WRITE_BC_DIR_READ,
221	WRITE_BC_TRT_LOCK,
222	WRITE_BC_IVT_LOCK,
223	WRITE_BC_DIR_INVAL,
224	WRITE_BC_CC_SEND,
225	WRITE_BC_XRAM_REQ,
226	WRITE_WAIT
227	};
228
229	/* States of the IXR_RSP fsm */
230	enum ixr_rsp_fsm_state_e
231	{
232	IXR_RSP_IDLE,
233	IXR_RSP_ACK,
234	IXR_RSP_TRT_ERASE,
235	IXR_RSP_TRT_READ
236	};
237
238	/* States of the XRAM_RSP fsm */
239	enum xram_rsp_fsm_state_e
240	{
241	XRAM_RSP_IDLE,
242	XRAM_RSP_TRT_COPY,
243	XRAM_RSP_TRT_DIRTY,
244	XRAM_RSP_DIR_LOCK,
245	XRAM_RSP_DIR_UPDT,
246	XRAM_RSP_DIR_RSP,
247	XRAM_RSP_IVT_LOCK,
248	XRAM_RSP_INVAL_WAIT,
249	XRAM_RSP_INVAL,
250	XRAM_RSP_WRITE_DIRTY,
251	XRAM_RSP_HEAP_REQ,
252	XRAM_RSP_HEAP_ERASE,
253	XRAM_RSP_HEAP_LAST,
254	XRAM_RSP_ERROR_ERASE,
255	XRAM_RSP_ERROR_RSP
256	};
257
258	/* States of the IXR_CMD fsm */
259	enum ixr_cmd_fsm_state_e
260	{
261	IXR_CMD_READ_IDLE,
262	IXR_CMD_WRITE_IDLE,
263	IXR_CMD_CAS_IDLE,
264	IXR_CMD_XRAM_IDLE,
265	IXR_CMD_CLEANUP_IDLE,
266	IXR_CMD_CONFIG_IDLE,
267	IXR_CMD_READ_TRT,
268	IXR_CMD_WRITE_TRT,
269	IXR_CMD_CAS_TRT,
270	IXR_CMD_XRAM_TRT,
271	IXR_CMD_CLEANUP_TRT,
272	IXR_CMD_CONFIG_TRT,
273	IXR_CMD_READ_SEND,
274	IXR_CMD_WRITE_SEND,
275	IXR_CMD_CAS_SEND,
276	IXR_CMD_XRAM_SEND,
277	IXR_CMD_CLEANUP_DATA_SEND,
278	IXR_CMD_CONFIG_SEND
279	};
280
281	/* States of the CAS fsm */
282	enum cas_fsm_state_e
283	{
284	CAS_IDLE,
285	CAS_DIR_REQ,
286	CAS_DIR_LOCK,
287	CAS_DIR_HIT_READ,
288	CAS_DIR_HIT_COMPARE,
289	CAS_DIR_HIT_WRITE,
290	CAS_UPT_LOCK,
291	CAS_UPT_HEAP_LOCK,
292	CAS_UPT_REQ,
293	CAS_UPT_NEXT,
294	CAS_BC_TRT_LOCK,
295	CAS_BC_IVT_LOCK,
296	CAS_BC_DIR_INVAL,
297	CAS_BC_CC_SEND,
298	CAS_BC_XRAM_REQ,
299	CAS_RSP_FAIL,
300	CAS_RSP_SUCCESS,
301	CAS_MISS_TRT_LOCK,
302	CAS_MISS_TRT_SET,
303	CAS_MISS_XRAM_REQ,
304	CAS_WAIT
305	};
306
307	/* States of the CLEANUP fsm */
308	enum cleanup_fsm_state_e
309	{
310	CLEANUP_IDLE,
311	CLEANUP_GET_NLINE,
312	CLEANUP_GET_DATA,
313	CLEANUP_DIR_REQ,
314	CLEANUP_DIR_LOCK,
315	CLEANUP_DIR_WRITE,
316	CLEANUP_IVT_LOCK_DATA,
317	CLEANUP_IVT_CLEAR_DATA,
318	CLEANUP_READ_RSP,
319	CLEANUP_HEAP_REQ,
320	CLEANUP_HEAP_LOCK,
321	CLEANUP_HEAP_SEARCH,
322	CLEANUP_HEAP_CLEAN,
323	CLEANUP_HEAP_FREE,
324	CLEANUP_IVT_LOCK,
325	CLEANUP_IVT_DECREMENT,
326	CLEANUP_IVT_CLEAR,
327	CLEANUP_WRITE_RSP,
328	CLEANUP_IXR_REQ,
329	CLEANUP_WAIT,
330	CLEANUP_SEND_CLACK
331	};
332
333	/* States of the ALLOC_DIR fsm */
334	enum alloc_dir_fsm_state_e
335	{
336	ALLOC_DIR_RESET,
337	ALLOC_DIR_READ,
338	ALLOC_DIR_WRITE,
339	ALLOC_DIR_CAS,
340	ALLOC_DIR_CLEANUP,
341	ALLOC_DIR_XRAM_RSP,
342	ALLOC_DIR_CONFIG
343	};
344
345	/* States of the ALLOC_TRT fsm */
346	enum alloc_trt_fsm_state_e
347	{
348	ALLOC_TRT_READ,
349	ALLOC_TRT_WRITE,
350	ALLOC_TRT_CAS,
351	ALLOC_TRT_XRAM_RSP,
352	ALLOC_TRT_IXR_RSP,
353	ALLOC_TRT_CLEANUP,
354	ALLOC_TRT_IXR_CMD,
355	ALLOC_TRT_CONFIG
356	};
357
358	/* States of the ALLOC_UPT fsm */
359	enum alloc_upt_fsm_state_e
360	{
361	ALLOC_UPT_WRITE,
362	ALLOC_UPT_CAS,
363	ALLOC_UPT_MULTI_ACK
364	};
365
366	/* States of the ALLOC_IVT fsm */
367	enum alloc_ivt_fsm_state_e
368	{
369	ALLOC_IVT_WRITE,
370	ALLOC_IVT_READ,
371	ALLOC_IVT_XRAM_RSP,
372	ALLOC_IVT_CLEANUP,
373	ALLOC_IVT_CAS,
374	ALLOC_IVT_CONFIG
375	};
376
377	/* States of the ALLOC_HEAP fsm */
378	enum alloc_heap_fsm_state_e
379	{
380	ALLOC_HEAP_RESET,
381	ALLOC_HEAP_READ,
382	ALLOC_HEAP_WRITE,
383	ALLOC_HEAP_CAS,
384	ALLOC_HEAP_CLEANUP,
385	ALLOC_HEAP_XRAM_RSP,
386	ALLOC_HEAP_CONFIG
387	};
388
389	/* transaction type, pktid field */
390	enum transaction_type_e
391	{
392	// b3 unused
393	// b2 READ / NOT READ
394	// Si READ
395	// b1 DATA / INS
396	// b0 UNC / MISS
397	// Si NOT READ
398	// b1 accÃšs table llsc type SW / other
399	// b2 WRITE/CAS/LL/SC
400	TYPE_READ_DATA_UNC = 0x0,
401	TYPE_READ_DATA_MISS = 0x1,
402	TYPE_READ_INS_UNC = 0x2,
403	TYPE_READ_INS_MISS = 0x3,
404	TYPE_WRITE = 0x4,
405	TYPE_CAS = 0x5,
406	TYPE_LL = 0x6,
407	TYPE_SC = 0x7
408	};
409
410	/* SC return values */
411	enum sc_status_type_e
412	{
413	SC_SUCCESS = 0x00000000,
414	SC_FAIL = 0x00000001
415	};
416
417	// debug variables
418	bool m_debug;
419	bool m_debug_previous_valid;
420	size_t m_debug_previous_count;
421	bool m_debug_previous_dirty;
422	data_t * m_debug_previous_data;
423	data_t * m_debug_data;
424
425	// instrumentation counters
426	uint32_t m_cpt_cycles; // Counter of cycles
427
428	// Counters accessible in software (not yet but eventually)
429	uint32_t m_cpt_read_local; // Number of local READ transactions
430	uint32_t m_cpt_read_remote; // number of remote READ transactions
431	uint32_t m_cpt_read_cost; // Number of (flits * distance) for READs
432
433	uint32_t m_cpt_write_local; // Number of local WRITE transactions
434	uint32_t m_cpt_write_remote; // number of remote WRITE transactions
435	uint32_t m_cpt_write_flits_local; // number of flits for local WRITEs
436	uint32_t m_cpt_write_flits_remote; // number of flits for remote WRITEs
437	uint32_t m_cpt_write_cost; // Number of (flits * distance) for WRITEs
438
439	uint32_t m_cpt_ll_local; // Number of local LL transactions
440	uint32_t m_cpt_ll_remote; // number of remote LL transactions
441	uint32_t m_cpt_ll_cost; // Number of (flits * distance) for LLs
442
443	uint32_t m_cpt_sc_local; // Number of local SC transactions
444	uint32_t m_cpt_sc_remote; // number of remote SC transactions
445	uint32_t m_cpt_sc_cost; // Number of (flits * distance) for SCs
446
447	uint32_t m_cpt_cas_local; // Number of local SC transactions
448	uint32_t m_cpt_cas_remote; // number of remote SC transactions
449	uint32_t m_cpt_cas_cost; // Number of (flits * distance) for SCs
450
451	uint32_t m_cpt_update; // Number of requests causing an UPDATE
452	uint32_t m_cpt_update_local; // Number of local UPDATE transactions
453	uint32_t m_cpt_update_remote; // Number of remote UPDATE transactions
454	uint32_t m_cpt_update_cost; // Number of (flits * distance) for UPDT
455
456	uint32_t m_cpt_minval; // Number of requests causing M_INV
457	uint32_t m_cpt_minval_local; // Number of local M_INV transactions
458	uint32_t m_cpt_minval_remote; // Number of remote M_INV transactions
459	uint32_t m_cpt_minval_cost; // Number of (flits * distance) for M_INV
460
461	uint32_t m_cpt_binval; // Number of BROADCAST INVAL
462
463	uint32_t m_cpt_cleanup_local; // Number of local CLEANUP transactions
464	uint32_t m_cpt_cleanup_remote; // Number of remote CLEANUP transactions
465	uint32_t m_cpt_cleanup_cost; // Number of (flits * distance) for CLEANUPs
466
467	// Counters not accessible by software
468	uint32_t m_cpt_read_miss; // Number of MISS READ
469	uint32_t m_cpt_write_miss; // Number of MISS WRITE
470	uint32_t m_cpt_write_dirty; // Cumulated length for WRITE transactions
471	uint32_t m_cpt_write_broadcast;// Number of BROADCAST INVAL because write
472
473	uint32_t m_cpt_trt_rb; // Read blocked by a hit in trt
474	uint32_t m_cpt_trt_full; // Transaction blocked due to a full trt
475
476	uint32_t m_cpt_read_fsm_dir_lock; // wait DIR LOCK
477	uint32_t m_cpt_read_fsm_n_dir_lock; // NB DIR LOCK
478	uint32_t m_cpt_write_fsm_dir_lock; // wait DIR LOCK
479	uint32_t m_cpt_write_fsm_n_dir_lock; // NB DIR LOCK
480	uint32_t m_cpt_xram_rsp_fsm_dir_lock; // wait DIR LOCK
481	uint32_t m_cpt_xram_rsp_fsm_n_dir_lock; // NB DIR LOCK
482	uint32_t m_cpt_cas_fsm_dir_lock; // wait DIR LOCK
483	uint32_t m_cpt_cas_fsm_n_dir_lock; // NB DIR LOCK
484	uint32_t m_cpt_cleanup_fsm_dir_lock; // wait DIR LOCK
485	uint32_t m_cpt_cleanup_fsm_n_dir_lock; // NB DIR LOCK
486
487	uint32_t m_cpt_dir_unused; // NB cycles DIR LOCK unused
488	uint32_t m_cpt_read_fsm_dir_used; // NB cycles DIR LOCK used
489	uint32_t m_cpt_write_fsm_dir_used; // NB cycles DIR LOCK used
490	uint32_t m_cpt_cas_fsm_dir_used; // NB cycles DIR LOCK used
491	uint32_t m_cpt_xram_rsp_fsm_dir_used; // NB cycles DIR LOCK used
492	uint32_t m_cpt_cleanup_fsm_dir_used; // NB cycles DIR LOCK used
493
494	uint32_t m_cpt_read_fsm_trt_lock; // wait TRT LOCK
495	uint32_t m_cpt_write_fsm_trt_lock; // wait TRT LOCK
496	uint32_t m_cpt_cas_fsm_trt_lock; // wait TRT LOCK
497	uint32_t m_cpt_xram_rsp_fsm_trt_lock; // wait TRT LOCK
498	uint32_t m_cpt_ixr_fsm_trt_lock; // wait TRT LOCK
499
500	uint32_t m_cpt_read_fsm_n_trt_lock; // NB TRT LOCK
501	uint32_t m_cpt_write_fsm_n_trt_lock; // NB TRT LOCK
502	uint32_t m_cpt_cas_fsm_n_trt_lock; // NB TRT LOCK
503	uint32_t m_cpt_xram_rsp_fsm_n_trt_lock; // NB TRT LOCK
504	uint32_t m_cpt_ixr_fsm_n_trt_lock; // NB TRT LOCK
505
506	uint32_t m_cpt_read_fsm_trt_used; // NB cycles TRT LOCK used
507	uint32_t m_cpt_write_fsm_trt_used; // NB cycles TRT LOCK used
508	uint32_t m_cpt_cas_fsm_trt_used; // NB cycles TRT LOCK used
509	uint32_t m_cpt_xram_rsp_fsm_trt_used; // NB cycles TRT LOCK used
510	uint32_t m_cpt_ixr_fsm_trt_used; // NB cycles TRT LOCK used
511
512	uint32_t m_cpt_trt_unused; // NB cycles TRT LOCK unused
513
514	uint32_t m_cpt_write_fsm_upt_lock; // wait UPT LOCK
515	uint32_t m_cpt_xram_rsp_fsm_upt_lock; // wait UPT LOCK
516	uint32_t m_cpt_multi_ack_fsm_upt_lock; // wait UPT LOCK
517	uint32_t m_cpt_cleanup_fsm_ivt_lock; // wait UPT LOCK
518	uint32_t m_cpt_cas_fsm_upt_lock; // wait UPT LOCK
519
520	uint32_t m_cpt_write_fsm_n_upt_lock; // NB UPT LOCK
521	uint32_t m_cpt_xram_rsp_fsm_n_upt_lock; // NB UPT LOCK
522	uint32_t m_cpt_multi_ack_fsm_n_upt_lock; // NB UPT LOCK
523	uint32_t m_cpt_cleanup_fsm_n_upt_lock; // NB UPT LOCK
524	uint32_t m_cpt_cas_fsm_n_upt_lock; // NB UPT LOCK
525
526	uint32_t m_cpt_write_fsm_upt_used; // NB cycles UPT LOCK used
527	uint32_t m_cpt_xram_rsp_fsm_upt_used; // NB cycles UPT LOCK used
528	uint32_t m_cpt_multi_ack_fsm_upt_used; // NB cycles UPT LOCK used
529	uint32_t m_cpt_cleanup_fsm_ivt_used; // NB cycles UPT LOCK used
530	uint32_t m_cpt_cas_fsm_upt_used; // NB cycles UPT LOCK used
531
532	uint32_t m_cpt_ivt_unused; // NB cycles UPT LOCK unused
533	uint32_t m_cpt_upt_unused; // NB cycles UPT LOCK unused
534
535	uint32_t m_cpt_read_fsm_heap_lock; // wait HEAP LOCK
536	uint32_t m_cpt_write_fsm_heap_lock; // wait HEAP LOCK
537	uint32_t m_cpt_cas_fsm_heap_lock; // wait HEAP LOCK
538	uint32_t m_cpt_cleanup_fsm_heap_lock; // wait HEAP LOCK
539	uint32_t m_cpt_xram_rsp_fsm_heap_lock; // wait HEAP LOCK
540
541	uint32_t m_cpt_read_fsm_n_heap_lock; // NB HEAP LOCK
542	uint32_t m_cpt_write_fsm_n_heap_lock; // NB HEAP LOCK
543	uint32_t m_cpt_cas_fsm_n_heap_lock; // NB HEAP LOCK
544	uint32_t m_cpt_cleanup_fsm_n_heap_lock; // NB HEAP LOCK
545	uint32_t m_cpt_xram_rsp_fsm_n_heap_lock; // NB HEAP LOCK
546
547	uint32_t m_cpt_read_fsm_heap_used; // NB cycles HEAP LOCK used
548	uint32_t m_cpt_write_fsm_heap_used; // NB cycles HEAP LOCK used
549	uint32_t m_cpt_cas_fsm_heap_used; // NB cycles HEAP LOCK used
550	uint32_t m_cpt_cleanup_fsm_heap_used; // NB cycles HEAP LOCK used
551	uint32_t m_cpt_xram_rsp_fsm_heap_used; // NB cycles HEAP LOCK used
552
553	uint32_t m_cpt_heap_unused; // NB cycles HEAP LOCK unused
554
555	//RWT
556	uint32_t m_cpt_cleanup_data;
557	uint32_t m_cpt_ncc_to_cc_read; // NB change from NCC to CC caused by a READ
558	uint32_t m_cpt_ncc_to_cc_write; // NB change from NCC to CC caused by a WRITE
559	uint32_t m_cpt_ncc_to_cc; // NB change from NCC to CC
560
561	uint32_t m_cpt_read_data_unc;
562	uint32_t m_cpt_read_data_miss_CC;
563	uint32_t m_cpt_read_ins_unc;
564	uint32_t m_cpt_read_ins_miss;
565	uint32_t m_cpt_read_ll_CC;
566	uint32_t m_cpt_read_data_miss_NCC;
567	uint32_t m_cpt_read_ll_NCC;
568	uint32_t m_cpt_read_WTF;
569
570	uint32_t m_cpt_update_flits; // Number of flits for UPDATEs
571	uint32_t m_cpt_inval_cost; // Number of (flits * distance) for INVALs
572
573	uint32_t m_cpt_get;
574	uint32_t m_cpt_put;
575
576	size_t m_prev_count;
577
578	protected:
579
580	SC_HAS_PROCESS(VciMemCache);
581
582	public:
583	sc_in<bool> p_clk;
584	sc_in<bool> p_resetn;
585	sc_in<bool> p_irq;
586	soclib::caba::VciTarget<vci_param_int> p_vci_tgt;
587	soclib::caba::VciInitiator<vci_param_ext> p_vci_ixr;
588	soclib::caba::DspinInput<dspin_in_width> p_dspin_p2m;
589	soclib::caba::DspinOutput<dspin_out_width> p_dspin_m2p;
590	soclib::caba::DspinOutput<dspin_out_width> p_dspin_clack;
591
592	#if MONITOR_MEMCACHE_FSM == 1
593	sc_out<int> p_read_fsm;
594	sc_out<int> p_write_fsm;
595	sc_out<int> p_xram_rsp_fsm;
596	sc_out<int> p_cas_fsm;
597	sc_out<int> p_cleanup_fsm;
598	sc_out<int> p_config_fsm;
599	sc_out<int> p_alloc_heap_fsm;
600	sc_out<int> p_alloc_dir_fsm;
601	sc_out<int> p_alloc_trt_fsm;
602	sc_out<int> p_alloc_upt_fsm;
603	sc_out<int> p_alloc_ivt_fsm;
604	sc_out<int> p_tgt_cmd_fsm;
605	sc_out<int> p_tgt_rsp_fsm;
606	sc_out<int> p_ixr_cmd_fsm;
607	sc_out<int> p_ixr_rsp_fsm;
608	sc_out<int> p_cc_send_fsm;
609	sc_out<int> p_cc_receive_fsm;
610	sc_out<int> p_multi_ack_fsm;
611	#endif
612
613	VciMemCache(
614	sc_module_name name, // Instance Name
615	const soclib::common::MappingTable &mtp, // Mapping table INT network
616	const soclib::common::MappingTable &mtx, // Mapping table RAM network
617	const soclib::common::IntTab &srcid_x, // global index RAM network
618	const soclib::common::IntTab &tgtid_d, // global index INT network
619	const size_t cc_global_id, // global index CC network
620	const size_t x_width, // X width in platform
621	const size_t y_width, // Y width in platform
622	const size_t nways, // Number of ways per set
623	const size_t nsets, // Number of sets
624	const size_t nwords, // Number of words per line
625	const size_t max_copies, // max number of copies
626	const size_t heap_size=HEAP_ENTRIES,
627	const size_t trt_lines=TRT_ENTRIES,
628	const size_t upt_lines=UPT_ENTRIES,
629	const size_t ivt_lines=IVT_ENTRIES,
630	const size_t debug_start_cycle=0,
631	const bool debug_ok=false );
632
633	~VciMemCache();
634
635	void print_stats(bool activity_counters, bool stats);
636	void print_trace( size_t detailled = 0 );
637	void cache_monitor(addr_t addr);
638	void start_monitor(addr_t addr, addr_t length);
639	void stop_monitor();
640
641	private:
642
643	void transition();
644	void genMoore();
645	void check_monitor(addr_t addr, data_t data, bool read);
646	uint32_t req_distance(uint32_t req_srcid);
647	bool is_local_req(uint32_t req_srcid);
648	int read_instrumentation(uint32_t regr, uint32_t & rdata);
649
650	// Component attributes
651	std::list<soclib::common::Segment> m_seglist; // segments allocated
652	size_t m_nseg; // number of segments
653	soclib::common::Segment **m_seg; // array of segments pointers
654	size_t m_seg_config; // config segment index
655	const size_t m_srcid_x; // global index on RAM network
656	const size_t m_initiators; // Number of initiators
657	const size_t m_heap_size; // Size of the heap
658	const size_t m_ways; // Number of ways in a set
659	const size_t m_sets; // Number of cache sets
660	const size_t m_words; // Number of words in a line
661	const size_t m_cc_global_id; // global_index on cc network
662	const size_t m_xwidth; // number of x bits in platform
663	const size_t m_ywidth; // number of y bits in platform
664	size_t m_debug_start_cycle;
665	bool m_debug_ok;
666	uint32_t m_trt_lines;
667	TransactionTab m_trt; // xram transaction table
668	uint32_t m_upt_lines;
669	UpdateTab m_upt; // pending update
670	UpdateTab m_ivt; // pending invalidate
671	CacheDirectory m_cache_directory; // data cache directory
672	CacheData m_cache_data; // data array[set][way][word]
673	HeapDirectory m_heap; // heap for copies
674	size_t m_max_copies; // max number of copies in heap
675	GenericLLSCGlobalTable
676	< 32 , // number of slots
677	4096, // number of processors in the system
678	8000, // registration life (# of LL operations)
679	addr_t > m_llsc_table; // ll/sc registration table
680
681	// adress masks
682	const soclib::common::AddressMaskingTable<addr_t> m_x;
683	const soclib::common::AddressMaskingTable<addr_t> m_y;
684	const soclib::common::AddressMaskingTable<addr_t> m_z;
685	const soclib::common::AddressMaskingTable<addr_t> m_nline;
686
687	// broadcast address
688	uint32_t m_broadcast_boundaries;
689
690	// configuration interface constants
691	const uint32_t m_config_addr_mask;
692	const uint32_t m_config_regr_width;
693	const uint32_t m_config_func_width;
694	const uint32_t m_config_regr_idx_mask;
695	const uint32_t m_config_func_idx_mask;
696
697	// Fifo between TGT_CMD fsm and READ fsm
698	GenericFifo<addr_t> m_cmd_read_addr_fifo;
699	GenericFifo<size_t> m_cmd_read_length_fifo;
700	GenericFifo<size_t> m_cmd_read_srcid_fifo;
701	GenericFifo<size_t> m_cmd_read_trdid_fifo;
702	GenericFifo<size_t> m_cmd_read_pktid_fifo;
703
704	// Fifo between TGT_CMD fsm and WRITE fsm
705	GenericFifo<addr_t> m_cmd_write_addr_fifo;
706	GenericFifo<bool> m_cmd_write_eop_fifo;
707	GenericFifo<size_t> m_cmd_write_srcid_fifo;
708	GenericFifo<size_t> m_cmd_write_trdid_fifo;
709	GenericFifo<size_t> m_cmd_write_pktid_fifo;
710	GenericFifo<data_t> m_cmd_write_data_fifo;
711	GenericFifo<be_t> m_cmd_write_be_fifo;
712
713	// Fifo between TGT_CMD fsm and CAS fsm
714	GenericFifo<addr_t> m_cmd_cas_addr_fifo;
715	GenericFifo<bool> m_cmd_cas_eop_fifo;
716	GenericFifo<size_t> m_cmd_cas_srcid_fifo;
717	GenericFifo<size_t> m_cmd_cas_trdid_fifo;
718	GenericFifo<size_t> m_cmd_cas_pktid_fifo;
719	GenericFifo<data_t> m_cmd_cas_wdata_fifo;
720
721	// Fifo between CC_RECEIVE fsm and CLEANUP fsm
722	GenericFifo<uint64_t> m_cc_receive_to_cleanup_fifo;
723
724	// Fifo between CC_RECEIVE fsm and MULTI_ACK fsm
725	GenericFifo<uint64_t> m_cc_receive_to_multi_ack_fifo;
726
727	// Buffer between TGT_CMD fsm and TGT_RSP fsm
728	// (segmentation violation response request)
729	sc_signal<bool> r_tgt_cmd_to_tgt_rsp_req;
730
731	sc_signal<uint32_t> r_tgt_cmd_to_tgt_rsp_rdata;
732	sc_signal<size_t> r_tgt_cmd_to_tgt_rsp_error;
733	sc_signal<size_t> r_tgt_cmd_to_tgt_rsp_srcid;
734	sc_signal<size_t> r_tgt_cmd_to_tgt_rsp_trdid;
735	sc_signal<size_t> r_tgt_cmd_to_tgt_rsp_pktid;
736
737	sc_signal<addr_t> r_tgt_cmd_config_addr;
738	sc_signal<size_t> r_tgt_cmd_config_cmd;
739
740	//////////////////////////////////////////////////
741	// Registers controlled by the TGT_CMD fsm
742	//////////////////////////////////////////////////
743
744	sc_signal<int> r_tgt_cmd_fsm;
745
746	///////////////////////////////////////////////////////
747	// Registers controlled by the CONFIG fsm
748	///////////////////////////////////////////////////////
749
750	sc_signal<int> r_config_fsm; // FSM state
751	sc_signal<bool> r_config_lock; // lock protecting exclusive access
752	sc_signal<int> r_config_cmd; // config request type
753	sc_signal<addr_t> r_config_address; // target buffer physical address
754	sc_signal<size_t> r_config_srcid; // config request srcid
755	sc_signal<size_t> r_config_trdid; // config request trdid
756	sc_signal<size_t> r_config_pktid; // config request pktid
757	sc_signal<size_t> r_config_cmd_lines; // number of lines to be handled
758	sc_signal<size_t> r_config_rsp_lines; // number of lines not completed
759	sc_signal<size_t> r_config_dir_way; // DIR: selected way
760	sc_signal<bool> r_config_dir_lock; // DIR: locked entry
761	sc_signal<size_t> r_config_dir_count; // DIR: number of copies
762	sc_signal<bool> r_config_dir_is_cnt; // DIR: counter mode (broadcast)
763	sc_signal<size_t> r_config_dir_copy_srcid; // DIR: first copy SRCID
764	sc_signal<bool> r_config_dir_copy_inst; // DIR: first copy L1 type
765	sc_signal<size_t> r_config_dir_ptr; // DIR: index of next copy in HEAP
766	sc_signal<size_t> r_config_heap_next; // current pointer to scan HEAP
767	sc_signal<size_t> r_config_trt_index; // selected entry in TRT
768	sc_signal<size_t> r_config_ivt_index; // selected entry in IVT
769
770	// Buffer between CONFIG fsm and IXR_CMD fsm
771	sc_signal<bool> r_config_to_ixr_cmd_req; // valid request
772	sc_signal<size_t> r_config_to_ixr_cmd_index; // TRT index
773
774	// Buffer between CONFIG fsm and TGT_RSP fsm (send a done response to L1 cache)
775	sc_signal<bool> r_config_to_tgt_rsp_req; // valid request
776	sc_signal<bool> r_config_to_tgt_rsp_error; // error response
777	sc_signal<size_t> r_config_to_tgt_rsp_srcid; // Transaction srcid
778	sc_signal<size_t> r_config_to_tgt_rsp_trdid; // Transaction trdid
779	sc_signal<size_t> r_config_to_tgt_rsp_pktid; // Transaction pktid
780
781	// Buffer between CONFIG fsm and CC_SEND fsm (multi-inval / broadcast-inval)
782	sc_signal<bool> r_config_to_cc_send_multi_req; // multi-inval request
783	sc_signal<bool> r_config_to_cc_send_brdcast_req; // broadcast-inval request
784	sc_signal<addr_t> r_config_to_cc_send_nline; // line index
785	sc_signal<size_t> r_config_to_cc_send_trdid; // UPT index
786	GenericFifo<bool> m_config_to_cc_send_inst_fifo; // fifo for the L1 type
787	GenericFifo<size_t> m_config_to_cc_send_srcid_fifo; // fifo for owners srcid
788
789	///////////////////////////////////////////////////////
790	// Registers controlled by the READ fsm
791	///////////////////////////////////////////////////////
792
793	sc_signal<int> r_read_fsm; // FSM state
794	sc_signal<size_t> r_read_copy; // Srcid of the first copy
795	sc_signal<size_t> r_read_copy_cache; // Srcid of the first copy
796	sc_signal<bool> r_read_copy_inst; // Type of the first copy
797	sc_signal<tag_t> r_read_tag; // cache line tag (in directory)
798	sc_signal<bool> r_read_is_cnt; // is_cnt bit (in directory)
799	sc_signal<bool> r_read_lock; // lock bit (in directory)
800	sc_signal<bool> r_read_dirty; // dirty bit (in directory)
801	sc_signal<size_t> r_read_count; // number of copies
802	sc_signal<size_t> r_read_ptr; // pointer to the heap
803	sc_signal<data_t> * r_read_data; // data (one cache line)
804	sc_signal<size_t> r_read_way; // associative way (in cache)
805	sc_signal<size_t> r_read_trt_index; // Transaction Table index
806	sc_signal<size_t> r_read_next_ptr; // Next entry to point to
807	sc_signal<bool> r_read_last_free; // Last free entry
808	sc_signal<addr_t> r_read_ll_key; // LL key from llsc_global_table
809
810	// Buffer between READ fsm and IXR_CMD fsm
811	sc_signal<bool> r_read_to_ixr_cmd_req; // valid request
812	sc_signal<size_t> r_read_to_ixr_cmd_index; // TRT index
813
814	// Buffer between READ fsm and TGT_RSP fsm (send a hit read response to L1 cache)
815	sc_signal<bool> r_read_to_tgt_rsp_req; // valid request
816	sc_signal<size_t> r_read_to_tgt_rsp_srcid; // Transaction srcid
817	sc_signal<size_t> r_read_to_tgt_rsp_trdid; // Transaction trdid
818	sc_signal<size_t> r_read_to_tgt_rsp_pktid; // Transaction pktid
819	sc_signal<data_t> * r_read_to_tgt_rsp_data; // data (one cache line)
820	sc_signal<size_t> r_read_to_tgt_rsp_word; // first word of the response
821	sc_signal<size_t> r_read_to_tgt_rsp_length; // length of the response
822	sc_signal<addr_t> r_read_to_tgt_rsp_ll_key; // LL key from llsc_global_table
823
824	//RWT: Buffer between READ fsm and CC_SEND fsm (send inval)
825	sc_signal<bool> r_read_to_cc_send_req;
826	sc_signal<size_t> r_read_to_cc_send_dest;
827	sc_signal<addr_t> r_read_to_cc_send_nline;
828	sc_signal<bool> r_read_to_cc_send_inst;
829
830	//RWT: Buffer between READ fsm and CLEANUP fsm (wait for the data coming from L1 cache)
831	sc_signal<bool> r_read_to_cleanup_req; // valid request
832	sc_signal<addr_t> r_read_to_cleanup_nline; // cache line index
833	sc_signal<size_t> r_read_to_cleanup_srcid;
834	sc_signal<size_t> r_read_to_cleanup_length;
835	sc_signal<size_t> r_read_to_cleanup_first_word;
836	sc_signal<bool> r_read_to_cleanup_cached_read;
837	sc_signal<bool> r_read_to_cleanup_is_ll;
838	sc_signal<addr_t> r_read_to_cleanup_addr;
839	sc_signal<addr_t> r_read_to_cleanup_ll_key;
840
841	//RWT:
842	sc_signal<bool> r_read_coherent; // State of the cache slot after transaction
843	sc_signal<bool> r_read_ll_done;
844
845	///////////////////////////////////////////////////////////////
846	// Registers controlled by the WRITE fsm
847	///////////////////////////////////////////////////////////////
848
849	sc_signal<int> r_write_fsm; // FSM state
850	sc_signal<addr_t> r_write_address; // first word address
851	sc_signal<size_t> r_write_word_index; // first word index in line
852	sc_signal<size_t> r_write_word_count; // number of words in line
853	sc_signal<size_t> r_write_srcid; // transaction srcid
854	sc_signal<size_t> r_write_trdid; // transaction trdid
855	sc_signal<size_t> r_write_pktid; // transaction pktid
856	sc_signal<data_t> * r_write_data; // data (one cache line)
857	sc_signal<be_t> * r_write_be; // one byte enable per word
858	sc_signal<bool> r_write_byte; // (BE != 0X0) and (BE != 0xF)
859	sc_signal<bool> r_write_is_cnt; // is_cnt bit (in directory)
860	sc_signal<bool> r_write_lock; // lock bit (in directory)
861	sc_signal<tag_t> r_write_tag; // cache line tag (in directory)
862	sc_signal<size_t> r_write_copy; // first owner of the line
863	sc_signal<size_t> r_write_copy_cache; // first owner of the line
864	sc_signal<bool> r_write_copy_inst; // is this owner a ICache ?
865	sc_signal<size_t> r_write_count; // number of copies
866	sc_signal<size_t> r_write_ptr; // pointer to the heap
867	sc_signal<size_t> r_write_next_ptr; // next pointer to the heap
868	sc_signal<bool> r_write_to_dec; // need to decrement update counter
869	sc_signal<size_t> r_write_way; // way of the line
870	sc_signal<size_t> r_write_trt_index; // index in Transaction Table
871	sc_signal<size_t> r_write_upt_index; // index in Update Table
872	sc_signal<bool> r_write_sc_fail; // sc command failed
873	sc_signal<data_t> r_write_sc_key; // sc command key
874	sc_signal<bool> r_write_bc_data_we; // Write enable for data buffer
875
876	// Buffer between WRITE fsm and TGT_RSP fsm (acknowledge a write command from L1)
877	sc_signal<bool> r_write_to_tgt_rsp_req; // valid request
878	sc_signal<size_t> r_write_to_tgt_rsp_srcid; // transaction srcid
879	sc_signal<size_t> r_write_to_tgt_rsp_trdid; // transaction trdid
880	sc_signal<size_t> r_write_to_tgt_rsp_pktid; // transaction pktid
881	sc_signal<bool> r_write_to_tgt_rsp_sc_fail; // sc command failed
882
883	// Buffer between WRITE fsm and IXR_CMD fsm
884	sc_signal<bool> r_write_to_ixr_cmd_req; // valid request
885	sc_signal<size_t> r_write_to_ixr_cmd_index; // TRT index
886
887	// Buffer between WRITE fsm and CC_SEND fsm (Update/Invalidate L1 caches)
888	sc_signal<bool> r_write_to_cc_send_multi_req; // valid multicast request
889	sc_signal<bool> r_write_to_cc_send_brdcast_req; // valid brdcast request
890	sc_signal<addr_t> r_write_to_cc_send_nline; // cache line index
891	sc_signal<size_t> r_write_to_cc_send_trdid; // index in Update Table
892	sc_signal<data_t> * r_write_to_cc_send_data; // data (one cache line)
893	sc_signal<be_t> * r_write_to_cc_send_be; // word enable
894	sc_signal<size_t> r_write_to_cc_send_count; // number of words in line
895	sc_signal<size_t> r_write_to_cc_send_index; // index of first word in line
896	GenericFifo<bool> m_write_to_cc_send_inst_fifo; // fifo for the L1 type
897	GenericFifo<size_t> m_write_to_cc_send_srcid_fifo; // fifo for srcids
898
899	// Buffer between WRITE fsm and MULTI_ACK fsm (Decrement UPT entry)
900	sc_signal<bool> r_write_to_multi_ack_req; // valid request
901	sc_signal<size_t> r_write_to_multi_ack_upt_index; // index in update table
902
903	// RWT: Buffer between WRITE fsm and CLEANUP fsm (change slot state)
904	sc_signal<bool> r_write_to_cleanup_req; // valid request
905	sc_signal<addr_t> r_write_to_cleanup_nline; // cache line index
906
907	// RWT
908	sc_signal<bool> r_write_coherent; // cache slot state after transaction
909
910	//Buffer between WRITE fsm and CC_SEND fsm (INVAL for RWT)
911	sc_signal<bool> r_write_to_cc_send_req;
912	sc_signal<size_t> r_write_to_cc_send_dest;
913
914
915	/////////////////////////////////////////////////////////
916	// Registers controlled by MULTI_ACK fsm
917	//////////////////////////////////////////////////////////
918
919	sc_signal<int> r_multi_ack_fsm; // FSM state
920	sc_signal<size_t> r_multi_ack_upt_index; // index in the Update Table
921	sc_signal<size_t> r_multi_ack_srcid; // pending write srcid
922	sc_signal<size_t> r_multi_ack_trdid; // pending write trdid
923	sc_signal<size_t> r_multi_ack_pktid; // pending write pktid
924	sc_signal<addr_t> r_multi_ack_nline; // pending write nline
925
926	// Buffer between MULTI_ACK fsm and TGT_RSP fsm (complete write/update transaction)
927	sc_signal<bool> r_multi_ack_to_tgt_rsp_req; // valid request
928	sc_signal<size_t> r_multi_ack_to_tgt_rsp_srcid; // Transaction srcid
929	sc_signal<size_t> r_multi_ack_to_tgt_rsp_trdid; // Transaction trdid
930	sc_signal<size_t> r_multi_ack_to_tgt_rsp_pktid; // Transaction pktid
931
932	///////////////////////////////////////////////////////
933	// Registers controlled by CLEANUP fsm
934	///////////////////////////////////////////////////////
935
936	sc_signal<int> r_cleanup_fsm; // FSM state
937	sc_signal<size_t> r_cleanup_srcid; // transaction srcid
938	sc_signal<bool> r_cleanup_inst; // Instruction or Data ?
939	sc_signal<size_t> r_cleanup_way_index; // L1 Cache Way index
940	sc_signal<addr_t> r_cleanup_nline; // cache line index
941
942
943	sc_signal<copy_t> r_cleanup_copy; // first copy
944	sc_signal<copy_t> r_cleanup_copy_cache; // first copy
945	sc_signal<size_t> r_cleanup_copy_inst; // type of the first copy
946	sc_signal<copy_t> r_cleanup_count; // number of copies
947	sc_signal<size_t> r_cleanup_ptr; // pointer to the heap
948	sc_signal<size_t> r_cleanup_prev_ptr; // previous pointer to the heap
949	sc_signal<size_t> r_cleanup_prev_srcid; // srcid of previous heap entry
950	sc_signal<size_t> r_cleanup_prev_cache_id; // srcid of previous heap entry
951	sc_signal<bool> r_cleanup_prev_inst; // inst bit of previous heap entry
952	sc_signal<size_t> r_cleanup_next_ptr; // next pointer to the heap
953	sc_signal<tag_t> r_cleanup_tag; // cache line tag (in directory)
954	sc_signal<bool> r_cleanup_is_cnt; // inst bit (in directory)
955	sc_signal<bool> r_cleanup_lock; // lock bit (in directory)
956	sc_signal<bool> r_cleanup_dirty; // dirty bit (in directory)
957	sc_signal<size_t> r_cleanup_way; // associative way (in cache)
958
959	sc_signal<size_t> r_cleanup_write_srcid; // srcid of write rsp
960	sc_signal<size_t> r_cleanup_write_trdid; // trdid of write rsp
961	sc_signal<size_t> r_cleanup_write_pktid; // pktid of write rsp
962
963	sc_signal<bool> r_cleanup_need_rsp; // write response required
964	sc_signal<bool> r_cleanup_need_ack; // config acknowledge required
965
966	sc_signal<size_t> r_cleanup_index; // index of the INVAL line (in the UPT)
967
968	// Buffer between CLEANUP fsm and TGT_RSP fsm (acknowledge a write command from L1)
969	sc_signal<bool> r_cleanup_to_tgt_rsp_req; // valid request
970	sc_signal<size_t> r_cleanup_to_tgt_rsp_srcid; // transaction srcid
971	sc_signal<size_t> r_cleanup_to_tgt_rsp_trdid; // transaction trdid
972	sc_signal<size_t> r_cleanup_to_tgt_rsp_pktid; // transaction pktid
973	sc_signal<addr_t> r_cleanup_to_tgt_rsp_ll_key;
974
975	//RWT
976	sc_signal<size_t> r_cleanup_read_srcid;
977	sc_signal<size_t> r_cleanup_read_trdid;
978	sc_signal<size_t> r_cleanup_read_pktid;
979	sc_signal<bool> r_cleanup_read_need_rsp;
980	sc_signal<bool> r_cleanup_to_tgt_rsp_type;
981	sc_signal<data_t> * r_cleanup_to_tgt_rsp_data;
982	sc_signal<size_t> r_cleanup_to_tgt_rsp_length;
983	sc_signal<size_t> r_cleanup_to_tgt_rsp_first_word;
984
985	///////////////////////////////////////////////////////
986	// Registers controlled by CAS fsm
987	///////////////////////////////////////////////////////
988
989	sc_signal<int> r_cas_fsm; // FSM state
990	sc_signal<data_t> r_cas_wdata; // write data word
991	sc_signal<data_t> * r_cas_rdata; // read data word
992	sc_signal<uint32_t> r_cas_lfsr; // lfsr for random introducing
993	sc_signal<size_t> r_cas_cpt; // size of command
994	sc_signal<copy_t> r_cas_copy; // Srcid of the first copy
995	sc_signal<copy_t> r_cas_copy_cache; // Srcid of the first copy
996	sc_signal<bool> r_cas_copy_inst; // Type of the first copy
997	sc_signal<size_t> r_cas_count; // number of copies
998	sc_signal<size_t> r_cas_ptr; // pointer to the heap
999	sc_signal<size_t> r_cas_next_ptr; // next pointer to the heap
1000	sc_signal<bool> r_cas_is_cnt; // is_cnt bit (in directory)
1001	sc_signal<bool> r_cas_dirty; // dirty bit (in directory)
1002	sc_signal<size_t> r_cas_way; // way in directory
1003	sc_signal<size_t> r_cas_set; // set in directory
1004	sc_signal<data_t> r_cas_tag; // cache line tag (in directory)
1005	sc_signal<size_t> r_cas_trt_index; // Transaction Table index
1006	sc_signal<size_t> r_cas_upt_index; // Update Table index
1007	sc_signal<data_t> * r_cas_data; // cache line data
1008
1009	sc_signal<bool> r_cas_coherent;
1010
1011	// Buffer between CAS fsm and IXR_CMD fsm (XRAM write)
1012	sc_signal<bool> r_cas_to_ixr_cmd_req; // valid request
1013	sc_signal<size_t> r_cas_to_ixr_cmd_index; // TRT index
1014
1015	// Buffer between CAS fsm and TGT_RSP fsm
1016	sc_signal<bool> r_cas_to_tgt_rsp_req; // valid request
1017	sc_signal<data_t> r_cas_to_tgt_rsp_data; // read data word
1018	sc_signal<size_t> r_cas_to_tgt_rsp_srcid; // Transaction srcid
1019	sc_signal<size_t> r_cas_to_tgt_rsp_trdid; // Transaction trdid
1020	sc_signal<size_t> r_cas_to_tgt_rsp_pktid; // Transaction pktid
1021
1022	// Buffer between CAS fsm and CC_SEND fsm (Update/Invalidate L1 caches)
1023	sc_signal<bool> r_cas_to_cc_send_multi_req; // valid request
1024	sc_signal<bool> r_cas_to_cc_send_brdcast_req; // brdcast request
1025	sc_signal<addr_t> r_cas_to_cc_send_nline; // cache line index
1026	sc_signal<size_t> r_cas_to_cc_send_trdid; // index in Update Table
1027	sc_signal<data_t> r_cas_to_cc_send_wdata; // data (one word)
1028	sc_signal<bool> r_cas_to_cc_send_is_long; // it is a 64 bits CAS
1029	sc_signal<data_t> r_cas_to_cc_send_wdata_high; // data high (one word)
1030	sc_signal<size_t> r_cas_to_cc_send_index; // index of the word in line
1031	GenericFifo<bool> m_cas_to_cc_send_inst_fifo; // fifo for the L1 type
1032	GenericFifo<size_t> m_cas_to_cc_send_srcid_fifo; // fifo for srcids
1033
1034	////////////////////////////////////////////////////
1035	// Registers controlled by the IXR_RSP fsm
1036	////////////////////////////////////////////////////
1037
1038	sc_signal<int> r_ixr_rsp_fsm; // FSM state
1039	sc_signal<size_t> r_ixr_rsp_trt_index; // TRT entry index
1040	sc_signal<size_t> r_ixr_rsp_cpt; // word counter
1041
1042	// Buffer between IXR_RSP fsm and CONFIG fsm (response from the XRAM)
1043	sc_signal<bool> r_ixr_rsp_to_config_ack; // one single bit
1044
1045	// Buffer between IXR_RSP fsm and XRAM_RSP fsm (response from the XRAM)
1046	sc_signal<bool> * r_ixr_rsp_to_xram_rsp_rok; // one bit per TRT entry
1047
1048	////////////////////////////////////////////////////
1049	// Registers controlled by the XRAM_RSP fsm
1050	////////////////////////////////////////////////////
1051
1052	sc_signal<int> r_xram_rsp_fsm; // FSM state
1053	sc_signal<size_t> r_xram_rsp_trt_index; // TRT entry index
1054	TransactionTabEntry r_xram_rsp_trt_buf; // TRT entry local buffer
1055	sc_signal<bool> r_xram_rsp_victim_inval; // victim line invalidate
1056	sc_signal<bool> r_xram_rsp_victim_is_cnt; // victim line inst bit
1057	sc_signal<bool> r_xram_rsp_victim_dirty; // victim line dirty bit
1058	sc_signal<size_t> r_xram_rsp_victim_way; // victim line way
1059	sc_signal<size_t> r_xram_rsp_victim_set; // victim line set
1060	sc_signal<addr_t> r_xram_rsp_victim_nline; // victim line index
1061	sc_signal<copy_t> r_xram_rsp_victim_copy; // victim line first copy
1062	sc_signal<copy_t> r_xram_rsp_victim_copy_cache; // victim line first copy
1063	sc_signal<bool> r_xram_rsp_victim_copy_inst; // victim line type of first copy
1064	sc_signal<size_t> r_xram_rsp_victim_count; // victim line number of copies
1065	sc_signal<size_t> r_xram_rsp_victim_ptr; // victim line pointer to the heap
1066	sc_signal<data_t> * r_xram_rsp_victim_data; // victim line data
1067	sc_signal<size_t> r_xram_rsp_ivt_index; // IVT entry index
1068	sc_signal<size_t> r_xram_rsp_next_ptr; // Next pointer to the heap
1069
1070	// Buffer between XRAM_RSP fsm and TGT_RSP fsm (response to L1 cache)
1071	sc_signal<bool> r_xram_rsp_to_tgt_rsp_req; // Valid request
1072	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_srcid; // Transaction srcid
1073	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_trdid; // Transaction trdid
1074	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_pktid; // Transaction pktid
1075	sc_signal<data_t> * r_xram_rsp_to_tgt_rsp_data; // data (one cache line)
1076	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_word; // first word index
1077	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_length; // length of the response
1078	sc_signal<bool> r_xram_rsp_to_tgt_rsp_rerror; // send error to requester
1079	sc_signal<addr_t> r_xram_rsp_to_tgt_rsp_ll_key; // LL key from llsc_global_table
1080
1081	// Buffer between XRAM_RSP fsm and CC_SEND fsm (Inval L1 Caches)
1082	sc_signal<bool> r_xram_rsp_to_cc_send_multi_req; // Valid request
1083	sc_signal<bool> r_xram_rsp_to_cc_send_brdcast_req; // Broadcast request
1084	sc_signal<addr_t> r_xram_rsp_to_cc_send_nline; // cache line index;
1085	sc_signal<size_t> r_xram_rsp_to_cc_send_trdid; // index of UPT entry
1086	GenericFifo<bool> m_xram_rsp_to_cc_send_inst_fifo; // fifo for the L1 type
1087	GenericFifo<size_t> m_xram_rsp_to_cc_send_srcid_fifo; // fifo for srcids
1088
1089	// Buffer between XRAM_RSP fsm and IXR_CMD fsm
1090	sc_signal<bool> r_xram_rsp_to_ixr_cmd_req; // Valid request
1091	sc_signal<size_t> r_xram_rsp_to_ixr_cmd_index; // TRT index
1092
1093	//RWT
1094	sc_signal<bool> r_xram_rsp_victim_coherent; // victim's cache slot state
1095	sc_signal<bool> r_xram_rsp_coherent; // coherence of the read
1096	////////////////////////////////////////////////////
1097	// Registers controlled by the IXR_CMD fsm
1098	////////////////////////////////////////////////////
1099
1100	sc_signal<int> r_ixr_cmd_fsm;
1101	sc_signal<size_t> r_ixr_cmd_word; // word index for a put
1102	sc_signal<size_t> r_ixr_cmd_trdid; // TRT index value
1103	sc_signal<addr_t> r_ixr_cmd_address; // address to XRAM
1104	sc_signal<data_t> * r_ixr_cmd_wdata; // cache line buffer
1105	sc_signal<bool> r_ixr_cmd_get; // transaction type (PUT/GET)
1106
1107	////////////////////////////////////////////////////
1108	// Registers controlled by TGT_RSP fsm
1109	////////////////////////////////////////////////////
1110
1111	sc_signal<int> r_tgt_rsp_fsm;
1112	sc_signal<size_t> r_tgt_rsp_cpt;
1113	sc_signal<bool> r_tgt_rsp_key_sent;
1114
1115	////////////////////////////////////////////////////
1116	// Registers controlled by CC_SEND fsm
1117	////////////////////////////////////////////////////
1118
1119	sc_signal<int> r_cc_send_fsm;
1120	sc_signal<size_t> r_cc_send_cpt;
1121	sc_signal<bool> r_cc_send_inst;
1122
1123	////////////////////////////////////////////////////
1124	// Registers controlled by CC_RECEIVE fsm
1125	////////////////////////////////////////////////////
1126
1127	sc_signal<int> r_cc_receive_fsm;
1128
1129	////////////////////////////////////////////////////
1130	// Registers controlled by ALLOC_DIR fsm
1131	////////////////////////////////////////////////////
1132
1133	sc_signal<int> r_alloc_dir_fsm;
1134	sc_signal<unsigned> r_alloc_dir_reset_cpt;
1135
1136	////////////////////////////////////////////////////
1137	// Registers controlled by ALLOC_TRT fsm
1138	////////////////////////////////////////////////////
1139
1140	sc_signal<int> r_alloc_trt_fsm;
1141
1142	////////////////////////////////////////////////////
1143	// Registers controlled by ALLOC_UPT fsm
1144	////////////////////////////////////////////////////
1145
1146	sc_signal<int> r_alloc_upt_fsm;
1147
1148	////////////////////////////////////////////////////
1149	// Registers controlled by ALLOC_IVT fsm
1150	////////////////////////////////////////////////////
1151
1152	sc_signal<int> r_alloc_ivt_fsm;
1153
1154	////////////////////////////////////////////////////
1155	// Registers controlled by ALLOC_HEAP fsm
1156	////////////////////////////////////////////////////
1157
1158	sc_signal<int> r_alloc_heap_fsm;
1159	sc_signal<unsigned> r_alloc_heap_reset_cpt;
1160
1161
1162	////////////////////////////////////////////////////
1163	// REGISTERS FOR ODCCP
1164	////////////////////////////////////////////////////
1165
1166	sc_signal<uint32_t> r_cleanup_data_index;
1167	sc_signal<uint32_t> r_cleanup_trdid;
1168	sc_signal<uint32_t> r_cleanup_pktid;
1169	sc_signal<bool> r_cleanup_coherent;
1170	sc_signal<data_t> *r_cleanup_data;
1171	sc_signal<data_t> *r_cleanup_old_data;
1172	sc_signal<bool> r_cleanup_contains_data;
1173
1174	sc_signal<bool> r_cleanup_ncc;
1175	sc_signal<bool> r_cleanup_to_ixr_cmd_ncc_l1_dirty;
1176	sc_signal<bool> r_xram_rsp_to_ixr_cmd_inval_ncc_pending;
1177
1178	sc_signal<bool> r_cleanup_to_ixr_cmd_req;
1179	sc_signal<data_t> *r_cleanup_to_ixr_cmd_data;
1180	sc_signal<uint32_t> r_cleanup_to_ixr_cmd_srcid;
1181	sc_signal<uint32_t> r_cleanup_to_ixr_cmd_index;
1182	sc_signal<uint32_t> r_cleanup_to_ixr_cmd_pktid;
1183	sc_signal<addr_t> r_cleanup_to_ixr_cmd_nline;
1184	}; // end class VciMemCache
1185
1186	}}
1187
1188	#endif
1189
1190	// Local Variables:
1191	// tab-width: 2
1192	// c-basic-offset: 2
1193	// c-file-offsets:((innamespace . 0)(inline-open . 0))
1194	// indent-tabs-mode: nil
1195	// End:
1196
1197	// vim: filetype=cpp:expandtab:shiftwidth=2:tabstop=2:softtabstop=2
1198

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