source: branches/fault_tolerance/platform/tsar_generic_iob/tsar_iob_cluster/caba/source/include/tsar_iob_cluster.h @ 648

Last change on this file since 648 was 648, checked in by cfuguet, 9 years ago

Introducing new platform with IO bridges in fault_tolerance
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1//////////////////////////////////////////////////////////////////////////////
2// File: tsar_iob_cluster.h
3// Author: Alain Greiner
4// Copyright: UPMC/LIP6
5// Date : april 2013
6// This program is released under the GNU public license
7//////////////////////////////////////////////////////////////////////////////
8
9#ifndef SOCLIB_CABA_TSAR_IOB_CLUSTER_H
10#define SOCLIB_CABA_TSAR_IOB_CLUSTER_H
11
12#include <systemc>
13#include <sys/time.h>
14#include <iostream>
15#include <sstream>
16#include <cstdlib>
17#include <cstdarg>
18
19#include "gdbserver.h"
20#include "mapping_table.h"
21#include "mips32.h"
22#include "vci_simple_ram.h"
23#include "vci_xicu.h"
24#include "dspin_local_crossbar.h"
25#include "vci_dspin_initiator_wrapper.h"
26#include "vci_dspin_target_wrapper.h"
27#include "dspin_router_tsar.h"
28#include "virtual_dspin_router.h"
29#include "vci_multi_dma.h"
30#include "vci_mem_cache.h"
31#include "vci_cc_vcache_wrapper.h"
32#include "vci_io_bridge.h"
33
34namespace soclib { namespace caba {
35
36///////////////////////////////////////////////////////////////////////////
37template<typename vci_param_int,
38         typename vci_param_ext,
39         size_t   dspin_int_cmd_width,
40         size_t   dspin_int_rsp_width,
41         size_t   dspin_ram_cmd_width,
42         size_t   dspin_ram_rsp_width>
43class TsarIobCluster
44///////////////////////////////////////////////////////////////////////////
45    : public soclib::caba::BaseModule
46{
47
48   public:
49
50      // Ports
51      sc_in<bool>   p_clk;
52      sc_in<bool>   p_resetn;
53
54      // Thes two ports are used to connect IOB to IOX nework in top cell
55      soclib::caba::VciInitiator<vci_param_ext>* p_vci_iob_iox_ini;
56      soclib::caba::VciTarget<vci_param_ext>*    p_vci_iob_iox_tgt;
57
58      // These ports are used to connect IOB to RAM network in top cell
59      soclib::caba::DspinOutput<dspin_ram_cmd_width>* p_dspin_iob_cmd_out;
60      soclib::caba::DspinInput<dspin_ram_rsp_width>*  p_dspin_iob_rsp_in;
61
62      // These ports are used to connect hard IRQ from external peripherals to
63      // IOB0
64      sc_in<bool>* p_irq[32];
65
66      // These arrays of ports are used to connect the INT & RAM networks in
67      // top cell
68      soclib::caba::DspinOutput<dspin_int_cmd_width>** p_dspin_int_cmd_out;
69      soclib::caba::DspinInput<dspin_int_cmd_width>**  p_dspin_int_cmd_in;
70      soclib::caba::DspinOutput<dspin_int_rsp_width>** p_dspin_int_rsp_out;
71      soclib::caba::DspinInput<dspin_int_rsp_width>**  p_dspin_int_rsp_in;
72
73      soclib::caba::DspinOutput<dspin_ram_cmd_width>* p_dspin_ram_cmd_out;
74      soclib::caba::DspinInput<dspin_ram_cmd_width>*  p_dspin_ram_cmd_in;
75      soclib::caba::DspinOutput<dspin_ram_rsp_width>* p_dspin_ram_rsp_out;
76      soclib::caba::DspinInput<dspin_ram_rsp_width>*  p_dspin_ram_rsp_in;
77
78      // interrupt signals
79      sc_signal<bool> signal_false;
80      sc_signal<bool> signal_proc_it[8];
81      sc_signal<bool> signal_irq_mdma[8];
82      sc_signal<bool> signal_irq_memc;
83
84      // INT network DSPIN signals between DSPIN routers and DSPIN
85      // local_crossbars
86      DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_l2g_d;
87      DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_g2l_d;
88      DspinSignals<dspin_int_cmd_width> signal_int_dspin_m2p_l2g_c;
89      DspinSignals<dspin_int_cmd_width> signal_int_dspin_m2p_g2l_c;
90      DspinSignals<dspin_int_cmd_width> signal_int_dspin_clack_l2g_c;
91      DspinSignals<dspin_int_cmd_width> signal_int_dspin_clack_g2l_c;
92      DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_l2g_d;
93      DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_g2l_d;
94      DspinSignals<dspin_int_rsp_width> signal_int_dspin_p2m_l2g_c;
95      DspinSignals<dspin_int_rsp_width> signal_int_dspin_p2m_g2l_c;
96
97      // INT network VCI signals between VCI components and VCI/DSPIN wrappers
98      VciSignals<vci_param_int> signal_int_vci_ini_proc[8];
99      VciSignals<vci_param_int> signal_int_vci_ini_mdma;
100      VciSignals<vci_param_int> signal_int_vci_ini_iobx;
101
102      VciSignals<vci_param_int> signal_int_vci_tgt_memc;
103      VciSignals<vci_param_int> signal_int_vci_tgt_xicu;
104      VciSignals<vci_param_int> signal_int_vci_tgt_mdma;
105      VciSignals<vci_param_int> signal_int_vci_tgt_iobx;
106
107      // INT network DSPIN signals between DSPIN local crossbars and VCI/DSPIN
108      // wrappers
109      DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_proc_i[8];
110      DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_proc_i[8];
111      DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_mdma_i;
112      DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_mdma_i;
113      DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_iobx_i;
114      DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_iobx_i;
115
116      DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_memc_t;
117      DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_memc_t;
118      DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_xicu_t;
119      DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_xicu_t;
120      DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_mdma_t;
121      DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_mdma_t;
122      DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_iobx_t;
123      DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_iobx_t;
124
125      // Coherence DSPIN signals between DSPIN local crossbars and CC
126      // components
127      DspinSignals<dspin_int_cmd_width> signal_int_dspin_m2p_memc;
128      DspinSignals<dspin_int_cmd_width> signal_int_dspin_clack_memc;
129      DspinSignals<dspin_int_rsp_width> signal_int_dspin_p2m_memc;
130      DspinSignals<dspin_int_cmd_width> signal_int_dspin_m2p_proc[8];
131      DspinSignals<dspin_int_cmd_width> signal_int_dspin_clack_proc[8];
132      DspinSignals<dspin_int_rsp_width> signal_int_dspin_p2m_proc[8];
133
134      // RAM network VCI signals between VCI components and VCI/DSPIN wrappers
135      VciSignals<vci_param_ext> signal_ram_vci_ini_memc;
136      VciSignals<vci_param_ext> signal_ram_vci_ini_iobx;
137      VciSignals<vci_param_ext> signal_ram_vci_tgt_xram;
138
139      // RAM network DSPIN signals between VCI/DSPIN wrappers and routers
140      DspinSignals<dspin_ram_cmd_width> signal_ram_dspin_cmd_xram_t;
141      DspinSignals<dspin_ram_rsp_width> signal_ram_dspin_rsp_xram_t;
142      DspinSignals<dspin_ram_cmd_width> signal_ram_dspin_cmd_memc_i;
143      DspinSignals<dspin_ram_rsp_width> signal_ram_dspin_rsp_memc_i;
144
145      //////////////////////////////////////
146      // Hardwate Components (pointers)
147      //////////////////////////////////////
148      typedef VciCcVCacheWrapper<vci_param_int, dspin_int_cmd_width,
149              dspin_int_rsp_width, GdbServer<Mips32ElIss> >
150              VciCcVCacheWrapperType;
151
152      typedef VciMemCache<vci_param_int, vci_param_ext, dspin_int_rsp_width,
153              dspin_int_cmd_width> VciMemCacheType;
154
155      typedef VciDspinInitiatorWrapper<vci_param_int, dspin_int_cmd_width,
156              dspin_int_rsp_width> VciIntDspinInitiatorWrapperType;
157
158      typedef VciDspinTargetWrapper<vci_param_int, dspin_int_cmd_width,
159              dspin_int_rsp_width> VciIntDspinTargetWrapperType;
160
161      typedef VciDspinInitiatorWrapper<vci_param_ext, dspin_ram_cmd_width,
162              dspin_ram_rsp_width> VciExtDspinInitiatorWrapperType;
163
164      typedef VciDspinTargetWrapper<vci_param_ext, dspin_ram_cmd_width,
165              dspin_ram_rsp_width> VciExtDspinTargetWrapperType;
166
167      VciCcVCacheWrapperType*          proc[8];
168      VciIntDspinInitiatorWrapperType* proc_wi[8];
169
170      VciMemCacheType*                 memc;
171      VciIntDspinTargetWrapperType*    memc_int_wt;
172      VciExtDspinInitiatorWrapperType* memc_ram_wi;
173
174      VciXicu<vci_param_int>*          xicu;
175      VciIntDspinTargetWrapperType*    xicu_int_wt;
176
177      VciMultiDma<vci_param_int>*      mdma;
178      VciIntDspinInitiatorWrapperType* mdma_int_wi;
179      VciIntDspinTargetWrapperType*    mdma_int_wt;
180
181      DspinLocalCrossbar<dspin_int_cmd_width>* int_xbar_cmd_d;
182      DspinLocalCrossbar<dspin_int_rsp_width>* int_xbar_rsp_d;
183      DspinLocalCrossbar<dspin_int_cmd_width>* int_xbar_m2p_c;
184      DspinLocalCrossbar<dspin_int_rsp_width>* int_xbar_p2m_c;
185      DspinLocalCrossbar<dspin_int_cmd_width>* int_xbar_clack_c;
186
187      VirtualDspinRouter<dspin_int_cmd_width>* int_router_cmd;
188      VirtualDspinRouter<dspin_int_rsp_width>* int_router_rsp;
189
190      VciSimpleRam<vci_param_ext>*  xram;
191      VciExtDspinTargetWrapperType* xram_ram_wt;
192
193      DspinRouterTsar<dspin_ram_cmd_width>* ram_router_cmd;
194      DspinRouterTsar<dspin_ram_rsp_width>* ram_router_rsp;
195
196      // IO Network Components (not instanciated in all clusters)
197
198      VciIoBridge<vci_param_int, vci_param_ext>* iob;
199      VciIntDspinInitiatorWrapperType*           iob_int_wi;
200      VciIntDspinTargetWrapperType*              iob_int_wt;
201      VciExtDspinInitiatorWrapperType*           iob_ram_wi;
202
203      size_t m_procs;
204
205      struct ClusterParams {
206         sc_module_name insname;
207
208         size_t nb_procs;
209         size_t nb_dmas;
210         size_t x_id;
211         size_t y_id;
212         size_t x_size;
213         size_t y_size;
214
215         const soclib::common::MappingTable &mt_int;
216         const soclib::common::MappingTable &mt_ext;
217         const soclib::common::MappingTable &mt_iox;
218
219         size_t x_width;
220         size_t y_width;
221         size_t l_width;
222
223         size_t int_memc_tgtid;
224         size_t int_xicu_tgtid;
225         size_t int_mdma_tgtid;
226         size_t int_iobx_tgtid;
227         size_t int_proc_srcid;
228         size_t int_mdma_srcid;
229         size_t int_iobx_srcid;
230         size_t ext_xram_tgtid;
231         size_t ext_memc_srcid;
232         size_t ext_iobx_srcid;
233
234         size_t memc_ways;
235         size_t memc_sets;
236         size_t l1_i_ways;
237         size_t l1_i_sets;
238         size_t l1_d_ways;
239         size_t l1_d_sets;
240         size_t xram_latency;
241
242         const Loader& loader;
243
244         uint32_t frozen_cycles;
245         uint32_t debug_start_cycle;
246         bool     memc_debug_ok;
247         bool     proc_debug_ok;
248         bool     iob_debug_ok;
249      };
250
251      // cluster constructor
252      TsarIobCluster(struct ClusterParams& params);
253      ~TsarIobCluster();
254};
255
256}}
257
258#endif
259
260// vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3
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