source: branches/fault_tolerance/platform/tsar_generic_iob/tsar_iob_cluster/caba/source/include/tsar_iob_cluster.h @ 658

Last change on this file since 658 was 658, checked in by cfuguet, 9 years ago

TSAR FAULT TOLERANCE BRANCH

  • Introducing replicated ROMs in cluster to contain the distributed boot procedure.
  • Erasing ROM in the IO network
File size: 10.3 KB
Line 
1//////////////////////////////////////////////////////////////////////////////
2// File: tsar_iob_cluster.h
3// Author: Alain Greiner
4// Copyright: UPMC/LIP6
5// Date : april 2013
6// This program is released under the GNU public license
7//////////////////////////////////////////////////////////////////////////////
8
9#ifndef SOCLIB_CABA_TSAR_IOB_CLUSTER_H
10#define SOCLIB_CABA_TSAR_IOB_CLUSTER_H
11
12#include <systemc>
13#include <sys/time.h>
14#include <iostream>
15#include <sstream>
16#include <cstdlib>
17#include <cstdarg>
18
19#include "gdbserver.h"
20#include "mapping_table.h"
21#include "mips32.h"
22#include "vci_simple_ram.h"
23#include "vci_simple_rom.h"
24#include "vci_xicu.h"
25#include "dspin_local_crossbar.h"
26#include "vci_dspin_initiator_wrapper.h"
27#include "vci_dspin_target_wrapper.h"
28#include "dspin_router_tsar.h"
29#include "virtual_dspin_router.h"
30#include "vci_multi_dma.h"
31#include "vci_mem_cache.h"
32#include "vci_cc_vcache_wrapper.h"
33#include "vci_io_bridge.h"
34
35namespace soclib { namespace caba {
36
37///////////////////////////////////////////////////////////////////////////
38template<typename vci_param_int,
39         typename vci_param_ext,
40         size_t   dspin_int_cmd_width,
41         size_t   dspin_int_rsp_width,
42         size_t   dspin_ram_cmd_width,
43         size_t   dspin_ram_rsp_width>
44class TsarIobCluster
45///////////////////////////////////////////////////////////////////////////
46    : public soclib::caba::BaseModule
47{
48
49   public:
50
51      // Ports
52      sc_in<bool>   p_clk;
53      sc_in<bool>   p_resetn;
54
55      // Thes two ports are used to connect IOB to IOX nework in top cell
56      soclib::caba::VciInitiator<vci_param_ext>* p_vci_iob_iox_ini;
57      soclib::caba::VciTarget<vci_param_ext>*    p_vci_iob_iox_tgt;
58
59      // These ports are used to connect IOB to RAM network in top cell
60      soclib::caba::DspinOutput<dspin_ram_cmd_width>* p_dspin_iob_cmd_out;
61      soclib::caba::DspinInput<dspin_ram_rsp_width>*  p_dspin_iob_rsp_in;
62
63      // These ports are used to connect hard IRQ from external peripherals to
64      // IOB0
65      sc_in<bool>* p_irq[32];
66
67      // These arrays of ports are used to connect the INT & RAM networks in
68      // top cell
69      soclib::caba::DspinOutput<dspin_int_cmd_width>** p_dspin_int_cmd_out;
70      soclib::caba::DspinInput<dspin_int_cmd_width>**  p_dspin_int_cmd_in;
71      soclib::caba::DspinOutput<dspin_int_rsp_width>** p_dspin_int_rsp_out;
72      soclib::caba::DspinInput<dspin_int_rsp_width>**  p_dspin_int_rsp_in;
73
74      soclib::caba::DspinOutput<dspin_ram_cmd_width>* p_dspin_ram_cmd_out;
75      soclib::caba::DspinInput<dspin_ram_cmd_width>*  p_dspin_ram_cmd_in;
76      soclib::caba::DspinOutput<dspin_ram_rsp_width>* p_dspin_ram_rsp_out;
77      soclib::caba::DspinInput<dspin_ram_rsp_width>*  p_dspin_ram_rsp_in;
78
79      // interrupt signals
80      sc_signal<bool> signal_false;
81      sc_signal<bool> signal_proc_it[8];
82      sc_signal<bool> signal_irq_mdma[8];
83      sc_signal<bool> signal_irq_memc;
84
85      // INT network DSPIN signals between DSPIN routers and DSPIN
86      // local_crossbars
87      DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_l2g_d;
88      DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_g2l_d;
89      DspinSignals<dspin_int_cmd_width> signal_int_dspin_m2p_l2g_c;
90      DspinSignals<dspin_int_cmd_width> signal_int_dspin_m2p_g2l_c;
91      DspinSignals<dspin_int_cmd_width> signal_int_dspin_clack_l2g_c;
92      DspinSignals<dspin_int_cmd_width> signal_int_dspin_clack_g2l_c;
93      DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_l2g_d;
94      DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_g2l_d;
95      DspinSignals<dspin_int_rsp_width> signal_int_dspin_p2m_l2g_c;
96      DspinSignals<dspin_int_rsp_width> signal_int_dspin_p2m_g2l_c;
97
98      // INT network VCI signals between VCI components and VCI/DSPIN wrappers
99      VciSignals<vci_param_int> signal_int_vci_ini_proc[8];
100      VciSignals<vci_param_int> signal_int_vci_ini_mdma;
101      VciSignals<vci_param_int> signal_int_vci_ini_iobx;
102
103      VciSignals<vci_param_int> signal_int_vci_tgt_memc;
104      VciSignals<vci_param_int> signal_int_vci_tgt_xicu;
105      VciSignals<vci_param_int> signal_int_vci_tgt_brom;
106      VciSignals<vci_param_int> signal_int_vci_tgt_mdma;
107      VciSignals<vci_param_int> signal_int_vci_tgt_iobx;
108
109      // INT network DSPIN signals between DSPIN local crossbars and VCI/DSPIN
110      // wrappers
111      DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_proc_i[8];
112      DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_proc_i[8];
113      DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_mdma_i;
114      DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_mdma_i;
115      DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_iobx_i;
116      DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_iobx_i;
117
118      DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_memc_t;
119      DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_memc_t;
120      DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_xicu_t;
121      DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_xicu_t;
122      DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_brom_t;
123      DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_brom_t;
124      DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_mdma_t;
125      DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_mdma_t;
126      DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_iobx_t;
127      DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_iobx_t;
128
129      // Coherence DSPIN signals between DSPIN local crossbars and CC
130      // components
131      DspinSignals<dspin_int_cmd_width> signal_int_dspin_m2p_memc;
132      DspinSignals<dspin_int_cmd_width> signal_int_dspin_clack_memc;
133      DspinSignals<dspin_int_rsp_width> signal_int_dspin_p2m_memc;
134      DspinSignals<dspin_int_cmd_width> signal_int_dspin_m2p_proc[8];
135      DspinSignals<dspin_int_cmd_width> signal_int_dspin_clack_proc[8];
136      DspinSignals<dspin_int_rsp_width> signal_int_dspin_p2m_proc[8];
137
138      // RAM network VCI signals between VCI components and VCI/DSPIN wrappers
139      VciSignals<vci_param_ext> signal_ram_vci_ini_memc;
140      VciSignals<vci_param_ext> signal_ram_vci_ini_iobx;
141      VciSignals<vci_param_ext> signal_ram_vci_tgt_xram;
142
143      // RAM network DSPIN signals between VCI/DSPIN wrappers and routers
144      DspinSignals<dspin_ram_cmd_width> signal_ram_dspin_cmd_xram_t;
145      DspinSignals<dspin_ram_rsp_width> signal_ram_dspin_rsp_xram_t;
146      DspinSignals<dspin_ram_cmd_width> signal_ram_dspin_cmd_memc_i;
147      DspinSignals<dspin_ram_rsp_width> signal_ram_dspin_rsp_memc_i;
148
149      //////////////////////////////////////
150      // Hardwate Components (pointers)
151      //////////////////////////////////////
152      typedef VciCcVCacheWrapper<vci_param_int, dspin_int_cmd_width,
153              dspin_int_rsp_width, GdbServer<Mips32ElIss> >
154              VciCcVCacheWrapperType;
155
156      typedef VciMemCache<vci_param_int, vci_param_ext, dspin_int_rsp_width,
157              dspin_int_cmd_width> VciMemCacheType;
158
159      typedef VciDspinInitiatorWrapper<vci_param_int, dspin_int_cmd_width,
160              dspin_int_rsp_width> VciIntDspinInitiatorWrapperType;
161
162      typedef VciDspinTargetWrapper<vci_param_int, dspin_int_cmd_width,
163              dspin_int_rsp_width> VciIntDspinTargetWrapperType;
164
165      typedef VciDspinInitiatorWrapper<vci_param_ext, dspin_ram_cmd_width,
166              dspin_ram_rsp_width> VciExtDspinInitiatorWrapperType;
167
168      typedef VciDspinTargetWrapper<vci_param_ext, dspin_ram_cmd_width,
169              dspin_ram_rsp_width> VciExtDspinTargetWrapperType;
170
171      VciCcVCacheWrapperType*          proc[8];
172      VciIntDspinInitiatorWrapperType* proc_wi[8];
173
174      VciMemCacheType*                 memc;
175      VciIntDspinTargetWrapperType*    memc_int_wt;
176      VciExtDspinInitiatorWrapperType* memc_ram_wi;
177
178      VciXicu<vci_param_int>*          xicu;
179      VciIntDspinTargetWrapperType*    xicu_int_wt;
180
181      VciMultiDma<vci_param_int>*      mdma;
182      VciIntDspinInitiatorWrapperType* mdma_int_wi;
183      VciIntDspinTargetWrapperType*    mdma_int_wt;
184
185      VciSimpleRom<vci_param_int>*     brom;
186      VciIntDspinTargetWrapperType*    brom_int_wt;
187
188      DspinLocalCrossbar<dspin_int_cmd_width>* int_xbar_cmd_d;
189      DspinLocalCrossbar<dspin_int_rsp_width>* int_xbar_rsp_d;
190      DspinLocalCrossbar<dspin_int_cmd_width>* int_xbar_m2p_c;
191      DspinLocalCrossbar<dspin_int_rsp_width>* int_xbar_p2m_c;
192      DspinLocalCrossbar<dspin_int_cmd_width>* int_xbar_clack_c;
193
194      VirtualDspinRouter<dspin_int_cmd_width>* int_router_cmd;
195      VirtualDspinRouter<dspin_int_rsp_width>* int_router_rsp;
196
197      VciSimpleRam<vci_param_ext>*  xram;
198      VciExtDspinTargetWrapperType* xram_ram_wt;
199
200      DspinRouterTsar<dspin_ram_cmd_width>* ram_router_cmd;
201      DspinRouterTsar<dspin_ram_rsp_width>* ram_router_rsp;
202
203      // IO Network Components (not instanciated in all clusters)
204
205      VciIoBridge<vci_param_int, vci_param_ext>* iob;
206      VciIntDspinInitiatorWrapperType*           iob_int_wi;
207      VciIntDspinTargetWrapperType*              iob_int_wt;
208      VciExtDspinInitiatorWrapperType*           iob_ram_wi;
209
210      size_t m_procs;
211
212      struct ClusterParams {
213         sc_module_name insname;
214
215         size_t nb_procs;
216         size_t nb_dmas;
217         size_t x_id;
218         size_t y_id;
219         size_t x_size;
220         size_t y_size;
221
222         const soclib::common::MappingTable &mt_int;
223         const soclib::common::MappingTable &mt_ext;
224         const soclib::common::MappingTable &mt_iox;
225
226         size_t x_width;
227         size_t y_width;
228         size_t l_width;
229
230         size_t int_memc_tgtid;
231         size_t int_xicu_tgtid;
232         size_t int_mdma_tgtid;
233         size_t int_iobx_tgtid;
234         size_t int_brom_tgtid;
235         size_t int_proc_srcid;
236         size_t int_mdma_srcid;
237         size_t int_iobx_srcid;
238         size_t ext_xram_tgtid;
239         size_t ext_memc_srcid;
240         size_t ext_iobx_srcid;
241
242         size_t memc_ways;
243         size_t memc_sets;
244         size_t l1_i_ways;
245         size_t l1_i_sets;
246         size_t l1_d_ways;
247         size_t l1_d_sets;
248         size_t xram_latency;
249
250         const Loader& loader;
251
252         uint32_t frozen_cycles;
253         uint32_t debug_start_cycle;
254         bool     memc_debug_ok;
255         bool     proc_debug_ok;
256         bool     iob_debug_ok;
257      };
258
259      // cluster constructor
260      TsarIobCluster(struct ClusterParams& params);
261      ~TsarIobCluster();
262};
263
264}}
265
266#endif
267
268// vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3
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