source: branches/fault_tolerance/platform/tsar_generic_iob/tsar_iob_cluster/caba/source/include/tsar_iob_cluster.h @ 695

Last change on this file since 695 was 695, checked in by cfuguet, 10 years ago

branches/fault-tolerance/tsar_generic_iob:

  • Introducing multi-tty component in all clusters for debug. Number of channels is set by a proprocessor contant in the tsar_iob_cluster.h file. Number of channels can be 0 if tty isn't needed.
  • Reducing number of parameters for cluster class. Using constants defined in hard_config.h instead.
File size: 11.3 KB
Line 
1//////////////////////////////////////////////////////////////////////////////
2// File: tsar_iob_cluster.h
3// Author: Alain Greiner
4// Copyright: UPMC/LIP6
5// Date : april 2013
6// This program is released under the GNU public license
7//////////////////////////////////////////////////////////////////////////////
8
9#ifndef SOCLIB_CABA_TSAR_IOB_CLUSTER_H
10#define SOCLIB_CABA_TSAR_IOB_CLUSTER_H
11
12#include <systemc>
13#include <sys/time.h>
14#include <iostream>
15#include <sstream>
16#include <cstdlib>
17#include <cstdarg>
18
19#include "gdbserver.h"
20#include "mapping_table.h"
21#include "mips32.h"
22#include "vci_simple_ram.h"
23#include "vci_simple_rom.h"
24#include "vci_xicu.h"
25#include "dspin_local_crossbar.h"
26#include "vci_dspin_initiator_wrapper.h"
27#include "vci_dspin_target_wrapper.h"
28#include "dspin_router_tsar.h"
29#include "virtual_dspin_router.h"
30#include "vci_multi_dma.h"
31#include "vci_mem_cache.h"
32#include "vci_cc_vcache_wrapper.h"
33#include "vci_io_bridge.h"
34#include "vci_multi_tty.h"
35#include "hard_config.h"
36
37///////////////////////////////////////////////////////////////////////
38//     Number of channels for debug TTY (may be 0)
39///////////////////////////////////////////////////////////////////////
40#define NB_DEBUG_TTY_CHANNELS 1
41
42///////////////////////////////////////////////////////////////////////
43//     TGT_ID and INI_ID port indexing for INT local interconnect
44///////////////////////////////////////////////////////////////////////
45
46#define INT_MEMC_TGT_ID 0
47#define INT_XICU_TGT_ID 1
48#define INT_BROM_TGT_ID 2
49#define INT_MDMA_TGT_ID 3
50#define INT_MTTY_TGT_ID 4
51#define INT_IOBX_TGT_ID (4 + (NB_DEBUG_TTY_CHANNELS ? 1 : 0))
52
53#define INT_PROC_INI_ID 0 // from 0 to 7
54#define INT_MDMA_INI_ID NB_PROCS
55#define INT_IOBX_INI_ID (NB_PROCS + 1)
56
57///////////////////////////////////////////////////////////////////////
58//     TGT_ID and INI_ID port indexing for RAM local interconnect
59///////////////////////////////////////////////////////////////////////
60
61#define RAM_XRAM_TGT_ID 0
62
63#define RAM_MEMC_INI_ID 0
64#define RAM_IOBX_INI_ID 1
65
66namespace soclib { namespace caba {
67
68///////////////////////////////////////////////////////////////////////////
69template<typename vci_param_int,
70         typename vci_param_ext,
71         size_t   dspin_int_cmd_width,
72         size_t   dspin_int_rsp_width,
73         size_t   dspin_ram_cmd_width,
74         size_t   dspin_ram_rsp_width>
75class TsarIobCluster
76///////////////////////////////////////////////////////////////////////////
77    : public soclib::caba::BaseModule
78{
79
80   public:
81
82      // Ports
83      sc_in<bool>   p_clk;
84      sc_in<bool>   p_resetn;
85
86      // Thes two ports are used to connect IOB to IOX nework in top cell
87      soclib::caba::VciInitiator<vci_param_ext>* p_vci_iob_iox_ini;
88      soclib::caba::VciTarget<vci_param_ext>*    p_vci_iob_iox_tgt;
89
90      // These ports are used to connect IOB to RAM network in top cell
91      soclib::caba::DspinOutput<dspin_ram_cmd_width>* p_dspin_iob_cmd_out;
92      soclib::caba::DspinInput<dspin_ram_rsp_width>*  p_dspin_iob_rsp_in;
93
94      // These ports are used to connect hard IRQ from external peripherals to
95      // IOB0
96      sc_in<bool>* p_irq[32];
97
98      // These arrays of ports are used to connect the INT & RAM networks in
99      // top cell
100      soclib::caba::DspinOutput<dspin_int_cmd_width>** p_dspin_int_cmd_out;
101      soclib::caba::DspinInput<dspin_int_cmd_width>**  p_dspin_int_cmd_in;
102      soclib::caba::DspinOutput<dspin_int_rsp_width>** p_dspin_int_rsp_out;
103      soclib::caba::DspinInput<dspin_int_rsp_width>**  p_dspin_int_rsp_in;
104
105      soclib::caba::DspinOutput<dspin_ram_cmd_width>* p_dspin_ram_cmd_out;
106      soclib::caba::DspinInput<dspin_ram_cmd_width>*  p_dspin_ram_cmd_in;
107      soclib::caba::DspinOutput<dspin_ram_rsp_width>* p_dspin_ram_rsp_out;
108      soclib::caba::DspinInput<dspin_ram_rsp_width>*  p_dspin_ram_rsp_in;
109
110      // interrupt signals
111      sc_signal<bool> signal_false;
112      sc_signal<bool> signal_proc_it[8];
113      sc_signal<bool> signal_irq_mdma[8];
114      sc_signal<bool> signal_irq_mtty[8];
115      sc_signal<bool> signal_irq_memc;
116
117      // INT network DSPIN signals between DSPIN routers and DSPIN
118      // local_crossbars
119      DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_l2g_d;
120      DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_g2l_d;
121      DspinSignals<dspin_int_cmd_width> signal_int_dspin_m2p_l2g_c;
122      DspinSignals<dspin_int_cmd_width> signal_int_dspin_m2p_g2l_c;
123      DspinSignals<dspin_int_cmd_width> signal_int_dspin_clack_l2g_c;
124      DspinSignals<dspin_int_cmd_width> signal_int_dspin_clack_g2l_c;
125      DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_l2g_d;
126      DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_g2l_d;
127      DspinSignals<dspin_int_rsp_width> signal_int_dspin_p2m_l2g_c;
128      DspinSignals<dspin_int_rsp_width> signal_int_dspin_p2m_g2l_c;
129
130      // INT network VCI signals between VCI components and VCI/DSPIN wrappers
131      VciSignals<vci_param_int> signal_int_vci_ini_proc[8];
132      VciSignals<vci_param_int> signal_int_vci_ini_mdma;
133      VciSignals<vci_param_int> signal_int_vci_ini_iobx;
134
135      VciSignals<vci_param_int> signal_int_vci_tgt_memc;
136      VciSignals<vci_param_int> signal_int_vci_tgt_xicu;
137      VciSignals<vci_param_int> signal_int_vci_tgt_brom;
138      VciSignals<vci_param_int> signal_int_vci_tgt_mtty;
139      VciSignals<vci_param_int> signal_int_vci_tgt_mdma;
140      VciSignals<vci_param_int> signal_int_vci_tgt_iobx;
141
142      // INT network DSPIN signals between DSPIN local crossbars and VCI/DSPIN
143      // wrappers
144      DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_proc_i[8];
145      DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_proc_i[8];
146      DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_mdma_i;
147      DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_mdma_i;
148      DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_iobx_i;
149      DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_iobx_i;
150
151      DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_memc_t;
152      DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_memc_t;
153      DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_xicu_t;
154      DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_xicu_t;
155      DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_brom_t;
156      DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_brom_t;
157      DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_mtty_t;
158      DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_mtty_t;
159      DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_mdma_t;
160      DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_mdma_t;
161      DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_iobx_t;
162      DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_iobx_t;
163
164      // Coherence DSPIN signals between DSPIN local crossbars and CC
165      // components
166      DspinSignals<dspin_int_cmd_width> signal_int_dspin_m2p_memc;
167      DspinSignals<dspin_int_cmd_width> signal_int_dspin_clack_memc;
168      DspinSignals<dspin_int_rsp_width> signal_int_dspin_p2m_memc;
169      DspinSignals<dspin_int_cmd_width> signal_int_dspin_m2p_proc[8];
170      DspinSignals<dspin_int_cmd_width> signal_int_dspin_clack_proc[8];
171      DspinSignals<dspin_int_rsp_width> signal_int_dspin_p2m_proc[8];
172
173      // RAM network VCI signals between VCI components and VCI/DSPIN wrappers
174      VciSignals<vci_param_ext> signal_ram_vci_ini_memc;
175      VciSignals<vci_param_ext> signal_ram_vci_ini_iobx;
176      VciSignals<vci_param_ext> signal_ram_vci_tgt_xram;
177
178      // RAM network DSPIN signals between VCI/DSPIN wrappers and routers
179      DspinSignals<dspin_ram_cmd_width> signal_ram_dspin_cmd_xram_t;
180      DspinSignals<dspin_ram_rsp_width> signal_ram_dspin_rsp_xram_t;
181      DspinSignals<dspin_ram_cmd_width> signal_ram_dspin_cmd_memc_i;
182      DspinSignals<dspin_ram_rsp_width> signal_ram_dspin_rsp_memc_i;
183
184      //////////////////////////////////////
185      // Hardwate Components (pointers)
186      //////////////////////////////////////
187      typedef VciCcVCacheWrapper<vci_param_int, dspin_int_cmd_width,
188              dspin_int_rsp_width, GdbServer<Mips32ElIss> >
189              VciCcVCacheWrapperType;
190
191      typedef VciMemCache<vci_param_int, vci_param_ext, dspin_int_rsp_width,
192              dspin_int_cmd_width> VciMemCacheType;
193
194      typedef VciDspinInitiatorWrapper<vci_param_int, dspin_int_cmd_width,
195              dspin_int_rsp_width> VciIntDspinInitiatorWrapperType;
196
197      typedef VciDspinTargetWrapper<vci_param_int, dspin_int_cmd_width,
198              dspin_int_rsp_width> VciIntDspinTargetWrapperType;
199
200      typedef VciDspinInitiatorWrapper<vci_param_ext, dspin_ram_cmd_width,
201              dspin_ram_rsp_width> VciExtDspinInitiatorWrapperType;
202
203      typedef VciDspinTargetWrapper<vci_param_ext, dspin_ram_cmd_width,
204              dspin_ram_rsp_width> VciExtDspinTargetWrapperType;
205
206      VciCcVCacheWrapperType*          proc[8];
207      VciIntDspinInitiatorWrapperType* proc_wi[8];
208
209      VciMemCacheType*                 memc;
210      VciIntDspinTargetWrapperType*    memc_int_wt;
211      VciExtDspinInitiatorWrapperType* memc_ram_wi;
212
213      VciXicu<vci_param_int>*          xicu;
214      VciIntDspinTargetWrapperType*    xicu_int_wt;
215
216      VciMultiDma<vci_param_int>*      mdma;
217      VciIntDspinInitiatorWrapperType* mdma_int_wi;
218      VciIntDspinTargetWrapperType*    mdma_int_wt;
219
220      VciSimpleRom<vci_param_int>*     brom;
221      VciIntDspinTargetWrapperType*    brom_int_wt;
222
223      VciMultiTty<vci_param_int>*      mtty;
224      VciIntDspinTargetWrapperType*    mtty_int_wt;
225
226      DspinLocalCrossbar<dspin_int_cmd_width>* int_xbar_cmd_d;
227      DspinLocalCrossbar<dspin_int_rsp_width>* int_xbar_rsp_d;
228      DspinLocalCrossbar<dspin_int_cmd_width>* int_xbar_m2p_c;
229      DspinLocalCrossbar<dspin_int_rsp_width>* int_xbar_p2m_c;
230      DspinLocalCrossbar<dspin_int_cmd_width>* int_xbar_clack_c;
231
232      VirtualDspinRouter<dspin_int_cmd_width>* int_router_cmd;
233      VirtualDspinRouter<dspin_int_rsp_width>* int_router_rsp;
234
235      VciSimpleRam<vci_param_ext>*  xram;
236      VciExtDspinTargetWrapperType* xram_ram_wt;
237
238      DspinRouterTsar<dspin_ram_cmd_width>* ram_router_cmd;
239      DspinRouterTsar<dspin_ram_rsp_width>* ram_router_rsp;
240
241      // IO Network Components (not instanciated in all clusters)
242
243      VciIoBridge<vci_param_int, vci_param_ext>* iob;
244      VciIntDspinInitiatorWrapperType*           iob_int_wi;
245      VciIntDspinTargetWrapperType*              iob_int_wt;
246      VciExtDspinInitiatorWrapperType*           iob_ram_wi;
247
248      size_t m_procs;
249
250      struct ClusterParams {
251         sc_module_name insname;
252
253         size_t x_id;
254         size_t y_id;
255
256         const soclib::common::MappingTable &mt_int;
257         const soclib::common::MappingTable &mt_ext;
258         const soclib::common::MappingTable &mt_iox;
259
260         size_t memc_ways;
261         size_t memc_sets;
262         size_t l1_i_ways;
263         size_t l1_i_sets;
264         size_t l1_d_ways;
265         size_t l1_d_sets;
266         size_t xram_latency;
267
268         const Loader& loader;
269
270         uint32_t frozen_cycles;
271         uint32_t debug_start_cycle;
272         bool     memc_debug_ok;
273         bool     proc_debug_ok;
274         bool     iob_debug_ok;
275      };
276
277      // utility functions
278      static uint32_t clusterId(size_t x_id, size_t y_id) {
279         return ((x_id << Y_WIDTH) | y_id); 
280      };
281
282      // cluster constructor
283      TsarIobCluster(struct ClusterParams& params);
284      ~TsarIobCluster();
285};
286
287}}
288
289#endif
290
291// vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3
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