[450] | 1 | ////////////////////////////////////////////////////////////////////////////// |
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| 2 | // File: tsar_iob_cluster.cpp |
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| 3 | // Author: Alain Greiner |
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| 4 | // Copyright: UPMC/LIP6 |
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| 5 | // Date : april 2013 |
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| 6 | // This program is released under the GNU public license |
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[648] | 7 | // |
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| 8 | // Modified by: Cesar Fuguet |
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| 9 | // Modified on: mars 2014 |
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[450] | 10 | ////////////////////////////////////////////////////////////////////////////// |
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| 11 | // Cluster(0,0) & Cluster(xmax-1,ymax-1) contains the IOB0 & IOB1 components. |
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| 12 | // These two clusters contain 6 extra components: |
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| 13 | // - 1 vci_io_bridge (connected to the 3 networks. |
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| 14 | // - 3 vci_dspin_wrapper for the IOB. |
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| 15 | // - 2 dspin_local_crossbar for commands and responses. |
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| 16 | ////////////////////////////////////////////////////////////////////////////// |
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| 17 | |
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| 18 | #include "../include/tsar_iob_cluster.h" |
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| 19 | |
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[648] | 20 | #define tmpl(x) \ |
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| 21 | template<typename vci_param_int , typename vci_param_ext,\ |
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| 22 | size_t dspin_int_cmd_width, size_t dspin_int_rsp_width,\ |
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| 23 | size_t dspin_ram_cmd_width, size_t dspin_ram_rsp_width>\ |
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| 24 | x TsarIobCluster<\ |
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| 25 | vci_param_int , vci_param_ext,\ |
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| 26 | dspin_int_cmd_width, dspin_int_rsp_width,\ |
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| 27 | dspin_ram_cmd_width, dspin_ram_rsp_width> |
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| 28 | |
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[450] | 29 | namespace soclib { namespace caba { |
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| 30 | |
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| 31 | ////////////////////////////////////////////////////////////////////////// |
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| 32 | // Constructor |
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| 33 | ////////////////////////////////////////////////////////////////////////// |
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[648] | 34 | tmpl(/**/)::TsarIobCluster(struct ClusterParams& params) : |
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| 35 | soclib::caba::BaseModule(params.insname), p_clk("clk"), p_resetn("resetn") |
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| 36 | { |
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| 37 | assert((params.x_id < params.x_size) and (params.y_id < params.y_size)); |
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[450] | 38 | |
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[648] | 39 | this->m_procs = params.nb_procs; |
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| 40 | size_t cluster_id = (params.x_id << 4) + params.y_id; |
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[450] | 41 | |
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[648] | 42 | size_t cluster_iob0 = 0; |
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| 43 | size_t cluster_iob1 = ((params.x_size - 1) << 4) + params.y_size - 1; |
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[450] | 44 | |
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[648] | 45 | // Vectors of DSPIN ports for inter-cluster communications |
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| 46 | p_dspin_int_cmd_in = |
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| 47 | alloc_elems<DspinInput<dspin_int_cmd_width> >("p_int_cmd_in", 4, 3); |
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| 48 | p_dspin_int_cmd_out = |
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| 49 | alloc_elems<DspinOutput<dspin_int_cmd_width> >("p_int_cmd_out", 4, 3); |
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| 50 | p_dspin_int_rsp_in = |
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| 51 | alloc_elems<DspinInput<dspin_int_rsp_width> >("p_int_rsp_in", 4, 2); |
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| 52 | p_dspin_int_rsp_out = |
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| 53 | alloc_elems<DspinOutput<dspin_int_rsp_width> >("p_int_rsp_out", 4, 2); |
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[450] | 54 | |
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[648] | 55 | p_dspin_ram_cmd_in = |
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| 56 | alloc_elems<DspinInput<dspin_ram_cmd_width> >("p_ext_cmd_in", 4); |
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| 57 | p_dspin_ram_cmd_out = |
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| 58 | alloc_elems<DspinOutput<dspin_ram_cmd_width> >("p_ext_cmd_out", 4); |
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| 59 | p_dspin_ram_rsp_in = |
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| 60 | alloc_elems<DspinInput<dspin_ram_rsp_width> >("p_ext_rsp_in", 4); |
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| 61 | p_dspin_ram_rsp_out = |
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| 62 | alloc_elems<DspinOutput<dspin_ram_rsp_width> >("p_ext_rsp_out", 4); |
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[450] | 63 | |
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[648] | 64 | // ports in cluster_iob0 and cluster_iob1 only |
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| 65 | if ( (cluster_id == cluster_iob0) or (cluster_id == cluster_iob1) ) |
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| 66 | { |
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| 67 | // VCI ports from IOB to IOX network |
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| 68 | p_vci_iob_iox_ini = new soclib::caba::VciInitiator<vci_param_ext>; |
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| 69 | p_vci_iob_iox_tgt = new soclib::caba::VciTarget<vci_param_ext>; |
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[450] | 70 | |
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[648] | 71 | // DSPIN ports from IOB to RAM network |
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| 72 | p_dspin_iob_cmd_out = |
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| 73 | new soclib::caba::DspinOutput<dspin_ram_cmd_width>; |
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| 74 | p_dspin_iob_rsp_in = |
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| 75 | new soclib::caba::DspinInput<dspin_ram_rsp_width>; |
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| 76 | } |
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| 77 | else |
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| 78 | { |
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| 79 | p_vci_iob_iox_ini = NULL; |
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| 80 | p_vci_iob_iox_tgt = NULL; |
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| 81 | p_dspin_iob_cmd_out = NULL; |
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| 82 | p_dspin_iob_rsp_in = NULL; |
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| 83 | } |
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[450] | 84 | |
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[648] | 85 | // IRQ ports in cluster_iob0 only |
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| 86 | for ( size_t n = 0 ; n < 32 ; n++ ) |
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| 87 | { |
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| 88 | if ( cluster_id == cluster_iob0 ) |
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| 89 | { |
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| 90 | p_irq[n] = new sc_in<bool>; |
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| 91 | } |
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| 92 | else |
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| 93 | { |
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| 94 | p_irq[n] = NULL; |
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| 95 | } |
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| 96 | } |
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[450] | 97 | |
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[648] | 98 | /////////////////////////////////////////////////////////////////////////// |
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| 99 | // Hardware components |
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| 100 | /////////////////////////////////////////////////////////////////////////// |
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[450] | 101 | |
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[648] | 102 | //////////// PROCS |
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| 103 | for (size_t p = 0; p < params.nb_procs; p++) |
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| 104 | { |
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| 105 | std::ostringstream s_proc; |
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| 106 | s_proc << "proc_" << params.x_id << "_" << params.y_id << "_" << p; |
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| 107 | proc[p] = new VciCcVCacheWrapperType ( |
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| 108 | s_proc.str().c_str(), |
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| 109 | cluster_id * params.nb_procs + p, |
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| 110 | params.mt_int, |
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| 111 | IntTab(cluster_id,p), |
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| 112 | (cluster_id << params.l_width) + p, |
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| 113 | 8, 8, |
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| 114 | 8, 8, |
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| 115 | params.l1_i_ways, params.l1_i_sets, 16, |
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| 116 | params.l1_d_ways, params.l1_d_sets, 16, |
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| 117 | 4, 4, |
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| 118 | params.x_width, params.y_width, |
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| 119 | params.frozen_cycles, |
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| 120 | params.debug_start_cycle, params.proc_debug_ok); |
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[450] | 121 | |
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[648] | 122 | std::ostringstream s_wi_proc; |
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| 123 | s_wi_proc << "proc_wi_" << params.x_id << "_" << params.y_id << "_" |
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| 124 | << p; |
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| 125 | proc_wi[p] = new VciIntDspinInitiatorWrapperType( |
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| 126 | s_wi_proc.str().c_str(), |
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| 127 | params.x_width + params.y_width + params.l_width); |
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| 128 | } |
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[450] | 129 | |
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[648] | 130 | /////////// MEMC |
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| 131 | std::ostringstream s_memc; |
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| 132 | s_memc << "memc_" << params.x_id << "_" << params.y_id; |
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| 133 | memc = new VciMemCacheType ( |
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| 134 | s_memc.str().c_str(), |
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| 135 | params.mt_int, |
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| 136 | params.mt_ext, |
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| 137 | IntTab(cluster_id, params.ext_memc_srcid), |
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| 138 | IntTab(cluster_id, params.int_memc_tgtid), |
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| 139 | params.x_width, |
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| 140 | params.y_width, |
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| 141 | params.memc_ways, params.memc_sets, 16, |
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| 142 | 3, |
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| 143 | 4096, |
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| 144 | 8, |
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| 145 | 8, |
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| 146 | 8, |
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| 147 | params.debug_start_cycle, |
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| 148 | params.memc_debug_ok); |
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[550] | 149 | |
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[648] | 150 | std::ostringstream s_wt_memc; |
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| 151 | s_wt_memc << "memc_wt_" << params.x_id << "_" << params.y_id; |
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| 152 | memc_int_wt = new VciIntDspinTargetWrapperType ( |
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| 153 | s_wt_memc.str().c_str(), |
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| 154 | params.x_width + params.y_width + params.l_width); |
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[450] | 155 | |
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[648] | 156 | std::ostringstream s_wi_memc; |
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| 157 | s_wi_memc << "memc_wi_" << params.x_id << "_" << params.y_id; |
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| 158 | memc_ram_wi = new VciExtDspinInitiatorWrapperType ( |
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| 159 | s_wi_memc.str().c_str(), |
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| 160 | params.x_width + params.y_width + params.l_width); |
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[450] | 161 | |
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[648] | 162 | /////////// XICU |
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| 163 | std::ostringstream s_xicu; |
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| 164 | s_xicu << "xicu_" << params.x_id << "_" << params.y_id; |
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| 165 | xicu = new VciXicu<vci_param_int>( |
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| 166 | s_xicu.str().c_str(), |
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| 167 | params.mt_int, |
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| 168 | IntTab(cluster_id,params.int_xicu_tgtid), |
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| 169 | 32, 32, 32, |
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| 170 | params.nb_procs); |
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[550] | 171 | |
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[648] | 172 | std::ostringstream s_wt_xicu; |
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| 173 | s_wt_xicu << "xicu_wt_" << params.x_id << "_" << params.y_id; |
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| 174 | xicu_int_wt = new VciIntDspinTargetWrapperType ( |
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| 175 | s_wt_xicu.str().c_str(), |
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| 176 | params.x_width + params.y_width + params.l_width); |
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[450] | 177 | |
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[648] | 178 | //////////// MDMA |
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| 179 | std::ostringstream s_mdma; |
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| 180 | s_mdma << "mdma_" << params.x_id << "_" << params.y_id; |
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| 181 | mdma = new VciMultiDma<vci_param_int>( |
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| 182 | s_mdma.str().c_str(), |
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| 183 | params.mt_int, |
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| 184 | IntTab(cluster_id, params.nb_procs), |
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| 185 | IntTab(cluster_id, params.int_mdma_tgtid), |
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| 186 | 64, |
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| 187 | params.nb_dmas); |
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[450] | 188 | |
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[648] | 189 | std::ostringstream s_wt_mdma; |
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| 190 | s_wt_mdma << "mdma_wt_" << params.x_id << "_" << params.y_id; |
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| 191 | mdma_int_wt = new VciIntDspinTargetWrapperType( |
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| 192 | s_wt_mdma.str().c_str(), |
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| 193 | params.x_width + params.y_width + params.l_width); |
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[450] | 194 | |
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[648] | 195 | std::ostringstream s_wi_mdma; |
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| 196 | s_wi_mdma << "mdma_wi_" << params.x_id << "_" << params.y_id; |
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| 197 | mdma_int_wi = new VciIntDspinInitiatorWrapperType( |
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| 198 | s_wi_mdma.str().c_str(), |
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| 199 | params.x_width + params.y_width + params.l_width); |
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[450] | 200 | |
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[648] | 201 | /////////// Direct LOCAL_XBAR(S) |
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| 202 | size_t nb_direct_initiators = params.nb_procs + 1; |
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| 203 | size_t nb_direct_targets = 3; |
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| 204 | if ((cluster_id == cluster_iob0) or (cluster_id == cluster_iob1)) |
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| 205 | { |
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| 206 | nb_direct_initiators = params.nb_procs + 2; |
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| 207 | nb_direct_targets = 4; |
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| 208 | } |
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[450] | 209 | |
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[648] | 210 | std::ostringstream s_int_xbar_cmd_d; |
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| 211 | s_int_xbar_cmd_d << "int_xbar_cmd_d_" << params.x_id << "_" << params.y_id; |
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| 212 | int_xbar_cmd_d = new DspinLocalCrossbar<dspin_int_cmd_width>( |
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| 213 | s_int_xbar_cmd_d.str().c_str(), |
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| 214 | params.mt_int, |
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| 215 | params.x_id, params.y_id, |
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| 216 | params.x_width, params.y_width, params.l_width, |
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| 217 | nb_direct_initiators, |
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| 218 | nb_direct_targets, |
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| 219 | 2, 2, |
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| 220 | true, |
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| 221 | true, |
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| 222 | false); |
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[450] | 223 | |
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[648] | 224 | std::ostringstream s_int_xbar_rsp_d; |
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| 225 | s_int_xbar_rsp_d << "int_xbar_rsp_d_" << params.x_id << "_" << params.y_id; |
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| 226 | int_xbar_rsp_d = new DspinLocalCrossbar<dspin_int_rsp_width>( |
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| 227 | s_int_xbar_rsp_d.str().c_str(), |
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| 228 | params.mt_int, |
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| 229 | params.x_id, params.y_id, |
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| 230 | params.x_width, params.y_width, params.l_width, |
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| 231 | nb_direct_targets, |
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| 232 | nb_direct_initiators, |
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| 233 | 2, 2, |
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| 234 | false, |
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| 235 | false, |
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| 236 | false); |
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[450] | 237 | |
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[648] | 238 | //////////// Coherence LOCAL_XBAR(S) |
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| 239 | std::ostringstream s_int_xbar_m2p_c; |
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| 240 | s_int_xbar_m2p_c << "int_xbar_m2p_c_" << params.x_id << "_" << params.y_id; |
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| 241 | int_xbar_m2p_c = new DspinLocalCrossbar<dspin_int_cmd_width>( |
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| 242 | s_int_xbar_m2p_c.str().c_str(), |
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| 243 | params.mt_int, |
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| 244 | params.x_id, params.y_id, |
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| 245 | params.x_width, params.y_width, params.l_width, |
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| 246 | 1, |
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| 247 | params.nb_procs, |
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| 248 | 2, 2, |
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| 249 | true, |
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| 250 | false, |
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| 251 | true); |
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[450] | 252 | |
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[648] | 253 | std::ostringstream s_int_xbar_p2m_c; |
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| 254 | s_int_xbar_p2m_c << "int_xbar_p2m_c_" << params.x_id << "_" << params.y_id; |
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| 255 | int_xbar_p2m_c = new DspinLocalCrossbar<dspin_int_rsp_width>( |
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| 256 | s_int_xbar_p2m_c.str().c_str(), |
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| 257 | params.mt_int, |
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| 258 | params.x_id, params.y_id, |
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| 259 | params.x_width, params.y_width, 0, |
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| 260 | params.nb_procs, |
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| 261 | 1, |
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| 262 | 2, 2, |
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| 263 | false, |
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| 264 | false, |
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| 265 | false); |
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[450] | 266 | |
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[648] | 267 | std::ostringstream s_int_xbar_clack_c; |
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| 268 | s_int_xbar_clack_c << "int_xbar_clack_c_" << params.x_id << "_" |
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| 269 | << params.y_id; |
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| 270 | int_xbar_clack_c = new DspinLocalCrossbar<dspin_int_cmd_width>( |
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| 271 | s_int_xbar_clack_c.str().c_str(), |
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| 272 | params.mt_int, |
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| 273 | params.x_id, params.y_id, |
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| 274 | params.x_width, params.y_width, params.l_width, |
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| 275 | 1, |
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| 276 | params.nb_procs, |
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| 277 | 1, 1, |
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| 278 | true, |
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| 279 | false, |
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| 280 | false); |
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[450] | 281 | |
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[648] | 282 | ////////////// INT ROUTER(S) |
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| 283 | std::ostringstream s_int_router_cmd; |
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| 284 | s_int_router_cmd << "router_cmd_" << params.x_id << "_" << params.y_id; |
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| 285 | int_router_cmd = new VirtualDspinRouter<dspin_int_cmd_width>( |
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| 286 | s_int_router_cmd.str().c_str(), |
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| 287 | params.x_id,params.y_id, |
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| 288 | params.x_width, params.y_width, |
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| 289 | 3, |
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| 290 | 4,4); |
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[450] | 291 | |
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[648] | 292 | std::ostringstream s_int_router_rsp; |
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| 293 | s_int_router_rsp << "router_rsp_" << params.x_id << "_" << params.y_id; |
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| 294 | int_router_rsp = new VirtualDspinRouter<dspin_int_rsp_width>( |
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| 295 | s_int_router_rsp.str().c_str(), |
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| 296 | params.x_id,params.y_id, |
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| 297 | params.x_width, params.y_width, |
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| 298 | 2, |
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| 299 | 4,4); |
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[450] | 300 | |
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[648] | 301 | ////////////// XRAM |
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| 302 | std::ostringstream s_xram; |
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| 303 | s_xram << "xram_" << params.x_id << "_" << params.y_id; |
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| 304 | xram = new VciSimpleRam<vci_param_ext>( |
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| 305 | s_xram.str().c_str(), |
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| 306 | IntTab(cluster_id, params.ext_xram_tgtid), |
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| 307 | params.mt_ext, |
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| 308 | params.loader, |
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| 309 | params.xram_latency); |
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[450] | 310 | |
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[648] | 311 | std::ostringstream s_wt_xram; |
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| 312 | s_wt_xram << "xram_wt_" << params.x_id << "_" << params.y_id; |
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| 313 | xram_ram_wt = new VciExtDspinTargetWrapperType( |
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| 314 | s_wt_xram.str().c_str(), |
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| 315 | params.x_width + params.y_width + params.l_width); |
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[450] | 316 | |
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[648] | 317 | ///////////// RAM ROUTER(S) |
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| 318 | std::ostringstream s_ram_router_cmd; |
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| 319 | s_ram_router_cmd << "ram_router_cmd_" << params.x_id << "_" << params.y_id; |
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| 320 | size_t is_iob0 = (params.x_id == 0) and (params.y_id == 0); |
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| 321 | size_t is_iob1 = (params.x_id == (params.x_size-1)) and |
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| 322 | (params.y_id == (params.y_size-1)); |
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| 323 | ram_router_cmd = new DspinRouterTsar<dspin_ram_cmd_width>( |
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| 324 | s_ram_router_cmd.str().c_str(), |
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| 325 | params.x_id, params.y_id, |
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| 326 | params.x_width, |
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| 327 | params.y_width, |
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| 328 | 4, 4, |
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| 329 | is_iob0, |
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| 330 | is_iob1, |
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| 331 | false, |
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| 332 | params.l_width); |
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[450] | 333 | |
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[648] | 334 | std::ostringstream s_ram_router_rsp; |
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| 335 | s_ram_router_rsp << "ram_router_rsp_" << params.x_id << "_" << params.y_id; |
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| 336 | ram_router_rsp = new DspinRouterTsar<dspin_ram_rsp_width>( |
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| 337 | s_ram_router_rsp.str().c_str(), |
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| 338 | params.x_id, params.y_id, |
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| 339 | params.x_width, |
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| 340 | params.y_width, |
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| 341 | 4, 4, |
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| 342 | is_iob0, |
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| 343 | is_iob1, |
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| 344 | true, |
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| 345 | params.l_width); |
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[450] | 346 | |
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[648] | 347 | ////////////////////// I/O CLUSTER ONLY /////////////////////// |
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| 348 | if ((cluster_id == cluster_iob0) or (cluster_id == cluster_iob1)) |
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| 349 | { |
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| 350 | /////////// IO_BRIDGE |
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| 351 | size_t iox_local_id; |
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| 352 | size_t global_id; |
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| 353 | bool has_irqs; |
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| 354 | if (cluster_id == cluster_iob0 ) |
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| 355 | { |
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| 356 | iox_local_id = 0; |
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| 357 | global_id = cluster_iob0; |
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| 358 | has_irqs = true; |
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| 359 | } |
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| 360 | else |
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| 361 | { |
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| 362 | iox_local_id = 1; |
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| 363 | global_id = cluster_iob1; |
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| 364 | has_irqs = false; |
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| 365 | } |
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[450] | 366 | |
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[648] | 367 | std::ostringstream s_iob; |
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| 368 | s_iob << "iob_" << params.x_id << "_" << params.y_id; |
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| 369 | iob = new VciIoBridge<vci_param_int, vci_param_ext>( |
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| 370 | s_iob.str().c_str(), |
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| 371 | params.mt_ext, |
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| 372 | params.mt_int, |
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| 373 | params.mt_iox, |
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| 374 | IntTab( global_id, params.int_iobx_tgtid), |
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| 375 | IntTab( global_id, params.int_iobx_srcid), |
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| 376 | IntTab( global_id, iox_local_id ), |
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| 377 | has_irqs, |
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| 378 | 16, |
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| 379 | 8, |
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| 380 | 8, |
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| 381 | params.debug_start_cycle, |
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| 382 | params.iob_debug_ok ); |
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[450] | 383 | |
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[648] | 384 | std::ostringstream s_iob_int_wi; |
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| 385 | s_iob_int_wi << "iob_int_wi_" << params.x_id << "_" << params.y_id; |
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| 386 | iob_int_wi = new VciIntDspinInitiatorWrapperType( |
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| 387 | s_iob_int_wi.str().c_str(), |
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| 388 | params.x_width + params.y_width + params.l_width); |
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[468] | 389 | |
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[648] | 390 | std::ostringstream s_iob_int_wt; |
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| 391 | s_iob_int_wt << "iob_int_wt_" << params.x_id << "_" << params.y_id; |
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| 392 | iob_int_wt = new VciIntDspinTargetWrapperType( |
---|
| 393 | s_iob_int_wt.str().c_str(), |
---|
| 394 | params.x_width + params.y_width + params.l_width); |
---|
[450] | 395 | |
---|
[648] | 396 | std::ostringstream s_iob_ram_wi; |
---|
| 397 | s_iob_ram_wi << "iob_ram_wi_" << params.x_id << "_" << params.y_id; |
---|
| 398 | iob_ram_wi = new VciExtDspinInitiatorWrapperType( |
---|
| 399 | s_iob_ram_wi.str().c_str(), |
---|
| 400 | params.x_width + params.y_width + params.l_width); |
---|
| 401 | } |
---|
| 402 | else |
---|
| 403 | { |
---|
| 404 | iob = NULL; |
---|
| 405 | iob_int_wi = NULL; |
---|
| 406 | iob_int_wt = NULL; |
---|
| 407 | iob_ram_wi = NULL; |
---|
| 408 | } |
---|
[450] | 409 | |
---|
[648] | 410 | //////////////////////////////////// |
---|
| 411 | // Connections are defined here |
---|
| 412 | //////////////////////////////////// |
---|
[450] | 413 | |
---|
[648] | 414 | // on coherence network : local srcid[proc] in [0...nb_procs-1] |
---|
| 415 | // : local srcid[memc] = nb_procs |
---|
| 416 | // In cluster_iob0, 32 HWI interrupts from external peripherals |
---|
| 417 | // are connected to the XICU ports p_hwi[0:31] |
---|
| 418 | // In other clusters, no HWI interrupts are connected to XICU |
---|
[450] | 419 | |
---|
[648] | 420 | //////////////////////// internal CMD & RSP routers |
---|
| 421 | int_router_cmd->p_clk (this->p_clk); |
---|
| 422 | int_router_cmd->p_resetn (this->p_resetn); |
---|
| 423 | int_router_rsp->p_clk (this->p_clk); |
---|
| 424 | int_router_rsp->p_resetn (this->p_resetn); |
---|
[450] | 425 | |
---|
[648] | 426 | for (int i = 0; i < 4; i++) |
---|
| 427 | { |
---|
| 428 | for(int k = 0; k < 3; k++) |
---|
| 429 | { |
---|
| 430 | int_router_cmd->p_out[i][k] (this->p_dspin_int_cmd_out[i][k]); |
---|
| 431 | int_router_cmd->p_in[i][k] (this->p_dspin_int_cmd_in[i][k]); |
---|
| 432 | } |
---|
[450] | 433 | |
---|
[648] | 434 | for(int k = 0; k < 2; k++) |
---|
| 435 | { |
---|
| 436 | int_router_rsp->p_out[i][k] (this->p_dspin_int_rsp_out[i][k]); |
---|
| 437 | int_router_rsp->p_in[i][k] (this->p_dspin_int_rsp_in[i][k]); |
---|
| 438 | } |
---|
| 439 | } |
---|
[550] | 440 | |
---|
[648] | 441 | // local ports |
---|
| 442 | int_router_cmd->p_out[4][0] (signal_int_dspin_cmd_g2l_d); |
---|
| 443 | int_router_cmd->p_out[4][1] (signal_int_dspin_m2p_g2l_c); |
---|
| 444 | int_router_cmd->p_out[4][2] (signal_int_dspin_clack_g2l_c); |
---|
| 445 | int_router_cmd->p_in[4][0] (signal_int_dspin_cmd_l2g_d); |
---|
| 446 | int_router_cmd->p_in[4][1] (signal_int_dspin_m2p_l2g_c); |
---|
| 447 | int_router_cmd->p_in[4][2] (signal_int_dspin_clack_l2g_c); |
---|
[450] | 448 | |
---|
[648] | 449 | int_router_rsp->p_out[4][0] (signal_int_dspin_rsp_g2l_d); |
---|
| 450 | int_router_rsp->p_out[4][1] (signal_int_dspin_p2m_g2l_c); |
---|
| 451 | int_router_rsp->p_in[4][0] (signal_int_dspin_rsp_l2g_d); |
---|
| 452 | int_router_rsp->p_in[4][1] (signal_int_dspin_p2m_l2g_c); |
---|
[450] | 453 | |
---|
[648] | 454 | ///////////////////// CMD DSPIN local crossbar direct |
---|
| 455 | int_xbar_cmd_d->p_clk (this->p_clk); |
---|
| 456 | int_xbar_cmd_d->p_resetn (this->p_resetn); |
---|
| 457 | int_xbar_cmd_d->p_global_out (signal_int_dspin_cmd_l2g_d); |
---|
| 458 | int_xbar_cmd_d->p_global_in (signal_int_dspin_cmd_g2l_d); |
---|
[450] | 459 | |
---|
[648] | 460 | int_xbar_cmd_d->p_local_out[params.int_memc_tgtid]( |
---|
| 461 | signal_int_dspin_cmd_memc_t); |
---|
| 462 | int_xbar_cmd_d->p_local_out[params.int_xicu_tgtid]( |
---|
| 463 | signal_int_dspin_cmd_xicu_t); |
---|
| 464 | int_xbar_cmd_d->p_local_out[params.int_mdma_tgtid]( |
---|
| 465 | signal_int_dspin_cmd_mdma_t); |
---|
| 466 | int_xbar_cmd_d->p_local_in[params.int_mdma_srcid]( |
---|
| 467 | signal_int_dspin_cmd_mdma_i); |
---|
[450] | 468 | |
---|
[648] | 469 | for (size_t p = 0; p < params.nb_procs; p++) { |
---|
| 470 | int_xbar_cmd_d->p_local_in[params.int_proc_srcid + p]( |
---|
| 471 | signal_int_dspin_cmd_proc_i[p]); |
---|
| 472 | } |
---|
[450] | 473 | |
---|
[648] | 474 | if ((cluster_id == cluster_iob0) or (cluster_id == cluster_iob1)) |
---|
| 475 | { |
---|
| 476 | int_xbar_cmd_d->p_local_out[params.int_iobx_tgtid]( |
---|
| 477 | signal_int_dspin_cmd_iobx_t); |
---|
| 478 | int_xbar_cmd_d->p_local_in[params.int_iobx_srcid]( |
---|
| 479 | signal_int_dspin_cmd_iobx_i); |
---|
| 480 | } |
---|
[468] | 481 | |
---|
[648] | 482 | //////////////////////// RSP DSPIN local crossbar direct |
---|
| 483 | int_xbar_rsp_d->p_clk (this->p_clk); |
---|
| 484 | int_xbar_rsp_d->p_resetn (this->p_resetn); |
---|
| 485 | int_xbar_rsp_d->p_global_out (signal_int_dspin_rsp_l2g_d); |
---|
| 486 | int_xbar_rsp_d->p_global_in (signal_int_dspin_rsp_g2l_d); |
---|
[468] | 487 | |
---|
[648] | 488 | int_xbar_rsp_d->p_local_in[params.int_memc_tgtid]( |
---|
| 489 | signal_int_dspin_rsp_memc_t); |
---|
| 490 | int_xbar_rsp_d->p_local_in[params.int_xicu_tgtid]( |
---|
| 491 | signal_int_dspin_rsp_xicu_t); |
---|
| 492 | int_xbar_rsp_d->p_local_in[params.int_mdma_tgtid]( |
---|
| 493 | signal_int_dspin_rsp_mdma_t); |
---|
[450] | 494 | |
---|
[648] | 495 | int_xbar_rsp_d->p_local_out[params.int_mdma_srcid]( |
---|
| 496 | signal_int_dspin_rsp_mdma_i); |
---|
| 497 | for (size_t p = 0; p < params.nb_procs; p++) |
---|
| 498 | int_xbar_rsp_d->p_local_out[params.int_proc_srcid + p]( |
---|
| 499 | signal_int_dspin_rsp_proc_i[p]); |
---|
[450] | 500 | |
---|
[648] | 501 | if ((cluster_id == cluster_iob0) or (cluster_id == cluster_iob1)) |
---|
| 502 | { |
---|
| 503 | int_xbar_rsp_d->p_local_in[params.int_iobx_tgtid]( |
---|
| 504 | signal_int_dspin_rsp_iobx_t); |
---|
| 505 | int_xbar_rsp_d->p_local_out[params.int_iobx_srcid]( |
---|
| 506 | signal_int_dspin_rsp_iobx_i); |
---|
| 507 | } |
---|
[450] | 508 | |
---|
[648] | 509 | ////////////////////// M2P DSPIN local crossbar coherence |
---|
| 510 | int_xbar_m2p_c->p_clk (this->p_clk); |
---|
| 511 | int_xbar_m2p_c->p_resetn (this->p_resetn); |
---|
| 512 | int_xbar_m2p_c->p_global_out (signal_int_dspin_m2p_l2g_c); |
---|
| 513 | int_xbar_m2p_c->p_global_in (signal_int_dspin_m2p_g2l_c); |
---|
| 514 | int_xbar_m2p_c->p_local_in[0] (signal_int_dspin_m2p_memc); |
---|
| 515 | for (size_t p = 0; p < params.nb_procs; p++) |
---|
| 516 | { |
---|
| 517 | int_xbar_m2p_c->p_local_out[p] (signal_int_dspin_m2p_proc[p]); |
---|
| 518 | } |
---|
[450] | 519 | |
---|
[648] | 520 | ////////////////////////// P2M DSPIN local crossbar coherence |
---|
| 521 | int_xbar_p2m_c->p_clk (this->p_clk); |
---|
| 522 | int_xbar_p2m_c->p_resetn (this->p_resetn); |
---|
| 523 | int_xbar_p2m_c->p_global_out (signal_int_dspin_p2m_l2g_c); |
---|
| 524 | int_xbar_p2m_c->p_global_in (signal_int_dspin_p2m_g2l_c); |
---|
| 525 | int_xbar_p2m_c->p_local_out[0] (signal_int_dspin_p2m_memc); |
---|
| 526 | for (size_t p = 0; p < params.nb_procs; p++) |
---|
| 527 | { |
---|
| 528 | int_xbar_p2m_c->p_local_in[p] (signal_int_dspin_p2m_proc[p]); |
---|
| 529 | } |
---|
| 530 | |
---|
| 531 | ////////////////////// CLACK DSPIN local crossbar coherence |
---|
| 532 | int_xbar_clack_c->p_clk (this->p_clk); |
---|
| 533 | int_xbar_clack_c->p_resetn (this->p_resetn); |
---|
| 534 | int_xbar_clack_c->p_global_out (signal_int_dspin_clack_l2g_c); |
---|
| 535 | int_xbar_clack_c->p_global_in (signal_int_dspin_clack_g2l_c); |
---|
| 536 | int_xbar_clack_c->p_local_in[0] (signal_int_dspin_clack_memc); |
---|
| 537 | for (size_t p = 0; p < params.nb_procs; p++) |
---|
| 538 | { |
---|
| 539 | int_xbar_clack_c->p_local_out[p] (signal_int_dspin_clack_proc[p]); |
---|
| 540 | } |
---|
[450] | 541 | |
---|
[648] | 542 | //////////////////////////////////// Processors |
---|
| 543 | for (size_t p = 0; p < params.nb_procs; p++) |
---|
| 544 | { |
---|
| 545 | proc[p]->p_clk (this->p_clk); |
---|
| 546 | proc[p]->p_resetn (this->p_resetn); |
---|
| 547 | proc[p]->p_vci (signal_int_vci_ini_proc[p]); |
---|
| 548 | proc[p]->p_dspin_m2p (signal_int_dspin_m2p_proc[p]); |
---|
| 549 | proc[p]->p_dspin_p2m (signal_int_dspin_p2m_proc[p]); |
---|
| 550 | proc[p]->p_dspin_clack (signal_int_dspin_clack_proc[p]); |
---|
| 551 | proc[p]->p_irq[0] (signal_proc_it[p]); |
---|
| 552 | for ( size_t j = 1 ; j < 6 ; j++) |
---|
| 553 | { |
---|
| 554 | proc[p]->p_irq[j] (signal_false); |
---|
| 555 | } |
---|
[450] | 556 | |
---|
[648] | 557 | proc_wi[p]->p_clk (this->p_clk); |
---|
| 558 | proc_wi[p]->p_resetn (this->p_resetn); |
---|
| 559 | proc_wi[p]->p_dspin_cmd (signal_int_dspin_cmd_proc_i[p]); |
---|
| 560 | proc_wi[p]->p_dspin_rsp (signal_int_dspin_rsp_proc_i[p]); |
---|
| 561 | proc_wi[p]->p_vci (signal_int_vci_ini_proc[p]); |
---|
| 562 | } |
---|
[450] | 563 | |
---|
[648] | 564 | ///////////////////////////////////// XICU |
---|
| 565 | xicu->p_clk (this->p_clk); |
---|
| 566 | xicu->p_resetn (this->p_resetn); |
---|
| 567 | xicu->p_vci (signal_int_vci_tgt_xicu); |
---|
| 568 | for ( size_t p = 0 ; p < params.nb_procs ; p++) |
---|
| 569 | { |
---|
| 570 | xicu->p_irq[p] (signal_proc_it[p]); |
---|
| 571 | } |
---|
| 572 | for ( size_t i=0 ; i<32 ; i++) |
---|
| 573 | { |
---|
| 574 | if (cluster_id == cluster_iob0) |
---|
| 575 | xicu->p_hwi[i] (*(this->p_irq[i])); |
---|
| 576 | else |
---|
| 577 | xicu->p_hwi[i] (signal_false); |
---|
| 578 | } |
---|
[450] | 579 | |
---|
[648] | 580 | // wrapper XICU |
---|
| 581 | xicu_int_wt->p_clk (this->p_clk); |
---|
| 582 | xicu_int_wt->p_resetn (this->p_resetn); |
---|
| 583 | xicu_int_wt->p_dspin_cmd (signal_int_dspin_cmd_xicu_t); |
---|
| 584 | xicu_int_wt->p_dspin_rsp (signal_int_dspin_rsp_xicu_t); |
---|
| 585 | xicu_int_wt->p_vci (signal_int_vci_tgt_xicu); |
---|
[450] | 586 | |
---|
[648] | 587 | ///////////////////////////////////// MEMC |
---|
| 588 | memc->p_clk (this->p_clk); |
---|
| 589 | memc->p_resetn (this->p_resetn); |
---|
| 590 | memc->p_vci_ixr (signal_ram_vci_ini_memc); |
---|
| 591 | memc->p_vci_tgt (signal_int_vci_tgt_memc); |
---|
| 592 | memc->p_dspin_p2m (signal_int_dspin_p2m_memc); |
---|
| 593 | memc->p_dspin_m2p (signal_int_dspin_m2p_memc); |
---|
| 594 | memc->p_dspin_clack (signal_int_dspin_clack_memc); |
---|
| 595 | memc->p_irq (signal_irq_memc); |
---|
[450] | 596 | |
---|
[648] | 597 | // wrapper to INT network |
---|
| 598 | memc_int_wt->p_clk (this->p_clk); |
---|
| 599 | memc_int_wt->p_resetn (this->p_resetn); |
---|
| 600 | memc_int_wt->p_dspin_cmd (signal_int_dspin_cmd_memc_t); |
---|
| 601 | memc_int_wt->p_dspin_rsp (signal_int_dspin_rsp_memc_t); |
---|
| 602 | memc_int_wt->p_vci (signal_int_vci_tgt_memc); |
---|
[450] | 603 | |
---|
[648] | 604 | // wrapper to RAM network |
---|
| 605 | memc_ram_wi->p_clk (this->p_clk); |
---|
| 606 | memc_ram_wi->p_resetn (this->p_resetn); |
---|
| 607 | memc_ram_wi->p_dspin_cmd (signal_ram_dspin_cmd_memc_i); |
---|
| 608 | memc_ram_wi->p_dspin_rsp (signal_ram_dspin_rsp_memc_i); |
---|
| 609 | memc_ram_wi->p_vci (signal_ram_vci_ini_memc); |
---|
[450] | 610 | |
---|
[648] | 611 | //////////////////////////////////// XRAM |
---|
| 612 | xram->p_clk (this->p_clk); |
---|
| 613 | xram->p_resetn (this->p_resetn); |
---|
| 614 | xram->p_vci (signal_ram_vci_tgt_xram); |
---|
[450] | 615 | |
---|
[648] | 616 | // wrapper to RAM network |
---|
| 617 | xram_ram_wt->p_clk (this->p_clk); |
---|
| 618 | xram_ram_wt->p_resetn (this->p_resetn); |
---|
| 619 | xram_ram_wt->p_dspin_cmd (signal_ram_dspin_cmd_xram_t); |
---|
| 620 | xram_ram_wt->p_dspin_rsp (signal_ram_dspin_rsp_xram_t); |
---|
| 621 | xram_ram_wt->p_vci (signal_ram_vci_tgt_xram); |
---|
[450] | 622 | |
---|
[648] | 623 | /////////////////////////////////// MDMA |
---|
| 624 | mdma->p_clk (this->p_clk); |
---|
| 625 | mdma->p_resetn (this->p_resetn); |
---|
| 626 | mdma->p_vci_target (signal_int_vci_tgt_mdma); |
---|
| 627 | mdma->p_vci_initiator (signal_int_vci_ini_mdma); |
---|
| 628 | for (size_t i = 0 ; i < params.nb_dmas ; i++) |
---|
| 629 | mdma->p_irq[i] (signal_irq_mdma[i]); |
---|
[468] | 630 | |
---|
[648] | 631 | // target wrapper |
---|
| 632 | mdma_int_wt->p_clk (this->p_clk); |
---|
| 633 | mdma_int_wt->p_resetn (this->p_resetn); |
---|
| 634 | mdma_int_wt->p_dspin_cmd (signal_int_dspin_cmd_mdma_t); |
---|
| 635 | mdma_int_wt->p_dspin_rsp (signal_int_dspin_rsp_mdma_t); |
---|
| 636 | mdma_int_wt->p_vci (signal_int_vci_tgt_mdma); |
---|
[450] | 637 | |
---|
[648] | 638 | // initiator wrapper |
---|
| 639 | mdma_int_wi->p_clk (this->p_clk); |
---|
| 640 | mdma_int_wi->p_resetn (this->p_resetn); |
---|
| 641 | mdma_int_wi->p_dspin_cmd (signal_int_dspin_cmd_mdma_i); |
---|
| 642 | mdma_int_wi->p_dspin_rsp (signal_int_dspin_rsp_mdma_i); |
---|
| 643 | mdma_int_wi->p_vci (signal_int_vci_ini_mdma); |
---|
[450] | 644 | |
---|
[648] | 645 | //////////////////////////// RAM network CMD & RSP routers |
---|
| 646 | ram_router_cmd->p_clk (this->p_clk); |
---|
| 647 | ram_router_cmd->p_resetn (this->p_resetn); |
---|
| 648 | ram_router_rsp->p_clk (this->p_clk); |
---|
| 649 | ram_router_rsp->p_resetn (this->p_resetn); |
---|
| 650 | for( size_t n=0 ; n<4 ; n++) |
---|
| 651 | { |
---|
| 652 | ram_router_cmd->p_out[n] (this->p_dspin_ram_cmd_out[n]); |
---|
| 653 | ram_router_cmd->p_in[n] (this->p_dspin_ram_cmd_in[n]); |
---|
| 654 | ram_router_rsp->p_out[n] (this->p_dspin_ram_rsp_out[n]); |
---|
| 655 | ram_router_rsp->p_in[n] (this->p_dspin_ram_rsp_in[n]); |
---|
| 656 | } |
---|
| 657 | ram_router_cmd->p_out[4] (signal_ram_dspin_cmd_xram_t); |
---|
| 658 | ram_router_cmd->p_in[4] (signal_ram_dspin_cmd_memc_i); |
---|
| 659 | ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_memc_i); |
---|
| 660 | ram_router_rsp->p_in[4] (signal_ram_dspin_rsp_xram_t); |
---|
[450] | 661 | |
---|
[648] | 662 | ///////////////////////// IOB exists only in cluster_iob0 & cluster_iob1. |
---|
| 663 | if ( (cluster_id == cluster_iob0) or (cluster_id == cluster_iob1) ) |
---|
| 664 | { |
---|
| 665 | // IO bridge |
---|
| 666 | iob->p_clk (this->p_clk); |
---|
| 667 | iob->p_resetn (this->p_resetn); |
---|
| 668 | iob->p_vci_ini_iox (*(this->p_vci_iob_iox_ini)); |
---|
| 669 | iob->p_vci_tgt_iox (*(this->p_vci_iob_iox_tgt)); |
---|
| 670 | iob->p_vci_tgt_int (signal_int_vci_tgt_iobx); |
---|
| 671 | iob->p_vci_ini_int (signal_int_vci_ini_iobx); |
---|
| 672 | iob->p_vci_ini_ram (signal_ram_vci_ini_iobx); |
---|
[450] | 673 | |
---|
[648] | 674 | if ( cluster_id == cluster_iob0 ) |
---|
| 675 | for ( size_t n = 0 ; n < 32 ; n++ ) |
---|
| 676 | (*iob->p_irq[n]) (*(this->p_irq[n])); |
---|
[450] | 677 | |
---|
[648] | 678 | // initiator wrapper to RAM network |
---|
| 679 | iob_ram_wi->p_clk (this->p_clk); |
---|
| 680 | iob_ram_wi->p_resetn (this->p_resetn); |
---|
| 681 | iob_ram_wi->p_dspin_cmd (*(this->p_dspin_iob_cmd_out)); |
---|
| 682 | iob_ram_wi->p_dspin_rsp (*(this->p_dspin_iob_rsp_in)); |
---|
| 683 | iob_ram_wi->p_vci (signal_ram_vci_ini_iobx); |
---|
[450] | 684 | |
---|
[648] | 685 | // initiator wrapper to INT network |
---|
| 686 | iob_int_wi->p_clk (this->p_clk); |
---|
| 687 | iob_int_wi->p_resetn (this->p_resetn); |
---|
| 688 | iob_int_wi->p_dspin_cmd (signal_int_dspin_cmd_iobx_i); |
---|
| 689 | iob_int_wi->p_dspin_rsp (signal_int_dspin_rsp_iobx_i); |
---|
| 690 | iob_int_wi->p_vci (signal_int_vci_ini_iobx); |
---|
[450] | 691 | |
---|
[648] | 692 | // target wrapper to INT network |
---|
| 693 | iob_int_wt->p_clk (this->p_clk); |
---|
| 694 | iob_int_wt->p_resetn (this->p_resetn); |
---|
| 695 | iob_int_wt->p_dspin_cmd (signal_int_dspin_cmd_iobx_t); |
---|
| 696 | iob_int_wt->p_dspin_rsp (signal_int_dspin_rsp_iobx_t); |
---|
| 697 | iob_int_wt->p_vci (signal_int_vci_tgt_iobx); |
---|
| 698 | } |
---|
| 699 | } // end constructor |
---|
[450] | 700 | |
---|
[648] | 701 | tmpl(/**/)::~TsarIobCluster() |
---|
| 702 | { |
---|
| 703 | if (p_vci_iob_iox_ini) delete p_vci_iob_iox_ini; |
---|
| 704 | if (p_vci_iob_iox_tgt) delete p_vci_iob_iox_tgt; |
---|
| 705 | if (p_dspin_iob_cmd_out) delete p_dspin_iob_cmd_out; |
---|
| 706 | if (p_dspin_iob_rsp_in) delete p_dspin_iob_rsp_in; |
---|
| 707 | if (iob) delete iob; |
---|
| 708 | if (iob_int_wi) delete iob_int_wi; |
---|
| 709 | if (iob_int_wt) delete iob_int_wt; |
---|
| 710 | if (iob_ram_wi) delete iob_ram_wi; |
---|
[450] | 711 | |
---|
[648] | 712 | for (size_t n = 0 ; n < 32 ; n++) |
---|
| 713 | { |
---|
| 714 | if (p_irq[n]) delete p_irq[n]; |
---|
| 715 | } |
---|
[450] | 716 | |
---|
[648] | 717 | for (size_t p = 0; p < m_procs; p++) |
---|
| 718 | { |
---|
| 719 | delete proc[p]; |
---|
| 720 | delete proc_wi[p]; |
---|
| 721 | } |
---|
[450] | 722 | |
---|
[648] | 723 | delete memc; |
---|
| 724 | delete memc_int_wt; |
---|
| 725 | delete memc_ram_wi; |
---|
| 726 | delete xicu; |
---|
| 727 | delete xicu_int_wt; |
---|
| 728 | delete mdma; |
---|
| 729 | delete mdma_int_wt; |
---|
| 730 | delete mdma_int_wi; |
---|
| 731 | delete int_xbar_cmd_d; |
---|
| 732 | delete int_xbar_rsp_d; |
---|
| 733 | delete int_xbar_m2p_c; |
---|
| 734 | delete int_xbar_p2m_c; |
---|
| 735 | delete int_xbar_clack_c; |
---|
| 736 | delete int_router_cmd; |
---|
| 737 | delete int_router_rsp; |
---|
| 738 | delete xram; |
---|
| 739 | delete xram_ram_wt; |
---|
| 740 | delete ram_router_cmd; |
---|
| 741 | delete ram_router_rsp; |
---|
| 742 | } |
---|
[450] | 743 | |
---|
| 744 | }} |
---|
| 745 | |
---|
| 746 | |
---|
| 747 | // Local Variables: |
---|
| 748 | // tab-width: 3 |
---|
| 749 | // c-basic-offset: 3 |
---|
| 750 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
---|
| 751 | // indent-tabs-mode: nil |
---|
| 752 | // End: |
---|
| 753 | |
---|
| 754 | // vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3 |
---|
| 755 | |
---|