source: branches/reconfiguration/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h

Last change on this file was 923, checked in by cfuguet, 9 years ago

reconf: reuse the UNC transactions' watchdog timer in the CC_TEST

  • When there is a timeout, reply the processor with an error. The r_dcache_cc_test_result register is not longer used. Therefore, the software can locate blackholes in the coherence network with a method similar to the one used for the direct networks.
File size: 36.9 KB
Line 
1/* -*- c++ -*-
2 *
3 * File : vci_cc_vcache_wrapper.h
4 * Copyright (c) UPMC, Lip6, SoC
5 * Authors : Alain GREINER, Yang GAO
6 * Date : 27/11/2011
7 *
8 * SOCLIB_LGPL_HEADER_BEGIN
9 *
10 * This file is part of SoCLib, GNU LGPLv2.1.
11 *
12 * SoCLib is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU Lesser General Public License as published
14 * by the Free Software Foundation; version 2.1 of the License.
15 *
16 * SoCLib is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
19 * Lesser General Public License for more details.
20 *
21 * You should have received a copy of the GNU Lesser General Public
22 * License along with SoCLib; if not, write to the Free Software
23 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
24 * 02110-1301 USA
25 *
26 * SOCLIB_LGPL_HEADER_END
27 *
28 * Maintainers: cesar.fuguet-tortolero@lip6.fr
29 *              alexandre.joannou@lip6.fr
30 */
31
32#ifndef SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER_H
33#define SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER_H
34
35#include <inttypes.h>
36#include <systemc>
37#include "caba_base_module.h"
38#include "multi_write_buffer.h"
39#include "generic_fifo.h"
40#include "generic_tlb.h"
41#include "generic_cache.h"
42#include "vci_initiator.h"
43#include "dspin_interface.h"
44#include "dspin_dhccp_param.h"
45#include "mapping_table.h"
46#include "static_assert.h"
47#include "iss2.h"
48
49#define LLSC_TIMEOUT    10000
50
51namespace soclib {
52namespace caba {
53
54using namespace sc_core;
55
56////////////////////////////////////////////
57template<typename vci_param,
58         size_t   dspin_in_width,
59         size_t   dspin_out_width,
60         typename iss_t>
61class VciCcVCacheWrapper
62////////////////////////////////////////////
63    : public soclib::caba::BaseModule
64{
65
66    typedef typename vci_param::fast_addr_t paddr_t;
67    typedef typename vci_param::trdid_t trdid_t;
68
69    enum icache_fsm_state_e
70    {
71        ICACHE_IDLE,
72        // handling XTN processor requests
73        ICACHE_XTN_TLB_FLUSH,
74        ICACHE_XTN_CACHE_FLUSH,
75        ICACHE_XTN_CACHE_FLUSH_GO,
76        ICACHE_XTN_TLB_INVAL,
77        ICACHE_XTN_CACHE_INVAL_VA,
78        ICACHE_XTN_CACHE_INVAL_PA,
79        ICACHE_XTN_CACHE_INVAL_GO,
80        // handling tlb miss
81        ICACHE_TLB_WAIT,
82        // handling cache miss
83        ICACHE_MISS_SELECT,
84        ICACHE_MISS_CLEAN,
85        ICACHE_MISS_WAIT,
86        ICACHE_MISS_DATA_UPDT,
87        ICACHE_MISS_DIR_UPDT,
88        // handling unc read
89        ICACHE_UNC_WAIT,
90        // handling coherence requests
91        ICACHE_CC_CHECK,
92        ICACHE_CC_UPDT,
93        ICACHE_CC_INVAL,
94    };
95
96    enum dcache_fsm_state_e
97    {
98        DCACHE_IDLE,
99        // handling itlb & dtlb miss
100        DCACHE_TLB_MISS,
101        DCACHE_TLB_PTE1_GET,
102        DCACHE_TLB_PTE1_SELECT,
103        DCACHE_TLB_PTE1_UPDT,
104        DCACHE_TLB_PTE2_GET,
105        DCACHE_TLB_PTE2_SELECT,
106        DCACHE_TLB_PTE2_UPDT,
107        DCACHE_TLB_LR_UPDT,
108        DCACHE_TLB_LR_WAIT,
109        DCACHE_TLB_RETURN,
110        // handling processor XTN requests
111        DCACHE_XTN_SWITCH,
112        DCACHE_XTN_SYNC,
113        DCACHE_XTN_IC_INVAL_VA,
114        DCACHE_XTN_IC_FLUSH,
115        DCACHE_XTN_IC_INVAL_PA,
116        DCACHE_XTN_IC_PADDR_EXT,
117        DCACHE_XTN_IT_INVAL,
118        DCACHE_XTN_DC_FLUSH,
119        DCACHE_XTN_DC_FLUSH_GO,
120        DCACHE_XTN_DC_INVAL_VA,
121        DCACHE_XTN_DC_INVAL_PA,
122        DCACHE_XTN_DC_INVAL_END,
123        DCACHE_XTN_DC_INVAL_GO,
124        DCACHE_XTN_DT_INVAL,
125        DCACHE_XTN_CC_TEST,
126        //handling dirty bit update
127        DCACHE_DIRTY_GET_PTE,
128        DCACHE_DIRTY_WAIT,
129        // handling processor miss requests
130        DCACHE_MISS_SELECT,
131        DCACHE_MISS_CLEAN,
132        DCACHE_MISS_WAIT,
133        DCACHE_MISS_DATA_UPDT,
134        DCACHE_MISS_DIR_UPDT,
135        // handling processor unc, ll and sc requests
136        DCACHE_UNC_WAIT,
137        DCACHE_LL_WAIT,
138        DCACHE_SC_WAIT,
139        // handling coherence requests
140        DCACHE_CC_CHECK,
141        DCACHE_CC_UPDT,
142        DCACHE_CC_INVAL,
143        // handling TLB inval (after a coherence or XTN request)
144        DCACHE_INVAL_TLB_SCAN,
145    };
146
147    enum cmd_fsm_state_e
148    {
149        CMD_IDLE,
150        CMD_INS_MISS,
151        CMD_INS_UNC,
152        CMD_DATA_MISS,
153        CMD_DATA_UNC_READ,
154        CMD_DATA_UNC_WRITE,
155        CMD_DATA_WRITE,
156        CMD_DATA_LL,
157        CMD_DATA_SC,
158        CMD_DATA_CAS,
159    };
160
161    enum rsp_fsm_state_e
162    {
163        RSP_IDLE,
164        RSP_INS_MISS,
165        RSP_INS_UNC,
166        RSP_DATA_MISS,
167        RSP_DATA_UNC,
168        RSP_DATA_LL,
169        RSP_DATA_WRITE,
170    };
171
172    enum cc_receive_fsm_state_e
173    {
174        CC_RECEIVE_IDLE,
175        CC_RECEIVE_BRDCAST_HEADER,
176        CC_RECEIVE_BRDCAST_NLINE,
177        CC_RECEIVE_INS_INVAL_HEADER,
178        CC_RECEIVE_INS_INVAL_NLINE,
179        CC_RECEIVE_INS_UPDT_HEADER,
180        CC_RECEIVE_INS_UPDT_NLINE,
181        CC_RECEIVE_DATA_INVAL_HEADER,
182        CC_RECEIVE_DATA_INVAL_NLINE,
183        CC_RECEIVE_DATA_UPDT_HEADER,
184        CC_RECEIVE_DATA_UPDT_NLINE,
185        CC_RECEIVE_INS_UPDT_DATA,
186        CC_RECEIVE_DATA_UPDT_DATA,
187        CC_RECEIVE_TEST_HEADER,
188        CC_RECEIVE_TEST_SIGNATURE,
189    };
190
191    enum cc_send_fsm_state_e
192    {
193        CC_SEND_IDLE,
194        CC_SEND_CLEANUP_1,
195        CC_SEND_CLEANUP_2,
196        CC_SEND_MULTI_ACK,
197        CC_SEND_TEST_HEADER,
198        CC_SEND_TEST_SIGNATURE,
199    };
200
201    enum cc_test_fsm_state_e
202    {
203        CC_TEST_IDLE,
204        CC_TEST_P2M_REQ,
205        CC_TEST_P2M_WAIT,
206        CC_TEST_ACK_WAIT,
207    };
208
209    /* transaction type, pktid field */
210    enum transaction_type_e
211    {
212        // b3 unused
213        // b2 READ / NOT READ
214        // if READ
215        //  b1 DATA / INS
216        //  b0 UNC / MISS
217        // else
218        //  b1 accÚs table llsc type SW / other
219        //  b2 WRITE/CAS/LL/SC
220        TYPE_DATA_UNC       = 0x0,
221        TYPE_READ_DATA_MISS = 0x1,
222        TYPE_READ_INS_UNC   = 0x2,
223        TYPE_READ_INS_MISS  = 0x3,
224        TYPE_WRITE          = 0x4,
225        TYPE_CAS            = 0x5,
226        TYPE_LL             = 0x6,
227        TYPE_SC             = 0x7
228    };
229
230    /* SC return values */
231    enum sc_status_type_e
232    {
233        SC_SUCCESS = 0x00000000,
234        SC_FAIL    = 0x00000001
235    };
236
237    // cc_send_type
238    typedef enum
239    {
240        CC_TYPE_CLEANUP,
241        CC_TYPE_MULTI_ACK,
242    } cc_send_t;
243
244    // cc_receive_type
245    typedef enum
246    {
247        CC_TYPE_CLACK,
248        CC_TYPE_BRDCAST,
249        CC_TYPE_INVAL,
250        CC_TYPE_UPDT,
251    } cc_receive_t;
252
253    // TLB Mode : ITLB / DTLB / ICACHE / DCACHE
254    enum
255    {
256        INS_TLB_MASK    = 0x8,
257        DATA_TLB_MASK   = 0x4,
258        INS_CACHE_MASK  = 0x2,
259        DATA_CACHE_MASK = 0x1,
260    };
261
262    // Error Type
263    enum mmu_error_type_e
264    {
265        MMU_NONE                      = 0x0000, // None
266        MMU_WRITE_PT1_UNMAPPED        = 0x0001, // Write & Page fault on PT1
267        MMU_WRITE_PT2_UNMAPPED        = 0x0002, // Write & Page fault on PT2
268        MMU_WRITE_PRIVILEGE_VIOLATION = 0x0004, // Write & Protected access in user mode
269        MMU_WRITE_ACCES_VIOLATION     = 0x0008, // Write to non writable page
270        MMU_WRITE_UNDEFINED_XTN       = 0x0020, // Write & undefined external access
271        MMU_WRITE_PT1_ILLEGAL_ACCESS  = 0x0040, // Write & Bus Error accessing PT1
272        MMU_WRITE_PT2_ILLEGAL_ACCESS  = 0x0080, // Write & Bus Error accessing PT2
273        MMU_WRITE_DATA_ILLEGAL_ACCESS = 0x0100, // Write & Bus Error in cache access
274        MMU_READ_PT1_UNMAPPED         = 0x1001, // Read & Page fault on PT1
275        MMU_READ_PT2_UNMAPPED         = 0x1002, // Read & Page fault on PT2
276        MMU_READ_PRIVILEGE_VIOLATION  = 0x1004, // Read & Protected access in user mode
277        MMU_READ_EXEC_VIOLATION       = 0x1010, // Read & Exec access to a non exec page
278        MMU_READ_UNDEFINED_XTN        = 0x1020, // Read & Undefined external access
279        MMU_READ_PT1_ILLEGAL_ACCESS   = 0x1040, // Read & Bus Error accessing PT1
280        MMU_READ_PT2_ILLEGAL_ACCESS   = 0x1080, // Read & Bus Error accessing PT2
281        MMU_READ_DATA_ILLEGAL_ACCESS  = 0x1100, // Read & Bus Error in cache access
282        MMU_WDT_TIMEOUT               = 0x1200, // Watchdog timeout
283    };
284
285    // miss types for data cache
286    enum dcache_miss_type_e
287    {
288        PTE1_MISS,
289        PTE2_MISS,
290        PROC_MISS,
291    };
292
293    // this enumeration type extends the ExternalAcessTypes defined in iss2.h
294    // XTN_CC_TEST:
295    //    When XTN_WRITE: triggers the CC_TEST. The target MEMC is in dreq.wdata
296    //    When XTN_READ: returns the CC_TEST result
297    enum xtn_cop2_extension_e {
298        XTN_WDT_MAX = 26,              // Read & Write the watchdog timer threshold
299        XTN_CC_TEST = 27,              // Trigger coherence network test
300    };
301
302public:
303    sc_in<bool>                                p_clk;
304    sc_in<bool>                                p_resetn;
305    sc_in<bool>                                p_irq[iss_t::n_irq];
306    soclib::caba::VciInitiator<vci_param>      p_vci;
307    soclib::caba::DspinInput<dspin_in_width>   p_dspin_m2p;
308    soclib::caba::DspinOutput<dspin_out_width> p_dspin_p2m;
309    soclib::caba::DspinInput<dspin_in_width>   p_dspin_clack;
310
311private:
312
313    // STRUCTURAL PARAMETERS
314    soclib::common::AddressDecodingTable<uint64_t, bool> m_cacheability_table;
315
316    const size_t   m_srcid;
317    const size_t   m_cc_global_id;
318    const size_t   m_nline_width;
319    const size_t   m_itlb_ways;
320    const size_t   m_itlb_sets;
321    const size_t   m_dtlb_ways;
322    const size_t   m_dtlb_sets;
323    const size_t   m_icache_ways;
324    const size_t   m_icache_sets;
325    const paddr_t  m_icache_yzmask;
326    const size_t   m_icache_words;
327    const size_t   m_dcache_ways;
328    const size_t   m_dcache_sets;
329    const paddr_t  m_dcache_yzmask;
330    const size_t   m_dcache_words;
331    const size_t   m_x_width;
332    const size_t   m_y_width;
333    const size_t   m_proc_id;
334    const uint32_t m_max_frozen_cycles;
335    const size_t   m_paddr_nbits;
336    uint32_t       m_debug_start_cycle;
337    bool           m_debug_ok;
338
339    uint32_t       m_dcache_paddr_ext_reset;
340    uint32_t       m_icache_paddr_ext_reset;
341
342    ////////////////////////////////////////
343    // Communication with processor ISS
344    ////////////////////////////////////////
345    typename iss_t::InstructionRequest  m_ireq;
346    typename iss_t::InstructionResponse m_irsp;
347    typename iss_t::DataRequest         m_dreq;
348    typename iss_t::DataResponse        m_drsp;
349
350    /////////////////////////////////////////////
351    // debug variables
352    /////////////////////////////////////////////
353    bool                                m_debug_previous_i_hit;
354    bool                                m_debug_previous_d_hit;
355    bool                                m_debug_icache_fsm;
356    bool                                m_debug_dcache_fsm;
357    bool                                m_debug_cmd_fsm;
358    uint32_t                            m_previous_status;
359
360
361    ///////////////////////////////
362    // Software visible REGISTERS
363    ///////////////////////////////
364    sc_signal<uint32_t>     r_mmu_ptpr;                 // page table pointer register
365    sc_signal<uint32_t>     r_mmu_mode;                 // mmu mode register
366    sc_signal<uint32_t>     r_mmu_word_lo;              // mmu misc data low
367    sc_signal<uint32_t>     r_mmu_word_hi;              // mmu misc data hight
368    sc_signal<uint32_t>     r_mmu_ibvar;                  // mmu bad instruction address
369    sc_signal<uint32_t>     r_mmu_dbvar;                  // mmu bad data address
370    sc_signal<uint32_t>     r_mmu_ietr;                 // mmu instruction error type
371    sc_signal<uint32_t>     r_mmu_detr;                 // mmu data error type
372    uint32_t                r_mmu_params;                // read-only
373    uint32_t                r_mmu_release;                // read_only
374
375
376    //////////////////////////////
377    // ICACHE FSM REGISTERS
378    //////////////////////////////
379    sc_signal<int>          r_icache_fsm;               // state register
380    sc_signal<int>          r_icache_fsm_save;          // return state for coherence op
381    sc_signal<paddr_t>      r_icache_vci_paddr;          // physical address
382    sc_signal<uint32_t>     r_icache_vaddr_save;        // virtual address from processor
383
384    // icache miss handling
385    sc_signal<size_t>       r_icache_miss_way;            // selected way for cache update
386    sc_signal<size_t>       r_icache_miss_set;            // selected set for cache update
387    sc_signal<size_t>       r_icache_miss_word;            // word index ( cache update)
388    sc_signal<bool>         r_icache_miss_inval;        // coherence request matching a miss
389    sc_signal<bool>         r_icache_miss_clack;        // waiting for a cleanup acknowledge
390
391    // coherence request handling
392    sc_signal<size_t>       r_icache_cc_way;            // selected way for cc update/inval
393    sc_signal<size_t>       r_icache_cc_set;            // selected set for cc update/inval
394    sc_signal<size_t>       r_icache_cc_word;            // word counter for cc update
395    sc_signal<bool>         r_icache_cc_need_write;     // activate the cache for writing
396
397    // coherence clack handling
398    sc_signal<bool>         r_icache_clack_req;         // clack request
399    sc_signal<size_t>       r_icache_clack_way;            // clack way
400    sc_signal<size_t>       r_icache_clack_set;            // clack set
401
402    // icache flush handling
403    sc_signal<size_t>       r_icache_flush_count;        // slot counter used for cache flush
404
405    // communication between ICACHE FSM and VCI_CMD FSM
406    sc_signal<bool>         r_icache_miss_req;           // cached read miss
407    sc_signal<bool>         r_icache_unc_req;            // uncached read miss
408
409    // communication between ICACHE FSM and DCACHE FSM
410    sc_signal<bool>            r_icache_tlb_miss_req;       // (set icache/reset dcache)
411    sc_signal<bool>         r_icache_tlb_rsp_error;      // tlb miss response error
412
413    // Filp-Flop in ICACHE FSM for saving the cleanup victim request
414    sc_signal<bool>         r_icache_cleanup_victim_req;
415    sc_signal<paddr_t>      r_icache_cleanup_victim_nline;
416
417    // communication between ICACHE FSM and CC_SEND FSM
418    sc_signal<bool>         r_icache_cc_send_req;           // ICACHE cc_send request
419    sc_signal<int>          r_icache_cc_send_type;          // ICACHE cc_send request type
420    sc_signal<paddr_t>      r_icache_cc_send_nline;         // ICACHE cc_send nline
421    sc_signal<size_t>       r_icache_cc_send_way;           // ICACHE cc_send way
422    sc_signal<size_t>       r_icache_cc_send_updt_tab_idx;  // ICACHE cc_send update table index
423
424    // Physical address extension for data access
425    sc_signal<uint32_t>     r_icache_paddr_ext;             // CP2 register (if vci_address > 32)
426
427    ///////////////////////////////
428    // DCACHE FSM REGISTERS
429    ///////////////////////////////
430    sc_signal<int>          r_dcache_fsm;               // state register
431    sc_signal<int>          r_dcache_fsm_cc_save;       // return state for coherence op
432    sc_signal<int>          r_dcache_fsm_scan_save;     // return state for tlb scan op
433    // registers written in P0 stage (used in P1 stage)
434    sc_signal<bool>         r_dcache_wbuf_req;          // WBUF must be written in P1 stage
435    sc_signal<bool>         r_dcache_updt_req;          // DCACHE must be updated in P1 stage
436    sc_signal<uint32_t>     r_dcache_save_vaddr;        // virtual address (from proc)
437    sc_signal<uint32_t>     r_dcache_save_wdata;        // write data (from proc)
438    sc_signal<uint32_t>     r_dcache_save_be;           // byte enable (from proc)
439    sc_signal<paddr_t>      r_dcache_save_paddr;        // physical address
440    sc_signal<size_t>       r_dcache_save_cache_way;    // selected way (from dcache)
441    sc_signal<size_t>       r_dcache_save_cache_set;    // selected set (from dcache)
442    sc_signal<size_t>       r_dcache_save_cache_word;    // selected word (from dcache)
443    // registers used by the Dirty bit sub-fsm
444    sc_signal<paddr_t>      r_dcache_dirty_paddr;       // PTE physical address
445    sc_signal<size_t>       r_dcache_dirty_way;            // way to invalidate in dcache
446    sc_signal<size_t>       r_dcache_dirty_set;            // set to invalidate in dcache
447
448    // communication between DCACHE FSM and VCI_CMD FSM
449    sc_signal<paddr_t>      r_dcache_vci_paddr;         // physical address for VCI command
450    sc_signal<uint32_t>     r_dcache_vci_wdata;         // write unc data for VCI command
451    sc_signal<bool>         r_dcache_vci_miss_req;      // read miss request
452    sc_signal<bool>         r_dcache_vci_unc_req;       // uncacheable request (read/write)
453    sc_signal<uint32_t>     r_dcache_vci_unc_be;        // uncacheable byte enable
454    sc_signal<uint32_t>     r_dcache_vci_unc_write;     // uncacheable data write request
455    sc_signal<bool>         r_dcache_vci_cas_req;       // atomic write request CAS
456    sc_signal<uint32_t>     r_dcache_vci_cas_old;       // previous data value for a CAS
457    sc_signal<uint32_t>     r_dcache_vci_cas_new;       // new data value for a CAS
458    sc_signal<bool>         r_dcache_vci_ll_req;        // atomic read request LL
459    sc_signal<bool>         r_dcache_vci_sc_req;        // atomic write request SC
460    sc_signal<uint32_t>     r_dcache_vci_sc_data;       // SC data (command)
461    sc_signal<trdid_t>      r_dcache_vci_wdt_trdid;     // dcache WDT trdid (for debug)
462
463    // register used for XTN inval
464    sc_signal<size_t>       r_dcache_xtn_way;           // selected way (from dcache)
465    sc_signal<size_t>       r_dcache_xtn_set;           // selected set (from dcache)
466
467    // handling dcache miss
468    sc_signal<int>          r_dcache_miss_type;         // depending on the requester
469    sc_signal<size_t>       r_dcache_miss_word;         // word index for cache update
470    sc_signal<size_t>       r_dcache_miss_way;          // selected way for cache update
471    sc_signal<size_t>       r_dcache_miss_set;          // selected set for cache update
472    sc_signal<bool>         r_dcache_miss_inval;        // coherence request matching a miss
473    sc_signal<bool>         r_dcache_miss_clack;        // waiting for a cleanup acknowledge
474
475    // Watchdog timer (WDT) for timeout exception (black-hole detection)
476    sc_signal<uint32_t>     r_dcache_wdt_max;           // wdt triggering value
477    sc_signal<uint32_t>     r_dcache_wdt;               // wdt counter
478    sc_signal<trdid_t>      r_dcache_wdt_timeout;       // timeout counter (for debug)
479
480    // handling coherence requests
481    sc_signal<size_t>       r_dcache_cc_way;            // selected way for cc update/inval
482    sc_signal<size_t>       r_dcache_cc_set;            // selected set for cc update/inval
483    sc_signal<size_t>       r_dcache_cc_word;           // word counter for cc update
484    sc_signal<bool>         r_dcache_cc_need_write;     // activate the cache for writing
485
486    // coherence clack handling
487    sc_signal<bool>         r_dcache_clack_req;         // clack request
488    sc_signal<size_t>       r_dcache_clack_way;         // clack way
489    sc_signal<size_t>       r_dcache_clack_set;         // clack set
490
491    // dcache flush handling
492    sc_signal<size_t>       r_dcache_flush_count;       // slot counter used for cache flush
493
494    // ll response handling
495    sc_signal<size_t>       r_dcache_ll_rsp_count;      // flit counter used for ll rsp
496
497    // used by the TLB miss sub-fsm
498    sc_signal<uint32_t>     r_dcache_tlb_vaddr;         // virtual address for a tlb miss
499    sc_signal<bool>         r_dcache_tlb_ins;           // target tlb (itlb if true)
500    sc_signal<paddr_t>      r_dcache_tlb_paddr;         // physical address of pte
501    sc_signal<uint32_t>     r_dcache_tlb_pte_flags;     // pte1 or first word of pte2
502    sc_signal<uint32_t>     r_dcache_tlb_pte_ppn;       // second word of pte2
503    sc_signal<size_t>       r_dcache_tlb_cache_way;     // selected way in dcache
504    sc_signal<size_t>       r_dcache_tlb_cache_set;     // selected set in dcache
505    sc_signal<size_t>       r_dcache_tlb_cache_word;    // selected word in dcache
506    sc_signal<size_t>       r_dcache_tlb_way;           // selected way in tlb
507    sc_signal<size_t>       r_dcache_tlb_set;           // selected set in tlb
508
509    // ITLB and DTLB invalidation
510    sc_signal<paddr_t>      r_dcache_tlb_inval_line;    // line index
511    sc_signal<size_t>       r_dcache_tlb_inval_set;     // tlb set counter
512
513    // communication between DCACHE FSM and ICACHE FSM
514    sc_signal<bool>         r_dcache_xtn_req;           // xtn request (caused by processor)
515    sc_signal<int>          r_dcache_xtn_opcode;        // xtn request type
516
517    // Filp-Flop in DCACHE FSM for saving the cleanup victim request
518    sc_signal<bool>         r_dcache_cleanup_victim_req;
519    sc_signal<paddr_t>      r_dcache_cleanup_victim_nline;
520
521    // communication between DCACHE FSM and CC_SEND FSM
522    sc_signal<bool>         r_dcache_cc_send_req;           // DCACHE cc_send request
523    sc_signal<int>          r_dcache_cc_send_type;          // DCACHE cc_send request type
524    sc_signal<paddr_t>      r_dcache_cc_send_nline;         // DCACHE cc_send nline
525    sc_signal<size_t>       r_dcache_cc_send_way;           // DCACHE cc_send way
526    sc_signal<size_t>       r_dcache_cc_send_updt_tab_idx;  // DCACHE cc_send update table index
527
528    // dcache directory extension
529    bool                    *r_dcache_in_tlb;               // copy exist in dtlb or itlb
530    bool                    *r_dcache_contains_ptd;         // cache line contains a PTD
531
532    // Physical address extension for data access
533    sc_signal<uint32_t>     r_dcache_paddr_ext;             // CP2 register (if vci_address > 32)
534
535    // communication between DCACHE FSM and CC_TEST FSM
536    sc_signal<bool>         r_dcache_to_cc_test_req;
537    sc_signal<uint32_t>     r_dcache_to_cc_test_dest;
538
539    ///////////////////////////////////
540    // VCI_CMD FSM REGISTERS
541    ///////////////////////////////////
542    sc_signal<int>          r_vci_cmd_fsm;
543    sc_signal<size_t>       r_vci_cmd_min;                  // used for write bursts
544    sc_signal<size_t>       r_vci_cmd_max;                  // used for write bursts
545    sc_signal<size_t>       r_vci_cmd_cpt;                  // used for write bursts
546    sc_signal<bool>         r_vci_cmd_imiss_prio;           // round-robin between imiss & dmiss
547
548    ///////////////////////////////////
549    // VCI_RSP FSM REGISTERS
550    ///////////////////////////////////
551    sc_signal<int>          r_vci_rsp_fsm;
552    sc_signal<size_t>       r_vci_rsp_cpt;
553    sc_signal<bool>         r_vci_rsp_ins_error;
554    sc_signal<bool>         r_vci_rsp_data_error;
555    GenericFifo<uint32_t>   r_vci_rsp_fifo_icache;          // response FIFO to ICACHE FSM
556    GenericFifo<uint32_t>   r_vci_rsp_fifo_dcache;          // response FIFO to DCACHE FSM
557
558    ///////////////////////////////////
559    //  CC_SEND FSM REGISTER
560    ///////////////////////////////////
561    sc_signal<int>          r_cc_send_fsm;                  // state register
562    sc_signal<bool>         r_cc_send_last_client;          // 0 dcache / 1 icache
563
564    ///////////////////////////////////
565    //  CC_RECEIVE FSM REGISTER
566    ///////////////////////////////////
567    sc_signal<int>          r_cc_receive_fsm;               // state register
568    sc_signal<bool>         r_cc_receive_data_ins;          // request to : 0 dcache / 1 icache
569
570    // communication between CC_RECEIVE FSM and ICACHE/DCACHE FSM
571    sc_signal<size_t>       r_cc_receive_word_idx;          // word index
572    GenericFifo<uint32_t>   r_cc_receive_updt_fifo_be;
573    GenericFifo<uint32_t>   r_cc_receive_updt_fifo_data;
574    GenericFifo<bool>       r_cc_receive_updt_fifo_eop;
575
576    // communication between CC_RECEIVE FSM and ICACHE FSM
577    sc_signal<bool>         r_cc_receive_icache_req;          // cc_receive to icache request
578    sc_signal<int>          r_cc_receive_icache_type;         // cc_receive type of request
579    sc_signal<size_t>       r_cc_receive_icache_way;          // cc_receive to icache way
580    sc_signal<size_t>       r_cc_receive_icache_set;          // cc_receive to icache set
581    sc_signal<size_t>       r_cc_receive_icache_updt_tab_idx; // cc_receive update table index
582    sc_signal<paddr_t>      r_cc_receive_icache_nline;        // cache line physical address
583
584    // communication between CC_RECEIVE FSM and DCACHE FSM
585    sc_signal<bool>         r_cc_receive_dcache_req;          // cc_receive to dcache request
586    sc_signal<int>          r_cc_receive_dcache_type;         // cc_receive type of request
587    sc_signal<size_t>       r_cc_receive_dcache_way;          // cc_receive to dcache way
588    sc_signal<size_t>       r_cc_receive_dcache_set;          // cc_receive to dcache set
589    sc_signal<size_t>       r_cc_receive_dcache_updt_tab_idx; // cc_receive update table index
590    sc_signal<paddr_t>      r_cc_receive_dcache_nline;        // cache line physical address
591
592    ///////////////////////////////////
593    //  DSPIN CLACK INTERFACE REGISTER
594    ///////////////////////////////////
595    sc_signal<bool>         r_dspin_clack_req;
596    sc_signal<uint64_t>     r_dspin_clack_flit;
597    sc_signal<bool>         r_dspin_clack_test;
598
599    ///////////////////////////////////
600    //  CC_TEST FSM REGISTER
601    ///////////////////////////////////
602
603    sc_signal<int>          r_cc_test_fsm;
604    sc_signal<bool>         r_cc_test_to_cc_send_req;
605    sc_signal<bool>         r_cc_test_m2p_req;
606    sc_signal<uint64_t>     r_cc_test_m2p_sign;
607    sc_signal<bool>         r_cc_test_clack_req;
608    sc_signal<uint64_t>     r_cc_test_clack_sign;
609
610    //////////////////////////////////////////////////////////////////
611    // processor, write buffer, caches , TLBs
612    //////////////////////////////////////////////////////////////////
613
614    iss_t                     r_iss;
615    MultiWriteBuffer<paddr_t> r_wbuf;
616    GenericCache<paddr_t>     r_icache;
617    GenericCache<paddr_t>     r_dcache;
618    GenericTlb<paddr_t>       r_itlb;
619    GenericTlb<paddr_t>       r_dtlb;
620
621    //////////////////////////////////////////////////////////////////
622    // llsc registration buffer
623    //////////////////////////////////////////////////////////////////
624
625    sc_signal<paddr_t>        r_dcache_llsc_paddr;
626    sc_signal<uint32_t>       r_dcache_llsc_key;
627    sc_signal<uint32_t>       r_dcache_llsc_count;
628    sc_signal<bool>           r_dcache_llsc_valid;
629
630    ////////////////////////////////
631    // Activity counters
632    ////////////////////////////////
633    uint32_t m_cpt_dcache_data_read;        // DCACHE DATA READ
634    uint32_t m_cpt_dcache_data_write;       // DCACHE DATA WRITE
635    uint32_t m_cpt_dcache_dir_read;         // DCACHE DIR READ
636    uint32_t m_cpt_dcache_dir_write;        // DCACHE DIR WRITE
637
638    uint32_t m_cpt_icache_data_read;        // ICACHE DATA READ
639    uint32_t m_cpt_icache_data_write;       // ICACHE DATA WRITE
640    uint32_t m_cpt_icache_dir_read;         // ICACHE DIR READ
641    uint32_t m_cpt_icache_dir_write;        // ICACHE DIR WRITE
642
643    uint32_t m_cpt_frz_cycles;              // number of cycles where the cpu is frozen
644    uint32_t m_cpt_total_cycles;            // total number of cycles
645
646    // Cache activity counters
647    uint32_t m_cpt_data_read;               // total number of read data
648    uint32_t m_cpt_data_write;              // total number of write data
649    uint32_t m_cpt_data_miss;               // number of read miss
650    uint32_t m_cpt_ins_miss;                // number of instruction miss
651    uint32_t m_cpt_unc_read;                // number of read uncached
652    uint32_t m_cpt_write_cached;            // number of cached write
653    uint32_t m_cpt_ins_read;                // number of instruction read
654    uint32_t m_cpt_ins_spc_miss;            // number of speculative instruction miss
655
656    uint32_t m_cost_write_frz;              // number of frozen cycles related to write buffer
657    uint32_t m_cost_data_miss_frz;          // number of frozen cycles related to data miss
658    uint32_t m_cost_unc_read_frz;           // number of frozen cycles related to uncached read
659    uint32_t m_cost_ins_miss_frz;           // number of frozen cycles related to ins miss
660
661    uint32_t m_cpt_imiss_transaction;       // number of VCI instruction miss transactions
662    uint32_t m_cpt_dmiss_transaction;       // number of VCI data miss transactions
663    uint32_t m_cpt_unc_transaction;         // number of VCI uncached read transactions
664    uint32_t m_cpt_write_transaction;       // number of VCI write transactions
665    uint32_t m_cpt_icache_unc_transaction;
666
667    uint32_t m_cost_imiss_transaction;      // cumulated duration for VCI IMISS transactions
668    uint32_t m_cost_dmiss_transaction;      // cumulated duration for VCI DMISS transactions
669    uint32_t m_cost_unc_transaction;        // cumulated duration for VCI UNC transactions
670    uint32_t m_cost_write_transaction;      // cumulated duration for VCI WRITE transactions
671    uint32_t m_cost_icache_unc_transaction; // cumulated duration for VCI IUNC transactions
672    uint32_t m_length_write_transaction;    // cumulated length for VCI WRITE transactions
673
674    // TLB activity counters
675    uint32_t m_cpt_ins_tlb_read;            // number of instruction tlb read
676    uint32_t m_cpt_ins_tlb_miss;            // number of instruction tlb miss
677    uint32_t m_cpt_ins_tlb_update_acc;      // number of instruction tlb update
678    uint32_t m_cpt_ins_tlb_occup_cache;     // number of instruction tlb occupy data cache line
679    uint32_t m_cpt_ins_tlb_hit_dcache;      // number of instruction tlb hit in data cache
680
681    uint32_t m_cpt_data_tlb_read;           // number of data tlb read
682    uint32_t m_cpt_data_tlb_miss;           // number of data tlb miss
683    uint32_t m_cpt_data_tlb_update_acc;     // number of data tlb update
684    uint32_t m_cpt_data_tlb_update_dirty;   // number of data tlb update dirty
685    uint32_t m_cpt_data_tlb_hit_dcache;     // number of data tlb hit in data cache
686    uint32_t m_cpt_data_tlb_occup_cache;    // number of data tlb occupy data cache line
687    uint32_t m_cpt_tlb_occup_dcache;
688
689    uint32_t m_cost_ins_tlb_miss_frz;          // number of frozen cycles related to instruction tlb miss
690    uint32_t m_cost_data_tlb_miss_frz;         // number of frozen cycles related to data tlb miss
691    uint32_t m_cost_ins_tlb_update_acc_frz;    // number of frozen cycles related to instruction tlb update acc
692    uint32_t m_cost_data_tlb_update_acc_frz;   // number of frozen cycles related to data tlb update acc
693    uint32_t m_cost_data_tlb_update_dirty_frz; // number of frozen cycles related to data tlb update dirty
694    uint32_t m_cost_ins_tlb_occup_cache_frz;   // number of frozen cycles related to instruction tlb miss operate in dcache
695    uint32_t m_cost_data_tlb_occup_cache_frz;  // number of frozen cycles related to data tlb miss operate in dcache
696
697    uint32_t m_cpt_itlbmiss_transaction;       // number of itlb miss transactions
698    uint32_t m_cpt_itlb_ll_transaction;        // number of itlb ll acc transactions
699    uint32_t m_cpt_itlb_sc_transaction;        // number of itlb sc acc transactions
700    uint32_t m_cpt_dtlbmiss_transaction;       // number of dtlb miss transactions
701    uint32_t m_cpt_dtlb_ll_transaction;        // number of dtlb ll acc transactions
702    uint32_t m_cpt_dtlb_sc_transaction;        // number of dtlb sc acc transactions
703    uint32_t m_cpt_dtlb_ll_dirty_transaction;  // number of dtlb ll dirty transactions
704    uint32_t m_cpt_dtlb_sc_dirty_transaction;  // number of dtlb sc dirty transactions
705
706    uint32_t m_cost_itlbmiss_transaction;      // cumulated duration for VCI instruction TLB miss transactions
707    uint32_t m_cost_itlb_ll_transaction;       // cumulated duration for VCI instruction TLB ll acc transactions
708    uint32_t m_cost_itlb_sc_transaction;       // cumulated duration for VCI instruction TLB sc acc transactions
709    uint32_t m_cost_dtlbmiss_transaction;      // cumulated duration for VCI data TLB miss transactions
710    uint32_t m_cost_dtlb_ll_transaction;       // cumulated duration for VCI data TLB ll acc transactions
711    uint32_t m_cost_dtlb_sc_transaction;       // cumulated duration for VCI data TLB sc acc transactions
712    uint32_t m_cost_dtlb_ll_dirty_transaction; // cumulated duration for VCI data TLB ll dirty transactions
713    uint32_t m_cost_dtlb_sc_dirty_transaction; // cumulated duration for VCI data TLB sc dirty transactions
714
715    // coherence activity counters
716    uint32_t m_cpt_cc_update_icache;        // number of coherence update instruction commands
717    uint32_t m_cpt_cc_update_dcache;        // number of coherence update data commands
718    uint32_t m_cpt_cc_inval_icache;         // number of coherence inval instruction commands
719    uint32_t m_cpt_cc_inval_dcache;         // number of coherence inval data commands
720    uint32_t m_cpt_cc_broadcast;            // number of coherence broadcast commands
721
722    uint32_t m_cost_updt_data_frz;          // number of frozen cycles related to coherence update data packets
723    uint32_t m_cost_inval_ins_frz;          // number of frozen cycles related to coherence inval instruction packets
724    uint32_t m_cost_inval_data_frz;         // number of frozen cycles related to coherence inval data packets
725    uint32_t m_cost_broadcast_frz;          // number of frozen cycles related to coherence broadcast packets
726
727    uint32_t m_cpt_cc_cleanup_ins;          // number of coherence cleanup packets
728    uint32_t m_cpt_cc_cleanup_data;         // number of coherence cleanup packets
729
730    uint32_t m_cpt_icleanup_transaction;    // number of instruction cleanup transactions
731    uint32_t m_cpt_dcleanup_transaction;    // number of instructinumber of data cleanup transactions
732    uint32_t m_cost_icleanup_transaction;   // cumulated duration for VCI instruction cleanup transactions
733    uint32_t m_cost_dcleanup_transaction;   // cumulated duration for VCI data cleanup transactions
734
735    uint32_t m_cost_ins_tlb_inval_frz;      // number of frozen cycles related to checking ins tlb invalidate
736    uint32_t m_cpt_ins_tlb_inval;           // number of ins tlb invalidate
737
738    uint32_t m_cost_data_tlb_inval_frz;     // number of frozen cycles related to checking data tlb invalidate
739    uint32_t m_cpt_data_tlb_inval;          // number of data tlb invalidate
740
741    // FSM activity counters
742    uint32_t m_cpt_fsm_icache     [64];
743    uint32_t m_cpt_fsm_dcache     [64];
744    uint32_t m_cpt_fsm_cmd        [64];
745    uint32_t m_cpt_fsm_rsp        [64];
746    uint32_t m_cpt_fsm_cc_receive [64];
747    uint32_t m_cpt_fsm_cc_send    [64];
748
749    uint32_t m_cpt_stop_simulation;       // used to stop simulation if frozen
750    bool     m_monitor_ok;                // used to debug cache output
751    uint32_t m_monitor_base;
752    uint32_t m_monitor_length;
753
754protected:
755    SC_HAS_PROCESS(VciCcVCacheWrapper);
756
757public:
758    VciCcVCacheWrapper(
759        sc_module_name                      name,
760        const int                           proc_id,
761        const soclib::common::MappingTable  &mtd,
762        const soclib::common::IntTab        &srcid,
763        const size_t                        cc_global_id,
764        const size_t                        itlb_ways,
765        const size_t                        itlb_sets,
766        const size_t                        dtlb_ways,
767        const size_t                        dtlb_sets,
768        const size_t                        icache_ways,
769        const size_t                        icache_sets,
770        const size_t                        icache_words,
771        const size_t                        dcache_ways,
772        const size_t                        dcache_sets,
773        const size_t                        dcache_words,
774        const size_t                        wbuf_nlines,
775        const size_t                        wbuf_nwords,
776        const size_t                        x_width,
777        const size_t                        y_width,
778        const uint32_t                      max_frozen_cycles,
779        const uint32_t                      debug_start_cycle,
780        const bool                          debug_ok );
781
782    ~VciCcVCacheWrapper();
783
784    void print_cpi();
785    void print_stats();
786    void clear_stats();
787    void print_trace(size_t mode = 0);
788    void cache_monitor(paddr_t addr);
789    void start_monitor(paddr_t,paddr_t);
790    void stop_monitor();
791    inline void iss_set_debug_mask(uint v)
792    {
793        r_iss.set_debug_mask(v);
794    }
795
796    /////////////////////////////////////////////////////////////
797    // Set the m_dcache_paddr_ext_reset attribute
798    //
799    // The r_dcache_paddr_ext register will be initialized after
800    // reset with the m_dcache_paddr_ext_reset value
801    /////////////////////////////////////////////////////////////
802    inline void set_dcache_paddr_ext_reset(uint32_t v)
803    {
804        m_dcache_paddr_ext_reset = v;
805    }
806
807    /////////////////////////////////////////////////////////////
808    // Set the m_icache_paddr_ext_reset attribute
809    //
810    // The r_icache_paddr_ext register will be initialized after
811    // reset with the m_icache_paddr_ext_reset value
812    /////////////////////////////////////////////////////////////
813    inline void set_icache_paddr_ext_reset(uint32_t v)
814    {
815        m_icache_paddr_ext_reset = v;
816    }
817
818private:
819    void transition();
820    void genMoore();
821
822    soclib_static_assert((int)iss_t::SC_ATOMIC == (int)vci_param::STORE_COND_ATOMIC);
823    soclib_static_assert((int)iss_t::SC_NOT_ATOMIC == (int)vci_param::STORE_COND_NOT_ATOMIC);
824};
825
826}}
827
828#endif /* SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER_H */
829
830// Local Variables:
831// tab-width: 4
832// c-basic-offset: 4
833// c-file-offsets:((innamespace . 0)(inline-open . 0))
834// indent-tabs-mode: nil
835// End:
836
837// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
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