source: branches/reconfiguration/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h @ 840

Last change on this file since 840 was 840, checked in by cfuguet, 9 years ago

reconf/vci_cc_vcache_wrapper: Renaming the soclib tag to avoid conflict

  • Modifying the soclib tag of the vci_cc_vcache_wrapper component to avoid a conflict with other versions of this component.
File size: 35.4 KB
Line 
1/* -*- c++ -*-
2 *
3 * File : vci_cc_vcache_wrapper.h
4 * Copyright (c) UPMC, Lip6, SoC
5 * Authors : Alain GREINER, Yang GAO
6 * Date : 27/11/2011
7 *
8 * SOCLIB_LGPL_HEADER_BEGIN
9 *
10 * This file is part of SoCLib, GNU LGPLv2.1.
11 *
12 * SoCLib is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU Lesser General Public License as published
14 * by the Free Software Foundation; version 2.1 of the License.
15 *
16 * SoCLib is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
19 * Lesser General Public License for more details.
20 *
21 * You should have received a copy of the GNU Lesser General Public
22 * License along with SoCLib; if not, write to the Free Software
23 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
24 * 02110-1301 USA
25 *
26 * SOCLIB_LGPL_HEADER_END
27 *
28 * Maintainers: cesar.fuguet-tortolero@lip6.fr
29 *              alexandre.joannou@lip6.fr
30 */
31
32#ifndef SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER_H
33#define SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER_H
34
35#include <inttypes.h>
36#include <systemc>
37#include "caba_base_module.h"
38#include "multi_write_buffer.h"
39#include "generic_fifo.h"
40#include "generic_tlb.h"
41#include "generic_cache.h"
42#include "vci_initiator.h"
43#include "dspin_interface.h"
44#include "dspin_dhccp_param.h"
45#include "mapping_table.h"
46#include "static_assert.h"
47#include "iss2.h"
48
49#define LLSC_TIMEOUT    10000
50
51namespace soclib {
52namespace caba {
53
54using namespace sc_core;
55
56////////////////////////////////////////////
57template<typename vci_param,
58         size_t   dspin_in_width,
59         size_t   dspin_out_width,
60         typename iss_t>
61class VciCcVCacheWrapper
62////////////////////////////////////////////
63    : public soclib::caba::BaseModule
64{
65
66    typedef typename vci_param::fast_addr_t  paddr_t;
67
68    enum icache_fsm_state_e
69    {
70        ICACHE_IDLE,
71        // handling XTN processor requests
72        ICACHE_XTN_TLB_FLUSH,
73        ICACHE_XTN_CACHE_FLUSH,
74        ICACHE_XTN_CACHE_FLUSH_GO,
75        ICACHE_XTN_TLB_INVAL,
76        ICACHE_XTN_CACHE_INVAL_VA,
77        ICACHE_XTN_CACHE_INVAL_PA,
78        ICACHE_XTN_CACHE_INVAL_GO,
79        // handling tlb miss
80        ICACHE_TLB_WAIT,
81        // handling cache miss
82        ICACHE_MISS_SELECT,
83        ICACHE_MISS_CLEAN,
84        ICACHE_MISS_WAIT,
85        ICACHE_MISS_DATA_UPDT,
86        ICACHE_MISS_DIR_UPDT,
87        // handling unc read
88        ICACHE_UNC_WAIT,
89        // handling coherence requests
90        ICACHE_CC_CHECK,
91        ICACHE_CC_UPDT,
92        ICACHE_CC_INVAL,
93    };
94
95    enum dcache_fsm_state_e
96    {
97        DCACHE_IDLE,
98        // handling itlb & dtlb miss
99        DCACHE_TLB_MISS,
100        DCACHE_TLB_PTE1_GET,
101        DCACHE_TLB_PTE1_SELECT,
102        DCACHE_TLB_PTE1_UPDT,
103        DCACHE_TLB_PTE2_GET,
104        DCACHE_TLB_PTE2_SELECT,
105        DCACHE_TLB_PTE2_UPDT,
106        DCACHE_TLB_LR_UPDT,
107        DCACHE_TLB_LR_WAIT,
108        DCACHE_TLB_RETURN,
109        // handling processor XTN requests
110        DCACHE_XTN_SWITCH,
111        DCACHE_XTN_SYNC,
112        DCACHE_XTN_IC_INVAL_VA,
113        DCACHE_XTN_IC_FLUSH,
114        DCACHE_XTN_IC_INVAL_PA,
115        DCACHE_XTN_IC_PADDR_EXT,
116        DCACHE_XTN_IT_INVAL,
117        DCACHE_XTN_DC_FLUSH,
118        DCACHE_XTN_DC_FLUSH_GO,
119        DCACHE_XTN_DC_INVAL_VA,
120        DCACHE_XTN_DC_INVAL_PA,
121        DCACHE_XTN_DC_INVAL_END,
122        DCACHE_XTN_DC_INVAL_GO,
123        DCACHE_XTN_DT_INVAL,
124        //handling dirty bit update
125        DCACHE_DIRTY_GET_PTE,
126        DCACHE_DIRTY_WAIT,
127        // handling processor miss requests
128        DCACHE_MISS_SELECT,
129        DCACHE_MISS_CLEAN,
130        DCACHE_MISS_WAIT,
131        DCACHE_MISS_DATA_UPDT,
132        DCACHE_MISS_DIR_UPDT,
133        // handling processor unc, ll and sc requests
134        DCACHE_UNC_WAIT,
135        DCACHE_LL_WAIT,
136        DCACHE_SC_WAIT,
137        // handling coherence requests
138        DCACHE_CC_CHECK,
139        DCACHE_CC_UPDT,
140        DCACHE_CC_INVAL,
141        // handling TLB inval (after a coherence or XTN request)
142        DCACHE_INVAL_TLB_SCAN,
143    };
144
145    enum cmd_fsm_state_e
146    {
147        CMD_IDLE,
148        CMD_INS_MISS,
149        CMD_INS_UNC,
150        CMD_DATA_MISS,
151        CMD_DATA_UNC_READ,
152        CMD_DATA_UNC_WRITE,
153        CMD_DATA_WRITE,
154        CMD_DATA_LL,
155        CMD_DATA_SC,
156        CMD_DATA_CAS,
157    };
158
159    enum rsp_fsm_state_e
160    {
161        RSP_IDLE,
162        RSP_INS_MISS,
163        RSP_INS_UNC,
164        RSP_DATA_MISS,
165        RSP_DATA_UNC,
166        RSP_DATA_LL,
167        RSP_DATA_WRITE,
168    };
169
170    enum cc_receive_fsm_state_e
171    {
172        CC_RECEIVE_IDLE,
173        CC_RECEIVE_BRDCAST_HEADER,
174        CC_RECEIVE_BRDCAST_NLINE,
175        CC_RECEIVE_INS_INVAL_HEADER,
176        CC_RECEIVE_INS_INVAL_NLINE,
177        CC_RECEIVE_INS_UPDT_HEADER,
178        CC_RECEIVE_INS_UPDT_NLINE,
179        CC_RECEIVE_DATA_INVAL_HEADER,
180        CC_RECEIVE_DATA_INVAL_NLINE,
181        CC_RECEIVE_DATA_UPDT_HEADER,
182        CC_RECEIVE_DATA_UPDT_NLINE,
183        CC_RECEIVE_INS_UPDT_DATA,
184        CC_RECEIVE_DATA_UPDT_DATA,
185    };
186
187    enum cc_send_fsm_state_e
188    {
189        CC_SEND_IDLE,
190        CC_SEND_CLEANUP_1,
191        CC_SEND_CLEANUP_2,
192        CC_SEND_MULTI_ACK,
193    };
194
195    /* transaction type, pktid field */
196    enum transaction_type_e
197    {
198        // b3 unused
199        // b2 READ / NOT READ
200        // if READ
201        //  b1 DATA / INS
202        //  b0 UNC / MISS
203        // else
204        //  b1 accÚs table llsc type SW / other
205        //  b2 WRITE/CAS/LL/SC
206        TYPE_DATA_UNC       = 0x0,
207        TYPE_READ_DATA_MISS = 0x1,
208        TYPE_READ_INS_UNC   = 0x2,
209        TYPE_READ_INS_MISS  = 0x3,
210        TYPE_WRITE          = 0x4,
211        TYPE_CAS            = 0x5,
212        TYPE_LL             = 0x6,
213        TYPE_SC             = 0x7
214    };
215
216    /* SC return values */
217    enum sc_status_type_e
218    {
219        SC_SUCCESS = 0x00000000,
220        SC_FAIL    = 0x00000001
221    };
222
223    // cc_send_type
224    typedef enum
225    {
226        CC_TYPE_CLEANUP,
227        CC_TYPE_MULTI_ACK,
228    } cc_send_t;
229
230    // cc_receive_type
231    typedef enum
232    {
233        CC_TYPE_CLACK,
234        CC_TYPE_BRDCAST,
235        CC_TYPE_INVAL,
236        CC_TYPE_UPDT,
237    } cc_receive_t;
238
239    // TLB Mode : ITLB / DTLB / ICACHE / DCACHE
240    enum
241    {
242        INS_TLB_MASK    = 0x8,
243        DATA_TLB_MASK   = 0x4,
244        INS_CACHE_MASK  = 0x2,
245        DATA_CACHE_MASK = 0x1,
246    };
247
248    // Error Type
249    enum mmu_error_type_e
250    {
251        MMU_NONE                      = 0x0000, // None
252        MMU_WRITE_PT1_UNMAPPED        = 0x0001, // Write & Page fault on PT1
253        MMU_WRITE_PT2_UNMAPPED        = 0x0002, // Write & Page fault on PT2
254        MMU_WRITE_PRIVILEGE_VIOLATION = 0x0004, // Write & Protected access in user mode
255        MMU_WRITE_ACCES_VIOLATION     = 0x0008, // Write to non writable page
256        MMU_WRITE_UNDEFINED_XTN       = 0x0020, // Write & undefined external access
257        MMU_WRITE_PT1_ILLEGAL_ACCESS  = 0x0040, // Write & Bus Error accessing PT1
258        MMU_WRITE_PT2_ILLEGAL_ACCESS  = 0x0080, // Write & Bus Error accessing PT2
259        MMU_WRITE_DATA_ILLEGAL_ACCESS = 0x0100, // Write & Bus Error in cache access
260        MMU_READ_PT1_UNMAPPED         = 0x1001, // Read & Page fault on PT1
261        MMU_READ_PT2_UNMAPPED         = 0x1002, // Read & Page fault on PT2
262        MMU_READ_PRIVILEGE_VIOLATION  = 0x1004, // Read & Protected access in user mode
263        MMU_READ_EXEC_VIOLATION       = 0x1010, // Read & Exec access to a non exec page
264        MMU_READ_UNDEFINED_XTN        = 0x1020, // Read & Undefined external access
265        MMU_READ_PT1_ILLEGAL_ACCESS   = 0x1040, // Read & Bus Error accessing PT1
266        MMU_READ_PT2_ILLEGAL_ACCESS   = 0x1080, // Read & Bus Error accessing PT2
267        MMU_READ_DATA_ILLEGAL_ACCESS  = 0x1100, // Read & Bus Error in cache access
268    };
269
270    // miss types for data cache
271    enum dcache_miss_type_e
272    {
273        PTE1_MISS,
274        PTE2_MISS,
275        PROC_MISS,
276    };
277
278//    enum transaction_type_d_e
279//    {
280//        // b0 : 1 if cached
281//        // b1 : 1 if instruction
282//        TYPE_DATA_UNC     = 0x0,
283//        TYPE_DATA_MISS    = 0x1,
284//        TYPE_INS_UNC      = 0x2,
285//        TYPE_INS_MISS     = 0x3,
286//    };
287
288public:
289    sc_in<bool>                                p_clk;
290    sc_in<bool>                                p_resetn;
291    sc_in<bool>                                p_irq[iss_t::n_irq];
292    soclib::caba::VciInitiator<vci_param>      p_vci;
293    soclib::caba::DspinInput<dspin_in_width>   p_dspin_m2p;
294    soclib::caba::DspinOutput<dspin_out_width> p_dspin_p2m;
295    soclib::caba::DspinInput<dspin_in_width>   p_dspin_clack;
296
297private:
298
299    // STRUCTURAL PARAMETERS
300    soclib::common::AddressDecodingTable<uint64_t, bool> m_cacheability_table;
301
302    const size_t   m_srcid;
303    const size_t   m_cc_global_id;
304    const size_t   m_nline_width;
305    const size_t   m_itlb_ways;
306    const size_t   m_itlb_sets;
307    const size_t   m_dtlb_ways;
308    const size_t   m_dtlb_sets;
309    const size_t   m_icache_ways;
310    const size_t   m_icache_sets;
311    const paddr_t  m_icache_yzmask;
312    const size_t   m_icache_words;
313    const size_t   m_dcache_ways;
314    const size_t   m_dcache_sets;
315    const paddr_t  m_dcache_yzmask;
316    const size_t   m_dcache_words;
317    const size_t   m_x_width;
318    const size_t   m_y_width;
319    const size_t   m_proc_id;
320    const uint32_t m_max_frozen_cycles;
321    const size_t   m_paddr_nbits;
322    uint32_t       m_debug_start_cycle;
323    bool           m_debug_ok;
324
325    uint32_t       m_dcache_paddr_ext_reset;
326    uint32_t       m_icache_paddr_ext_reset;
327
328    ////////////////////////////////////////
329    // Communication with processor ISS
330    ////////////////////////////////////////
331    typename iss_t::InstructionRequest  m_ireq;
332    typename iss_t::InstructionResponse m_irsp;
333    typename iss_t::DataRequest         m_dreq;
334    typename iss_t::DataResponse        m_drsp;
335
336    /////////////////////////////////////////////
337    // debug variables
338    /////////////////////////////////////////////
339    bool                                m_debug_previous_i_hit;
340    bool                                m_debug_previous_d_hit;
341    bool                                m_debug_icache_fsm;
342    bool                                m_debug_dcache_fsm;
343    bool                                m_debug_cmd_fsm;
344    uint32_t                            m_previous_status;
345
346
347    ///////////////////////////////
348    // Software visible REGISTERS
349    ///////////////////////////////
350    sc_signal<uint32_t>     r_mmu_ptpr;                 // page table pointer register
351    sc_signal<uint32_t>     r_mmu_mode;                 // mmu mode register
352    sc_signal<uint32_t>     r_mmu_word_lo;              // mmu misc data low
353    sc_signal<uint32_t>     r_mmu_word_hi;              // mmu misc data hight
354    sc_signal<uint32_t>     r_mmu_ibvar;                  // mmu bad instruction address
355    sc_signal<uint32_t>     r_mmu_dbvar;                  // mmu bad data address
356    sc_signal<uint32_t>     r_mmu_ietr;                 // mmu instruction error type
357    sc_signal<uint32_t>     r_mmu_detr;                 // mmu data error type
358    uint32_t                r_mmu_params;                // read-only
359    uint32_t                r_mmu_release;                // read_only
360
361
362    //////////////////////////////
363    // ICACHE FSM REGISTERS
364    //////////////////////////////
365    sc_signal<int>          r_icache_fsm;               // state register
366    sc_signal<int>          r_icache_fsm_save;          // return state for coherence op
367    sc_signal<paddr_t>      r_icache_vci_paddr;          // physical address
368    sc_signal<uint32_t>     r_icache_vaddr_save;        // virtual address from processor
369
370    // icache miss handling
371    sc_signal<size_t>       r_icache_miss_way;            // selected way for cache update
372    sc_signal<size_t>       r_icache_miss_set;            // selected set for cache update
373    sc_signal<size_t>       r_icache_miss_word;            // word index ( cache update)
374    sc_signal<bool>         r_icache_miss_inval;        // coherence request matching a miss
375    sc_signal<bool>         r_icache_miss_clack;        // waiting for a cleanup acknowledge
376
377    // coherence request handling
378    sc_signal<size_t>       r_icache_cc_way;            // selected way for cc update/inval
379    sc_signal<size_t>       r_icache_cc_set;            // selected set for cc update/inval
380    sc_signal<size_t>       r_icache_cc_word;            // word counter for cc update
381    sc_signal<bool>         r_icache_cc_need_write;     // activate the cache for writing
382
383    // coherence clack handling
384    sc_signal<bool>         r_icache_clack_req;         // clack request
385    sc_signal<size_t>       r_icache_clack_way;            // clack way
386    sc_signal<size_t>       r_icache_clack_set;            // clack set
387
388    // icache flush handling
389    sc_signal<size_t>       r_icache_flush_count;        // slot counter used for cache flush
390
391    // communication between ICACHE FSM and VCI_CMD FSM
392    sc_signal<bool>         r_icache_miss_req;           // cached read miss
393    sc_signal<bool>         r_icache_unc_req;            // uncached read miss
394
395    // communication between ICACHE FSM and DCACHE FSM
396    sc_signal<bool>            r_icache_tlb_miss_req;       // (set icache/reset dcache)
397    sc_signal<bool>         r_icache_tlb_rsp_error;      // tlb miss response error
398
399    // Filp-Flop in ICACHE FSM for saving the cleanup victim request
400    sc_signal<bool>         r_icache_cleanup_victim_req;
401    sc_signal<paddr_t>      r_icache_cleanup_victim_nline;
402
403    // communication between ICACHE FSM and CC_SEND FSM
404    sc_signal<bool>         r_icache_cc_send_req;           // ICACHE cc_send request
405    sc_signal<int>          r_icache_cc_send_type;          // ICACHE cc_send request type
406    sc_signal<paddr_t>      r_icache_cc_send_nline;         // ICACHE cc_send nline
407    sc_signal<size_t>       r_icache_cc_send_way;           // ICACHE cc_send way
408    sc_signal<size_t>       r_icache_cc_send_updt_tab_idx;  // ICACHE cc_send update table index
409
410    // Physical address extension for data access
411    sc_signal<uint32_t>     r_icache_paddr_ext;             // CP2 register (if vci_address > 32)
412
413    ///////////////////////////////
414    // DCACHE FSM REGISTERS
415    ///////////////////////////////
416    sc_signal<int>          r_dcache_fsm;               // state register
417    sc_signal<int>          r_dcache_fsm_cc_save;       // return state for coherence op
418    sc_signal<int>          r_dcache_fsm_scan_save;     // return state for tlb scan op
419    // registers written in P0 stage (used in P1 stage)
420    sc_signal<bool>         r_dcache_wbuf_req;          // WBUF must be written in P1 stage
421    sc_signal<bool>         r_dcache_updt_req;          // DCACHE must be updated in P1 stage
422    sc_signal<uint32_t>     r_dcache_save_vaddr;        // virtual address (from proc)
423    sc_signal<uint32_t>     r_dcache_save_wdata;        // write data (from proc)
424    sc_signal<uint32_t>     r_dcache_save_be;           // byte enable (from proc)
425    sc_signal<paddr_t>      r_dcache_save_paddr;        // physical address
426    sc_signal<size_t>       r_dcache_save_cache_way;    // selected way (from dcache)
427    sc_signal<size_t>       r_dcache_save_cache_set;    // selected set (from dcache)
428    sc_signal<size_t>       r_dcache_save_cache_word;    // selected word (from dcache)
429    // registers used by the Dirty bit sub-fsm
430    sc_signal<paddr_t>      r_dcache_dirty_paddr;       // PTE physical address
431    sc_signal<size_t>       r_dcache_dirty_way;            // way to invalidate in dcache
432    sc_signal<size_t>       r_dcache_dirty_set;            // set to invalidate in dcache
433
434    // communication between DCACHE FSM and VCI_CMD FSM
435    sc_signal<paddr_t>      r_dcache_vci_paddr;            // physical address for VCI command
436    sc_signal<uint32_t>     r_dcache_vci_wdata;            // write unc data for VCI command
437    sc_signal<bool>         r_dcache_vci_miss_req;      // read miss request
438    sc_signal<bool>         r_dcache_vci_unc_req;       // uncacheable request (read/write)
439    sc_signal<uint32_t>     r_dcache_vci_unc_be;        // uncacheable byte enable
440    sc_signal<uint32_t>     r_dcache_vci_unc_write;     // uncacheable data write request
441    sc_signal<bool>         r_dcache_vci_cas_req;       // atomic write request CAS
442    sc_signal<uint32_t>     r_dcache_vci_cas_old;       // previous data value for a CAS
443    sc_signal<uint32_t>     r_dcache_vci_cas_new;       // new data value for a CAS
444    sc_signal<bool>         r_dcache_vci_ll_req;        // atomic read request LL
445    sc_signal<bool>         r_dcache_vci_sc_req;        // atomic write request SC
446    sc_signal<uint32_t>     r_dcache_vci_sc_data;       // SC data (command)
447
448    // register used for XTN inval
449    sc_signal<size_t>       r_dcache_xtn_way;            // selected way (from dcache)
450    sc_signal<size_t>       r_dcache_xtn_set;            // selected set (from dcache)
451
452    // handling dcache miss
453    sc_signal<int>            r_dcache_miss_type;            // depending on the requester
454    sc_signal<size_t>       r_dcache_miss_word;            // word index for cache update
455    sc_signal<size_t>       r_dcache_miss_way;            // selected way for cache update
456    sc_signal<size_t>       r_dcache_miss_set;            // selected set for cache update
457    sc_signal<bool>         r_dcache_miss_inval;        // coherence request matching a miss
458    sc_signal<bool>         r_dcache_miss_clack;        // waiting for a cleanup acknowledge
459
460    // handling coherence requests
461    sc_signal<size_t>       r_dcache_cc_way;            // selected way for cc update/inval
462    sc_signal<size_t>       r_dcache_cc_set;            // selected set for cc update/inval
463    sc_signal<size_t>       r_dcache_cc_word;            // word counter for cc update
464    sc_signal<bool>         r_dcache_cc_need_write;     // activate the cache for writing
465
466    // coherence clack handling
467    sc_signal<bool>         r_dcache_clack_req;         // clack request
468    sc_signal<size_t>       r_dcache_clack_way;            // clack way
469    sc_signal<size_t>       r_dcache_clack_set;            // clack set
470
471    // dcache flush handling
472    sc_signal<size_t>       r_dcache_flush_count;        // slot counter used for cache flush
473
474    // ll response handling
475    sc_signal<size_t>       r_dcache_ll_rsp_count;        // flit counter used for ll rsp
476
477    // used by the TLB miss sub-fsm
478    sc_signal<uint32_t>     r_dcache_tlb_vaddr;            // virtual address for a tlb miss
479    sc_signal<bool>         r_dcache_tlb_ins;            // target tlb (itlb if true)
480    sc_signal<paddr_t>      r_dcache_tlb_paddr;            // physical address of pte
481    sc_signal<uint32_t>     r_dcache_tlb_pte_flags;        // pte1 or first word of pte2
482    sc_signal<uint32_t>     r_dcache_tlb_pte_ppn;        // second word of pte2
483    sc_signal<size_t>       r_dcache_tlb_cache_way;        // selected way in dcache
484    sc_signal<size_t>       r_dcache_tlb_cache_set;        // selected set in dcache
485    sc_signal<size_t>       r_dcache_tlb_cache_word;    // selected word in dcache
486    sc_signal<size_t>       r_dcache_tlb_way;            // selected way in tlb
487    sc_signal<size_t>       r_dcache_tlb_set;            // selected set in tlb
488
489    // ITLB and DTLB invalidation
490    sc_signal<paddr_t>      r_dcache_tlb_inval_line;    // line index
491    sc_signal<size_t>       r_dcache_tlb_inval_set;     // tlb set counter
492
493    // communication between DCACHE FSM and ICACHE FSM
494    sc_signal<bool>         r_dcache_xtn_req;           // xtn request (caused by processor)
495    sc_signal<int>          r_dcache_xtn_opcode;        // xtn request type
496
497    // Filp-Flop in DCACHE FSM for saving the cleanup victim request
498    sc_signal<bool>         r_dcache_cleanup_victim_req;
499    sc_signal<paddr_t>      r_dcache_cleanup_victim_nline;
500
501    // communication between DCACHE FSM and CC_SEND FSM
502    sc_signal<bool>         r_dcache_cc_send_req;           // DCACHE cc_send request
503    sc_signal<int>          r_dcache_cc_send_type;          // DCACHE cc_send request type
504    sc_signal<paddr_t>      r_dcache_cc_send_nline;         // DCACHE cc_send nline
505    sc_signal<size_t>       r_dcache_cc_send_way;           // DCACHE cc_send way
506    sc_signal<size_t>       r_dcache_cc_send_updt_tab_idx;  // DCACHE cc_send update table index
507
508    // dcache directory extension
509    bool                    *r_dcache_in_tlb;               // copy exist in dtlb or itlb
510    bool                    *r_dcache_contains_ptd;         // cache line contains a PTD
511
512    // Physical address extension for data access
513    sc_signal<uint32_t>     r_dcache_paddr_ext;             // CP2 register (if vci_address > 32)
514
515    ///////////////////////////////////
516    // VCI_CMD FSM REGISTERS
517    ///////////////////////////////////
518    sc_signal<int>          r_vci_cmd_fsm;
519    sc_signal<size_t>       r_vci_cmd_min;                  // used for write bursts
520    sc_signal<size_t>       r_vci_cmd_max;                  // used for write bursts
521    sc_signal<size_t>       r_vci_cmd_cpt;                    // used for write bursts
522    sc_signal<bool>         r_vci_cmd_imiss_prio;            // round-robin between imiss & dmiss
523
524    ///////////////////////////////////
525    // VCI_RSP FSM REGISTERS
526    ///////////////////////////////////
527    sc_signal<int>          r_vci_rsp_fsm;
528    sc_signal<size_t>       r_vci_rsp_cpt;
529    sc_signal<bool>         r_vci_rsp_ins_error;
530    sc_signal<bool>         r_vci_rsp_data_error;
531    GenericFifo<uint32_t>   r_vci_rsp_fifo_icache;            // response FIFO to ICACHE FSM
532    GenericFifo<uint32_t>   r_vci_rsp_fifo_dcache;            // response FIFO to DCACHE FSM
533
534    ///////////////////////////////////
535    //  CC_SEND FSM REGISTER
536    ///////////////////////////////////
537    sc_signal<int>          r_cc_send_fsm;                  // state register
538    sc_signal<bool>         r_cc_send_last_client;          // 0 dcache / 1 icache
539
540    ///////////////////////////////////
541    //  CC_RECEIVE FSM REGISTER
542    ///////////////////////////////////
543    sc_signal<int>          r_cc_receive_fsm;               // state register
544    sc_signal<bool>         r_cc_receive_data_ins;          // request to : 0 dcache / 1 icache
545
546    // communication between CC_RECEIVE FSM and ICACHE/DCACHE FSM
547    sc_signal<size_t>       r_cc_receive_word_idx;          // word index
548    GenericFifo<uint32_t>   r_cc_receive_updt_fifo_be;
549    GenericFifo<uint32_t>   r_cc_receive_updt_fifo_data;
550    GenericFifo<bool>       r_cc_receive_updt_fifo_eop;
551
552    // communication between CC_RECEIVE FSM and ICACHE FSM
553    sc_signal<bool>         r_cc_receive_icache_req;        // cc_receive to icache request
554    sc_signal<int>          r_cc_receive_icache_type;       // cc_receive type of request
555    sc_signal<size_t>       r_cc_receive_icache_way;        // cc_receive to icache way
556    sc_signal<size_t>       r_cc_receive_icache_set;        // cc_receive to icache set
557    sc_signal<size_t>       r_cc_receive_icache_updt_tab_idx;  // cc_receive update table index
558    sc_signal<paddr_t>      r_cc_receive_icache_nline;        // cache line physical address
559
560    // communication between CC_RECEIVE FSM and DCACHE FSM
561    sc_signal<bool>         r_cc_receive_dcache_req;        // cc_receive to dcache request
562    sc_signal<int>          r_cc_receive_dcache_type;       // cc_receive type of request
563    sc_signal<size_t>       r_cc_receive_dcache_way;        // cc_receive to dcache way
564    sc_signal<size_t>       r_cc_receive_dcache_set;        // cc_receive to dcache set
565    sc_signal<size_t>       r_cc_receive_dcache_updt_tab_idx;  // cc_receive update table index
566    sc_signal<paddr_t>      r_cc_receive_dcache_nline;        // cache line physical address
567
568    ///////////////////////////////////
569    //  DSPIN CLACK INTERFACE REGISTER
570    ///////////////////////////////////
571    sc_signal<bool>         r_dspin_clack_req;
572    sc_signal<uint64_t>     r_dspin_clack_flit;
573
574    //////////////////////////////////////////////////////////////////
575    // processor, write buffer, caches , TLBs
576    //////////////////////////////////////////////////////////////////
577
578    iss_t                     r_iss;
579    MultiWriteBuffer<paddr_t> r_wbuf;
580    GenericCache<paddr_t>     r_icache;
581    GenericCache<paddr_t>     r_dcache;
582    GenericTlb<paddr_t>       r_itlb;
583    GenericTlb<paddr_t>       r_dtlb;
584
585    //////////////////////////////////////////////////////////////////
586    // llsc registration buffer
587    //////////////////////////////////////////////////////////////////
588
589    sc_signal<paddr_t>        r_dcache_llsc_paddr;
590    sc_signal<uint32_t>       r_dcache_llsc_key;
591    sc_signal<uint32_t>       r_dcache_llsc_count;
592    sc_signal<bool>           r_dcache_llsc_valid;
593
594    ////////////////////////////////
595    // Activity counters
596    ////////////////////////////////
597    uint32_t m_cpt_dcache_data_read;        // DCACHE DATA READ
598    uint32_t m_cpt_dcache_data_write;       // DCACHE DATA WRITE
599    uint32_t m_cpt_dcache_dir_read;         // DCACHE DIR READ
600    uint32_t m_cpt_dcache_dir_write;        // DCACHE DIR WRITE
601
602    uint32_t m_cpt_icache_data_read;        // ICACHE DATA READ
603    uint32_t m_cpt_icache_data_write;       // ICACHE DATA WRITE
604    uint32_t m_cpt_icache_dir_read;         // ICACHE DIR READ
605    uint32_t m_cpt_icache_dir_write;        // ICACHE DIR WRITE
606
607    uint32_t m_cpt_frz_cycles;              // number of cycles where the cpu is frozen
608    uint32_t m_cpt_total_cycles;            // total number of cycles
609
610    // Cache activity counters
611    uint32_t m_cpt_data_read;               // total number of read data
612    uint32_t m_cpt_data_write;              // total number of write data
613    uint32_t m_cpt_data_miss;               // number of read miss
614    uint32_t m_cpt_ins_miss;                // number of instruction miss
615    uint32_t m_cpt_unc_read;                // number of read uncached
616    uint32_t m_cpt_write_cached;            // number of cached write
617    uint32_t m_cpt_ins_read;                // number of instruction read
618    uint32_t m_cpt_ins_spc_miss;            // number of speculative instruction miss
619
620    uint32_t m_cost_write_frz;              // number of frozen cycles related to write buffer
621    uint32_t m_cost_data_miss_frz;          // number of frozen cycles related to data miss
622    uint32_t m_cost_unc_read_frz;           // number of frozen cycles related to uncached read
623    uint32_t m_cost_ins_miss_frz;           // number of frozen cycles related to ins miss
624
625    uint32_t m_cpt_imiss_transaction;       // number of VCI instruction miss transactions
626    uint32_t m_cpt_dmiss_transaction;       // number of VCI data miss transactions
627    uint32_t m_cpt_unc_transaction;         // number of VCI uncached read transactions
628    uint32_t m_cpt_write_transaction;       // number of VCI write transactions
629    uint32_t m_cpt_icache_unc_transaction;
630
631    uint32_t m_cost_imiss_transaction;      // cumulated duration for VCI IMISS transactions
632    uint32_t m_cost_dmiss_transaction;      // cumulated duration for VCI DMISS transactions
633    uint32_t m_cost_unc_transaction;        // cumulated duration for VCI UNC transactions
634    uint32_t m_cost_write_transaction;      // cumulated duration for VCI WRITE transactions
635    uint32_t m_cost_icache_unc_transaction; // cumulated duration for VCI IUNC transactions
636    uint32_t m_length_write_transaction;    // cumulated length for VCI WRITE transactions
637
638    // TLB activity counters
639    uint32_t m_cpt_ins_tlb_read;            // number of instruction tlb read
640    uint32_t m_cpt_ins_tlb_miss;            // number of instruction tlb miss
641    uint32_t m_cpt_ins_tlb_update_acc;      // number of instruction tlb update
642    uint32_t m_cpt_ins_tlb_occup_cache;     // number of instruction tlb occupy data cache line
643    uint32_t m_cpt_ins_tlb_hit_dcache;      // number of instruction tlb hit in data cache
644
645    uint32_t m_cpt_data_tlb_read;           // number of data tlb read
646    uint32_t m_cpt_data_tlb_miss;           // number of data tlb miss
647    uint32_t m_cpt_data_tlb_update_acc;     // number of data tlb update
648    uint32_t m_cpt_data_tlb_update_dirty;   // number of data tlb update dirty
649    uint32_t m_cpt_data_tlb_hit_dcache;     // number of data tlb hit in data cache
650    uint32_t m_cpt_data_tlb_occup_cache;    // number of data tlb occupy data cache line
651    uint32_t m_cpt_tlb_occup_dcache;
652
653    uint32_t m_cost_ins_tlb_miss_frz;          // number of frozen cycles related to instruction tlb miss
654    uint32_t m_cost_data_tlb_miss_frz;         // number of frozen cycles related to data tlb miss
655    uint32_t m_cost_ins_tlb_update_acc_frz;    // number of frozen cycles related to instruction tlb update acc
656    uint32_t m_cost_data_tlb_update_acc_frz;   // number of frozen cycles related to data tlb update acc
657    uint32_t m_cost_data_tlb_update_dirty_frz; // number of frozen cycles related to data tlb update dirty
658    uint32_t m_cost_ins_tlb_occup_cache_frz;   // number of frozen cycles related to instruction tlb miss operate in dcache
659    uint32_t m_cost_data_tlb_occup_cache_frz;  // number of frozen cycles related to data tlb miss operate in dcache
660
661    uint32_t m_cpt_itlbmiss_transaction;       // number of itlb miss transactions
662    uint32_t m_cpt_itlb_ll_transaction;        // number of itlb ll acc transactions
663    uint32_t m_cpt_itlb_sc_transaction;        // number of itlb sc acc transactions
664    uint32_t m_cpt_dtlbmiss_transaction;       // number of dtlb miss transactions
665    uint32_t m_cpt_dtlb_ll_transaction;        // number of dtlb ll acc transactions
666    uint32_t m_cpt_dtlb_sc_transaction;        // number of dtlb sc acc transactions
667    uint32_t m_cpt_dtlb_ll_dirty_transaction;  // number of dtlb ll dirty transactions
668    uint32_t m_cpt_dtlb_sc_dirty_transaction;  // number of dtlb sc dirty transactions
669
670    uint32_t m_cost_itlbmiss_transaction;      // cumulated duration for VCI instruction TLB miss transactions
671    uint32_t m_cost_itlb_ll_transaction;       // cumulated duration for VCI instruction TLB ll acc transactions
672    uint32_t m_cost_itlb_sc_transaction;       // cumulated duration for VCI instruction TLB sc acc transactions
673    uint32_t m_cost_dtlbmiss_transaction;      // cumulated duration for VCI data TLB miss transactions
674    uint32_t m_cost_dtlb_ll_transaction;       // cumulated duration for VCI data TLB ll acc transactions
675    uint32_t m_cost_dtlb_sc_transaction;       // cumulated duration for VCI data TLB sc acc transactions
676    uint32_t m_cost_dtlb_ll_dirty_transaction; // cumulated duration for VCI data TLB ll dirty transactions
677    uint32_t m_cost_dtlb_sc_dirty_transaction; // cumulated duration for VCI data TLB sc dirty transactions
678
679    // coherence activity counters
680    uint32_t m_cpt_cc_update_icache;        // number of coherence update instruction commands
681    uint32_t m_cpt_cc_update_dcache;        // number of coherence update data commands
682    uint32_t m_cpt_cc_inval_icache;         // number of coherence inval instruction commands
683    uint32_t m_cpt_cc_inval_dcache;         // number of coherence inval data commands
684    uint32_t m_cpt_cc_broadcast;            // number of coherence broadcast commands
685
686    uint32_t m_cost_updt_data_frz;          // number of frozen cycles related to coherence update data packets
687    uint32_t m_cost_inval_ins_frz;          // number of frozen cycles related to coherence inval instruction packets
688    uint32_t m_cost_inval_data_frz;         // number of frozen cycles related to coherence inval data packets
689    uint32_t m_cost_broadcast_frz;          // number of frozen cycles related to coherence broadcast packets
690
691    uint32_t m_cpt_cc_cleanup_ins;          // number of coherence cleanup packets
692    uint32_t m_cpt_cc_cleanup_data;         // number of coherence cleanup packets
693
694    uint32_t m_cpt_icleanup_transaction;    // number of instruction cleanup transactions
695    uint32_t m_cpt_dcleanup_transaction;    // number of instructinumber of data cleanup transactions
696    uint32_t m_cost_icleanup_transaction;   // cumulated duration for VCI instruction cleanup transactions
697    uint32_t m_cost_dcleanup_transaction;   // cumulated duration for VCI data cleanup transactions
698
699    uint32_t m_cost_ins_tlb_inval_frz;      // number of frozen cycles related to checking ins tlb invalidate
700    uint32_t m_cpt_ins_tlb_inval;           // number of ins tlb invalidate
701
702    uint32_t m_cost_data_tlb_inval_frz;     // number of frozen cycles related to checking data tlb invalidate
703    uint32_t m_cpt_data_tlb_inval;          // number of data tlb invalidate
704
705    // FSM activity counters
706    uint32_t m_cpt_fsm_icache     [64];
707    uint32_t m_cpt_fsm_dcache     [64];
708    uint32_t m_cpt_fsm_cmd        [64];
709    uint32_t m_cpt_fsm_rsp        [64];
710    uint32_t m_cpt_fsm_cc_receive [64];
711    uint32_t m_cpt_fsm_cc_send    [64];
712
713    uint32_t m_cpt_stop_simulation;       // used to stop simulation if frozen
714    bool     m_monitor_ok;                // used to debug cache output
715    uint32_t m_monitor_base;
716    uint32_t m_monitor_length;
717
718protected:
719    SC_HAS_PROCESS(VciCcVCacheWrapper);
720
721public:
722    VciCcVCacheWrapper(
723        sc_module_name                      name,
724        const int                           proc_id,
725        const soclib::common::MappingTable  &mtd,
726        const soclib::common::IntTab        &srcid,
727        const size_t                        cc_global_id,
728        const size_t                        itlb_ways,
729        const size_t                        itlb_sets,
730        const size_t                        dtlb_ways,
731        const size_t                        dtlb_sets,
732        const size_t                        icache_ways,
733        const size_t                        icache_sets,
734        const size_t                        icache_words,
735        const size_t                        dcache_ways,
736        const size_t                        dcache_sets,
737        const size_t                        dcache_words,
738        const size_t                        wbuf_nlines,
739        const size_t                        wbuf_nwords,
740        const size_t                        x_width,
741        const size_t                        y_width,
742        const uint32_t                      max_frozen_cycles,
743        const uint32_t                      debug_start_cycle,
744        const bool                          debug_ok );
745
746    ~VciCcVCacheWrapper();
747
748    void print_cpi();
749    void print_stats();
750    void clear_stats();
751    void print_trace(size_t mode = 0);
752    void cache_monitor(paddr_t addr);
753    void start_monitor(paddr_t,paddr_t);
754    void stop_monitor();
755    inline void iss_set_debug_mask(uint v)
756    {
757        r_iss.set_debug_mask(v);
758    }
759
760    /////////////////////////////////////////////////////////////
761    // Set the m_dcache_paddr_ext_reset attribute
762    //
763    // The r_dcache_paddr_ext register will be initialized after
764    // reset with the m_dcache_paddr_ext_reset value
765    /////////////////////////////////////////////////////////////
766    inline void set_dcache_paddr_ext_reset(uint32_t v)
767    {
768        m_dcache_paddr_ext_reset = v;
769    }
770
771    /////////////////////////////////////////////////////////////
772    // Set the m_icache_paddr_ext_reset attribute
773    //
774    // The r_icache_paddr_ext register will be initialized after
775    // reset with the m_icache_paddr_ext_reset value
776    /////////////////////////////////////////////////////////////
777    inline void set_icache_paddr_ext_reset(uint32_t v)
778    {
779        m_icache_paddr_ext_reset = v;
780    }
781
782private:
783    void transition();
784    void genMoore();
785
786    soclib_static_assert((int)iss_t::SC_ATOMIC == (int)vci_param::STORE_COND_ATOMIC);
787    soclib_static_assert((int)iss_t::SC_NOT_ATOMIC == (int)vci_param::STORE_COND_NOT_ATOMIC);
788};
789
790}}
791
792#endif /* SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER_H */
793
794// Local Variables:
795// tab-width: 4
796// c-basic-offset: 4
797// c-file-offsets:((innamespace . 0)(inline-open . 0))
798// indent-tabs-mode: nil
799// End:
800
801// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
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