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source: branches/reconfiguration/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp @ 888

Last change on this file since 888 was 888, checked in by cfuguet, 9 years ago

reconf: use the watchdog timer for the uncacheable requests too.

The vci_cc_vcache_wrapper's dcache FSM triggers the watchdog timer also for the uncacheable requests (read and write).

File size: 246.6 KB

Line
1	/* -- c++ --
2	* File : vci_cc_vcache_wrapper.cpp
3	* Copyright (c) UPMC, Lip6, SoC
4	* Authors : Alain GREINER, Yang GAO
5	*
6	* SOCLIB_LGPL_HEADER_BEGIN
7	*
8	* This file is part of SoCLib, GNU LGPLv2.1.
9	*
10	* SoCLib is free software; you can redistribute it and/or modify it
11	* under the terms of the GNU Lesser General Public License as published
12	* by the Free Software Foundation; version 2.1 of the License.
13	*
14	* SoCLib is distributed in the hope that it will be useful, but
15	* WITHOUT ANY WARRANTY; without even the implied warranty of
16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17	* Lesser General Public License for more details.
18	*
19	* You should have received a copy of the GNU Lesser General Public
20	* License along with SoCLib; if not, write to the Free Software
21	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
22	* 02110-1301 USA
23	*
24	* SOCLIB_LGPL_HEADER_END
25	*
26	* Maintainers: cesar.fuguet-tortolero@lip6.fr
27	* alexandre.joannou@lip6.fr
28	*/
29
30	#include <cassert>
31	#include <signal.h>
32
33	#include "arithmetics.h"
34	#include "../include/vci_cc_vcache_wrapper.h"
35
36	#define DEBUG_DCACHE 1
37	#define DEBUG_ICACHE 1
38	#define DEBUG_CMD 0
39
40	namespace soclib {
41	namespace caba {
42
43	namespace {
44	const char * icache_fsm_state_str[] = {
45	"ICACHE_IDLE",
46
47	"ICACHE_XTN_TLB_FLUSH",
48	"ICACHE_XTN_CACHE_FLUSH",
49	"ICACHE_XTN_CACHE_FLUSH_GO",
50	"ICACHE_XTN_TLB_INVAL",
51	"ICACHE_XTN_CACHE_INVAL_VA",
52	"ICACHE_XTN_CACHE_INVAL_PA",
53	"ICACHE_XTN_CACHE_INVAL_GO",
54
55	"ICACHE_TLB_WAIT",
56
57	"ICACHE_MISS_SELECT",
58	"ICACHE_MISS_CLEAN",
59	"ICACHE_MISS_WAIT",
60	"ICACHE_MISS_DATA_UPDT",
61	"ICACHE_MISS_DIR_UPDT",
62
63	"ICACHE_UNC_WAIT",
64
65	"ICACHE_CC_CHECK",
66	"ICACHE_CC_UPDT",
67	"ICACHE_CC_INVAL",
68	};
69
70	const char * dcache_fsm_state_str[] = {
71	"DCACHE_IDLE",
72
73	"DCACHE_TLB_MISS",
74	"DCACHE_TLB_PTE1_GET",
75	"DCACHE_TLB_PTE1_SELECT",
76	"DCACHE_TLB_PTE1_UPDT",
77	"DCACHE_TLB_PTE2_GET",
78	"DCACHE_TLB_PTE2_SELECT",
79	"DCACHE_TLB_PTE2_UPDT",
80	"DCACHE_TLB_LR_UPDT",
81	"DCACHE_TLB_LR_WAIT",
82	"DCACHE_TLB_RETURN",
83
84	"DCACHE_XTN_SWITCH",
85	"DCACHE_XTN_SYNC",
86	"DCACHE_XTN_IC_INVAL_VA",
87	"DCACHE_XTN_IC_FLUSH",
88	"DCACHE_XTN_IC_INVAL_PA",
89	"DCACHE_XTN_IC_PADDR_EXT",
90	"DCACHE_XTN_IT_INVAL",
91	"DCACHE_XTN_DC_FLUSH",
92	"DCACHE_XTN_DC_FLUSH_GO",
93	"DCACHE_XTN_DC_INVAL_VA",
94	"DCACHE_XTN_DC_INVAL_PA",
95	"DCACHE_XTN_DC_INVAL_END",
96	"DCACHE_XTN_DC_INVAL_GO",
97	"DCACHE_XTN_DT_INVAL",
98
99	"DCACHE_DIRTY_GET_PTE",
100	"DCACHE_DIRTY_WAIT",
101
102	"DCACHE_MISS_SELECT",
103	"DCACHE_MISS_CLEAN",
104	"DCACHE_MISS_WAIT",
105	"DCACHE_MISS_DATA_UPDT",
106	"DCACHE_MISS_DIR_UPDT",
107
108	"DCACHE_UNC_WAIT",
109	"DCACHE_LL_WAIT",
110	"DCACHE_SC_WAIT",
111
112	"DCACHE_CC_CHECK",
113	"DCACHE_CC_UPDT",
114	"DCACHE_CC_INVAL",
115
116	"DCACHE_INVAL_TLB_SCAN",
117	};
118
119	const char * cmd_fsm_state_str[] = {
120	"CMD_IDLE",
121	"CMD_INS_MISS",
122	"CMD_INS_UNC",
123	"CMD_DATA_MISS",
124	"CMD_DATA_UNC_READ",
125	"CMD_DATA_UNC_WRITE",
126	"CMD_DATA_WRITE",
127	"CMD_DATA_LL",
128	"CMD_DATA_SC",
129	"CMD_DATA_CAS",
130	};
131
132	const char * vci_pktid_type_str[] = {
133	"TYPE_DATA_UNC",
134	"TYPE_READ_DATA_MISS",
135	"TYPE_READ_INS_UNC",
136	"TYPE_READ_INS_MISS",
137	"TYPE_WRITE",
138	"TYPE_CAS",
139	"TYPE_LL",
140	"TYPE_SC",
141	};
142
143	const char * vci_cmd_type_str[] = {
144	"NOP or STORE_COND",
145	"READ",
146	"WRITE",
147	"LOCKED_READ"
148	};
149
150	const char * rsp_fsm_state_str[] = {
151	"RSP_IDLE",
152	"RSP_INS_MISS",
153	"RSP_INS_UNC",
154	"RSP_DATA_MISS",
155	"RSP_DATA_UNC",
156	"RSP_DATA_LL",
157	"RSP_DATA_WRITE",
158	};
159
160	const char * cc_receive_fsm_state_str[] = {
161	"CC_RECEIVE_IDLE",
162	"CC_RECEIVE_BRDCAST_HEADER",
163	"CC_RECEIVE_BRDCAST_NLINE",
164	"CC_RECEIVE_INS_INVAL_HEADER",
165	"CC_RECEIVE_INS_INVAL_NLINE",
166	"CC_RECEIVE_INS_UPDT_HEADER",
167	"CC_RECEIVE_INS_UPDT_NLINE",
168	"CC_RECEIVE_INS_UPDT_DATA",
169	"CC_RECEIVE_DATA_INVAL_HEADER",
170	"CC_RECEIVE_DATA_INVAL_NLINE",
171	"CC_RECEIVE_DATA_UPDT_HEADER",
172	"CC_RECEIVE_DATA_UPDT_NLINE",
173	"CC_RECEIVE_DATA_UPDT_DATA",
174	};
175
176	const char * cc_send_fsm_state_str[] = {
177	"CC_SEND_IDLE",
178	"CC_SEND_CLEANUP_1",
179	"CC_SEND_CLEANUP_2",
180	"CC_SEND_MULTI_ACK",
181	};
182	}
183
184	#define tmpl(...) \
185	template<typename vci_param, \
186	size_t dspin_in_width, \
187	size_t dspin_out_width, \
188	typename iss_t> __VA_ARGS__ \
189	VciCcVCacheWrapper<vci_param, dspin_in_width, dspin_out_width, iss_t>
190
191	using namespace soclib::common;
192
193	/////////////////////////////////
194	tmpl(/**/)::VciCcVCacheWrapper(
195	sc_module_name name,
196	const int proc_id,
197	const MappingTable &mtd,
198	const IntTab &srcid,
199	const size_t cc_global_id,
200	const size_t itlb_ways,
201	const size_t itlb_sets,
202	const size_t dtlb_ways,
203	const size_t dtlb_sets,
204	const size_t icache_ways,
205	const size_t icache_sets,
206	const size_t icache_words,
207	const size_t dcache_ways,
208	const size_t dcache_sets,
209	const size_t dcache_words,
210	const size_t wbuf_nlines,
211	const size_t wbuf_nwords,
212	const size_t x_width,
213	const size_t y_width,
214	const uint32_t max_frozen_cycles,
215	const uint32_t debug_start_cycle,
216	const bool debug_ok)
217	: soclib::caba::BaseModule(name),
218
219	p_clk("p_clk"),
220	p_resetn("p_resetn"),
221	p_vci("p_vci"),
222	p_dspin_m2p("p_dspin_m2p"),
223	p_dspin_p2m("p_dspin_p2m"),
224	p_dspin_clack("p_dspin_clack"),
225
226	m_cacheability_table( mtd.getCacheabilityTable()),
227	m_srcid(mtd.indexForId(srcid)),
228	m_cc_global_id(cc_global_id),
229	m_nline_width(vci_param::N - (uint32_log2(dcache_words)) - 2),
230	m_itlb_ways(itlb_ways),
231	m_itlb_sets(itlb_sets),
232	m_dtlb_ways(dtlb_ways),
233	m_dtlb_sets(dtlb_sets),
234	m_icache_ways(icache_ways),
235	m_icache_sets(icache_sets),
236	m_icache_yzmask((~0) << (uint32_log2(icache_words) + 2)),
237	m_icache_words(icache_words),
238	m_dcache_ways(dcache_ways),
239	m_dcache_sets(dcache_sets),
240	m_dcache_yzmask((~0) << (uint32_log2(dcache_words) + 2)),
241	m_dcache_words(dcache_words),
242	m_x_width(x_width),
243	m_y_width(y_width),
244	m_proc_id(proc_id),
245	m_max_frozen_cycles(max_frozen_cycles),
246	m_paddr_nbits(vci_param::N),
247	m_debug_start_cycle(debug_start_cycle),
248	m_debug_ok(debug_ok),
249	m_dcache_paddr_ext_reset(0),
250	m_icache_paddr_ext_reset(0),
251
252	r_mmu_ptpr("r_mmu_ptpr"),
253	r_mmu_mode("r_mmu_mode"),
254	r_mmu_word_lo("r_mmu_word_lo"),
255	r_mmu_word_hi("r_mmu_word_hi"),
256	r_mmu_ibvar("r_mmu_ibvar"),
257	r_mmu_dbvar("r_mmu_dbvar"),
258	r_mmu_ietr("r_mmu_ietr"),
259	r_mmu_detr("r_mmu_detr"),
260
261	r_icache_fsm("r_icache_fsm"),
262	r_icache_fsm_save("r_icache_fsm_save"),
263	r_icache_vci_paddr("r_icache_vci_paddr"),
264	r_icache_vaddr_save("r_icache_vaddr_save"),
265
266	r_icache_miss_way("r_icache_miss_way"),
267	r_icache_miss_set("r_icache_miss_set"),
268	r_icache_miss_word("r_icache_miss_word"),
269	r_icache_miss_inval("r_icache_miss_inval"),
270	r_icache_miss_clack("r_icache_miss_clack"),
271
272	r_icache_cc_way("r_icache_cc_way"),
273	r_icache_cc_set("r_icache_cc_set"),
274	r_icache_cc_word("r_icache_cc_word"),
275	r_icache_cc_need_write("r_icache_cc_need_write"),
276
277	r_icache_flush_count("r_icache_flush_count"),
278
279	r_icache_miss_req("r_icache_miss_req"),
280	r_icache_unc_req("r_icache_unc_req"),
281
282	r_icache_tlb_miss_req("r_icache_tlb_read_req"),
283	r_icache_tlb_rsp_error("r_icache_tlb_rsp_error"),
284
285	r_icache_cleanup_victim_req("r_icache_cleanup_victim_req"),
286	r_icache_cleanup_victim_nline("r_icache_cleanup_victim_nline"),
287
288	r_icache_cc_send_req("r_icache_cc_send_req"),
289	r_icache_cc_send_type("r_icache_cc_send_type"),
290	r_icache_cc_send_nline("r_icache_cc_send_nline"),
291	r_icache_cc_send_way("r_icache_cc_send_way"),
292	r_icache_cc_send_updt_tab_idx("r_icache_cc_send_updt_tab_idx"),
293
294	r_dcache_fsm("r_dcache_fsm"),
295	r_dcache_fsm_cc_save("r_dcache_fsm_cc_save"),
296	r_dcache_fsm_scan_save("r_dcache_fsm_scan_save"),
297
298	r_dcache_wbuf_req("r_dcache_wbuf_req"),
299	r_dcache_updt_req("r_dcache_updt_req"),
300	r_dcache_save_vaddr("r_dcache_save_vaddr"),
301	r_dcache_save_wdata("r_dcache_save_wdata"),
302	r_dcache_save_be("r_dcache_save_be"),
303	r_dcache_save_paddr("r_dcache_save_paddr"),
304	r_dcache_save_cache_way("r_dcache_save_cache_way"),
305	r_dcache_save_cache_set("r_dcache_save_cache_set"),
306	r_dcache_save_cache_word("r_dcache_save_cache_word"),
307
308	r_dcache_dirty_paddr("r_dcache_dirty_paddr"),
309	r_dcache_dirty_way("r_dcache_dirty_way"),
310	r_dcache_dirty_set("r_dcache_dirty_set"),
311
312	r_dcache_vci_paddr("r_dcache_vci_paddr"),
313	r_dcache_vci_wdata("r_dcache_vci_wdata"),
314	r_dcache_vci_miss_req("r_dcache_vci_miss_req"),
315	r_dcache_vci_unc_req("r_dcache_vci_unc_req"),
316	r_dcache_vci_unc_be("r_dcache_vci_unc_be"),
317	r_dcache_vci_unc_write("r_dcache_vci_unc_write"),
318	r_dcache_vci_cas_req("r_dcache_vci_cas_req"),
319	r_dcache_vci_cas_old("r_dcache_vci_cas_old"),
320	r_dcache_vci_cas_new("r_dcache_vci_cas_new"),
321	r_dcache_vci_ll_req("r_dcache_vci_ll_req"),
322	r_dcache_vci_sc_req("r_dcache_vci_sc_req"),
323	r_dcache_vci_sc_data("r_dcache_vci_sc_data"),
324	r_dcache_vci_wdt_trdid("r_dcache_vci_wdt_trdid"),
325
326	r_dcache_xtn_way("r_dcache_xtn_way"),
327	r_dcache_xtn_set("r_dcache_xtn_set"),
328
329	r_dcache_miss_type("r_dcache_miss_type"),
330	r_dcache_miss_word("r_dcache_miss_word"),
331	r_dcache_miss_way("r_dcache_miss_way"),
332	r_dcache_miss_set("r_dcache_miss_set"),
333	r_dcache_miss_inval("r_dcache_miss_inval"),
334
335	r_dcache_wdt_max("r_dcache_wdt_max"),
336	r_dcache_wdt("r_dcache_wdt"),
337	r_dcache_wdt_timeout("r_dcache_wdt_timeout"),
338
339	r_dcache_cc_way("r_dcache_cc_way"),
340	r_dcache_cc_set("r_dcache_cc_set"),
341	r_dcache_cc_word("r_dcache_cc_word"),
342	r_dcache_cc_need_write("r_dcache_cc_need_write"),
343
344	r_dcache_flush_count("r_dcache_flush_count"),
345
346	r_dcache_ll_rsp_count("r_dcache_ll_rsp_count"),
347
348	r_dcache_tlb_vaddr("r_dcache_tlb_vaddr"),
349	r_dcache_tlb_ins("r_dcache_tlb_ins"),
350	r_dcache_tlb_pte_flags("r_dcache_tlb_pte_flags"),
351	r_dcache_tlb_pte_ppn("r_dcache_tlb_pte_ppn"),
352	r_dcache_tlb_cache_way("r_dcache_tlb_cache_way"),
353	r_dcache_tlb_cache_set("r_dcache_tlb_cache_set"),
354	r_dcache_tlb_cache_word("r_dcache_tlb_cache_word"),
355	r_dcache_tlb_way("r_dcache_tlb_way"),
356	r_dcache_tlb_set("r_dcache_tlb_set"),
357
358	r_dcache_tlb_inval_line("r_dcache_tlb_inval_line"),
359	r_dcache_tlb_inval_set("r_dcache_tlb_inval_set"),
360
361	r_dcache_xtn_req("r_dcache_xtn_req"),
362	r_dcache_xtn_opcode("r_dcache_xtn_opcode"),
363
364	r_dcache_cleanup_victim_req("r_dcache_cleanup_victim_req"),
365	r_dcache_cleanup_victim_nline("r_dcache_cleanup_victim_nline"),
366
367	r_dcache_cc_send_req("r_dcache_cc_send_req"),
368	r_dcache_cc_send_type("r_dcache_cc_send_type"),
369	r_dcache_cc_send_nline("r_dcache_cc_send_nline"),
370	r_dcache_cc_send_way("r_dcache_cc_send_way"),
371	r_dcache_cc_send_updt_tab_idx("r_dcache_cc_send_updt_tab_idx"),
372
373	r_vci_cmd_fsm("r_vci_cmd_fsm"),
374	r_vci_cmd_min("r_vci_cmd_min"),
375	r_vci_cmd_max("r_vci_cmd_max"),
376	r_vci_cmd_cpt("r_vci_cmd_cpt"),
377	r_vci_cmd_imiss_prio("r_vci_cmd_imiss_prio"),
378
379	r_vci_rsp_fsm("r_vci_rsp_fsm"),
380	r_vci_rsp_cpt("r_vci_rsp_cpt"),
381	r_vci_rsp_ins_error("r_vci_rsp_ins_error"),
382	r_vci_rsp_data_error("r_vci_rsp_data_error"),
383	r_vci_rsp_fifo_icache("r_vci_rsp_fifo_icache", 2), // 2 words depth
384	r_vci_rsp_fifo_dcache("r_vci_rsp_fifo_dcache", 2), // 2 words depth
385
386	r_cc_send_fsm("r_cc_send_fsm"),
387	r_cc_send_last_client("r_cc_send_last_client"),
388
389	r_cc_receive_fsm("r_cc_receive_fsm"),
390	r_cc_receive_data_ins("r_cc_receive_data_ins"),
391	r_cc_receive_word_idx("r_cc_receive_word_idx"),
392	r_cc_receive_updt_fifo_be("r_cc_receive_updt_fifo_be", 2), // 2 words depth
393	r_cc_receive_updt_fifo_data("r_cc_receive_updt_fifo_data", 2), // 2 words depth
394	r_cc_receive_updt_fifo_eop("r_cc_receive_updt_fifo_eop", 2), // 2 words depth
395
396	r_cc_receive_icache_req("r_cc_receive_icache_req"),
397	r_cc_receive_icache_type("r_cc_receive_icache_type"),
398	r_cc_receive_icache_way("r_cc_receive_icache_way"),
399	r_cc_receive_icache_set("r_cc_receive_icache_set"),
400	r_cc_receive_icache_updt_tab_idx("r_cc_receive_icache_updt_tab_idx"),
401	r_cc_receive_icache_nline("r_cc_receive_icache_nline"),
402
403	r_cc_receive_dcache_req("r_cc_receive_dcache_req"),
404	r_cc_receive_dcache_type("r_cc_receive_dcache_type"),
405	r_cc_receive_dcache_way("r_cc_receive_dcache_way"),
406	r_cc_receive_dcache_set("r_cc_receive_dcache_set"),
407	r_cc_receive_dcache_updt_tab_idx("r_cc_receive_dcache_updt_tab_idx"),
408	r_cc_receive_dcache_nline("r_cc_receive_dcache_nline"),
409
410	r_iss(this->name(), proc_id),
411	r_wbuf("wbuf", wbuf_nwords, wbuf_nlines, dcache_words ),
412	r_icache("icache", icache_ways, icache_sets, icache_words),
413	r_dcache("dcache", dcache_ways, dcache_sets, dcache_words),
414	r_itlb("itlb", proc_id, itlb_ways,itlb_sets,vci_param::N),
415	r_dtlb("dtlb", proc_id, dtlb_ways,dtlb_sets,vci_param::N)
416	{
417	std::cout << " - Building VciCcVcacheWrapper : " << name << std::endl;
418
419	assert(((icache_words*vci_param::B) < (1 << vci_param::K)) and
420	"Need more PLEN bits.");
421
422	assert((vci_param::T > 2) and ((1 << (vci_param::T - 1)) >= (wbuf_nlines)) and
423	"Need more TRDID bits.");
424
425	assert((icache_words == dcache_words) and
426	"icache_words and dcache_words parameters must be equal");
427
428	assert((itlb_sets == dtlb_sets) and
429	"itlb_sets and dtlb_sets parameters must be etqual");
430
431	assert((itlb_ways == dtlb_ways) and
432	"itlb_ways and dtlb_ways parameters must be etqual");
433
434	r_mmu_params = (uint32_log2(m_dtlb_ways) << 29) \| (uint32_log2(m_dtlb_sets) << 25) \|
435	(uint32_log2(m_dcache_ways) << 22) \| (uint32_log2(m_dcache_sets) << 18) \|
436	(uint32_log2(m_itlb_ways) << 15) \| (uint32_log2(m_itlb_sets) << 11) \|
437	(uint32_log2(m_icache_ways) << 8) \| (uint32_log2(m_icache_sets) << 4) \|
438	(uint32_log2(m_icache_words << 2));
439
440	r_mmu_release = (uint32_t) (1 << 16) \| 0x1;
441
442	r_dcache_in_tlb = new bool[dcache_ways * dcache_sets];
443	r_dcache_contains_ptd = new bool[dcache_ways * dcache_sets];
444
445	SC_METHOD(transition);
446	dont_initialize();
447	sensitive << p_clk.pos();
448
449	SC_METHOD(genMoore);
450	dont_initialize();
451	sensitive << p_clk.neg();
452
453	typename iss_t::CacheInfo cache_info;
454	cache_info.has_mmu = true;
455	cache_info.icache_line_size = icache_words * sizeof(uint32_t);
456	cache_info.icache_assoc = icache_ways;
457	cache_info.icache_n_lines = icache_sets;
458	cache_info.dcache_line_size = dcache_words * sizeof(uint32_t);
459	cache_info.dcache_assoc = dcache_ways;
460	cache_info.dcache_n_lines = dcache_sets;
461	r_iss.setCacheInfo(cache_info);
462	}
463
464	/////////////////////////////////////
465	tmpl(/**/)::~VciCcVCacheWrapper()
466	/////////////////////////////////////
467	{
468	delete [] r_dcache_in_tlb;
469	delete [] r_dcache_contains_ptd;
470	}
471
472	////////////////////////
473	tmpl(void)::print_cpi()
474	////////////////////////
475	{
476	std::cout << name() << " CPI = "
477	<< (float)m_cpt_total_cycles/(m_cpt_total_cycles - m_cpt_frz_cycles) << std::endl ;
478	}
479
480	////////////////////////////////////
481	tmpl(void)::print_trace(size_t mode)
482	////////////////////////////////////
483	{
484	// b0 : write buffer trace
485	// b1 : dump processor registers
486	// b2 : dcache trace
487	// b3 : icache trace
488	// b4 : dtlb trace
489	// b5 : itlb trace
490	// b6 : SR (ISS register 32)
491
492	std::cout << std::dec << "PROC " << name() << std::endl;
493
494	std::cout << " " << m_ireq << std::endl;
495	std::cout << " " << m_irsp << std::endl;
496	std::cout << " " << m_dreq << std::endl;
497	std::cout << " " << m_drsp << std::endl;
498
499	std::cout << " " << icache_fsm_state_str[r_icache_fsm.read()]
500	<< " \| " << dcache_fsm_state_str[r_dcache_fsm.read()]
501	<< " \| " << cmd_fsm_state_str[r_vci_cmd_fsm.read()]
502	<< " \| " << rsp_fsm_state_str[r_vci_rsp_fsm.read()]
503	<< " \| " << cc_receive_fsm_state_str[r_cc_receive_fsm.read()]
504	<< " \| " << cc_send_fsm_state_str[r_cc_send_fsm.read()]
505	<< " \| MMU = " << r_mmu_mode.read();
506
507	if (r_dcache_updt_req.read()) std::cout << " \| P1_UPDT";
508	if (r_dcache_wbuf_req.read()) std::cout << " \| P1_WBUF";
509	std::cout << std::endl;
510
511	if (mode & 0x01)
512	{
513	if (r_icache_miss_req.read()) std::cout << " IMISS_REQ" << std::endl;
514	if (r_icache_unc_req.read()) std::cout << " IUNC_REQ" << std::endl;
515	if (r_dcache_vci_miss_req.read()) std::cout << " DMISS_REQ" << std::endl;
516	if (r_dcache_vci_unc_req.read()) std::cout << " DUNC_REQ" << std::endl;
517
518	r_wbuf.printTrace((mode >> 1) & 1);
519	}
520	if (mode & 0x02)
521	{
522	r_iss.dump();
523	}
524	if (mode & 0x04)
525	{
526	std::cout << " Data Cache" << std::endl;
527	r_dcache.printTrace();
528	}
529	if (mode & 0x08)
530	{
531	std::cout << " Instruction Cache" << std::endl;
532	r_icache.printTrace();
533	}
534	if (mode & 0x10)
535	{
536	std::cout << " Data TLB" << std::endl;
537	r_dtlb.printTrace();
538	}
539	if (mode & 0x20)
540	{
541	std::cout << " Instruction TLB" << std::endl;
542	r_itlb.printTrace();
543	}
544	if (mode & 0x40)
545	{
546	uint32_t status = r_iss.debugGetRegisterValue(32);
547	std::cout << name();
548	if (status != m_previous_status ) std::cout << " NEW ";
549	std::cout << " status = " << std::hex << status << " " << std::endl;
550	m_previous_status = status;
551	}
552	}
553
554	//////////////////////////////////////////
555	tmpl(void)::cache_monitor(paddr_t addr)
556	//////////////////////////////////////////
557	{
558	bool cache_hit;
559	size_t cache_way = 0;
560	size_t cache_set = 0;
561	size_t cache_word = 0;
562	uint32_t cache_rdata = 0;
563
564	cache_hit = r_dcache.read_neutral(addr,
565	&cache_rdata,
566	&cache_way,
567	&cache_set,
568	&cache_word);
569
570	if (cache_hit != m_debug_previous_d_hit)
571	{
572	std::cout << "Monitor PROC " << name()
573	<< " DCACHE at cycle " << std::dec << m_cpt_total_cycles
574	<< " / HIT = " << cache_hit
575	<< " / PADDR = " << std::hex << addr
576	<< " / DATA = " << cache_rdata
577	<< " / WAY = " << cache_way << std::endl;
578	m_debug_previous_d_hit = cache_hit;
579	}
580
581	cache_hit = r_icache.read_neutral(addr,
582	&cache_rdata,
583	&cache_way,
584	&cache_set,
585	&cache_word);
586
587	if (cache_hit != m_debug_previous_i_hit)
588	{
589	std::cout << "Monitor PROC " << name()
590	<< " ICACHE at cycle " << std::dec << m_cpt_total_cycles
591	<< " / HIT = " << cache_hit
592	<< " / PADDR = " << std::hex << addr
593	<< " / DATA = " << cache_rdata
594	<< " / WAY = " << cache_way << std::endl;
595	m_debug_previous_i_hit = cache_hit;
596	}
597	}
598
599	/*
600	////////////////////////
601	tmpl(void)::print_stats()
602	////////////////////////
603	{
604	float run_cycles = (float)(m_cpt_total_cycles - m_cpt_frz_cycles);
605	std::cout << name() << std::endl
606	<< "- CPI = " << (float)m_cpt_total_cycles/run_cycles << std::endl
607	<< "- READ RATE = " << (float)m_cpt_read/run_cycles << std::endl
608	<< "- WRITE RATE = " << (float)m_cpt_write/run_cycles << std::endl
609	<< "- IMISS_RATE = " << (float)m_cpt_ins_miss/m_cpt_ins_read << std::endl
610	<< "- DMISS RATE = " << (float)m_cpt_data_miss/(m_cpt_read-m_cpt_unc_read) << std::endl
611	<< "- INS MISS COST = " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl
612	<< "- DATA MISS COST = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl
613	<< "- WRITE COST = " << (float)m_cost_write_frz/m_cpt_write << std::endl
614	<< "- UNC COST = " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl
615	<< "- UNCACHED READ RATE = " << (float)m_cpt_unc_read/m_cpt_read << std::endl
616	<< "- CACHED WRITE RATE = " << (float)m_cpt_write_cached/m_cpt_write << std::endl
617	<< "- INS TLB MISS RATE = " << (float)m_cpt_ins_tlb_miss/m_cpt_ins_tlb_read << std::endl
618	<< "- DATA TLB MISS RATE = " << (float)m_cpt_data_tlb_miss/m_cpt_data_tlb_read << std::endl
619	<< "- ITLB MISS COST = " << (float)m_cost_ins_tlb_miss_frz/m_cpt_ins_tlb_miss << std::endl
620	<< "- DTLB MISS COST = " << (float)m_cost_data_tlb_miss_frz/m_cpt_data_tlb_miss << std::endl
621	<< "- ITLB UPDATE ACC COST = " << (float)m_cost_ins_tlb_update_acc_frz/m_cpt_ins_tlb_update_acc << std::endl
622	<< "- DTLB UPDATE ACC COST = " << (float)m_cost_data_tlb_update_acc_frz/m_cpt_data_tlb_update_acc << std::endl
623	<< "- DTLB UPDATE DIRTY COST = " << (float)m_cost_data_tlb_update_dirty_frz/m_cpt_data_tlb_update_dirty << std::endl
624	<< "- ITLB HIT IN DCACHE RATE= " << (float)m_cpt_ins_tlb_hit_dcache/m_cpt_ins_tlb_miss << std::endl
625	<< "- DTLB HIT IN DCACHE RATE= " << (float)m_cpt_data_tlb_hit_dcache/m_cpt_data_tlb_miss << std::endl
626	<< "- DCACHE FROZEN BY ITLB = " << (float)m_cost_ins_tlb_occup_cache_frz/m_cpt_dcache_frz_cycles << std::endl
627	<< "- DCACHE FOR TLB % = " << (float)m_cpt_tlb_occup_dcache/(m_dcache_ways*m_dcache_sets) << std::endl
628	<< "- NB CC BROADCAST = " << m_cpt_cc_broadcast << std::endl
629	<< "- NB CC UPDATE DATA = " << m_cpt_cc_update_data << std::endl
630	<< "- NB CC INVAL DATA = " << m_cpt_cc_inval_data << std::endl
631	<< "- NB CC INVAL INS = " << m_cpt_cc_inval_ins << std::endl
632	<< "- CC BROADCAST COST = " << (float)m_cost_broadcast_frz/m_cpt_cc_broadcast << std::endl
633	<< "- CC UPDATE DATA COST = " << (float)m_cost_updt_data_frz/m_cpt_cc_update_data << std::endl
634	<< "- CC INVAL DATA COST = " << (float)m_cost_inval_data_frz/m_cpt_cc_inval_data << std::endl
635	<< "- CC INVAL INS COST = " << (float)m_cost_inval_ins_frz/m_cpt_cc_inval_ins << std::endl
636	<< "- NB CC CLEANUP DATA = " << m_cpt_cc_cleanup_data << std::endl
637	<< "- NB CC CLEANUP INS = " << m_cpt_cc_cleanup_ins << std::endl
638	<< "- IMISS TRANSACTION = " << (float)m_cost_imiss_transaction/m_cpt_imiss_transaction << std::endl
639	<< "- DMISS TRANSACTION = " << (float)m_cost_dmiss_transaction/m_cpt_dmiss_transaction << std::endl
640	<< "- UNC TRANSACTION = " << (float)m_cost_unc_transaction/m_cpt_unc_transaction << std::endl
641	<< "- WRITE TRANSACTION = " << (float)m_cost_write_transaction/m_cpt_write_transaction << std::endl
642	<< "- WRITE LENGTH = " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl
643	<< "- ITLB MISS TRANSACTION = " << (float)m_cost_itlbmiss_transaction/m_cpt_itlbmiss_transaction << std::endl
644	<< "- DTLB MISS TRANSACTION = " << (float)m_cost_dtlbmiss_transaction/m_cpt_dtlbmiss_transaction << std::endl;
645	}
646
647	////////////////////////
648	tmpl(void)::clear_stats()
649	////////////////////////
650	{
651	m_cpt_dcache_data_read = 0;
652	m_cpt_dcache_data_write = 0;
653	m_cpt_dcache_dir_read = 0;
654	m_cpt_dcache_dir_write = 0;
655	m_cpt_icache_data_read = 0;
656	m_cpt_icache_data_write = 0;
657	m_cpt_icache_dir_read = 0;
658	m_cpt_icache_dir_write = 0;
659
660	m_cpt_frz_cycles = 0;
661	m_cpt_dcache_frz_cycles = 0;
662	m_cpt_total_cycles = 0;
663
664	m_cpt_read = 0;
665	m_cpt_write = 0;
666	m_cpt_data_miss = 0;
667	m_cpt_ins_miss = 0;
668	m_cpt_unc_read = 0;
669	m_cpt_write_cached = 0;
670	m_cpt_ins_read = 0;
671
672	m_cost_write_frz = 0;
673	m_cost_data_miss_frz = 0;
674	m_cost_unc_read_frz = 0;
675	m_cost_ins_miss_frz = 0;
676
677	m_cpt_imiss_transaction = 0;
678	m_cpt_dmiss_transaction = 0;
679	m_cpt_unc_transaction = 0;
680	m_cpt_write_transaction = 0;
681	m_cpt_icache_unc_transaction = 0;
682
683	m_cost_imiss_transaction = 0;
684	m_cost_dmiss_transaction = 0;
685	m_cost_unc_transaction = 0;
686	m_cost_write_transaction = 0;
687	m_cost_icache_unc_transaction = 0;
688	m_length_write_transaction = 0;
689
690	m_cpt_ins_tlb_read = 0;
691	m_cpt_ins_tlb_miss = 0;
692	m_cpt_ins_tlb_update_acc = 0;
693
694	m_cpt_data_tlb_read = 0;
695	m_cpt_data_tlb_miss = 0;
696	m_cpt_data_tlb_update_acc = 0;
697	m_cpt_data_tlb_update_dirty = 0;
698	m_cpt_ins_tlb_hit_dcache = 0;
699	m_cpt_data_tlb_hit_dcache = 0;
700	m_cpt_ins_tlb_occup_cache = 0;
701	m_cpt_data_tlb_occup_cache = 0;
702
703	m_cost_ins_tlb_miss_frz = 0;
704	m_cost_data_tlb_miss_frz = 0;
705	m_cost_ins_tlb_update_acc_frz = 0;
706	m_cost_data_tlb_update_acc_frz = 0;
707	m_cost_data_tlb_update_dirty_frz = 0;
708	m_cost_ins_tlb_occup_cache_frz = 0;
709	m_cost_data_tlb_occup_cache_frz = 0;
710
711	m_cpt_itlbmiss_transaction = 0;
712	m_cpt_itlb_ll_transaction = 0;
713	m_cpt_itlb_sc_transaction = 0;
714	m_cpt_dtlbmiss_transaction = 0;
715	m_cpt_dtlb_ll_transaction = 0;
716	m_cpt_dtlb_sc_transaction = 0;
717	m_cpt_dtlb_ll_dirty_transaction = 0;
718	m_cpt_dtlb_sc_dirty_transaction = 0;
719
720	m_cost_itlbmiss_transaction = 0;
721	m_cost_itlb_ll_transaction = 0;
722	m_cost_itlb_sc_transaction = 0;
723	m_cost_dtlbmiss_transaction = 0;
724	m_cost_dtlb_ll_transaction = 0;
725	m_cost_dtlb_sc_transaction = 0;
726	m_cost_dtlb_ll_dirty_transaction = 0;
727	m_cost_dtlb_sc_dirty_transaction = 0;
728
729	m_cpt_cc_update_data = 0;
730	m_cpt_cc_inval_ins = 0;
731	m_cpt_cc_inval_data = 0;
732	m_cpt_cc_broadcast = 0;
733
734	m_cost_updt_data_frz = 0;
735	m_cost_inval_ins_frz = 0;
736	m_cost_inval_data_frz = 0;
737	m_cost_broadcast_frz = 0;
738
739	m_cpt_cc_cleanup_data = 0;
740	m_cpt_cc_cleanup_ins = 0;
741	}
742
743	*/
744
745	/////////////////////////
746	tmpl(void)::transition()
747	/////////////////////////
748	{
749	if (not p_resetn.read())
750	{
751	r_iss.reset();
752	r_wbuf.reset();
753	r_icache.reset();
754	r_dcache.reset();
755	r_itlb.reset();
756	r_dtlb.reset();
757
758	r_dcache_fsm = DCACHE_IDLE;
759	r_icache_fsm = ICACHE_IDLE;
760	r_vci_cmd_fsm = CMD_IDLE;
761	r_vci_rsp_fsm = RSP_IDLE;
762	r_cc_receive_fsm = CC_RECEIVE_IDLE;
763	r_cc_send_fsm = CC_SEND_IDLE;
764
765	// reset data physical address extension
766	r_dcache_paddr_ext = m_dcache_paddr_ext_reset;
767
768	// reset inst physical address extension
769	r_icache_paddr_ext = m_icache_paddr_ext_reset;
770
771	// reset dcache directory extension
772	for (size_t i = 0; i< m_dcache_ways * m_dcache_sets; i++)
773	{
774	r_dcache_in_tlb[i] = false;
775	r_dcache_contains_ptd[i] = false;
776	}
777
778	// Response FIFOs and cleanup buffer
779	r_vci_rsp_fifo_icache.init();
780	r_vci_rsp_fifo_dcache.init();
781
782	// ICACHE & DCACHE activated
783	// ITLB & DTLB desactivated
784	r_mmu_mode = 0x3;
785
786	// No request from ICACHE FSM to CMD FSM
787	r_icache_miss_req = false;
788	r_icache_unc_req = false;
789
790	// No request from ICACHE_FSM to DCACHE FSM
791	r_icache_tlb_miss_req = false;
792
793	// No request from ICACHE_FSM to CC_SEND FSM
794	r_icache_cc_send_req = false;
795	r_icache_cleanup_victim_req = false;
796
797	r_icache_clack_req = false;
798
799	// No pending write in pipeline
800	r_dcache_wbuf_req = false;
801	r_dcache_updt_req = false;
802
803	// No request from DCACHE_FSM to CMD_FSM
804	r_dcache_vci_miss_req = false;
805	r_dcache_vci_unc_req = false;
806	r_dcache_vci_cas_req = false;
807	r_dcache_vci_ll_req = false;
808	r_dcache_vci_sc_req = false;
809
810	// No processor XTN request pending
811	r_dcache_xtn_req = false;
812
813	// No request from DCACHE FSM to CC_SEND FSM
814	r_dcache_cc_send_req = false;
815	r_dcache_cleanup_victim_req = false;
816
817	r_dcache_clack_req = false;
818
819	// Reset watchdog timer threshold to max value
820	r_dcache_wdt_max = UINT32_MAX;
821	r_dcache_wdt_timeout = 0;
822
823	// No request from CC_RECEIVE FSM to ICACHE/DCACHE FSMs
824	r_cc_receive_icache_req = false;
825	r_cc_receive_dcache_req = false;
826
827	// last cc_send client was dcache
828	r_cc_send_last_client = false;
829
830	// No pending cleanup after a replacement
831	r_icache_miss_clack = false;
832	r_dcache_miss_clack = false;
833
834	// No signalisation of a coherence request matching a pending miss
835	r_icache_miss_inval = false;
836	r_dcache_miss_inval = false;
837
838	r_dspin_clack_req = false;
839
840	// No signalisation of errors
841	r_vci_rsp_ins_error = false;
842	r_vci_rsp_data_error = false;
843
844	// Debug variables
845	m_debug_previous_i_hit = false;
846	m_debug_previous_d_hit = false;
847	m_debug_icache_fsm = false;
848	m_debug_dcache_fsm = false;
849	m_debug_cmd_fsm = false;
850
851	// activity counters
852	m_cpt_dcache_data_read = 0;
853	m_cpt_dcache_data_write = 0;
854	m_cpt_dcache_dir_read = 0;
855	m_cpt_dcache_dir_write = 0;
856	m_cpt_icache_data_read = 0;
857	m_cpt_icache_data_write = 0;
858	m_cpt_icache_dir_read = 0;
859	m_cpt_icache_dir_write = 0;
860
861	m_cpt_frz_cycles = 0;
862	m_cpt_total_cycles = 0;
863	m_cpt_stop_simulation = 0;
864
865	m_cpt_data_miss = 0;
866	m_cpt_ins_miss = 0;
867	m_cpt_unc_read = 0;
868	m_cpt_write_cached = 0;
869	m_cpt_ins_read = 0;
870
871	m_cost_write_frz = 0;
872	m_cost_data_miss_frz = 0;
873	m_cost_unc_read_frz = 0;
874	m_cost_ins_miss_frz = 0;
875
876	m_cpt_imiss_transaction = 0;
877	m_cpt_dmiss_transaction = 0;
878	m_cpt_unc_transaction = 0;
879	m_cpt_write_transaction = 0;
880	m_cpt_icache_unc_transaction = 0;
881
882	m_cost_imiss_transaction = 0;
883	m_cost_dmiss_transaction = 0;
884	m_cost_unc_transaction = 0;
885	m_cost_write_transaction = 0;
886	m_cost_icache_unc_transaction = 0;
887	m_length_write_transaction = 0;
888
889	m_cpt_ins_tlb_read = 0;
890	m_cpt_ins_tlb_miss = 0;
891	m_cpt_ins_tlb_update_acc = 0;
892
893	m_cpt_data_tlb_read = 0;
894	m_cpt_data_tlb_miss = 0;
895	m_cpt_data_tlb_update_acc = 0;
896	m_cpt_data_tlb_update_dirty = 0;
897	m_cpt_ins_tlb_hit_dcache = 0;
898	m_cpt_data_tlb_hit_dcache = 0;
899	m_cpt_ins_tlb_occup_cache = 0;
900	m_cpt_data_tlb_occup_cache = 0;
901
902	m_cost_ins_tlb_miss_frz = 0;
903	m_cost_data_tlb_miss_frz = 0;
904	m_cost_ins_tlb_update_acc_frz = 0;
905	m_cost_data_tlb_update_acc_frz = 0;
906	m_cost_data_tlb_update_dirty_frz = 0;
907	m_cost_ins_tlb_occup_cache_frz = 0;
908	m_cost_data_tlb_occup_cache_frz = 0;
909
910	m_cpt_ins_tlb_inval = 0;
911	m_cpt_data_tlb_inval = 0;
912	m_cost_ins_tlb_inval_frz = 0;
913	m_cost_data_tlb_inval_frz = 0;
914
915	m_cpt_cc_broadcast = 0;
916
917	m_cost_updt_data_frz = 0;
918	m_cost_inval_ins_frz = 0;
919	m_cost_inval_data_frz = 0;
920	m_cost_broadcast_frz = 0;
921
922	m_cpt_cc_cleanup_data = 0;
923	m_cpt_cc_cleanup_ins = 0;
924
925	m_cpt_itlbmiss_transaction = 0;
926	m_cpt_itlb_ll_transaction = 0;
927	m_cpt_itlb_sc_transaction = 0;
928	m_cpt_dtlbmiss_transaction = 0;
929	m_cpt_dtlb_ll_transaction = 0;
930	m_cpt_dtlb_sc_transaction = 0;
931	m_cpt_dtlb_ll_dirty_transaction = 0;
932	m_cpt_dtlb_sc_dirty_transaction = 0;
933
934	m_cost_itlbmiss_transaction = 0;
935	m_cost_itlb_ll_transaction = 0;
936	m_cost_itlb_sc_transaction = 0;
937	m_cost_dtlbmiss_transaction = 0;
938	m_cost_dtlb_ll_transaction = 0;
939	m_cost_dtlb_sc_transaction = 0;
940	m_cost_dtlb_ll_dirty_transaction = 0;
941	m_cost_dtlb_sc_dirty_transaction = 0;
942	/*
943	m_cpt_dcache_frz_cycles = 0;
944	m_cpt_read = 0;
945	m_cpt_write = 0;
946	m_cpt_cc_update_data = 0;
947	m_cpt_cc_inval_ins = 0;
948	m_cpt_cc_inval_data = 0;
949	*/
950
951	for (uint32_t i = 0; i < 32; ++i) m_cpt_fsm_icache[i] = 0;
952	for (uint32_t i = 0; i < 32; ++i) m_cpt_fsm_dcache[i] = 0;
953	for (uint32_t i = 0; i < 32; ++i) m_cpt_fsm_cmd[i] = 0;
954	for (uint32_t i = 0; i < 32; ++i) m_cpt_fsm_rsp[i] = 0;
955
956	// init the llsc reservation buffer
957	r_dcache_llsc_valid = false;
958	m_monitor_ok = false;
959
960	return;
961	}
962
963	// Response FIFOs default values
964	bool vci_rsp_fifo_icache_get = false;
965	bool vci_rsp_fifo_icache_put = false;
966	uint32_t vci_rsp_fifo_icache_data = 0;
967
968	bool vci_rsp_fifo_dcache_get = false;
969	bool vci_rsp_fifo_dcache_put = false;
970	uint32_t vci_rsp_fifo_dcache_data = 0;
971
972	// updt fifo
973	bool cc_receive_updt_fifo_get = false;
974	bool cc_receive_updt_fifo_put = false;
975	uint32_t cc_receive_updt_fifo_be = 0;
976	uint32_t cc_receive_updt_fifo_data = 0;
977	bool cc_receive_updt_fifo_eop = false;
978
979	#ifdef INSTRUMENTATION
980	m_cpt_fsm_dcache [r_dcache_fsm.read() ] ++;
981	m_cpt_fsm_icache [r_icache_fsm.read() ] ++;
982	m_cpt_fsm_cmd [r_vci_cmd_fsm.read()] ++;
983	m_cpt_fsm_rsp [r_vci_rsp_fsm.read()] ++;
984	m_cpt_fsm_tgt [r_tgt_fsm.read() ] ++;
985	m_cpt_fsm_cleanup[r_cleanup_cmd_fsm.read()] ++;
986	#endif
987
988	m_cpt_total_cycles++;
989
990	m_debug_icache_fsm = m_debug_icache_fsm \|\|
991	((m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok);
992	m_debug_dcache_fsm = m_debug_dcache_fsm \|\|
993	((m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok);
994	m_debug_cmd_fsm = m_debug_cmd_fsm \|\|
995	((m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok);
996
997	/////////////////////////////////////////////////////////////////////
998	// Get data and instruction requests from processor
999	///////////////////////////////////////////////////////////////////////
1000
1001	r_iss.getRequests(m_ireq, m_dreq);
1002
1003	////////////////////////////////////////////////////////////////////////////////////
1004	// ICACHE_FSM
1005	//
1006	// 1/ Coherence operations
1007	// They are handled as interrupts generated by the CC_RECEIVE FSM.
1008	// - There is a coherence request when r_tgt_icache_req is set.
1009	// They are taken in IDLE, MISS_WAIT, MISS_DIR_UPDT, UNC_WAIT, states.
1010	// - There is a cleanup ack request when r_cleanup_icache_req is set.
1011	// They are taken in IDLE, MISS_SELECT, MISS_CLEAN, MISS_WAIT,
1012	// MISS_DATA_UPDT, MISS_DIR_UPDT and UNC_WAIT states.
1013	// - For both types of requests, actions associated to the pre-empted state
1014	// are not executed. The DCACHE FSM goes to the proper sub-FSM (CC_CHECK
1015	// or CC_CLACK) to execute the requested coherence operation, and returns
1016	// to the pre-empted state.
1017	//
1018	// 2/ Processor requests
1019	// They are taken in IDLE state only. In case of cache miss, or uncacheable
1020	// instruction, the ICACHE FSM request a VCI transaction to CMD FSM,
1021	// using the r_icache_miss_req or r_icache_unc_req flip-flops. These
1022	// flip-flops are reset when the transaction starts.
1023	// - In case of miss the ICACHE FSM goes to the ICACHE_MISS_SELECT state
1024	// to select a slot and possibly request a cleanup transaction to the CC_SEND FSM.
1025	// It goes next to the ICACHE_MISS_WAIT state waiting a response from RSP FSM,
1026	// The availability of the missing cache line is signaled by the response fifo,
1027	// and the cache update is done (one word per cycle) in the ICACHE_MISS_DATA_UPDT
1028	// and ICACHE_MISS_DIR_UPDT states.
1029	// - In case of uncacheable instruction, the ICACHE FSM goes to ICACHE_UNC_WAIT
1030	// to wait the response from the RSP FSM, through the response fifo.
1031	// The missing instruction is directly returned to processor in this state.
1032	//
1033	// 3/ TLB miss
1034	// In case of tlb miss, the ICACHE FSM request to the DCACHE FSM to update the
1035	// ITLB using the r_icache_tlb_miss_req flip-flop and the r_icache_tlb_miss_vaddr
1036	// register, and goes to the ICACHE_TLB_WAIT state.
1037	// The tlb update is entirely done by the DCACHE FSM (who becomes the owner
1038	// of ITLB until the update is completed, and reset r_icache_tlb_miss_req
1039	// to signal the completion.
1040	//
1041	// 4/ XTN requests
1042	// The DCACHE FSM signals XTN processor requests to ICACHE_FSM
1043	// using the r_dcache_xtn_req flip-flop.
1044	// The request opcode and the address to be invalidated are transmitted
1045	// in the r_dcache_xtn_opcode and r_dcache_save_wdata registers respectively.
1046	// The r_dcache_xtn_req flip-flop is reset by the ICACHE_FSM when the operation
1047	// is completed.
1048	//
1049	// 5/ Error Handling
1050	// The r_vci_rsp_ins_error flip-flop is set by the RSP FSM in case of bus error
1051	// in a cache miss or uncacheable read VCI transaction. Nothing is written
1052	// in the response fifo. This flip-flop is reset by the ICACHE-FSM.
1053	////////////////////////////////////////////////////////////////////////////////////////
1054
1055	// default value for m_irsp
1056	m_irsp.valid = false;
1057	m_irsp.error = false;
1058	m_irsp.instruction = 0;
1059
1060	switch (r_icache_fsm.read())
1061	{
1062	/////////////////
1063	case ICACHE_IDLE: // In this state, we handle processor requests, XTN requests,
1064	// and coherence requests with a fixed priority:
1065	// 1/ Coherence requests => ICACHE_CC_CHECK
1066	// 2/ XTN processor requests (from DCACHE FSM) => ICACHE_XTN_*
1067	// 3/ tlb miss => ICACHE_TLB_WAIT
1068	// 4/ cacheable read miss => ICACHE_MISS_SELECT
1069	// 5/ uncacheable read miss => ICACHE_UNC_REQ
1070	{
1071	// coherence clack interrupt
1072	if (r_icache_clack_req.read())
1073	{
1074	r_icache_fsm = ICACHE_CC_CHECK;
1075	r_icache_fsm_save = r_icache_fsm.read();
1076	break;
1077	}
1078
1079	// coherence interrupt
1080	if (r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read())
1081	{
1082	r_icache_fsm = ICACHE_CC_CHECK;
1083	r_icache_fsm_save = r_icache_fsm.read();
1084	break;
1085	}
1086
1087	// XTN requests sent by DCACHE FSM
1088	// These request are not executed in this IDLE state (except XTN_INST_PADDR_EXT),
1089	// because they require access to icache or itlb, that are already accessed
1090	if (r_dcache_xtn_req.read())
1091	{
1092	if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_PTPR )
1093	{
1094	r_icache_fsm = ICACHE_XTN_TLB_FLUSH;
1095	}
1096	else if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_ICACHE_FLUSH)
1097	{
1098	r_icache_flush_count = 0;
1099	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH;
1100	}
1101	else if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_ITLB_INVAL)
1102	{
1103	r_icache_fsm = ICACHE_XTN_TLB_INVAL;
1104	}
1105	else if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_ICACHE_INVAL)
1106	{
1107	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_VA;
1108	}
1109	else if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_MMU_ICACHE_PA_INV)
1110	{
1111	if (sizeof(paddr_t) <= 32)
1112	{
1113	assert(r_mmu_word_hi.read() == 0 &&
1114	"illegal XTN request in ICACHE: high bits should be 0 for 32bit paddr");
1115	r_icache_vci_paddr = (paddr_t) r_mmu_word_lo.read();
1116	}
1117	else
1118	{
1119	r_icache_vci_paddr = (paddr_t) r_mmu_word_hi.read() << 32 \|
1120	(paddr_t) r_mmu_word_lo.read();
1121	}
1122	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA;
1123	}
1124	else if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_INST_PADDR_EXT)
1125	{
1126	r_icache_paddr_ext = r_dcache_save_wdata.read();
1127	r_dcache_xtn_req = false;
1128	}
1129	else
1130	{
1131	assert(false and
1132	"undefined XTN request received by ICACHE FSM");
1133	}
1134	break;
1135	} // end if xtn_req
1136
1137	// processor request
1138	if (m_ireq.valid )
1139	{
1140	bool cacheable;
1141	paddr_t paddr;
1142	bool tlb_hit = false;
1143	pte_info_t tlb_flags;
1144	size_t tlb_way;
1145	size_t tlb_set;
1146	paddr_t tlb_nline;
1147	uint32_t cache_inst = 0;
1148	size_t cache_way;
1149	size_t cache_set;
1150	size_t cache_word;
1151	int cache_state = CACHE_SLOT_STATE_EMPTY;
1152
1153	// We register processor request
1154	r_icache_vaddr_save = m_ireq.addr;
1155	paddr = (paddr_t) m_ireq.addr;
1156
1157	// sytematic itlb access (if activated)
1158	if (r_mmu_mode.read() & INS_TLB_MASK)
1159	{
1160
1161	#ifdef INSTRUMENTATION
1162	m_cpt_itlb_read++;
1163	#endif
1164	tlb_hit = r_itlb.translate(m_ireq.addr,
1165	&paddr,
1166	&tlb_flags,
1167	&tlb_nline, // unused
1168	&tlb_way, // unused
1169	&tlb_set); // unused
1170	}
1171	else if (vci_param::N > 32)
1172	{
1173	paddr = paddr \| ((paddr_t) r_icache_paddr_ext.read() << 32);
1174	}
1175
1176	// systematic icache access (if activated)
1177	if (r_mmu_mode.read() & INS_CACHE_MASK)
1178	{
1179
1180
1181	#ifdef INSTRUMENTATION
1182	m_cpt_icache_data_read++;
1183	m_cpt_icache_dir_read++;
1184	#endif
1185	r_icache.read(paddr,
1186	&cache_inst,
1187	&cache_way,
1188	&cache_set,
1189	&cache_word,
1190	&cache_state);
1191	}
1192
1193	// We compute cacheability and check access rights:
1194	// - If MMU activated : cacheability is defined by the C bit in the PTE,
1195	// and the access rights are defined by the U and X bits in the PTE.
1196	// - If MMU not activated : cacheability is defined by the segment table,
1197	// and there is no access rights checking
1198
1199	if (not (r_mmu_mode.read() & INS_TLB_MASK)) // tlb not activated:
1200	{
1201	// cacheability
1202	if (not (r_mmu_mode.read() & INS_CACHE_MASK)) cacheable = false;
1203	else cacheable = m_cacheability_table[(uint64_t) m_ireq.addr];
1204	}
1205	else // itlb activated
1206	{
1207	if (tlb_hit) // ITLB hit
1208	{
1209	// cacheability
1210	if (not (r_mmu_mode.read() & INS_CACHE_MASK)) cacheable = false;
1211	else cacheable = tlb_flags.c;
1212
1213	// access rights checking
1214	if (not tlb_flags.u && (m_ireq.mode == iss_t::MODE_USER))
1215	{
1216
1217	#if DEBUG_ICACHE
1218	if ( m_debug_icache_fsm )
1219	std::cout << " <PROC " << name() << " ICACHE_IDLE> MMU Privilege Violation"
1220	<< " : PADDR = " << std::hex << paddr << std::endl;
1221	#endif
1222	r_mmu_ietr = MMU_READ_PRIVILEGE_VIOLATION;
1223	r_mmu_ibvar = m_ireq.addr;
1224	m_irsp.valid = true;
1225	m_irsp.error = true;
1226	m_irsp.instruction = 0;
1227	break;
1228	}
1229	else if (not tlb_flags.x)
1230	{
1231
1232	#if DEBUG_ICACHE
1233	if ( m_debug_icache_fsm )
1234	std::cout << " <PROC " << name() << " ICACHE_IDLE> MMU Executable Violation"
1235	<< " : PADDR = " << std::hex << paddr << std::endl;
1236	#endif
1237	r_mmu_ietr = MMU_READ_EXEC_VIOLATION;
1238	r_mmu_ibvar = m_ireq.addr;
1239	m_irsp.valid = true;
1240	m_irsp.error = true;
1241	m_irsp.instruction = 0;
1242	break;
1243	}
1244	}
1245	else // ITLB miss
1246	{
1247
1248	#ifdef INSTRUMENTATION
1249	m_cpt_itlb_miss++;
1250	#endif
1251	r_icache_fsm = ICACHE_TLB_WAIT;
1252	r_icache_tlb_miss_req = true;
1253	break;
1254	}
1255	} // end if itlb activated
1256
1257	// physical address registration
1258	r_icache_vci_paddr = paddr;
1259
1260	// Finally, we send the response to processor, and compute next state
1261	if (cacheable)
1262	{
1263	if (cache_state == CACHE_SLOT_STATE_EMPTY) // cache miss
1264	{
1265
1266	#ifdef INSTRUMENTATION
1267	m_cpt_icache_miss++;
1268	#endif
1269	// we request a VCI transaction
1270	r_icache_fsm = ICACHE_MISS_SELECT;
1271	#if DEBUG_ICACHE
1272	if (m_debug_icache_fsm)
1273	std::cout << " <PROC " << name() << " ICACHE_IDLE> READ MISS in icache"
1274	<< " : PADDR = " << std::hex << paddr << std::endl;
1275	#endif
1276	r_icache_miss_req = true;
1277	}
1278	else if (cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup
1279	{
1280	// stalled until cleanup is acknowledged
1281	r_icache_fsm = ICACHE_IDLE;
1282	}
1283	else // cache hit
1284	{
1285
1286	#ifdef INSTRUMENTATION
1287	m_cpt_ins_read++;
1288	#endif
1289	// return instruction to processor
1290	m_irsp.valid = true;
1291	m_irsp.instruction = cache_inst;
1292	r_icache_fsm = ICACHE_IDLE;
1293	#if DEBUG_ICACHE
1294	if (m_debug_icache_fsm)
1295	std::cout << " <PROC " << name() << " ICACHE_IDLE> READ HIT in icache"
1296	<< " : PADDR = " << std::hex << paddr
1297	<< " / INST = " << cache_inst << std::endl;
1298	#endif
1299	}
1300	}
1301	else // non cacheable read
1302	{
1303	r_icache_unc_req = true;
1304	r_icache_fsm = ICACHE_UNC_WAIT;
1305
1306	#if DEBUG_ICACHE
1307	if (m_debug_icache_fsm)
1308	{
1309	std::cout << " <PROC " << name()
1310	<< " ICACHE_IDLE> READ UNCACHEABLE in icache"
1311	<< " : PADDR = " << std::hex << paddr << std::endl;
1312	}
1313	#endif
1314	}
1315	} // end if m_ireq.valid
1316	break;
1317	}
1318	/////////////////////
1319	case ICACHE_TLB_WAIT: // Waiting the itlb update by the DCACHE FSM after a tlb miss
1320	// the itlb is udated by the DCACHE FSM, as well as the
1321	// r_mmu_ietr and r_mmu_ibvar registers in case of error.
1322	// the itlb is not accessed by ICACHE FSM until DCACHE FSM
1323	// reset the r_icache_tlb_miss_req flip-flop
1324	// external coherence request are accepted in this state.
1325	{
1326	// coherence clack interrupt
1327	if (r_icache_clack_req.read())
1328	{
1329	r_icache_fsm = ICACHE_CC_CHECK;
1330	r_icache_fsm_save = r_icache_fsm.read();
1331	break;
1332	}
1333
1334	// coherence interrupt
1335	if (r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read())
1336	{
1337	r_icache_fsm = ICACHE_CC_CHECK;
1338	r_icache_fsm_save = r_icache_fsm.read();
1339	break;
1340	}
1341
1342	if (m_ireq.valid) m_cost_ins_tlb_miss_frz++;
1343
1344	// DCACHE FSM signals response by reseting the request flip-flop
1345	if (not r_icache_tlb_miss_req.read())
1346	{
1347	if (r_icache_tlb_rsp_error.read()) // error reported : tlb not updated
1348	{
1349	r_icache_tlb_rsp_error = false;
1350	m_irsp.error = true;
1351	m_irsp.valid = true;
1352	r_icache_fsm = ICACHE_IDLE;
1353	}
1354	else // tlb updated : return to IDLE state
1355	{
1356	r_icache_fsm = ICACHE_IDLE;
1357	}
1358	}
1359	break;
1360	}
1361	//////////////////////////
1362	case ICACHE_XTN_TLB_FLUSH: // invalidate in one cycle all non global TLB entries
1363	{
1364	r_itlb.flush();
1365	r_dcache_xtn_req = false;
1366	r_icache_fsm = ICACHE_IDLE;
1367	break;
1368	}
1369	////////////////////////////
1370	case ICACHE_XTN_CACHE_FLUSH: // Invalidate sequencially all cache lines, using
1371	// r_icache_flush_count as a slot counter,
1372	// looping in this state until all slots are visited.
1373	// It can require two cycles per slot:
1374	// We test here the slot state, and make the actual inval
1375	// (if line is valid) in ICACHE_XTN_CACHE_FLUSH_GO state.
1376	// A cleanup request is generated for each valid line
1377	{
1378	// coherence clack interrupt
1379	if (r_icache_clack_req.read())
1380	{
1381	r_icache_fsm = ICACHE_CC_CHECK;
1382	r_icache_fsm_save = r_icache_fsm.read();
1383	break;
1384	}
1385
1386	// coherence request (from CC_RECEIVE FSM)
1387	if (r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read())
1388	{
1389	r_icache_fsm = ICACHE_CC_CHECK;
1390	r_icache_fsm_save = r_icache_fsm.read();
1391	break;
1392	}
1393
1394	if (not r_icache_cc_send_req.read()) // blocked until previous cc_send request is sent
1395	{
1396	int state;
1397	paddr_t tag;
1398	size_t way = r_icache_flush_count.read() / m_icache_sets;
1399	size_t set = r_icache_flush_count.read() % m_icache_sets;
1400
1401	#ifdef INSTRUMENTATION
1402	m_cpt_icache_dir_read++;
1403	#endif
1404	r_icache.read_dir(way,
1405	set,
1406	&tag,
1407	&state);
1408
1409	if (state == CACHE_SLOT_STATE_VALID) // inval required
1410	{
1411	// request cleanup
1412	r_icache_cc_send_req = true;
1413	r_icache_cc_send_nline = tag * m_icache_sets + set;
1414	r_icache_cc_send_way = way;
1415	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1416
1417	// goes to ICACHE_XTN_CACHE_FLUSH_GO to make inval
1418	r_icache_miss_way = way;
1419	r_icache_miss_set = set;
1420	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH_GO;
1421	}
1422	else if (r_icache_flush_count.read() ==
1423	(m_icache_sets*m_icache_ways - 1)) // last slot
1424	{
1425	r_dcache_xtn_req = false;
1426	m_drsp.valid = true;
1427	r_icache_fsm = ICACHE_IDLE;
1428	}
1429
1430	// saturation counter, to have the same last slot condition
1431	// in ICACHE_XTN_CACHE_FLUSH and ICACHE_XTN_CACHE_FLUSH_GO states
1432	if (r_icache_flush_count.read() < (m_icache_sets * m_icache_ways - 1))
1433	{
1434	r_icache_flush_count = r_icache_flush_count.read() + 1;
1435	}
1436	}
1437	break;
1438	}
1439	///////////////////////////////
1440	case ICACHE_XTN_CACHE_FLUSH_GO: // Switch slot state to ZOMBI for an XTN flush
1441	{
1442	size_t way = r_icache_miss_way.read();
1443	size_t set = r_icache_miss_set.read();
1444
1445	#ifdef INSTRUMENTATION
1446	m_cpt_icache_dir_write++;
1447	#endif
1448
1449	r_icache.write_dir(way,
1450	set,
1451	CACHE_SLOT_STATE_ZOMBI);
1452
1453	if (r_icache_flush_count.read() ==
1454	(m_icache_sets*m_icache_ways - 1)) // last slot
1455	{
1456	r_dcache_xtn_req = false;
1457	m_drsp.valid = true;
1458	r_icache_fsm = ICACHE_IDLE;
1459	}
1460	else
1461	{
1462	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH;
1463	}
1464	break;
1465	}
1466
1467	//////////////////////////
1468	case ICACHE_XTN_TLB_INVAL: // invalidate one TLB entry selected by the virtual address
1469	// stored in the r_dcache_save_wdata register
1470	{
1471	r_itlb.inval(r_dcache_save_wdata.read());
1472	r_dcache_xtn_req = false;
1473	r_icache_fsm = ICACHE_IDLE;
1474	break;
1475	}
1476	///////////////////////////////
1477	case ICACHE_XTN_CACHE_INVAL_VA: // Selective cache line invalidate with virtual address
1478	// requires 3 cycles (in case of hit on itlb and icache).
1479	// In this state, access TLB to translate virtual address
1480	// stored in the r_dcache_save_wdata register.
1481	{
1482	paddr_t paddr;
1483	bool hit;
1484
1485	// read physical address in TLB when MMU activated
1486	if (r_mmu_mode.read() & INS_TLB_MASK) // itlb activated
1487	{
1488
1489	#ifdef INSTRUMENTATION
1490	m_cpt_itlb_read++;
1491	#endif
1492	hit = r_itlb.translate(r_dcache_save_wdata.read(), &paddr);
1493	}
1494	else // itlb not activated
1495	{
1496	paddr = (paddr_t) r_dcache_save_wdata.read();
1497	hit = true;
1498	}
1499
1500	if (hit) // continue the selective inval process
1501	{
1502	r_icache_vci_paddr = paddr;
1503	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA;
1504	}
1505	else // miss : send a request to DCACHE FSM
1506	{
1507
1508	#ifdef INSTRUMENTATION
1509	m_cpt_itlb_miss++;
1510	#endif
1511	r_icache_tlb_miss_req = true;
1512	r_icache_vaddr_save = r_dcache_save_wdata.read();
1513	r_icache_fsm = ICACHE_TLB_WAIT;
1514	}
1515	break;
1516	}
1517	///////////////////////////////
1518	case ICACHE_XTN_CACHE_INVAL_PA: // selective invalidate cache line with physical address
1519	// require 2 cycles. In this state, we read directory
1520	// with address stored in r_icache_vci_paddr register.
1521	{
1522	int state;
1523	size_t way;
1524	size_t set;
1525	size_t word;
1526
1527	#ifdef INSTRUMENTATION
1528	m_cpt_icache_dir_read++;
1529	#endif
1530	r_icache.read_dir(r_icache_vci_paddr.read(),
1531	&state,
1532	&way,
1533	&set,
1534	&word);
1535
1536	if (state == CACHE_SLOT_STATE_VALID) // inval to be done
1537	{
1538	r_icache_miss_way = way;
1539	r_icache_miss_set = set;
1540	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_GO;
1541	}
1542	else // miss : acknowlege the XTN request and return
1543	{
1544	r_dcache_xtn_req = false;
1545	r_icache_fsm = ICACHE_IDLE;
1546	}
1547	break;
1548	}
1549	///////////////////////////////
1550	case ICACHE_XTN_CACHE_INVAL_GO: // Switch slot to ZOMBI state for an XTN inval
1551	{
1552	if (not r_icache_cc_send_req.read()) // blocked until previous cc_send request not sent
1553	{
1554
1555	#ifdef INSTRUMENTATION
1556	m_cpt_icache_dir_write++;
1557	#endif
1558	r_icache.write_dir(r_icache_miss_way.read(),
1559	r_icache_miss_set.read(),
1560	CACHE_SLOT_STATE_ZOMBI);
1561
1562	// request cleanup
1563	r_icache_cc_send_req = true;
1564	r_icache_cc_send_nline = r_icache_vci_paddr.read() / (m_icache_words << 2);
1565	r_icache_cc_send_way = r_icache_miss_way.read();
1566	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1567
1568	// acknowledge the XTN request and return
1569	r_dcache_xtn_req = false;
1570	r_icache_fsm = ICACHE_IDLE;
1571	}
1572	break;
1573	}
1574	////////////////////////
1575	case ICACHE_MISS_SELECT: // Try to select a slot in associative set,
1576	// Waiting in this state if no slot available.
1577	// If a victim slot has been choosen and the r_icache_cc_send_req is false,
1578	// we send the cleanup request in this state.
1579	// If not, a r_icache_cleanup_victim_req flip-flop is
1580	// utilized for saving this cleanup request, and it will be sent later
1581	// in state ICACHE_MISS_WAIT or ICACHE_MISS_UPDT_DIR.
1582	// The r_icache_miss_clack flip-flop is set
1583	// when a cleanup is required
1584	{
1585	if (m_ireq.valid) m_cost_ins_miss_frz++;
1586
1587	// coherence clack interrupt
1588	if (r_icache_clack_req.read())
1589	{
1590	r_icache_fsm = ICACHE_CC_CHECK;
1591	r_icache_fsm_save = r_icache_fsm.read();
1592	break;
1593	}
1594
1595	// coherence interrupt
1596	if (r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read())
1597	{
1598	r_icache_fsm = ICACHE_CC_CHECK;
1599	r_icache_fsm_save = r_icache_fsm.read();
1600	break;
1601	}
1602
1603
1604	bool found;
1605	bool cleanup;
1606	size_t way;
1607	size_t set;
1608	paddr_t victim;
1609
1610	#ifdef INSTRUMENTATION
1611	m_cpt_icache_dir_read++;
1612	#endif
1613	r_icache.read_select(r_icache_vci_paddr.read(),
1614	&victim,
1615	&way,
1616	&set,
1617	&found,
1618	&cleanup);
1619	if (not found)
1620	{
1621	break;
1622	}
1623	else
1624	{
1625	r_icache_miss_way = way;
1626	r_icache_miss_set = set;
1627
1628	if (cleanup)
1629	{
1630	if (not r_icache_cc_send_req.read())
1631	{
1632	r_icache_cc_send_req = true;
1633	r_icache_cc_send_nline = victim;
1634	r_icache_cc_send_way = way;
1635	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1636	}
1637	else
1638	{
1639	r_icache_cleanup_victim_req = true;
1640	r_icache_cleanup_victim_nline = victim;
1641	}
1642
1643	r_icache_miss_clack = true;
1644	r_icache_fsm = ICACHE_MISS_CLEAN;
1645	}
1646	else
1647	{
1648	r_icache_fsm = ICACHE_MISS_WAIT;
1649	}
1650
1651	#if DEBUG_ICACHE
1652	if (m_debug_icache_fsm)
1653	{
1654	std::cout << " <PROC " << name()
1655	<< " ICACHE_MISS_SELECT> Select a slot:" << std::dec
1656	<< " / WAY = " << way
1657	<< " / SET = " << set;
1658	if (cleanup) std::cout << " / VICTIM = " << std::hex << victim << std::endl;
1659	else std::cout << std::endl;
1660	}
1661	#endif
1662	}
1663	break;
1664	}
1665	///////////////////////
1666	case ICACHE_MISS_CLEAN: // switch the slot to zombi state
1667	{
1668	if (m_ireq.valid) m_cost_ins_miss_frz++;
1669
1670	#ifdef INSTRUMENTATION
1671	m_cpt_icache_dir_write++;
1672	#endif
1673	r_icache.write_dir(r_icache_miss_way.read(),
1674	r_icache_miss_set.read(),
1675	CACHE_SLOT_STATE_ZOMBI);
1676	#if DEBUG_ICACHE
1677	if (m_debug_icache_fsm)
1678	{
1679	std::cout << " <PROC " << name()
1680	<< " ICACHE_MISS_CLEAN> Switch to ZOMBI state" << std::dec
1681	<< " / WAY = " << r_icache_miss_way.read()
1682	<< " / SET = " << r_icache_miss_set.read() << std::endl;
1683	}
1684	#endif
1685
1686	r_icache_fsm = ICACHE_MISS_WAIT;
1687	break;
1688	}
1689	//////////////////////
1690	case ICACHE_MISS_WAIT: // waiting response from VCI_RSP FSM
1691	{
1692	if (m_ireq.valid) m_cost_ins_miss_frz++;
1693
1694	// send cleanup victim request
1695	if (r_icache_cleanup_victim_req.read() and not r_icache_cc_send_req.read())
1696	{
1697	r_icache_cc_send_req = true;
1698	r_icache_cc_send_nline = r_icache_cleanup_victim_nline;
1699	r_icache_cc_send_way = r_icache_miss_way;
1700	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1701	r_icache_cleanup_victim_req = false;
1702	}
1703
1704	// coherence clack interrupt
1705	if (r_icache_clack_req.read())
1706	{
1707	r_icache_fsm = ICACHE_CC_CHECK;
1708	r_icache_fsm_save = r_icache_fsm.read();
1709	break;
1710	}
1711
1712	// coherence interrupt
1713	if (r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read() and not r_icache_cleanup_victim_req.read())
1714	{
1715	r_icache_fsm = ICACHE_CC_CHECK;
1716	r_icache_fsm_save = r_icache_fsm.read();
1717	break;
1718	}
1719
1720	if (r_vci_rsp_ins_error.read()) // bus error
1721	{
1722	r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS;
1723	r_mmu_ibvar = r_icache_vaddr_save.read();
1724	m_irsp.valid = true;
1725	m_irsp.error = true;
1726	r_vci_rsp_ins_error = false;
1727	r_icache_fsm = ICACHE_IDLE;
1728	}
1729	else if (r_vci_rsp_fifo_icache.rok()) // response available
1730	{
1731	r_icache_miss_word = 0;
1732	r_icache_fsm = ICACHE_MISS_DATA_UPDT;
1733	}
1734	break;
1735	}
1736	///////////////////////////
1737	case ICACHE_MISS_DATA_UPDT: // update the cache (one word per cycle)
1738	{
1739	if (m_ireq.valid) m_cost_ins_miss_frz++;
1740
1741	if (r_vci_rsp_fifo_icache.rok()) // response available
1742	{
1743
1744	#ifdef INSTRUMENTATION
1745	m_cpt_icache_data_write++;
1746	#endif
1747	r_icache.write(r_icache_miss_way.read(),
1748	r_icache_miss_set.read(),
1749	r_icache_miss_word.read(),
1750	r_vci_rsp_fifo_icache.read());
1751	#if DEBUG_ICACHE
1752	if (m_debug_icache_fsm)
1753	{
1754	std::cout << " <PROC " << name()
1755	<< " ICACHE_MISS_DATA_UPDT> Write one word:"
1756	<< " WDATA = " << std::hex << r_vci_rsp_fifo_icache.read()
1757	<< " WAY = " << r_icache_miss_way.read()
1758	<< " SET = " << r_icache_miss_set.read()
1759	<< " WORD = " << r_icache_miss_word.read() << std::endl;
1760	}
1761	#endif
1762	vci_rsp_fifo_icache_get = true;
1763	r_icache_miss_word = r_icache_miss_word.read() + 1;
1764
1765	if (r_icache_miss_word.read() == m_icache_words - 1) // last word
1766	{
1767	r_icache_fsm = ICACHE_MISS_DIR_UPDT;
1768	}
1769	}
1770	break;
1771	}
1772	//////////////////////////
1773	case ICACHE_MISS_DIR_UPDT: // Stalled if a victim line has been evicted,
1774	// and the cleanup ack has not been received,
1775	// as indicated by r_icache_miss_clack.
1776	// - If no matching coherence request (r_icache_miss_inval)
1777	// switch directory slot to VALID state.
1778	// - If matching coherence request, switch directory slot
1779	// to ZOMBI state, and send a cleanup request.
1780	{
1781	if (m_ireq.valid ) m_cost_ins_miss_frz++;
1782
1783	// send cleanup victim request
1784	if (r_icache_cleanup_victim_req.read() and not r_icache_cc_send_req.read())
1785	{
1786	r_icache_cc_send_req = true;
1787	r_icache_cc_send_nline = r_icache_cleanup_victim_nline;
1788	r_icache_cc_send_way = r_icache_miss_way;
1789	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1790	r_icache_cleanup_victim_req = false;
1791	}
1792
1793	// coherence clack interrupt
1794	if (r_icache_clack_req.read())
1795	{
1796	r_icache_fsm = ICACHE_CC_CHECK;
1797	r_icache_fsm_save = r_icache_fsm.read();
1798	break;
1799	}
1800
1801	// coherence interrupt
1802	if (r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read() and not r_icache_cleanup_victim_req.read())
1803	{
1804	r_icache_fsm = ICACHE_CC_CHECK;
1805	r_icache_fsm_save = r_icache_fsm.read();
1806	break;
1807	}
1808
1809	if (not r_icache_miss_clack.read()) // waiting cleanup acknowledge for victim line
1810	{
1811	if (r_icache_miss_inval) // Switch slot to ZOMBI state, and new cleanup
1812	{
1813	if (not r_icache_cc_send_req.read())
1814	{
1815	r_icache_miss_inval = false;
1816	// request cleanup
1817	r_icache_cc_send_req = true;
1818	r_icache_cc_send_nline = r_icache_vci_paddr.read() / (m_icache_words << 2);
1819	r_icache_cc_send_way = r_icache_miss_way.read();
1820	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1821
1822	#ifdef INSTRUMENTATION
1823	m_cpt_icache_dir_write++;
1824	#endif
1825	r_icache.write_dir(r_icache_vci_paddr.read(),
1826	r_icache_miss_way.read(),
1827	r_icache_miss_set.read(),
1828	CACHE_SLOT_STATE_ZOMBI);
1829	#if DEBUG_ICACHE
1830	if (m_debug_icache_fsm)
1831	{
1832	std::cout << " <PROC " << name()
1833	<< " ICACHE_MISS_DIR_UPDT> Switch cache slot to ZOMBI state"
1834	<< " PADDR = " << std::hex << r_icache_vci_paddr.read()
1835	<< " WAY = " << std::dec << r_icache_miss_way.read()
1836	<< " SET = " << r_icache_miss_set.read() << std::endl;
1837	}
1838	#endif
1839	}
1840	else
1841	break;
1842	}
1843	else // Switch slot to VALID state
1844	{
1845
1846	#ifdef INSTRUMENTATION
1847	m_cpt_icache_dir_write++;
1848	#endif
1849	r_icache.write_dir(r_icache_vci_paddr.read(),
1850	r_icache_miss_way.read(),
1851	r_icache_miss_set.read(),
1852	CACHE_SLOT_STATE_VALID);
1853	#if DEBUG_ICACHE
1854	if (m_debug_icache_fsm)
1855	{
1856	std::cout << " <PROC " << name()
1857	<< " ICACHE_MISS_DIR_UPDT> Switch cache slot to VALID state"
1858	<< " PADDR = " << std::hex << r_icache_vci_paddr.read()
1859	<< " WAY = " << std::dec << r_icache_miss_way.read()
1860	<< " SET = " << r_icache_miss_set.read() << std::endl;
1861	}
1862	#endif
1863	}
1864
1865	r_icache_fsm = ICACHE_IDLE;
1866	}
1867	break;
1868	}
1869	////////////////////
1870	case ICACHE_UNC_WAIT: // waiting a response to an uncacheable read from VCI_RSP FSM
1871	{
1872	// coherence clack interrupt
1873	if (r_icache_clack_req.read())
1874	{
1875	r_icache_fsm = ICACHE_CC_CHECK;
1876	r_icache_fsm_save = r_icache_fsm.read();
1877	break;
1878	}
1879
1880	// coherence interrupt
1881	if (r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read())
1882	{
1883	r_icache_fsm = ICACHE_CC_CHECK;
1884	r_icache_fsm_save = r_icache_fsm.read();
1885	break;
1886	}
1887
1888	if (r_vci_rsp_ins_error.read()) // bus error
1889	{
1890	r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS;
1891	r_mmu_ibvar = m_ireq.addr;
1892	r_vci_rsp_ins_error = false;
1893	m_irsp.valid = true;
1894	m_irsp.error = true;
1895	r_icache_fsm = ICACHE_IDLE;
1896	}
1897	else if (r_vci_rsp_fifo_icache.rok()) // instruction available
1898	{
1899	vci_rsp_fifo_icache_get = true;
1900	r_icache_fsm = ICACHE_IDLE;
1901	if (m_ireq.valid and
1902	(m_ireq.addr == r_icache_vaddr_save.read())) // request unmodified
1903	{
1904	m_irsp.valid = true;
1905	m_irsp.instruction = r_vci_rsp_fifo_icache.read();
1906	}
1907	}
1908	break;
1909	}
1910	/////////////////////
1911	case ICACHE_CC_CHECK: // This state is the entry point of a sub-fsm
1912	// handling coherence requests.
1913	// if there is a matching pending miss, it is
1914	// signaled in the r_icache_miss_inval flip-flop.
1915	// The return state is defined in r_icache_fsm_save.
1916	{
1917	paddr_t paddr = r_cc_receive_icache_nline.read() * m_icache_words * 4;
1918	paddr_t mask = ~((m_icache_words << 2) - 1);
1919
1920	// CLACK handler
1921	// We switch the directory slot to EMPTY state
1922	// and reset r_icache_miss_clack if the cleanup ack
1923	// is matching a pending miss.
1924	if (r_icache_clack_req.read())
1925	{
1926
1927	if (m_ireq.valid) m_cost_ins_miss_frz++;
1928
1929	#ifdef INSTRUMENTATION
1930	m_cpt_icache_dir_write++;
1931	#endif
1932	r_icache.write_dir(0,
1933	r_icache_clack_way.read(),
1934	r_icache_clack_set.read(),
1935	CACHE_SLOT_STATE_EMPTY);
1936
1937	if ((r_icache_miss_set.read() == r_icache_clack_set.read()) and
1938	(r_icache_miss_way.read() == r_icache_clack_way.read()))
1939	{
1940	r_icache_miss_clack = false;
1941	}
1942
1943	r_icache_clack_req = false;
1944
1945	// return to cc_save state
1946	r_icache_fsm = r_icache_fsm_save.read();
1947
1948	#if DEBUG_ICACHE
1949	if (m_debug_icache_fsm)
1950	{
1951	std::cout << " <PROC " << name()
1952	<< " ICACHE_CC_CHECK> CC_TYPE_CLACK slot returns to empty state"
1953	<< " set = " << r_icache_clack_set.read()
1954	<< " / way = " << r_icache_clack_way.read() << std::endl;
1955	}
1956	#endif
1957
1958	break;
1959	}
1960
1961	assert(not r_icache_cc_send_req.read() and "CC_SEND must be available in ICACHE_CC_CHECK");
1962
1963	// Match between MISS address and CC address
1964	if (r_cc_receive_icache_req.read() and
1965	((r_icache_fsm_save.read() == ICACHE_MISS_SELECT) or
1966	(r_icache_fsm_save.read() == ICACHE_MISS_WAIT) or
1967	(r_icache_fsm_save.read() == ICACHE_MISS_DIR_UPDT)) and
1968	((r_icache_vci_paddr.read() & mask) == (paddr & mask))) // matching
1969	{
1970	// signaling the matching
1971	r_icache_miss_inval = true;
1972
1973	// in case of update, go to CC_UPDT
1974	// JUST TO POP THE FIFO
1975	if (r_cc_receive_icache_type.read() == CC_TYPE_UPDT)
1976	{
1977	r_icache_fsm = ICACHE_CC_UPDT;
1978	r_icache_cc_word = r_cc_receive_word_idx.read();
1979
1980	// just pop the fifo , don't write in icache
1981	r_icache_cc_need_write = false;
1982	}
1983	// the request is dealt with
1984	else
1985	{
1986	r_cc_receive_icache_req = false;
1987	r_icache_fsm = r_icache_fsm_save.read();
1988	}
1989	#if DEBUG_ICACHE
1990	if (m_debug_icache_fsm)
1991	{
1992	std::cout << " <PROC " << name()
1993	<< " ICACHE_CC_CHECK> Coherence request matching a pending miss:"
1994	<< " PADDR = " << std::hex << paddr << std::endl;
1995	}
1996	#endif
1997	}
1998
1999	// CC request handler
2000
2001	int state = 0;
2002	size_t way = 0;
2003	size_t set = 0;
2004	size_t word = 0;
2005
2006	#ifdef INSTRUMENTATION
2007	m_cpt_icache_dir_read++;
2008	#endif
2009	r_icache.read_dir(paddr,
2010	&state,
2011	&way,
2012	&set,
2013	&word);
2014
2015	r_icache_cc_way = way;
2016	r_icache_cc_set = set;
2017
2018	if (state == CACHE_SLOT_STATE_VALID) // hit
2019	{
2020	// need to update the cache state
2021	if (r_cc_receive_icache_type.read() == CC_TYPE_UPDT) // hit update
2022	{
2023	r_icache_cc_need_write = true;
2024	r_icache_fsm = ICACHE_CC_UPDT;
2025	r_icache_cc_word = r_cc_receive_word_idx.read();
2026	}
2027	else if (r_cc_receive_icache_type.read() == CC_TYPE_INVAL) // hit inval
2028	{
2029	r_icache_fsm = ICACHE_CC_INVAL;
2030	}
2031	}
2032	else // miss
2033	{
2034	// multicast acknowledgement required in case of update
2035	if (r_cc_receive_icache_type.read() == CC_TYPE_UPDT)
2036	{
2037	r_icache_fsm = ICACHE_CC_UPDT;
2038	r_icache_cc_word = r_cc_receive_word_idx.read();
2039
2040	// just pop the fifo , don't write in icache
2041	r_icache_cc_need_write = false;
2042	}
2043	else // No response needed
2044	{
2045	r_cc_receive_icache_req = false;
2046	r_icache_fsm = r_icache_fsm_save.read();
2047	}
2048	}
2049	break;
2050	}
2051	/////////////////////
2052	case ICACHE_CC_INVAL: // hit inval : switch slot to ZOMBI state
2053	{
2054	assert (not r_icache_cc_send_req.read() &&
2055	"ERROR in ICACHE_CC_INVAL: the r_icache_cc_send_req "
2056	"must not be set");
2057
2058	#ifdef INSTRUMENTATION
2059	m_cpt_icache_dir_read++;
2060	#endif
2061
2062	// Switch slot state to ZOMBI and send CLEANUP command
2063	r_icache.write_dir(r_icache_cc_way.read(),
2064	r_icache_cc_set.read(),
2065	CACHE_SLOT_STATE_ZOMBI);
2066
2067	// coherence request completed
2068	r_icache_cc_send_req = true;
2069	r_icache_cc_send_nline = r_cc_receive_icache_nline.read();
2070	r_icache_cc_send_way = r_icache_cc_way.read();
2071	r_icache_cc_send_type = CC_TYPE_CLEANUP;
2072
2073	r_icache_fsm = r_icache_fsm_save.read();
2074
2075	#if DEBUG_ICACHE
2076	if (m_debug_icache_fsm)
2077	{
2078	std::cout << " <PROC " << name()
2079	<< " ICACHE_CC_INVAL> slot returns to ZOMBI state"
2080	<< " set = " << r_icache_cc_set.read()
2081	<< " / way = " << r_icache_cc_way.read() << std::endl;
2082	}
2083	#endif
2084
2085	break;
2086	}
2087	////////////////////
2088	case ICACHE_CC_UPDT: // hit update : write one word per cycle
2089	{
2090	assert (not r_icache_cc_send_req.read() &&
2091	"ERROR in ICACHE_CC_UPDT: the r_icache_cc_send_req "
2092	"must not be set");
2093
2094	if (not r_cc_receive_updt_fifo_be.rok()) break;
2095
2096
2097	size_t word = r_icache_cc_word.read();
2098	size_t way = r_icache_cc_way.read();
2099	size_t set = r_icache_cc_set.read();
2100
2101	if (r_icache_cc_need_write.read())
2102	{
2103	r_icache.write(way,
2104	set,
2105	word,
2106	r_cc_receive_updt_fifo_data.read(),
2107	r_cc_receive_updt_fifo_be.read());
2108
2109	r_icache_cc_word = word + 1;
2110
2111	#ifdef INSTRUMENTATION
2112	m_cpt_icache_data_write++;
2113	#endif
2114
2115	#if DEBUG_ICACHE
2116	if (m_debug_icache_fsm)
2117	{
2118	std::cout << " <PROC " << name()
2119	<< " ICACHE_CC_UPDT> Write one word "
2120	<< " set = " << r_icache_cc_set.read()
2121	<< " / way = " << r_icache_cc_way.read()
2122	<< " / word = " << r_icache_cc_word.read() << std::endl;
2123	}
2124	#endif
2125	}
2126
2127	if (r_cc_receive_updt_fifo_eop.read()) // last word
2128	{
2129	// no need to write in the cache anymore
2130	r_icache_cc_need_write = false;
2131
2132	// coherence request completed
2133	r_cc_receive_icache_req = false;
2134
2135	// request multicast acknowledgement
2136	r_icache_cc_send_req = true;
2137	r_icache_cc_send_nline = r_cc_receive_icache_nline.read();
2138	r_icache_cc_send_updt_tab_idx = r_cc_receive_icache_updt_tab_idx.read();
2139	r_icache_cc_send_type = CC_TYPE_MULTI_ACK;
2140
2141	r_icache_fsm = r_icache_fsm_save.read();
2142	}
2143	//consume fifo if not eop
2144	cc_receive_updt_fifo_get = true;
2145
2146	break;
2147	}
2148
2149	} // end switch r_icache_fsm
2150
2151	////////////////////////////////////////////////////////////////////////////////////
2152	// DCACHE FSM
2153	//
2154	// 1/ Coherence operations
2155	// They are handled as interrupts generated by the CC_RECEIVE FSM.
2156	// - There is a coherence request when r_tgt_dcache_req is set.
2157	// They are taken in IDLE, MISS_WAIT, MISS_DIR_UPDT, UNC_WAIT, LL_WAIT
2158	// and SC_WAIT states.
2159	// - There is a cleanup acknowledge request when r_cleanup_dcache_req is set.
2160	// They are taken in IDLE, MISS_SELECT, MISS_CLEAN, MISS_WAIT, MISS_DATA_UPDT,
2161	// MISS_DIR_UPDT, UNC_WAIT, LL_WAIT, SC_WAIT states.
2162	// - For both types of requests, actions associated to the pre-empted state
2163	// are not executed. The DCACHE FSM goes to the proper sub-FSM (CC_CHECK
2164	// or CC_CLACK) to execute the requested coherence operation, and returns
2165	// to the pre-empted state.
2166	//
2167	// 2/ TLB miss
2168	// The page tables are generally cacheable.
2169	// In case of miss in itlb or dtlb, the tlb miss is handled by a dedicated
2170	// sub-fsm (DCACHE_TLB_MISS state), that handle possible miss in DCACHE,
2171	// this sub-fsm implement the table-walk...
2172	//
2173	// 3/ processor requests
2174	// Processor requests are taken in IDLE state only.
2175	// The IDLE state implements a two stages pipe-line to handle write bursts:
2176	// - Both DTLB and DCACHE are accessed in stage P0 (if processor request valid).
2177	// - The registration in wbuf and the dcache update is done in stage P1
2178	// (if the processor request is a write).
2179	// The two r_dcache_wbuf_req and r_dcache_updt_req flip-flops define
2180	// the operations that must be done in P1 stage, and the access type
2181	// (read or write) to the DATA part of DCACHE depends on r_dcache_updt_req.
2182	// READ requests are delayed if a cache update is requested.
2183	// WRITE or SC requests can require a PTE Dirty bit update (in memory),
2184	// that is done (before handling the processor request) by a dedicated sub-fsm.
2185	// If a PTE is modified, both the itlb and dtlb are selectively, but sequencially
2186	// cleared by a dedicated sub_fsm (DCACHE_INVAL_TLB_SCAN state).
2187	//
2188	// 4/ Atomic instructions LL/SC
2189	// The LL/SC address are non cacheable (systematic access to memory).
2190	// The llsc buffer contains a registration for an active LL/SC operation
2191	// (with an address, a registration key, an aging counter and a valid bit).
2192	// - LL requests from the processor are transmitted as a one flit VCI command
2193	// (CMD_LOCKED_READ as CMD, and TYPE_LL as PKTID value). PLEN must
2194	// be 8 as the response is 2 flits long (data and registration key)
2195	// - SC requests from the processor are systematically transmitted to the
2196	// memory cache as 2 flits VCI command (CMD_STORE_COND as CMD, and TYPE_SC
2197	// as PKTID value). The first flit contains the registration key, the second
2198	// flit contains the data to write in case of success.
2199	// The cache is not updated, as this is done in case of success by the
2200	// coherence transaction.
2201	//
2202	// 5/ Non cacheable access:
2203	// This component implement a strong order between non cacheable access
2204	// (read or write) : A new non cacheable VCI transaction starts only when
2205	// the previous non cacheable transaction is completed. After send the VCI
2206	// transaction, the DCACHE FSM wait for the respone in the DCACHE_UNC_WAIT state.
2207	// So the processor is blocked until the respone arrives in CACHE L1.
2208	//
2209	// 6/ Error handling:
2210	// When the MMU is not activated, Read Bus Errors are synchronous events,
2211	// Some Write Bus Errors are synchronous events when the request is a non cacheable access
2212	// but some Write Bus Errors are asynchronous events when the request is cacheable access
2213	// (processor is not frozen).
2214	// - If a Read Bus Error or a Non Cacheable Write Bus Error is detected, the VCI_RSP FSM sets the
2215	// r_vci_rsp_data_error flip-flop, without writing any data in the
2216	// r_vci_rsp_fifo_dcache FIFO, and the synchronous error is signaled
2217	// by the DCACHE FSM.
2218	// - If a Cacheable Write Bus Error is detected, the VCI_RSP_FSM signals
2219	// the asynchronous error using the setWriteBerr() method.
2220	// When the MMU is activated bus error are rare events, as the MMU
2221	// checks the physical address before the VCI transaction starts.
2222	////////////////////////////////////////////////////////////////////////////////////////
2223
2224	// default value for m_drsp
2225	m_drsp.valid = false;
2226	m_drsp.error = false;
2227	m_drsp.rdata = 0;
2228
2229	switch (r_dcache_fsm.read())
2230	{
2231	case DCACHE_IDLE: // There are 10 conditions to exit the IDLE state :
2232	// 1) ITLB/DTLB inval request (update) => DCACHE_INVAL_TLB_SCAN
2233	// 2) Coherence request (TGT FSM) => DCACHE_CC_CHECK
2234	// 3) ITLB miss request (ICACHE FSM) => DCACHE_TLB_MISS
2235	// 4) XTN request (processor) => DCACHE_XTN_*
2236	// 5) DTLB miss (processor) => DCACHE_TLB_MISS
2237	// 6) Dirty bit update (processor) => DCACHE_DIRTY_GET_PTE
2238	// 7) Cacheable read miss (processor) => DCACHE_MISS_SELECT
2239	// 8) Uncacheable read/write (processor)=> DCACHE_UNC_WAIT
2240	// 9) LL access (processor) => DCACHE_LL_WAIT
2241	// 10) SC access (processor) => DCACHE_SC_WAIT
2242	//
2243	// There is a fixed priority to handle requests to DCACHE:
2244	// 1/ the ITLB/DTLB invalidate requests
2245	// 2/ the coherence requests,
2246	// 3/ the processor requests (including DTLB miss),
2247	// 4/ the ITLB miss requests,
2248	// The address space processor request are handled as follows:
2249	// - WRITE request is blocked if the Dirty bit mus be set.
2250	// If DTLB hit, the P1 stage is activated (writes WBUF, and
2251	// updates DCACHE if DCACHE hit) & processor request acknowledged.
2252	// - READ request generate a simultaneouss access to DCACHE.DATA
2253	// and DCACHE.DIR, but is delayed if DCACHE update required.
2254	//
2255	// There is 4 configurations defining the access type to
2256	// DTLB, DCACHE.DATA, and DCACHE.DIR, depending on the
2257	// dreq.valid (dreq) and r_dcache_updt_req (updt) signals:
2258	// dreq / updt / DTLB / DCACHE.DIR / DCACHE.DATA /
2259	// 0 / 0 / NOP / NOP / NOP /
2260	// 0 / 1 / NOP / NOP / WRITE /
2261	// 1 / 0 / READ / READ / NOP /
2262	// 1 / 1 / READ / READ / WRITE /
2263	// Those two registers are set at each cycle from the 3 signals
2264	// updt_request, wbuf_request, wbuf_write_miss.
2265	{
2266	paddr_t paddr;
2267	pte_info_t tlb_flags;
2268	size_t tlb_way;
2269	size_t tlb_set;
2270	paddr_t tlb_nline = 0;
2271	size_t cache_way;
2272	size_t cache_set;
2273	size_t cache_word;
2274	uint32_t cache_rdata = 0;
2275	bool tlb_hit = false;
2276	int cache_state = CACHE_SLOT_STATE_EMPTY;
2277
2278	bool tlb_inval_required = false; // request TLB inval after cache update
2279	bool wbuf_write_miss = false; // miss a WBUF write request
2280	bool updt_request = false; // request DCACHE update in P1 stage
2281	bool wbuf_request = false; // request WBUF write in P1 stage
2282
2283	// physical address computation : systematic DTLB access if activated
2284	paddr = (paddr_t) m_dreq.addr;
2285	if (m_dreq.valid)
2286	{
2287	if (r_mmu_mode.read() & DATA_TLB_MASK) // DTLB activated
2288	{
2289	tlb_hit = r_dtlb.translate(m_dreq.addr,
2290	&paddr,
2291	&tlb_flags,
2292	&tlb_nline,
2293	&tlb_way,
2294	&tlb_set);
2295	#ifdef INSTRUMENTATION
2296	m_cpt_dtlb_read++;
2297	#endif
2298	}
2299	else // identity mapping
2300	{
2301	// we take into account the paddr extension
2302	if (vci_param::N > 32)
2303	paddr = paddr \| ((paddr_t) (r_dcache_paddr_ext.read()) << 32);
2304	}
2305	} // end physical address computation
2306
2307	// systematic DCACHE access depending on r_dcache_updt_req (if activated)
2308	if (r_mmu_mode.read() & DATA_CACHE_MASK)
2309	{
2310
2311	if (m_dreq.valid and r_dcache_updt_req.read()) // read DIR and write DATA
2312	{
2313	r_dcache.read_dir(paddr,
2314	&cache_state,
2315	&cache_way,
2316	&cache_set,
2317	&cache_word);
2318
2319	r_dcache.write(r_dcache_save_cache_way.read(),
2320	r_dcache_save_cache_set.read(),
2321	r_dcache_save_cache_word.read(),
2322	r_dcache_save_wdata.read(),
2323	r_dcache_save_be.read());
2324	#ifdef INSTRUMENTATION
2325	m_cpt_dcache_dir_read++;
2326	m_cpt_dcache_data_write++;
2327	#endif
2328	}
2329	else if (m_dreq.valid and not r_dcache_updt_req.read()) // read DIR and DATA
2330	{
2331	r_dcache.read(paddr,
2332	&cache_rdata,
2333	&cache_way,
2334	&cache_set,
2335	&cache_word,
2336	&cache_state);
2337
2338	#ifdef INSTRUMENTATION
2339	m_cpt_dcache_dir_read++;
2340	m_cpt_dcache_data_read++;
2341	#endif
2342	}
2343	else if (not m_dreq.valid and r_dcache_updt_req.read()) // write DATA
2344	{
2345	r_dcache.write(r_dcache_save_cache_way.read(),
2346	r_dcache_save_cache_set.read(),
2347	r_dcache_save_cache_word.read(),
2348	r_dcache_save_wdata.read(),
2349	r_dcache_save_be.read());
2350	#ifdef INSTRUMENTATION
2351	m_cpt_dcache_data_write++;
2352	#endif
2353	}
2354	} // end dcache access
2355
2356	// DCACHE update in P1 stage can require ITLB / DTLB inval or flush
2357	if (r_dcache_updt_req.read())
2358	{
2359	size_t way = r_dcache_save_cache_way.read();
2360	size_t set = r_dcache_save_cache_set.read();
2361
2362	if (r_dcache_in_tlb[way * m_dcache_sets + set])
2363	{
2364	tlb_inval_required = true;
2365	r_dcache_tlb_inval_set = 0;
2366	r_dcache_tlb_inval_line = r_dcache_save_paddr.read() >>
2367	(uint32_log2(m_dcache_words << 2));
2368	r_dcache_in_tlb[way * m_dcache_sets + set] = false;
2369	}
2370	else if (r_dcache_contains_ptd[way * m_dcache_sets + set])
2371	{
2372	r_itlb.reset();
2373	r_dtlb.reset();
2374	r_dcache_contains_ptd[way * m_dcache_sets + set] = false;
2375	}
2376
2377	#if DEBUG_DCACHE
2378	if (m_debug_dcache_fsm)
2379	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
2380	<< " Cache update in P1 stage" << std::dec
2381	<< " / WAY = " << r_dcache_save_cache_way.read()
2382	<< " / SET = " << r_dcache_save_cache_set.read()
2383	<< " / WORD = " << r_dcache_save_cache_word.read() << std::hex
2384	<< " / WDATA = " << r_dcache_save_wdata.read()
2385	<< " / BE = " << r_dcache_save_be.read() << std::endl;
2386	#endif
2387	} // end test TLB inval
2388
2389	// Try WBUF update in P1 stage
2390	// Miss if the write request is non cacheable, and there is a pending
2391	// non cacheable write, or if the write buffer is full.
2392	if (r_dcache_wbuf_req.read())
2393	{
2394	bool wok = r_wbuf.write(r_dcache_save_paddr.read(),
2395	r_dcache_save_be.read(),
2396	r_dcache_save_wdata.read(),
2397	true);
2398	#ifdef INSTRUMENTATION
2399	m_cpt_wbuf_write++;
2400	#endif
2401	if (not wok ) // miss if write buffer full
2402	{
2403	wbuf_write_miss = true;
2404	}
2405	} // end WBUF update
2406
2407	// Computing the response to processor,
2408	// and the next value for r_dcache_fsm
2409
2410	// itlb/dtlb invalidation self-request
2411	if (tlb_inval_required)
2412	{
2413	r_dcache_fsm_scan_save = r_dcache_fsm.read();
2414	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
2415	}
2416
2417	// coherence clack request (from DSPIN CLACK)
2418	else if (r_dcache_clack_req.read())
2419	{
2420	r_dcache_fsm = DCACHE_CC_CHECK;
2421	r_dcache_fsm_cc_save = r_dcache_fsm.read();
2422	}
2423	// coherence request (from CC_RECEIVE FSM)
2424	else if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
2425	{
2426	r_dcache_fsm = DCACHE_CC_CHECK;
2427	r_dcache_fsm_cc_save = r_dcache_fsm.read();
2428	}
2429
2430	// processor request (READ, WRITE, LL, SC, XTN_READ, XTN_WRITE)
2431	// we don't take the processor request, and registers
2432	// are frozen in case of wbuf_write_miss
2433	else if (m_dreq.valid and not wbuf_write_miss)
2434	{
2435	// register processor request and DCACHE response
2436	r_dcache_save_vaddr = m_dreq.addr;
2437	r_dcache_save_be = m_dreq.be;
2438	r_dcache_save_wdata = m_dreq.wdata;
2439	r_dcache_save_paddr = paddr;
2440	r_dcache_save_cache_way = cache_way;
2441	r_dcache_save_cache_set = cache_set;
2442	r_dcache_save_cache_word = cache_word;
2443
2444	// READ XTN requests from processor
2445	// They are executed in this DCACHE_IDLE state.
2446	// The processor must not be in user mode
2447	if (m_dreq.type == iss_t::XTN_READ)
2448	{
2449	int xtn_opcode = (int) m_dreq.addr / 4;
2450
2451	// checking processor mode:
2452	if (m_dreq.mode == iss_t::MODE_USER)
2453	{
2454	r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION;
2455	r_mmu_dbvar = m_dreq.addr;
2456	m_drsp.valid = true;
2457	m_drsp.error = true;
2458	m_drsp.rdata = 0;
2459	r_dcache_fsm = DCACHE_IDLE;
2460	}
2461	else
2462	{
2463	switch (xtn_opcode)
2464	{
2465	case iss_t::XTN_INS_ERROR_TYPE:
2466	m_drsp.rdata = r_mmu_ietr.read();
2467	m_drsp.valid = true;
2468	m_drsp.error = false;
2469	break;
2470
2471	case iss_t::XTN_DATA_ERROR_TYPE:
2472	m_drsp.rdata = r_mmu_detr.read();
2473	m_drsp.valid = true;
2474	m_drsp.error = false;
2475	break;
2476
2477	case iss_t::XTN_INS_BAD_VADDR:
2478	m_drsp.rdata = r_mmu_ibvar.read();
2479	m_drsp.valid = true;
2480	m_drsp.error = false;
2481	break;
2482
2483	case iss_t::XTN_DATA_BAD_VADDR:
2484	m_drsp.rdata = r_mmu_dbvar.read();
2485	m_drsp.valid = true;
2486	m_drsp.error = false;
2487	break;
2488
2489	case iss_t::XTN_PTPR:
2490	m_drsp.rdata = r_mmu_ptpr.read();
2491	m_drsp.valid = true;
2492	m_drsp.error = false;
2493	break;
2494
2495	case iss_t::XTN_TLB_MODE:
2496	m_drsp.rdata = r_mmu_mode.read();
2497	m_drsp.valid = true;
2498	m_drsp.error = false;
2499	break;
2500
2501	case iss_t::XTN_MMU_PARAMS:
2502	m_drsp.rdata = r_mmu_params;
2503	m_drsp.valid = true;
2504	m_drsp.error = false;
2505	break;
2506
2507	case iss_t::XTN_MMU_RELEASE:
2508	m_drsp.rdata = r_mmu_release;
2509	m_drsp.valid = true;
2510	m_drsp.error = false;
2511	break;
2512
2513	case iss_t::XTN_MMU_WORD_LO:
2514	m_drsp.rdata = r_mmu_word_lo.read();
2515	m_drsp.valid = true;
2516	m_drsp.error = false;
2517	break;
2518
2519	case iss_t::XTN_MMU_WORD_HI:
2520	m_drsp.rdata = r_mmu_word_hi.read();
2521	m_drsp.valid = true;
2522	m_drsp.error = false;
2523	break;
2524
2525	case iss_t::XTN_DATA_PADDR_EXT:
2526	m_drsp.rdata = r_dcache_paddr_ext.read();
2527	m_drsp.valid = true;
2528	m_drsp.error = false;
2529	break;
2530
2531	case iss_t::XTN_INST_PADDR_EXT:
2532	m_drsp.rdata = r_icache_paddr_ext.read();
2533	m_drsp.valid = true;
2534	m_drsp.error = false;
2535	break;
2536
2537	case XTN_WDT_MAX:
2538	m_drsp.rdata = r_dcache_wdt_max.read();
2539	m_drsp.valid = true;
2540	m_drsp.error = false;
2541	break;
2542
2543	default:
2544	r_mmu_detr = MMU_READ_UNDEFINED_XTN;
2545	r_mmu_dbvar = m_dreq.addr;
2546	m_drsp.valid = true;
2547	m_drsp.error = true;
2548	m_drsp.rdata = 0;
2549	break;
2550	} // end switch xtn_opcode
2551	} // end else
2552	} // end if XTN_READ
2553
2554	// Handling WRITE XTN requests from processor.
2555	// They are not executed in this DCACHE_IDLE state
2556	// if they require access to the caches or the TLBs
2557	// that are already accessed.
2558	// Caches can be invalidated or flushed in user mode,
2559	// and the sync instruction can be executed in user mode
2560	else if (m_dreq.type == iss_t::XTN_WRITE)
2561	{
2562	int xtn_opcode = (int)m_dreq.addr / 4;
2563	r_dcache_xtn_opcode = xtn_opcode;
2564
2565	// checking processor mode:
2566	if ((m_dreq.mode == iss_t::MODE_USER) &&
2567	(xtn_opcode != iss_t::XTN_SYNC) &&
2568	(xtn_opcode != iss_t::XTN_DCACHE_INVAL) &&
2569	(xtn_opcode != iss_t::XTN_DCACHE_FLUSH) &&
2570	(xtn_opcode != iss_t::XTN_ICACHE_INVAL) &&
2571	(xtn_opcode != iss_t::XTN_ICACHE_FLUSH))
2572	{
2573	r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION;
2574	r_mmu_dbvar = m_dreq.addr;
2575	m_drsp.valid = true;
2576	m_drsp.error = true;
2577	m_drsp.rdata = 0;
2578	r_dcache_fsm = DCACHE_IDLE;
2579	}
2580	else
2581	{
2582	switch (xtn_opcode)
2583	{
2584	case iss_t::XTN_PTPR: // itlb & dtlb must be flushed
2585	r_dcache_xtn_req = true;
2586	r_dcache_fsm = DCACHE_XTN_SWITCH;
2587	break;
2588
2589	case iss_t::XTN_TLB_MODE: // no cache or tlb access
2590	r_mmu_mode = m_dreq.wdata;
2591	m_drsp.valid = true;
2592	r_dcache_fsm = DCACHE_IDLE;
2593	break;
2594
2595	case iss_t::XTN_DTLB_INVAL: // dtlb access
2596	r_dcache_fsm = DCACHE_XTN_DT_INVAL;
2597	break;
2598
2599	case iss_t::XTN_ITLB_INVAL: // itlb access
2600	r_dcache_xtn_req = true;
2601	r_dcache_fsm = DCACHE_XTN_IT_INVAL;
2602	break;
2603
2604	case iss_t::XTN_DCACHE_INVAL: // dcache, dtlb & itlb access
2605	r_dcache_fsm = DCACHE_XTN_DC_INVAL_VA;
2606	break;
2607
2608	case iss_t::XTN_MMU_DCACHE_PA_INV: // dcache, dtlb & itlb access
2609	r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA;
2610	if (sizeof(paddr_t) <= 32)
2611	{
2612	assert(r_mmu_word_hi.read() == 0 &&
2613	"high bits should be 0 for 32bit paddr");
2614	r_dcache_save_paddr = (paddr_t)r_mmu_word_lo.read();
2615	}
2616	else
2617	{
2618	r_dcache_save_paddr = (paddr_t)r_mmu_word_hi.read() << 32 \|
2619	(paddr_t)r_mmu_word_lo.read();
2620	}
2621	break;
2622
2623	case iss_t::XTN_DCACHE_FLUSH: // itlb and dtlb must be reset
2624	r_dcache_flush_count = 0;
2625	r_dcache_fsm = DCACHE_XTN_DC_FLUSH;
2626	break;
2627
2628	case iss_t::XTN_ICACHE_INVAL: // icache and itlb access
2629	r_dcache_xtn_req = true;
2630	r_dcache_fsm = DCACHE_XTN_IC_INVAL_VA;
2631	break;
2632
2633	case iss_t::XTN_MMU_ICACHE_PA_INV: // icache access
2634	r_dcache_xtn_req = true;
2635	r_dcache_fsm = DCACHE_XTN_IC_INVAL_PA;
2636	break;
2637
2638	case iss_t::XTN_ICACHE_FLUSH: // icache access
2639	r_dcache_xtn_req = true;
2640	r_dcache_fsm = DCACHE_XTN_IC_FLUSH;
2641	break;
2642
2643	case iss_t::XTN_SYNC: // wait until write buffer empty
2644	r_dcache_fsm = DCACHE_XTN_SYNC;
2645	break;
2646
2647	case iss_t::XTN_MMU_WORD_LO: // no cache or tlb access
2648	r_mmu_word_lo = m_dreq.wdata;
2649	m_drsp.valid = true;
2650	r_dcache_fsm = DCACHE_IDLE;
2651	break;
2652
2653	case iss_t::XTN_MMU_WORD_HI: // no cache or tlb access
2654	r_mmu_word_hi = m_dreq.wdata;
2655	m_drsp.valid = true;
2656	r_dcache_fsm = DCACHE_IDLE;
2657	break;
2658
2659	case iss_t::XTN_MMU_LL_RESET: // no cache or tlb access
2660	r_dcache_llsc_valid = false;
2661	m_drsp.valid = true;
2662	r_dcache_fsm = DCACHE_IDLE;
2663	break;
2664
2665	case iss_t::XTN_DATA_PADDR_EXT: // no cache or tlb access
2666	r_dcache_paddr_ext = m_dreq.wdata;
2667	m_drsp.valid = true;
2668	r_dcache_fsm = DCACHE_IDLE;
2669	break;
2670
2671	case iss_t::XTN_INST_PADDR_EXT: // no cache or tlb access
2672	r_dcache_xtn_req = true;
2673	r_dcache_fsm = DCACHE_XTN_IC_PADDR_EXT;
2674	break;
2675
2676	case iss_t::XTN_ICACHE_PREFETCH: // not implemented : no action
2677	case iss_t::XTN_DCACHE_PREFETCH: // not implemented : no action
2678	m_drsp.valid = true;
2679	r_dcache_fsm = DCACHE_IDLE;
2680	break;
2681
2682	case XTN_WDT_MAX:
2683	r_dcache_wdt_max = m_dreq.wdata;
2684	m_drsp.valid = true;
2685	r_dcache_fsm = DCACHE_IDLE;
2686	break;
2687
2688	case iss_t::XTN_DEBUG_MASK: // debug mask
2689	m_debug_dcache_fsm = ((m_dreq.wdata & 0x1) != 0);
2690	m_debug_icache_fsm = ((m_dreq.wdata & 0x2) != 0);
2691	m_debug_cmd_fsm = ((m_dreq.wdata & 0x4) != 0);
2692	m_drsp.valid = true;
2693	r_dcache_fsm = DCACHE_IDLE;
2694	break;
2695
2696	default:
2697	r_mmu_detr = MMU_WRITE_UNDEFINED_XTN;
2698	r_mmu_dbvar = m_dreq.addr;
2699	m_drsp.valid = true;
2700	m_drsp.error = true;
2701	r_dcache_fsm = DCACHE_IDLE;
2702	break;
2703	} // end switch xtn_opcode
2704	} // end else
2705	} // end if XTN_WRITE
2706
2707	// Handling processor requests to address space (READ/WRITE/LL/SC)
2708	// The dtlb and dcache can be activated or not.
2709	// We compute the cacheability, and check processor request validity:
2710	// - If DTLB not activated : cacheability is defined by the segment table,
2711	// and there is no access rights checking.
2712	// - If DTLB activated : cacheability is defined by the C bit in the PTE,
2713	// and the U & W bits of the PTE are checked, as well as the DTLB hit.
2714	// Jumps to the TLB_MISS sub-fsm in case of dtlb miss.
2715	else
2716	{
2717	bool valid_req;
2718	bool cacheable;
2719
2720	if (not (r_mmu_mode.read() & DATA_TLB_MASK)) // dtlb not activated
2721	{
2722	valid_req = true;
2723
2724	if (not (r_mmu_mode.read() & DATA_CACHE_MASK)) cacheable = false;
2725	else cacheable = m_cacheability_table[(uint64_t)m_dreq.addr];
2726	}
2727	else // dtlb activated
2728	{
2729	if (tlb_hit) // tlb hit
2730	{
2731	// cacheability
2732	if (not (r_mmu_mode.read() & DATA_CACHE_MASK)) cacheable = false;
2733	else cacheable = tlb_flags.c;
2734
2735	// access rights checking
2736	if (not tlb_flags.u and (m_dreq.mode == iss_t::MODE_USER))
2737	{
2738	if ((m_dreq.type == iss_t::DATA_READ) or
2739	(m_dreq.type == iss_t::DATA_LL))
2740	{
2741	r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION;
2742	}
2743	else
2744	{
2745	r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION;
2746	}
2747	valid_req = false;
2748	r_mmu_dbvar = m_dreq.addr;
2749	m_drsp.valid = true;
2750	m_drsp.error = true;
2751	m_drsp.rdata = 0;
2752	#if DEBUG_DCACHE
2753	if (m_debug_dcache_fsm)
2754	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
2755	<< " HIT in dtlb, but privilege violation" << std::endl;
2756	#endif
2757	}
2758	else if (not tlb_flags.w and
2759	((m_dreq.type == iss_t::DATA_WRITE) or
2760	(m_dreq.type == iss_t::DATA_SC)))
2761	{
2762	r_mmu_detr = MMU_WRITE_ACCES_VIOLATION;
2763	valid_req = false;
2764	r_mmu_dbvar = m_dreq.addr;
2765	m_drsp.valid = true;
2766	m_drsp.error = true;
2767	m_drsp.rdata = 0;
2768	#if DEBUG_DCACHE
2769	if (m_debug_dcache_fsm)
2770	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
2771	<< " HIT in dtlb, but writable violation" << std::endl;
2772	#endif
2773	}
2774	else
2775	{
2776	valid_req = true;
2777	}
2778	}
2779	else // tlb miss
2780	{
2781	valid_req = false;
2782	r_dcache_tlb_vaddr = m_dreq.addr;
2783	r_dcache_tlb_ins = false;
2784	r_dcache_fsm = DCACHE_TLB_MISS;
2785	}
2786	} // end DTLB activated
2787
2788	if (valid_req) // processor request is valid (after MMU check)
2789	{
2790	// READ request
2791	// The read requests are taken only if there is no cache update.
2792	// We request a VCI transaction to CMD FSM if miss or uncachable
2793
2794	if (((m_dreq.type == iss_t::DATA_READ))
2795	and not r_dcache_updt_req.read())
2796	{
2797	if (cacheable) // cacheable read
2798	{
2799	if (cache_state == CACHE_SLOT_STATE_EMPTY) // cache miss
2800	{
2801	#ifdef INSTRUMENTATION
2802	m_cpt_dcache_miss++;
2803	#endif
2804	// request a VCI DMISS transaction
2805	r_dcache_vci_wdt_trdid = r_dcache_wdt_timeout.read();
2806
2807	r_dcache_vci_paddr = paddr;
2808	r_dcache_vci_miss_req = true;
2809	r_dcache_miss_type = PROC_MISS;
2810	r_dcache_fsm = DCACHE_MISS_SELECT;
2811	#if DEBUG_DCACHE
2812	if (m_debug_dcache_fsm)
2813	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
2814	<< " READ MISS in dcache"
2815	<< " / PADDR = " << std::hex << paddr << std::endl;
2816	#endif
2817	}
2818	else if (cache_state == CACHE_SLOT_STATE_ZOMBI) // pending cleanup
2819	{
2820	// stalled until cleanup is acknowledged
2821	r_dcache_fsm = DCACHE_IDLE;
2822	#if DEBUG_DCACHE
2823	if (m_debug_dcache_fsm)
2824	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
2825	<< " Pending cleanup, stalled until cleanup acknowledge"
2826	<< " / PADDR = " << std::hex << paddr << std::endl;
2827	#endif
2828	}
2829	else // cache hit
2830	{
2831	#ifdef INSTRUMENTATION
2832	m_cpt_data_read++;
2833	#endif
2834	// returns data to processor
2835	m_drsp.valid = true;
2836	m_drsp.error = false;
2837	m_drsp.rdata = cache_rdata;
2838	#if DEBUG_DCACHE
2839	if (m_debug_dcache_fsm)
2840	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
2841	<< " READ HIT in dcache"
2842	<< " : PADDR = " << std::hex << paddr
2843	<< " / DATA = " << std::hex << cache_rdata << std::endl;
2844	#endif
2845	}
2846	}
2847	else // uncacheable read
2848	{
2849	r_dcache_vci_paddr = paddr;
2850	r_dcache_vci_unc_be = m_dreq.be;
2851	r_dcache_vci_unc_write = false;
2852	r_dcache_vci_unc_req = true;
2853	r_dcache_fsm = DCACHE_UNC_WAIT;
2854
2855	// reset to 0 the watchdog timer
2856	r_dcache_vci_wdt_trdid = r_dcache_wdt_timeout.read();
2857	r_dcache_wdt = 0;
2858	#if DEBUG_DCACHE
2859	if (m_debug_dcache_fsm)
2860	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
2861	<< " READ UNCACHEABLE in dcache"
2862	<< " / PADDR = " << std::hex << paddr << std::endl;
2863	#endif
2864	}
2865	} // end READ
2866
2867	// LL request (non cachable)
2868	// We request a VCI LL transaction to CMD FSM and register
2869	// the LL/SC operation in llsc buffer.
2870	else if (m_dreq.type == iss_t::DATA_LL)
2871	{
2872	// register paddr in LLSC buffer
2873	r_dcache_llsc_paddr = paddr;
2874	r_dcache_llsc_count = LLSC_TIMEOUT;
2875	r_dcache_llsc_valid = true;
2876
2877	// request an LL VCI transaction and go to DCACHE_LL_WAIT state
2878	r_dcache_vci_ll_req = true;
2879	r_dcache_vci_paddr = paddr;
2880	r_dcache_ll_rsp_count = 0;
2881	r_dcache_fsm = DCACHE_LL_WAIT;
2882
2883	}// end LL
2884
2885	// WRITE request:
2886	// If the TLB is activated and the PTE Dirty bit is not set, we stall
2887	// the processor and set the Dirty bit before handling the write request,
2888	// going to the DCACHE_DIRTY_GT_PTE state.
2889	// If we don't need to set the Dirty bit, we can acknowledge
2890	// the processor request, as the write arguments (including the
2891	// physical address) are registered in r_dcache_save registers,
2892	// and the write will be done in the P1 pipeline stage.
2893	else if (m_dreq.type == iss_t::DATA_WRITE)
2894	{
2895	if ((r_mmu_mode.read() & DATA_TLB_MASK)
2896	and not tlb_flags.d) // Dirty bit must be set
2897	{
2898	// The PTE physical address is obtained from the nline value (dtlb),
2899	// and from the virtual address (word index)
2900	if (tlb_flags.b ) // PTE1
2901	{
2902	r_dcache_dirty_paddr = (paddr_t)(tlb_nline * (m_dcache_words << 2)) \|
2903	(paddr_t)((m_dreq.addr >> 19) & 0x3c);
2904	}
2905	else // PTE2
2906	{
2907	r_dcache_dirty_paddr = (paddr_t) (tlb_nline * (m_dcache_words << 2)) \|
2908	(paddr_t) ((m_dreq.addr >> 9) & 0x38);
2909	}
2910	r_dcache_fsm = DCACHE_DIRTY_GET_PTE;
2911	}
2912	else // Write request accepted
2913	{
2914	#ifdef INSTRUMENTATION
2915	m_cpt_data_write++;
2916	#endif
2917	// cleaning llsc buffer if address matching
2918	if (paddr == r_dcache_llsc_paddr.read())
2919	r_dcache_llsc_valid = false;
2920
2921	if (not cacheable) // uncacheable write
2922	{
2923	r_dcache_vci_paddr = paddr;
2924	r_dcache_vci_wdata = m_dreq.wdata;
2925	r_dcache_vci_unc_write = true;
2926	r_dcache_vci_unc_be = m_dreq.be;
2927	r_dcache_vci_unc_req = true;
2928	r_dcache_fsm = DCACHE_UNC_WAIT;
2929
2930	// reset to 0 the watchdog timer
2931	r_dcache_vci_wdt_trdid = r_dcache_wdt_timeout.read();
2932	r_dcache_wdt = 0;
2933	}
2934	else
2935	{
2936	// response to processor
2937	m_drsp.valid = true;
2938	// activating P1 stage
2939	wbuf_request = true;
2940	updt_request = (cache_state == CACHE_SLOT_STATE_VALID);
2941	}
2942	}
2943	} // end WRITE
2944
2945	// SC request:
2946	// If the TLB is activated and the PTE Dirty bit is not set, we stall
2947	// the processor and set the Dirty bit before handling the write request,
2948	// going to the DCACHE_DIRTY_GT_PTE state.
2949	// If we don't need to set the Dirty bit, we test the llsc buffer:
2950	// If failure, we send a negative response to processor.
2951	// If success, we request a SC transaction to CMD FSM and go
2952	// to DCACHE_SC_WAIT state.
2953	// We don't check a possible write hit in dcache, as the cache update
2954	// is done by the coherence transaction induced by the SC...
2955	else if (m_dreq.type == iss_t::DATA_SC)
2956	{
2957	if ((r_mmu_mode.read() & DATA_TLB_MASK)
2958	and not tlb_flags.d) // Dirty bit must be set
2959	{
2960	// The PTE physical address is obtained from the nline value (dtlb),
2961	// and the word index (virtual address)
2962	if (tlb_flags.b) // PTE1
2963	{
2964	r_dcache_dirty_paddr = (paddr_t) (tlb_nline * (m_dcache_words << 2)) \|
2965	(paddr_t) ((m_dreq.addr >> 19) & 0x3c);
2966	}
2967	else // PTE2
2968	{
2969	r_dcache_dirty_paddr = (paddr_t) (tlb_nline * (m_dcache_words << 2)) \|
2970	(paddr_t) ((m_dreq.addr >> 9) & 0x38);
2971	}
2972	r_dcache_fsm = DCACHE_DIRTY_GET_PTE;
2973	m_drsp.valid = false;
2974	m_drsp.error = false;
2975	m_drsp.rdata = 0;
2976	}
2977	else // SC request accepted
2978	{
2979	#ifdef INSTRUMENTATION
2980	m_cpt_data_sc++;
2981	#endif
2982	// checking local success
2983	if (r_dcache_llsc_valid.read() and
2984	(r_dcache_llsc_paddr.read() == paddr)) // local success
2985	{
2986	// request an SC CMD and go to DCACHE_SC_WAIT state
2987	r_dcache_vci_paddr = paddr;
2988	r_dcache_vci_sc_req = true;
2989	r_dcache_vci_sc_data = m_dreq.wdata;
2990	r_dcache_fsm = DCACHE_SC_WAIT;
2991	}
2992	else // local fail
2993	{
2994	m_drsp.valid = true;
2995	m_drsp.error = false;
2996	m_drsp.rdata = 0x1;
2997	}
2998	}
2999	} // end SC
3000	} // end valid_req
3001	} // end if read/write/ll/sc request
3002	} // end processor request
3003
3004	// itlb miss request
3005	else if (r_icache_tlb_miss_req.read() and not wbuf_write_miss)
3006	{
3007	r_dcache_tlb_ins = true;
3008	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
3009	r_dcache_fsm = DCACHE_TLB_MISS;
3010	}
3011
3012	// Computing requests for P1 stage : r_dcache_wbuf_req & r_dcache_updt_req
3013	r_dcache_updt_req = updt_request;
3014	r_dcache_wbuf_req = wbuf_request or
3015	(r_dcache_wbuf_req.read() and wbuf_write_miss);
3016	break;
3017	}
3018	/////////////////////
3019	case DCACHE_TLB_MISS: // This is the entry point for the sub-fsm handling all tlb miss.
3020	// Input arguments are:
3021	// - r_dcache_tlb_vaddr
3022	// - r_dcache_tlb_ins (true when itlb miss)
3023	// The sub-fsm access the dcache to find the missing TLB entry,
3024	// and activates the cache miss procedure in case of miss.
3025	// It bypass the first level page table access if possible.
3026	// It uses atomic access to update the R/L access bits
3027	// in the page table if required.
3028	// It directly updates the itlb or dtlb, and writes into the
3029	// r_mmu_ins_* or r_mmu_data* error reporting registers.
3030	{
3031	uint32_t ptba = 0;
3032	bool bypass;
3033	paddr_t pte_paddr;
3034
3035	// evaluate bypass in order to skip first level page table access
3036	if (r_dcache_tlb_ins.read()) // itlb miss
3037	{
3038	bypass = r_itlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba);
3039	}
3040	else // dtlb miss
3041	{
3042	bypass = r_dtlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba);
3043	}
3044
3045	if (not bypass) // Try to read PTE1/PTD1 in dcache
3046	{
3047	pte_paddr = (((paddr_t) r_mmu_ptpr.read()) << (INDEX1_NBITS + 2)) \|
3048	((((paddr_t) r_dcache_tlb_vaddr.read()) >> PAGE_M_NBITS) << 2);
3049	r_dcache_tlb_paddr = pte_paddr;
3050	r_dcache_fsm = DCACHE_TLB_PTE1_GET;
3051	}
3052	else // Try to read PTE2 in dcache
3053	{
3054	pte_paddr = (paddr_t) ptba << PAGE_K_NBITS \|
3055	(paddr_t) (r_dcache_tlb_vaddr.read() & PTD_ID2_MASK) >> (PAGE_K_NBITS - 3);
3056	r_dcache_tlb_paddr = pte_paddr;
3057	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
3058	}
3059
3060	#if DEBUG_DCACHE
3061	if (m_debug_dcache_fsm)
3062	{
3063	if (r_dcache_tlb_ins.read())
3064	std::cout << " <PROC " << name() << " DCACHE_TLB_MISS> ITLB miss";
3065	else
3066	std::cout << " <PROC " << name() << " DCACHE_TLB_MISS> DTLB miss";
3067	std::cout << " / VADDR = " << std::hex << r_dcache_tlb_vaddr.read()
3068	<< " / ptpr = " << (((paddr_t)r_mmu_ptpr.read()) << (INDEX1_NBITS+2))
3069	<< " / BYPASS = " << bypass
3070	<< " / PTE_ADR = " << pte_paddr << std::endl;
3071	}
3072	#endif
3073
3074	break;
3075	}
3076	/////////////////////////
3077	case DCACHE_TLB_PTE1_GET: // try to read a PT1 entry in dcache
3078	{
3079	// coherence clack request (from DSPIN CLACK)
3080	if (r_dcache_clack_req.read())
3081	{
3082	r_dcache_fsm = DCACHE_CC_CHECK;
3083	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3084	break;
3085	}
3086
3087	// coherence request (from CC_RECEIVE FSM)
3088	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
3089	{
3090	r_dcache_fsm = DCACHE_CC_CHECK;
3091	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3092	break;
3093	}
3094
3095	uint32_t entry;
3096	size_t way;
3097	size_t set;
3098	size_t word;
3099	int cache_state;
3100	r_dcache.read(r_dcache_tlb_paddr.read(),
3101	&entry,
3102	&way,
3103	&set,
3104	&word,
3105	&cache_state);
3106	#ifdef INSTRUMENTATION
3107	m_cpt_dcache_data_read++;
3108	m_cpt_dcache_dir_read++;
3109	#endif
3110	if (cache_state == CACHE_SLOT_STATE_VALID) // hit in dcache
3111	{
3112	if (not (entry & PTE_V_MASK)) // unmapped
3113	{
3114	if (r_dcache_tlb_ins.read())
3115	{
3116	r_mmu_ietr = MMU_READ_PT1_UNMAPPED;
3117	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3118	r_icache_tlb_miss_req = false;
3119	r_icache_tlb_rsp_error = true;
3120	}
3121	else
3122	{
3123	r_mmu_detr = MMU_READ_PT1_UNMAPPED;
3124	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3125	m_drsp.valid = true;
3126	m_drsp.error = true;
3127	}
3128	r_dcache_fsm = DCACHE_IDLE;
3129
3130	#if DEBUG_DCACHE
3131	if (m_debug_dcache_fsm)
3132	{
3133	std::cout << " <PROC " << name()
3134	<< " DCACHE_TLB_PTE1_GET> HIT in dcache, but unmapped"
3135	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
3136	<< std::dec << " / way = " << way
3137	<< std::dec << " / set = " << set
3138	<< std::dec << " / word = " << word
3139	<< std::hex << " / PTE1 = " << entry << std::endl;
3140	}
3141	#endif
3142
3143	}
3144	else if (entry & PTE_T_MASK) // PTD : me must access PT2
3145	{
3146	// mark the cache line ac containing a PTD
3147	r_dcache_contains_ptd[m_dcache_sets * way + set] = true;
3148
3149	// register bypass
3150	if (r_dcache_tlb_ins.read()) // itlb
3151	{
3152	r_itlb.set_bypass(r_dcache_tlb_vaddr.read(),
3153	entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1),
3154	r_dcache_tlb_paddr.read() / (m_icache_words << 2));
3155	}
3156	else // dtlb
3157	{
3158	r_dtlb.set_bypass(r_dcache_tlb_vaddr.read(),
3159	entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1),
3160	r_dcache_tlb_paddr.read() / (m_dcache_words << 2));
3161	}
3162	r_dcache_tlb_paddr =
3163	(paddr_t)(entry & ((1 << (m_paddr_nbits - PAGE_K_NBITS)) - 1)) << PAGE_K_NBITS \|
3164	(paddr_t)(((r_dcache_tlb_vaddr.read() & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3);
3165	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
3166
3167	#if DEBUG_DCACHE
3168	if (m_debug_dcache_fsm)
3169	{
3170	std::cout << " <PROC " << name()
3171	<< " DCACHE_TLB_PTE1_GET> HIT in dcache"
3172	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
3173	<< std::dec << " / way = " << way
3174	<< std::dec << " / set = " << set
3175	<< std::dec << " / word = " << word
3176	<< std::hex << " / PTD = " << entry << std::endl;
3177	}
3178	#endif
3179	}
3180	else // PTE1 : we must update the TLB
3181	{
3182	r_dcache_in_tlb[m_icache_sets * way + set] = true;
3183	r_dcache_tlb_pte_flags = entry;
3184	r_dcache_tlb_cache_way = way;
3185	r_dcache_tlb_cache_set = set;
3186	r_dcache_tlb_cache_word = word;
3187	r_dcache_fsm = DCACHE_TLB_PTE1_SELECT;
3188
3189	#if DEBUG_DCACHE
3190	if (m_debug_dcache_fsm)
3191	{
3192	std::cout << " <PROC " << name()
3193	<< " DCACHE_TLB_PTE1_GET> HIT in dcache"
3194	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
3195	<< std::dec << " / way = " << way
3196	<< std::dec << " / set = " << set
3197	<< std::dec << " / word = " << word
3198	<< std::hex << " / PTE1 = " << entry << std::endl;
3199	}
3200	#endif
3201	}
3202	}
3203	else if (cache_state == CACHE_SLOT_STATE_ZOMBI) // pending cleanup
3204	{
3205	// stalled until cleanup is acknowledged
3206	r_dcache_fsm = DCACHE_TLB_PTE1_GET;
3207	}
3208	else // we must load the missing cache line in dcache
3209	{
3210	r_dcache_vci_wdt_trdid = r_dcache_wdt_timeout.read();
3211
3212	r_dcache_vci_miss_req = true;
3213	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
3214	r_dcache_save_paddr = r_dcache_tlb_paddr.read();
3215	r_dcache_miss_type = PTE1_MISS;
3216	r_dcache_fsm = DCACHE_MISS_SELECT;
3217
3218	#if DEBUG_DCACHE
3219	if (m_debug_dcache_fsm)
3220	{
3221	std::cout << " <PROC " << name()
3222	<< " DCACHE_TLB_PTE1_GET> MISS in dcache:"
3223	<< " PTE1 address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
3224	}
3225	#endif
3226	}
3227	break;
3228	}
3229	////////////////////////////
3230	case DCACHE_TLB_PTE1_SELECT: // select a slot for PTE1
3231	{
3232	size_t way;
3233	size_t set;
3234
3235	if (r_dcache_tlb_ins.read())
3236	{
3237	r_itlb.select(r_dcache_tlb_vaddr.read(),
3238	true, // PTE1
3239	&way,
3240	&set);
3241	#ifdef INSTRUMENTATION
3242	m_cpt_itlb_read++;
3243	#endif
3244	}
3245	else
3246	{
3247	r_dtlb.select(r_dcache_tlb_vaddr.read(),
3248	true, // PTE1
3249	&way,
3250	&set);
3251	#ifdef INSTRUMENTATION
3252	m_cpt_dtlb_read++;
3253	#endif
3254	}
3255	r_dcache_tlb_way = way;
3256	r_dcache_tlb_set = set;
3257	r_dcache_fsm = DCACHE_TLB_PTE1_UPDT;
3258
3259	#if DEBUG_DCACHE
3260	if (m_debug_dcache_fsm)
3261	{
3262	if (r_dcache_tlb_ins.read())
3263	std::cout << " <PROC " << name()
3264	<< " DCACHE_TLB_PTE1_SELECT> Select a slot in ITLB:";
3265	else
3266	std::cout << " <PROC " << name()
3267	<< ".DCACHE_TLB_PTE1_SELECT> Select a slot in DTLB:";
3268	std::cout << " way = " << std::dec << way
3269	<< " / set = " << set << std::endl;
3270	}
3271	#endif
3272	break;
3273	}
3274	//////////////////////////
3275	case DCACHE_TLB_PTE1_UPDT: // write a new PTE1 in tlb after testing the L/R bit
3276	// - if L/R bit already set, exit the sub-fsm.
3277	// - if not, we update the page table but we dont write
3278	// neither in DCACHE, nor in TLB, as this will be done by
3279	// the coherence mechanism.
3280	{
3281	paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words) + 2);
3282	uint32_t pte = r_dcache_tlb_pte_flags.read();
3283	bool pt_updt = false;
3284	bool local = true;
3285
3286	// We should compute the access locality:
3287	// The PPN MSB bits define the destination cluster index.
3288	// The m_srcid MSB bits define the source cluster index.
3289	// The number of bits to compare depends on the number of clusters,
3290	// and can be obtained in the mapping table.
3291	// As long as this computation is not done, all access are local.
3292
3293	if (local) // local access
3294	{
3295	if (not ((pte & PTE_L_MASK) == PTE_L_MASK)) // we must set the L bit
3296	{
3297	pt_updt = true;
3298	r_dcache_vci_cas_old = pte;
3299	r_dcache_vci_cas_new = pte \| PTE_L_MASK;
3300	pte = pte \| PTE_L_MASK;
3301	r_dcache_tlb_pte_flags = pte;
3302	}
3303	}
3304	else // remote access
3305	{
3306	if (not ((pte & PTE_R_MASK) == PTE_R_MASK)) // we must set the R bit
3307	{
3308	pt_updt = true;
3309	r_dcache_vci_cas_old = pte;
3310	r_dcache_vci_cas_new = pte \| PTE_R_MASK;
3311	pte = pte \| PTE_R_MASK;
3312	r_dcache_tlb_pte_flags = pte;
3313	}
3314	}
3315
3316	if (not pt_updt) // update TLB and return
3317	{
3318	if (r_dcache_tlb_ins.read())
3319	{
3320	r_itlb.write(true, // 2M page
3321	pte,
3322	0, // argument unused for a PTE1
3323	r_dcache_tlb_vaddr.read(),
3324	r_dcache_tlb_way.read(),
3325	r_dcache_tlb_set.read(),
3326	nline);
3327	#ifdef INSTRUMENTATION
3328	m_cpt_itlb_write++;
3329	#endif
3330
3331	#if DEBUG_DCACHE
3332	if (m_debug_dcache_fsm)
3333	{
3334	std::cout << " <PROC " << name()
3335	<< " DCACHE_TLB_PTE1_UPDT> write PTE1 in ITLB"
3336	<< " / set = " << std::dec << r_dcache_tlb_set.read()
3337	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3338	r_itlb.printTrace();
3339	}
3340	#endif
3341	}
3342	else
3343	{
3344	r_dtlb.write(true, // 2M page
3345	pte,
3346	0, // argument unused for a PTE1
3347	r_dcache_tlb_vaddr.read(),
3348	r_dcache_tlb_way.read(),
3349	r_dcache_tlb_set.read(),
3350	nline);
3351	#ifdef INSTRUMENTATION
3352	m_cpt_dtlb_write++;
3353	#endif
3354
3355	#if DEBUG_DCACHE
3356	if (m_debug_dcache_fsm)
3357	{
3358	std::cout << " <PROC " << name()
3359	<< " DCACHE_TLB_PTE1_UPDT> write PTE1 in DTLB"
3360	<< " / set = " << std::dec << r_dcache_tlb_set.read()
3361	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3362	r_dtlb.printTrace();
3363	}
3364	#endif
3365	}
3366	r_dcache_fsm = DCACHE_TLB_RETURN;
3367	}
3368	else // update page table but not TLB
3369	{
3370	r_dcache_fsm = DCACHE_TLB_LR_UPDT;
3371
3372	#if DEBUG_DCACHE
3373	if (m_debug_dcache_fsm)
3374	{
3375	std::cout << " <PROC " << name()
3376	<< " DCACHE_TLB_PTE1_UPDT> L/R bit update required"
3377	<< std::endl;
3378	}
3379	#endif
3380	}
3381	break;
3382	}
3383	/////////////////////////
3384	case DCACHE_TLB_PTE2_GET: // Try to get a PTE2 (64 bits) in the dcache
3385	{
3386	// coherence clack request (from DSPIN CLACK)
3387	if (r_dcache_clack_req.read())
3388	{
3389	r_dcache_fsm = DCACHE_CC_CHECK;
3390	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3391	break;
3392	}
3393
3394	// coherence request (from CC_RECEIVE FSM)
3395	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
3396	{
3397	r_dcache_fsm = DCACHE_CC_CHECK;
3398	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3399	break;
3400	}
3401
3402	uint32_t pte_flags;
3403	uint32_t pte_ppn;
3404	size_t way;
3405	size_t set;
3406	size_t word;
3407	int cache_state;
3408
3409	r_dcache.read(r_dcache_tlb_paddr.read(),
3410	&pte_flags,
3411	&pte_ppn,
3412	&way,
3413	&set,
3414	&word,
3415	&cache_state);
3416	#ifdef INSTRUMENTATION
3417	m_cpt_dcache_data_read++;
3418	m_cpt_dcache_dir_read++;
3419	#endif
3420	if (cache_state == CACHE_SLOT_STATE_VALID) // hit in dcache
3421	{
3422	if (not (pte_flags & PTE_V_MASK)) // unmapped
3423	{
3424	if (r_dcache_tlb_ins.read())
3425	{
3426	r_mmu_ietr = MMU_READ_PT2_UNMAPPED;
3427	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3428	r_icache_tlb_miss_req = false;
3429	r_icache_tlb_rsp_error = true;
3430	}
3431	else
3432	{
3433	r_mmu_detr = MMU_READ_PT2_UNMAPPED;
3434	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3435	m_drsp.valid = true;
3436	m_drsp.error = true;
3437	}
3438	r_dcache_fsm = DCACHE_IDLE;
3439
3440	#if DEBUG_DCACHE
3441	if (m_debug_dcache_fsm)
3442	{
3443	std::cout << " <PROC " << name()
3444	<< " DCACHE_TLB_PTE2_GET> HIT in dcache, but PTE unmapped"
3445	<< " PTE_FLAGS = " << std::hex << pte_flags
3446	<< " PTE_PPN = " << std::hex << pte_ppn << std::endl;
3447	}
3448	#endif
3449	}
3450	else // mapped : we must update the TLB
3451	{
3452	r_dcache_in_tlb[m_dcache_sets * way + set] = true;
3453	r_dcache_tlb_pte_flags = pte_flags;
3454	r_dcache_tlb_pte_ppn = pte_ppn;
3455	r_dcache_tlb_cache_way = way;
3456	r_dcache_tlb_cache_set = set;
3457	r_dcache_tlb_cache_word = word;
3458	r_dcache_fsm = DCACHE_TLB_PTE2_SELECT;
3459
3460	#if DEBUG_DCACHE
3461	if (m_debug_dcache_fsm)
3462	{
3463	std::cout << " <PROC " << name()
3464	<< " DCACHE_TLB_PTE2_GET> HIT in dcache:"
3465	<< " PTE_FLAGS = " << std::hex << pte_flags
3466	<< " PTE_PPN = " << std::hex << pte_ppn << std::endl;
3467	}
3468	#endif
3469	}
3470	}
3471	else if (cache_state == CACHE_SLOT_STATE_ZOMBI) // pending cleanup
3472	{
3473	// stalled until cleanup is acknowledged
3474	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
3475
3476	#if DEBUG_DCACHE
3477	if (m_debug_dcache_fsm)
3478	{
3479	std::cout << " <PROC " << name()
3480	<< " DCACHE_TLB_PTE2_GET> ZOMBI in dcache: waiting cleanup ack"
3481	<< std::endl;
3482	}
3483	#endif
3484	}
3485	else // we must load the missing cache line in dcache
3486	{
3487	r_dcache_vci_wdt_trdid = r_dcache_wdt_timeout.read();
3488
3489	r_dcache_fsm = DCACHE_MISS_SELECT;
3490	r_dcache_vci_miss_req = true;
3491	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
3492	r_dcache_save_paddr = r_dcache_tlb_paddr.read();
3493	r_dcache_miss_type = PTE2_MISS;
3494
3495	#if DEBUG_DCACHE
3496	if (m_debug_dcache_fsm)
3497	{
3498	std::cout << " <PROC " << name()
3499	<< " DCACHE_TLB_PTE2_GET> MISS in dcache:"
3500	<< " PTE address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
3501	}
3502	#endif
3503	}
3504	break;
3505	}
3506	////////////////////////////
3507	case DCACHE_TLB_PTE2_SELECT: // select a slot for PTE2
3508	{
3509	size_t way;
3510	size_t set;
3511
3512	if (r_dcache_tlb_ins.read())
3513	{
3514	r_itlb.select(r_dcache_tlb_vaddr.read(),
3515	false, // PTE2
3516	&way,
3517	&set);
3518	#ifdef INSTRUMENTATION
3519	m_cpt_itlb_read++;
3520	#endif
3521	}
3522	else
3523	{
3524	r_dtlb.select(r_dcache_tlb_vaddr.read(),
3525	false, // PTE2
3526	&way,
3527	&set);
3528	#ifdef INSTRUMENTATION
3529	m_cpt_dtlb_read++;
3530	#endif
3531	}
3532
3533	#if DEBUG_DCACHE
3534	if (m_debug_dcache_fsm)
3535	{
3536	if (r_dcache_tlb_ins.read())
3537	std::cout << " <PROC " << name()
3538	<< " DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB:";
3539	else
3540	std::cout << " <PROC " << name()
3541	<< " DCACHE_TLB_PTE2_SELECT> Select a slot in DTLB:";
3542	std::cout << " way = " << std::dec << way
3543	<< " / set = " << set << std::endl;
3544	}
3545	#endif
3546	r_dcache_tlb_way = way;
3547	r_dcache_tlb_set = set;
3548	r_dcache_fsm = DCACHE_TLB_PTE2_UPDT;
3549	break;
3550	}
3551	//////////////////////////
3552	case DCACHE_TLB_PTE2_UPDT: // write a new PTE2 in tlb after testing the L/R bit
3553	// - if L/R bit already set, exit the sub-fsm.
3554	// - if not, we update the page table but we dont write
3555	// neither in DCACHE, nor in TLB, as this will be done by
3556	// the coherence mechanism.
3557	{
3558	paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words) + 2);
3559	uint32_t pte_flags = r_dcache_tlb_pte_flags.read();
3560	uint32_t pte_ppn = r_dcache_tlb_pte_ppn.read();
3561	bool pt_updt = false;
3562	bool local = true;
3563
3564	// We should compute the access locality:
3565	// The PPN MSB bits define the destination cluster index.
3566	// The m_srcid MSB bits define the source cluster index.
3567	// The number of bits to compare depends on the number of clusters,
3568	// and can be obtained in the mapping table.
3569	// As long as this computation is not done, all access are local.
3570
3571	if (local) // local access
3572	{
3573	if (not ((pte_flags & PTE_L_MASK) == PTE_L_MASK)) // we must set the L bit
3574	{
3575	pt_updt = true;
3576	r_dcache_vci_cas_old = pte_flags;
3577	r_dcache_vci_cas_new = pte_flags \| PTE_L_MASK;
3578	pte_flags = pte_flags \| PTE_L_MASK;
3579	r_dcache_tlb_pte_flags = pte_flags;
3580	}
3581	}
3582	else // remote access
3583	{
3584	if (not ((pte_flags & PTE_R_MASK) == PTE_R_MASK)) // we must set the R bit
3585	{
3586	pt_updt = true;
3587	r_dcache_vci_cas_old = pte_flags;
3588	r_dcache_vci_cas_new = pte_flags \| PTE_R_MASK;
3589	pte_flags = pte_flags \| PTE_R_MASK;
3590	r_dcache_tlb_pte_flags = pte_flags;
3591	}
3592	}
3593
3594	if (not pt_updt) // update TLB
3595	{
3596	if (r_dcache_tlb_ins.read())
3597	{
3598	r_itlb.write( false, // 4K page
3599	pte_flags,
3600	pte_ppn,
3601	r_dcache_tlb_vaddr.read(),
3602	r_dcache_tlb_way.read(),
3603	r_dcache_tlb_set.read(),
3604	nline );
3605	#ifdef INSTRUMENTATION
3606	m_cpt_itlb_write++;
3607	#endif
3608
3609	#if DEBUG_DCACHE
3610	if (m_debug_dcache_fsm)
3611	{
3612	std::cout << " <PROC " << name()
3613	<< " DCACHE_TLB_PTE2_UPDT> write PTE2 in ITLB"
3614	<< " / set = " << std::dec << r_dcache_tlb_set.read()
3615	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3616	r_itlb.printTrace();
3617	}
3618	#endif
3619	}
3620	else
3621	{
3622	r_dtlb.write(false, // 4K page
3623	pte_flags,
3624	pte_ppn,
3625	r_dcache_tlb_vaddr.read(),
3626	r_dcache_tlb_way.read(),
3627	r_dcache_tlb_set.read(),
3628	nline);
3629	#ifdef INSTRUMENTATION
3630	m_cpt_dtlb_write++;
3631	#endif
3632
3633	#if DEBUG_DCACHE
3634	if (m_debug_dcache_fsm)
3635	{
3636	std::cout << " <PROC " << name()
3637	<< " DCACHE_TLB_PTE2_UPDT> write PTE2 in DTLB"
3638	<< " / set = " << std::dec << r_dcache_tlb_set.read()
3639	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3640	r_dtlb.printTrace();
3641	}
3642	#endif
3643
3644	}
3645	r_dcache_fsm = DCACHE_TLB_RETURN;
3646	}
3647	else // update page table but not TLB
3648	{
3649	r_dcache_fsm = DCACHE_TLB_LR_UPDT; // dcache and page table update
3650
3651	#if DEBUG_DCACHE
3652	if (m_debug_dcache_fsm)
3653	{
3654	std::cout << " <PROC " << name()
3655	<< " DCACHE_TLB_PTE2_UPDT> L/R bit update required" << std::endl;
3656	}
3657	#endif
3658	}
3659	break;
3660	}
3661	////////////////////////
3662	case DCACHE_TLB_LR_UPDT: // request a CAS transaction to update L/R bit
3663	{
3664	#if DEBUG_DCACHE
3665	if (m_debug_dcache_fsm)
3666	{
3667	std::cout << " <PROC " << name()
3668	<< " DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit" << std::endl;
3669	}
3670	#endif
3671	// r_dcache_vci_cas_old & r_dcache_vci_cas_new registers are already set
3672	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
3673
3674	// checking llsc reservation buffer
3675	if (r_dcache_llsc_paddr.read() == r_dcache_tlb_paddr.read())
3676	r_dcache_llsc_valid = false;
3677
3678	// request a CAS CMD and go to DCACHE_TLB_LR_WAIT state
3679	r_dcache_vci_cas_req = true;
3680	r_dcache_fsm = DCACHE_TLB_LR_WAIT;
3681	break;
3682	}
3683	////////////////////////
3684	case DCACHE_TLB_LR_WAIT: // Waiting the response to SC transaction for DIRTY bit.
3685	// We consume the response in rsp FIFO,
3686	// and exit the sub-fsm, but we don't
3687	// analyse the response, because we don't
3688	// care if the L/R bit update is not done.
3689	// We must take the coherence requests because
3690	// there is a risk of dead-lock
3691
3692	{
3693	// coherence clack request (from DSPIN CLACK)
3694	if (r_dcache_clack_req.read())
3695	{
3696	r_dcache_fsm = DCACHE_CC_CHECK;
3697	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3698	break;
3699	}
3700
3701	// coherence request (from CC_RECEIVE FSM)
3702	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
3703	{
3704	r_dcache_fsm = DCACHE_CC_CHECK;
3705	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3706	break;
3707	}
3708
3709	if (r_vci_rsp_data_error.read()) // bus error
3710	{
3711	std::cout << "BUS ERROR in DCACHE_TLB_LR_WAIT state" << std::endl;
3712	std::cout << "This should not happen in this state" << std::endl;
3713	exit(0);
3714	}
3715	else if (r_vci_rsp_fifo_dcache.rok()) // response available
3716	{
3717	#if DEBUG_DCACHE
3718	if (m_debug_dcache_fsm)
3719	{
3720	std::cout << " <PROC " << name()
3721	<< " DCACHE_TLB_LR_WAIT> SC response received" << std::endl;
3722	}
3723	#endif
3724	vci_rsp_fifo_dcache_get = true;
3725	r_dcache_fsm = DCACHE_TLB_RETURN;
3726	}
3727	break;
3728	}
3729	///////////////////////
3730	case DCACHE_TLB_RETURN: // return to caller depending on tlb miss type
3731	{
3732	#if DEBUG_DCACHE
3733	if (m_debug_dcache_fsm)
3734	{
3735	std::cout << " <PROC " << name()
3736	<< " DCACHE_TLB_RETURN> TLB MISS completed" << std::endl;
3737	}
3738	#endif
3739	if (r_dcache_tlb_ins.read()) r_icache_tlb_miss_req = false;
3740	r_dcache_fsm = DCACHE_IDLE;
3741	break;
3742	}
3743	///////////////////////
3744	case DCACHE_XTN_SWITCH: // The r_ptpr registers must be written,
3745	// and both itlb and dtlb must be flushed.
3746	// Caution : the itlb miss requests must be taken
3747	// to avoid dead-lock in case of simultaneous ITLB miss
3748	// Caution : the clack and cc requests must be taken
3749	// to avoid dead-lock
3750	{
3751	// coherence clack request (from DSPIN CLACK)
3752	if (r_dcache_clack_req.read())
3753	{
3754	r_dcache_fsm = DCACHE_CC_CHECK;
3755	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3756	break;
3757	}
3758
3759	// coherence request (from CC_RECEIVE FSM)
3760	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
3761	{
3762	r_dcache_fsm = DCACHE_CC_CHECK;
3763	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3764	break;
3765	}
3766
3767	// itlb miss request
3768	if (r_icache_tlb_miss_req.read())
3769	{
3770	r_dcache_tlb_ins = true;
3771	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
3772	r_dcache_fsm = DCACHE_TLB_MISS;
3773	break;
3774	}
3775
3776	if (not r_dcache_xtn_req.read())
3777	{
3778	r_dtlb.flush();
3779	r_mmu_ptpr = m_dreq.wdata;
3780	r_dcache_fsm = DCACHE_IDLE;
3781	m_drsp.valid = true;
3782	}
3783	break;
3784	}
3785	/////////////////////
3786	case DCACHE_XTN_SYNC: // waiting until write buffer empty
3787	// The coherence request must be taken
3788	// as there is a risk of dead-lock
3789	{
3790	// coherence clack request (from DSPIN CLACK)
3791	if (r_dcache_clack_req.read())
3792	{
3793	r_dcache_fsm = DCACHE_CC_CHECK;
3794	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3795	break;
3796	}
3797
3798	// coherence request (from CC_RECEIVE FSM)
3799	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
3800	{
3801	r_dcache_fsm = DCACHE_CC_CHECK;
3802	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3803	break;
3804	}
3805
3806	if (r_wbuf.empty())
3807	{
3808	m_drsp.valid = true;
3809	r_dcache_fsm = DCACHE_IDLE;
3810	}
3811	break;
3812	}
3813	////////////////////////
3814	case DCACHE_XTN_IC_FLUSH: // Waiting completion of an XTN request to the ICACHE FSM
3815	case DCACHE_XTN_IC_INVAL_VA: // Caution : the itlb miss requests must be taken
3816	case DCACHE_XTN_IC_INVAL_PA: // because the XTN_ICACHE_INVAL request to icache
3817	case DCACHE_XTN_IC_PADDR_EXT: // can generate an itlb miss,
3818	case DCACHE_XTN_IT_INVAL: // and because it can exist a simultaneous ITLB miss
3819
3820	{
3821	// coherence clack request (from DSPIN CLACK)
3822	if (r_dcache_clack_req.read())
3823	{
3824	r_dcache_fsm = DCACHE_CC_CHECK;
3825	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3826	break;
3827	}
3828
3829	// coherence request (from CC_RECEIVE FSM)
3830	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
3831	{
3832	r_dcache_fsm = DCACHE_CC_CHECK;
3833	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3834	break;
3835	}
3836
3837	// itlb miss request
3838	if (r_icache_tlb_miss_req.read())
3839	{
3840	r_dcache_tlb_ins = true;
3841	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
3842	r_dcache_fsm = DCACHE_TLB_MISS;
3843	break;
3844	}
3845
3846	// test if XTN request to icache completed
3847	if (not r_dcache_xtn_req.read())
3848	{
3849	r_dcache_fsm = DCACHE_IDLE;
3850	m_drsp.valid = true;
3851	}
3852	break;
3853	}
3854	/////////////////////////
3855	case DCACHE_XTN_DC_FLUSH: // Invalidate sequencially all cache lines, using
3856	// r_dcache_flush_count as a slot counter,
3857	// looping in this state until all slots have been visited.
3858	// It can require two cycles per slot:
3859	// We test here the slot state, and make the actual inval
3860	// (if line is valid) in DCACHE_XTN_DC_FLUSH_GO state.
3861	// A cleanup request is generated for each valid line.
3862	// returns to IDLE and flush TLBs when last slot
3863	{
3864	// coherence clack request (from DSPIN CLACK)
3865	if (r_dcache_clack_req.read())
3866	{
3867	r_dcache_fsm = DCACHE_CC_CHECK;
3868	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3869	break;
3870	}
3871
3872	// coherence request (from CC_RECEIVE FSM)
3873	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
3874	{
3875	r_dcache_fsm = DCACHE_CC_CHECK;
3876	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3877	break;
3878	}
3879
3880	if (not r_dcache_cc_send_req.read()) // blocked until previous cc_send request is sent
3881	{
3882	int state;
3883	paddr_t tag;
3884	size_t way = r_dcache_flush_count.read() / m_dcache_sets;
3885	size_t set = r_dcache_flush_count.read() % m_dcache_sets;
3886
3887	#ifdef INSTRUMENTATION
3888	m_cpt_dcache_dir_read++;
3889	#endif
3890	r_dcache.read_dir(way,
3891	set,
3892	&tag,
3893	&state);
3894
3895	if (state == CACHE_SLOT_STATE_VALID) // inval required
3896	{
3897	// request cleanup
3898	r_dcache_cc_send_req = true;
3899	r_dcache_cc_send_nline = tag * m_dcache_sets + set;
3900	r_dcache_cc_send_way = way;
3901	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
3902
3903	// goes to DCACHE_XTN_DC_FLUSH_GO to inval directory
3904	r_dcache_miss_way = way;
3905	r_dcache_miss_set = set;
3906	r_dcache_fsm = DCACHE_XTN_DC_FLUSH_GO;
3907	}
3908	else if (r_dcache_flush_count.read() ==
3909	(m_dcache_sets*m_dcache_ways - 1)) // last slot
3910	{
3911	r_dtlb.reset();
3912	r_itlb.reset();
3913	r_dcache_fsm = DCACHE_IDLE;
3914	m_drsp.valid = true;
3915	}
3916
3917	// saturation counter
3918	if (r_dcache_flush_count.read() < (m_dcache_sets * m_dcache_ways - 1))
3919	r_dcache_flush_count = r_dcache_flush_count.read() + 1;
3920	}
3921	break;
3922	}
3923	////////////////////////////
3924	case DCACHE_XTN_DC_FLUSH_GO: // Switch the cache slot to ZOMBI state
3925	// and reset directory extension.
3926	// returns to IDLE and flush TLBs when last slot
3927	{
3928	size_t way = r_dcache_miss_way.read();
3929	size_t set = r_dcache_miss_set.read();
3930
3931	r_dcache_in_tlb[m_dcache_sets * way + set] = false;
3932	r_dcache_contains_ptd[m_dcache_sets * way + set] = false;
3933
3934	#ifdef INSTRUMENTATION
3935	m_cpt_dcache_dir_write++;
3936	#endif
3937	r_dcache.write_dir(way,
3938	set,
3939	CACHE_SLOT_STATE_ZOMBI);
3940
3941	if (r_dcache_flush_count.read() ==
3942	(m_dcache_sets*m_dcache_ways - 1)) // last slot
3943	{
3944	r_dtlb.reset();
3945	r_itlb.reset();
3946	r_dcache_fsm = DCACHE_IDLE;
3947	m_drsp.valid = true;
3948	}
3949	else
3950	{
3951	r_dcache_fsm = DCACHE_XTN_DC_FLUSH;
3952	}
3953	break;
3954	}
3955	/////////////////////////
3956	case DCACHE_XTN_DT_INVAL: // handling processor XTN_DTLB_INVAL request
3957	{
3958	r_dtlb.inval(r_dcache_save_wdata.read());
3959	r_dcache_fsm = DCACHE_IDLE;
3960	m_drsp.valid = true;
3961	break;
3962	}
3963	////////////////////////////
3964	case DCACHE_XTN_DC_INVAL_VA: // selective cache line invalidate with virtual address
3965	// requires 3 cycles: access tlb, read cache, inval cache
3966	// we compute the physical address in this state
3967	{
3968	paddr_t paddr;
3969	bool hit;
3970
3971	if (r_mmu_mode.read() & DATA_TLB_MASK) // dtlb activated
3972	{
3973
3974	#ifdef INSTRUMENTATION
3975	m_cpt_dtlb_read++;
3976	#endif
3977	hit = r_dtlb.translate(r_dcache_save_wdata.read(),
3978	&paddr);
3979	}
3980	else // dtlb not activated
3981	{
3982	paddr = (paddr_t)r_dcache_save_wdata.read();
3983	if (vci_param::N > 32)
3984	paddr = paddr \| ((paddr_t)(r_dcache_paddr_ext.read()) << 32);
3985	hit = true;
3986	}
3987
3988	if (hit) // tlb hit
3989	{
3990	r_dcache_save_paddr = paddr;
3991	r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA;
3992	}
3993	else // tlb miss
3994	{
3995
3996	#ifdef INSTRUMENTATION
3997	m_cpt_dtlb_miss++;
3998	#endif
3999	r_dcache_tlb_ins = false; // dtlb
4000	r_dcache_tlb_vaddr = r_dcache_save_wdata.read();
4001	r_dcache_fsm = DCACHE_TLB_MISS;
4002	}
4003
4004	#if DEBUG_DCACHE
4005	if (m_debug_dcache_fsm)
4006	{
4007	std::cout << " <PROC " << name()
4008	<< " DCACHE_XTN_DC_INVAL_VA> Compute physical address" << std::hex
4009	<< " / VADDR = " << r_dcache_save_wdata.read()
4010	<< " / PADDR = " << paddr << std::endl;
4011	}
4012	#endif
4013
4014	break;
4015	}
4016	////////////////////////////
4017	case DCACHE_XTN_DC_INVAL_PA: // selective cache line invalidate with physical address
4018	// requires 2 cycles: read cache / inval cache
4019	// In this state we read dcache.
4020	{
4021	size_t way;
4022	size_t set;
4023	size_t word;
4024	int state;
4025
4026	#ifdef INSTRUMENTATION
4027	m_cpt_dcache_dir_read++;
4028	#endif
4029	r_dcache.read_dir(r_dcache_save_paddr.read(),
4030	&state,
4031	&way,
4032	&set,
4033	&word);
4034
4035	if (state == CACHE_SLOT_STATE_VALID) // inval to be done
4036	{
4037	r_dcache_xtn_way = way;
4038	r_dcache_xtn_set = set;
4039	r_dcache_fsm = DCACHE_XTN_DC_INVAL_GO;
4040	}
4041	else // miss : nothing to do
4042	{
4043	r_dcache_fsm = DCACHE_IDLE;
4044	m_drsp.valid = true;
4045	}
4046
4047	#if DEBUG_DCACHE
4048	if (m_debug_dcache_fsm)
4049	{
4050	std::cout << " <PROC " << name()
4051	<< " DCACHE_XTN_DC_INVAL_PA> Test hit in dcache" << std::hex
4052	<< " / PADDR = " << r_dcache_save_paddr.read() << std::dec
4053	<< " / HIT = " << (state == CACHE_SLOT_STATE_VALID)
4054	<< " / SET = " << set
4055	<< " / WAY = " << way << std::endl;
4056	}
4057	#endif
4058	break;
4059	}
4060	////////////////////////////
4061	case DCACHE_XTN_DC_INVAL_GO: // In this state, we invalidate the cache line
4062	// Blocked if previous cleanup not completed
4063	// Test if itlb or dtlb inval is required
4064	{
4065	if (not r_dcache_cc_send_req.read()) // blocked until previous cc_send request is sent
4066	{
4067	size_t way = r_dcache_xtn_way.read();
4068	size_t set = r_dcache_xtn_set.read();
4069	paddr_t nline = r_dcache_save_paddr.read() / (m_dcache_words << 2);
4070
4071	#ifdef INSTRUMENTATION
4072	m_cpt_dcache_dir_write++;
4073	#endif
4074	r_dcache.write_dir(way,
4075	set,
4076	CACHE_SLOT_STATE_ZOMBI);
4077
4078	// request cleanup
4079	r_dcache_cc_send_req = true;
4080	r_dcache_cc_send_nline = nline;
4081	r_dcache_cc_send_way = way;
4082	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
4083
4084	// possible itlb & dtlb invalidate
4085	if (r_dcache_in_tlb[way * m_dcache_sets + set])
4086	{
4087	r_dcache_tlb_inval_line = nline;
4088	r_dcache_tlb_inval_set = 0;
4089	r_dcache_fsm_scan_save = DCACHE_XTN_DC_INVAL_END;
4090	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4091	r_dcache_in_tlb[way * m_dcache_sets + set] = false;
4092	}
4093	else if (r_dcache_contains_ptd[way * m_dcache_sets + set])
4094	{
4095	r_itlb.reset();
4096	r_dtlb.reset();
4097	r_dcache_contains_ptd[way * m_dcache_sets + set] = false;
4098	r_dcache_fsm = DCACHE_IDLE;
4099	m_drsp.valid = true;
4100	}
4101	else
4102	{
4103	r_dcache_fsm = DCACHE_IDLE;
4104	m_drsp.valid = true;
4105	}
4106
4107	#if DEBUG_DCACHE
4108	if (m_debug_dcache_fsm)
4109	{
4110	std::cout << " <PROC " << name()
4111	<< " DCACHE_XTN_DC_INVAL_GO> Actual dcache inval" << std::hex
4112	<< " / PADDR = " << r_dcache_save_paddr.read() << std::endl;
4113	}
4114	#endif
4115	}
4116	break;
4117	}
4118	//////////////////////////////
4119	case DCACHE_XTN_DC_INVAL_END: // send response to processor XTN request
4120	{
4121	r_dcache_fsm = DCACHE_IDLE;
4122	m_drsp.valid = true;
4123	break;
4124	}
4125	////////////////////////
4126	case DCACHE_MISS_SELECT: // Try to select a slot in associative set,
4127	// Waiting in this state if no slot available.
4128	// If a victim slot has been choosen and the r_icache_cc_send_req is false,
4129	// we send the cleanup request in this state.
4130	// If not, a r_icache_cleanup_victim_req flip-flop is
4131	// utilized for saving this cleanup request, and it will be sent later
4132	// in state ICACHE_MISS_WAIT or ICACHE_MISS_UPDT_DIR.
4133	// The r_icache_miss_clack flip-flop is set
4134	// when a cleanup is required
4135	{
4136	if (m_dreq.valid) m_cost_data_miss_frz++;
4137
4138	// coherence clack request (from DSPIN CLACK)
4139	if (r_dcache_clack_req.read())
4140	{
4141	r_dcache_fsm = DCACHE_CC_CHECK;
4142	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4143	break;
4144	}
4145
4146	// coherence request (from CC_RECEIVE FSM)
4147	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
4148	{
4149	r_dcache_fsm = DCACHE_CC_CHECK;
4150	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4151	break;
4152	}
4153
4154	bool found = false;
4155	bool cleanup = false;
4156	size_t way = 0;
4157	size_t set = 0;
4158	paddr_t victim = 0;
4159
4160	#ifdef INSTRUMENTATION
4161	m_cpt_dcache_dir_read++;
4162	#endif
4163	r_dcache.read_select(r_dcache_save_paddr.read(),
4164	&victim,
4165	&way,
4166	&set,
4167	&found,
4168	&cleanup);
4169
4170	if (not found)
4171	{
4172	break;
4173	}
4174	else
4175	{
4176	r_dcache_miss_way = way;
4177	r_dcache_miss_set = set;
4178
4179	// reset to 0 the watchdog timer
4180	r_dcache_wdt = 0;
4181
4182	if (cleanup)
4183	{
4184	if (not r_dcache_cc_send_req.read())
4185	{
4186	r_dcache_cc_send_req = true;
4187	r_dcache_cc_send_nline = victim;
4188	r_dcache_cc_send_way = way;
4189	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
4190
4191	}
4192	else
4193	{
4194	r_dcache_cleanup_victim_req = true;
4195	r_dcache_cleanup_victim_nline = victim;
4196	}
4197
4198	r_dcache_miss_clack = true;
4199	r_dcache_fsm = DCACHE_MISS_CLEAN;
4200	}
4201	else
4202	{
4203	r_dcache_fsm = DCACHE_MISS_WAIT;
4204	}
4205
4206	#if DEBUG_DCACHE
4207	if (m_debug_dcache_fsm)
4208	{
4209	std::cout << " <PROC " << name()
4210	<< " DCACHE_MISS_SELECT> Select a slot:" << std::dec
4211	<< " / WAY = " << way
4212	<< " / SET = " << set
4213	<< " / PADDR = " << std::hex << r_dcache_save_paddr.read();
4214	if (cleanup) std::cout << " / VICTIM = " << (victimm_dcache_words4) << std::endl;
4215	else std::cout << std::endl;
4216	}
4217	#endif
4218	} // end found
4219	break;
4220	}
4221	///////////////////////
4222	case DCACHE_MISS_CLEAN: // switch the slot to ZOMBI state
4223	// and possibly request itlb or dtlb invalidate
4224	{
4225	if (m_dreq.valid) m_cost_data_miss_frz++;
4226
4227	size_t way = r_dcache_miss_way.read();
4228	size_t set = r_dcache_miss_set.read();
4229
4230	#ifdef INSTRUMENTATION
4231	m_cpt_dcache_dir_read++;
4232	#endif
4233	r_dcache.write_dir(way,
4234	set,
4235	CACHE_SLOT_STATE_ZOMBI);
4236	#if DEBUG_DCACHE
4237	if (m_debug_dcache_fsm)
4238	{
4239	std::cout << " <PROC " << name()
4240	<< " DCACHE_MISS_CLEAN> Switch to ZOMBI state" << std::dec
4241	<< " / way = " << way
4242	<< " / set = " << set << std::endl;
4243	}
4244	#endif
4245	// if selective itlb & dtlb invalidate are required
4246	// the miss response is not handled before invalidate completed
4247	if (r_dcache_in_tlb[way * m_dcache_sets + set])
4248	{
4249	r_dcache_in_tlb[way * m_dcache_sets + set] = false;
4250
4251	if (not r_dcache_cleanup_victim_req.read())
4252	r_dcache_tlb_inval_line = r_dcache_cc_send_nline.read();
4253	else
4254	r_dcache_tlb_inval_line = r_dcache_cleanup_victim_nline.read();
4255
4256	r_dcache_tlb_inval_set = 0;
4257	r_dcache_fsm_scan_save = DCACHE_MISS_WAIT;
4258	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4259	}
4260	else if (r_dcache_contains_ptd[way * m_dcache_sets + set])
4261	{
4262	r_itlb.reset();
4263	r_dtlb.reset();
4264	r_dcache_contains_ptd[way * m_dcache_sets + set] = false;
4265	r_dcache_fsm = DCACHE_MISS_WAIT;
4266	}
4267	else
4268	{
4269	r_dcache_fsm = DCACHE_MISS_WAIT;
4270	}
4271	break;
4272	}
4273	//////////////////////
4274	case DCACHE_MISS_WAIT: // waiting the response to a miss request from VCI_RSP FSM
4275	// This state is in charge of error signaling
4276	// There is 5 types of error depending on the requester
4277	{
4278	if (m_dreq.valid) m_cost_data_miss_frz++;
4279
4280	// send cleanup victim request
4281	if (r_dcache_cleanup_victim_req.read() and not r_dcache_cc_send_req.read())
4282	{
4283	r_dcache_cc_send_req = true;
4284	r_dcache_cc_send_nline = r_dcache_cleanup_victim_nline;
4285	r_dcache_cc_send_way = r_dcache_miss_way;
4286	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
4287	r_dcache_cleanup_victim_req = false;
4288	}
4289
4290	// coherence clack request (from DSPIN CLACK)
4291	if (r_dcache_clack_req.read())
4292	{
4293	r_dcache_fsm = DCACHE_CC_CHECK;
4294	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4295	break;
4296	}
4297
4298	// coherence request (from CC_RECEIVE FSM)
4299	if (r_cc_receive_dcache_req.read() and
4300	not r_dcache_cc_send_req.read() and
4301	not r_dcache_cleanup_victim_req.read())
4302	{
4303	r_dcache_fsm = DCACHE_CC_CHECK;
4304	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4305	break;
4306	}
4307
4308	// increment watchdog timer for black-hole detection
4309	r_dcache_wdt = r_dcache_wdt.read() + 1;
4310	if (r_dcache_wdt.read() == r_dcache_wdt_max.read())
4311	{
4312	r_mmu_detr = MMU_READ_DATA_TIMEOUT;
4313	r_mmu_dbvar = r_dcache_save_vaddr.read();
4314	m_drsp.valid = true;
4315	m_drsp.error = true;
4316	r_dcache_fsm = DCACHE_IDLE;
4317
4318	// debug: this counter is used to detect an early WDT timeout.
4319	// It is sent as the data miss transactions TRDID. When a data miss
4320	// response is treated by the RSP FSM, the RTRDID is compared to
4321	// this counter to determine if a timeout was triggered during the
4322	// transaction.
4323	r_dcache_wdt_timeout = r_dcache_wdt_timeout.read() + 1;
4324
4325	#if DEBUG_DCACHE
4326	if (m_debug_dcache_fsm)
4327	{
4328	std::cout << " <PROC " << name() << " DCACHE_MISS_WAIT>"
4329	" watchdog timer exception" << std::endl;
4330	}
4331	#endif
4332	break;
4333	}
4334
4335	if (r_vci_rsp_data_error.read()) // bus error
4336	{
4337	switch (r_dcache_miss_type.read())
4338	{
4339	case PROC_MISS:
4340	{
4341	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
4342	r_mmu_dbvar = r_dcache_save_vaddr.read();
4343	m_drsp.valid = true;
4344	m_drsp.error = true;
4345	r_dcache_fsm = DCACHE_IDLE;
4346	break;
4347	}
4348	case PTE1_MISS:
4349	{
4350	if (r_dcache_tlb_ins.read())
4351	{
4352	r_mmu_ietr = MMU_READ_PT1_ILLEGAL_ACCESS;
4353	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
4354	r_icache_tlb_miss_req = false;
4355	r_icache_tlb_rsp_error = true;
4356	}
4357	else
4358	{
4359	r_mmu_detr = MMU_READ_PT1_ILLEGAL_ACCESS;
4360	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
4361	m_drsp.valid = true;
4362	m_drsp.error = true;
4363	}
4364	r_dcache_fsm = DCACHE_IDLE;
4365	break;
4366	}
4367	case PTE2_MISS:
4368	{
4369	if (r_dcache_tlb_ins.read())
4370	{
4371	r_mmu_ietr = MMU_READ_PT2_ILLEGAL_ACCESS;
4372	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
4373	r_icache_tlb_miss_req = false;
4374	r_icache_tlb_rsp_error = true;
4375	}
4376	else
4377	{
4378	r_mmu_detr = MMU_READ_PT2_ILLEGAL_ACCESS;
4379	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
4380	m_drsp.valid = true;
4381	m_drsp.error = true;
4382	}
4383	r_dcache_fsm = DCACHE_IDLE;
4384	break;
4385	}
4386	} // end switch type
4387	r_vci_rsp_data_error = false;
4388	}
4389	else if (r_vci_rsp_fifo_dcache.rok()) // valid response available
4390	{
4391	r_dcache_miss_word = 0;
4392	r_dcache_fsm = DCACHE_MISS_DATA_UPDT;
4393	}
4394	break;
4395	}
4396	//////////////////////////
4397	case DCACHE_MISS_DATA_UPDT: // update the dcache (one word per cycle)
4398	{
4399	if (m_dreq.valid) m_cost_data_miss_frz++;
4400
4401	if (r_vci_rsp_fifo_dcache.rok()) // one word available
4402	{
4403	#ifdef INSTRUMENTATION
4404	m_cpt_dcache_data_write++;
4405	#endif
4406	r_dcache.write(r_dcache_miss_way.read(),
4407	r_dcache_miss_set.read(),
4408	r_dcache_miss_word.read(),
4409	r_vci_rsp_fifo_dcache.read());
4410	#if DEBUG_DCACHE
4411	if (m_debug_dcache_fsm)
4412	{
4413	std::cout << " <PROC " << name()
4414	<< " DCACHE_MISS_DATA_UPDT> Write one word:"
4415	<< " / DATA = " << std::hex << r_vci_rsp_fifo_dcache.read()
4416	<< " / WAY = " << std::dec << r_dcache_miss_way.read()
4417	<< " / SET = " << r_dcache_miss_set.read()
4418	<< " / WORD = " << r_dcache_miss_word.read() << std::endl;
4419	}
4420	#endif
4421	vci_rsp_fifo_dcache_get = true;
4422	r_dcache_miss_word = r_dcache_miss_word.read() + 1;
4423
4424	if (r_dcache_miss_word.read() == (m_dcache_words - 1)) // last word
4425	{
4426	r_dcache_fsm = DCACHE_MISS_DIR_UPDT;
4427	}
4428	}
4429	break;
4430	}
4431	//////////////////////////
4432	case DCACHE_MISS_DIR_UPDT: // Stalled if a victim line has been evicted
4433	// and the cleanup ack has not been received,
4434	// as indicated by the r_dcache_miss clack.
4435	// - If no matching coherence request (r_dcache_inval_miss)
4436	// switch directory slot to VALID state.
4437	// - If matching coherence request, switch directory slot
4438	// to ZOMBI state, and send a cleanup request.
4439	{
4440	if (m_dreq.valid) m_cost_data_miss_frz++;
4441
4442	// send cleanup victim request
4443	if (r_dcache_cleanup_victim_req.read() and not r_dcache_cc_send_req.read())
4444	{
4445	r_dcache_cc_send_req = true;
4446	r_dcache_cc_send_nline = r_dcache_cleanup_victim_nline;
4447	r_dcache_cc_send_way = r_dcache_miss_way;
4448	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
4449	r_dcache_cleanup_victim_req = false;
4450	}
4451
4452	// coherence clack request (from DSPIN CLACK)
4453	if (r_dcache_clack_req.read())
4454	{
4455	r_dcache_fsm = DCACHE_CC_CHECK;
4456	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4457	break;
4458	}
4459
4460	// coherence request (from CC_RECEIVE FSM)
4461	if (r_cc_receive_dcache_req.read() and
4462	not r_dcache_cc_send_req.read() and
4463	not r_dcache_cleanup_victim_req.read())
4464	{
4465	r_dcache_fsm = DCACHE_CC_CHECK;
4466	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4467	break;
4468	}
4469
4470	if (not r_dcache_miss_clack.read()) // waiting cleanup acknowledge
4471	{
4472	if (r_dcache_miss_inval.read()) // switch slot to ZOMBI state, and new cleanup
4473	{
4474	if (not r_dcache_cc_send_req.read()) // blocked until previous request sent
4475	{
4476	r_dcache_miss_inval = false;
4477	// request cleanup
4478	r_dcache_cc_send_req = true;
4479	r_dcache_cc_send_nline = r_dcache_save_paddr.read() / (m_dcache_words << 2);
4480	r_dcache_cc_send_way = r_dcache_miss_way.read();
4481	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
4482
4483	#ifdef INSTRUMENTATION
4484	m_cpt_dcache_dir_write++;
4485	#endif
4486	r_dcache.write_dir( r_dcache_save_paddr.read(),
4487	r_dcache_miss_way.read(),
4488	r_dcache_miss_set.read(),
4489	CACHE_SLOT_STATE_ZOMBI );
4490	#if DEBUG_DCACHE
4491	if (m_debug_dcache_fsm)
4492	std::cout << " <PROC " << name()
4493	<< " DCACHE_MISS_DIR_UPDT> Switch slot to ZOMBI state"
4494	<< " PADDR = " << std::hex << r_dcache_save_paddr.read()
4495	<< " / WAY = " << std::dec << r_dcache_miss_way.read()
4496	<< " / SET = " << r_dcache_miss_set.read() << std::endl;
4497	#endif
4498	}
4499	else
4500	break;
4501	}
4502	else // switch slot to VALID state
4503	{
4504
4505	#ifdef INSTRUMENTATION
4506	m_cpt_dcache_dir_write++;
4507	#endif
4508	r_dcache.write_dir(r_dcache_save_paddr.read(),
4509	r_dcache_miss_way.read(),
4510	r_dcache_miss_set.read(),
4511	CACHE_SLOT_STATE_VALID);
4512
4513	#if DEBUG_DCACHE
4514	if (m_debug_dcache_fsm)
4515	std::cout << " <PROC " << name()
4516	<< " DCACHE_MISS_DIR_UPDT> Switch slot to VALID state"
4517	<< " PADDR = " << std::hex << r_dcache_save_paddr.read()
4518	<< " / WAY = " << std::dec << r_dcache_miss_way.read()
4519	<< " / SET = " << r_dcache_miss_set.read() << std::endl;
4520	#endif
4521	// reset directory extension
4522	size_t way = r_dcache_miss_way.read();
4523	size_t set = r_dcache_miss_set.read();
4524	r_dcache_in_tlb[way * m_dcache_sets + set] = false;
4525	r_dcache_contains_ptd[way * m_dcache_sets + set] = false;
4526	}
4527	if (r_dcache_miss_type.read() == PTE1_MISS) r_dcache_fsm = DCACHE_TLB_PTE1_GET;
4528	else if (r_dcache_miss_type.read() == PTE2_MISS) r_dcache_fsm = DCACHE_TLB_PTE2_GET;
4529	else r_dcache_fsm = DCACHE_IDLE;
4530	}
4531	break;
4532	}
4533	/////////////////////
4534	case DCACHE_UNC_WAIT: // waiting a response to an uncacheable read/write
4535	{
4536	// coherence clack request (from DSPIN CLACK)
4537	if (r_dcache_clack_req.read())
4538	{
4539	r_dcache_fsm = DCACHE_CC_CHECK;
4540	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4541	break;
4542	}
4543
4544	// coherence request (from CC_RECEIVE FSM)
4545	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
4546	{
4547	r_dcache_fsm = DCACHE_CC_CHECK;
4548	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4549	break;
4550	}
4551
4552	// increment watchdog timer for black-hole detection
4553	r_dcache_wdt = r_dcache_wdt.read() + 1;
4554	if (r_dcache_wdt.read() == r_dcache_wdt_max.read())
4555	{
4556	r_mmu_detr = MMU_READ_DATA_TIMEOUT;
4557	r_mmu_dbvar = m_dreq.addr;
4558	m_drsp.valid = true;
4559	m_drsp.error = true;
4560	r_dcache_fsm = DCACHE_IDLE;
4561
4562	// debug: this counter is used to detect an early WDT timeout.
4563	// It is sent as the data uncacheable transactions TRDID. When a
4564	// response is treated by the RSP FSM, the RTRDID is compared to
4565	// this counter to determine if a timeout was triggered during the
4566	// transaction.
4567	r_dcache_wdt_timeout = r_dcache_wdt_timeout.read() + 1;
4568
4569	#if DEBUG_DCACHE
4570	if (m_debug_dcache_fsm)
4571	{
4572	std::cout << " <PROC " << name() << " DCACHE_MISS_WAIT>"
4573	" watchdog timer exception" << std::endl;
4574	}
4575	#endif
4576	break;
4577	}
4578
4579	if (r_vci_rsp_data_error.read()) // bus error
4580	{
4581	if (r_dcache_vci_unc_write.read())
4582	r_mmu_detr = MMU_WRITE_DATA_ILLEGAL_ACCESS;
4583	else
4584	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
4585
4586	r_mmu_dbvar = m_dreq.addr;
4587	r_vci_rsp_data_error = false;
4588	m_drsp.error = true;
4589	m_drsp.valid = true;
4590	r_dcache_fsm = DCACHE_IDLE;
4591	break;
4592	}
4593	else if (r_vci_rsp_fifo_dcache.rok()) // data available
4594	{
4595	// consume data
4596	vci_rsp_fifo_dcache_get = true;
4597	r_dcache_fsm = DCACHE_IDLE;
4598
4599	// acknowledge the processor request if it has not been modified
4600	if (m_dreq.valid and (m_dreq.addr == r_dcache_save_vaddr.read()))
4601	{
4602	m_drsp.valid = true;
4603	m_drsp.error = false;
4604	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
4605	}
4606	}
4607	break;
4608	}
4609	/////////////////////
4610	case DCACHE_LL_WAIT: // waiting VCI response to a LL transaction
4611	{
4612	// coherence clack request (from DSPIN CLACK)
4613	if (r_dcache_clack_req.read())
4614	{
4615	r_dcache_fsm = DCACHE_CC_CHECK;
4616	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4617	break;
4618	}
4619
4620	// coherence request (from CC_RECEIVE FSM)
4621	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
4622	{
4623	r_dcache_fsm = DCACHE_CC_CHECK;
4624	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4625	break;
4626	}
4627
4628	if (r_vci_rsp_data_error.read()) // bus error
4629	{
4630	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
4631	r_mmu_dbvar = m_dreq.addr;
4632	r_vci_rsp_data_error = false;
4633	m_drsp.error = true;
4634	m_drsp.valid = true;
4635	r_dcache_fsm = DCACHE_IDLE;
4636	break;
4637	}
4638	else if (r_vci_rsp_fifo_dcache.rok()) // data available
4639	{
4640	// consume data
4641	vci_rsp_fifo_dcache_get = true;
4642
4643	if (r_dcache_ll_rsp_count.read() == 0) // first flit
4644	{
4645	// set key value in llsc reservation buffer
4646	r_dcache_llsc_key = r_vci_rsp_fifo_dcache.read();
4647	r_dcache_ll_rsp_count = r_dcache_ll_rsp_count.read() + 1;
4648	}
4649	else // last flit
4650	{
4651	// acknowledge the processor request if it has not been modified
4652	if (m_dreq.valid and (m_dreq.addr == r_dcache_save_vaddr.read()))
4653	{
4654	m_drsp.valid = true;
4655	m_drsp.error = false;
4656	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
4657	}
4658	r_dcache_fsm = DCACHE_IDLE;
4659	}
4660	}
4661	break;
4662	}
4663	////////////////////
4664	case DCACHE_SC_WAIT: // waiting VCI response to a SC transaction
4665	{
4666	// coherence clack request (from DSPIN CLACK)
4667	if (r_dcache_clack_req.read())
4668	{
4669	r_dcache_fsm = DCACHE_CC_CHECK;
4670	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4671	break;
4672	}
4673
4674	// coherence request (from CC_RECEIVE FSM)
4675	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
4676	{
4677	r_dcache_fsm = DCACHE_CC_CHECK;
4678	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4679	break;
4680	}
4681
4682	if (r_vci_rsp_data_error.read()) // bus error
4683	{
4684	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
4685	r_mmu_dbvar = m_dreq.addr;
4686	r_vci_rsp_data_error = false;
4687	m_drsp.error = true;
4688	m_drsp.valid = true;
4689	r_dcache_fsm = DCACHE_IDLE;
4690	break;
4691	}
4692	else if (r_vci_rsp_fifo_dcache.rok()) // response available
4693	{
4694	// consume response
4695	vci_rsp_fifo_dcache_get = true;
4696	m_drsp.valid = true;
4697	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
4698	r_dcache_fsm = DCACHE_IDLE;
4699	}
4700	break;
4701	}
4702	//////////////////////////
4703	case DCACHE_DIRTY_GET_PTE: // This sub_fsm set the PTE Dirty bit in memory
4704	// before handling a processor WRITE or SC request
4705	// Input argument is r_dcache_dirty_paddr
4706	// In this first state, we get PTE value in dcache
4707	// and post a CAS request to CMD FSM
4708	{
4709	// get PTE in dcache
4710	uint32_t pte;
4711	size_t way;
4712	size_t set;
4713	size_t word; // unused
4714	int state;
4715
4716	#ifdef INSTRUMENTATION
4717	m_cpt_dcache_data_read++;
4718	m_cpt_dcache_dir_read++;
4719	#endif
4720	r_dcache.read(r_dcache_dirty_paddr.read(),
4721	&pte,
4722	&way,
4723	&set,
4724	&word,
4725	&state);
4726
4727	assert( (state == CACHE_SLOT_STATE_VALID) and
4728	"error in DCACHE_DIRTY_TLB_SET: the PTE should be in dcache" );
4729
4730	// request CAS transaction to CMD_FSM
4731	r_dcache_dirty_way = way;
4732	r_dcache_dirty_set = set;
4733
4734	// check llsc reservation buffer
4735	if (r_dcache_llsc_paddr.read() == r_dcache_dirty_paddr.read())
4736	r_dcache_llsc_valid = false;
4737
4738	// request a CAS CMD and go to DCACHE_DIRTY_WAIT state
4739	r_dcache_vci_cas_req = true;
4740	r_dcache_vci_paddr = r_dcache_dirty_paddr.read();
4741	r_dcache_vci_cas_old = pte;
4742	r_dcache_vci_cas_new = pte \| PTE_D_MASK;
4743	r_dcache_fsm = DCACHE_DIRTY_WAIT;
4744
4745	#if DEBUG_DCACHE
4746	if (m_debug_dcache_fsm)
4747	{
4748	std::cout << " <PROC " << name()
4749	<< " DCACHE_DIRTY_GET_PTE> CAS request" << std::hex
4750	<< " / PTE_PADDR = " << r_dcache_dirty_paddr.read()
4751	<< " / PTE_VALUE = " << pte << std::dec
4752	<< " / SET = " << set
4753	<< " / WAY = " << way << std::endl;
4754	}
4755	#endif
4756	break;
4757	}
4758	///////////////////////
4759	case DCACHE_DIRTY_WAIT: // wait completion of CAS for PTE Dirty bit,
4760	// and return to IDLE state when response is received.
4761	// we don't care if the CAS is a failure:
4762	// - if the CAS is a success, the coherence mechanism
4763	// updates the local copy.
4764	// - if the CAS is a failure, we just retry the write.
4765	{
4766	// coherence clack request (from DSPIN CLACK)
4767	if (r_dcache_clack_req.read())
4768	{
4769	r_dcache_fsm = DCACHE_CC_CHECK;
4770	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4771	break;
4772	}
4773
4774	// coherence request (from CC_RECEIVE FSM)
4775	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
4776	{
4777	r_dcache_fsm = DCACHE_CC_CHECK;
4778	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4779	break;
4780	}
4781
4782	if (r_vci_rsp_data_error.read()) // bus error
4783	{
4784	std::cout << "BUS ERROR in DCACHE_DIRTY_WAIT state" << std::endl;
4785	std::cout << "This should not happen in this state" << std::endl;
4786	exit(0);
4787	}
4788	else if (r_vci_rsp_fifo_dcache.rok()) // response available
4789	{
4790	vci_rsp_fifo_dcache_get = true;
4791	r_dcache_fsm = DCACHE_IDLE;
4792
4793	#if DEBUG_DCACHE
4794	if (m_debug_dcache_fsm)
4795	{
4796	std::cout << " <PROC " << name()
4797	<< " DCACHE_DIRTY_WAIT> CAS completed" << std::endl;
4798	}
4799	#endif
4800	}
4801	break;
4802	}
4803	/////////////////////
4804	case DCACHE_CC_CHECK: // This state is the entry point for the sub-FSM
4805	// handling coherence requests for DCACHE.
4806	// If there is a matching pending miss on the modified cache
4807	// line this is signaled in the r_dcache_miss inval flip-flop.
4808	// If the updated (or invalidated) cache line has copies in TLBs
4809	// these TLB copies are invalidated.
4810	// The return state is defined in r_dcache_fsm_cc_save
4811	{
4812	paddr_t paddr = r_cc_receive_dcache_nline.read() * m_dcache_words * 4;
4813	paddr_t mask = ~((m_dcache_words << 2) - 1);
4814
4815	// CLACK handler
4816	// We switch the directory slot to EMPTY state and reset
4817	// r_dcache_miss_clack if the cleanup ack is matching a pending miss.
4818	if (r_dcache_clack_req.read())
4819	{
4820	if (m_dreq.valid ) m_cost_data_miss_frz++;
4821
4822	#ifdef INSTRUMENTATION
4823	m_cpt_dcache_dir_write++;
4824	#endif
4825	r_dcache.write_dir(0,
4826	r_dcache_clack_way.read(),
4827	r_dcache_clack_set.read(),
4828	CACHE_SLOT_STATE_EMPTY);
4829
4830	if ((r_dcache_miss_set.read() == r_dcache_clack_set.read()) and
4831	(r_dcache_miss_way.read() == r_dcache_clack_way.read()))
4832	{
4833	r_dcache_miss_clack = false;
4834	}
4835
4836	r_dcache_clack_req = false;
4837
4838	// return to cc_save state
4839	r_dcache_fsm = r_dcache_fsm_cc_save.read() ;
4840
4841	#if DEBUG_DCACHE
4842	if (m_debug_dcache_fsm)
4843	{
4844	std::cout << " <PROC " << name()
4845	<< " DCACHE_CC_CHECK> CLACK for PADDR " << paddr
4846	<< " Switch slot to EMPTY state : "
4847	<< " set = " << r_dcache_clack_set.read()
4848	<< " / way = " << r_dcache_clack_way.read() << std::endl;
4849	}
4850	#endif
4851	break;
4852	}
4853
4854	assert(not r_dcache_cc_send_req.read() and
4855	"CC_SEND must be available in DCACHE_CC_CHECK");
4856
4857	// Match between MISS address and CC address
4858	if (r_cc_receive_dcache_req.read() and
4859	((r_dcache_fsm_cc_save == DCACHE_MISS_SELECT) or
4860	(r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) or
4861	(r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT)) and
4862	((r_dcache_vci_paddr.read() & mask) == (paddr & mask))) // matching
4863	{
4864	// signaling matching
4865	r_dcache_miss_inval = true;
4866
4867	// in case of update, go to CC_UPDT
4868	// JUST TO POP THE FIFO
4869	if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT)
4870	{
4871	r_dcache_fsm = DCACHE_CC_UPDT;
4872	r_dcache_cc_word = r_cc_receive_word_idx.read();
4873
4874	// just pop the fifo , don't write in icache
4875	r_dcache_cc_need_write = false;
4876	}
4877	// the request is dealt with
4878	else
4879	{
4880	r_cc_receive_dcache_req = false;
4881	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4882	}
4883
4884	#if DEBUG_DCACHE
4885	if (m_debug_dcache_fsm)
4886	{
4887	std::cout << " <PROC " << name()
4888	<< " DCACHE_CC_CHECK> Coherence request matching a pending miss:"
4889	<< " PADDR = " << std::hex << paddr << std::endl;
4890	}
4891	#endif
4892	}
4893
4894	// CC request handler
4895
4896	int state = 0;
4897	size_t way = 0;
4898	size_t set = 0;
4899	size_t word = 0;
4900
4901	#ifdef INSTRUMENTATION
4902	m_cpt_dcache_dir_read++;
4903	#endif
4904	r_dcache.read_dir(paddr,
4905	&state,
4906	&way,
4907	&set,
4908	&word); // unused
4909
4910	r_dcache_cc_way = way;
4911	r_dcache_cc_set = set;
4912
4913	if (state == CACHE_SLOT_STATE_VALID) // hit
4914	{
4915	// need to update the cache state
4916	if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT) // hit update
4917	{
4918	r_dcache_cc_need_write = true;
4919	r_dcache_fsm = DCACHE_CC_UPDT;
4920	r_dcache_cc_word = r_cc_receive_word_idx.read();
4921	}
4922	else if (r_cc_receive_dcache_type.read() == CC_TYPE_INVAL) // hit inval
4923	{
4924	r_dcache_fsm = DCACHE_CC_INVAL;
4925	}
4926	}
4927	else // miss
4928	{
4929	// multicast acknowledgement required in case of update
4930	if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT)
4931	{
4932	r_dcache_fsm = DCACHE_CC_UPDT;
4933	r_dcache_cc_word = r_cc_receive_word_idx.read();
4934
4935	// just pop the fifo , don't write in icache
4936	r_dcache_cc_need_write = false;
4937	}
4938	else // No response needed
4939	{
4940	r_cc_receive_dcache_req = false;
4941	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4942	}
4943	}
4944
4945	#if DEBUG_DCACHE
4946	if (m_debug_dcache_fsm)
4947	{
4948	std::cout << " <PROC " << name()
4949	<< " DCACHE_CC_CHECK> Coherence request received:"
4950	<< " PADDR = " << std::hex << paddr
4951	<< " / TYPE = " << std::dec << r_cc_receive_dcache_type.read()
4952	<< " / HIT = " << (state == CACHE_SLOT_STATE_VALID) << std::endl;
4953	}
4954	#endif
4955
4956	break;
4957	}
4958	/////////////////////
4959	case DCACHE_CC_INVAL: // hit inval: switch slot to ZOMBI state and send a
4960	// CLEANUP after possible invalidation of copies in
4961	// TLBs
4962	{
4963	size_t way = r_dcache_cc_way.read();
4964	size_t set = r_dcache_cc_set.read();
4965
4966	if (r_dcache_in_tlb[way * m_dcache_sets + set]) // selective TLB inval
4967	{
4968	r_dcache_in_tlb[way * m_dcache_sets + set] = false;
4969	r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read();
4970	r_dcache_tlb_inval_set = 0;
4971	r_dcache_fsm_scan_save = r_dcache_fsm.read();
4972	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4973	break;
4974	}
4975
4976	if (r_dcache_contains_ptd[way * m_dcache_sets + set]) // TLB flush
4977	{
4978	r_itlb.reset();
4979	r_dtlb.reset();
4980	r_dcache_contains_ptd[way * m_dcache_sets + set] = false;
4981
4982	#if DEBUG_DCACHE
4983	if (m_debug_dcache_fsm)
4984	{
4985	std::cout << " <PROC " << name()
4986	<< " DCACHE_CC_INVAL> Flush DTLB & ITLB" << std::endl;
4987	}
4988	#endif
4989	}
4990
4991	assert(not r_dcache_cc_send_req.read() &&
4992	"ERROR in DCACHE_CC_INVAL: the r_dcache_cc_send_req "
4993	"must not be set");
4994
4995	// Switch slot state to ZOMBI and send CLEANUP command
4996	r_dcache.write_dir(way,
4997	set,
4998	CACHE_SLOT_STATE_ZOMBI);
4999
5000	// coherence request completed
5001	r_cc_receive_dcache_req = false;
5002	r_dcache_cc_send_req = true;
5003	r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read();
5004	r_dcache_cc_send_way = r_dcache_cc_way.read();
5005	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
5006	r_dcache_fsm = r_dcache_fsm_cc_save.read();
5007
5008	#if DEBUG_DCACHE
5009	if (m_debug_dcache_fsm)
5010	{
5011	std::cout << " <PROC " << name()
5012	<< " DCACHE_CC_INVAL> Switch slot to EMPTY state:" << std::dec
5013	<< " / WAY = " << way
5014	<< " / SET = " << set << std::endl;
5015	}
5016	#endif
5017	break;
5018	}
5019	///////////////////
5020	case DCACHE_CC_UPDT: // hit update: write one word per cycle,
5021	// after possible invalidation of copies in TLBs
5022	{
5023	size_t word = r_dcache_cc_word.read();
5024	size_t way = r_dcache_cc_way.read();
5025	size_t set = r_dcache_cc_set.read();
5026
5027	if (r_dcache_in_tlb[way * m_dcache_sets + set]) // selective TLB inval
5028	{
5029	r_dcache_in_tlb[way * m_dcache_sets + set] = false;
5030	r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read();
5031	r_dcache_tlb_inval_set = 0;
5032	r_dcache_fsm_scan_save = r_dcache_fsm.read();
5033	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
5034
5035	break;
5036	}
5037
5038	if (r_dcache_contains_ptd[way * m_dcache_sets + set]) // TLB flush
5039	{
5040	r_itlb.reset();
5041	r_dtlb.reset();
5042	r_dcache_contains_ptd[way * m_dcache_sets + set] = false;
5043
5044	#if DEBUG_DCACHE
5045	if (m_debug_dcache_fsm)
5046	{
5047	std::cout << " <PROC " << name()
5048	<< " DCACHE_CC_UPDT> Flush DTLB & ITLB" << std::endl;
5049	}
5050	#endif
5051	}
5052
5053	assert (not r_dcache_cc_send_req.read() &&
5054	"ERROR in DCACHE_CC_INVAL: the r_dcache_cc_send_req "
5055	"must not be set");
5056
5057	if (not r_cc_receive_updt_fifo_be.rok()) break;
5058
5059	if (r_dcache_cc_need_write.read())
5060	{
5061
5062	#ifdef INSTRUMENTATION
5063	m_cpt_dcache_data_write++;
5064	#endif
5065	r_dcache.write(way,
5066	set,
5067	word,
5068	r_cc_receive_updt_fifo_data.read(),
5069	r_cc_receive_updt_fifo_be.read());
5070
5071	r_dcache_cc_word = word + 1;
5072
5073	#if DEBUG_DCACHE
5074	if (m_debug_dcache_fsm)
5075	{
5076	std::cout << " <PROC " << name()
5077	<< " DCACHE_CC_UPDT> Write one word" << std::dec
5078	<< " / WAY = " << way
5079	<< " / SET = " << set
5080	<< " / WORD = " << word
5081	<< " / VALUE = " << std::hex << r_cc_receive_updt_fifo_data.read() << std::endl;
5082	}
5083	#endif
5084	}
5085
5086	if (r_cc_receive_updt_fifo_eop.read()) // last word
5087	{
5088	// no need to write in the cache anymore
5089	r_dcache_cc_need_write = false;
5090
5091	// coherence request completed
5092	r_cc_receive_dcache_req = false;
5093
5094	// request multicast acknowledgement
5095	r_dcache_cc_send_req = true;
5096	r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read();
5097	r_dcache_cc_send_updt_tab_idx = r_cc_receive_dcache_updt_tab_idx.read();
5098	r_dcache_cc_send_type = CC_TYPE_MULTI_ACK;
5099	r_dcache_fsm = r_dcache_fsm_cc_save.read();
5100	}
5101
5102	//consume fifo if not eop
5103	cc_receive_updt_fifo_get = true;
5104
5105	break;
5106	}
5107	///////////////////////////
5108	case DCACHE_INVAL_TLB_SCAN: // Scan sequencially all sets for both ITLB & DTLB
5109	// It makes assumption: m_itlb_sets == m_dtlb_sets
5110	// All ways are handled in parallel.
5111	// We enter this state when a DCACHE line is modified,
5112	// and there is a copy in itlb or dtlb.
5113	// It can be caused by:
5114	// - a coherence inval or updt transaction,
5115	// - a line inval caused by a cache miss
5116	// - a processor XTN inval request,
5117	// - a WRITE hit,
5118	// - a Dirty bit update
5119	// Input arguments are:
5120	// - r_dcache_tlb_inval_line
5121	// - r_dcache_tlb_inval_set
5122	// - r_dcache_fsm_scan_save
5123	{
5124	paddr_t line = r_dcache_tlb_inval_line.read();
5125	size_t set = r_dcache_tlb_inval_set.read();
5126	size_t way;
5127	bool ok;
5128
5129	for (way = 0; way < m_itlb_ways; way++)
5130	{
5131	ok = r_itlb.inval(line, way, set);
5132
5133	#if DEBUG_DCACHE
5134	if (m_debug_dcache_fsm and ok)
5135	{
5136	std::cout << " <PROC " << name()
5137	<< ".DCACHE_INVAL_TLB_SCAN> Invalidate ITLB entry:" << std::hex
5138	<< " line = " << line << std::dec
5139	<< " / set = " << set
5140	<< " / way = " << way << std::endl;
5141	}
5142	#endif
5143	}
5144
5145	for (way = 0; way < m_dtlb_ways; way++)
5146	{
5147	ok = r_dtlb.inval( line, way, set);
5148
5149	#if DEBUG_DCACHE
5150	if (m_debug_dcache_fsm and ok)
5151	std::cout << " <PROC " << name() << " DCACHE_INVAL_TLB_SCAN>"
5152	<< " Invalidate DTLB entry" << std::hex
5153	<< " / line = " << line << std::dec
5154	<< " / set = " << set
5155	<< " / way = " << way << std::endl;
5156	#endif
5157	}
5158
5159	// return to the calling state when TLB inval completed
5160	if (r_dcache_tlb_inval_set.read() == (m_dtlb_sets - 1))
5161	{
5162	r_dcache_fsm = r_dcache_fsm_scan_save.read();
5163	}
5164	r_dcache_tlb_inval_set = r_dcache_tlb_inval_set.read() + 1;
5165	break;
5166	}
5167	} // end switch r_dcache_fsm
5168
5169	///////////////// wbuf update ///////////////////////////////////////////////////////
5170	r_wbuf.update();
5171
5172	///////////////// llsc update ///////////////////////////////////////////////////////
5173	if (r_dcache_llsc_valid.read()) r_dcache_llsc_count = r_dcache_llsc_count.read() - 1;
5174	if (r_dcache_llsc_count.read() == 1) r_dcache_llsc_valid = false;
5175
5176	//////////////// test processor frozen //////////////////////////////////////////////
5177	// The simulation exit if the number of consecutive frozen cycles
5178	// is larger than the m_max_frozen_cycles (constructor parameter)
5179	if ((m_ireq.valid and not m_irsp.valid) or (m_dreq.valid and not m_drsp.valid))
5180	{
5181	m_cpt_frz_cycles++; // used for instrumentation
5182	m_cpt_stop_simulation++; // used for debug
5183	if (m_cpt_stop_simulation > m_max_frozen_cycles)
5184	{
5185	std::cout << std::dec << "ERROR in CC_VCACHE_WRAPPER " << name() << std::endl
5186	<< " stop at cycle " << m_cpt_total_cycles << std::endl
5187	<< " frozen since cycle " << m_cpt_total_cycles - m_max_frozen_cycles
5188	<< std::endl;
5189	r_iss.dump();
5190	exit(1);
5191	}
5192	}
5193	else
5194	{
5195	m_cpt_stop_simulation = 0;
5196	}
5197
5198	/////////// execute one iss cycle /////////////////////////////////
5199	{
5200	uint32_t it = 0;
5201	for (size_t i = 0; i < (size_t) iss_t::n_irq; i++) if (p_irq[i].read()) it \|= (1 << i);
5202	r_iss.executeNCycles(1, m_irsp, m_drsp, it);
5203	}
5204
5205	////////////////////////////////////////////////////////////////////////////
5206	// The VCI_CMD FSM controls the following ressources:
5207	// - r_vci_cmd_fsm
5208	// - r_vci_cmd_min
5209	// - r_vci_cmd_max
5210	// - r_vci_cmd_cpt
5211	// - r_vci_cmd_imiss_prio
5212	// - wbuf (reset)
5213	// - r_icache_miss_req (reset)
5214	// - r_icache_unc_req (reset)
5215	// - r_dcache_vci_miss_req (reset)
5216	// - r_dcache_vci_unc_req (reset)
5217	// - r_dcache_vci_ll_req (reset)
5218	// - r_dcache_vci_sc_req (reset in case of local sc fail)
5219	// - r_dcache_vci_cas_req (reset)
5220	//
5221	// This FSM handles requests from both the DCACHE FSM & the ICACHE FSM.
5222	// There are 8 request types, with the following priorities :
5223	// 1 - Data Read Miss : r_dcache_vci_miss_req and miss in the write buffer
5224	// 2 - Data Read Uncachable : r_dcache_vci_unc_req
5225	// 3 - Instruction Miss : r_icache_miss_req and miss in the write buffer
5226	// 4 - Instruction Uncachable : r_icache_unc_req
5227	// 5 - Data Write : r_wbuf.rok()
5228	// 6 - Data Linked Load : r_dcache_vci_ll_req
5229	// 7 - Data Store Conditionnal: r_dcache_vci_sc_req
5230	// 8 - Compare And Swap : r_dcache_vci_cas_req
5231	//
5232	// As we want to support several simultaneous VCI transactions, the VCI_CMD_FSM
5233	// and the VCI_RSP_FSM are fully desynchronized.
5234	//
5235	// VCI formats:
5236	// According to the VCI advanced specification, all read requests packets
5237	// (data Uncached, Miss data, instruction Uncached, Miss instruction)
5238	// are one word packets.
5239	// For write burst packets, all words are in the same cache line,
5240	// and addresses must be contiguous (the BE field is 0 in case of "holes").
5241	// The sc command packet implements actually a compare-and-swap mechanism
5242	// and the packet contains two flits.
5243	////////////////////////////////////////////////////////////////////////////////////
5244
5245
5246	switch (r_vci_cmd_fsm.read())
5247	{
5248	//////////////
5249	case CMD_IDLE:
5250	{
5251	// DCACHE read requests (r_dcache_vci_miss_req or r_dcache_vci_ll_req), and
5252	// ICACHE read requests (r_icache_miss_req) require both a write_buffer access
5253	// to check a possible pending write on the same cache line.
5254	// As there is only one possible access per cycle to write buffer, we implement
5255	// a round-robin priority between DCACHE and ICACHE for this access,
5256	// using the r_vci_cmd_imiss_prio flip-flop.
5257
5258	size_t wbuf_min;
5259	size_t wbuf_max;
5260
5261	bool dcache_miss_req = r_dcache_vci_miss_req.read() and
5262	(not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read());
5263
5264	bool dcache_ll_req = r_dcache_vci_ll_req.read() and
5265	(not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read());
5266
5267	bool dcache_sc_req = r_dcache_vci_sc_req.read() and
5268	(not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read());
5269
5270	bool dcache_cas_req = r_dcache_vci_cas_req.read() and
5271	(not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read());
5272
5273	bool icache_miss_req = r_icache_miss_req.read() and
5274	(not (r_dcache_vci_miss_req.read() or
5275	r_dcache_vci_ll_req.read() or
5276	r_dcache_vci_cas_req.read() or
5277	r_dcache_vci_sc_req.read()) or
5278	r_vci_cmd_imiss_prio.read());
5279
5280	// 1 - Data unc write
5281	if (r_dcache_vci_unc_req.read() and r_dcache_vci_unc_write.read())
5282	{
5283	r_vci_cmd_fsm = CMD_DATA_UNC_WRITE;
5284	r_dcache_vci_unc_req = false;
5285	}
5286	// 2 data read miss
5287	else if (dcache_miss_req and r_wbuf.miss(r_dcache_vci_paddr.read()))
5288	{
5289	r_vci_cmd_fsm = CMD_DATA_MISS;
5290	r_dcache_vci_miss_req = false;
5291	r_vci_cmd_imiss_prio = true;
5292	}
5293	// 3 - Data Read Uncachable
5294	else if (r_dcache_vci_unc_req.read() and not r_dcache_vci_unc_write.read())
5295	{
5296	r_vci_cmd_fsm = CMD_DATA_UNC_READ;
5297	r_dcache_vci_unc_req = false;
5298	}
5299	// 4 - Data Linked Load
5300	else if (dcache_ll_req and r_wbuf.miss(r_dcache_vci_paddr.read()))
5301	{
5302	r_vci_cmd_fsm = CMD_DATA_LL;
5303	r_dcache_vci_ll_req = false;
5304	r_vci_cmd_imiss_prio = true;
5305	}
5306	// 5 - Instruction Miss
5307	else if (icache_miss_req and r_wbuf.miss(r_icache_vci_paddr.read()))
5308	{
5309	r_vci_cmd_fsm = CMD_INS_MISS;
5310	r_icache_miss_req = false;
5311	r_vci_cmd_imiss_prio = false;
5312	}
5313	// 6 - Instruction Uncachable
5314	else if (r_icache_unc_req.read())
5315	{
5316	r_vci_cmd_fsm = CMD_INS_UNC;
5317	r_icache_unc_req = false;
5318	}
5319	// 7 - Data Write
5320	else if (r_wbuf.rok(&wbuf_min, &wbuf_max))
5321	{
5322	r_vci_cmd_fsm = CMD_DATA_WRITE;
5323	r_vci_cmd_cpt = wbuf_min;
5324	r_vci_cmd_min = wbuf_min;
5325	r_vci_cmd_max = wbuf_max;
5326	}
5327	// 8 - Data Store Conditionnal
5328	else if (dcache_sc_req and r_wbuf.miss(r_dcache_vci_paddr.read()))
5329	{
5330	r_vci_cmd_fsm = CMD_DATA_SC;
5331	r_dcache_vci_sc_req = false;
5332	r_vci_cmd_imiss_prio = true;
5333	r_vci_cmd_cpt = 0;
5334	}
5335	// 9 - Compare And Swap
5336	else if (dcache_cas_req and r_wbuf.miss(r_dcache_vci_paddr.read()))
5337	{
5338	r_vci_cmd_fsm = CMD_DATA_CAS;
5339	r_dcache_vci_cas_req = false;
5340	r_vci_cmd_imiss_prio = true;
5341	r_vci_cmd_cpt = 0;
5342	}
5343
5344	#if DEBUG_CMD
5345	if (m_debug_cmd_fsm )
5346	{
5347	std::cout << " <PROC " << name() << " CMD_IDLE>"
5348	<< " / dmiss_req = " << dcache_miss_req
5349	<< " / imiss_req = " << icache_miss_req
5350	<< std::endl;
5351	}
5352	#endif
5353	break;
5354	}
5355	////////////////////
5356	case CMD_DATA_WRITE:
5357	{
5358	if (p_vci.cmdack.read())
5359	{
5360	r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
5361	if (r_vci_cmd_cpt == r_vci_cmd_max) // last flit sent
5362	{
5363	r_vci_cmd_fsm = CMD_IDLE;
5364	r_wbuf.sent();
5365	}
5366	}
5367	break;
5368	}
5369	/////////////////
5370	case CMD_DATA_SC:
5371	case CMD_DATA_CAS:
5372	{
5373	// The CAS and SC VCI commands contain two flits
5374	if (p_vci.cmdack.read())
5375	{
5376	r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
5377	if (r_vci_cmd_cpt == 1) r_vci_cmd_fsm = CMD_IDLE ;
5378	}
5379	break;
5380	}
5381	//////////////////
5382	case CMD_INS_MISS:
5383	case CMD_INS_UNC:
5384	case CMD_DATA_MISS:
5385	case CMD_DATA_UNC_READ:
5386	case CMD_DATA_UNC_WRITE:
5387	case CMD_DATA_LL:
5388	{
5389	// all read VCI commands contain one single flit
5390	if (p_vci.cmdack.read()) {
5391	r_vci_cmd_fsm = CMD_IDLE;
5392	}
5393	break;
5394	}
5395
5396	} // end switch r_vci_cmd_fsm
5397
5398	//////////////////////////////////////////////////////////////////////////
5399	// The VCI_RSP FSM controls the following ressources:
5400	// - r_vci_rsp_fsm:
5401	// - r_vci_rsp_fifo_icache (push)
5402	// - r_vci_rsp_fifo_dcache (push)
5403	// - r_vci_rsp_data_error (set)
5404	// - r_vci_rsp_ins_error (set)
5405	// - r_vci_rsp_cpt
5406	// - r_dcache_vci_sc_req (reset when SC response recieved)
5407	//
5408	// As the VCI_RSP and VCI_CMD are fully desynchronized to support several
5409	// simultaneous VCI transactions, this FSM uses the VCI RPKTID field
5410	// to identify the transactions.
5411	//
5412	// VCI vormat:
5413	// This component checks the response packet length and accepts only
5414	// single word packets for write response packets.
5415	//
5416	// Error handling:
5417	// This FSM analyzes the VCI error code and signals directly the Write Bus Error.
5418	// In case of Read Data Error, the VCI_RSP FSM sets the r_vci_rsp_data_error
5419	// flip_flop and the error is signaled by the DCACHE FSM.
5420	// In case of Instruction Error, the VCI_RSP FSM sets the r_vci_rsp_ins_error
5421	// flip_flop and the error is signaled by the ICACHE FSM.
5422	// In case of Cleanup Error, the simulation stops with an error message...
5423	//////////////////////////////////////////////////////////////////////////
5424
5425	switch (r_vci_rsp_fsm.read())
5426	{
5427	//////////////
5428	case RSP_IDLE:
5429	{
5430	if (p_vci.rspval.read())
5431	{
5432	r_vci_rsp_cpt = 0;
5433
5434	if ((p_vci.rpktid.read() & 0x7) == TYPE_DATA_UNC)
5435	{
5436	// debug: verify that the available response concerns the current transaction.
5437	assert(r_dcache_wdt_timeout.read() == p_vci.rtrdid.read());
5438
5439	r_vci_rsp_fsm = RSP_DATA_UNC;
5440	}
5441	else if ((p_vci.rpktid.read() & 0x7) == TYPE_READ_DATA_MISS)
5442	{
5443	// debug: verify that the available response concerns the current transaction.
5444	assert(r_dcache_wdt_timeout.read() == p_vci.rtrdid.read());
5445
5446	r_vci_rsp_fsm = RSP_DATA_MISS;
5447	}
5448	else if ((p_vci.rpktid.read() & 0x7) == TYPE_READ_INS_UNC)
5449	{
5450	r_vci_rsp_fsm = RSP_INS_UNC;
5451	}
5452	else if ((p_vci.rpktid.read() & 0x7) == TYPE_READ_INS_MISS)
5453	{
5454	r_vci_rsp_fsm = RSP_INS_MISS;
5455	}
5456	else if ((p_vci.rpktid.read() & 0x7) == TYPE_WRITE)
5457	{
5458	r_vci_rsp_fsm = RSP_DATA_WRITE;
5459	}
5460	else if ((p_vci.rpktid.read() & 0x7) == TYPE_CAS)
5461	{
5462	r_vci_rsp_fsm = RSP_DATA_UNC;
5463	}
5464	else if ((p_vci.rpktid.read() & 0x7) == TYPE_LL)
5465	{
5466	r_vci_rsp_fsm = RSP_DATA_LL;
5467	}
5468	else if ((p_vci.rpktid.read() & 0x7) == TYPE_SC)
5469	{
5470	r_vci_rsp_fsm = RSP_DATA_UNC;
5471	}
5472	else
5473	{
5474	assert(false and "Unexpected VCI response");
5475	}
5476	}
5477	break;
5478	}
5479	//////////////////
5480	case RSP_INS_MISS:
5481	{
5482	if (p_vci.rspval.read())
5483	{
5484	if ((p_vci.rerror.read() & 0x1) != 0) // error reported
5485	{
5486	r_vci_rsp_ins_error = true;
5487	if (p_vci.reop.read()) r_vci_rsp_fsm = RSP_IDLE;
5488	}
5489	else // no error reported
5490	{
5491	if (r_vci_rsp_fifo_icache.wok())
5492	{
5493	if (r_vci_rsp_cpt.read() >= m_icache_words)
5494	{
5495	std::cout << "ERROR in VCI_CC_VCACHE " << name()
5496	<< " VCI response packet too long "
5497	<< " for instruction miss" << std::endl;
5498	exit(0);
5499	}
5500	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
5501	vci_rsp_fifo_icache_put = true,
5502	vci_rsp_fifo_icache_data = p_vci.rdata.read();
5503	if (p_vci.reop.read())
5504	{
5505	if (r_vci_rsp_cpt.read() != (m_icache_words - 1))
5506	{
5507	std::cout << "ERROR in VCI_CC_VCACHE " << name()
5508	<< " VCI response packet too short"
5509	<< " for instruction miss" << std::endl;
5510	exit(0);
5511	}
5512	r_vci_rsp_fsm = RSP_IDLE;
5513	}
5514	}
5515	}
5516	}
5517	break;
5518	}
5519	/////////////////
5520	case RSP_INS_UNC:
5521	{
5522	if (p_vci.rspval.read())
5523	{
5524	assert(p_vci.reop.read() and
5525	"illegal VCI response packet for uncachable instruction");
5526
5527	if ((p_vci.rerror.read() & 0x1) != 0) // error reported
5528	{
5529	r_vci_rsp_ins_error = true;
5530	r_vci_rsp_fsm = RSP_IDLE;
5531	}
5532	else // no error reported
5533	{
5534	if (r_vci_rsp_fifo_icache.wok())
5535	{
5536	vci_rsp_fifo_icache_put = true;
5537	vci_rsp_fifo_icache_data = p_vci.rdata.read();
5538	r_vci_rsp_fsm = RSP_IDLE;
5539	}
5540	}
5541	}
5542	break;
5543	}
5544	///////////////////
5545	case RSP_DATA_MISS:
5546	{
5547	if (p_vci.rspval.read())
5548	{
5549	if ((p_vci.rerror.read() & 0x1) != 0) // error reported
5550	{
5551	r_vci_rsp_data_error = true;
5552	if (p_vci.reop.read()) r_vci_rsp_fsm = RSP_IDLE;
5553	}
5554	else // no error reported
5555	{
5556	if (r_vci_rsp_fifo_dcache.wok())
5557	{
5558	assert((r_vci_rsp_cpt.read() < m_dcache_words) and
5559	"The VCI response packet for data miss is too long");
5560
5561	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
5562	vci_rsp_fifo_dcache_put = true,
5563	vci_rsp_fifo_dcache_data = p_vci.rdata.read();
5564	if (p_vci.reop.read())
5565	{
5566	assert((r_vci_rsp_cpt.read() == m_dcache_words - 1) and
5567	"The VCI response packet for data miss is too short");
5568
5569	r_vci_rsp_fsm = RSP_IDLE;
5570	}
5571	}
5572	}
5573	}
5574	break;
5575	}
5576	//////////////////
5577	case RSP_DATA_UNC:
5578	{
5579	if (p_vci.rspval.read())
5580	{
5581	assert(p_vci.reop.read() and
5582	"illegal VCI response packet for uncachable read data");
5583
5584	if ((p_vci.rerror.read() & 0x1) != 0) // error reported
5585	{
5586	r_vci_rsp_data_error = true;
5587	r_vci_rsp_fsm = RSP_IDLE;
5588	}
5589	else // no error reported
5590	{
5591	if (r_vci_rsp_fifo_dcache.wok())
5592	{
5593	vci_rsp_fifo_dcache_put = true;
5594	vci_rsp_fifo_dcache_data = p_vci.rdata.read();
5595	r_vci_rsp_fsm = RSP_IDLE;
5596	}
5597	}
5598	}
5599	break;
5600	}
5601	/////////////////
5602	case RSP_DATA_LL:
5603	{
5604	if (p_vci.rspval.read())
5605	{
5606	if ((p_vci.rerror.read() & 0x1) != 0) // error reported
5607	{
5608	r_vci_rsp_data_error = true;
5609	r_vci_rsp_fsm = RSP_IDLE;
5610	break;
5611	}
5612	if (r_vci_rsp_cpt.read() == 0) //first flit
5613	{
5614	if (r_vci_rsp_fifo_dcache.wok())
5615	{
5616	assert(!p_vci.reop.read() &&
5617	"illegal VCI response packet for LL");
5618	vci_rsp_fifo_dcache_put = true;
5619	vci_rsp_fifo_dcache_data = p_vci.rdata.read();
5620	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
5621	}
5622	break;
5623	}
5624	else // last flit
5625	{
5626	if (r_vci_rsp_fifo_dcache.wok())
5627	{
5628	assert(p_vci.reop.read() &&
5629	"illegal VCI response packet for LL");
5630	vci_rsp_fifo_dcache_put = true;
5631	vci_rsp_fifo_dcache_data = p_vci.rdata.read();
5632	r_vci_rsp_fsm = RSP_IDLE;
5633	}
5634	break;
5635	}
5636	}
5637	break;
5638	}
5639	////////////////////
5640	case RSP_DATA_WRITE:
5641	{
5642	if (p_vci.rspval.read())
5643	{
5644	assert(p_vci.reop.read() and
5645	"a VCI response packet must contain one flit for a write transaction");
5646
5647	r_vci_rsp_fsm = RSP_IDLE;
5648	uint32_t wbuf_index = p_vci.rtrdid.read();
5649	r_wbuf.completed(wbuf_index);
5650	if ((p_vci.rerror.read() & 0x1) != 0) r_iss.setWriteBerr();
5651	}
5652	break;
5653	}
5654	} // end switch r_vci_rsp_fsm
5655
5656	/////////////////////////////////////////////////////////////////////////////////////
5657	// The CC_SEND FSM is in charge of sending cleanups and the multicast
5658	// acknowledgements on the coherence network. It has two clients (DCACHE FSM
5659	// and ICACHE FSM) that are served with a round-robin priority.
5660	// The CC_SEND FSM resets the r_*cache_cc_send_req request flip-flops as
5661	// soon as the request has been sent.
5662	/////////////////////////////////////////////////////////////////////////////////////
5663	switch (r_cc_send_fsm.read())
5664	{
5665	///////////////////////////
5666	case CC_SEND_IDLE:
5667	{
5668	///////////////////////////////////////////////////////
5669	// handling round robin between icache and dcache : //
5670	// we first check for the last client and listen for //
5671	// a request of the other, then update the client //
5672	// r_cc_send_last_client : 0 dcache / 1 icache
5673	///////////////////////////////////////////////////////
5674	bool update_last_client = r_cc_send_last_client.read();
5675	if (r_cc_send_last_client.read() == 0) // last client was dcache
5676	{
5677	if (r_icache_cc_send_req.read()) // request from icache
5678	update_last_client = 1; // update last client to icache
5679	}
5680	else // last client was icache
5681	{
5682	if (r_dcache_cc_send_req.read()) // request from dcache
5683	update_last_client = 0; // update last client to dcache
5684	}
5685	r_cc_send_last_client = update_last_client;
5686
5687	// if there is an actual request
5688	if (r_dcache_cc_send_req.read() or r_icache_cc_send_req.read())
5689	{
5690	// the new client is dcache and has a cleanup request
5691	if ((update_last_client == 0) and
5692	(r_dcache_cc_send_type.read() == CC_TYPE_CLEANUP))
5693	r_cc_send_fsm = CC_SEND_CLEANUP_1;
5694	// the new client is dcache and has a multi acknowledgement request
5695	else if ((update_last_client == 0) and
5696	(r_dcache_cc_send_type.read() == CC_TYPE_MULTI_ACK))
5697	r_cc_send_fsm = CC_SEND_MULTI_ACK;
5698	// the new client is icache and has a cleanup request
5699	else if ((update_last_client == 1) and
5700	(r_icache_cc_send_type.read() == CC_TYPE_CLEANUP))
5701	r_cc_send_fsm = CC_SEND_CLEANUP_1;
5702	// the new client is icache and has a multi acknowledgement request
5703	else if ((update_last_client == 1) and
5704	(r_icache_cc_send_type.read() == CC_TYPE_MULTI_ACK))
5705	r_cc_send_fsm = CC_SEND_MULTI_ACK;
5706	}
5707	break;
5708	}
5709	///////////////////////////
5710	case CC_SEND_CLEANUP_1:
5711	{
5712	// wait for the first flit to be consumed
5713	if (p_dspin_p2m.read.read())
5714	r_cc_send_fsm = CC_SEND_CLEANUP_2;
5715
5716	break;
5717	}
5718	///////////////////////////
5719	case CC_SEND_CLEANUP_2:
5720	{
5721	// wait for the second flit to be consumed
5722	if (p_dspin_p2m.read.read())
5723	{
5724	if (r_cc_send_last_client.read() == 0) // dcache active request
5725	r_dcache_cc_send_req = false; // reset dcache request
5726	else // icache active request
5727	r_icache_cc_send_req = false; // reset icache request
5728
5729	// go back to idle state
5730	r_cc_send_fsm = CC_SEND_IDLE;
5731	}
5732	break;
5733	}
5734	///////////////////////////
5735	case CC_SEND_MULTI_ACK:
5736	{
5737	// wait for the flit to be consumed
5738	if (p_dspin_p2m.read.read())
5739	{
5740	if (r_cc_send_last_client.read() == 0) // dcache active request
5741	r_dcache_cc_send_req = false; // reset dcache request
5742	else // icache active request
5743	r_icache_cc_send_req = false; // reset icache request
5744	// go back to idle state
5745	r_cc_send_fsm = CC_SEND_IDLE;
5746	}
5747	break;
5748	}
5749	} // end switch CC_SEND FSM
5750
5751	///////////////////////////////////////////////////////////////////////////////
5752	// CC_RECEIVE FSM
5753	// This FSM receive all coherence packets on a DSPIN40 port.
5754	// There is 5 packet types:
5755	// - CC_DATA_INVAL : DCACHE invalidate request
5756	// - CC_DATA_UPDT : DCACHE update request (multi-words)
5757	// - CC_INST_INVAL : ICACHE invalidate request
5758	// - CC_INST_UPDT : ICACHE update request (multi-words)
5759	// - CC_BROADCAST : Broadcast invalidate request (both DCACHE & ICACHE)
5760	//////////////////////////////////////////////////////////////////////////////
5761	switch (r_cc_receive_fsm.read())
5762	{
5763	/////////////////////
5764	case CC_RECEIVE_IDLE:
5765	{
5766	// a coherence request has arrived
5767	if (p_dspin_m2p.write.read())
5768	{
5769	// initialize dspin received data
5770	uint64_t receive_data = p_dspin_m2p.data.read();
5771	// initialize coherence packet type
5772	uint64_t receive_type = DspinDhccpParam::dspin_get(receive_data,
5773	DspinDhccpParam::M2P_TYPE);
5774	// test for a broadcast
5775	if (DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::M2P_BC))
5776	{
5777	r_cc_receive_fsm = CC_RECEIVE_BRDCAST_HEADER;
5778	}
5779	// test for a multi updt
5780	else if (receive_type == DspinDhccpParam::TYPE_MULTI_UPDT_DATA)
5781	{
5782	r_cc_receive_fsm = CC_RECEIVE_DATA_UPDT_HEADER;
5783	}
5784	else if (receive_type == DspinDhccpParam::TYPE_MULTI_UPDT_INST)
5785	{
5786	r_cc_receive_fsm = CC_RECEIVE_INS_UPDT_HEADER;
5787	}
5788	// test for a multi inval
5789	else if (receive_type == DspinDhccpParam::TYPE_MULTI_INVAL_DATA)
5790	{
5791	r_cc_receive_fsm = CC_RECEIVE_DATA_INVAL_HEADER;
5792	}
5793	else
5794	{
5795	r_cc_receive_fsm = CC_RECEIVE_INS_INVAL_HEADER;
5796	}
5797	}
5798	break;
5799	}
5800	///////////////////////////////
5801	case CC_RECEIVE_BRDCAST_HEADER:
5802	{
5803	// no actual data in the HEADER, just skip to second flit
5804	r_cc_receive_fsm = CC_RECEIVE_BRDCAST_NLINE;
5805	break;
5806	}
5807	//////////////////////////////
5808	case CC_RECEIVE_BRDCAST_NLINE:
5809	{
5810	// initialize dspin received data
5811	uint64_t receive_data = p_dspin_m2p.data.read();
5812	// wait for both dcache and icache to take the request
5813	// TODO maybe we need to wait for both only to leave the state, but
5814	// not to actually post a request to an available cache => need a
5815	// flip_flop to check that ?
5816	if (not (r_cc_receive_icache_req.read()) and
5817	not (r_cc_receive_dcache_req.read()) and
5818	(p_dspin_m2p.write.read()))
5819	{
5820	// request dcache to handle the BROADCAST
5821	r_cc_receive_dcache_req = true;
5822	r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,
5823	DspinDhccpParam::BROADCAST_NLINE);
5824	r_cc_receive_dcache_type = CC_TYPE_INVAL;
5825	// request icache to handle the BROADCAST
5826	r_cc_receive_icache_req = true;
5827	r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,
5828	DspinDhccpParam::BROADCAST_NLINE);
5829	r_cc_receive_icache_type = CC_TYPE_INVAL;
5830	// get back to idle state
5831	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5832	break;
5833	}
5834	// keep waiting for the caches to accept the request
5835	break;
5836	}
5837	/////////////////////////////
5838	case CC_RECEIVE_DATA_INVAL_HEADER:
5839	{
5840	// sample updt tab index in the HEADER, then skip to second flit
5841	r_cc_receive_fsm = CC_RECEIVE_DATA_INVAL_NLINE;
5842	break;
5843	}
5844	/////////////////////////////
5845	case CC_RECEIVE_INS_INVAL_HEADER:
5846	{
5847	// sample updt tab index in the HEADER, then skip to second flit
5848	r_cc_receive_fsm = CC_RECEIVE_INS_INVAL_NLINE;
5849	break;
5850	}
5851	////////////////////////////
5852	case CC_RECEIVE_DATA_INVAL_NLINE:
5853	{
5854	// sample nline in the second flit
5855	uint64_t receive_data = p_dspin_m2p.data.read();
5856	// for data INVAL, wait for dcache to take the request
5857	if (p_dspin_m2p.write.read() and
5858	not r_cc_receive_dcache_req.read())
5859	{
5860	// request dcache to handle the INVAL
5861	r_cc_receive_dcache_req = true;
5862	r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_NLINE);
5863	r_cc_receive_dcache_type = CC_TYPE_INVAL;
5864	// get back to idle state
5865	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5866	break;
5867	}
5868	break;
5869	}
5870	//////////////////////////////
5871	case CC_RECEIVE_INS_INVAL_NLINE:
5872	{
5873	// sample nline in the second flit
5874	uint64_t receive_data = p_dspin_m2p.data.read();
5875	// for ins INVAL, wait for icache to take the request
5876	if (p_dspin_m2p.write.read() and
5877	not r_cc_receive_icache_req.read())
5878	{
5879	// request icache to handle the INVAL
5880	r_cc_receive_icache_req = true;
5881	r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_NLINE);
5882	r_cc_receive_icache_type = CC_TYPE_INVAL;
5883	// get back to idle state
5884	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5885	break;
5886	}
5887	break;
5888	}
5889	////////////////////////////
5890	case CC_RECEIVE_DATA_UPDT_HEADER:
5891	{
5892	// sample updt tab index in the HEADER, than skip to second flit
5893	uint64_t receive_data = p_dspin_m2p.data.read();
5894	// for data INVAL, wait for dcache to take the request and fifo to
5895	// be empty
5896	if (not r_cc_receive_dcache_req.read())
5897	{
5898	r_cc_receive_dcache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_UPDT_INDEX);
5899	r_cc_receive_fsm = CC_RECEIVE_DATA_UPDT_NLINE;
5900	break;
5901	}
5902	break;
5903	}
5904	////////////////////////////
5905	case CC_RECEIVE_INS_UPDT_HEADER:
5906	{
5907	// sample updt tab index in the HEADER, than skip to second flit
5908	uint64_t receive_data = p_dspin_m2p.data.read();
5909	// for ins INVAL, wait for icache to take the request and fifo to be
5910	// empty
5911	if (not r_cc_receive_icache_req.read())
5912	{
5913	r_cc_receive_icache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_UPDT_INDEX);
5914	r_cc_receive_fsm = CC_RECEIVE_INS_UPDT_NLINE;
5915	break;
5916	}
5917	// keep waiting for the correct cache to accept the request
5918	break;
5919	}
5920	///////////////////////////
5921	case CC_RECEIVE_DATA_UPDT_NLINE:
5922	{
5923	// sample nline and word index in the second flit
5924	uint64_t receive_data = p_dspin_m2p.data.read();
5925	// for data INVAL, wait for dcache to take the request and fifo to
5926	// be empty
5927	if (r_cc_receive_updt_fifo_be.empty() and
5928	p_dspin_m2p.write.read())
5929	{
5930	r_cc_receive_dcache_req = true;
5931	r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_NLINE);
5932	r_cc_receive_word_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_WORD_INDEX);
5933	r_cc_receive_dcache_type = CC_TYPE_UPDT;
5934	// get back to idle state
5935	r_cc_receive_fsm = CC_RECEIVE_DATA_UPDT_DATA;
5936	break;
5937	}
5938	break;
5939	}
5940	////////////////////////////
5941	case CC_RECEIVE_INS_UPDT_NLINE:
5942	{
5943	// sample nline and word index in the second flit
5944	uint64_t receive_data = p_dspin_m2p.data.read();
5945	// for ins INVAL, wait for icache to take the request and fifo to be
5946	// empty
5947	if (r_cc_receive_updt_fifo_be.empty() and
5948	p_dspin_m2p.write.read())
5949	{
5950	r_cc_receive_icache_req = true;
5951	r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_NLINE);
5952	r_cc_receive_word_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_WORD_INDEX);
5953	r_cc_receive_icache_type = CC_TYPE_UPDT;
5954	// get back to idle state
5955	r_cc_receive_fsm = CC_RECEIVE_INS_UPDT_DATA;
5956	break;
5957	}
5958	break;
5959	}
5960	//////////////////////////
5961	case CC_RECEIVE_DATA_UPDT_DATA:
5962	{
5963	// wait for the fifo
5964	if (r_cc_receive_updt_fifo_be.wok() and (p_dspin_m2p.write.read()))
5965	{
5966	uint64_t receive_data = p_dspin_m2p.data.read();
5967	bool receive_eop = p_dspin_m2p.eop.read();
5968	cc_receive_updt_fifo_be = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_BE);
5969	cc_receive_updt_fifo_data = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_DATA);
5970	cc_receive_updt_fifo_eop = receive_eop;
5971	cc_receive_updt_fifo_put = true;
5972	if (receive_eop ) r_cc_receive_fsm = CC_RECEIVE_IDLE;
5973	}
5974	break;
5975	}
5976	//////////////////////////
5977	case CC_RECEIVE_INS_UPDT_DATA:
5978	{
5979	// wait for the fifo
5980	if (r_cc_receive_updt_fifo_be.wok() and (p_dspin_m2p.write.read()))
5981	{
5982	uint64_t receive_data = p_dspin_m2p.data.read();
5983	bool receive_eop = p_dspin_m2p.eop.read();
5984	cc_receive_updt_fifo_be = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_BE);
5985	cc_receive_updt_fifo_data = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_DATA);
5986	cc_receive_updt_fifo_eop = receive_eop;
5987	cc_receive_updt_fifo_put = true;
5988	if (receive_eop ) r_cc_receive_fsm = CC_RECEIVE_IDLE;
5989	}
5990	break;
5991	}
5992
5993	} // end switch CC_RECEIVE FSM
5994
5995	///////////////// DSPIN CLACK interface ///////////////
5996
5997	uint64_t clack_type = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(),
5998	DspinDhccpParam::CLACK_TYPE);
5999
6000	size_t clack_way = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(),
6001	DspinDhccpParam::CLACK_WAY);
6002
6003	size_t clack_set = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(),
6004	DspinDhccpParam::CLACK_SET);
6005
6006	bool dspin_clack_get = false;
6007	bool dcache_clack_request = (clack_type == DspinDhccpParam::TYPE_CLACK_DATA);
6008	bool icache_clack_request = (clack_type == DspinDhccpParam::TYPE_CLACK_INST);
6009
6010	if (r_dspin_clack_req.read())
6011	{
6012	// CLACK DATA: Send request to DCACHE FSM
6013	if (dcache_clack_request and not r_dcache_clack_req.read())
6014	{
6015	r_dcache_clack_req = true;
6016	r_dcache_clack_way = clack_way & ((1ULL << (uint32_log2(m_dcache_ways))) - 1);
6017	r_dcache_clack_set = clack_set & ((1ULL << (uint32_log2(m_dcache_sets))) - 1);
6018	dspin_clack_get = true;
6019	}
6020
6021	// CLACK INST: Send request to ICACHE FSM
6022	else if (icache_clack_request and not r_icache_clack_req.read())
6023	{
6024	r_icache_clack_req = true;
6025	r_icache_clack_way = clack_way & ((1ULL<<(uint32_log2(m_dcache_ways)))-1);
6026	r_icache_clack_set = clack_set & ((1ULL<<(uint32_log2(m_icache_sets)))-1);
6027	dspin_clack_get = true;
6028	}
6029	}
6030	else
6031	{
6032	dspin_clack_get = true;
6033	}
6034
6035	if (dspin_clack_get)
6036	{
6037	r_dspin_clack_req = p_dspin_clack.write.read();
6038	r_dspin_clack_flit = p_dspin_clack.data.read();
6039	}
6040
6041	///////////////// Response FIFOs update //////////////////////
6042	r_vci_rsp_fifo_icache.update(vci_rsp_fifo_icache_get,
6043	vci_rsp_fifo_icache_put,
6044	vci_rsp_fifo_icache_data);
6045
6046	r_vci_rsp_fifo_dcache.update(vci_rsp_fifo_dcache_get,
6047	vci_rsp_fifo_dcache_put,
6048	vci_rsp_fifo_dcache_data);
6049
6050	///////////////// updt FIFO update //////////////////////
6051	//TODO check this
6052	r_cc_receive_updt_fifo_be.update(cc_receive_updt_fifo_get,
6053	cc_receive_updt_fifo_put,
6054	cc_receive_updt_fifo_be);
6055	r_cc_receive_updt_fifo_data.update(cc_receive_updt_fifo_get,
6056	cc_receive_updt_fifo_put,
6057	cc_receive_updt_fifo_data);
6058	r_cc_receive_updt_fifo_eop.update(cc_receive_updt_fifo_get,
6059	cc_receive_updt_fifo_put,
6060	cc_receive_updt_fifo_eop);
6061
6062	} // end transition()
6063
6064	///////////////////////
6065	tmpl(void)::genMoore()
6066	///////////////////////
6067	{
6068
6069	// VCI initiator command on the direct network
6070	// it depends on the CMD FSM state
6071
6072	bool is_sc_or_cas = (r_vci_cmd_fsm.read() == CMD_DATA_CAS) or
6073	(r_vci_cmd_fsm.read() == CMD_DATA_SC);
6074
6075	p_vci.pktid = 0;
6076	p_vci.srcid = m_srcid;
6077	p_vci.cons = is_sc_or_cas;
6078	p_vci.contig = not is_sc_or_cas;
6079	p_vci.wrap = false;
6080	p_vci.clen = 0;
6081	p_vci.cfixed = false;
6082
6083	if (m_monitor_ok) {
6084	if (p_vci.cmdack.read() == true and p_vci.cmdval == true) {
6085	if (((p_vci.address.read()) >= m_monitor_base) and
6086	((p_vci.address.read()) < m_monitor_base + m_monitor_length)) {
6087	std::cout << "CC_VCACHE Monitor " << name() << std::hex
6088	<< " Access type = " << vci_cmd_type_str[p_vci.cmd.read()]
6089	<< " Pktid type = " << vci_pktid_type_str[p_vci.pktid.read()]
6090	<< " : address = " << p_vci.address.read()
6091	<< " / be = " << p_vci.be.read();
6092	if (p_vci.cmd.read() == vci_param::CMD_WRITE ) {
6093	std::cout << " / data = " << p_vci.wdata.read();
6094	}
6095	std::cout << std::dec << std::endl;
6096	}
6097	}
6098	}
6099
6100	switch (r_vci_cmd_fsm.read()) {
6101
6102	case CMD_IDLE:
6103	p_vci.cmdval = false;
6104	p_vci.address = 0;
6105	p_vci.wdata = 0;
6106	p_vci.be = 0;
6107	p_vci.trdid = 0;
6108	p_vci.pktid = 0;
6109	p_vci.plen = 0;
6110	p_vci.cmd = vci_param::CMD_NOP;
6111	p_vci.eop = false;
6112	break;
6113
6114	case CMD_INS_MISS:
6115	p_vci.cmdval = true;
6116	p_vci.address = r_icache_vci_paddr.read() & m_icache_yzmask;
6117	p_vci.wdata = 0;
6118	p_vci.be = 0xF;
6119	p_vci.trdid = 0;
6120	p_vci.pktid = TYPE_READ_INS_MISS;
6121	p_vci.plen = m_icache_words << 2;
6122	p_vci.cmd = vci_param::CMD_READ;
6123	p_vci.eop = true;
6124	break;
6125
6126	case CMD_INS_UNC:
6127	p_vci.cmdval = true;
6128	p_vci.address = r_icache_vci_paddr.read() & ~0x3;
6129	p_vci.wdata = 0;
6130	p_vci.be = 0xF;
6131	p_vci.trdid = 0;
6132	p_vci.pktid = TYPE_READ_INS_UNC;
6133	p_vci.plen = 4;
6134	p_vci.cmd = vci_param::CMD_READ;
6135	p_vci.eop = true;
6136	break;
6137
6138	case CMD_DATA_MISS:
6139	p_vci.cmdval = true;
6140	p_vci.address = r_dcache_vci_paddr.read() & m_dcache_yzmask;
6141	p_vci.wdata = 0;
6142	p_vci.be = 0xF;
6143	p_vci.trdid = r_dcache_vci_wdt_trdid.read();
6144	p_vci.pktid = TYPE_READ_DATA_MISS;
6145	p_vci.plen = m_dcache_words << 2;
6146	p_vci.cmd = vci_param::CMD_READ;
6147	p_vci.eop = true;
6148	break;
6149
6150	case CMD_DATA_UNC_READ:
6151	p_vci.cmdval = true;
6152	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
6153	p_vci.wdata = r_dcache_vci_wdt_trdid.read();
6154	p_vci.be = r_dcache_vci_unc_be.read();
6155	p_vci.trdid = 0;
6156	p_vci.pktid = TYPE_DATA_UNC;
6157	p_vci.plen = 4;
6158	p_vci.cmd = vci_param::CMD_READ;
6159	p_vci.eop = true;
6160	break;
6161
6162	case CMD_DATA_UNC_WRITE:
6163	p_vci.cmdval = true;
6164	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
6165	p_vci.wdata = r_dcache_vci_wdata.read();
6166	p_vci.be = r_dcache_vci_unc_be.read();
6167	p_vci.trdid = r_dcache_vci_wdt_trdid.read();
6168	p_vci.pktid = TYPE_DATA_UNC;
6169	p_vci.plen = 4;
6170	p_vci.cmd = vci_param::CMD_WRITE;
6171	p_vci.eop = true;
6172	break;
6173
6174	case CMD_DATA_WRITE:
6175	p_vci.cmdval = true;
6176	p_vci.address = r_wbuf.getAddress(r_vci_cmd_cpt.read()) & ~0x3;
6177	p_vci.wdata = r_wbuf.getData(r_vci_cmd_cpt.read());
6178	p_vci.be = r_wbuf.getBe(r_vci_cmd_cpt.read());
6179	p_vci.trdid = r_wbuf.getIndex();
6180	p_vci.pktid = TYPE_WRITE;
6181	p_vci.plen = (r_vci_cmd_max.read() - r_vci_cmd_min.read() + 1) << 2;
6182	p_vci.cmd = vci_param::CMD_WRITE;
6183	p_vci.eop = (r_vci_cmd_cpt.read() == r_vci_cmd_max.read());
6184	break;
6185
6186	case CMD_DATA_LL:
6187	p_vci.cmdval = true;
6188	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
6189	p_vci.wdata = 0;
6190	p_vci.be = 0xF;
6191	p_vci.trdid = 0;
6192	p_vci.pktid = TYPE_LL;
6193	p_vci.plen = 8;
6194	p_vci.cmd = vci_param::CMD_LOCKED_READ;
6195	p_vci.eop = true;
6196	break;
6197
6198	case CMD_DATA_SC:
6199	p_vci.cmdval = true;
6200	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
6201	if (r_vci_cmd_cpt.read() == 0) p_vci.wdata = r_dcache_llsc_key.read();
6202	else p_vci.wdata = r_dcache_vci_sc_data.read();
6203	p_vci.be = 0xF;
6204	p_vci.trdid = 0;
6205	p_vci.pktid = TYPE_SC;
6206	p_vci.plen = 8;
6207	p_vci.cmd = vci_param::CMD_NOP;
6208	p_vci.eop = (r_vci_cmd_cpt.read() == 1);
6209	break;
6210
6211	case CMD_DATA_CAS:
6212	p_vci.cmdval = true;
6213	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
6214	if (r_vci_cmd_cpt.read() == 0) p_vci.wdata = r_dcache_vci_cas_old.read();
6215	else p_vci.wdata = r_dcache_vci_cas_new.read();
6216	p_vci.be = 0xF;
6217	p_vci.trdid = 0;
6218	p_vci.pktid = TYPE_CAS;
6219	p_vci.plen = 8;
6220	p_vci.cmd = vci_param::CMD_NOP;
6221	p_vci.eop = (r_vci_cmd_cpt.read() == 1);
6222	break;
6223	} // end switch r_vci_cmd_fsm
6224
6225	// VCI initiator response on the direct network
6226	// it depends on the VCI_RSP FSM
6227
6228	switch (r_vci_rsp_fsm.read())
6229	{
6230	case RSP_DATA_WRITE : p_vci.rspack = true; break;
6231	case RSP_INS_MISS : p_vci.rspack = r_vci_rsp_fifo_icache.wok(); break;
6232	case RSP_INS_UNC : p_vci.rspack = r_vci_rsp_fifo_icache.wok(); break;
6233	case RSP_DATA_MISS : p_vci.rspack = r_vci_rsp_fifo_dcache.wok(); break;
6234	case RSP_DATA_UNC : p_vci.rspack = r_vci_rsp_fifo_dcache.wok(); break;
6235	case RSP_DATA_LL : p_vci.rspack = r_vci_rsp_fifo_dcache.wok(); break;
6236	case RSP_IDLE : p_vci.rspack = false; break;
6237	} // end switch r_vci_rsp_fsm
6238
6239
6240	// Send coherence packets on DSPIN P2M
6241	// it depends on the CC_SEND FSM
6242
6243	uint64_t dspin_send_data = 0;
6244	switch (r_cc_send_fsm.read())
6245	{
6246	//////////////////
6247	case CC_SEND_IDLE:
6248	{
6249	p_dspin_p2m.write = false;
6250	break;
6251	}
6252	///////////////////////
6253	case CC_SEND_CLEANUP_1:
6254	{
6255	// initialize dspin send data
6256	DspinDhccpParam::dspin_set(dspin_send_data,
6257	m_cc_global_id,
6258	DspinDhccpParam::CLEANUP_SRCID);
6259	DspinDhccpParam::dspin_set(dspin_send_data,
6260	0,
6261	DspinDhccpParam::P2M_BC);
6262
6263	if (r_cc_send_last_client.read() == 0) // dcache active request
6264	{
6265	uint64_t dest = (uint64_t) r_dcache_cc_send_nline.read()
6266	>> (m_nline_width - m_x_width - m_y_width)
6267	<< (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
6268
6269	DspinDhccpParam::dspin_set(dspin_send_data,
6270	dest,
6271	DspinDhccpParam::CLEANUP_DEST);
6272
6273	DspinDhccpParam::dspin_set(dspin_send_data,
6274	(r_dcache_cc_send_nline.read() & 0x300000000ULL)>>32,
6275	DspinDhccpParam::CLEANUP_NLINE_MSB);
6276
6277	DspinDhccpParam::dspin_set(dspin_send_data,
6278	r_dcache_cc_send_way.read(),
6279	DspinDhccpParam::CLEANUP_WAY_INDEX);
6280
6281	DspinDhccpParam::dspin_set(dspin_send_data,
6282	DspinDhccpParam::TYPE_CLEANUP_DATA,
6283	DspinDhccpParam::P2M_TYPE);
6284	}
6285	else // icache active request
6286	{
6287	uint64_t dest = (uint64_t) r_icache_cc_send_nline.read()
6288	>> (m_nline_width - m_x_width - m_y_width)
6289	<< (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
6290
6291	DspinDhccpParam::dspin_set(dspin_send_data,
6292	dest,
6293	DspinDhccpParam::CLEANUP_DEST);
6294
6295	DspinDhccpParam::dspin_set(dspin_send_data,
6296	(r_icache_cc_send_nline.read() & 0x300000000ULL) >> 32,
6297	DspinDhccpParam::CLEANUP_NLINE_MSB);
6298
6299	DspinDhccpParam::dspin_set(dspin_send_data,
6300	r_icache_cc_send_way.read(),
6301	DspinDhccpParam::CLEANUP_WAY_INDEX);
6302
6303	DspinDhccpParam::dspin_set(dspin_send_data,
6304	DspinDhccpParam::TYPE_CLEANUP_INST,
6305	DspinDhccpParam::P2M_TYPE);
6306	}
6307	// send flit
6308	p_dspin_p2m.data = dspin_send_data;
6309	p_dspin_p2m.write = true;
6310	p_dspin_p2m.eop = false;
6311	break;
6312	}
6313	///////////////////////
6314	case CC_SEND_CLEANUP_2:
6315	{
6316	// initialize dspin send data
6317
6318	if (r_cc_send_last_client.read() == 0) // dcache active request
6319	{
6320	DspinDhccpParam::dspin_set(dspin_send_data,
6321	r_dcache_cc_send_nline.read() & 0xFFFFFFFFULL,
6322	DspinDhccpParam::CLEANUP_NLINE_LSB);
6323	}
6324	else // icache active request
6325	{
6326	DspinDhccpParam::dspin_set(dspin_send_data,
6327	r_icache_cc_send_nline.read() & 0xFFFFFFFFULL,
6328	DspinDhccpParam::CLEANUP_NLINE_LSB);
6329	}
6330	// send flit
6331	p_dspin_p2m.data = dspin_send_data;
6332	p_dspin_p2m.write = true;
6333	p_dspin_p2m.eop = true;
6334	break;
6335	}
6336	///////////////////////
6337	case CC_SEND_MULTI_ACK:
6338	{
6339	// initialize dspin send data
6340	DspinDhccpParam::dspin_set(dspin_send_data,
6341	0,
6342	DspinDhccpParam::P2M_BC);
6343	DspinDhccpParam::dspin_set(dspin_send_data,
6344	DspinDhccpParam::TYPE_MULTI_ACK,
6345	DspinDhccpParam::P2M_TYPE);
6346
6347	if (r_cc_send_last_client.read() == 0) // dcache active request
6348	{
6349	uint64_t dest = (uint64_t) r_dcache_cc_send_nline.read()
6350	>> (m_nline_width - m_x_width - m_y_width)
6351	<< (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
6352
6353	DspinDhccpParam::dspin_set(dspin_send_data,
6354	dest,
6355	DspinDhccpParam::MULTI_ACK_DEST);
6356
6357	DspinDhccpParam::dspin_set(dspin_send_data,
6358	r_dcache_cc_send_updt_tab_idx.read(),
6359	DspinDhccpParam::MULTI_ACK_UPDT_INDEX);
6360	}
6361	else // icache active request
6362	{
6363	uint64_t dest = (uint64_t) r_icache_cc_send_nline.read()
6364	>> (m_nline_width - m_x_width - m_y_width)
6365	<< (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
6366
6367
6368	DspinDhccpParam::dspin_set(dspin_send_data,
6369	dest,
6370	DspinDhccpParam::MULTI_ACK_DEST);
6371
6372	DspinDhccpParam::dspin_set(dspin_send_data,
6373	r_icache_cc_send_updt_tab_idx.read(),
6374	DspinDhccpParam::MULTI_ACK_UPDT_INDEX);
6375	}
6376	// send flit
6377	p_dspin_p2m.data = dspin_send_data;
6378	p_dspin_p2m.write = true;
6379	p_dspin_p2m.eop = true;
6380
6381	break;
6382	}
6383	} // end switch CC_SEND FSM
6384
6385	// Receive coherence packets
6386	// It depends on the CC_RECEIVE FSM
6387	switch (r_cc_receive_fsm.read())
6388	{
6389	/////////////////////
6390	case CC_RECEIVE_IDLE:
6391	{
6392	p_dspin_m2p.read = false;
6393	break;
6394	}
6395	///////////////////////////////
6396	case CC_RECEIVE_BRDCAST_HEADER:
6397	{
6398	p_dspin_m2p.read = true;
6399	break;
6400	}
6401	//////////////////////////////
6402	case CC_RECEIVE_BRDCAST_NLINE:
6403	{
6404	// TODO maybe we need to wait for both only to leave the state, but
6405	// not to actually post a request to an available cache => need a
6406	// flip_flop to check that ?
6407	if (not (r_cc_receive_icache_req.read()) and not (r_cc_receive_dcache_req.read()))
6408	p_dspin_m2p.read = true;
6409	else
6410	p_dspin_m2p.read = false;
6411	break;
6412	}
6413	/////////////////////////////
6414	case CC_RECEIVE_DATA_INVAL_HEADER:
6415	case CC_RECEIVE_INS_INVAL_HEADER:
6416	{
6417	p_dspin_m2p.read = true;
6418	break;
6419	}
6420	////////////////////////////
6421	case CC_RECEIVE_DATA_INVAL_NLINE:
6422	{
6423	p_dspin_m2p.read = not r_cc_receive_dcache_req.read();
6424	break;
6425	}
6426	case CC_RECEIVE_INS_INVAL_NLINE:
6427	{
6428	p_dspin_m2p.read = not r_cc_receive_icache_req.read();
6429	break;
6430	}
6431	///////////////////////////
6432	case CC_RECEIVE_DATA_UPDT_HEADER:
6433	{
6434	if (not r_cc_receive_dcache_req.read())
6435	p_dspin_m2p.read = true;
6436	else
6437	p_dspin_m2p.read = false;
6438	break;
6439	}
6440	////////////////////////////
6441	case CC_RECEIVE_INS_UPDT_HEADER:
6442	{
6443	if (not r_cc_receive_icache_req.read())
6444	p_dspin_m2p.read = true;
6445	else
6446	p_dspin_m2p.read = false;
6447	break;
6448	}
6449	///////////////////////////
6450	case CC_RECEIVE_DATA_UPDT_NLINE:
6451	case CC_RECEIVE_INS_UPDT_NLINE:
6452	{
6453	if (r_cc_receive_updt_fifo_be.empty())
6454	p_dspin_m2p.read = true;
6455	else
6456	p_dspin_m2p.read = false;
6457	break;
6458	}
6459	///////////////////////////
6460	case CC_RECEIVE_DATA_UPDT_DATA:
6461	case CC_RECEIVE_INS_UPDT_DATA:
6462	{
6463	if (r_cc_receive_updt_fifo_be.wok())
6464	p_dspin_m2p.read = true;
6465	else
6466	p_dspin_m2p.read = false;
6467	break;
6468	}
6469	} // end switch CC_RECEIVE FSM
6470
6471
6472	int clack_type = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(),
6473	DspinDhccpParam::CLACK_TYPE);
6474
6475	bool dspin_clack_get = false;
6476	bool dcache_clack_request = (clack_type == DspinDhccpParam::TYPE_CLACK_DATA);
6477	bool icache_clack_request = (clack_type == DspinDhccpParam::TYPE_CLACK_INST);
6478
6479	if (r_dspin_clack_req.read())
6480	{
6481	// CLACK DATA: wait if pending request to DCACHE FSM
6482	if (dcache_clack_request and not r_dcache_clack_req.read())
6483	{
6484	dspin_clack_get = true;
6485	}
6486
6487	// CLACK INST: wait if pending request to ICACHE FSM
6488	else if (icache_clack_request and not r_icache_clack_req.read())
6489	{
6490	dspin_clack_get = true;
6491	}
6492	}
6493	else
6494	{
6495	dspin_clack_get = true;
6496	}
6497
6498	p_dspin_clack.read = dspin_clack_get;
6499	} // end genMoore
6500
6501	tmpl(void)::start_monitor(paddr_t base, paddr_t length)
6502	// This version of monitor print both Read and Write request
6503	{
6504	m_monitor_ok = true;
6505	m_monitor_base = base;
6506	m_monitor_length = length;
6507	}
6508
6509	tmpl(void)::stop_monitor()
6510	{
6511	m_monitor_ok = false;
6512	}
6513
6514	}}
6515
6516	// Local Variables:
6517	// tab-width: 4
6518	// c-basic-offset: 4
6519	// c-file-offsets:((innamespace . 0)(inline-open . 0))
6520	// indent-tabs-mode: nil
6521	// End:
6522
6523	// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4

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