[747] | 1 | /////////////////////////////////////////////////////////////////////////////// |
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| 2 | // File: top.cpp (for tsar_generic_iob platform) |
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| 3 | // Author: Alain Greiner |
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| 4 | // Copyright: UPMC/LIP6 |
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| 5 | // Date : august 2013 |
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| 6 | // This program is released under the GNU public license |
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[875] | 7 | // |
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| 8 | // Modified by: Cesar Fuguet |
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[747] | 9 | /////////////////////////////////////////////////////////////////////////////// |
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| 10 | // This file define a generic TSAR architecture with an IO network emulating |
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| 11 | // an external bus (i.e. Hypertransport) to access 7 external peripherals: |
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| 12 | // |
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| 13 | // - FBUF : Frame Buffer |
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| 14 | // - MTTY : multi TTY (one channel) |
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| 15 | // - MNIC : Network controller (up to 2 channels) |
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| 16 | // - CDMA : Chained Buffer DMA controller (up to 4 channels) |
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| 17 | // - BDEV : Dlock Device controler (one channel) |
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| 18 | // - IOPI : HWI to SWI translator. |
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[875] | 19 | // - SIMH : Simulation Helper |
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[747] | 20 | // |
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| 21 | // The internal physical address space is 40 bits, and the cluster index |
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| 22 | // is defined by the 8 MSB bits, using a fixed format: X is encoded on 4 bits, |
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| 23 | // Y is encodes on 4 bits, whatever the actual mesh size. |
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| 24 | // => at most 16 * 16 clusters. Each cluster contains up to 4 processors. |
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| 25 | // |
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| 26 | // It contains 3 networks: |
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| 27 | // |
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| 28 | // 1) the "INT" network supports Read/Write transactions |
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| 29 | // between processors and L2 caches or peripherals. |
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| 30 | // (VCI ADDDRESS = 40 bits / VCI DATA width = 32 bits) |
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| 31 | // It supports also coherence transactions between L1 & L2 caches. |
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| 32 | // 3) the "RAM" network emulates the 3D network between L2 caches |
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| 33 | // and L3 caches, and is implemented as a 2D mesh between the L2 caches, |
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| 34 | // the two IO bridges and the physical RAMs disributed in all clusters. |
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| 35 | // (VCI ADDRESS = 40 bits / VCI DATA = 64 bits) |
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| 36 | // 4) the IOX network connects the two IO bridge components to the |
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| 37 | // 7 external peripheral controllers. |
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| 38 | // (VCI ADDDRESS = 40 bits / VCI DATA width = 64 bits) |
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| 39 | // |
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| 40 | // The external peripherals HWI IRQs are translated to WTI IRQs by the |
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| 41 | // external IOPIC component, that must be configured by the OS to route |
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[875] | 42 | // these WTI IRQS to one or several internal XICU components. |
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[747] | 43 | // - IOPIC HWI[1:0] connected to IRQ_NIC_RX[1:0] |
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| 44 | // - IOPIC HWI[3:2] connected to IRQ_NIC_TX[1:0] |
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| 45 | // - IOPIC HWI[7:4] connected to IRQ_CMA_TX[3:0]] |
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| 46 | // - IOPIC HWI[8] connected to IRQ_BDEV |
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[875] | 47 | // - IOPIC HWI[31:16] connected to IRQ_TTY_RX[15:0] |
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[747] | 48 | // |
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| 49 | // Besides the external peripherals, each cluster contains one XICU component, |
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| 50 | // and one multi channels DMA component. |
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| 51 | // The XICU component is mainly used to handle WTI IRQs, as only 5 HWI IRQs |
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| 52 | // are connected to XICU in each cluster: |
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| 53 | // - IRQ_IN[0] : MMC |
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| 54 | // - IRQ_IN[1] : DMA channel 0 |
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| 55 | // - IRQ_IN[2] : DMA channel 1 |
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| 56 | // - IRQ_IN[3] : DMA channel 2 |
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| 57 | // - IRQ_IN[4] : DMA channel 3 |
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| 58 | // |
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[855] | 59 | // All clusters are identical, but cluster(0, 0) and cluster(X_SIZE-1, Y_SIZE-1) |
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[747] | 60 | // contain an extra IO bridge component. These IOB0 & IOB1 components are |
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| 61 | // connected to the three networks (INT, RAM, IOX). |
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| 62 | // |
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| 63 | // - It uses two dspin_local_crossbar per cluster to implement the |
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| 64 | // local interconnect correponding to the INT network. |
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| 65 | // - It uses three dspin_local_crossbar per cluster to implement the |
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| 66 | // local interconnect correponding to the coherence INT network. |
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| 67 | // - It uses two virtual_dspin_router per cluster to implement |
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| 68 | // the INT network (routing both the direct and coherence trafic). |
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| 69 | // - It uses two dspin_router per cluster to implement the RAM network. |
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| 70 | // - It uses the vci_cc_vcache_wrapper. |
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| 71 | // - It uses the vci_mem_cache. |
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| 72 | // - It contains one vci_xicu and one vci_multi_dma per cluster. |
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| 73 | // - It contains one vci_simple ram per cluster to model the L3 cache. |
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| 74 | // |
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| 75 | // The TsarIobCluster component is defined in files |
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| 76 | // tsar_iob_cluster.* (with * = cpp, h, sd) |
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| 77 | // |
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| 78 | // The main hardware parameters must be defined in the hard_config.h file : |
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| 79 | // - X_SIZE : number of clusters in a row |
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| 80 | // - Y_SIZE : number of clusters in a column |
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| 81 | // - NB_PROCS_MAX : number of processors per cluster (power of 2) |
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[875] | 82 | // - NB_TTY_CHANNELS : number of TTY channels in I/O network (up to 16) |
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[747] | 83 | // - NB_NIC_CHANNELS : number of NIC channels in I/O network (up to 2) |
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| 84 | // - NB_CMA_CHANNELS : number of CMA channels in I/O network (up to 4) |
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| 85 | // - FBUF_X_SIZE : width of frame buffer (pixels) |
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| 86 | // - FBUF_Y_SIZE : heigth of frame buffer (lines) |
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| 87 | // - XCU_NB_INPUTS : number of HWIs = number of WTIs = number of PTIs |
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| 88 | // |
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| 89 | // Some secondary hardware parameters must be defined in this top.cpp file: |
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| 90 | // - XRAM_LATENCY : external ram latency |
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| 91 | // - MEMC_WAYS : L2 cache number of ways |
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| 92 | // - MEMC_SETS : L2 cache number of sets |
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| 93 | // - L1_IWAYS |
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| 94 | // - L1_ISETS |
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| 95 | // - L1_DWAYS |
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| 96 | // - L1_DSETS |
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| 97 | // - BDEV_IMAGE_NAME : file pathname for block device |
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| 98 | // - NIC_RX_NAME : file pathname for NIC received packets |
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| 99 | // - NIC_TX_NAME : file pathname for NIC transmited packets |
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| 100 | // - NIC_TIMEOUT : max number of cycles before closing a container |
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| 101 | // |
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| 102 | // General policy for 40 bits physical address decoding: |
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| 103 | // All physical segments base addresses are multiple of 1 Mbytes |
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| 104 | // (=> the 24 LSB bits = 0, and the 16 MSB bits define the target) |
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[806] | 105 | // The (X_WIDTH + Y_WIDTH) MSB bits (left aligned) define |
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[747] | 106 | // the cluster index, and the LADR bits define the local index: |
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| 107 | // |X_ID|Y_ID| LADR | OFFSET | |
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| 108 | // | 4 | 4 | 8 | 24 | |
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| 109 | // |
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| 110 | // General policy for 14 bits SRCID decoding: |
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| 111 | // Each component is identified by (x_id, y_id, l_id) tuple. |
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| 112 | // |X_ID|Y_ID| L_ID | |
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| 113 | // | 4 | 4 | 6 | |
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| 114 | ///////////////////////////////////////////////////////////////////////// |
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| 115 | |
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| 116 | #include <systemc> |
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| 117 | #include <sys/time.h> |
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| 118 | #include <iostream> |
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| 119 | #include <sstream> |
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| 120 | #include <cstdlib> |
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| 121 | #include <cstdarg> |
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[750] | 122 | #include <climits> |
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[747] | 123 | #include <stdint.h> |
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| 124 | |
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| 125 | #include "gdbserver.h" |
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| 126 | #include "mapping_table.h" |
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| 127 | |
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| 128 | #include "tsar_iob_cluster.h" |
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| 129 | #include "vci_chbuf_dma.h" |
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| 130 | #include "vci_multi_tty.h" |
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| 131 | #include "vci_multi_nic.h" |
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| 132 | #include "vci_simple_rom.h" |
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| 133 | #include "vci_block_device_tsar.h" |
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| 134 | #include "vci_framebuffer.h" |
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| 135 | #include "vci_iox_network.h" |
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| 136 | #include "vci_iox_network.h" |
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| 137 | #include "vci_iopic.h" |
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[769] | 138 | #include "vci_simhelper.h" |
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[747] | 139 | |
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| 140 | #include "alloc_elems.h" |
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| 141 | |
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| 142 | /////////////////////////////////////////////////// |
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| 143 | // OS |
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| 144 | /////////////////////////////////////////////////// |
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| 145 | #define USE_ALMOS 0 |
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| 146 | |
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| 147 | #define almos_bootloader_pathname "bootloader.bin" |
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| 148 | #define almos_kernel_pathname "kernel-soclib.bin@0xbfc10000:D" |
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| 149 | #define almos_archinfo_pathname "arch-info.bin@0xBFC08000:D" |
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| 150 | |
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| 151 | /////////////////////////////////////////////////// |
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| 152 | // Parallelisation |
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| 153 | /////////////////////////////////////////////////// |
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| 154 | #if USE_OPENMP |
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| 155 | #include <omp.h> |
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| 156 | #endif |
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| 157 | |
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| 158 | /////////////////////////////////////////////////////////// |
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| 159 | // DSPIN parameters |
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| 160 | /////////////////////////////////////////////////////////// |
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| 161 | |
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| 162 | #define dspin_int_cmd_width 39 |
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| 163 | #define dspin_int_rsp_width 32 |
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| 164 | |
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| 165 | #define dspin_ram_cmd_width 64 |
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| 166 | #define dspin_ram_rsp_width 64 |
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| 167 | |
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| 168 | /////////////////////////////////////////////////////////// |
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| 169 | // VCI fields width for the 3 VCI networks |
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| 170 | /////////////////////////////////////////////////////////// |
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| 171 | |
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| 172 | #define vci_cell_width_int 4 |
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| 173 | #define vci_cell_width_ext 8 |
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| 174 | |
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| 175 | #define vci_plen_width 8 |
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| 176 | #define vci_address_width 40 |
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| 177 | #define vci_rerror_width 1 |
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| 178 | #define vci_clen_width 1 |
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| 179 | #define vci_rflag_width 1 |
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| 180 | #define vci_srcid_width 14 |
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| 181 | #define vci_pktid_width 4 |
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| 182 | #define vci_trdid_width 4 |
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| 183 | #define vci_wrplen_width 1 |
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| 184 | |
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| 185 | //////////////////////////////////////////////////////////// |
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| 186 | // Main Hardware Parameters values |
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| 187 | //////////////////////i///////////////////////////////////// |
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| 188 | |
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| 189 | #include "hard_config.h" |
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| 190 | |
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| 191 | //////////////////////////////////////////////////////////// |
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| 192 | // Secondary Hardware Parameters values |
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| 193 | //////////////////////i///////////////////////////////////// |
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| 194 | |
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| 195 | #define XRAM_LATENCY 0 |
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| 196 | |
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| 197 | #define MEMC_WAYS 16 |
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| 198 | #define MEMC_SETS 256 |
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| 199 | |
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| 200 | #define L1_IWAYS 4 |
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| 201 | #define L1_ISETS 64 |
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| 202 | |
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| 203 | #define L1_DWAYS 4 |
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| 204 | #define L1_DSETS 64 |
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| 205 | |
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| 206 | #define BDEV_IMAGE_NAME "../../../giet_vm/hdd/virt_hdd.dmg" |
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| 207 | |
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[760] | 208 | #define NIC_RX_NAME "/dev/null" |
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| 209 | #define NIC_TX_NAME "/dev/null" |
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[747] | 210 | #define NIC_TIMEOUT 10000 |
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| 211 | |
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| 212 | #define NORTH 0 |
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| 213 | #define SOUTH 1 |
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| 214 | #define EAST 2 |
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| 215 | #define WEST 3 |
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| 216 | |
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[855] | 217 | #define cluster(x, y) ((y) + ((x) << Y_WIDTH)) |
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[747] | 218 | |
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| 219 | //////////////////////////////////////////////////////////// |
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| 220 | // Software to be loaded in ROM & RAM |
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| 221 | //////////////////////i///////////////////////////////////// |
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| 222 | |
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| 223 | #define BOOT_SOFT_NAME "../../softs/tsar_boot/preloader.elf" |
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| 224 | |
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| 225 | //////////////////////////////////////////////////////////// |
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| 226 | // DEBUG Parameters default values |
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| 227 | //////////////////////i///////////////////////////////////// |
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| 228 | |
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[748] | 229 | #define MAX_FROZEN_CYCLES 200000 |
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[747] | 230 | |
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| 231 | ///////////////////////////////////////////////////////// |
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| 232 | // Physical segments definition |
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| 233 | ///////////////////////////////////////////////////////// |
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| 234 | |
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| 235 | // All physical segments base addresses and sizes are defined |
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| 236 | // in the hard_config.h file. For replicated segments, the |
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| 237 | // base address is incremented by a cluster offset: |
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[855] | 238 | // offset = cluster(x, y) << (address_width-X_WIDTH-Y_WIDTH); |
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[747] | 239 | |
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| 240 | //////////////////////////////////////////////////////////////////////// |
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| 241 | // SRCID definition |
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| 242 | //////////////////////////////////////////////////////////////////////// |
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| 243 | // All initiators are in the same indexing space (14 bits). |
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| 244 | // The SRCID is structured in two fields: |
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[875] | 245 | // - The 8 MSB bits define the cluster index (left aligned) |
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| 246 | // - The 6 LSB bits define the local index. |
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[747] | 247 | // Two different initiators cannot have the same SRCID, but a given |
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| 248 | // initiator can have two alias SRCIDs: |
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| 249 | // - Internal initiators (procs, mdma) are replicated in all clusters, |
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| 250 | // and each initiator has one single SRCID. |
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| 251 | // - External initiators (bdev, cdma) are not replicated, but can be |
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| 252 | // accessed in 2 clusters : cluster_iob0 and cluster_iob1. |
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| 253 | // They have the same local index, but two different cluster indexes. |
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| 254 | // |
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| 255 | // As cluster_iob0 and cluster_iob1 contain both internal initiators |
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| 256 | // and external initiators, they must have different local indexes. |
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| 257 | // Consequence: For a local interconnect, the INI_ID port index |
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| 258 | // is NOT equal to the SRCID local index, and the local interconnect |
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| 259 | // must make a translation: SRCID => INI_ID |
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| 260 | //////////////////////////////////////////////////////////////////////// |
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| 261 | |
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| 262 | #define PROC_LOCAL_SRCID 0x0 // from 0 to 7 |
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| 263 | #define MDMA_LOCAL_SRCID 0x8 |
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| 264 | #define IOBX_LOCAL_SRCID 0x9 |
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| 265 | #define MEMC_LOCAL_SRCID 0xA |
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| 266 | #define CDMA_LOCAL_SRCID 0xB |
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| 267 | #define BDEV_LOCAL_SRCID 0xC |
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| 268 | #define IOPI_LOCAL_SRCID 0xD |
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| 269 | |
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| 270 | /////////////////////////////////////////////////////////////////////// |
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| 271 | // TGT_ID and INI_ID port indexing for INT local interconnect |
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| 272 | /////////////////////////////////////////////////////////////////////// |
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| 273 | |
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| 274 | #define INT_MEMC_TGT_ID 0 |
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| 275 | #define INT_XICU_TGT_ID 1 |
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| 276 | #define INT_MDMA_TGT_ID 2 |
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[748] | 277 | #define INT_BROM_TGT_ID 3 |
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| 278 | #define INT_IOBX_TGT_ID 4 |
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[747] | 279 | |
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| 280 | #define INT_PROC_INI_ID 0 // from 0 to (NB_PROCS_MAX-1) |
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| 281 | #define INT_MDMA_INI_ID (NB_PROCS_MAX) |
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| 282 | #define INT_IOBX_INI_ID (NB_PROCS_MAX+1) |
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| 283 | |
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| 284 | /////////////////////////////////////////////////////////////////////// |
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| 285 | // TGT_ID and INI_ID port indexing for RAM local interconnect |
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| 286 | /////////////////////////////////////////////////////////////////////// |
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| 287 | |
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| 288 | #define RAM_XRAM_TGT_ID 0 |
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| 289 | |
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| 290 | #define RAM_MEMC_INI_ID 0 |
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| 291 | #define RAM_IOBX_INI_ID 1 |
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| 292 | |
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| 293 | /////////////////////////////////////////////////////////////////////// |
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| 294 | // TGT_ID and INI_ID port indexing for I0X local interconnect |
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| 295 | /////////////////////////////////////////////////////////////////////// |
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| 296 | |
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| 297 | #define IOX_FBUF_TGT_ID 0 |
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| 298 | #define IOX_BDEV_TGT_ID 1 |
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| 299 | #define IOX_MNIC_TGT_ID 2 |
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| 300 | #define IOX_CDMA_TGT_ID 3 |
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[748] | 301 | #define IOX_MTTY_TGT_ID 4 |
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| 302 | #define IOX_IOPI_TGT_ID 5 |
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[769] | 303 | #define IOX_SIMH_TGT_ID 6 |
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| 304 | #define IOX_IOB0_TGT_ID 7 |
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| 305 | #define IOX_IOB1_TGT_ID 8 |
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[747] | 306 | |
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| 307 | #define IOX_BDEV_INI_ID 0 |
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| 308 | #define IOX_CDMA_INI_ID 1 |
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| 309 | #define IOX_IOPI_INI_ID 2 |
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| 310 | #define IOX_IOB0_INI_ID 3 |
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| 311 | #define IOX_IOB1_INI_ID 4 |
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| 312 | |
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| 313 | //////////////////////////////////////////////////////////////////////// |
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| 314 | int _main(int argc, char *argv[]) |
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| 315 | //////////////////////////////////////////////////////////////////////// |
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| 316 | { |
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| 317 | using namespace sc_core; |
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| 318 | using namespace soclib::caba; |
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| 319 | using namespace soclib::common; |
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| 320 | |
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| 321 | |
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[859] | 322 | char soft_name[256] = BOOT_SOFT_NAME; // pathname: binary code |
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| 323 | size_t ncycles = UINT_MAX; // simulated cycles |
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| 324 | char disk_name[256] = BDEV_IMAGE_NAME; // pathname: disk image |
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| 325 | char nic_rx_name[256] = NIC_RX_NAME; // pathname: rx packets file |
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| 326 | char nic_tx_name[256] = NIC_TX_NAME; // pathname: tx packets file |
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| 327 | ssize_t threads_nr = 1; // simulator's threads number |
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| 328 | size_t faulty_router_id = 0xFFFFFFFF; // faulty router coordinates |
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| 329 | size_t faulty_mask = 0x1F; // interface mask for the faulty router |
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| 330 | bool debug_ok = false; // trace activated |
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| 331 | size_t debug_period = 1; // trace period |
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| 332 | size_t debug_memc_id = 0xFFFFFFFF; // index of traced memc |
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| 333 | size_t debug_proc_id = 0xFFFFFFFF; // index of traced proc |
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| 334 | size_t debug_xram_id = 0xFFFFFFFF; // index of traced xram |
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| 335 | bool debug_iob = false; // trace iob0 & iob1 when true |
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| 336 | uint32_t debug_from = 0; // trace start cycle |
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| 337 | uint32_t frozen_cycles = MAX_FROZEN_CYCLES; // monitoring frozen processor |
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[747] | 338 | |
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| 339 | assert( (X_WIDTH == 4) and (Y_WIDTH == 4) and |
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| 340 | "ERROR: we must have X_WIDTH == Y_WIDTH == 4"); |
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| 341 | |
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| 342 | ////////////// command line arguments ////////////////////// |
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| 343 | if (argc > 1) |
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| 344 | { |
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| 345 | for (int n = 1; n < argc; n = n + 2) |
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| 346 | { |
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[855] | 347 | if ((strcmp(argv[n], "-NCYCLES") == 0) && (n+1<argc)) |
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[747] | 348 | { |
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[748] | 349 | ncycles = strtol(argv[n+1], NULL, 0); |
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[747] | 350 | } |
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[855] | 351 | else if ((strcmp(argv[n], "-SOFT") == 0) && (n+1<argc) ) |
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[747] | 352 | { |
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| 353 | strcpy(soft_name, argv[n+1]); |
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| 354 | } |
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[855] | 355 | else if ((strcmp(argv[n], "-DEBUG") == 0) && (n+1<argc) ) |
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[747] | 356 | { |
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| 357 | debug_ok = true; |
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[748] | 358 | debug_from = strtol(argv[n+1], NULL, 0); |
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[747] | 359 | } |
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[855] | 360 | else if ((strcmp(argv[n], "-DISK") == 0) && (n+1<argc) ) |
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[747] | 361 | { |
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| 362 | strcpy(disk_name, argv[n+1]); |
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| 363 | } |
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[855] | 364 | else if ((strcmp(argv[n], "-MEMCID") == 0) && (n+1<argc) ) |
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[747] | 365 | { |
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[748] | 366 | debug_memc_id = strtol(argv[n+1], NULL, 0); |
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[855] | 367 | size_t x = debug_memc_id >> Y_WIDTH; |
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| 368 | size_t y = debug_memc_id & ((1 << Y_WIDTH) - 1); |
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[806] | 369 | if( (x>=X_SIZE) || (y>=Y_SIZE) ) |
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[747] | 370 | { |
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[806] | 371 | std::cout << "MEMCID parameter does'nt fit X_SIZE/Y_SIZE" << std::endl; |
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[747] | 372 | exit(0); |
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| 373 | } |
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| 374 | } |
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[855] | 375 | else if ((strcmp(argv[n], "-XRAMID") == 0) && (n+1<argc) ) |
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[747] | 376 | { |
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[748] | 377 | debug_xram_id = strtol(argv[n+1], NULL, 0); |
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[855] | 378 | size_t x = debug_xram_id >> Y_WIDTH; |
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| 379 | size_t y = debug_xram_id & ((1 << Y_WIDTH) - 1); |
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[806] | 380 | if( (x>=X_SIZE) || (y>=Y_SIZE) ) |
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[747] | 381 | { |
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[806] | 382 | std::cout << "XRAMID parameter does'nt fit X_SIZE/Y_SIZE" << std::endl; |
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[747] | 383 | exit(0); |
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| 384 | } |
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| 385 | } |
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[855] | 386 | else if ((strcmp(argv[n], "-IOB") == 0) && (n+1<argc) ) |
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[747] | 387 | { |
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[748] | 388 | debug_iob = strtol(argv[n+1], NULL, 0); |
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[747] | 389 | } |
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[855] | 390 | else if ((strcmp(argv[n], "-PROCID") == 0) && (n+1<argc) ) |
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[747] | 391 | { |
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[748] | 392 | debug_proc_id = strtol(argv[n+1], NULL, 0); |
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[855] | 393 | size_t cluster_xy = debug_proc_id >> P_WIDTH; |
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| 394 | size_t x = cluster_xy >> Y_WIDTH; |
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| 395 | size_t y = cluster_xy & ((1 << Y_WIDTH) - 1); |
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[806] | 396 | if( (x>=X_SIZE) || (y>=Y_SIZE) ) |
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[747] | 397 | { |
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[806] | 398 | std::cout << "PROCID parameter does'nt fit X_SIZE/Y_SIZE" << std::endl; |
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[747] | 399 | exit(0); |
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| 400 | } |
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| 401 | } |
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| 402 | else if ((strcmp(argv[n], "-THREADS") == 0) && ((n+1) < argc)) |
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| 403 | { |
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[748] | 404 | threads_nr = strtol(argv[n+1], NULL, 0); |
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[747] | 405 | threads_nr = (threads_nr < 1) ? 1 : threads_nr; |
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| 406 | } |
---|
| 407 | else if ((strcmp(argv[n], "-FROZEN") == 0) && (n+1 < argc)) |
---|
| 408 | { |
---|
[748] | 409 | frozen_cycles = strtol(argv[n+1], NULL, 0); |
---|
[747] | 410 | } |
---|
| 411 | else if ((strcmp(argv[n], "-PERIOD") == 0) && (n+1 < argc)) |
---|
| 412 | { |
---|
[748] | 413 | debug_period = strtol(argv[n+1], NULL, 0); |
---|
[747] | 414 | } |
---|
[855] | 415 | else if ((strcmp(argv[n], "-FAULTY_ROUTER") == 0) && (n+1 < argc) ) |
---|
| 416 | { |
---|
| 417 | faulty_router_id = strtol(argv[n+1], NULL, 0); |
---|
| 418 | size_t x = faulty_router_id >> Y_WIDTH; |
---|
| 419 | size_t y = faulty_router_id & ((1 << Y_WIDTH) - 1); |
---|
| 420 | if( (x>=X_SIZE) || (y>=Y_SIZE) ) |
---|
| 421 | { |
---|
| 422 | std::cout << "FAULTY_ROUTER parameter doesn't fit X_SIZE/Y_SIZE" << std::endl; |
---|
| 423 | exit(0); |
---|
| 424 | } |
---|
| 425 | } |
---|
[859] | 426 | else if ((strcmp(argv[n], "-FAULTY_MASK") == 0) && (n+1 < argc) ) |
---|
| 427 | { |
---|
| 428 | faulty_mask = strtol(argv[n+1], NULL, 0); |
---|
| 429 | if( faulty_mask > 0x1F ) |
---|
| 430 | { |
---|
| 431 | std::cout << "FAULTY_MASK parameter max value is 0x1F" << std::endl; |
---|
| 432 | exit(0); |
---|
| 433 | } |
---|
| 434 | } |
---|
[747] | 435 | else |
---|
| 436 | { |
---|
[855] | 437 | std::cout << " Arguments are (key, value) couples." << std::endl; |
---|
[747] | 438 | std::cout << " The order is not important." << std::endl; |
---|
| 439 | std::cout << " Accepted arguments are :" << std::endl << std::endl; |
---|
| 440 | std::cout << " -SOFT pathname_for_embedded_soft" << std::endl; |
---|
| 441 | std::cout << " -DISK pathname_for_disk_image" << std::endl; |
---|
| 442 | std::cout << " -NCYCLES number_of_simulated_cycles" << std::endl; |
---|
| 443 | std::cout << " -DEBUG debug_start_cycle" << std::endl; |
---|
| 444 | std::cout << " -THREADS simulator's threads number" << std::endl; |
---|
| 445 | std::cout << " -FROZEN max_number_of_lines" << std::endl; |
---|
| 446 | std::cout << " -PERIOD number_of_cycles between trace" << std::endl; |
---|
| 447 | std::cout << " -MEMCID index_memc_to_be_traced" << std::endl; |
---|
| 448 | std::cout << " -XRAMID index_xram_to_be_traced" << std::endl; |
---|
| 449 | std::cout << " -PROCID index_proc_to_be_traced" << std::endl; |
---|
| 450 | std::cout << " -IOB non_zero_value" << std::endl; |
---|
| 451 | exit(0); |
---|
| 452 | } |
---|
| 453 | } |
---|
| 454 | } |
---|
| 455 | |
---|
[748] | 456 | // Activate Distributed Boot (set by environment variable) |
---|
| 457 | // When this is activated, every processor boots with its instruction and data |
---|
| 458 | // physical address extension register initialized to its cluster index |
---|
| 459 | // (X_LOCAL, Y_LOCAL). To support this feature, a distributed ROM is |
---|
| 460 | // implemented in each cluster. |
---|
| 461 | |
---|
| 462 | const bool distributed_boot = (getenv("DISTRIBUTED_BOOT") != NULL); |
---|
| 463 | |
---|
[747] | 464 | // checking hardware parameters |
---|
[806] | 465 | assert( (X_SIZE <= (1 << X_WIDTH)) and |
---|
| 466 | "The X_SIZE parameter cannot be larger than 16" ); |
---|
[747] | 467 | |
---|
[806] | 468 | assert( (Y_SIZE <= (1 << Y_WIDTH)) and |
---|
| 469 | "The Y_SIZE parameter cannot be larger than 16" ); |
---|
[747] | 470 | |
---|
[875] | 471 | assert( (NB_PROCS_MAX <= (1 << P_WIDTH)) and |
---|
| 472 | "NB_PROCS_MAX parameter cannot be larger than 2^P_WIDTH" ); |
---|
[747] | 473 | |
---|
| 474 | assert( (NB_DMA_CHANNELS <= 4) and |
---|
| 475 | "The NB_DMA_CHANNELS parameter cannot be larger than 4" ); |
---|
| 476 | |
---|
[875] | 477 | assert( (NB_TTY_CHANNELS >= 1) and (NB_TTY_CHANNELS <= 16) and |
---|
| 478 | "The NB_TTY_CHANNELS parameter cannot be larger than 16" ); |
---|
[747] | 479 | |
---|
| 480 | assert( (NB_NIC_CHANNELS == 2) and |
---|
| 481 | "The NB_NIC_CHANNELS parameter must be 2" ); |
---|
| 482 | |
---|
| 483 | std::cout << std::endl << std::dec |
---|
[806] | 484 | << " - X_SIZE = " << X_SIZE << std::endl |
---|
| 485 | << " - Y_SIZE = " << Y_SIZE << std::endl |
---|
[747] | 486 | << " - NB_PROCS_MAX = " << NB_PROCS_MAX << std::endl |
---|
| 487 | << " - NB_TTY_CHANNELS = " << NB_TTY_CHANNELS << std::endl |
---|
| 488 | << " - NB_DMA_CHANNELS = " << NB_DMA_CHANNELS << std::endl |
---|
| 489 | << " - NB_NIC_CHANNELS = " << NB_NIC_CHANNELS << std::endl |
---|
| 490 | << " - MEMC_WAYS = " << MEMC_WAYS << std::endl |
---|
| 491 | << " - MEMC_SETS = " << MEMC_SETS << std::endl |
---|
| 492 | << " - RAM_LATENCY = " << XRAM_LATENCY << std::endl |
---|
| 493 | << " - MAX_FROZEN = " << frozen_cycles << std::endl |
---|
[748] | 494 | << " - DIST_BOOT = " << distributed_boot << std::endl |
---|
[747] | 495 | << " - DEBUG_PROCID = " << debug_proc_id << std::endl |
---|
| 496 | << " - DEBUG_MEMCID = " << debug_memc_id << std::endl |
---|
| 497 | << " - DEBUG_XRAMID = " << debug_xram_id << std::endl; |
---|
| 498 | |
---|
| 499 | std::cout << std::endl; |
---|
| 500 | |
---|
| 501 | #if USE_OPENMP |
---|
| 502 | omp_set_dynamic(false); |
---|
| 503 | omp_set_num_threads(threads_nr); |
---|
| 504 | std::cerr << "Built with openmp version " << _OPENMP << std::endl; |
---|
| 505 | #endif |
---|
| 506 | |
---|
| 507 | // Define VciParams objects |
---|
| 508 | typedef soclib::caba::VciParams<vci_cell_width_int, |
---|
| 509 | vci_plen_width, |
---|
| 510 | vci_address_width, |
---|
| 511 | vci_rerror_width, |
---|
| 512 | vci_clen_width, |
---|
| 513 | vci_rflag_width, |
---|
| 514 | vci_srcid_width, |
---|
| 515 | vci_pktid_width, |
---|
| 516 | vci_trdid_width, |
---|
| 517 | vci_wrplen_width> vci_param_int; |
---|
| 518 | |
---|
| 519 | typedef soclib::caba::VciParams<vci_cell_width_ext, |
---|
| 520 | vci_plen_width, |
---|
| 521 | vci_address_width, |
---|
| 522 | vci_rerror_width, |
---|
| 523 | vci_clen_width, |
---|
| 524 | vci_rflag_width, |
---|
| 525 | vci_srcid_width, |
---|
| 526 | vci_pktid_width, |
---|
| 527 | vci_trdid_width, |
---|
| 528 | vci_wrplen_width> vci_param_ext; |
---|
| 529 | |
---|
[859] | 530 | const size_t cluster_iob0 = cluster(0, 0); // cluster containing IOB0 |
---|
| 531 | const size_t cluster_iob1 = cluster(X_SIZE-1, Y_SIZE-1); // cluster containing IOB1 |
---|
| 532 | |
---|
[747] | 533 | ///////////////////////////////////////////////////////////////////// |
---|
| 534 | // INT network mapping table |
---|
| 535 | // - two levels address decoding for commands |
---|
| 536 | // - two levels srcid decoding for responses |
---|
| 537 | // - NB_PROCS_MAX + 2 (MDMA, IOBX) local initiators per cluster |
---|
| 538 | // - 4 local targets (MEMC, XICU, MDMA, IOBX) per cluster |
---|
| 539 | ///////////////////////////////////////////////////////////////////// |
---|
| 540 | MappingTable maptab_int( vci_address_width, |
---|
[806] | 541 | IntTab(X_WIDTH + Y_WIDTH, 16 - X_WIDTH - Y_WIDTH), |
---|
| 542 | IntTab(X_WIDTH + Y_WIDTH, vci_srcid_width - X_WIDTH - Y_WIDTH), |
---|
[747] | 543 | 0x00FF000000); |
---|
| 544 | |
---|
[806] | 545 | for (size_t x = 0; x < X_SIZE; x++) |
---|
[747] | 546 | { |
---|
[806] | 547 | for (size_t y = 0; y < Y_SIZE; y++) |
---|
[747] | 548 | { |
---|
[855] | 549 | uint64_t offset = ((uint64_t)cluster(x, y)) |
---|
[806] | 550 | << (vci_address_width-X_WIDTH-Y_WIDTH); |
---|
[747] | 551 | bool config = true; |
---|
| 552 | bool cacheable = true; |
---|
| 553 | |
---|
| 554 | // the four following segments are defined in all clusters |
---|
| 555 | |
---|
| 556 | std::ostringstream smemc_conf; |
---|
| 557 | smemc_conf << "int_seg_memc_conf_" << x << "_" << y; |
---|
| 558 | maptab_int.add(Segment(smemc_conf.str(), SEG_MMC_BASE+offset, SEG_MMC_SIZE, |
---|
[855] | 559 | IntTab(cluster(x, y), INT_MEMC_TGT_ID), not cacheable, config )); |
---|
[747] | 560 | |
---|
| 561 | std::ostringstream smemc_xram; |
---|
| 562 | smemc_xram << "int_seg_memc_xram_" << x << "_" << y; |
---|
| 563 | maptab_int.add(Segment(smemc_xram.str(), SEG_RAM_BASE+offset, SEG_RAM_SIZE, |
---|
[855] | 564 | IntTab(cluster(x, y), INT_MEMC_TGT_ID), cacheable)); |
---|
[747] | 565 | |
---|
| 566 | std::ostringstream sxicu; |
---|
| 567 | sxicu << "int_seg_xicu_" << x << "_" << y; |
---|
| 568 | maptab_int.add(Segment(sxicu.str(), SEG_XCU_BASE+offset, SEG_XCU_SIZE, |
---|
[855] | 569 | IntTab(cluster(x, y), INT_XICU_TGT_ID), not cacheable)); |
---|
[747] | 570 | |
---|
| 571 | std::ostringstream smdma; |
---|
| 572 | smdma << "int_seg_mdma_" << x << "_" << y; |
---|
| 573 | maptab_int.add(Segment(smdma.str(), SEG_DMA_BASE+offset, SEG_DMA_SIZE, |
---|
[855] | 574 | IntTab(cluster(x, y), INT_MDMA_TGT_ID), not cacheable)); |
---|
[747] | 575 | |
---|
[748] | 576 | std::ostringstream sbrom; |
---|
| 577 | sbrom << "int_seg_brom_" << x << "_" << y; |
---|
| 578 | maptab_int.add(Segment(sbrom.str(), SEG_ROM_BASE+offset, SEG_ROM_SIZE, |
---|
[855] | 579 | IntTab(cluster(x, y), INT_BROM_TGT_ID), cacheable)); |
---|
[748] | 580 | |
---|
[747] | 581 | // the following segments are only defined in cluster_iob0 or in cluster_iob1 |
---|
| 582 | |
---|
[855] | 583 | if ( (cluster(x, y) == cluster_iob0) or (cluster(x, y) == cluster_iob1) ) |
---|
[747] | 584 | { |
---|
| 585 | std::ostringstream siobx; |
---|
| 586 | siobx << "int_seg_iobx_" << x << "_" << y; |
---|
| 587 | maptab_int.add(Segment(siobx.str(), SEG_IOB_BASE+offset, SEG_IOB_SIZE, |
---|
[855] | 588 | IntTab(cluster(x, y), INT_IOBX_TGT_ID), not cacheable, config )); |
---|
[747] | 589 | |
---|
| 590 | std::ostringstream stty; |
---|
| 591 | stty << "int_seg_mtty_" << x << "_" << y; |
---|
| 592 | maptab_int.add(Segment(stty.str(), SEG_TTY_BASE+offset, SEG_TTY_SIZE, |
---|
[855] | 593 | IntTab(cluster(x, y), INT_IOBX_TGT_ID), not cacheable)); |
---|
[747] | 594 | |
---|
| 595 | std::ostringstream sfbf; |
---|
| 596 | sfbf << "int_seg_fbuf_" << x << "_" << y; |
---|
| 597 | maptab_int.add(Segment(sfbf.str(), SEG_FBF_BASE+offset, SEG_FBF_SIZE, |
---|
[855] | 598 | IntTab(cluster(x, y), INT_IOBX_TGT_ID), not cacheable)); |
---|
[747] | 599 | |
---|
| 600 | std::ostringstream sbdv; |
---|
| 601 | sbdv << "int_seg_bdev_" << x << "_" << y; |
---|
| 602 | maptab_int.add(Segment(sbdv.str(), SEG_IOC_BASE+offset, SEG_IOC_SIZE, |
---|
[855] | 603 | IntTab(cluster(x, y), INT_IOBX_TGT_ID), not cacheable)); |
---|
[747] | 604 | |
---|
| 605 | std::ostringstream snic; |
---|
| 606 | snic << "int_seg_mnic_" << x << "_" << y; |
---|
| 607 | maptab_int.add(Segment(snic.str(), SEG_NIC_BASE+offset, SEG_NIC_SIZE, |
---|
[855] | 608 | IntTab(cluster(x, y), INT_IOBX_TGT_ID), not cacheable)); |
---|
[747] | 609 | |
---|
| 610 | std::ostringstream sdma; |
---|
| 611 | sdma << "int_seg_cdma_" << x << "_" << y; |
---|
| 612 | maptab_int.add(Segment(sdma.str(), SEG_CMA_BASE+offset, SEG_CMA_SIZE, |
---|
[855] | 613 | IntTab(cluster(x, y), INT_IOBX_TGT_ID), not cacheable)); |
---|
[747] | 614 | |
---|
| 615 | std::ostringstream spic; |
---|
| 616 | spic << "int_seg_iopi_" << x << "_" << y; |
---|
| 617 | maptab_int.add(Segment(spic.str(), SEG_PIC_BASE+offset, SEG_PIC_SIZE, |
---|
[855] | 618 | IntTab(cluster(x, y), INT_IOBX_TGT_ID), not cacheable)); |
---|
[769] | 619 | |
---|
| 620 | std::ostringstream ssim; |
---|
| 621 | ssim << "int_seg_simh_" << x << "_" << y; |
---|
| 622 | maptab_int.add(Segment(ssim.str(), SEG_SIM_BASE+offset, SEG_SIM_SIZE, |
---|
[855] | 623 | IntTab(cluster(x, y), INT_IOBX_TGT_ID), not cacheable)); |
---|
[747] | 624 | } |
---|
| 625 | |
---|
| 626 | // This define the mapping between the SRCIDs |
---|
| 627 | // and the port index on the local interconnect. |
---|
| 628 | |
---|
[855] | 629 | maptab_int.srcid_map( IntTab( cluster(x, y), MDMA_LOCAL_SRCID ), |
---|
| 630 | IntTab( cluster(x, y), INT_MDMA_INI_ID ) ); |
---|
[747] | 631 | |
---|
[855] | 632 | maptab_int.srcid_map( IntTab( cluster(x, y), IOBX_LOCAL_SRCID ), |
---|
| 633 | IntTab( cluster(x, y), INT_IOBX_INI_ID ) ); |
---|
[747] | 634 | |
---|
[855] | 635 | maptab_int.srcid_map( IntTab( cluster(x, y), IOPI_LOCAL_SRCID ), |
---|
| 636 | IntTab( cluster(x, y), INT_IOBX_INI_ID ) ); |
---|
[747] | 637 | |
---|
| 638 | for ( size_t p = 0 ; p < NB_PROCS_MAX ; p++ ) |
---|
[855] | 639 | maptab_int.srcid_map( IntTab( cluster(x, y), PROC_LOCAL_SRCID+p ), |
---|
| 640 | IntTab( cluster(x, y), INT_PROC_INI_ID+p ) ); |
---|
[747] | 641 | } |
---|
| 642 | } |
---|
| 643 | std::cout << "INT network " << maptab_int << std::endl; |
---|
| 644 | |
---|
| 645 | ///////////////////////////////////////////////////////////////////////// |
---|
| 646 | // RAM network mapping table |
---|
| 647 | // - two levels address decoding for commands |
---|
| 648 | // - two levels srcid decoding for responses |
---|
| 649 | // - 2 local initiators (MEMC, IOBX) per cluster |
---|
| 650 | // (IOBX component only in cluster_iob0 and cluster_iob1) |
---|
| 651 | // - 1 local target (XRAM) per cluster |
---|
| 652 | //////////////////////////////////////////////////////////////////////// |
---|
| 653 | MappingTable maptab_ram( vci_address_width, |
---|
[806] | 654 | IntTab(X_WIDTH+Y_WIDTH, 0), |
---|
| 655 | IntTab(X_WIDTH+Y_WIDTH, vci_srcid_width - X_WIDTH - Y_WIDTH), |
---|
[747] | 656 | 0x00FF000000); |
---|
| 657 | |
---|
[806] | 658 | for (size_t x = 0; x < X_SIZE; x++) |
---|
[747] | 659 | { |
---|
[806] | 660 | for (size_t y = 0; y < Y_SIZE ; y++) |
---|
[747] | 661 | { |
---|
[855] | 662 | uint64_t offset = ((uint64_t)cluster(x, y)) |
---|
[806] | 663 | << (vci_address_width-X_WIDTH-Y_WIDTH); |
---|
[747] | 664 | |
---|
| 665 | std::ostringstream sxram; |
---|
| 666 | sxram << "ext_seg_xram_" << x << "_" << y; |
---|
| 667 | maptab_ram.add(Segment(sxram.str(), SEG_RAM_BASE+offset, |
---|
[855] | 668 | SEG_RAM_SIZE, IntTab(cluster(x, y), RAM_XRAM_TGT_ID), false)); |
---|
[747] | 669 | } |
---|
| 670 | } |
---|
| 671 | |
---|
| 672 | // This define the mapping between the initiators SRCID |
---|
| 673 | // and the port index on the RAM local interconnect. |
---|
| 674 | // External initiator have two alias SRCID (iob0 / iob1) |
---|
| 675 | |
---|
| 676 | maptab_ram.srcid_map( IntTab( cluster_iob0, CDMA_LOCAL_SRCID ), |
---|
| 677 | IntTab( cluster_iob0, RAM_IOBX_INI_ID ) ); |
---|
| 678 | |
---|
| 679 | maptab_ram.srcid_map( IntTab( cluster_iob1, CDMA_LOCAL_SRCID ), |
---|
| 680 | IntTab( cluster_iob1, RAM_IOBX_INI_ID ) ); |
---|
| 681 | |
---|
| 682 | maptab_ram.srcid_map( IntTab( cluster_iob0, BDEV_LOCAL_SRCID ), |
---|
| 683 | IntTab( cluster_iob0, RAM_IOBX_INI_ID ) ); |
---|
| 684 | |
---|
| 685 | maptab_ram.srcid_map( IntTab( cluster_iob1, BDEV_LOCAL_SRCID ), |
---|
| 686 | IntTab( cluster_iob1, RAM_IOBX_INI_ID ) ); |
---|
| 687 | |
---|
| 688 | maptab_ram.srcid_map( IntTab( cluster_iob0, IOPI_LOCAL_SRCID ), |
---|
| 689 | IntTab( cluster_iob0, RAM_IOBX_INI_ID ) ); |
---|
| 690 | |
---|
| 691 | maptab_ram.srcid_map( IntTab( cluster_iob1, IOPI_LOCAL_SRCID ), |
---|
| 692 | IntTab( cluster_iob1, RAM_IOBX_INI_ID ) ); |
---|
| 693 | |
---|
| 694 | maptab_ram.srcid_map( IntTab( cluster_iob0, MEMC_LOCAL_SRCID ), |
---|
| 695 | IntTab( cluster_iob0, RAM_MEMC_INI_ID ) ); |
---|
| 696 | |
---|
| 697 | maptab_ram.srcid_map( IntTab( cluster_iob1, MEMC_LOCAL_SRCID ), |
---|
| 698 | IntTab( cluster_iob1, RAM_MEMC_INI_ID ) ); |
---|
| 699 | |
---|
| 700 | std::cout << "RAM network " << maptab_ram << std::endl; |
---|
| 701 | |
---|
| 702 | /////////////////////////////////////////////////////////////////////// |
---|
| 703 | // IOX network mapping table |
---|
| 704 | // - two levels address decoding for commands (9, 7) bits |
---|
| 705 | // - two levels srcid decoding for responses |
---|
| 706 | // - 5 initiators (IOB0, IOB1, BDEV, CDMA, IOPI) |
---|
| 707 | // - 9 targets (IOB0, IOB1, BDEV, CDMA, MTTY, FBUF, BROM, MNIC, IOPI) |
---|
| 708 | // |
---|
| 709 | // Address bit 32 is used to determine if a command must be routed to |
---|
| 710 | // IOB0 or IOB1. |
---|
| 711 | /////////////////////////////////////////////////////////////////////// |
---|
| 712 | MappingTable maptab_iox( |
---|
| 713 | vci_address_width, |
---|
[806] | 714 | IntTab(X_WIDTH + Y_WIDTH - 1, 16 - X_WIDTH - Y_WIDTH + 1), |
---|
| 715 | IntTab(X_WIDTH + Y_WIDTH , vci_param_ext::S - X_WIDTH - Y_WIDTH), |
---|
[747] | 716 | 0x00FF000000); |
---|
| 717 | |
---|
| 718 | // External peripherals segments |
---|
| 719 | // When there is more than one cluster, external peripherals can be accessed |
---|
| 720 | // through two segments, depending on the used IOB (IOB0 or IOB1). |
---|
| 721 | |
---|
| 722 | const uint64_t iob0_base = ((uint64_t)cluster_iob0) |
---|
[806] | 723 | << (vci_address_width - X_WIDTH - Y_WIDTH); |
---|
[747] | 724 | |
---|
| 725 | maptab_iox.add(Segment("iox_seg_mtty_0", SEG_TTY_BASE + iob0_base, SEG_TTY_SIZE, |
---|
| 726 | IntTab(0, IOX_MTTY_TGT_ID), false)); |
---|
| 727 | maptab_iox.add(Segment("iox_seg_fbuf_0", SEG_FBF_BASE + iob0_base, SEG_FBF_SIZE, |
---|
| 728 | IntTab(0, IOX_FBUF_TGT_ID), false)); |
---|
| 729 | maptab_iox.add(Segment("iox_seg_bdev_0", SEG_IOC_BASE + iob0_base, SEG_IOC_SIZE, |
---|
| 730 | IntTab(0, IOX_BDEV_TGT_ID), false)); |
---|
| 731 | maptab_iox.add(Segment("iox_seg_mnic_0", SEG_NIC_BASE + iob0_base, SEG_NIC_SIZE, |
---|
| 732 | IntTab(0, IOX_MNIC_TGT_ID), false)); |
---|
| 733 | maptab_iox.add(Segment("iox_seg_cdma_0", SEG_CMA_BASE + iob0_base, SEG_CMA_SIZE, |
---|
| 734 | IntTab(0, IOX_CDMA_TGT_ID), false)); |
---|
| 735 | maptab_iox.add(Segment("iox_seg_iopi_0", SEG_PIC_BASE + iob0_base, SEG_PIC_SIZE, |
---|
| 736 | IntTab(0, IOX_IOPI_TGT_ID), false)); |
---|
[769] | 737 | maptab_iox.add(Segment("iox_seg_simh_0", SEG_SIM_BASE + iob0_base, SEG_SIM_SIZE, |
---|
| 738 | IntTab(0, IOX_SIMH_TGT_ID), false)); |
---|
[747] | 739 | |
---|
| 740 | if ( cluster_iob0 != cluster_iob1 ) |
---|
| 741 | { |
---|
| 742 | const uint64_t iob1_base = ((uint64_t)cluster_iob1) |
---|
[806] | 743 | << (vci_address_width - X_WIDTH - Y_WIDTH); |
---|
[747] | 744 | |
---|
| 745 | maptab_iox.add(Segment("iox_seg_mtty_1", SEG_TTY_BASE + iob1_base, SEG_TTY_SIZE, |
---|
| 746 | IntTab(0, IOX_MTTY_TGT_ID), false)); |
---|
| 747 | maptab_iox.add(Segment("iox_seg_fbuf_1", SEG_FBF_BASE + iob1_base, SEG_FBF_SIZE, |
---|
| 748 | IntTab(0, IOX_FBUF_TGT_ID), false)); |
---|
| 749 | maptab_iox.add(Segment("iox_seg_bdev_1", SEG_IOC_BASE + iob1_base, SEG_IOC_SIZE, |
---|
| 750 | IntTab(0, IOX_BDEV_TGT_ID), false)); |
---|
| 751 | maptab_iox.add(Segment("iox_seg_mnic_1", SEG_NIC_BASE + iob1_base, SEG_NIC_SIZE, |
---|
| 752 | IntTab(0, IOX_MNIC_TGT_ID), false)); |
---|
| 753 | maptab_iox.add(Segment("iox_seg_cdma_1", SEG_CMA_BASE + iob1_base, SEG_CMA_SIZE, |
---|
| 754 | IntTab(0, IOX_CDMA_TGT_ID), false)); |
---|
| 755 | maptab_iox.add(Segment("iox_seg_iopi_1", SEG_PIC_BASE + iob1_base, SEG_PIC_SIZE, |
---|
| 756 | IntTab(0, IOX_IOPI_TGT_ID), false)); |
---|
[769] | 757 | maptab_iox.add(Segment("iox_seg_simh_1", SEG_SIM_BASE + iob1_base, SEG_SIM_SIZE, |
---|
| 758 | IntTab(0, IOX_SIMH_TGT_ID), false)); |
---|
[747] | 759 | } |
---|
| 760 | |
---|
| 761 | // If there is more than one cluster, external peripherals |
---|
| 762 | // can access RAM through two segments (IOB0 / IOB1). |
---|
| 763 | // As IOMMU is not activated, addresses are 40 bits (physical addresses), |
---|
| 764 | // and the choice depends on address bit A[32]. |
---|
[806] | 765 | for (size_t x = 0; x < X_SIZE; x++) |
---|
[747] | 766 | { |
---|
[806] | 767 | for (size_t y = 0; y < Y_SIZE ; y++) |
---|
[747] | 768 | { |
---|
| 769 | const bool wti = true; |
---|
| 770 | const bool cacheable = true; |
---|
| 771 | |
---|
[855] | 772 | const uint64_t offset = ((uint64_t)cluster(x, y)) |
---|
[806] | 773 | << (vci_address_width-X_WIDTH-Y_WIDTH); |
---|
[747] | 774 | |
---|
| 775 | const uint64_t xicu_base = SEG_XCU_BASE + offset; |
---|
| 776 | |
---|
| 777 | if ( (y & 0x1) == 0 ) // use IOB0 |
---|
| 778 | { |
---|
| 779 | std::ostringstream sxcu0; |
---|
| 780 | sxcu0 << "iox_seg_xcu0_" << x << "_" << y; |
---|
| 781 | maptab_iox.add(Segment(sxcu0.str(), xicu_base, SEG_XCU_SIZE, |
---|
| 782 | IntTab(0, IOX_IOB0_TGT_ID), not cacheable, wti)); |
---|
| 783 | |
---|
| 784 | std::ostringstream siob0; |
---|
| 785 | siob0 << "iox_seg_ram0_" << x << "_" << y; |
---|
| 786 | maptab_iox.add(Segment(siob0.str(), offset, SEG_XCU_BASE, |
---|
| 787 | IntTab(0, IOX_IOB0_TGT_ID), not cacheable, not wti)); |
---|
| 788 | } |
---|
| 789 | else // USE IOB1 |
---|
| 790 | { |
---|
| 791 | std::ostringstream sxcu1; |
---|
| 792 | sxcu1 << "iox_seg_xcu1_" << x << "_" << y; |
---|
| 793 | maptab_iox.add(Segment(sxcu1.str(), xicu_base, SEG_XCU_SIZE, |
---|
| 794 | IntTab(0, IOX_IOB1_TGT_ID), not cacheable, wti)); |
---|
| 795 | |
---|
| 796 | std::ostringstream siob1; |
---|
| 797 | siob1 << "iox_seg_ram1_" << x << "_" << y; |
---|
| 798 | maptab_iox.add(Segment(siob1.str(), offset, SEG_XCU_BASE, |
---|
| 799 | IntTab(0, IOX_IOB1_TGT_ID), not cacheable, not wti)); |
---|
| 800 | } |
---|
| 801 | } |
---|
| 802 | } |
---|
| 803 | |
---|
| 804 | // This define the mapping between the external initiators (SRCID) |
---|
| 805 | // and the port index on the IOX local interconnect. |
---|
| 806 | |
---|
| 807 | maptab_iox.srcid_map( IntTab( 0, CDMA_LOCAL_SRCID ) , |
---|
| 808 | IntTab( 0, IOX_CDMA_INI_ID ) ); |
---|
| 809 | maptab_iox.srcid_map( IntTab( 0, BDEV_LOCAL_SRCID ) , |
---|
| 810 | IntTab( 0, IOX_BDEV_INI_ID ) ); |
---|
| 811 | maptab_iox.srcid_map( IntTab( 0, IOPI_LOCAL_SRCID ) , |
---|
| 812 | IntTab( 0, IOX_IOPI_INI_ID ) ); |
---|
| 813 | maptab_iox.srcid_map( IntTab( 0, IOX_IOB0_INI_ID ) , |
---|
| 814 | IntTab( 0, IOX_IOB0_INI_ID ) ); |
---|
| 815 | |
---|
| 816 | if ( cluster_iob0 != cluster_iob1 ) |
---|
| 817 | { |
---|
| 818 | maptab_iox.srcid_map( IntTab( 0, IOX_IOB1_INI_ID ) , |
---|
| 819 | IntTab( 0, IOX_IOB1_INI_ID ) ); |
---|
| 820 | } |
---|
| 821 | |
---|
| 822 | std::cout << "IOX network " << maptab_iox << std::endl; |
---|
| 823 | |
---|
| 824 | //////////////////// |
---|
| 825 | // Signals |
---|
| 826 | /////////////////// |
---|
| 827 | |
---|
| 828 | sc_clock signal_clk("clk"); |
---|
| 829 | sc_signal<bool> signal_resetn("resetn"); |
---|
| 830 | |
---|
| 831 | sc_signal<bool> signal_irq_false; |
---|
| 832 | sc_signal<bool> signal_irq_bdev; |
---|
[875] | 833 | sc_signal<bool> signal_irq_mtty_rx[NB_TTY_CHANNELS]; |
---|
[747] | 834 | sc_signal<bool> signal_irq_mnic_rx[NB_NIC_CHANNELS]; |
---|
| 835 | sc_signal<bool> signal_irq_mnic_tx[NB_NIC_CHANNELS]; |
---|
| 836 | sc_signal<bool> signal_irq_cdma[NB_CMA_CHANNELS]; |
---|
| 837 | |
---|
| 838 | // VCI signals for IOX network |
---|
| 839 | VciSignals<vci_param_ext> signal_vci_ini_iob0("signal_vci_ini_iob0"); |
---|
| 840 | VciSignals<vci_param_ext> signal_vci_ini_iob1("signal_vci_ini_iob1"); |
---|
| 841 | VciSignals<vci_param_ext> signal_vci_ini_bdev("signal_vci_ini_bdev"); |
---|
| 842 | VciSignals<vci_param_ext> signal_vci_ini_cdma("signal_vci_ini_cdma"); |
---|
| 843 | VciSignals<vci_param_ext> signal_vci_ini_iopi("signal_vci_ini_iopi"); |
---|
| 844 | |
---|
| 845 | VciSignals<vci_param_ext> signal_vci_tgt_iob0("signal_vci_tgt_iob0"); |
---|
| 846 | VciSignals<vci_param_ext> signal_vci_tgt_iob1("signal_vci_tgt_iob1"); |
---|
| 847 | VciSignals<vci_param_ext> signal_vci_tgt_mtty("signal_vci_tgt_mtty"); |
---|
| 848 | VciSignals<vci_param_ext> signal_vci_tgt_fbuf("signal_vci_tgt_fbuf"); |
---|
| 849 | VciSignals<vci_param_ext> signal_vci_tgt_mnic("signal_vci_tgt_mnic"); |
---|
| 850 | VciSignals<vci_param_ext> signal_vci_tgt_bdev("signal_vci_tgt_bdev"); |
---|
| 851 | VciSignals<vci_param_ext> signal_vci_tgt_cdma("signal_vci_tgt_cdma"); |
---|
| 852 | VciSignals<vci_param_ext> signal_vci_tgt_iopi("signal_vci_ini_iopi"); |
---|
[769] | 853 | VciSignals<vci_param_ext> signal_vci_tgt_simh("signal_vci_ini_simh"); |
---|
[747] | 854 | |
---|
| 855 | // Horizontal inter-clusters INT network DSPIN |
---|
| 856 | DspinSignals<dspin_int_cmd_width>*** signal_dspin_int_cmd_h_inc = |
---|
[806] | 857 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_cmd_h_inc", X_SIZE-1, Y_SIZE, 3); |
---|
[747] | 858 | DspinSignals<dspin_int_cmd_width>*** signal_dspin_int_cmd_h_dec = |
---|
[806] | 859 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_cmd_h_dec", X_SIZE-1, Y_SIZE, 3); |
---|
[747] | 860 | DspinSignals<dspin_int_rsp_width>*** signal_dspin_int_rsp_h_inc = |
---|
[806] | 861 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_int_rsp_h_inc", X_SIZE-1, Y_SIZE, 2); |
---|
[747] | 862 | DspinSignals<dspin_int_rsp_width>*** signal_dspin_int_rsp_h_dec = |
---|
[806] | 863 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_int_rsp_h_dec", X_SIZE-1, Y_SIZE, 2); |
---|
[747] | 864 | |
---|
| 865 | // Vertical inter-clusters INT network DSPIN |
---|
| 866 | DspinSignals<dspin_int_cmd_width>*** signal_dspin_int_cmd_v_inc = |
---|
[806] | 867 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_cmd_v_inc", X_SIZE, Y_SIZE-1, 3); |
---|
[747] | 868 | DspinSignals<dspin_int_cmd_width>*** signal_dspin_int_cmd_v_dec = |
---|
[806] | 869 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_cmd_v_dec", X_SIZE, Y_SIZE-1, 3); |
---|
[747] | 870 | DspinSignals<dspin_int_rsp_width>*** signal_dspin_int_rsp_v_inc = |
---|
[806] | 871 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_int_rsp_v_inc", X_SIZE, Y_SIZE-1, 2); |
---|
[747] | 872 | DspinSignals<dspin_int_rsp_width>*** signal_dspin_int_rsp_v_dec = |
---|
[806] | 873 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_int_rsp_v_dec", X_SIZE, Y_SIZE-1, 2); |
---|
[747] | 874 | |
---|
| 875 | // Mesh boundaries INT network DSPIN |
---|
[751] | 876 | DspinSignals<dspin_int_cmd_width>**** signal_dspin_false_int_cmd_in = |
---|
[806] | 877 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_false_int_cmd_in", X_SIZE, Y_SIZE, 4, 3); |
---|
[751] | 878 | DspinSignals<dspin_int_cmd_width>**** signal_dspin_false_int_cmd_out = |
---|
[806] | 879 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_false_int_cmd_out", X_SIZE, Y_SIZE, 4, 3); |
---|
[751] | 880 | DspinSignals<dspin_int_rsp_width>**** signal_dspin_false_int_rsp_in = |
---|
[806] | 881 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_false_int_rsp_in", X_SIZE, Y_SIZE, 4, 2); |
---|
[751] | 882 | DspinSignals<dspin_int_rsp_width>**** signal_dspin_false_int_rsp_out = |
---|
[806] | 883 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_false_int_rsp_out", X_SIZE, Y_SIZE, 4, 2); |
---|
[747] | 884 | |
---|
[751] | 885 | |
---|
[747] | 886 | // Horizontal inter-clusters RAM network DSPIN |
---|
| 887 | DspinSignals<dspin_ram_cmd_width>** signal_dspin_ram_cmd_h_inc = |
---|
[806] | 888 | alloc_elems<DspinSignals<dspin_ram_cmd_width> >("signal_dspin_ram_cmd_h_inc", X_SIZE-1, Y_SIZE); |
---|
[747] | 889 | DspinSignals<dspin_ram_cmd_width>** signal_dspin_ram_cmd_h_dec = |
---|
[806] | 890 | alloc_elems<DspinSignals<dspin_ram_cmd_width> >("signal_dspin_ram_cmd_h_dec", X_SIZE-1, Y_SIZE); |
---|
[747] | 891 | DspinSignals<dspin_ram_rsp_width>** signal_dspin_ram_rsp_h_inc = |
---|
[806] | 892 | alloc_elems<DspinSignals<dspin_ram_rsp_width> >("signal_dspin_ram_rsp_h_inc", X_SIZE-1, Y_SIZE); |
---|
[747] | 893 | DspinSignals<dspin_ram_rsp_width>** signal_dspin_ram_rsp_h_dec = |
---|
[806] | 894 | alloc_elems<DspinSignals<dspin_ram_rsp_width> >("signal_dspin_ram_rsp_h_dec", X_SIZE-1, Y_SIZE); |
---|
[747] | 895 | |
---|
| 896 | // Vertical inter-clusters RAM network DSPIN |
---|
| 897 | DspinSignals<dspin_ram_cmd_width>** signal_dspin_ram_cmd_v_inc = |
---|
[806] | 898 | alloc_elems<DspinSignals<dspin_ram_cmd_width> >("signal_dspin_ram_cmd_v_inc", X_SIZE, Y_SIZE-1); |
---|
[747] | 899 | DspinSignals<dspin_ram_cmd_width>** signal_dspin_ram_cmd_v_dec = |
---|
[806] | 900 | alloc_elems<DspinSignals<dspin_ram_cmd_width> >("signal_dspin_ram_cmd_v_dec", X_SIZE, Y_SIZE-1); |
---|
[747] | 901 | DspinSignals<dspin_ram_rsp_width>** signal_dspin_ram_rsp_v_inc = |
---|
[806] | 902 | alloc_elems<DspinSignals<dspin_ram_rsp_width> >("signal_dspin_ram_rsp_v_inc", X_SIZE, Y_SIZE-1); |
---|
[747] | 903 | DspinSignals<dspin_ram_rsp_width>** signal_dspin_ram_rsp_v_dec = |
---|
[806] | 904 | alloc_elems<DspinSignals<dspin_ram_rsp_width> >("signal_dspin_ram_rsp_v_dec", X_SIZE, Y_SIZE-1); |
---|
[747] | 905 | |
---|
| 906 | // Mesh boundaries RAM network DSPIN |
---|
[751] | 907 | DspinSignals<dspin_ram_cmd_width>*** signal_dspin_false_ram_cmd_in = |
---|
[806] | 908 | alloc_elems<DspinSignals<dspin_ram_cmd_width> >("signal_dspin_false_ram_cmd_in", X_SIZE, Y_SIZE, 4); |
---|
[751] | 909 | DspinSignals<dspin_ram_cmd_width>*** signal_dspin_false_ram_cmd_out = |
---|
[806] | 910 | alloc_elems<DspinSignals<dspin_ram_cmd_width> >("signal_dspin_false_ram_cmd_out", X_SIZE, Y_SIZE, 4); |
---|
[751] | 911 | DspinSignals<dspin_ram_rsp_width>*** signal_dspin_false_ram_rsp_in = |
---|
[806] | 912 | alloc_elems<DspinSignals<dspin_ram_rsp_width> >("signal_dspin_false_ram_rsp_in", X_SIZE, Y_SIZE, 4); |
---|
[751] | 913 | DspinSignals<dspin_ram_rsp_width>*** signal_dspin_false_ram_rsp_out = |
---|
[806] | 914 | alloc_elems<DspinSignals<dspin_ram_rsp_width> >("signal_dspin_false_ram_rsp_out", X_SIZE, Y_SIZE, 4); |
---|
[747] | 915 | |
---|
| 916 | //////////////////////////// |
---|
| 917 | // Loader |
---|
| 918 | //////////////////////////// |
---|
| 919 | |
---|
| 920 | #if USE_ALMOS |
---|
| 921 | soclib::common::Loader loader(almos_bootloader_pathname, |
---|
| 922 | almos_archinfo_pathname, |
---|
| 923 | almos_kernel_pathname); |
---|
| 924 | #else |
---|
| 925 | soclib::common::Loader loader(soft_name); |
---|
| 926 | #endif |
---|
| 927 | |
---|
[756] | 928 | // initialize memory with a value different than 0 (expose software errors |
---|
| 929 | // dues to uninitialized data) |
---|
| 930 | loader.memory_default(0xA0); |
---|
| 931 | |
---|
[747] | 932 | typedef soclib::common::GdbServer<soclib::common::Mips32ElIss> proc_iss; |
---|
| 933 | proc_iss::set_loader(loader); |
---|
| 934 | |
---|
| 935 | //////////////////////////////////////// |
---|
| 936 | // Instanciated Hardware Components |
---|
| 937 | //////////////////////////////////////// |
---|
| 938 | |
---|
| 939 | std::cout << std::endl << "External Bus and Peripherals" << std::endl << std::endl; |
---|
| 940 | |
---|
| 941 | const size_t nb_iox_initiators = (cluster_iob0 != cluster_iob1) ? 5 : 4; |
---|
[769] | 942 | const size_t nb_iox_targets = (cluster_iob0 != cluster_iob1) ? 9 : 8; |
---|
[747] | 943 | |
---|
| 944 | // IOX network |
---|
| 945 | VciIoxNetwork<vci_param_ext>* iox_network; |
---|
| 946 | iox_network = new VciIoxNetwork<vci_param_ext>( "iox_network", |
---|
| 947 | maptab_iox, |
---|
| 948 | nb_iox_targets, |
---|
| 949 | nb_iox_initiators ); |
---|
[748] | 950 | |
---|
[747] | 951 | // Network Controller |
---|
| 952 | VciMultiNic<vci_param_ext>* mnic; |
---|
| 953 | mnic = new VciMultiNic<vci_param_ext>( "mnic", |
---|
| 954 | IntTab(0, IOX_MNIC_TGT_ID), |
---|
| 955 | maptab_iox, |
---|
| 956 | NB_NIC_CHANNELS, |
---|
| 957 | 0, // mac_4 address |
---|
| 958 | 0, // mac_2 address |
---|
| 959 | nic_rx_name, |
---|
| 960 | nic_tx_name); |
---|
| 961 | |
---|
| 962 | // Frame Buffer |
---|
| 963 | VciFrameBuffer<vci_param_ext>* fbuf; |
---|
| 964 | fbuf = new VciFrameBuffer<vci_param_ext>( "fbuf", |
---|
| 965 | IntTab(0, IOX_FBUF_TGT_ID), |
---|
| 966 | maptab_iox, |
---|
| 967 | FBUF_X_SIZE, FBUF_Y_SIZE ); |
---|
| 968 | |
---|
| 969 | // Block Device |
---|
| 970 | // for AHCI |
---|
| 971 | // std::vector<std::string> filenames; |
---|
| 972 | // filenames.push_back(disk_name); // one single disk |
---|
| 973 | VciBlockDeviceTsar<vci_param_ext>* bdev; |
---|
| 974 | bdev = new VciBlockDeviceTsar<vci_param_ext>( "bdev", |
---|
| 975 | maptab_iox, |
---|
| 976 | IntTab(0, BDEV_LOCAL_SRCID), |
---|
| 977 | IntTab(0, IOX_BDEV_TGT_ID), |
---|
| 978 | disk_name, |
---|
| 979 | 512, // block size |
---|
| 980 | 64, // burst size (bytes) |
---|
| 981 | 0 ); // disk latency |
---|
| 982 | |
---|
| 983 | // Chained Buffer DMA controller |
---|
| 984 | VciChbufDma<vci_param_ext>* cdma; |
---|
| 985 | cdma = new VciChbufDma<vci_param_ext>( "cdma", |
---|
| 986 | maptab_iox, |
---|
| 987 | IntTab(0, CDMA_LOCAL_SRCID), |
---|
| 988 | IntTab(0, IOX_CDMA_TGT_ID), |
---|
| 989 | 64, // burst size (bytes) |
---|
| 990 | 2*NB_NIC_CHANNELS ); |
---|
| 991 | // Multi-TTY controller |
---|
| 992 | std::vector<std::string> vect_names; |
---|
| 993 | for( size_t tid = 0 ; tid < NB_TTY_CHANNELS ; tid++ ) |
---|
| 994 | { |
---|
| 995 | std::ostringstream term_name; |
---|
| 996 | term_name << "term" << tid; |
---|
| 997 | vect_names.push_back(term_name.str().c_str()); |
---|
| 998 | } |
---|
| 999 | VciMultiTty<vci_param_ext>* mtty; |
---|
| 1000 | mtty = new VciMultiTty<vci_param_ext>( "mtty", |
---|
| 1001 | IntTab(0, IOX_MTTY_TGT_ID), |
---|
| 1002 | maptab_iox, |
---|
| 1003 | vect_names); |
---|
| 1004 | |
---|
| 1005 | // IOPIC |
---|
| 1006 | VciIopic<vci_param_ext>* iopi; |
---|
| 1007 | iopi = new VciIopic<vci_param_ext>( "iopi", |
---|
| 1008 | maptab_iox, |
---|
| 1009 | IntTab(0, IOPI_LOCAL_SRCID), |
---|
| 1010 | IntTab(0, IOX_IOPI_TGT_ID), |
---|
| 1011 | 32 ); // number of input HWI |
---|
[748] | 1012 | |
---|
[769] | 1013 | // Simhelper |
---|
| 1014 | VciSimhelper<vci_param_ext>* simh; |
---|
| 1015 | simh = new VciSimhelper<vci_param_ext>("simh", |
---|
| 1016 | IntTab(0, IOX_SIMH_TGT_ID), |
---|
| 1017 | maptab_iox ); |
---|
| 1018 | |
---|
[747] | 1019 | // Clusters |
---|
| 1020 | TsarIobCluster<vci_param_int, |
---|
| 1021 | vci_param_ext, |
---|
| 1022 | dspin_int_cmd_width, |
---|
| 1023 | dspin_int_rsp_width, |
---|
| 1024 | dspin_ram_cmd_width, |
---|
[806] | 1025 | dspin_ram_rsp_width>* clusters[X_SIZE][Y_SIZE]; |
---|
[747] | 1026 | |
---|
| 1027 | #if USE_OPENMP |
---|
| 1028 | #pragma omp parallel |
---|
| 1029 | { |
---|
| 1030 | #pragma omp for |
---|
| 1031 | #endif |
---|
[806] | 1032 | for(size_t i = 0; i < (X_SIZE * Y_SIZE); i++) |
---|
[747] | 1033 | { |
---|
[806] | 1034 | size_t x = i / Y_SIZE; |
---|
| 1035 | size_t y = i % Y_SIZE; |
---|
[747] | 1036 | |
---|
| 1037 | #if USE_OPENMP |
---|
| 1038 | #pragma omp critical |
---|
| 1039 | { |
---|
| 1040 | #endif |
---|
| 1041 | std::cout << std::endl; |
---|
| 1042 | std::cout << "Cluster_" << std::dec << x << "_" << y << std::endl; |
---|
| 1043 | std::cout << std::endl; |
---|
| 1044 | |
---|
[855] | 1045 | const bool is_iob0 = (cluster(x, y) == cluster_iob0); |
---|
| 1046 | const bool is_iob1 = (cluster(x, y) == cluster_iob1); |
---|
[747] | 1047 | const bool is_io_cluster = is_iob0 || is_iob1; |
---|
| 1048 | |
---|
| 1049 | const int iox_iob_ini_id = is_iob0 ? |
---|
| 1050 | IOX_IOB0_INI_ID : |
---|
| 1051 | IOX_IOB1_INI_ID ; |
---|
| 1052 | const int iox_iob_tgt_id = is_iob0 ? |
---|
| 1053 | IOX_IOB0_TGT_ID : |
---|
| 1054 | IOX_IOB1_TGT_ID ; |
---|
| 1055 | |
---|
| 1056 | std::ostringstream sc; |
---|
| 1057 | sc << "cluster_" << x << "_" << y; |
---|
| 1058 | clusters[x][y] = new TsarIobCluster<vci_param_int, |
---|
| 1059 | vci_param_ext, |
---|
| 1060 | dspin_int_cmd_width, |
---|
| 1061 | dspin_int_rsp_width, |
---|
| 1062 | dspin_ram_cmd_width, |
---|
| 1063 | dspin_ram_rsp_width> |
---|
| 1064 | ( |
---|
| 1065 | sc.str().c_str(), |
---|
| 1066 | NB_PROCS_MAX, |
---|
| 1067 | NB_DMA_CHANNELS, |
---|
| 1068 | x, |
---|
| 1069 | y, |
---|
[806] | 1070 | X_SIZE, |
---|
| 1071 | Y_SIZE, |
---|
[747] | 1072 | |
---|
[806] | 1073 | P_WIDTH, |
---|
| 1074 | |
---|
[747] | 1075 | maptab_int, |
---|
| 1076 | maptab_ram, |
---|
| 1077 | maptab_iox, |
---|
| 1078 | |
---|
[806] | 1079 | X_WIDTH, |
---|
| 1080 | Y_WIDTH, |
---|
| 1081 | vci_srcid_width - X_WIDTH - Y_WIDTH, // l_id width, |
---|
[747] | 1082 | |
---|
| 1083 | INT_MEMC_TGT_ID, |
---|
| 1084 | INT_XICU_TGT_ID, |
---|
| 1085 | INT_MDMA_TGT_ID, |
---|
[748] | 1086 | INT_BROM_TGT_ID, |
---|
[747] | 1087 | INT_IOBX_TGT_ID, |
---|
| 1088 | |
---|
| 1089 | INT_PROC_INI_ID, |
---|
| 1090 | INT_MDMA_INI_ID, |
---|
| 1091 | INT_IOBX_INI_ID, |
---|
| 1092 | |
---|
| 1093 | RAM_XRAM_TGT_ID, |
---|
| 1094 | |
---|
| 1095 | RAM_MEMC_INI_ID, |
---|
| 1096 | RAM_IOBX_INI_ID, |
---|
| 1097 | |
---|
| 1098 | is_io_cluster, |
---|
| 1099 | iox_iob_tgt_id, |
---|
| 1100 | iox_iob_ini_id, |
---|
| 1101 | |
---|
| 1102 | MEMC_WAYS, |
---|
| 1103 | MEMC_SETS, |
---|
| 1104 | L1_IWAYS, |
---|
| 1105 | L1_ISETS, |
---|
| 1106 | L1_DWAYS, |
---|
| 1107 | L1_DSETS, |
---|
| 1108 | XRAM_LATENCY, |
---|
| 1109 | XCU_NB_INPUTS, |
---|
| 1110 | |
---|
[748] | 1111 | distributed_boot, |
---|
| 1112 | |
---|
[747] | 1113 | loader, |
---|
| 1114 | |
---|
| 1115 | frozen_cycles, |
---|
| 1116 | debug_from, |
---|
[855] | 1117 | debug_ok and (cluster(x, y) == debug_memc_id), |
---|
| 1118 | debug_ok and (cluster(x, y) == (debug_proc_id >> P_WIDTH)), |
---|
[747] | 1119 | debug_ok and debug_iob |
---|
| 1120 | ); |
---|
| 1121 | |
---|
| 1122 | #if USE_OPENMP |
---|
| 1123 | } // end critical |
---|
| 1124 | #endif |
---|
| 1125 | } // end for |
---|
| 1126 | #if USE_OPENMP |
---|
| 1127 | } |
---|
| 1128 | #endif |
---|
| 1129 | |
---|
[855] | 1130 | // disable all interfaces of the faulty router |
---|
| 1131 | if (faulty_router_id != 0xFFFFFFFF) |
---|
| 1132 | { |
---|
| 1133 | int faulty_x = faulty_router_id >> Y_WIDTH; |
---|
| 1134 | int faulty_y = faulty_router_id & ((1 << Y_WIDTH) - 1); |
---|
[859] | 1135 | clusters[faulty_x][faulty_y]->int_router_cmd[0]->set_disable_mask(faulty_mask); |
---|
[855] | 1136 | } |
---|
| 1137 | |
---|
[747] | 1138 | std::cout << std::endl; |
---|
| 1139 | |
---|
| 1140 | /////////////////////////////////////////////////////////////////////////////// |
---|
| 1141 | // Net-list |
---|
| 1142 | /////////////////////////////////////////////////////////////////////////////// |
---|
| 1143 | |
---|
| 1144 | // IOX network connexion |
---|
| 1145 | iox_network->p_clk (signal_clk); |
---|
| 1146 | iox_network->p_resetn (signal_resetn); |
---|
| 1147 | iox_network->p_to_ini[IOX_IOB0_INI_ID] (signal_vci_ini_iob0); |
---|
| 1148 | iox_network->p_to_ini[IOX_BDEV_INI_ID] (signal_vci_ini_bdev); |
---|
| 1149 | iox_network->p_to_ini[IOX_CDMA_INI_ID] (signal_vci_ini_cdma); |
---|
| 1150 | iox_network->p_to_ini[IOX_IOPI_INI_ID] (signal_vci_ini_iopi); |
---|
| 1151 | |
---|
| 1152 | iox_network->p_to_tgt[IOX_IOB0_TGT_ID] (signal_vci_tgt_iob0); |
---|
| 1153 | iox_network->p_to_tgt[IOX_MTTY_TGT_ID] (signal_vci_tgt_mtty); |
---|
| 1154 | iox_network->p_to_tgt[IOX_FBUF_TGT_ID] (signal_vci_tgt_fbuf); |
---|
| 1155 | iox_network->p_to_tgt[IOX_MNIC_TGT_ID] (signal_vci_tgt_mnic); |
---|
| 1156 | iox_network->p_to_tgt[IOX_BDEV_TGT_ID] (signal_vci_tgt_bdev); |
---|
| 1157 | iox_network->p_to_tgt[IOX_CDMA_TGT_ID] (signal_vci_tgt_cdma); |
---|
| 1158 | iox_network->p_to_tgt[IOX_IOPI_TGT_ID] (signal_vci_tgt_iopi); |
---|
[769] | 1159 | iox_network->p_to_tgt[IOX_SIMH_TGT_ID] (signal_vci_tgt_simh); |
---|
[747] | 1160 | |
---|
| 1161 | if (cluster_iob0 != cluster_iob1) |
---|
| 1162 | { |
---|
| 1163 | iox_network->p_to_ini[IOX_IOB1_INI_ID] (signal_vci_ini_iob1); |
---|
| 1164 | iox_network->p_to_tgt[IOX_IOB1_TGT_ID] (signal_vci_tgt_iob1); |
---|
| 1165 | } |
---|
| 1166 | |
---|
| 1167 | // BDEV connexion |
---|
| 1168 | bdev->p_clk (signal_clk); |
---|
| 1169 | bdev->p_resetn (signal_resetn); |
---|
| 1170 | bdev->p_irq (signal_irq_bdev); |
---|
| 1171 | bdev->p_vci_target (signal_vci_tgt_bdev); |
---|
| 1172 | bdev->p_vci_initiator (signal_vci_ini_bdev); |
---|
| 1173 | |
---|
| 1174 | std::cout << " - BDEV connected" << std::endl; |
---|
| 1175 | |
---|
| 1176 | // FBUF connexion |
---|
| 1177 | fbuf->p_clk (signal_clk); |
---|
| 1178 | fbuf->p_resetn (signal_resetn); |
---|
| 1179 | fbuf->p_vci (signal_vci_tgt_fbuf); |
---|
| 1180 | |
---|
| 1181 | std::cout << " - FBUF connected" << std::endl; |
---|
| 1182 | |
---|
| 1183 | // MNIC connexion |
---|
| 1184 | mnic->p_clk (signal_clk); |
---|
| 1185 | mnic->p_resetn (signal_resetn); |
---|
| 1186 | mnic->p_vci (signal_vci_tgt_mnic); |
---|
| 1187 | for ( size_t i=0 ; i<NB_NIC_CHANNELS ; i++ ) |
---|
| 1188 | { |
---|
| 1189 | mnic->p_rx_irq[i] (signal_irq_mnic_rx[i]); |
---|
| 1190 | mnic->p_tx_irq[i] (signal_irq_mnic_tx[i]); |
---|
| 1191 | } |
---|
| 1192 | |
---|
| 1193 | std::cout << " - MNIC connected" << std::endl; |
---|
| 1194 | |
---|
| 1195 | // MTTY connexion |
---|
| 1196 | mtty->p_clk (signal_clk); |
---|
| 1197 | mtty->p_resetn (signal_resetn); |
---|
| 1198 | mtty->p_vci (signal_vci_tgt_mtty); |
---|
[875] | 1199 | for ( size_t i=0 ; i<NB_TTY_CHANNELS ; i++ ) |
---|
| 1200 | { |
---|
| 1201 | mtty->p_irq[i] (signal_irq_mtty_rx[i]); |
---|
| 1202 | } |
---|
[747] | 1203 | std::cout << " - MTTY connected" << std::endl; |
---|
| 1204 | |
---|
| 1205 | // CDMA connexion |
---|
| 1206 | cdma->p_clk (signal_clk); |
---|
| 1207 | cdma->p_resetn (signal_resetn); |
---|
| 1208 | cdma->p_vci_target (signal_vci_tgt_cdma); |
---|
| 1209 | cdma->p_vci_initiator (signal_vci_ini_cdma); |
---|
| 1210 | for ( size_t i=0 ; i<(NB_NIC_CHANNELS*2) ; i++) |
---|
| 1211 | { |
---|
| 1212 | cdma->p_irq[i] (signal_irq_cdma[i]); |
---|
| 1213 | } |
---|
| 1214 | |
---|
| 1215 | std::cout << " - CDMA connected" << std::endl; |
---|
| 1216 | |
---|
| 1217 | // IOPI connexion |
---|
| 1218 | iopi->p_clk (signal_clk); |
---|
| 1219 | iopi->p_resetn (signal_resetn); |
---|
| 1220 | iopi->p_vci_target (signal_vci_tgt_iopi); |
---|
| 1221 | iopi->p_vci_initiator (signal_vci_ini_iopi); |
---|
| 1222 | for ( size_t i=0 ; i<32 ; i++) |
---|
| 1223 | { |
---|
| 1224 | if (i < NB_NIC_CHANNELS) iopi->p_hwi[i] (signal_irq_mnic_rx[i]); |
---|
| 1225 | else if(i < 2 ) iopi->p_hwi[i] (signal_irq_false); |
---|
| 1226 | else if(i < 2+NB_NIC_CHANNELS) iopi->p_hwi[i] (signal_irq_mnic_tx[i-2]); |
---|
| 1227 | else if(i < 4 ) iopi->p_hwi[i] (signal_irq_false); |
---|
| 1228 | else if(i < 4+NB_CMA_CHANNELS) iopi->p_hwi[i] (signal_irq_cdma[i-4]); |
---|
| 1229 | else if(i < 8) iopi->p_hwi[i] (signal_irq_false); |
---|
[875] | 1230 | else if(i < 9) iopi->p_hwi[i] (signal_irq_bdev); |
---|
| 1231 | else if(i < 16) iopi->p_hwi[i] (signal_irq_false); |
---|
| 1232 | else if(i < 16+NB_TTY_CHANNELS) iopi->p_hwi[i] (signal_irq_mtty_rx[i-16]); |
---|
[747] | 1233 | else iopi->p_hwi[i] (signal_irq_false); |
---|
| 1234 | } |
---|
| 1235 | |
---|
| 1236 | std::cout << " - IOPIC connected" << std::endl; |
---|
| 1237 | |
---|
[769] | 1238 | // Simhelper connexion |
---|
| 1239 | simh->p_clk(signal_clk); |
---|
| 1240 | simh->p_resetn(signal_resetn); |
---|
| 1241 | simh->p_vci(signal_vci_tgt_simh); |
---|
[747] | 1242 | |
---|
| 1243 | // IOB0 cluster connexion to IOX network |
---|
| 1244 | (*clusters[0][0]->p_vci_iob_iox_ini) (signal_vci_ini_iob0); |
---|
| 1245 | (*clusters[0][0]->p_vci_iob_iox_tgt) (signal_vci_tgt_iob0); |
---|
| 1246 | |
---|
| 1247 | // IOB1 cluster connexion to IOX network |
---|
| 1248 | // (only when there is more than 1 cluster) |
---|
| 1249 | if ( cluster_iob0 != cluster_iob1 ) |
---|
| 1250 | { |
---|
[806] | 1251 | (*clusters[X_SIZE-1][Y_SIZE-1]->p_vci_iob_iox_ini) (signal_vci_ini_iob1); |
---|
| 1252 | (*clusters[X_SIZE-1][Y_SIZE-1]->p_vci_iob_iox_tgt) (signal_vci_tgt_iob1); |
---|
[747] | 1253 | } |
---|
| 1254 | |
---|
| 1255 | // All clusters Clock & RESET connexions |
---|
[806] | 1256 | for ( size_t x = 0; x < (X_SIZE); x++ ) |
---|
[747] | 1257 | { |
---|
[806] | 1258 | for (size_t y = 0; y < Y_SIZE; y++) |
---|
[747] | 1259 | { |
---|
| 1260 | clusters[x][y]->p_clk (signal_clk); |
---|
| 1261 | clusters[x][y]->p_resetn (signal_resetn); |
---|
| 1262 | } |
---|
| 1263 | } |
---|
| 1264 | |
---|
| 1265 | // Inter Clusters horizontal connections |
---|
[806] | 1266 | if (X_SIZE > 1) |
---|
[747] | 1267 | { |
---|
[806] | 1268 | for (size_t x = 0; x < (X_SIZE-1); x++) |
---|
[747] | 1269 | { |
---|
[806] | 1270 | for (size_t y = 0; y < Y_SIZE; y++) |
---|
[747] | 1271 | { |
---|
| 1272 | for (size_t k = 0; k < 3; k++) |
---|
| 1273 | { |
---|
| 1274 | clusters[x][y]->p_dspin_int_cmd_out[EAST][k] (signal_dspin_int_cmd_h_inc[x][y][k]); |
---|
| 1275 | clusters[x+1][y]->p_dspin_int_cmd_in[WEST][k] (signal_dspin_int_cmd_h_inc[x][y][k]); |
---|
| 1276 | clusters[x][y]->p_dspin_int_cmd_in[EAST][k] (signal_dspin_int_cmd_h_dec[x][y][k]); |
---|
| 1277 | clusters[x+1][y]->p_dspin_int_cmd_out[WEST][k] (signal_dspin_int_cmd_h_dec[x][y][k]); |
---|
| 1278 | } |
---|
| 1279 | |
---|
| 1280 | for (size_t k = 0; k < 2; k++) |
---|
| 1281 | { |
---|
| 1282 | clusters[x][y]->p_dspin_int_rsp_out[EAST][k] (signal_dspin_int_rsp_h_inc[x][y][k]); |
---|
| 1283 | clusters[x+1][y]->p_dspin_int_rsp_in[WEST][k] (signal_dspin_int_rsp_h_inc[x][y][k]); |
---|
| 1284 | clusters[x][y]->p_dspin_int_rsp_in[EAST][k] (signal_dspin_int_rsp_h_dec[x][y][k]); |
---|
| 1285 | clusters[x+1][y]->p_dspin_int_rsp_out[WEST][k] (signal_dspin_int_rsp_h_dec[x][y][k]); |
---|
| 1286 | } |
---|
| 1287 | |
---|
| 1288 | clusters[x][y]->p_dspin_ram_cmd_out[EAST] (signal_dspin_ram_cmd_h_inc[x][y]); |
---|
| 1289 | clusters[x+1][y]->p_dspin_ram_cmd_in[WEST] (signal_dspin_ram_cmd_h_inc[x][y]); |
---|
| 1290 | clusters[x][y]->p_dspin_ram_cmd_in[EAST] (signal_dspin_ram_cmd_h_dec[x][y]); |
---|
| 1291 | clusters[x+1][y]->p_dspin_ram_cmd_out[WEST] (signal_dspin_ram_cmd_h_dec[x][y]); |
---|
| 1292 | clusters[x][y]->p_dspin_ram_rsp_out[EAST] (signal_dspin_ram_rsp_h_inc[x][y]); |
---|
| 1293 | clusters[x+1][y]->p_dspin_ram_rsp_in[WEST] (signal_dspin_ram_rsp_h_inc[x][y]); |
---|
| 1294 | clusters[x][y]->p_dspin_ram_rsp_in[EAST] (signal_dspin_ram_rsp_h_dec[x][y]); |
---|
| 1295 | clusters[x+1][y]->p_dspin_ram_rsp_out[WEST] (signal_dspin_ram_rsp_h_dec[x][y]); |
---|
| 1296 | } |
---|
| 1297 | } |
---|
| 1298 | } |
---|
| 1299 | |
---|
| 1300 | std::cout << std::endl << "Horizontal connections established" << std::endl; |
---|
| 1301 | |
---|
| 1302 | // Inter Clusters vertical connections |
---|
[806] | 1303 | if (Y_SIZE > 1) |
---|
[747] | 1304 | { |
---|
[806] | 1305 | for (size_t y = 0; y < (Y_SIZE-1); y++) |
---|
[747] | 1306 | { |
---|
[806] | 1307 | for (size_t x = 0; x < X_SIZE; x++) |
---|
[747] | 1308 | { |
---|
| 1309 | for (size_t k = 0; k < 3; k++) |
---|
| 1310 | { |
---|
| 1311 | clusters[x][y]->p_dspin_int_cmd_out[NORTH][k] (signal_dspin_int_cmd_v_inc[x][y][k]); |
---|
| 1312 | clusters[x][y+1]->p_dspin_int_cmd_in[SOUTH][k] (signal_dspin_int_cmd_v_inc[x][y][k]); |
---|
| 1313 | clusters[x][y]->p_dspin_int_cmd_in[NORTH][k] (signal_dspin_int_cmd_v_dec[x][y][k]); |
---|
| 1314 | clusters[x][y+1]->p_dspin_int_cmd_out[SOUTH][k] (signal_dspin_int_cmd_v_dec[x][y][k]); |
---|
| 1315 | } |
---|
| 1316 | |
---|
| 1317 | for (size_t k = 0; k < 2; k++) |
---|
| 1318 | { |
---|
| 1319 | clusters[x][y]->p_dspin_int_rsp_out[NORTH][k] (signal_dspin_int_rsp_v_inc[x][y][k]); |
---|
| 1320 | clusters[x][y+1]->p_dspin_int_rsp_in[SOUTH][k] (signal_dspin_int_rsp_v_inc[x][y][k]); |
---|
| 1321 | clusters[x][y]->p_dspin_int_rsp_in[NORTH][k] (signal_dspin_int_rsp_v_dec[x][y][k]); |
---|
| 1322 | clusters[x][y+1]->p_dspin_int_rsp_out[SOUTH][k] (signal_dspin_int_rsp_v_dec[x][y][k]); |
---|
| 1323 | } |
---|
| 1324 | |
---|
| 1325 | clusters[x][y]->p_dspin_ram_cmd_out[NORTH] (signal_dspin_ram_cmd_v_inc[x][y]); |
---|
| 1326 | clusters[x][y+1]->p_dspin_ram_cmd_in[SOUTH] (signal_dspin_ram_cmd_v_inc[x][y]); |
---|
| 1327 | clusters[x][y]->p_dspin_ram_cmd_in[NORTH] (signal_dspin_ram_cmd_v_dec[x][y]); |
---|
| 1328 | clusters[x][y+1]->p_dspin_ram_cmd_out[SOUTH] (signal_dspin_ram_cmd_v_dec[x][y]); |
---|
| 1329 | clusters[x][y]->p_dspin_ram_rsp_out[NORTH] (signal_dspin_ram_rsp_v_inc[x][y]); |
---|
| 1330 | clusters[x][y+1]->p_dspin_ram_rsp_in[SOUTH] (signal_dspin_ram_rsp_v_inc[x][y]); |
---|
| 1331 | clusters[x][y]->p_dspin_ram_rsp_in[NORTH] (signal_dspin_ram_rsp_v_dec[x][y]); |
---|
| 1332 | clusters[x][y+1]->p_dspin_ram_rsp_out[SOUTH] (signal_dspin_ram_rsp_v_dec[x][y]); |
---|
| 1333 | } |
---|
| 1334 | } |
---|
| 1335 | } |
---|
| 1336 | |
---|
| 1337 | std::cout << "Vertical connections established" << std::endl; |
---|
| 1338 | |
---|
| 1339 | // East & West boundary cluster connections |
---|
[806] | 1340 | for (size_t y = 0; y < Y_SIZE; y++) |
---|
[747] | 1341 | { |
---|
| 1342 | for (size_t k = 0; k < 3; k++) |
---|
| 1343 | { |
---|
[751] | 1344 | clusters[0][y]->p_dspin_int_cmd_in[WEST][k] (signal_dspin_false_int_cmd_in[0][y][WEST][k]); |
---|
| 1345 | clusters[0][y]->p_dspin_int_cmd_out[WEST][k] (signal_dspin_false_int_cmd_out[0][y][WEST][k]); |
---|
[806] | 1346 | clusters[X_SIZE-1][y]->p_dspin_int_cmd_in[EAST][k] (signal_dspin_false_int_cmd_in[X_SIZE-1][y][EAST][k]); |
---|
| 1347 | clusters[X_SIZE-1][y]->p_dspin_int_cmd_out[EAST][k] (signal_dspin_false_int_cmd_out[X_SIZE-1][y][EAST][k]); |
---|
[747] | 1348 | } |
---|
| 1349 | |
---|
| 1350 | for (size_t k = 0; k < 2; k++) |
---|
| 1351 | { |
---|
[751] | 1352 | clusters[0][y]->p_dspin_int_rsp_in[WEST][k] (signal_dspin_false_int_rsp_in[0][y][WEST][k]); |
---|
| 1353 | clusters[0][y]->p_dspin_int_rsp_out[WEST][k] (signal_dspin_false_int_rsp_out[0][y][WEST][k]); |
---|
[806] | 1354 | clusters[X_SIZE-1][y]->p_dspin_int_rsp_in[EAST][k] (signal_dspin_false_int_rsp_in[X_SIZE-1][y][EAST][k]); |
---|
| 1355 | clusters[X_SIZE-1][y]->p_dspin_int_rsp_out[EAST][k] (signal_dspin_false_int_rsp_out[X_SIZE-1][y][EAST][k]); |
---|
[747] | 1356 | } |
---|
| 1357 | |
---|
[751] | 1358 | clusters[0][y]->p_dspin_ram_cmd_in[WEST] (signal_dspin_false_ram_cmd_in[0][y][WEST]); |
---|
| 1359 | clusters[0][y]->p_dspin_ram_cmd_out[WEST] (signal_dspin_false_ram_cmd_out[0][y][WEST]); |
---|
| 1360 | clusters[0][y]->p_dspin_ram_rsp_in[WEST] (signal_dspin_false_ram_rsp_in[0][y][WEST]); |
---|
| 1361 | clusters[0][y]->p_dspin_ram_rsp_out[WEST] (signal_dspin_false_ram_rsp_out[0][y][WEST]); |
---|
[747] | 1362 | |
---|
[806] | 1363 | clusters[X_SIZE-1][y]->p_dspin_ram_cmd_in[EAST] (signal_dspin_false_ram_cmd_in[X_SIZE-1][y][EAST]); |
---|
| 1364 | clusters[X_SIZE-1][y]->p_dspin_ram_cmd_out[EAST] (signal_dspin_false_ram_cmd_out[X_SIZE-1][y][EAST]); |
---|
| 1365 | clusters[X_SIZE-1][y]->p_dspin_ram_rsp_in[EAST] (signal_dspin_false_ram_rsp_in[X_SIZE-1][y][EAST]); |
---|
| 1366 | clusters[X_SIZE-1][y]->p_dspin_ram_rsp_out[EAST] (signal_dspin_false_ram_rsp_out[X_SIZE-1][y][EAST]); |
---|
[747] | 1367 | } |
---|
| 1368 | |
---|
| 1369 | std::cout << "East & West boundaries established" << std::endl; |
---|
| 1370 | |
---|
| 1371 | // North & South boundary clusters connections |
---|
[806] | 1372 | for (size_t x = 0; x < X_SIZE; x++) |
---|
[747] | 1373 | { |
---|
| 1374 | for (size_t k = 0; k < 3; k++) |
---|
| 1375 | { |
---|
[751] | 1376 | clusters[x][0]->p_dspin_int_cmd_in[SOUTH][k] (signal_dspin_false_int_cmd_in[x][0][SOUTH][k]); |
---|
| 1377 | clusters[x][0]->p_dspin_int_cmd_out[SOUTH][k] (signal_dspin_false_int_cmd_out[x][0][SOUTH][k]); |
---|
[806] | 1378 | clusters[x][Y_SIZE-1]->p_dspin_int_cmd_in[NORTH][k] (signal_dspin_false_int_cmd_in[x][Y_SIZE-1][NORTH][k]); |
---|
| 1379 | clusters[x][Y_SIZE-1]->p_dspin_int_cmd_out[NORTH][k] (signal_dspin_false_int_cmd_out[x][Y_SIZE-1][NORTH][k]); |
---|
[747] | 1380 | } |
---|
| 1381 | |
---|
| 1382 | for (size_t k = 0; k < 2; k++) |
---|
| 1383 | { |
---|
[751] | 1384 | clusters[x][0]->p_dspin_int_rsp_in[SOUTH][k] (signal_dspin_false_int_rsp_in[x][0][SOUTH][k]); |
---|
| 1385 | clusters[x][0]->p_dspin_int_rsp_out[SOUTH][k] (signal_dspin_false_int_rsp_out[x][0][SOUTH][k]); |
---|
[806] | 1386 | clusters[x][Y_SIZE-1]->p_dspin_int_rsp_in[NORTH][k] (signal_dspin_false_int_rsp_in[x][Y_SIZE-1][NORTH][k]); |
---|
| 1387 | clusters[x][Y_SIZE-1]->p_dspin_int_rsp_out[NORTH][k] (signal_dspin_false_int_rsp_out[x][Y_SIZE-1][NORTH][k]); |
---|
[747] | 1388 | } |
---|
| 1389 | |
---|
[751] | 1390 | clusters[x][0]->p_dspin_ram_cmd_in[SOUTH] (signal_dspin_false_ram_cmd_in[x][0][SOUTH]); |
---|
| 1391 | clusters[x][0]->p_dspin_ram_cmd_out[SOUTH] (signal_dspin_false_ram_cmd_out[x][0][SOUTH]); |
---|
| 1392 | clusters[x][0]->p_dspin_ram_rsp_in[SOUTH] (signal_dspin_false_ram_rsp_in[x][0][SOUTH]); |
---|
| 1393 | clusters[x][0]->p_dspin_ram_rsp_out[SOUTH] (signal_dspin_false_ram_rsp_out[x][0][SOUTH]); |
---|
[747] | 1394 | |
---|
[806] | 1395 | clusters[x][Y_SIZE-1]->p_dspin_ram_cmd_in[NORTH] (signal_dspin_false_ram_cmd_in[x][Y_SIZE-1][NORTH]); |
---|
| 1396 | clusters[x][Y_SIZE-1]->p_dspin_ram_cmd_out[NORTH] (signal_dspin_false_ram_cmd_out[x][Y_SIZE-1][NORTH]); |
---|
| 1397 | clusters[x][Y_SIZE-1]->p_dspin_ram_rsp_in[NORTH] (signal_dspin_false_ram_rsp_in[x][Y_SIZE-1][NORTH]); |
---|
| 1398 | clusters[x][Y_SIZE-1]->p_dspin_ram_rsp_out[NORTH] (signal_dspin_false_ram_rsp_out[x][Y_SIZE-1][NORTH]); |
---|
[747] | 1399 | } |
---|
| 1400 | |
---|
| 1401 | std::cout << "North & South boundaries established" << std::endl << std::endl; |
---|
| 1402 | |
---|
| 1403 | //////////////////////////////////////////////////////// |
---|
| 1404 | // Simulation |
---|
| 1405 | /////////////////////////////////////////////////////// |
---|
| 1406 | |
---|
| 1407 | sc_start(sc_core::sc_time(0, SC_NS)); |
---|
| 1408 | |
---|
| 1409 | signal_resetn = false; |
---|
| 1410 | signal_irq_false = false; |
---|
| 1411 | |
---|
[751] | 1412 | // network boundaries signals |
---|
[806] | 1413 | for (size_t x = 0; x < X_SIZE ; x++) |
---|
[751] | 1414 | { |
---|
[806] | 1415 | for (size_t y = 0; y < Y_SIZE ; y++) |
---|
[751] | 1416 | { |
---|
| 1417 | for (size_t a = 0; a < 4; a++) |
---|
| 1418 | { |
---|
| 1419 | for (size_t k = 0; k < 3; k++) |
---|
| 1420 | { |
---|
| 1421 | signal_dspin_false_int_cmd_in[x][y][a][k].write = false; |
---|
| 1422 | signal_dspin_false_int_cmd_in[x][y][a][k].read = true; |
---|
| 1423 | signal_dspin_false_int_cmd_out[x][y][a][k].write = false; |
---|
| 1424 | signal_dspin_false_int_cmd_out[x][y][a][k].read = true; |
---|
| 1425 | } |
---|
[750] | 1426 | |
---|
[751] | 1427 | for (size_t k = 0; k < 2; k++) |
---|
| 1428 | { |
---|
| 1429 | signal_dspin_false_int_rsp_in[x][y][a][k].write = false; |
---|
| 1430 | signal_dspin_false_int_rsp_in[x][y][a][k].read = true; |
---|
| 1431 | signal_dspin_false_int_rsp_out[x][y][a][k].write = false; |
---|
| 1432 | signal_dspin_false_int_rsp_out[x][y][a][k].read = true; |
---|
| 1433 | } |
---|
| 1434 | |
---|
| 1435 | signal_dspin_false_ram_cmd_in[x][y][a].write = false; |
---|
| 1436 | signal_dspin_false_ram_cmd_in[x][y][a].read = true; |
---|
| 1437 | signal_dspin_false_ram_cmd_out[x][y][a].write = false; |
---|
| 1438 | signal_dspin_false_ram_cmd_out[x][y][a].read = true; |
---|
| 1439 | |
---|
| 1440 | signal_dspin_false_ram_rsp_in[x][y][a].write = false; |
---|
| 1441 | signal_dspin_false_ram_rsp_in[x][y][a].read = true; |
---|
| 1442 | signal_dspin_false_ram_rsp_out[x][y][a].write = false; |
---|
| 1443 | signal_dspin_false_ram_rsp_out[x][y][a].read = true; |
---|
| 1444 | } |
---|
| 1445 | } |
---|
| 1446 | } |
---|
| 1447 | |
---|
[750] | 1448 | sc_start(sc_core::sc_time(1, SC_NS)); |
---|
| 1449 | signal_resetn = true; |
---|
| 1450 | |
---|
| 1451 | // simulation loop |
---|
[855] | 1452 | struct timeval t1, t2; |
---|
[750] | 1453 | |
---|
[766] | 1454 | // cycles between stats |
---|
| 1455 | const size_t stats_period = 100000; |
---|
| 1456 | const size_t simul_period = debug_ok ? debug_period : stats_period; |
---|
[747] | 1457 | |
---|
[766] | 1458 | for (size_t n = 0; n < ncycles; n += simul_period) |
---|
[750] | 1459 | { |
---|
| 1460 | // stats display |
---|
[766] | 1461 | if((n % stats_period) == 0) |
---|
[750] | 1462 | { |
---|
[766] | 1463 | if (n > 0) |
---|
| 1464 | { |
---|
| 1465 | gettimeofday(&t2, NULL); |
---|
[747] | 1466 | |
---|
[766] | 1467 | uint64_t ms1 = (uint64_t) t1.tv_sec * 1000ULL + |
---|
| 1468 | (uint64_t) t1.tv_usec / 1000; |
---|
| 1469 | uint64_t ms2 = (uint64_t) t2.tv_sec * 1000ULL + |
---|
| 1470 | (uint64_t) t2.tv_usec / 1000; |
---|
| 1471 | std::cerr << "### cycle = " << n << " / frequency (Khz) = " |
---|
| 1472 | << (double) stats_period / (double) (ms2 - ms1) << std::endl; |
---|
| 1473 | } |
---|
[747] | 1474 | |
---|
[750] | 1475 | gettimeofday(&t1, NULL); |
---|
| 1476 | } |
---|
[747] | 1477 | |
---|
[750] | 1478 | // Monitor a specific address for one L1 cache |
---|
| 1479 | // clusters[1][1]->proc[0]->cache_monitor(0x50090ULL); |
---|
[747] | 1480 | |
---|
[750] | 1481 | // Monitor a specific address for one L2 cache |
---|
| 1482 | // clusters[0][0]->memc->cache_monitor( 0x170000ULL); |
---|
[747] | 1483 | |
---|
[750] | 1484 | // Monitor a specific address for one XRAM |
---|
| 1485 | // if (n == 3000000) clusters[0][0]->xram->start_monitor( 0x170000ULL , 64); |
---|
[747] | 1486 | |
---|
[750] | 1487 | if (debug_ok and (n > debug_from) and (n % debug_period == 0)) |
---|
| 1488 | { |
---|
| 1489 | std::cout << "****************** cycle " << std::dec << n ; |
---|
| 1490 | std::cout << " ************************************************" << std::endl; |
---|
[747] | 1491 | |
---|
[887] | 1492 | #if 0 |
---|
| 1493 | for (int x = 0; x < X_SIZE; ++x) |
---|
| 1494 | { |
---|
| 1495 | for (int y = 0; y < Y_SIZE; ++y) |
---|
| 1496 | { |
---|
| 1497 | clusters[x][y]->int_router_cmd[0]->print_trace(); |
---|
| 1498 | clusters[x][y]->int_router_rsp[0]->print_trace(); |
---|
| 1499 | } |
---|
| 1500 | } |
---|
| 1501 | #endif |
---|
| 1502 | |
---|
[750] | 1503 | // trace proc[debug_proc_id] |
---|
| 1504 | if ( debug_proc_id != 0xFFFFFFFF ) |
---|
| 1505 | { |
---|
[855] | 1506 | size_t l = debug_proc_id & ((1 << P_WIDTH) - 1); |
---|
| 1507 | size_t cluster_xy = debug_proc_id >> P_WIDTH ; |
---|
| 1508 | size_t x = cluster_xy >> Y_WIDTH; |
---|
| 1509 | size_t y = cluster_xy & ((1 << Y_WIDTH) - 1); |
---|
[747] | 1510 | |
---|
[750] | 1511 | clusters[x][y]->proc[l]->print_trace(1); |
---|
| 1512 | std::ostringstream proc_signame; |
---|
| 1513 | proc_signame << "[SIG]PROC_" << x << "_" << y << "_" << l ; |
---|
| 1514 | clusters[x][y]->signal_int_vci_ini_proc[l].print_trace(proc_signame.str()); |
---|
[747] | 1515 | |
---|
[750] | 1516 | clusters[x][y]->xicu->print_trace(l); |
---|
| 1517 | std::ostringstream xicu_signame; |
---|
| 1518 | xicu_signame << "[SIG]XICU_" << x << "_" << y; |
---|
| 1519 | clusters[x][y]->signal_int_vci_tgt_xicu.print_trace(xicu_signame.str()); |
---|
[747] | 1520 | |
---|
[750] | 1521 | // clusters[x][y]->mdma->print_trace(); |
---|
| 1522 | // std::ostringstream mdma_signame; |
---|
| 1523 | // mdma_signame << "[SIG]MDMA_" << x << "_" << y; |
---|
| 1524 | // clusters[x][y]->signal_int_vci_tgt_mdma.print_trace(mdma_signame.str()); |
---|
[748] | 1525 | |
---|
[750] | 1526 | if( clusters[x][y]->signal_proc_it[l].read() ) |
---|
| 1527 | std::cout << "### IRQ_PROC_" << std::dec |
---|
| 1528 | << x << "_" << y << "_" << l << " ACTIVE" << std::endl; |
---|
| 1529 | } |
---|
[747] | 1530 | |
---|
[750] | 1531 | // trace memc[debug_memc_id] |
---|
| 1532 | if ( debug_memc_id != 0xFFFFFFFF ) |
---|
| 1533 | { |
---|
[855] | 1534 | size_t x = debug_memc_id >> Y_WIDTH; |
---|
| 1535 | size_t y = debug_memc_id & ((1 << Y_WIDTH) - 1); |
---|
[747] | 1536 | |
---|
[750] | 1537 | clusters[x][y]->memc->print_trace(0); |
---|
| 1538 | std::ostringstream smemc_tgt; |
---|
| 1539 | smemc_tgt << "[SIG]MEMC_TGT_" << x << "_" << y; |
---|
| 1540 | clusters[x][y]->signal_int_vci_tgt_memc.print_trace(smemc_tgt.str()); |
---|
| 1541 | std::ostringstream smemc_ini; |
---|
| 1542 | smemc_ini << "[SIG]MEMC_INI_" << x << "_" << y; |
---|
| 1543 | clusters[x][y]->signal_ram_vci_ini_memc.print_trace(smemc_ini.str()); |
---|
[747] | 1544 | |
---|
[750] | 1545 | clusters[x][y]->xram->print_trace(); |
---|
| 1546 | std::ostringstream sxram_tgt; |
---|
| 1547 | sxram_tgt << "[SIG]XRAM_TGT_" << x << "_" << y; |
---|
| 1548 | clusters[x][y]->signal_ram_vci_tgt_xram.print_trace(sxram_tgt.str()); |
---|
| 1549 | } |
---|
[747] | 1550 | |
---|
| 1551 | |
---|
[750] | 1552 | // trace XRAM and XRAM network routers in cluster[debug_xram_id] |
---|
| 1553 | if ( debug_xram_id != 0xFFFFFFFF ) |
---|
| 1554 | { |
---|
[855] | 1555 | size_t x = debug_xram_id >> Y_WIDTH; |
---|
| 1556 | size_t y = debug_xram_id & ((1 << Y_WIDTH) - 1); |
---|
[747] | 1557 | |
---|
[750] | 1558 | clusters[x][y]->xram->print_trace(); |
---|
| 1559 | std::ostringstream sxram_tgt; |
---|
| 1560 | sxram_tgt << "[SIG]XRAM_TGT_" << x << "_" << y; |
---|
| 1561 | clusters[x][y]->signal_ram_vci_tgt_xram.print_trace(sxram_tgt.str()); |
---|
[747] | 1562 | |
---|
[750] | 1563 | clusters[x][y]->ram_router_cmd->print_trace(); |
---|
| 1564 | clusters[x][y]->ram_router_rsp->print_trace(); |
---|
| 1565 | } |
---|
[747] | 1566 | |
---|
[750] | 1567 | // trace iob, iox and external peripherals |
---|
| 1568 | if ( debug_iob ) |
---|
| 1569 | { |
---|
| 1570 | clusters[0][0]->iob->print_trace(); |
---|
[806] | 1571 | clusters[X_SIZE-1][Y_SIZE-1]->iob->print_trace(); |
---|
[750] | 1572 | // clusters[0][0]->signal_int_vci_tgt_iobx.print_trace( "[SIG]IOB0_INT_TGT"); |
---|
| 1573 | // clusters[0][0]->signal_int_vci_ini_iobx.print_trace( "[SIG]IOB0_INT_INI"); |
---|
| 1574 | // clusters[0][0]->signal_ram_vci_ini_iobx.print_trace( "[SIG]IOB0_RAM_INI"); |
---|
[747] | 1575 | |
---|
[750] | 1576 | signal_vci_ini_iob0.print_trace("[SIG]IOB0_IOX_INI"); |
---|
| 1577 | signal_vci_tgt_iob0.print_trace("[SIG]IOB0_IOX_TGT"); |
---|
[747] | 1578 | |
---|
[750] | 1579 | // cdma->print_trace(); |
---|
| 1580 | // signal_vci_tgt_cdma.print_trace("[SIG]IOX_CDMA_TGT"); |
---|
| 1581 | // signal_vci_ini_cdma.print_trace("[SIG]IOX_CDMA_INI"); |
---|
[747] | 1582 | |
---|
[750] | 1583 | // mtty->print_trace(); |
---|
| 1584 | // signal_vci_tgt_mtty.print_trace("[SIG]IOX_MTTY_TGT"); |
---|
[747] | 1585 | |
---|
[750] | 1586 | bdev->print_trace(); |
---|
| 1587 | signal_vci_tgt_bdev.print_trace("[SIG]BDEV_TGT"); |
---|
| 1588 | signal_vci_ini_bdev.print_trace("[SIG]BDEV_INI"); |
---|
[747] | 1589 | |
---|
[750] | 1590 | mnic->print_trace(); |
---|
| 1591 | signal_vci_tgt_mnic.print_trace("[SIG]MNIC_TGT"); |
---|
[747] | 1592 | |
---|
[750] | 1593 | // fbuf->print_trace(); |
---|
| 1594 | // signal_vci_tgt_fbuf.print_trace("[SIG]FBUF"); |
---|
[747] | 1595 | |
---|
[750] | 1596 | iopi->print_trace(); |
---|
| 1597 | signal_vci_ini_iopi.print_trace("[SIG]IOPI_INI"); |
---|
| 1598 | signal_vci_tgt_iopi.print_trace("[SIG]IOPI_TGT"); |
---|
[769] | 1599 | |
---|
| 1600 | signal_vci_tgt_simh.print_trace("[SIG]SIMH_TGT"); |
---|
| 1601 | |
---|
[750] | 1602 | iox_network->print_trace(); |
---|
[747] | 1603 | |
---|
[750] | 1604 | // interrupts |
---|
| 1605 | if (signal_irq_bdev) std::cout << "### IRQ_BDEV ACTIVE" << std::endl; |
---|
[875] | 1606 | if (signal_irq_mtty_rx[0]) std::cout << "### IRQ_MTTY ACTIVE" << std::endl; |
---|
[750] | 1607 | if (signal_irq_mnic_rx[0]) std::cout << "### IRQ_MNIC_RX[0] ACTIVE" << std::endl; |
---|
| 1608 | if (signal_irq_mnic_rx[1]) std::cout << "### IRQ_MNIC_RX[1] ACTIVE" << std::endl; |
---|
| 1609 | if (signal_irq_mnic_tx[0]) std::cout << "### IRQ_MNIC_TX[0] ACTIVE" << std::endl; |
---|
| 1610 | if (signal_irq_mnic_tx[1]) std::cout << "### IRQ_MNIC_TX[1] ACTIVE" << std::endl; |
---|
| 1611 | } |
---|
| 1612 | } |
---|
[747] | 1613 | |
---|
[766] | 1614 | sc_start(sc_core::sc_time(simul_period, SC_NS)); |
---|
[750] | 1615 | } |
---|
| 1616 | return EXIT_SUCCESS; |
---|
[747] | 1617 | } |
---|
| 1618 | |
---|
| 1619 | int sc_main (int argc, char *argv[]) |
---|
| 1620 | { |
---|
| 1621 | try { |
---|
| 1622 | return _main(argc, argv); |
---|
[769] | 1623 | } catch (soclib::exception::RunTimeError &e) { |
---|
| 1624 | std::cout << "RunTimeError: " << e.what() << std::endl; |
---|
[747] | 1625 | } catch (std::exception &e) { |
---|
| 1626 | std::cout << e.what() << std::endl; |
---|
| 1627 | } catch (...) { |
---|
| 1628 | std::cout << "Unknown exception occured" << std::endl; |
---|
| 1629 | throw; |
---|
| 1630 | } |
---|
| 1631 | return 1; |
---|
| 1632 | } |
---|
| 1633 | |
---|
| 1634 | |
---|
| 1635 | // Local Variables: |
---|
| 1636 | // tab-width: 3 |
---|
| 1637 | // c-basic-offset: 3 |
---|
| 1638 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
---|
| 1639 | // indent-tabs-mode: nil |
---|
| 1640 | // End: |
---|
| 1641 | |
---|
| 1642 | // vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3 |
---|
| 1643 | |
---|
| 1644 | |
---|
| 1645 | |
---|