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source: branches/reconfiguration/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/src/tsar_iob_cluster.cpp @ 1015

Last change on this file since 1015 was 1015, checked in by cfuguet, 9 years ago

reconf: when a local router in a cluster is faulty, the cores are kept
deactivated.

In the physical implementation this is achieved with the hardware reset signal. This signal is masked with the GO signals of the NoC BIST. Only when all the local routers pass the BIST, the reset signal of the cores is deasserted.

File size: 35.6 KB

Rev	Line
[747]	1	//////////////////////////////////////////////////////////////////////////////
	2	// File: tsar_iob_cluster.cpp
[806]	3	// Author: Alain Greiner
[747]	4	// Copyright: UPMC/LIP6
	5	// Date : april 2013
	6	// This program is released under the GNU public license
	7	//////////////////////////////////////////////////////////////////////////////
[806]	8	// Cluster(0,0) & Cluster(x_size-1,y_size-1) contains the IOB0 & IOB1 components.
[747]	9	// These two clusters contain 6 extra components:
	10	// - 1 vci_io_bridge (connected to the 3 networks.
	11	// - 3 vci_dspin_wrapper for the IOB.
[806]	12	// - 2 dspin_local_crossbar for commands and responses.
[747]	13	//////////////////////////////////////////////////////////////////////////////
	14
	15	#include "../include/tsar_iob_cluster.h"
	16
	17	#define tmpl(x) \
	18	template<typename vci_param_int , typename vci_param_ext,\
	19	size_t dspin_int_cmd_width, size_t dspin_int_rsp_width,\
	20	size_t dspin_ram_cmd_width, size_t dspin_ram_rsp_width>\
	21	x TsarIobCluster<\
	22	vci_param_int , vci_param_ext,\
	23	dspin_int_cmd_width, dspin_int_rsp_width,\
	24	dspin_ram_cmd_width, dspin_ram_rsp_width>
	25
	26	namespace soclib { namespace caba {
	27
	28	//////////////////////////////////////////////////////////////////////////
	29	// Constructor
	30	//////////////////////////////////////////////////////////////////////////
	31	tmpl(/**/)::TsarIobCluster(
[806]	32	sc_module_name insname,
	33	size_t nb_procs,
	34	size_t nb_dmas,
	35	size_t x_id,
	36	size_t y_id,
	37	size_t x_size,
	38	size_t y_size,
[747]	39
[806]	40	size_t p_width,
[747]	41
[806]	42	const soclib::common::MappingTable &mt_int,
	43	const soclib::common::MappingTable &mt_ram,
	44	const soclib::common::MappingTable &mt_iox,
[747]	45
[806]	46	size_t x_width,
	47	size_t y_width,
	48	size_t l_width,
[747]	49
[806]	50	size_t int_memc_tgt_id, // local index
	51	size_t int_xicu_tgt_id, // local index
	52	size_t int_mdma_tgt_id, // local index
[926]	53	size_t int_drom_tgt_id, // local index
[806]	54	size_t int_iobx_tgt_id, // local index
[747]	55
[806]	56	size_t int_proc_ini_id, // local index
	57	size_t int_mdma_ini_id, // local index
	58	size_t int_iobx_ini_id, // local index
[747]	59
[806]	60	size_t ram_xram_tgt_id, // local index
	61	size_t ram_memc_ini_id, // local index
	62	size_t ram_iobx_ini_id, // local index
[747]	63
[806]	64	bool is_io, // is IO cluster (IOB)?
	65	size_t iox_iobx_tgt_id, // local_index
	66	size_t iox_iobx_ini_id, // local index
[747]	67
[806]	68	size_t memc_ways,
	69	size_t memc_sets,
	70	size_t l1_i_ways,
	71	size_t l1_i_sets,
	72	size_t l1_d_ways,
	73	size_t l1_d_sets,
	74	size_t xram_latency,
[961]	75	size_t xcu_nb_hwi,
	76	size_t xcu_nb_pti,
	77	size_t xcu_nb_wti,
	78	size_t xcu_nb_out,
[963]	79	size_t irq_per_proc,
[747]	80
[806]	81	bool distboot,
[1015]	82	bool disable_procs,
[748]	83
[806]	84	const Loader &loader,
	85
	86	uint32_t frozen_cycles,
	87	uint32_t debug_start_cycle,
	88	bool memc_debug_ok,
	89	bool proc_debug_ok,
	90	bool iob_debug_ok ) :
	91
	92	// constructor initialization list
	93
	94	soclib::caba::BaseModule(insname),
	95	p_clk("clk"),
[1001]	96	p_resetn("resetn"),
[1015]	97	p_false("false"),
	98	m_nb_procs(nb_procs),
	99	m_disable_procs(disable_procs)
[747]	100	{
	101
[806]	102	assert( (x_id < x_size) and (y_id < y_size) and "Illegal cluster coordinates");
[747]	103
[1000]	104	size_t cluster_id = (x_id << y_width) \| y_id;
[806]	105
[747]	106	// Vectors of DSPIN ports for inter-cluster communications
	107	p_dspin_int_cmd_in = alloc_elems<DspinInput<dspin_int_cmd_width> >("p_int_cmd_in", 4, 3);
	108	p_dspin_int_cmd_out = alloc_elems<DspinOutput<dspin_int_cmd_width> >("p_int_cmd_out", 4, 3);
	109	p_dspin_int_rsp_in = alloc_elems<DspinInput<dspin_int_rsp_width> >("p_int_rsp_in", 4, 2);
	110	p_dspin_int_rsp_out = alloc_elems<DspinOutput<dspin_int_rsp_width> >("p_int_rsp_out", 4, 2);
	111
	112	p_dspin_ram_cmd_in = alloc_elems<DspinInput<dspin_ram_cmd_width> >("p_ext_cmd_in", 4);
	113	p_dspin_ram_cmd_out = alloc_elems<DspinOutput<dspin_ram_cmd_width> >("p_ext_cmd_out", 4);
	114	p_dspin_ram_rsp_in = alloc_elems<DspinInput<dspin_ram_rsp_width> >("p_ext_rsp_in", 4);
	115	p_dspin_ram_rsp_out = alloc_elems<DspinOutput<dspin_ram_rsp_width> >("p_ext_rsp_out", 4);
	116
	117	// VCI ports from IOB to IOX network (only in IO clusters)
[806]	118	if (is_io)
[747]	119	{
	120	p_vci_iob_iox_ini = new soclib::caba::VciInitiator<vci_param_ext>;
[806]	121	p_vci_iob_iox_tgt = new soclib::caba::VciTarget<vci_param_ext>;
[747]	122	}
	123
	124	/////////////////////////////////////////////////////////////////////////////
	125	// Hardware components
	126	/////////////////////////////////////////////////////////////////////////////
	127
	128	//////////// PROCS
[1015]	129	for (size_t p = 0; p < nb_procs && !m_disable_procs; p++)
[806]	130	{
[747]	131	std::ostringstream s_proc;
	132	s_proc << "proc_" << x_id << "_" << y_id << "_" << p;
	133	proc[p] = new VciCcVCacheWrapper<vci_param_int,
	134	dspin_int_cmd_width,
	135	dspin_int_rsp_width,
	136	GdbServer<Mips32ElIss> >(
	137	s_proc.str().c_str(),
[806]	138	(cluster_id << p_width) \| p, // GLOBAL PROC_ID
[747]	139	mt_int, // Mapping Table INT network
	140	IntTab(cluster_id,p), // SRCID
[806]	141	(cluster_id << l_width) \| p, // CC_GLOBAL_ID
[747]	142	8, // ITLB ways
	143	8, // ITLB sets
	144	8, // DTLB ways
	145	8, // DTLB sets
	146	l1_i_ways, l1_i_sets, 16, // ICACHE size
	147	l1_d_ways, l1_d_sets, 16, // DCACHE size
	148	4, // WBUF nlines
	149	4, // WBUF nwords
[806]	150	x_width, // number of bits for x coordinate
	151	y_width, // number of bits for y coordinate
[747]	152	frozen_cycles, // max frozen cycles
	153	debug_start_cycle,
	154	proc_debug_ok);
[748]	155
	156	// initialize physical address extension with cluster ID when using
	157	// distributed boot
	158	if (distboot)
	159	{
	160	proc[p]->set_dcache_paddr_ext_reset(cluster_id);
	161	proc[p]->set_icache_paddr_ext_reset(cluster_id);
	162	}
[747]	163	}
	164
[806]	165	/////////// MEMC
[747]	166	std::ostringstream s_memc;
	167	s_memc << "memc_" << x_id << "_" << y_id;
	168	memc = new VciMemCache<vci_param_int,
	169	vci_param_ext,
	170	dspin_int_rsp_width,
	171	dspin_int_cmd_width>(
	172	s_memc.str().c_str(),
	173	mt_int, // Mapping Table INT network
	174	mt_ram, // Mapping Table RAM network
	175	IntTab(cluster_id, ram_memc_ini_id), // SRCID RAM network
	176	IntTab(cluster_id, int_memc_tgt_id), // TGTID INT network
	177	x_width, // number of bits for x coordinate
	178	y_width, // number of bits for y coordinate
	179	memc_ways, memc_sets, 16, // CACHE SIZE
	180	3, // MAX NUMBER OF COPIES
	181	4096, // HEAP SIZE
	182	8, // TRANSACTION TABLE DEPTH
	183	8, // UPDATE TABLE DEPTH
	184	8, // INVALIDATE TABLE DEPTH
	185	debug_start_cycle,
	186	memc_debug_ok );
	187
	188	std::ostringstream s_wi_memc;
	189	s_wi_memc << "memc_wi_" << x_id << "_" << y_id;
	190	memc_ram_wi = new VciDspinInitiatorWrapper<vci_param_ext,
	191	dspin_ram_cmd_width,
	192	dspin_ram_rsp_width>(
	193	s_wi_memc.str().c_str(),
	194	x_width + y_width + l_width);
	195
	196	/////////// XICU
	197	std::ostringstream s_xicu;
	198	s_xicu << "xicu_" << x_id << "_" << y_id;
	199	xicu = new VciXicu<vci_param_int>(
	200	s_xicu.str().c_str(),
	201	mt_int, // mapping table INT network
	202	IntTab(cluster_id, int_xicu_tgt_id), // TGTID direct space
[961]	203	xcu_nb_pti, // number of timer IRQs
	204	xcu_nb_hwi, // number of hard IRQs
	205	xcu_nb_wti, // number of soft IRQs
	206	xcu_nb_out, // number of output IRQs
[1001]	207	6); // number of config regs
[747]	208
	209	//////////// MDMA
	210	std::ostringstream s_mdma;
	211	s_mdma << "mdma_" << x_id << "_" << y_id;
	212	mdma = new VciMultiDma<vci_param_int>(
	213	s_mdma.str().c_str(),
	214	mt_int,
	215	IntTab(cluster_id, nb_procs), // SRCID
	216	IntTab(cluster_id, int_mdma_tgt_id), // TGTID
	217	64, // burst size
	218	nb_dmas); // number of IRQs
	219
[926]	220	/////////// DISTRIBUTED ROM
	221	std::ostringstream s_drom;
	222	s_drom << "drom_" << x_id << "_" << y_id;
	223	drom = new VciSimpleRom<vci_param_int>(
	224	s_drom.str().c_str(),
	225	IntTab(cluster_id, int_drom_tgt_id),
[748]	226	mt_int,
	227	loader,
	228	x_width + y_width); // msb drop bits
	229
[747]	230	/////////// Direct LOCAL_XBAR(S)
	231	size_t nb_direct_initiators = is_io ? nb_procs + 2 : nb_procs + 1;
[748]	232	size_t nb_direct_targets = is_io ? 5 : 4;
[747]	233
	234	std::ostringstream s_int_xbar_d;
	235	s_int_xbar_d << "int_xbar_cmd_d_" << x_id << "_" << y_id;
	236	int_xbar_d = new VciLocalCrossbar<vci_param_int>(
	237	s_int_xbar_d.str().c_str(),
	238	mt_int, // mapping table
	239	cluster_id, // cluster id
	240	nb_direct_initiators, // number of local initiators
[806]	241	nb_direct_targets, // number of local targets
[1001]	242	0, // default target
	243	true ); // hardware barrier
[747]	244
	245	std::ostringstream s_int_dspin_ini_wrapper_gate_d;
	246	s_int_dspin_ini_wrapper_gate_d << "int_dspin_ini_wrapper_gate_d_"
	247	<< x_id << "_" << y_id;
	248	int_wi_gate_d = new VciDspinInitiatorWrapper<vci_param_int,
	249	dspin_int_cmd_width,
	250	dspin_int_rsp_width>(
	251	s_int_dspin_ini_wrapper_gate_d.str().c_str(),
	252	x_width + y_width + l_width);
	253
	254	std::ostringstream s_int_dspin_tgt_wrapper_gate_d;
	255	s_int_dspin_tgt_wrapper_gate_d << "int_dspin_tgt_wrapper_gate_d_"
	256	<< x_id << "_" << y_id;
	257	int_wt_gate_d = new VciDspinTargetWrapper<vci_param_int,
	258	dspin_int_cmd_width,
	259	dspin_int_rsp_width>(
	260	s_int_dspin_tgt_wrapper_gate_d.str().c_str(),
	261	x_width + y_width + l_width);
	262
	263	//////////// Coherence LOCAL_XBAR(S)
	264	std::ostringstream s_int_xbar_m2p_c;
	265	s_int_xbar_m2p_c << "int_xbar_m2p_c_" << x_id << "_" << y_id;
	266	int_xbar_m2p_c = new DspinLocalCrossbar<dspin_int_cmd_width>(
	267	s_int_xbar_m2p_c.str().c_str(),
	268	mt_int, // mapping table
	269	x_id, y_id, // cluster coordinates
	270	x_width, y_width, l_width, // several dests
	271	1, // number of local sources
[806]	272	nb_procs, // number of local dests
	273	2, 2, // fifo depths
[747]	274	true, // pseudo CMD
	275	false, // no routing table
[1001]	276	true, // broacast
	277	true ); // hardware barrier
[747]	278
	279	std::ostringstream s_int_xbar_p2m_c;
	280	s_int_xbar_p2m_c << "int_xbar_p2m_c_" << x_id << "_" << y_id;
	281	int_xbar_p2m_c = new DspinLocalCrossbar<dspin_int_rsp_width>(
	282	s_int_xbar_p2m_c.str().c_str(),
	283	mt_int, // mapping table
	284	x_id, y_id, // cluster coordinates
	285	x_width, y_width, 0, // only one dest
	286	nb_procs, // number of local sources
	287	1, // number of local dests
[806]	288	2, 2, // fifo depths
[747]	289	false, // pseudo RSP
	290	false, // no routing table
[1001]	291	false, // no broacast
	292	true ); // hardware barrier
[747]	293
	294	std::ostringstream s_int_xbar_clack_c;
	295	s_int_xbar_clack_c << "int_xbar_clack_c_" << x_id << "_" << y_id;
	296	int_xbar_clack_c = new DspinLocalCrossbar<dspin_int_cmd_width>(
	297	s_int_xbar_clack_c.str().c_str(),
	298	mt_int, // mapping table
	299	x_id, y_id, // cluster coordinates
	300	x_width, y_width, l_width,
	301	1, // number of local sources
[806]	302	nb_procs, // number of local targets
[747]	303	1, 1, // fifo depths
	304	true, // CMD
	305	false, // no routing table
[1001]	306	false, // broadcast
	307	true ); // hardware barrier
[747]	308
[995]	309	const bool ROUTER_CONFIG_SUPPORTED = true;
	310
[747]	311	////////////// INT ROUTER(S)
[851]	312	int_router_cmd = new DspinRouter<dspin_int_cmd_width>*[3];
	313	for (int k = 0; k < 3; k++)
	314	{
	315	std::ostringstream s_int_router_cmd;
	316	s_int_router_cmd << "router_cmd_" << x_id << "_" << y_id << "_" << k;
	317	int_router_cmd[k] = new DspinRouter<dspin_int_cmd_width>(
	318	s_int_router_cmd.str().c_str(),
	319	x_id, y_id,
	320	x_width, y_width,
	321	4, 4,
[995]	322	(k == 1),
	323	ROUTER_CONFIG_SUPPORTED);
[851]	324	}
[747]	325
[851]	326	int_router_rsp = new DspinRouter<dspin_int_rsp_width>*[2];
	327	for (int k = 0; k < 2; k++)
	328	{
	329	std::ostringstream s_int_router_rsp;
	330	s_int_router_rsp << "router_rsp_" << x_id << "_" << y_id << "_" << k;
	331	int_router_rsp[k] = new DspinRouter<dspin_int_rsp_width>(
	332	s_int_router_rsp.str().c_str(),
	333	x_id, y_id,
	334	x_width, y_width,
	335	4, 4,
[995]	336	false,
	337	ROUTER_CONFIG_SUPPORTED);
[851]	338	}
[747]	339
	340	////////////// XRAM
	341	std::ostringstream s_xram;
	342	s_xram << "xram_" << x_id << "_" << y_id;
	343	xram = new VciSimpleRam<vci_param_ext>(
	344	s_xram.str().c_str(),
	345	IntTab(cluster_id, ram_xram_tgt_id),
	346	mt_ram,
	347	loader,
	348	xram_latency);
	349
	350	std::ostringstream s_wt_xram;
	351	s_wt_xram << "xram_wt_" << x_id << "_" << y_id;
	352	xram_ram_wt = new VciDspinTargetWrapper<vci_param_ext,
	353	dspin_ram_cmd_width,
	354	dspin_ram_rsp_width>(
	355	s_wt_xram.str().c_str(),
	356	x_width + y_width + l_width);
	357
	358	///////////// RAM ROUTER(S)
	359	std::ostringstream s_ram_router_cmd;
	360	s_ram_router_cmd << "ram_router_cmd_" << x_id << "_" << y_id;
	361	ram_router_cmd = new DspinRouter<dspin_ram_cmd_width>(
	362	s_ram_router_cmd.str().c_str(),
	363	x_id, y_id, // router coordinates in mesh
	364	x_width, // x field width in first flit
	365	y_width, // y field width in first flit
	366	4, 4); // input & output fifo depths
	367
	368	std::ostringstream s_ram_router_rsp;
	369	s_ram_router_rsp << "ram_router_rsp_" << x_id << "_" << y_id;
	370	ram_router_rsp = new DspinRouter<dspin_ram_rsp_width>(
	371	s_ram_router_rsp.str().c_str(),
	372	x_id, y_id, // coordinates in mesh
	373	x_width, // x field width in first flit
	374	y_width, // y field width in first flit
	375	4, 4); // input & output fifo depths
	376
	377
	378	////////////////////// I/O CLUSTER ONLY ///////////////////////
	379	if ( is_io )
	380	{
	381	/////////// IO_BRIDGE
	382	std::ostringstream s_iob;
[806]	383	s_iob << "iob_" << x_id << "_" << y_id;
[747]	384	iob = new VciIoBridge<vci_param_int,
[806]	385	vci_param_ext>(
[747]	386	s_iob.str().c_str(),
	387	mt_ram, // EXT network maptab
	388	mt_int, // INT network maptab
	389	mt_iox, // IOX network maptab
	390	IntTab( cluster_id, int_iobx_tgt_id ), // INT TGTID
	391	IntTab( cluster_id, int_iobx_ini_id ), // INT SRCID
	392	IntTab( 0 , iox_iobx_tgt_id ), // IOX TGTID
	393	IntTab( 0 , iox_iobx_ini_id ), // IOX SRCID
	394	16, // cache line words
	395	8, // IOTLB ways
	396	8, // IOTLB sets
	397	debug_start_cycle,
	398	iob_debug_ok );
[806]	399
[747]	400	std::ostringstream s_iob_ram_wi;
[806]	401	s_iob_ram_wi << "iob_ram_wi_" << x_id << "_" << y_id;
[747]	402	iob_ram_wi = new VciDspinInitiatorWrapper<vci_param_ext,
	403	dspin_ram_cmd_width,
	404	dspin_ram_rsp_width>(
	405	s_iob_ram_wi.str().c_str(),
	406	vci_param_int::S);
	407
	408	std::ostringstream s_ram_xbar_cmd;
	409	s_ram_xbar_cmd << "s_ram_xbar_cmd_" << x_id << "_" << y_id;
	410	ram_xbar_cmd = new DspinLocalCrossbar<dspin_ram_cmd_width>(
	411	s_ram_xbar_cmd.str().c_str(), // name
	412	mt_ram, // mapping table
	413	x_id, y_id, // x, y
	414	x_width, y_width, l_width, // x_width, y_width, l_width
	415	2, 0, // local inputs, local outputs
	416	2, 2, // in fifo, out fifo depths
	417	true, // is cmd ?
	418	false, // use routing table ?
	419	false); // support broadcast ?
	420
	421	std::ostringstream s_ram_xbar_rsp;
	422	s_ram_xbar_rsp << "s_ram_xbar_rsp_" << x_id << "_" << y_id;
	423	ram_xbar_rsp = new DspinLocalCrossbar<dspin_ram_rsp_width>(
	424	s_ram_xbar_rsp.str().c_str(), // name
	425	mt_ram, // mapping table
	426	x_id, y_id, // x, y
	427	x_width, y_width, l_width, // x_width, y_width, l_width
	428	0, 2, // local inputs, local outputs
	429	2, 2, // in fifo, out fifo depths
	430	false, // is cmd ?
	431	true, // use routing table ?
	432	false); // support broadcast ?
	433	} // end if IO
	434
	435	////////////////////////////////////
	436	// Connections are defined here
	437	////////////////////////////////////
	438
	439	// on coherence network : local srcid[proc] in [0...nb_procs-1]
	440	// : local srcid[memc] = nb_procs
[806]	441
[747]	442	//////////////////////// internal CMD & RSP routers
[851]	443	for(int k = 0; k < 3; k++)
[747]	444	{
[851]	445	int_router_cmd[k]->p_clk (this->p_clk);
	446	int_router_cmd[k]->p_resetn (this->p_resetn);
[931]	447	int_router_cmd[k]->bind_recovery_port (signal_cfg_router_cmd[k]);
[851]	448	for (int i = 0; i < 4; i++)
[747]	449	{
[851]	450	int_router_cmd[k]->p_out[i] (this->p_dspin_int_cmd_out[i][k]);
	451	int_router_cmd[k]->p_in[i] (this->p_dspin_int_cmd_in[i][k]);
[747]	452	}
[851]	453	}
[747]	454
[851]	455	for(int k = 0; k < 2; k++)
	456	{
	457	int_router_rsp[k]->p_clk (this->p_clk);
	458	int_router_rsp[k]->p_resetn (this->p_resetn);
[931]	459	int_router_rsp[k]->bind_recovery_port (signal_cfg_router_rsp[k]);
[851]	460	for (int i = 0; i < 4; i++)
[747]	461	{
[851]	462	int_router_rsp[k]->p_out[i] (this->p_dspin_int_rsp_out[i][k]);
	463	int_router_rsp[k]->p_in[i] (this->p_dspin_int_rsp_in[i][k]);
[747]	464	}
	465	}
	466
	467	// local ports
[851]	468	int_router_cmd[0]->p_out[4] (signal_int_dspin_cmd_g2l_d);
	469	int_router_cmd[1]->p_out[4] (signal_int_dspin_m2p_g2l_c);
	470	int_router_cmd[2]->p_out[4] (signal_int_dspin_clack_g2l_c);
	471	int_router_cmd[0]->p_in[4] (signal_int_dspin_cmd_l2g_d);
	472	int_router_cmd[1]->p_in[4] (signal_int_dspin_m2p_l2g_c);
	473	int_router_cmd[2]->p_in[4] (signal_int_dspin_clack_l2g_c);
[806]	474
[851]	475	int_router_rsp[0]->p_out[4] (signal_int_dspin_rsp_g2l_d);
	476	int_router_rsp[1]->p_out[4] (signal_int_dspin_p2m_g2l_c);
	477	int_router_rsp[0]->p_in[4] (signal_int_dspin_rsp_l2g_d);
	478	int_router_rsp[1]->p_in[4] (signal_int_dspin_p2m_l2g_c);
[747]	479
[1001]	480	///////////////////// CMD & RSP local crossbar
[747]	481	int_xbar_d->p_clk (this->p_clk);
	482	int_xbar_d->p_resetn (this->p_resetn);
[1001]	483	(*int_xbar_d->p_barrier_enable) (signal_cfg_xbar_barrier);
[747]	484	int_xbar_d->p_initiator_to_up (signal_int_vci_l2g);
	485	int_xbar_d->p_target_to_up (signal_int_vci_g2l);
	486
	487	int_xbar_d->p_to_target[int_memc_tgt_id] (signal_int_vci_tgt_memc);
	488	int_xbar_d->p_to_target[int_xicu_tgt_id] (signal_int_vci_tgt_xicu);
	489	int_xbar_d->p_to_target[int_mdma_tgt_id] (signal_int_vci_tgt_mdma);
[926]	490	int_xbar_d->p_to_target[int_drom_tgt_id] (signal_int_vci_tgt_drom);
[747]	491	int_xbar_d->p_to_initiator[int_mdma_ini_id] (signal_int_vci_ini_mdma);
	492	for (size_t p = 0; p < nb_procs; p++)
	493	int_xbar_d->p_to_initiator[int_proc_ini_id + p] (signal_int_vci_ini_proc[p]);
	494
	495	if ( is_io )
	496	{
	497	int_xbar_d->p_to_target[int_iobx_tgt_id] (signal_int_vci_tgt_iobx);
	498	int_xbar_d->p_to_initiator[int_iobx_ini_id] (signal_int_vci_ini_iobx);
	499	}
	500
	501	int_wi_gate_d->p_clk (this->p_clk);
	502	int_wi_gate_d->p_resetn (this->p_resetn);
	503	int_wi_gate_d->p_vci (signal_int_vci_l2g);
	504	int_wi_gate_d->p_dspin_cmd (signal_int_dspin_cmd_l2g_d);
	505	int_wi_gate_d->p_dspin_rsp (signal_int_dspin_rsp_g2l_d);
	506
	507	int_wt_gate_d->p_clk (this->p_clk);
	508	int_wt_gate_d->p_resetn (this->p_resetn);
	509	int_wt_gate_d->p_vci (signal_int_vci_g2l);
	510	int_wt_gate_d->p_dspin_cmd (signal_int_dspin_cmd_g2l_d);
	511	int_wt_gate_d->p_dspin_rsp (signal_int_dspin_rsp_l2g_d);
[806]	512
[747]	513	////////////////////// M2P DSPIN local crossbar coherence
	514	int_xbar_m2p_c->p_clk (this->p_clk);
	515	int_xbar_m2p_c->p_resetn (this->p_resetn);
[1001]	516	(*int_xbar_m2p_c->p_barrier_enable) (signal_cfg_xbar_barrier);
[747]	517	int_xbar_m2p_c->p_global_out (signal_int_dspin_m2p_l2g_c);
	518	int_xbar_m2p_c->p_global_in (signal_int_dspin_m2p_g2l_c);
	519	int_xbar_m2p_c->p_local_in[0] (signal_int_dspin_m2p_memc);
[806]	520	for (size_t p = 0; p < nb_procs; p++)
[747]	521	int_xbar_m2p_c->p_local_out[p] (signal_int_dspin_m2p_proc[p]);
	522
	523	////////////////////////// P2M DSPIN local crossbar coherence
	524	int_xbar_p2m_c->p_clk (this->p_clk);
	525	int_xbar_p2m_c->p_resetn (this->p_resetn);
[1001]	526	(*int_xbar_p2m_c->p_barrier_enable) (signal_cfg_xbar_barrier);
[747]	527	int_xbar_p2m_c->p_global_out (signal_int_dspin_p2m_l2g_c);
	528	int_xbar_p2m_c->p_global_in (signal_int_dspin_p2m_g2l_c);
	529	int_xbar_p2m_c->p_local_out[0] (signal_int_dspin_p2m_memc);
[806]	530	for (size_t p = 0; p < nb_procs; p++)
[747]	531	int_xbar_p2m_c->p_local_in[p] (signal_int_dspin_p2m_proc[p]);
	532
	533	////////////////////// CLACK DSPIN local crossbar coherence
	534	int_xbar_clack_c->p_clk (this->p_clk);
	535	int_xbar_clack_c->p_resetn (this->p_resetn);
[1001]	536	(*int_xbar_clack_c->p_barrier_enable) (signal_cfg_xbar_barrier);
[747]	537	int_xbar_clack_c->p_global_out (signal_int_dspin_clack_l2g_c);
	538	int_xbar_clack_c->p_global_in (signal_int_dspin_clack_g2l_c);
	539	int_xbar_clack_c->p_local_in[0] (signal_int_dspin_clack_memc);
	540	for (size_t p = 0; p < nb_procs; p++)
	541	int_xbar_clack_c->p_local_out[p] (signal_int_dspin_clack_proc[p]);
	542
	543	//////////////////////////////////// Processors
[1015]	544	for (size_t p = 0; p < nb_procs && !m_disable_procs; p++)
[747]	545	{
	546	proc[p]->p_clk (this->p_clk);
	547	proc[p]->p_resetn (this->p_resetn);
	548	proc[p]->p_vci (signal_int_vci_ini_proc[p]);
	549	proc[p]->p_dspin_m2p (signal_int_dspin_m2p_proc[p]);
	550	proc[p]->p_dspin_p2m (signal_int_dspin_p2m_proc[p]);
	551	proc[p]->p_dspin_clack (signal_int_dspin_clack_proc[p]);
	552
	553	for ( size_t j = 0 ; j < 6 ; j++)
	554	{
[963]	555	if ( j < irq_per_proc )
	556	{
	557	proc[p]->p_irq[j] (signal_proc_it[irq_per_proc*p + j]);
	558	}
	559	else
	560	{
[1001]	561	proc[p]->p_irq[j] (this->p_false);
[963]	562	}
[747]	563	}
	564	}
	565
	566	///////////////////////////////////// XICU
	567	xicu->p_clk (this->p_clk);
	568	xicu->p_resetn (this->p_resetn);
	569	xicu->p_vci (signal_int_vci_tgt_xicu);
[961]	570	for ( size_t i=0 ; i < xcu_nb_out ; i++)
[747]	571	{
	572	xicu->p_irq[i] (signal_proc_it[i]);
	573	}
[961]	574	for ( size_t i=0 ; i < xcu_nb_hwi ; i++)
[747]	575	{
	576	if ( i == 0 ) xicu->p_hwi[i] (signal_irq_memc);
	577	else if ( i <= nb_dmas ) xicu->p_hwi[i] (signal_irq_mdma[i-1]);
[1001]	578	else xicu->p_hwi[i] (this->p_false);
[806]	579	}
[904]	580	xicu->p_cfg[0] (signal_cfg_router_cmd[0]); // CMD
	581	xicu->p_cfg[1] (signal_cfg_router_rsp[0]); // RSP
	582	xicu->p_cfg[2] (signal_cfg_router_cmd[1]); // M2P
	583	xicu->p_cfg[3] (signal_cfg_router_rsp[1]); // P2M
	584	xicu->p_cfg[4] (signal_cfg_router_cmd[2]); // CLACK
[1001]	585	xicu->p_cfg[5] (signal_cfg_xbar_barrier); // CLACK
[747]	586
	587	///////////////////////////////////// MEMC
	588	memc->p_clk (this->p_clk);
	589	memc->p_resetn (this->p_resetn);
	590	memc->p_vci_ixr (signal_ram_vci_ini_memc);
	591	memc->p_vci_tgt (signal_int_vci_tgt_memc);
	592	memc->p_dspin_p2m (signal_int_dspin_p2m_memc);
	593	memc->p_dspin_m2p (signal_int_dspin_m2p_memc);
	594	memc->p_dspin_clack (signal_int_dspin_clack_memc);
	595	memc->p_irq (signal_irq_memc);
	596
	597	// wrapper to RAM network
	598	memc_ram_wi->p_clk (this->p_clk);
	599	memc_ram_wi->p_resetn (this->p_resetn);
	600	memc_ram_wi->p_dspin_cmd (signal_ram_dspin_cmd_memc_i);
	601	memc_ram_wi->p_dspin_rsp (signal_ram_dspin_rsp_memc_i);
	602	memc_ram_wi->p_vci (signal_ram_vci_ini_memc);
	603
	604	//////////////////////////////////// XRAM
	605	xram->p_clk (this->p_clk);
	606	xram->p_resetn (this->p_resetn);
	607	xram->p_vci (signal_ram_vci_tgt_xram);
	608
	609	// wrapper to RAM network
	610	xram_ram_wt->p_clk (this->p_clk);
	611	xram_ram_wt->p_resetn (this->p_resetn);
	612	xram_ram_wt->p_dspin_cmd (signal_ram_dspin_cmd_xram_t);
	613	xram_ram_wt->p_dspin_rsp (signal_ram_dspin_rsp_xram_t);
	614	xram_ram_wt->p_vci (signal_ram_vci_tgt_xram);
	615
	616	/////////////////////////////////// MDMA
	617	mdma->p_clk (this->p_clk);
	618	mdma->p_resetn (this->p_resetn);
	619	mdma->p_vci_target (signal_int_vci_tgt_mdma);
	620	mdma->p_vci_initiator (signal_int_vci_ini_mdma);
	621	for (size_t i=0 ; i<nb_dmas ; i++)
	622	mdma->p_irq[i] (signal_irq_mdma[i]);
	623
[926]	624	/////////////////////////////////// DROM
	625	drom->p_clk (this->p_clk);
	626	drom->p_resetn (this->p_resetn);
	627	drom->p_vci (signal_int_vci_tgt_drom);
[748]	628
[747]	629	//////////////////////////// RAM network CMD & RSP routers
	630	ram_router_cmd->p_clk (this->p_clk);
	631	ram_router_cmd->p_resetn (this->p_resetn);
	632	ram_router_rsp->p_clk (this->p_clk);
	633	ram_router_rsp->p_resetn (this->p_resetn);
	634	for( size_t n=0 ; n<4 ; n++)
	635	{
	636	ram_router_cmd->p_out[n] (this->p_dspin_ram_cmd_out[n]);
	637	ram_router_cmd->p_in[n] (this->p_dspin_ram_cmd_in[n]);
	638	ram_router_rsp->p_out[n] (this->p_dspin_ram_rsp_out[n]);
	639	ram_router_rsp->p_in[n] (this->p_dspin_ram_rsp_in[n]);
	640	}
	641
	642	ram_router_cmd->p_out[4] (signal_ram_dspin_cmd_xram_t);
	643	ram_router_rsp->p_in[4] (signal_ram_dspin_rsp_xram_t);
	644
	645	if ( is_io )
	646	{
	647	ram_router_cmd->p_in[4] (signal_ram_dspin_cmd_xbar);
	648	ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_xbar);
	649	}
	650	else
	651	{
	652	ram_router_cmd->p_in[4] (signal_ram_dspin_cmd_memc_i);
	653	ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_memc_i);
	654	}
[806]	655
	656	///////////////////////// IOB exists only in cluster_iob0 & cluster_iob1.
[747]	657	if ( is_io )
	658	{
	659	// IO bridge
	660	iob->p_clk (this->p_clk);
	661	iob->p_resetn (this->p_resetn);
	662	iob->p_vci_ini_iox (*(this->p_vci_iob_iox_ini));
	663	iob->p_vci_tgt_iox (*(this->p_vci_iob_iox_tgt));
	664	iob->p_vci_tgt_int (signal_int_vci_tgt_iobx);
	665	iob->p_vci_ini_int (signal_int_vci_ini_iobx);
	666	iob->p_vci_ini_ram (signal_ram_vci_ini_iobx);
	667
	668	// initiator wrapper to RAM network
	669	iob_ram_wi->p_clk (this->p_clk);
	670	iob_ram_wi->p_resetn (this->p_resetn);
	671	iob_ram_wi->p_dspin_cmd (signal_ram_dspin_cmd_iob_i);
	672	iob_ram_wi->p_dspin_rsp (signal_ram_dspin_rsp_iob_i);
	673	iob_ram_wi->p_vci (signal_ram_vci_ini_iobx);
	674
	675	// crossbar between MEMC and IOB to RAM network
	676	ram_xbar_cmd->p_clk (this->p_clk);
	677	ram_xbar_cmd->p_resetn (this->p_resetn);
	678	ram_xbar_cmd->p_global_out (signal_ram_dspin_cmd_xbar);
	679	ram_xbar_cmd->p_global_in (signal_ram_dspin_cmd_false);
	680	ram_xbar_cmd->p_local_in[ram_memc_ini_id] (signal_ram_dspin_cmd_memc_i);
	681	ram_xbar_cmd->p_local_in[ram_iobx_ini_id] (signal_ram_dspin_cmd_iob_i);
	682
	683	ram_xbar_rsp->p_clk (this->p_clk);
	684	ram_xbar_rsp->p_resetn (this->p_resetn);
	685	ram_xbar_rsp->p_global_out (signal_ram_dspin_rsp_false);
	686	ram_xbar_rsp->p_global_in (signal_ram_dspin_rsp_xbar);
	687	ram_xbar_rsp->p_local_out[ram_memc_ini_id] (signal_ram_dspin_rsp_memc_i);
	688	ram_xbar_rsp->p_local_out[ram_iobx_ini_id] (signal_ram_dspin_rsp_iob_i);
	689	}
	690
	691	SC_METHOD(init);
	692
	693	} // end constructor
	694
	695	tmpl(void)::init()
	696	{
[1015]	697	for (size_t p = 0; p < m_nb_procs && m_disable_procs; p++)
	698	{
	699	signal_int_vci_ini_proc[p].cmdval = false;
	700	signal_int_vci_ini_proc[p].rspack = true;
	701	signal_int_dspin_m2p_proc[p].read = true;
	702	signal_int_dspin_p2m_proc[p].write = false;
	703	signal_int_dspin_clack_proc[p].write = false;
	704	}
	705
	706	signal_ram_dspin_cmd_false.write = false;
	707	signal_ram_dspin_rsp_false.read = true;
[747]	708	} // end init
	709
[851]	710	tmpl(/**/)::~TsarIobCluster()
	711	{
	712	for (int k = 0; k < 3; k++)
	713	{
	714	delete int_router_cmd[k];
	715	}
	716	delete [] int_router_cmd;
	717
	718	for (int k = 0; k < 2; k++)
	719	{
	720	delete int_router_rsp[k];
	721	}
	722	delete [] int_router_rsp;
	723	}
	724
[747]	725	}}
	726
	727
	728	// Local Variables:
[748]	729	// tab-width: 4
	730	// c-basic-offset: 4
[747]	731	// c-file-offsets:((innamespace . 0)(inline-open . 0))
	732	// indent-tabs-mode: nil
	733	// End:
	734
[748]	735	// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
[747]	736

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Project-Id-Version: Trac 0.12
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POT-Creation-Date: 2018-07-07 16:55+0000
PO-Revision-Date: 2010-07-19 23:05+0200
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Language-Team: en_US <trac-dev@googlegroups.com>
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