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tsar_iob_cluster.cpp @ 1001

Last change on this file since 1001 was 1001, checked in by cfuguet, 9 years ago

reconf: introducing a hardware barrier in the global-local interface of
the local interconnects.

This barrier is controlled by a port (barrier enable) in the dspin and vci local interconnects.

The barrier enable port is connected to a configuration register of the XICU component to allow the software to control this barrier. The barrier is enabled when the barrier enable port value is different of 0xFFFFFFFF. As the configuration register of the XICU component are reset to 0, this barrier is enabled by default.

This barrier allows to isolate the cluster from the rest of the architecture and only if it self-diagnoses as functional, it release the barrier to communicate with the others.

The same barrier enable signal is connected to the five local interconnects. Therefore, either all are released or all are disabled.

If a local initiator or an external initiator sends a packet out or into the cluster respectively, and the barrier is enabled, the packet is dropped.

File size: 35.1 KB

Line
1	//////////////////////////////////////////////////////////////////////////////
2	// File: tsar_iob_cluster.cpp
3	// Author: Alain Greiner
4	// Copyright: UPMC/LIP6
5	// Date : april 2013
6	// This program is released under the GNU public license
7	//////////////////////////////////////////////////////////////////////////////
8	// Cluster(0,0) & Cluster(x_size-1,y_size-1) contains the IOB0 & IOB1 components.
9	// These two clusters contain 6 extra components:
10	// - 1 vci_io_bridge (connected to the 3 networks.
11	// - 3 vci_dspin_wrapper for the IOB.
12	// - 2 dspin_local_crossbar for commands and responses.
13	//////////////////////////////////////////////////////////////////////////////
14
15	#include "../include/tsar_iob_cluster.h"
16
17	#define tmpl(x) \
18	template<typename vci_param_int , typename vci_param_ext,\
19	size_t dspin_int_cmd_width, size_t dspin_int_rsp_width,\
20	size_t dspin_ram_cmd_width, size_t dspin_ram_rsp_width>\
21	x TsarIobCluster<\
22	vci_param_int , vci_param_ext,\
23	dspin_int_cmd_width, dspin_int_rsp_width,\
24	dspin_ram_cmd_width, dspin_ram_rsp_width>
25
26	namespace soclib { namespace caba {
27
28	//////////////////////////////////////////////////////////////////////////
29	// Constructor
30	//////////////////////////////////////////////////////////////////////////
31	tmpl(/**/)::TsarIobCluster(
32	sc_module_name insname,
33	size_t nb_procs,
34	size_t nb_dmas,
35	size_t x_id,
36	size_t y_id,
37	size_t x_size,
38	size_t y_size,
39
40	size_t p_width,
41
42	const soclib::common::MappingTable &mt_int,
43	const soclib::common::MappingTable &mt_ram,
44	const soclib::common::MappingTable &mt_iox,
45
46	size_t x_width,
47	size_t y_width,
48	size_t l_width,
49
50	size_t int_memc_tgt_id, // local index
51	size_t int_xicu_tgt_id, // local index
52	size_t int_mdma_tgt_id, // local index
53	size_t int_drom_tgt_id, // local index
54	size_t int_iobx_tgt_id, // local index
55
56	size_t int_proc_ini_id, // local index
57	size_t int_mdma_ini_id, // local index
58	size_t int_iobx_ini_id, // local index
59
60	size_t ram_xram_tgt_id, // local index
61	size_t ram_memc_ini_id, // local index
62	size_t ram_iobx_ini_id, // local index
63
64	bool is_io, // is IO cluster (IOB)?
65	size_t iox_iobx_tgt_id, // local_index
66	size_t iox_iobx_ini_id, // local index
67
68	size_t memc_ways,
69	size_t memc_sets,
70	size_t l1_i_ways,
71	size_t l1_i_sets,
72	size_t l1_d_ways,
73	size_t l1_d_sets,
74	size_t xram_latency,
75	size_t xcu_nb_hwi,
76	size_t xcu_nb_pti,
77	size_t xcu_nb_wti,
78	size_t xcu_nb_out,
79	size_t irq_per_proc,
80
81	bool distboot,
82
83	const Loader &loader,
84
85	uint32_t frozen_cycles,
86	uint32_t debug_start_cycle,
87	bool memc_debug_ok,
88	bool proc_debug_ok,
89	bool iob_debug_ok ) :
90
91	// constructor initialization list
92
93	soclib::caba::BaseModule(insname),
94	p_clk("clk"),
95	p_resetn("resetn"),
96	p_false("false")
97	{
98
99	assert( (x_id < x_size) and (y_id < y_size) and "Illegal cluster coordinates");
100
101	size_t cluster_id = (x_id << y_width) \| y_id;
102
103	// Vectors of DSPIN ports for inter-cluster communications
104	p_dspin_int_cmd_in = alloc_elems<DspinInput<dspin_int_cmd_width> >("p_int_cmd_in", 4, 3);
105	p_dspin_int_cmd_out = alloc_elems<DspinOutput<dspin_int_cmd_width> >("p_int_cmd_out", 4, 3);
106	p_dspin_int_rsp_in = alloc_elems<DspinInput<dspin_int_rsp_width> >("p_int_rsp_in", 4, 2);
107	p_dspin_int_rsp_out = alloc_elems<DspinOutput<dspin_int_rsp_width> >("p_int_rsp_out", 4, 2);
108
109	p_dspin_ram_cmd_in = alloc_elems<DspinInput<dspin_ram_cmd_width> >("p_ext_cmd_in", 4);
110	p_dspin_ram_cmd_out = alloc_elems<DspinOutput<dspin_ram_cmd_width> >("p_ext_cmd_out", 4);
111	p_dspin_ram_rsp_in = alloc_elems<DspinInput<dspin_ram_rsp_width> >("p_ext_rsp_in", 4);
112	p_dspin_ram_rsp_out = alloc_elems<DspinOutput<dspin_ram_rsp_width> >("p_ext_rsp_out", 4);
113
114	// VCI ports from IOB to IOX network (only in IO clusters)
115	if (is_io)
116	{
117	p_vci_iob_iox_ini = new soclib::caba::VciInitiator<vci_param_ext>;
118	p_vci_iob_iox_tgt = new soclib::caba::VciTarget<vci_param_ext>;
119	}
120
121	/////////////////////////////////////////////////////////////////////////////
122	// Hardware components
123	/////////////////////////////////////////////////////////////////////////////
124
125	//////////// PROCS
126	for (size_t p = 0; p < nb_procs; p++)
127	{
128	std::ostringstream s_proc;
129	s_proc << "proc_" << x_id << "_" << y_id << "_" << p;
130	proc[p] = new VciCcVCacheWrapper<vci_param_int,
131	dspin_int_cmd_width,
132	dspin_int_rsp_width,
133	GdbServer<Mips32ElIss> >(
134	s_proc.str().c_str(),
135	(cluster_id << p_width) \| p, // GLOBAL PROC_ID
136	mt_int, // Mapping Table INT network
137	IntTab(cluster_id,p), // SRCID
138	(cluster_id << l_width) \| p, // CC_GLOBAL_ID
139	8, // ITLB ways
140	8, // ITLB sets
141	8, // DTLB ways
142	8, // DTLB sets
143	l1_i_ways, l1_i_sets, 16, // ICACHE size
144	l1_d_ways, l1_d_sets, 16, // DCACHE size
145	4, // WBUF nlines
146	4, // WBUF nwords
147	x_width, // number of bits for x coordinate
148	y_width, // number of bits for y coordinate
149	frozen_cycles, // max frozen cycles
150	debug_start_cycle,
151	proc_debug_ok);
152
153	// initialize physical address extension with cluster ID when using
154	// distributed boot
155	if (distboot)
156	{
157	proc[p]->set_dcache_paddr_ext_reset(cluster_id);
158	proc[p]->set_icache_paddr_ext_reset(cluster_id);
159	}
160	}
161
162	/////////// MEMC
163	std::ostringstream s_memc;
164	s_memc << "memc_" << x_id << "_" << y_id;
165	memc = new VciMemCache<vci_param_int,
166	vci_param_ext,
167	dspin_int_rsp_width,
168	dspin_int_cmd_width>(
169	s_memc.str().c_str(),
170	mt_int, // Mapping Table INT network
171	mt_ram, // Mapping Table RAM network
172	IntTab(cluster_id, ram_memc_ini_id), // SRCID RAM network
173	IntTab(cluster_id, int_memc_tgt_id), // TGTID INT network
174	x_width, // number of bits for x coordinate
175	y_width, // number of bits for y coordinate
176	memc_ways, memc_sets, 16, // CACHE SIZE
177	3, // MAX NUMBER OF COPIES
178	4096, // HEAP SIZE
179	8, // TRANSACTION TABLE DEPTH
180	8, // UPDATE TABLE DEPTH
181	8, // INVALIDATE TABLE DEPTH
182	debug_start_cycle,
183	memc_debug_ok );
184
185	std::ostringstream s_wi_memc;
186	s_wi_memc << "memc_wi_" << x_id << "_" << y_id;
187	memc_ram_wi = new VciDspinInitiatorWrapper<vci_param_ext,
188	dspin_ram_cmd_width,
189	dspin_ram_rsp_width>(
190	s_wi_memc.str().c_str(),
191	x_width + y_width + l_width);
192
193	/////////// XICU
194	std::ostringstream s_xicu;
195	s_xicu << "xicu_" << x_id << "_" << y_id;
196	xicu = new VciXicu<vci_param_int>(
197	s_xicu.str().c_str(),
198	mt_int, // mapping table INT network
199	IntTab(cluster_id, int_xicu_tgt_id), // TGTID direct space
200	xcu_nb_pti, // number of timer IRQs
201	xcu_nb_hwi, // number of hard IRQs
202	xcu_nb_wti, // number of soft IRQs
203	xcu_nb_out, // number of output IRQs
204	6); // number of config regs
205
206	//////////// MDMA
207	std::ostringstream s_mdma;
208	s_mdma << "mdma_" << x_id << "_" << y_id;
209	mdma = new VciMultiDma<vci_param_int>(
210	s_mdma.str().c_str(),
211	mt_int,
212	IntTab(cluster_id, nb_procs), // SRCID
213	IntTab(cluster_id, int_mdma_tgt_id), // TGTID
214	64, // burst size
215	nb_dmas); // number of IRQs
216
217	/////////// DISTRIBUTED ROM
218	std::ostringstream s_drom;
219	s_drom << "drom_" << x_id << "_" << y_id;
220	drom = new VciSimpleRom<vci_param_int>(
221	s_drom.str().c_str(),
222	IntTab(cluster_id, int_drom_tgt_id),
223	mt_int,
224	loader,
225	x_width + y_width); // msb drop bits
226
227	/////////// Direct LOCAL_XBAR(S)
228	size_t nb_direct_initiators = is_io ? nb_procs + 2 : nb_procs + 1;
229	size_t nb_direct_targets = is_io ? 5 : 4;
230
231	std::ostringstream s_int_xbar_d;
232	s_int_xbar_d << "int_xbar_cmd_d_" << x_id << "_" << y_id;
233	int_xbar_d = new VciLocalCrossbar<vci_param_int>(
234	s_int_xbar_d.str().c_str(),
235	mt_int, // mapping table
236	cluster_id, // cluster id
237	nb_direct_initiators, // number of local initiators
238	nb_direct_targets, // number of local targets
239	0, // default target
240	true ); // hardware barrier
241
242	std::ostringstream s_int_dspin_ini_wrapper_gate_d;
243	s_int_dspin_ini_wrapper_gate_d << "int_dspin_ini_wrapper_gate_d_"
244	<< x_id << "_" << y_id;
245	int_wi_gate_d = new VciDspinInitiatorWrapper<vci_param_int,
246	dspin_int_cmd_width,
247	dspin_int_rsp_width>(
248	s_int_dspin_ini_wrapper_gate_d.str().c_str(),
249	x_width + y_width + l_width);
250
251	std::ostringstream s_int_dspin_tgt_wrapper_gate_d;
252	s_int_dspin_tgt_wrapper_gate_d << "int_dspin_tgt_wrapper_gate_d_"
253	<< x_id << "_" << y_id;
254	int_wt_gate_d = new VciDspinTargetWrapper<vci_param_int,
255	dspin_int_cmd_width,
256	dspin_int_rsp_width>(
257	s_int_dspin_tgt_wrapper_gate_d.str().c_str(),
258	x_width + y_width + l_width);
259
260	//////////// Coherence LOCAL_XBAR(S)
261	std::ostringstream s_int_xbar_m2p_c;
262	s_int_xbar_m2p_c << "int_xbar_m2p_c_" << x_id << "_" << y_id;
263	int_xbar_m2p_c = new DspinLocalCrossbar<dspin_int_cmd_width>(
264	s_int_xbar_m2p_c.str().c_str(),
265	mt_int, // mapping table
266	x_id, y_id, // cluster coordinates
267	x_width, y_width, l_width, // several dests
268	1, // number of local sources
269	nb_procs, // number of local dests
270	2, 2, // fifo depths
271	true, // pseudo CMD
272	false, // no routing table
273	true, // broacast
274	true ); // hardware barrier
275
276	std::ostringstream s_int_xbar_p2m_c;
277	s_int_xbar_p2m_c << "int_xbar_p2m_c_" << x_id << "_" << y_id;
278	int_xbar_p2m_c = new DspinLocalCrossbar<dspin_int_rsp_width>(
279	s_int_xbar_p2m_c.str().c_str(),
280	mt_int, // mapping table
281	x_id, y_id, // cluster coordinates
282	x_width, y_width, 0, // only one dest
283	nb_procs, // number of local sources
284	1, // number of local dests
285	2, 2, // fifo depths
286	false, // pseudo RSP
287	false, // no routing table
288	false, // no broacast
289	true ); // hardware barrier
290
291	std::ostringstream s_int_xbar_clack_c;
292	s_int_xbar_clack_c << "int_xbar_clack_c_" << x_id << "_" << y_id;
293	int_xbar_clack_c = new DspinLocalCrossbar<dspin_int_cmd_width>(
294	s_int_xbar_clack_c.str().c_str(),
295	mt_int, // mapping table
296	x_id, y_id, // cluster coordinates
297	x_width, y_width, l_width,
298	1, // number of local sources
299	nb_procs, // number of local targets
300	1, 1, // fifo depths
301	true, // CMD
302	false, // no routing table
303	false, // broadcast
304	true ); // hardware barrier
305
306	const bool ROUTER_CONFIG_SUPPORTED = true;
307
308	////////////// INT ROUTER(S)
309	int_router_cmd = new DspinRouter<dspin_int_cmd_width>*[3];
310	for (int k = 0; k < 3; k++)
311	{
312	std::ostringstream s_int_router_cmd;
313	s_int_router_cmd << "router_cmd_" << x_id << "_" << y_id << "_" << k;
314	int_router_cmd[k] = new DspinRouter<dspin_int_cmd_width>(
315	s_int_router_cmd.str().c_str(),
316	x_id, y_id,
317	x_width, y_width,
318	4, 4,
319	(k == 1),
320	ROUTER_CONFIG_SUPPORTED);
321	}
322
323	int_router_rsp = new DspinRouter<dspin_int_rsp_width>*[2];
324	for (int k = 0; k < 2; k++)
325	{
326	std::ostringstream s_int_router_rsp;
327	s_int_router_rsp << "router_rsp_" << x_id << "_" << y_id << "_" << k;
328	int_router_rsp[k] = new DspinRouter<dspin_int_rsp_width>(
329	s_int_router_rsp.str().c_str(),
330	x_id, y_id,
331	x_width, y_width,
332	4, 4,
333	false,
334	ROUTER_CONFIG_SUPPORTED);
335	}
336
337	////////////// XRAM
338	std::ostringstream s_xram;
339	s_xram << "xram_" << x_id << "_" << y_id;
340	xram = new VciSimpleRam<vci_param_ext>(
341	s_xram.str().c_str(),
342	IntTab(cluster_id, ram_xram_tgt_id),
343	mt_ram,
344	loader,
345	xram_latency);
346
347	std::ostringstream s_wt_xram;
348	s_wt_xram << "xram_wt_" << x_id << "_" << y_id;
349	xram_ram_wt = new VciDspinTargetWrapper<vci_param_ext,
350	dspin_ram_cmd_width,
351	dspin_ram_rsp_width>(
352	s_wt_xram.str().c_str(),
353	x_width + y_width + l_width);
354
355	///////////// RAM ROUTER(S)
356	std::ostringstream s_ram_router_cmd;
357	s_ram_router_cmd << "ram_router_cmd_" << x_id << "_" << y_id;
358	ram_router_cmd = new DspinRouter<dspin_ram_cmd_width>(
359	s_ram_router_cmd.str().c_str(),
360	x_id, y_id, // router coordinates in mesh
361	x_width, // x field width in first flit
362	y_width, // y field width in first flit
363	4, 4); // input & output fifo depths
364
365	std::ostringstream s_ram_router_rsp;
366	s_ram_router_rsp << "ram_router_rsp_" << x_id << "_" << y_id;
367	ram_router_rsp = new DspinRouter<dspin_ram_rsp_width>(
368	s_ram_router_rsp.str().c_str(),
369	x_id, y_id, // coordinates in mesh
370	x_width, // x field width in first flit
371	y_width, // y field width in first flit
372	4, 4); // input & output fifo depths
373
374
375	////////////////////// I/O CLUSTER ONLY ///////////////////////
376	if ( is_io )
377	{
378	/////////// IO_BRIDGE
379	std::ostringstream s_iob;
380	s_iob << "iob_" << x_id << "_" << y_id;
381	iob = new VciIoBridge<vci_param_int,
382	vci_param_ext>(
383	s_iob.str().c_str(),
384	mt_ram, // EXT network maptab
385	mt_int, // INT network maptab
386	mt_iox, // IOX network maptab
387	IntTab( cluster_id, int_iobx_tgt_id ), // INT TGTID
388	IntTab( cluster_id, int_iobx_ini_id ), // INT SRCID
389	IntTab( 0 , iox_iobx_tgt_id ), // IOX TGTID
390	IntTab( 0 , iox_iobx_ini_id ), // IOX SRCID
391	16, // cache line words
392	8, // IOTLB ways
393	8, // IOTLB sets
394	debug_start_cycle,
395	iob_debug_ok );
396
397	std::ostringstream s_iob_ram_wi;
398	s_iob_ram_wi << "iob_ram_wi_" << x_id << "_" << y_id;
399	iob_ram_wi = new VciDspinInitiatorWrapper<vci_param_ext,
400	dspin_ram_cmd_width,
401	dspin_ram_rsp_width>(
402	s_iob_ram_wi.str().c_str(),
403	vci_param_int::S);
404
405	std::ostringstream s_ram_xbar_cmd;
406	s_ram_xbar_cmd << "s_ram_xbar_cmd_" << x_id << "_" << y_id;
407	ram_xbar_cmd = new DspinLocalCrossbar<dspin_ram_cmd_width>(
408	s_ram_xbar_cmd.str().c_str(), // name
409	mt_ram, // mapping table
410	x_id, y_id, // x, y
411	x_width, y_width, l_width, // x_width, y_width, l_width
412	2, 0, // local inputs, local outputs
413	2, 2, // in fifo, out fifo depths
414	true, // is cmd ?
415	false, // use routing table ?
416	false); // support broadcast ?
417
418	std::ostringstream s_ram_xbar_rsp;
419	s_ram_xbar_rsp << "s_ram_xbar_rsp_" << x_id << "_" << y_id;
420	ram_xbar_rsp = new DspinLocalCrossbar<dspin_ram_rsp_width>(
421	s_ram_xbar_rsp.str().c_str(), // name
422	mt_ram, // mapping table
423	x_id, y_id, // x, y
424	x_width, y_width, l_width, // x_width, y_width, l_width
425	0, 2, // local inputs, local outputs
426	2, 2, // in fifo, out fifo depths
427	false, // is cmd ?
428	true, // use routing table ?
429	false); // support broadcast ?
430	} // end if IO
431
432	////////////////////////////////////
433	// Connections are defined here
434	////////////////////////////////////
435
436	// on coherence network : local srcid[proc] in [0...nb_procs-1]
437	// : local srcid[memc] = nb_procs
438
439	//////////////////////// internal CMD & RSP routers
440	for(int k = 0; k < 3; k++)
441	{
442	int_router_cmd[k]->p_clk (this->p_clk);
443	int_router_cmd[k]->p_resetn (this->p_resetn);
444	int_router_cmd[k]->bind_recovery_port (signal_cfg_router_cmd[k]);
445	for (int i = 0; i < 4; i++)
446	{
447	int_router_cmd[k]->p_out[i] (this->p_dspin_int_cmd_out[i][k]);
448	int_router_cmd[k]->p_in[i] (this->p_dspin_int_cmd_in[i][k]);
449	}
450	}
451
452	for(int k = 0; k < 2; k++)
453	{
454	int_router_rsp[k]->p_clk (this->p_clk);
455	int_router_rsp[k]->p_resetn (this->p_resetn);
456	int_router_rsp[k]->bind_recovery_port (signal_cfg_router_rsp[k]);
457	for (int i = 0; i < 4; i++)
458	{
459	int_router_rsp[k]->p_out[i] (this->p_dspin_int_rsp_out[i][k]);
460	int_router_rsp[k]->p_in[i] (this->p_dspin_int_rsp_in[i][k]);
461	}
462	}
463
464	// local ports
465	int_router_cmd[0]->p_out[4] (signal_int_dspin_cmd_g2l_d);
466	int_router_cmd[1]->p_out[4] (signal_int_dspin_m2p_g2l_c);
467	int_router_cmd[2]->p_out[4] (signal_int_dspin_clack_g2l_c);
468	int_router_cmd[0]->p_in[4] (signal_int_dspin_cmd_l2g_d);
469	int_router_cmd[1]->p_in[4] (signal_int_dspin_m2p_l2g_c);
470	int_router_cmd[2]->p_in[4] (signal_int_dspin_clack_l2g_c);
471
472	int_router_rsp[0]->p_out[4] (signal_int_dspin_rsp_g2l_d);
473	int_router_rsp[1]->p_out[4] (signal_int_dspin_p2m_g2l_c);
474	int_router_rsp[0]->p_in[4] (signal_int_dspin_rsp_l2g_d);
475	int_router_rsp[1]->p_in[4] (signal_int_dspin_p2m_l2g_c);
476
477	///////////////////// CMD & RSP local crossbar
478	int_xbar_d->p_clk (this->p_clk);
479	int_xbar_d->p_resetn (this->p_resetn);
480	(*int_xbar_d->p_barrier_enable) (signal_cfg_xbar_barrier);
481	int_xbar_d->p_initiator_to_up (signal_int_vci_l2g);
482	int_xbar_d->p_target_to_up (signal_int_vci_g2l);
483
484	int_xbar_d->p_to_target[int_memc_tgt_id] (signal_int_vci_tgt_memc);
485	int_xbar_d->p_to_target[int_xicu_tgt_id] (signal_int_vci_tgt_xicu);
486	int_xbar_d->p_to_target[int_mdma_tgt_id] (signal_int_vci_tgt_mdma);
487	int_xbar_d->p_to_target[int_drom_tgt_id] (signal_int_vci_tgt_drom);
488	int_xbar_d->p_to_initiator[int_mdma_ini_id] (signal_int_vci_ini_mdma);
489	for (size_t p = 0; p < nb_procs; p++)
490	int_xbar_d->p_to_initiator[int_proc_ini_id + p] (signal_int_vci_ini_proc[p]);
491
492	if ( is_io )
493	{
494	int_xbar_d->p_to_target[int_iobx_tgt_id] (signal_int_vci_tgt_iobx);
495	int_xbar_d->p_to_initiator[int_iobx_ini_id] (signal_int_vci_ini_iobx);
496	}
497
498	int_wi_gate_d->p_clk (this->p_clk);
499	int_wi_gate_d->p_resetn (this->p_resetn);
500	int_wi_gate_d->p_vci (signal_int_vci_l2g);
501	int_wi_gate_d->p_dspin_cmd (signal_int_dspin_cmd_l2g_d);
502	int_wi_gate_d->p_dspin_rsp (signal_int_dspin_rsp_g2l_d);
503
504	int_wt_gate_d->p_clk (this->p_clk);
505	int_wt_gate_d->p_resetn (this->p_resetn);
506	int_wt_gate_d->p_vci (signal_int_vci_g2l);
507	int_wt_gate_d->p_dspin_cmd (signal_int_dspin_cmd_g2l_d);
508	int_wt_gate_d->p_dspin_rsp (signal_int_dspin_rsp_l2g_d);
509
510	////////////////////// M2P DSPIN local crossbar coherence
511	int_xbar_m2p_c->p_clk (this->p_clk);
512	int_xbar_m2p_c->p_resetn (this->p_resetn);
513	(*int_xbar_m2p_c->p_barrier_enable) (signal_cfg_xbar_barrier);
514	int_xbar_m2p_c->p_global_out (signal_int_dspin_m2p_l2g_c);
515	int_xbar_m2p_c->p_global_in (signal_int_dspin_m2p_g2l_c);
516	int_xbar_m2p_c->p_local_in[0] (signal_int_dspin_m2p_memc);
517	for (size_t p = 0; p < nb_procs; p++)
518	int_xbar_m2p_c->p_local_out[p] (signal_int_dspin_m2p_proc[p]);
519
520	////////////////////////// P2M DSPIN local crossbar coherence
521	int_xbar_p2m_c->p_clk (this->p_clk);
522	int_xbar_p2m_c->p_resetn (this->p_resetn);
523	(*int_xbar_p2m_c->p_barrier_enable) (signal_cfg_xbar_barrier);
524	int_xbar_p2m_c->p_global_out (signal_int_dspin_p2m_l2g_c);
525	int_xbar_p2m_c->p_global_in (signal_int_dspin_p2m_g2l_c);
526	int_xbar_p2m_c->p_local_out[0] (signal_int_dspin_p2m_memc);
527	for (size_t p = 0; p < nb_procs; p++)
528	int_xbar_p2m_c->p_local_in[p] (signal_int_dspin_p2m_proc[p]);
529
530	////////////////////// CLACK DSPIN local crossbar coherence
531	int_xbar_clack_c->p_clk (this->p_clk);
532	int_xbar_clack_c->p_resetn (this->p_resetn);
533	(*int_xbar_clack_c->p_barrier_enable) (signal_cfg_xbar_barrier);
534	int_xbar_clack_c->p_global_out (signal_int_dspin_clack_l2g_c);
535	int_xbar_clack_c->p_global_in (signal_int_dspin_clack_g2l_c);
536	int_xbar_clack_c->p_local_in[0] (signal_int_dspin_clack_memc);
537	for (size_t p = 0; p < nb_procs; p++)
538	int_xbar_clack_c->p_local_out[p] (signal_int_dspin_clack_proc[p]);
539
540	//////////////////////////////////// Processors
541	for (size_t p = 0; p < nb_procs; p++)
542	{
543	proc[p]->p_clk (this->p_clk);
544	proc[p]->p_resetn (this->p_resetn);
545	proc[p]->p_vci (signal_int_vci_ini_proc[p]);
546	proc[p]->p_dspin_m2p (signal_int_dspin_m2p_proc[p]);
547	proc[p]->p_dspin_p2m (signal_int_dspin_p2m_proc[p]);
548	proc[p]->p_dspin_clack (signal_int_dspin_clack_proc[p]);
549
550	for ( size_t j = 0 ; j < 6 ; j++)
551	{
552	if ( j < irq_per_proc )
553	{
554	proc[p]->p_irq[j] (signal_proc_it[irq_per_proc*p + j]);
555	}
556	else
557	{
558	proc[p]->p_irq[j] (this->p_false);
559	}
560	}
561	}
562
563	///////////////////////////////////// XICU
564	xicu->p_clk (this->p_clk);
565	xicu->p_resetn (this->p_resetn);
566	xicu->p_vci (signal_int_vci_tgt_xicu);
567	for ( size_t i=0 ; i < xcu_nb_out ; i++)
568	{
569	xicu->p_irq[i] (signal_proc_it[i]);
570	}
571	for ( size_t i=0 ; i < xcu_nb_hwi ; i++)
572	{
573	if ( i == 0 ) xicu->p_hwi[i] (signal_irq_memc);
574	else if ( i <= nb_dmas ) xicu->p_hwi[i] (signal_irq_mdma[i-1]);
575	else xicu->p_hwi[i] (this->p_false);
576	}
577	xicu->p_cfg[0] (signal_cfg_router_cmd[0]); // CMD
578	xicu->p_cfg[1] (signal_cfg_router_rsp[0]); // RSP
579	xicu->p_cfg[2] (signal_cfg_router_cmd[1]); // M2P
580	xicu->p_cfg[3] (signal_cfg_router_rsp[1]); // P2M
581	xicu->p_cfg[4] (signal_cfg_router_cmd[2]); // CLACK
582	xicu->p_cfg[5] (signal_cfg_xbar_barrier); // CLACK
583
584	///////////////////////////////////// MEMC
585	memc->p_clk (this->p_clk);
586	memc->p_resetn (this->p_resetn);
587	memc->p_vci_ixr (signal_ram_vci_ini_memc);
588	memc->p_vci_tgt (signal_int_vci_tgt_memc);
589	memc->p_dspin_p2m (signal_int_dspin_p2m_memc);
590	memc->p_dspin_m2p (signal_int_dspin_m2p_memc);
591	memc->p_dspin_clack (signal_int_dspin_clack_memc);
592	memc->p_irq (signal_irq_memc);
593
594	// wrapper to RAM network
595	memc_ram_wi->p_clk (this->p_clk);
596	memc_ram_wi->p_resetn (this->p_resetn);
597	memc_ram_wi->p_dspin_cmd (signal_ram_dspin_cmd_memc_i);
598	memc_ram_wi->p_dspin_rsp (signal_ram_dspin_rsp_memc_i);
599	memc_ram_wi->p_vci (signal_ram_vci_ini_memc);
600
601	//////////////////////////////////// XRAM
602	xram->p_clk (this->p_clk);
603	xram->p_resetn (this->p_resetn);
604	xram->p_vci (signal_ram_vci_tgt_xram);
605
606	// wrapper to RAM network
607	xram_ram_wt->p_clk (this->p_clk);
608	xram_ram_wt->p_resetn (this->p_resetn);
609	xram_ram_wt->p_dspin_cmd (signal_ram_dspin_cmd_xram_t);
610	xram_ram_wt->p_dspin_rsp (signal_ram_dspin_rsp_xram_t);
611	xram_ram_wt->p_vci (signal_ram_vci_tgt_xram);
612
613	/////////////////////////////////// MDMA
614	mdma->p_clk (this->p_clk);
615	mdma->p_resetn (this->p_resetn);
616	mdma->p_vci_target (signal_int_vci_tgt_mdma);
617	mdma->p_vci_initiator (signal_int_vci_ini_mdma);
618	for (size_t i=0 ; i<nb_dmas ; i++)
619	mdma->p_irq[i] (signal_irq_mdma[i]);
620
621	/////////////////////////////////// DROM
622	drom->p_clk (this->p_clk);
623	drom->p_resetn (this->p_resetn);
624	drom->p_vci (signal_int_vci_tgt_drom);
625
626	//////////////////////////// RAM network CMD & RSP routers
627	ram_router_cmd->p_clk (this->p_clk);
628	ram_router_cmd->p_resetn (this->p_resetn);
629	ram_router_rsp->p_clk (this->p_clk);
630	ram_router_rsp->p_resetn (this->p_resetn);
631	for( size_t n=0 ; n<4 ; n++)
632	{
633	ram_router_cmd->p_out[n] (this->p_dspin_ram_cmd_out[n]);
634	ram_router_cmd->p_in[n] (this->p_dspin_ram_cmd_in[n]);
635	ram_router_rsp->p_out[n] (this->p_dspin_ram_rsp_out[n]);
636	ram_router_rsp->p_in[n] (this->p_dspin_ram_rsp_in[n]);
637	}
638
639	ram_router_cmd->p_out[4] (signal_ram_dspin_cmd_xram_t);
640	ram_router_rsp->p_in[4] (signal_ram_dspin_rsp_xram_t);
641
642	if ( is_io )
643	{
644	ram_router_cmd->p_in[4] (signal_ram_dspin_cmd_xbar);
645	ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_xbar);
646	}
647	else
648	{
649	ram_router_cmd->p_in[4] (signal_ram_dspin_cmd_memc_i);
650	ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_memc_i);
651	}
652
653	///////////////////////// IOB exists only in cluster_iob0 & cluster_iob1.
654	if ( is_io )
655	{
656	// IO bridge
657	iob->p_clk (this->p_clk);
658	iob->p_resetn (this->p_resetn);
659	iob->p_vci_ini_iox (*(this->p_vci_iob_iox_ini));
660	iob->p_vci_tgt_iox (*(this->p_vci_iob_iox_tgt));
661	iob->p_vci_tgt_int (signal_int_vci_tgt_iobx);
662	iob->p_vci_ini_int (signal_int_vci_ini_iobx);
663	iob->p_vci_ini_ram (signal_ram_vci_ini_iobx);
664
665	// initiator wrapper to RAM network
666	iob_ram_wi->p_clk (this->p_clk);
667	iob_ram_wi->p_resetn (this->p_resetn);
668	iob_ram_wi->p_dspin_cmd (signal_ram_dspin_cmd_iob_i);
669	iob_ram_wi->p_dspin_rsp (signal_ram_dspin_rsp_iob_i);
670	iob_ram_wi->p_vci (signal_ram_vci_ini_iobx);
671
672	// crossbar between MEMC and IOB to RAM network
673	ram_xbar_cmd->p_clk (this->p_clk);
674	ram_xbar_cmd->p_resetn (this->p_resetn);
675	ram_xbar_cmd->p_global_out (signal_ram_dspin_cmd_xbar);
676	ram_xbar_cmd->p_global_in (signal_ram_dspin_cmd_false);
677	ram_xbar_cmd->p_local_in[ram_memc_ini_id] (signal_ram_dspin_cmd_memc_i);
678	ram_xbar_cmd->p_local_in[ram_iobx_ini_id] (signal_ram_dspin_cmd_iob_i);
679
680	ram_xbar_rsp->p_clk (this->p_clk);
681	ram_xbar_rsp->p_resetn (this->p_resetn);
682	ram_xbar_rsp->p_global_out (signal_ram_dspin_rsp_false);
683	ram_xbar_rsp->p_global_in (signal_ram_dspin_rsp_xbar);
684	ram_xbar_rsp->p_local_out[ram_memc_ini_id] (signal_ram_dspin_rsp_memc_i);
685	ram_xbar_rsp->p_local_out[ram_iobx_ini_id] (signal_ram_dspin_rsp_iob_i);
686	}
687
688	SC_METHOD(init);
689
690	} // end constructor
691
692	tmpl(void)::init()
693	{
694	signal_ram_dspin_cmd_false.write = false;
695	signal_ram_dspin_rsp_false.read = true;
696	} // end init
697
698	tmpl(/**/)::~TsarIobCluster()
699	{
700	for (int k = 0; k < 3; k++)
701	{
702	delete int_router_cmd[k];
703	}
704	delete [] int_router_cmd;
705
706	for (int k = 0; k < 2; k++)
707	{
708	delete int_router_rsp[k];
709	}
710	delete [] int_router_rsp;
711	}
712
713	}}
714
715
716	// Local Variables:
717	// tab-width: 4
718	// c-basic-offset: 4
719	// c-file-offsets:((innamespace . 0)(inline-open . 0))
720	// indent-tabs-mode: nil
721	// End:
722
723	// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
724

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source: branches/reconfiguration/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/src/tsar_iob_cluster.cpp @ 1001

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