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source: branches/reconfiguration/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/src/tsar_iob_cluster.cpp @ 806

Last change on this file since 806 was 806, checked in by cfuguet, 10 years ago

reconf/tsar_generic_iob: Using the new P_WIDTH constant

This constant is used in the clusters to compute the procesor id which now is: (((x << Y_WIDTH) + y) << P_WIDTH) + lpid

Introducing the p_width constant in the arch.py files

File size: 33.2 KB

Line
1	//////////////////////////////////////////////////////////////////////////////
2	// File: tsar_iob_cluster.cpp
3	// Author: Alain Greiner
4	// Copyright: UPMC/LIP6
5	// Date : april 2013
6	// This program is released under the GNU public license
7	//////////////////////////////////////////////////////////////////////////////
8	// Cluster(0,0) & Cluster(x_size-1,y_size-1) contains the IOB0 & IOB1 components.
9	// These two clusters contain 6 extra components:
10	// - 1 vci_io_bridge (connected to the 3 networks.
11	// - 3 vci_dspin_wrapper for the IOB.
12	// - 2 dspin_local_crossbar for commands and responses.
13	//////////////////////////////////////////////////////////////////////////////
14
15	#include "../include/tsar_iob_cluster.h"
16
17	#define tmpl(x) \
18	template<typename vci_param_int , typename vci_param_ext,\
19	size_t dspin_int_cmd_width, size_t dspin_int_rsp_width,\
20	size_t dspin_ram_cmd_width, size_t dspin_ram_rsp_width>\
21	x TsarIobCluster<\
22	vci_param_int , vci_param_ext,\
23	dspin_int_cmd_width, dspin_int_rsp_width,\
24	dspin_ram_cmd_width, dspin_ram_rsp_width>
25
26	namespace soclib { namespace caba {
27
28	//////////////////////////////////////////////////////////////////////////
29	// Constructor
30	//////////////////////////////////////////////////////////////////////////
31	tmpl(/**/)::TsarIobCluster(
32	sc_module_name insname,
33	size_t nb_procs,
34	size_t nb_dmas,
35	size_t x_id,
36	size_t y_id,
37	size_t x_size,
38	size_t y_size,
39
40	size_t p_width,
41
42	const soclib::common::MappingTable &mt_int,
43	const soclib::common::MappingTable &mt_ram,
44	const soclib::common::MappingTable &mt_iox,
45
46	size_t x_width,
47	size_t y_width,
48	size_t l_width,
49
50	size_t int_memc_tgt_id, // local index
51	size_t int_xicu_tgt_id, // local index
52	size_t int_mdma_tgt_id, // local index
53	size_t int_brom_tgt_id, // local index
54	size_t int_iobx_tgt_id, // local index
55
56	size_t int_proc_ini_id, // local index
57	size_t int_mdma_ini_id, // local index
58	size_t int_iobx_ini_id, // local index
59
60	size_t ram_xram_tgt_id, // local index
61	size_t ram_memc_ini_id, // local index
62	size_t ram_iobx_ini_id, // local index
63
64	bool is_io, // is IO cluster (IOB)?
65	size_t iox_iobx_tgt_id, // local_index
66	size_t iox_iobx_ini_id, // local index
67
68	size_t memc_ways,
69	size_t memc_sets,
70	size_t l1_i_ways,
71	size_t l1_i_sets,
72	size_t l1_d_ways,
73	size_t l1_d_sets,
74	size_t xram_latency,
75	size_t xcu_nb_inputs,
76
77	bool distboot,
78
79	const Loader &loader,
80
81	uint32_t frozen_cycles,
82	uint32_t debug_start_cycle,
83	bool memc_debug_ok,
84	bool proc_debug_ok,
85	bool iob_debug_ok ) :
86
87	// constructor initialization list
88
89	soclib::caba::BaseModule(insname),
90	p_clk("clk"),
91	p_resetn("resetn")
92	{
93
94	assert( (x_id < x_size) and (y_id < y_size) and "Illegal cluster coordinates");
95
96	size_t cluster_id = (x_id << x_width) \| y_id;
97
98	// Vectors of DSPIN ports for inter-cluster communications
99	p_dspin_int_cmd_in = alloc_elems<DspinInput<dspin_int_cmd_width> >("p_int_cmd_in", 4, 3);
100	p_dspin_int_cmd_out = alloc_elems<DspinOutput<dspin_int_cmd_width> >("p_int_cmd_out", 4, 3);
101	p_dspin_int_rsp_in = alloc_elems<DspinInput<dspin_int_rsp_width> >("p_int_rsp_in", 4, 2);
102	p_dspin_int_rsp_out = alloc_elems<DspinOutput<dspin_int_rsp_width> >("p_int_rsp_out", 4, 2);
103
104	p_dspin_ram_cmd_in = alloc_elems<DspinInput<dspin_ram_cmd_width> >("p_ext_cmd_in", 4);
105	p_dspin_ram_cmd_out = alloc_elems<DspinOutput<dspin_ram_cmd_width> >("p_ext_cmd_out", 4);
106	p_dspin_ram_rsp_in = alloc_elems<DspinInput<dspin_ram_rsp_width> >("p_ext_rsp_in", 4);
107	p_dspin_ram_rsp_out = alloc_elems<DspinOutput<dspin_ram_rsp_width> >("p_ext_rsp_out", 4);
108
109	// VCI ports from IOB to IOX network (only in IO clusters)
110	if (is_io)
111	{
112	p_vci_iob_iox_ini = new soclib::caba::VciInitiator<vci_param_ext>;
113	p_vci_iob_iox_tgt = new soclib::caba::VciTarget<vci_param_ext>;
114	}
115
116	/////////////////////////////////////////////////////////////////////////////
117	// Hardware components
118	/////////////////////////////////////////////////////////////////////////////
119
120	//////////// PROCS
121	for (size_t p = 0; p < nb_procs; p++)
122	{
123	std::ostringstream s_proc;
124	s_proc << "proc_" << x_id << "_" << y_id << "_" << p;
125	proc[p] = new VciCcVCacheWrapper<vci_param_int,
126	dspin_int_cmd_width,
127	dspin_int_rsp_width,
128	GdbServer<Mips32ElIss> >(
129	s_proc.str().c_str(),
130	(cluster_id << p_width) \| p, // GLOBAL PROC_ID
131	mt_int, // Mapping Table INT network
132	IntTab(cluster_id,p), // SRCID
133	(cluster_id << l_width) \| p, // CC_GLOBAL_ID
134	8, // ITLB ways
135	8, // ITLB sets
136	8, // DTLB ways
137	8, // DTLB sets
138	l1_i_ways, l1_i_sets, 16, // ICACHE size
139	l1_d_ways, l1_d_sets, 16, // DCACHE size
140	4, // WBUF nlines
141	4, // WBUF nwords
142	x_width, // number of bits for x coordinate
143	y_width, // number of bits for y coordinate
144	frozen_cycles, // max frozen cycles
145	debug_start_cycle,
146	proc_debug_ok);
147
148	// initialize physical address extension with cluster ID when using
149	// distributed boot
150	if (distboot)
151	{
152	proc[p]->set_dcache_paddr_ext_reset(cluster_id);
153	proc[p]->set_icache_paddr_ext_reset(cluster_id);
154	}
155	}
156
157	/////////// MEMC
158	std::ostringstream s_memc;
159	s_memc << "memc_" << x_id << "_" << y_id;
160	memc = new VciMemCache<vci_param_int,
161	vci_param_ext,
162	dspin_int_rsp_width,
163	dspin_int_cmd_width>(
164	s_memc.str().c_str(),
165	mt_int, // Mapping Table INT network
166	mt_ram, // Mapping Table RAM network
167	IntTab(cluster_id, ram_memc_ini_id), // SRCID RAM network
168	IntTab(cluster_id, int_memc_tgt_id), // TGTID INT network
169	x_width, // number of bits for x coordinate
170	y_width, // number of bits for y coordinate
171	memc_ways, memc_sets, 16, // CACHE SIZE
172	3, // MAX NUMBER OF COPIES
173	4096, // HEAP SIZE
174	8, // TRANSACTION TABLE DEPTH
175	8, // UPDATE TABLE DEPTH
176	8, // INVALIDATE TABLE DEPTH
177	debug_start_cycle,
178	memc_debug_ok );
179
180	std::ostringstream s_wi_memc;
181	s_wi_memc << "memc_wi_" << x_id << "_" << y_id;
182	memc_ram_wi = new VciDspinInitiatorWrapper<vci_param_ext,
183	dspin_ram_cmd_width,
184	dspin_ram_rsp_width>(
185	s_wi_memc.str().c_str(),
186	x_width + y_width + l_width);
187
188	/////////// XICU
189	std::ostringstream s_xicu;
190	s_xicu << "xicu_" << x_id << "_" << y_id;
191	xicu = new VciXicu<vci_param_int>(
192	s_xicu.str().c_str(),
193	mt_int, // mapping table INT network
194	IntTab(cluster_id, int_xicu_tgt_id), // TGTID direct space
195	xcu_nb_inputs, // number of timer IRQs
196	xcu_nb_inputs, // number of hard IRQs
197	xcu_nb_inputs, // number of soft IRQs
198	16); // number of output IRQs
199
200	//////////// MDMA
201	std::ostringstream s_mdma;
202	s_mdma << "mdma_" << x_id << "_" << y_id;
203	mdma = new VciMultiDma<vci_param_int>(
204	s_mdma.str().c_str(),
205	mt_int,
206	IntTab(cluster_id, nb_procs), // SRCID
207	IntTab(cluster_id, int_mdma_tgt_id), // TGTID
208	64, // burst size
209	nb_dmas); // number of IRQs
210
211	/////////// DISTRIBUTED BOOT ROM
212	std::ostringstream s_brom;
213	s_brom << "brom_" << x_id << "_" << y_id;
214	brom = new VciSimpleRom<vci_param_int>(
215	s_brom.str().c_str(),
216	IntTab(cluster_id, int_brom_tgt_id),
217	mt_int,
218	loader,
219	x_width + y_width); // msb drop bits
220
221	/////////// Direct LOCAL_XBAR(S)
222	size_t nb_direct_initiators = is_io ? nb_procs + 2 : nb_procs + 1;
223	size_t nb_direct_targets = is_io ? 5 : 4;
224
225	std::ostringstream s_int_xbar_d;
226	s_int_xbar_d << "int_xbar_cmd_d_" << x_id << "_" << y_id;
227	int_xbar_d = new VciLocalCrossbar<vci_param_int>(
228	s_int_xbar_d.str().c_str(),
229	mt_int, // mapping table
230	cluster_id, // cluster id
231	nb_direct_initiators, // number of local initiators
232	nb_direct_targets, // number of local targets
233	0 ); // default target
234
235	std::ostringstream s_int_dspin_ini_wrapper_gate_d;
236	s_int_dspin_ini_wrapper_gate_d << "int_dspin_ini_wrapper_gate_d_"
237	<< x_id << "_" << y_id;
238	int_wi_gate_d = new VciDspinInitiatorWrapper<vci_param_int,
239	dspin_int_cmd_width,
240	dspin_int_rsp_width>(
241	s_int_dspin_ini_wrapper_gate_d.str().c_str(),
242	x_width + y_width + l_width);
243
244	std::ostringstream s_int_dspin_tgt_wrapper_gate_d;
245	s_int_dspin_tgt_wrapper_gate_d << "int_dspin_tgt_wrapper_gate_d_"
246	<< x_id << "_" << y_id;
247	int_wt_gate_d = new VciDspinTargetWrapper<vci_param_int,
248	dspin_int_cmd_width,
249	dspin_int_rsp_width>(
250	s_int_dspin_tgt_wrapper_gate_d.str().c_str(),
251	x_width + y_width + l_width);
252
253	//////////// Coherence LOCAL_XBAR(S)
254	std::ostringstream s_int_xbar_m2p_c;
255	s_int_xbar_m2p_c << "int_xbar_m2p_c_" << x_id << "_" << y_id;
256	int_xbar_m2p_c = new DspinLocalCrossbar<dspin_int_cmd_width>(
257	s_int_xbar_m2p_c.str().c_str(),
258	mt_int, // mapping table
259	x_id, y_id, // cluster coordinates
260	x_width, y_width, l_width, // several dests
261	1, // number of local sources
262	nb_procs, // number of local dests
263	2, 2, // fifo depths
264	true, // pseudo CMD
265	false, // no routing table
266	true ); // broacast
267
268	std::ostringstream s_int_xbar_p2m_c;
269	s_int_xbar_p2m_c << "int_xbar_p2m_c_" << x_id << "_" << y_id;
270	int_xbar_p2m_c = new DspinLocalCrossbar<dspin_int_rsp_width>(
271	s_int_xbar_p2m_c.str().c_str(),
272	mt_int, // mapping table
273	x_id, y_id, // cluster coordinates
274	x_width, y_width, 0, // only one dest
275	nb_procs, // number of local sources
276	1, // number of local dests
277	2, 2, // fifo depths
278	false, // pseudo RSP
279	false, // no routing table
280	false ); // no broacast
281
282	std::ostringstream s_int_xbar_clack_c;
283	s_int_xbar_clack_c << "int_xbar_clack_c_" << x_id << "_" << y_id;
284	int_xbar_clack_c = new DspinLocalCrossbar<dspin_int_cmd_width>(
285	s_int_xbar_clack_c.str().c_str(),
286	mt_int, // mapping table
287	x_id, y_id, // cluster coordinates
288	x_width, y_width, l_width,
289	1, // number of local sources
290	nb_procs, // number of local targets
291	1, 1, // fifo depths
292	true, // CMD
293	false, // no routing table
294	false); // broadcast
295
296	////////////// INT ROUTER(S)
297	std::ostringstream s_int_router_cmd;
298	s_int_router_cmd << "router_cmd_" << x_id << "_" << y_id;
299	int_router_cmd = new VirtualDspinRouter<dspin_int_cmd_width>(
300	s_int_router_cmd.str().c_str(),
301	x_id,y_id, // coordinate in the mesh
302	x_width, y_width, // x & y fields width
303	3, // nb virtual channels
304	4, 4); // input & output fifo depths
305
306	std::ostringstream s_int_router_rsp;
307	s_int_router_rsp << "router_rsp_" << x_id << "_" << y_id;
308	int_router_rsp = new VirtualDspinRouter<dspin_int_rsp_width>(
309	s_int_router_rsp.str().c_str(),
310	x_id,y_id, // router coordinates in mesh
311	x_width, y_width, // x & y fields width
312	2, // nb virtual channels
313	4, 4); // input & output fifo depths
314
315	////////////// XRAM
316	std::ostringstream s_xram;
317	s_xram << "xram_" << x_id << "_" << y_id;
318	xram = new VciSimpleRam<vci_param_ext>(
319	s_xram.str().c_str(),
320	IntTab(cluster_id, ram_xram_tgt_id),
321	mt_ram,
322	loader,
323	xram_latency);
324
325	std::ostringstream s_wt_xram;
326	s_wt_xram << "xram_wt_" << x_id << "_" << y_id;
327	xram_ram_wt = new VciDspinTargetWrapper<vci_param_ext,
328	dspin_ram_cmd_width,
329	dspin_ram_rsp_width>(
330	s_wt_xram.str().c_str(),
331	x_width + y_width + l_width);
332
333	///////////// RAM ROUTER(S)
334	std::ostringstream s_ram_router_cmd;
335	s_ram_router_cmd << "ram_router_cmd_" << x_id << "_" << y_id;
336	ram_router_cmd = new DspinRouter<dspin_ram_cmd_width>(
337	s_ram_router_cmd.str().c_str(),
338	x_id, y_id, // router coordinates in mesh
339	x_width, // x field width in first flit
340	y_width, // y field width in first flit
341	4, 4); // input & output fifo depths
342
343	std::ostringstream s_ram_router_rsp;
344	s_ram_router_rsp << "ram_router_rsp_" << x_id << "_" << y_id;
345	ram_router_rsp = new DspinRouter<dspin_ram_rsp_width>(
346	s_ram_router_rsp.str().c_str(),
347	x_id, y_id, // coordinates in mesh
348	x_width, // x field width in first flit
349	y_width, // y field width in first flit
350	4, 4); // input & output fifo depths
351
352
353	////////////////////// I/O CLUSTER ONLY ///////////////////////
354	if ( is_io )
355	{
356	/////////// IO_BRIDGE
357	std::ostringstream s_iob;
358	s_iob << "iob_" << x_id << "_" << y_id;
359	iob = new VciIoBridge<vci_param_int,
360	vci_param_ext>(
361	s_iob.str().c_str(),
362	mt_ram, // EXT network maptab
363	mt_int, // INT network maptab
364	mt_iox, // IOX network maptab
365	IntTab( cluster_id, int_iobx_tgt_id ), // INT TGTID
366	IntTab( cluster_id, int_iobx_ini_id ), // INT SRCID
367	IntTab( 0 , iox_iobx_tgt_id ), // IOX TGTID
368	IntTab( 0 , iox_iobx_ini_id ), // IOX SRCID
369	16, // cache line words
370	8, // IOTLB ways
371	8, // IOTLB sets
372	debug_start_cycle,
373	iob_debug_ok );
374
375	std::ostringstream s_iob_ram_wi;
376	s_iob_ram_wi << "iob_ram_wi_" << x_id << "_" << y_id;
377	iob_ram_wi = new VciDspinInitiatorWrapper<vci_param_ext,
378	dspin_ram_cmd_width,
379	dspin_ram_rsp_width>(
380	s_iob_ram_wi.str().c_str(),
381	vci_param_int::S);
382
383	std::ostringstream s_ram_xbar_cmd;
384	s_ram_xbar_cmd << "s_ram_xbar_cmd_" << x_id << "_" << y_id;
385	ram_xbar_cmd = new DspinLocalCrossbar<dspin_ram_cmd_width>(
386	s_ram_xbar_cmd.str().c_str(), // name
387	mt_ram, // mapping table
388	x_id, y_id, // x, y
389	x_width, y_width, l_width, // x_width, y_width, l_width
390	2, 0, // local inputs, local outputs
391	2, 2, // in fifo, out fifo depths
392	true, // is cmd ?
393	false, // use routing table ?
394	false); // support broadcast ?
395
396	std::ostringstream s_ram_xbar_rsp;
397	s_ram_xbar_rsp << "s_ram_xbar_rsp_" << x_id << "_" << y_id;
398	ram_xbar_rsp = new DspinLocalCrossbar<dspin_ram_rsp_width>(
399	s_ram_xbar_rsp.str().c_str(), // name
400	mt_ram, // mapping table
401	x_id, y_id, // x, y
402	x_width, y_width, l_width, // x_width, y_width, l_width
403	0, 2, // local inputs, local outputs
404	2, 2, // in fifo, out fifo depths
405	false, // is cmd ?
406	true, // use routing table ?
407	false); // support broadcast ?
408	} // end if IO
409
410	////////////////////////////////////
411	// Connections are defined here
412	////////////////////////////////////
413
414	// on coherence network : local srcid[proc] in [0...nb_procs-1]
415	// : local srcid[memc] = nb_procs
416
417	//////////////////////// internal CMD & RSP routers
418	int_router_cmd->p_clk (this->p_clk);
419	int_router_cmd->p_resetn (this->p_resetn);
420	int_router_rsp->p_clk (this->p_clk);
421	int_router_rsp->p_resetn (this->p_resetn);
422
423	for (int i = 0; i < 4; i++)
424	{
425	for(int k = 0; k < 3; k++)
426	{
427	int_router_cmd->p_out[i][k] (this->p_dspin_int_cmd_out[i][k]);
428	int_router_cmd->p_in[i][k] (this->p_dspin_int_cmd_in[i][k]);
429	}
430
431	for(int k = 0; k < 2; k++)
432	{
433	int_router_rsp->p_out[i][k] (this->p_dspin_int_rsp_out[i][k]);
434	int_router_rsp->p_in[i][k] (this->p_dspin_int_rsp_in[i][k]);
435	}
436	}
437
438	// local ports
439	int_router_cmd->p_out[4][0] (signal_int_dspin_cmd_g2l_d);
440	int_router_cmd->p_out[4][1] (signal_int_dspin_m2p_g2l_c);
441	int_router_cmd->p_out[4][2] (signal_int_dspin_clack_g2l_c);
442	int_router_cmd->p_in[4][0] (signal_int_dspin_cmd_l2g_d);
443	int_router_cmd->p_in[4][1] (signal_int_dspin_m2p_l2g_c);
444	int_router_cmd->p_in[4][2] (signal_int_dspin_clack_l2g_c);
445
446	int_router_rsp->p_out[4][0] (signal_int_dspin_rsp_g2l_d);
447	int_router_rsp->p_out[4][1] (signal_int_dspin_p2m_g2l_c);
448	int_router_rsp->p_in[4][0] (signal_int_dspin_rsp_l2g_d);
449	int_router_rsp->p_in[4][1] (signal_int_dspin_p2m_l2g_c);
450
451	///////////////////// CMD DSPIN local crossbar direct
452	int_xbar_d->p_clk (this->p_clk);
453	int_xbar_d->p_resetn (this->p_resetn);
454	int_xbar_d->p_initiator_to_up (signal_int_vci_l2g);
455	int_xbar_d->p_target_to_up (signal_int_vci_g2l);
456
457	int_xbar_d->p_to_target[int_memc_tgt_id] (signal_int_vci_tgt_memc);
458	int_xbar_d->p_to_target[int_xicu_tgt_id] (signal_int_vci_tgt_xicu);
459	int_xbar_d->p_to_target[int_mdma_tgt_id] (signal_int_vci_tgt_mdma);
460	int_xbar_d->p_to_target[int_brom_tgt_id] (signal_int_vci_tgt_brom);
461	int_xbar_d->p_to_initiator[int_mdma_ini_id] (signal_int_vci_ini_mdma);
462	for (size_t p = 0; p < nb_procs; p++)
463	int_xbar_d->p_to_initiator[int_proc_ini_id + p] (signal_int_vci_ini_proc[p]);
464
465	if ( is_io )
466	{
467	int_xbar_d->p_to_target[int_iobx_tgt_id] (signal_int_vci_tgt_iobx);
468	int_xbar_d->p_to_initiator[int_iobx_ini_id] (signal_int_vci_ini_iobx);
469	}
470
471	int_wi_gate_d->p_clk (this->p_clk);
472	int_wi_gate_d->p_resetn (this->p_resetn);
473	int_wi_gate_d->p_vci (signal_int_vci_l2g);
474	int_wi_gate_d->p_dspin_cmd (signal_int_dspin_cmd_l2g_d);
475	int_wi_gate_d->p_dspin_rsp (signal_int_dspin_rsp_g2l_d);
476
477	int_wt_gate_d->p_clk (this->p_clk);
478	int_wt_gate_d->p_resetn (this->p_resetn);
479	int_wt_gate_d->p_vci (signal_int_vci_g2l);
480	int_wt_gate_d->p_dspin_cmd (signal_int_dspin_cmd_g2l_d);
481	int_wt_gate_d->p_dspin_rsp (signal_int_dspin_rsp_l2g_d);
482
483	////////////////////// M2P DSPIN local crossbar coherence
484	int_xbar_m2p_c->p_clk (this->p_clk);
485	int_xbar_m2p_c->p_resetn (this->p_resetn);
486	int_xbar_m2p_c->p_global_out (signal_int_dspin_m2p_l2g_c);
487	int_xbar_m2p_c->p_global_in (signal_int_dspin_m2p_g2l_c);
488	int_xbar_m2p_c->p_local_in[0] (signal_int_dspin_m2p_memc);
489	for (size_t p = 0; p < nb_procs; p++)
490	int_xbar_m2p_c->p_local_out[p] (signal_int_dspin_m2p_proc[p]);
491
492	////////////////////////// P2M DSPIN local crossbar coherence
493	int_xbar_p2m_c->p_clk (this->p_clk);
494	int_xbar_p2m_c->p_resetn (this->p_resetn);
495	int_xbar_p2m_c->p_global_out (signal_int_dspin_p2m_l2g_c);
496	int_xbar_p2m_c->p_global_in (signal_int_dspin_p2m_g2l_c);
497	int_xbar_p2m_c->p_local_out[0] (signal_int_dspin_p2m_memc);
498	for (size_t p = 0; p < nb_procs; p++)
499	int_xbar_p2m_c->p_local_in[p] (signal_int_dspin_p2m_proc[p]);
500
501	////////////////////// CLACK DSPIN local crossbar coherence
502	int_xbar_clack_c->p_clk (this->p_clk);
503	int_xbar_clack_c->p_resetn (this->p_resetn);
504	int_xbar_clack_c->p_global_out (signal_int_dspin_clack_l2g_c);
505	int_xbar_clack_c->p_global_in (signal_int_dspin_clack_g2l_c);
506	int_xbar_clack_c->p_local_in[0] (signal_int_dspin_clack_memc);
507	for (size_t p = 0; p < nb_procs; p++)
508	int_xbar_clack_c->p_local_out[p] (signal_int_dspin_clack_proc[p]);
509
510	//////////////////////////////////// Processors
511	for (size_t p = 0; p < nb_procs; p++)
512	{
513	proc[p]->p_clk (this->p_clk);
514	proc[p]->p_resetn (this->p_resetn);
515	proc[p]->p_vci (signal_int_vci_ini_proc[p]);
516	proc[p]->p_dspin_m2p (signal_int_dspin_m2p_proc[p]);
517	proc[p]->p_dspin_p2m (signal_int_dspin_p2m_proc[p]);
518	proc[p]->p_dspin_clack (signal_int_dspin_clack_proc[p]);
519
520	for ( size_t j = 0 ; j < 6 ; j++)
521	{
522	if ( j < 4 ) proc[p]->p_irq[j] (signal_proc_it[4*p + j]);
523	else proc[p]->p_irq[j] (signal_false);
524	}
525	}
526
527	///////////////////////////////////// XICU
528	xicu->p_clk (this->p_clk);
529	xicu->p_resetn (this->p_resetn);
530	xicu->p_vci (signal_int_vci_tgt_xicu);
531	for ( size_t i=0 ; i < 16 ; i++)
532	{
533	xicu->p_irq[i] (signal_proc_it[i]);
534	}
535	for ( size_t i=0 ; i < xcu_nb_inputs ; i++)
536	{
537	if ( i == 0 ) xicu->p_hwi[i] (signal_irq_memc);
538	else if ( i <= nb_dmas ) xicu->p_hwi[i] (signal_irq_mdma[i-1]);
539	else xicu->p_hwi[i] (signal_false);
540	}
541
542	///////////////////////////////////// MEMC
543	memc->p_clk (this->p_clk);
544	memc->p_resetn (this->p_resetn);
545	memc->p_vci_ixr (signal_ram_vci_ini_memc);
546	memc->p_vci_tgt (signal_int_vci_tgt_memc);
547	memc->p_dspin_p2m (signal_int_dspin_p2m_memc);
548	memc->p_dspin_m2p (signal_int_dspin_m2p_memc);
549	memc->p_dspin_clack (signal_int_dspin_clack_memc);
550	memc->p_irq (signal_irq_memc);
551
552	// wrapper to RAM network
553	memc_ram_wi->p_clk (this->p_clk);
554	memc_ram_wi->p_resetn (this->p_resetn);
555	memc_ram_wi->p_dspin_cmd (signal_ram_dspin_cmd_memc_i);
556	memc_ram_wi->p_dspin_rsp (signal_ram_dspin_rsp_memc_i);
557	memc_ram_wi->p_vci (signal_ram_vci_ini_memc);
558
559	//////////////////////////////////// XRAM
560	xram->p_clk (this->p_clk);
561	xram->p_resetn (this->p_resetn);
562	xram->p_vci (signal_ram_vci_tgt_xram);
563
564	// wrapper to RAM network
565	xram_ram_wt->p_clk (this->p_clk);
566	xram_ram_wt->p_resetn (this->p_resetn);
567	xram_ram_wt->p_dspin_cmd (signal_ram_dspin_cmd_xram_t);
568	xram_ram_wt->p_dspin_rsp (signal_ram_dspin_rsp_xram_t);
569	xram_ram_wt->p_vci (signal_ram_vci_tgt_xram);
570
571	/////////////////////////////////// MDMA
572	mdma->p_clk (this->p_clk);
573	mdma->p_resetn (this->p_resetn);
574	mdma->p_vci_target (signal_int_vci_tgt_mdma);
575	mdma->p_vci_initiator (signal_int_vci_ini_mdma);
576	for (size_t i=0 ; i<nb_dmas ; i++)
577	mdma->p_irq[i] (signal_irq_mdma[i]);
578
579	/////////////////////////////////// BROM
580	brom->p_clk (this->p_clk);
581	brom->p_resetn (this->p_resetn);
582	brom->p_vci (signal_int_vci_tgt_brom);
583
584	//////////////////////////// RAM network CMD & RSP routers
585	ram_router_cmd->p_clk (this->p_clk);
586	ram_router_cmd->p_resetn (this->p_resetn);
587	ram_router_rsp->p_clk (this->p_clk);
588	ram_router_rsp->p_resetn (this->p_resetn);
589	for( size_t n=0 ; n<4 ; n++)
590	{
591	ram_router_cmd->p_out[n] (this->p_dspin_ram_cmd_out[n]);
592	ram_router_cmd->p_in[n] (this->p_dspin_ram_cmd_in[n]);
593	ram_router_rsp->p_out[n] (this->p_dspin_ram_rsp_out[n]);
594	ram_router_rsp->p_in[n] (this->p_dspin_ram_rsp_in[n]);
595	}
596
597	ram_router_cmd->p_out[4] (signal_ram_dspin_cmd_xram_t);
598	ram_router_rsp->p_in[4] (signal_ram_dspin_rsp_xram_t);
599
600	if ( is_io )
601	{
602	ram_router_cmd->p_in[4] (signal_ram_dspin_cmd_xbar);
603	ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_xbar);
604	}
605	else
606	{
607	ram_router_cmd->p_in[4] (signal_ram_dspin_cmd_memc_i);
608	ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_memc_i);
609	}
610
611	///////////////////////// IOB exists only in cluster_iob0 & cluster_iob1.
612	if ( is_io )
613	{
614	// IO bridge
615	iob->p_clk (this->p_clk);
616	iob->p_resetn (this->p_resetn);
617	iob->p_vci_ini_iox (*(this->p_vci_iob_iox_ini));
618	iob->p_vci_tgt_iox (*(this->p_vci_iob_iox_tgt));
619	iob->p_vci_tgt_int (signal_int_vci_tgt_iobx);
620	iob->p_vci_ini_int (signal_int_vci_ini_iobx);
621	iob->p_vci_ini_ram (signal_ram_vci_ini_iobx);
622
623	// initiator wrapper to RAM network
624	iob_ram_wi->p_clk (this->p_clk);
625	iob_ram_wi->p_resetn (this->p_resetn);
626	iob_ram_wi->p_dspin_cmd (signal_ram_dspin_cmd_iob_i);
627	iob_ram_wi->p_dspin_rsp (signal_ram_dspin_rsp_iob_i);
628	iob_ram_wi->p_vci (signal_ram_vci_ini_iobx);
629
630	// crossbar between MEMC and IOB to RAM network
631	ram_xbar_cmd->p_clk (this->p_clk);
632	ram_xbar_cmd->p_resetn (this->p_resetn);
633	ram_xbar_cmd->p_global_out (signal_ram_dspin_cmd_xbar);
634	ram_xbar_cmd->p_global_in (signal_ram_dspin_cmd_false);
635	ram_xbar_cmd->p_local_in[ram_memc_ini_id] (signal_ram_dspin_cmd_memc_i);
636	ram_xbar_cmd->p_local_in[ram_iobx_ini_id] (signal_ram_dspin_cmd_iob_i);
637
638	ram_xbar_rsp->p_clk (this->p_clk);
639	ram_xbar_rsp->p_resetn (this->p_resetn);
640	ram_xbar_rsp->p_global_out (signal_ram_dspin_rsp_false);
641	ram_xbar_rsp->p_global_in (signal_ram_dspin_rsp_xbar);
642	ram_xbar_rsp->p_local_out[ram_memc_ini_id] (signal_ram_dspin_rsp_memc_i);
643	ram_xbar_rsp->p_local_out[ram_iobx_ini_id] (signal_ram_dspin_rsp_iob_i);
644	}
645
646	SC_METHOD(init);
647
648	} // end constructor
649
650	tmpl(void)::init()
651	{
652	signal_ram_dspin_cmd_false.write = false;
653	signal_ram_dspin_rsp_false.read = true;
654	} // end init
655
656	}}
657
658
659	// Local Variables:
660	// tab-width: 4
661	// c-basic-offset: 4
662	// c-file-offsets:((innamespace . 0)(inline-open . 0))
663	// indent-tabs-mode: nil
664	// End:
665
666	// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
667

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Project-Id-Version: Trac 0.12
Report-Msgid-Bugs-To: trac-dev@googlegroups.com
POT-Creation-Date: 2018-07-07 16:55+0000
PO-Revision-Date: 2010-07-19 23:05+0200
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