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vci_block_device_tsar_v4.cpp @ 407

Last change on this file since 407 was 407, checked in by porquet, 11 years ago
add missing header (for ::read, ::write, etc.)
File size: 23.5 KB

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1	/* -- c++ --
2	*
3	* SOCLIB_LGPL_HEADER_BEGIN
4	*
5	* This file is part of SoCLib, GNU LGPLv2.1.
6	*
7	* SoCLib is free software; you can redistribute it and/or modify it
8	* under the terms of the GNU Lesser General Public License as published
9	* by the Free Software Foundation; version 2.1 of the License.
10	*
11	* SoCLib is distributed in the hope that it will be useful, but
12	* WITHOUT ANY WARRANTY; without even the implied warranty of
13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14	* Lesser General Public License for more details.
15	*
16	* You should have received a copy of the GNU Lesser General Public
17	* License along with SoCLib; if not, write to the Free Software
18	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
19	* 02110-1301 USA
20	*
21	* SOCLIB_LGPL_HEADER_END
22	*
23	* Copyright (c) UPMC, Lip6, Asim
24	* alain.greiner@lip6.fr april 2011
25	*
26	* Maintainers: alain
27	*/
28
29	#include <unistd.h>
30	#include <stdint.h>
31	#include <iostream>
32	#include <fcntl.h>
33	#include "vci_block_device_tsar_v4.h"
34
35	namespace soclib { namespace caba {
36
37	#define tmpl(t) template<typename vci_param> t VciBlockDeviceTsarV4<vci_param>
38
39	using namespace soclib::caba;
40	using namespace soclib::common;
41
42	////////////////////////
43	tmpl(void)::transition()
44	{
45	if(p_resetn.read() == false)
46	{
47	r_initiator_fsm = M_IDLE;
48	r_target_fsm = T_IDLE;
49	r_irq_enable = true;
50	r_go = false;
51	return;
52	}
53
54	//////////////////////////////////////////////////////////////////////////////
55	// The Target FSM controls the following registers:
56	// r_target_fsm, r_irq_enable, r_nblocks, r_buf adress, r_lba, r_go, r_read
57	//////////////////////////////////////////////////////////////////////////////
58
59	switch(r_target_fsm) {
60	////////////
61	case T_IDLE:
62	{
63	if ( p_vci_target.cmdval.read() )
64	{
65	r_srcid = p_vci_target.srcid.read();
66	r_trdid = p_vci_target.trdid.read();
67	r_pktid = p_vci_target.pktid.read();
68	sc_dt::sc_uint<vci_param::N> address = p_vci_target.address.read();
69	bool read = (p_vci_target.cmd.read() == vci_param::CMD_READ);
70	uint32_t cell = (uint32_t)((address & 0x1F)>>2);
71
72	if ( !read && !m_segment.contains(address) ) r_target_fsm = T_WRITE_ERROR;
73	else if( read && !m_segment.contains(address) ) r_target_fsm = T_READ_ERROR;
74	else if( !read && !p_vci_target.eop.read() ) r_target_fsm = T_WRITE_ERROR;
75	else if( read && !p_vci_target.eop.read() ) r_target_fsm = T_READ_ERROR;
76	else if( !read && (cell == BLOCK_DEVICE_BUFFER) ) r_target_fsm = T_WRITE_BUFFER;
77	else if( read && (cell == BLOCK_DEVICE_BUFFER) ) r_target_fsm = T_READ_BUFFER;
78	else if( !read && (cell == BLOCK_DEVICE_COUNT) ) r_target_fsm = T_WRITE_COUNT;
79	else if( read && (cell == BLOCK_DEVICE_COUNT) ) r_target_fsm = T_READ_COUNT;
80	else if( !read && (cell == BLOCK_DEVICE_LBA) ) r_target_fsm = T_WRITE_LBA;
81	else if( read && (cell == BLOCK_DEVICE_LBA) ) r_target_fsm = T_READ_LBA;
82	else if( !read && (cell == BLOCK_DEVICE_OP) ) r_target_fsm = T_WRITE_OP;
83	else if( read && (cell == BLOCK_DEVICE_STATUS) ) r_target_fsm = T_READ_STATUS;
84	else if( !read && (cell == BLOCK_DEVICE_IRQ_ENABLE) ) r_target_fsm = T_WRITE_IRQEN;
85	else if( read && (cell == BLOCK_DEVICE_IRQ_ENABLE) ) r_target_fsm = T_READ_IRQEN;
86	else if( read && (cell == BLOCK_DEVICE_SIZE) ) r_target_fsm = T_READ_SIZE;
87	else if( read && (cell == BLOCK_DEVICE_BLOCK_SIZE) ) r_target_fsm = T_READ_BLOCK;
88	}
89	break;
90	}
91	////////////////////
92	case T_WRITE_BUFFER:
93	{
94	if ( r_initiator_fsm == M_IDLE ) r_buf_address = (uint32_t)p_vci_target.wdata.read();
95	if ( p_vci_target.rspack.read() ) r_target_fsm = T_IDLE;
96	break;
97	}
98	///////////////////
99	case T_WRITE_COUNT:
100	{
101	if ( r_initiator_fsm == M_IDLE ) r_nblocks = (uint32_t)p_vci_target.wdata.read();
102	if ( p_vci_target.rspack.read() ) r_target_fsm = T_IDLE;
103	break;
104	}
105	/////////////////
106	case T_WRITE_LBA:
107	{
108	if ( r_initiator_fsm == M_IDLE ) r_lba = (uint32_t)p_vci_target.wdata.read();
109	if ( p_vci_target.rspack.read() ) r_target_fsm = T_IDLE;
110	break;
111	}
112	////////////////
113	case T_WRITE_OP:
114	{
115	if ( r_initiator_fsm == M_IDLE )
116	{
117	if ( (uint32_t)p_vci_target.wdata.read() == BLOCK_DEVICE_READ )
118	{
119	r_read = true;
120	r_go = true;
121	}
122	else if ( (uint32_t)p_vci_target.wdata.read() == BLOCK_DEVICE_WRITE)
123	{
124	r_read = false;
125	r_go = true;
126	}
127	}
128	if ( p_vci_target.rspack.read() ) r_target_fsm = T_IDLE;
129	break;
130	}
131	///////////////////
132	case T_WRITE_IRQEN:
133	{
134	r_irq_enable = (p_vci_target.wdata.read() != 0);
135	if ( p_vci_target.rspack.read() ) r_target_fsm = T_IDLE;
136	break;
137	}
138	///////////////////
139	case T_READ_BUFFER:
140	case T_READ_COUNT:
141	case T_READ_LBA:
142	case T_READ_IRQEN:
143	case T_READ_SIZE:
144	case T_READ_BLOCK:
145	case T_READ_ERROR:
146	case T_WRITE_ERROR:
147	{
148	if ( p_vci_target.rspack.read() ) r_target_fsm = T_IDLE;
149	break;
150	}
151	///////////////////
152	case T_READ_STATUS:
153	{
154	if ( p_vci_target.rspack.read() )
155	{
156	r_target_fsm = T_IDLE;
157	if( (r_initiator_fsm == M_READ_SUCCESS ) \|\|
158	(r_initiator_fsm == M_READ_ERROR ) \|\|
159	(r_initiator_fsm == M_WRITE_SUCCESS) \|\|
160	(r_initiator_fsm == M_WRITE_ERROR ) ) r_go = false;
161	}
162	break;
163	}
164	} // end switch target fsm
165
166	//////////////////////////////////////////////////////////////////////////////
167	// The initiator FSM executes a loop, transfering one block per iteration.
168	// Each block is split in bursts, and the number of bursts depends
169	// on the memory buffer alignment on a burst boundary:
170	// - If buffer aligned, all burst have the same length (m_flits_per burst)
171	// and the number of bursts is (m_bursts_per_block).
172	// - If buffer not aligned, the number of bursts is (m_bursts_per_block + 1)
173	// and first and last burst are shorter, because all flits in a burst
174	// must be contained in a single cache line.
175	// first burst => nflits = m_flits_per_burst - offset
176	// last burst => nflits = offset
177	// other burst => nflits = m_flits_per_burst
178	//////////////////////////////////////////////////////////////////////////////
179
180	switch( r_initiator_fsm.read() ) {
181	////////////
182	case M_IDLE: // check buffer alignment to compute the number of bursts
183	{
184	if ( r_go.read() )
185	{
186	r_index = 0;
187	r_block_count = 0;
188	r_burst_count = 0;
189	r_flit_count = 0;
190	r_latency_count = m_latency;
191
192	// compute r_burst_offset (zero when buffer aligned)
193	r_burst_offset = (r_buf_address.read()>>2) % m_flits_per_burst;
194
195	// start tranfer
196	if ( r_read.read() ) r_initiator_fsm = M_READ_BLOCK;
197	else r_initiator_fsm = M_WRITE_BURST;
198	}
199	break;
200	}
201	//////////////////
202	case M_READ_BLOCK: // read one block from disk after waiting m_latency cycles
203	{
204	if ( r_latency_count.read() == 0 )
205	{
206	r_latency_count = m_latency;
207	::lseek(m_fd, (r_lba + r_block_count)m_flits_per_block4, SEEK_SET);
208	if( ::read(m_fd, r_local_buffer, m_flits_per_block*4) < 0 )
209	{
210	r_initiator_fsm = M_READ_ERROR;
211	}
212	else
213	{
214	r_burst_count = 0;
215	r_flit_count = 0;
216	r_initiator_fsm = M_READ_BURST;
217	}
218	}
219	else
220	{
221	r_latency_count = r_latency_count.read() - 1;
222	}
223	break;
224	}
225	//////////////////
226	case M_READ_BURST: // Compute the number of flits in the burst
227	{
228	uint32_t offset = r_burst_offset.read();
229
230	if ( offset ) // buffer not aligned
231	{
232	if ( r_burst_count.read() == 0 ) r_burst_nflits = m_flits_per_burst - offset;
233	else if ( r_burst_count.read() == m_bursts_per_block ) r_burst_nflits = offset;
234	else r_burst_nflits = m_flits_per_burst;
235	}
236	else // buffer aligned
237	{
238	r_burst_nflits = m_flits_per_burst;
239	}
240	r_initiator_fsm = M_READ_CMD;
241	break;
242	}
243	////////////////
244	case M_READ_CMD: // Send a multi-flits VCI WRITE command
245	{
246	if ( p_vci_initiator.cmdack.read() )
247	{
248	if ( r_flit_count == (r_burst_nflits.read() - 1) ) // last flit in a burst
249	{
250	r_initiator_fsm = M_READ_RSP;
251	r_flit_count = 0;
252	}
253	else // not the last flit
254	{
255	r_flit_count = r_flit_count.read() + 1;
256	}
257
258	// compute next flit address and next local buffer index
259	r_buf_address = r_buf_address.read() + 4;
260	r_index = r_index.read() + 1;
261	}
262	break;
263	}
264	////////////////
265	case M_READ_RSP: // Wait a single flit VCI WRITE response
266	{
267	if ( p_vci_initiator.rspval.read() )
268	{
269	bool aligned = (r_burst_offset.read() == 0);
270
271	if ( (p_vci_initiator.rerror.read()&0x1) != 0 )
272	{
273	r_initiator_fsm = M_READ_ERROR;
274	}
275	else if ( (not aligned and (r_burst_count.read() == m_bursts_per_block)) or
276	(aligned and (r_burst_count.read() == (m_bursts_per_block-1))) )
277	{
278	if ( r_block_count.read() == (r_nblocks.read()-1) ) // last burst of last block
279	{
280	r_initiator_fsm = M_READ_SUCCESS;
281	}
282	else // last burst not last block
283	{
284	r_index = 0;
285	r_burst_count = 0;
286	r_block_count = r_block_count.read() + 1;
287	r_initiator_fsm = M_READ_BLOCK;
288	}
289	}
290	else // not the last burst
291	{
292	r_burst_count = r_burst_count.read() + 1;
293	r_initiator_fsm = M_READ_BURST;
294	}
295	}
296	break;
297	}
298	///////////////////
299	case M_READ_SUCCESS:
300	case M_READ_ERROR:
301	{
302	if( !r_go ) r_initiator_fsm = M_IDLE;
303	break;
304	}
305	///////////////////
306	case M_WRITE_BURST: // Compute the number of flits in the burst
307	{
308	uint32_t offset = r_burst_offset.read();
309
310	if ( offset ) // buffer not aligned
311	{
312	if ( r_burst_count.read() == 0 ) r_burst_nflits = m_flits_per_burst - offset;
313	else if ( r_burst_count.read() == m_bursts_per_block ) r_burst_nflits = offset;
314	else r_burst_nflits = m_flits_per_burst;
315	}
316	else // buffer aligned
317	{
318	r_burst_nflits = m_flits_per_burst;
319	}
320	r_initiator_fsm = M_WRITE_CMD;
321	break;
322	}
323	/////////////////
324	case M_WRITE_CMD: // This is actually a single flit VCI READ command
325	{
326	if ( p_vci_initiator.cmdack.read() ) r_initiator_fsm = M_WRITE_RSP;
327	break;
328	}
329	/////////////////
330	case M_WRITE_RSP: // This is actually a multi-flits VCI READ response
331	{
332	bool aligned = (r_burst_offset.read() == 0);
333
334	if ( p_vci_initiator.rspval.read() )
335	{
336	r_local_buffer[r_index.read()] = (uint32_t)p_vci_initiator.rdata.read();
337	r_index = r_index.read() + 1;
338
339	if ( p_vci_initiator.reop.read() ) // last flit of the burst
340	{
341	r_flit_count = 0;
342	r_buf_address = r_buf_address.read() + (r_burst_nflits.read()<<2);
343
344	if( (p_vci_initiator.rerror.read()&0x1) != 0 )
345	{
346	r_initiator_fsm = M_WRITE_ERROR;
347	}
348	else if ( (not aligned and (r_burst_count.read() == m_bursts_per_block)) or
349	(aligned and (r_burst_count.read() == (m_bursts_per_block-1))) ) // last burst
350	{
351	r_initiator_fsm = M_WRITE_BLOCK;
352	}
353	else // not the last burst
354	{
355	r_burst_count = r_burst_count.read() + 1;
356	r_initiator_fsm = M_WRITE_BURST;
357	}
358	}
359	else
360	{
361	r_flit_count = r_flit_count.read() + 1;
362	}
363	}
364	break;
365	}
366	///////////////////
367	case M_WRITE_BLOCK: // write a block to disk after waiting m_latency cycles
368	{
369	if ( r_latency_count == 0 )
370	{
371	r_latency_count = m_latency;
372	::lseek(m_fd, (r_lba + r_block_count)m_flits_per_blockvci_param::B, SEEK_SET);
373	if( ::write(m_fd, r_local_buffer, m_flits_per_block*vci_param::B) < 0 )
374	{
375	r_initiator_fsm = M_WRITE_ERROR;
376	}
377	else if ( r_block_count.read() == r_nblocks.read() - 1 )
378	{
379	r_initiator_fsm = M_WRITE_SUCCESS;
380	}
381	else
382	{
383	r_burst_count = 0;
384	r_index = 0;
385	r_block_count = r_block_count.read() + 1;
386	r_initiator_fsm = M_WRITE_BURST;
387	}
388	}
389	else
390	{
391	r_latency_count = r_latency_count - 1;
392	}
393	break;
394	}
395	/////////////////////
396	case M_WRITE_SUCCESS:
397	case M_WRITE_ERROR:
398	{
399	if( !r_go ) r_initiator_fsm = M_IDLE;
400	break;
401	}
402	} // end switch r_initiator_fsm
403	} // end transition
404
405	//////////////////////
406	tmpl(void)::genMoore()
407	{
408	// p_vci_target port
409	p_vci_target.rsrcid = (sc_dt::sc_uint<vci_param::S>)r_srcid.read();
410	p_vci_target.rtrdid = (sc_dt::sc_uint<vci_param::T>)r_trdid.read();
411	p_vci_target.rpktid = (sc_dt::sc_uint<vci_param::P>)r_pktid.read();
412	p_vci_target.reop = true;
413
414	switch(r_target_fsm) {
415	case T_IDLE:
416	p_vci_target.cmdack = true;
417	p_vci_target.rspval = false;
418	break;
419	case T_READ_STATUS:
420	p_vci_target.cmdack = false;
421	p_vci_target.rspval = true;
422	if (r_initiator_fsm == M_IDLE) p_vci_target.rdata = BLOCK_DEVICE_IDLE;
423	else if(r_initiator_fsm == M_READ_SUCCESS) p_vci_target.rdata = BLOCK_DEVICE_READ_SUCCESS;
424	else if(r_initiator_fsm == M_WRITE_SUCCESS) p_vci_target.rdata = BLOCK_DEVICE_WRITE_SUCCESS;
425	else if(r_initiator_fsm == M_READ_ERROR) p_vci_target.rdata = BLOCK_DEVICE_READ_ERROR;
426	else if(r_initiator_fsm == M_WRITE_ERROR) p_vci_target.rdata = BLOCK_DEVICE_WRITE_ERROR;
427	else p_vci_target.rdata = BLOCK_DEVICE_BUSY;
428	p_vci_target.rerror = VCI_READ_OK;
429	break;
430	case T_READ_BUFFER:
431	p_vci_target.cmdack = false;
432	p_vci_target.rspval = true;
433	p_vci_target.rdata = (uint32_t)r_buf_address.read();
434	p_vci_target.rerror = VCI_READ_OK;
435	break;
436	case T_READ_COUNT:
437	p_vci_target.cmdack = false;
438	p_vci_target.rspval = true;
439	p_vci_target.rdata = (uint32_t)r_nblocks.read();
440	p_vci_target.rerror = VCI_READ_OK;
441	break;
442	case T_READ_LBA:
443	p_vci_target.cmdack = false;
444	p_vci_target.rspval = true;
445	p_vci_target.rdata = (uint32_t)r_lba.read();
446	p_vci_target.rerror = VCI_READ_OK;
447	break;
448	case T_READ_IRQEN:
449	p_vci_target.cmdack = false;
450	p_vci_target.rspval = true;
451	p_vci_target.rdata = (uint32_t)r_irq_enable.read();
452	p_vci_target.rerror = VCI_READ_OK;
453	break;
454	case T_READ_SIZE:
455	p_vci_target.cmdack = false;
456	p_vci_target.rspval = true;
457	p_vci_target.rdata = (uint32_t)m_device_size;
458	p_vci_target.rerror = VCI_READ_OK;
459	break;
460	case T_READ_BLOCK:
461	p_vci_target.cmdack = false;
462	p_vci_target.rspval = true;
463	p_vci_target.rdata = (uint32_t)m_flits_per_block*vci_param::B;
464	p_vci_target.rerror = VCI_READ_OK;
465	break;
466	case T_READ_ERROR:
467	p_vci_target.cmdack = false;
468	p_vci_target.rspval = true;
469	p_vci_target.rdata = 0;
470	p_vci_target.rerror = VCI_READ_ERROR;
471	break;
472	case T_WRITE_ERROR:
473	p_vci_target.cmdack = false;
474	p_vci_target.rspval = true;
475	p_vci_target.rdata = 0;
476	p_vci_target.rerror = VCI_WRITE_ERROR;
477	break;
478	default:
479	p_vci_target.cmdack = false;
480	p_vci_target.rspval = true;
481	p_vci_target.rdata = 0;
482	p_vci_target.rerror = VCI_WRITE_OK;
483	break;
484	} // end switch target fsm
485
486	// p_vci_initiator port
487	p_vci_initiator.srcid = (sc_dt::sc_uint<vci_param::S>)m_srcid;
488	p_vci_initiator.trdid = 0;
489	p_vci_initiator.contig = true;
490	p_vci_initiator.cons = false;
491	p_vci_initiator.wrap = false;
492	p_vci_initiator.cfixed = false;
493	p_vci_initiator.clen = 0;
494
495	switch (r_initiator_fsm) {
496	case M_WRITE_CMD: // It is actually a single flit VCI read command
497	p_vci_initiator.rspack = false;
498	p_vci_initiator.cmdval = true;
499	p_vci_initiator.address = (sc_dt::sc_uint<vci_param::N>)r_buf_address.read();
500	p_vci_initiator.cmd = vci_param::CMD_READ;
501	p_vci_initiator.pktid = TYPE_READ_DATA_UNC; // or _MISS ?
502	p_vci_initiator.wdata = 0;
503	p_vci_initiator.be = (uint32_t)0xF;
504	p_vci_initiator.plen = (sc_dt::sc_uint<vci_param::K>)(r_burst_nflits.read()<<2);
505	p_vci_initiator.eop = true;
506	break;
507	case M_READ_CMD: // It is actually a multi-flits VCI WRITE command
508	p_vci_initiator.rspack = false;
509	p_vci_initiator.cmdval = true;
510	p_vci_initiator.address = (sc_dt::sc_uint<vci_param::N>)r_buf_address.read();
511	p_vci_initiator.cmd = vci_param::CMD_WRITE;
512	p_vci_initiator.pktid = TYPE_WRITE;
513	p_vci_initiator.wdata = (uint32_t)r_local_buffer[r_index.read()];
514	p_vci_initiator.be = 0xF;
515	p_vci_initiator.plen = (sc_dt::sc_uint<vci_param::K>)(r_burst_nflits.read()<<2);
516	p_vci_initiator.eop = ( r_flit_count.read() == (r_burst_nflits.read() - 1) );
517	break;
518	case M_READ_RSP:
519	case M_WRITE_RSP:
520	p_vci_initiator.rspack = true;
521	p_vci_initiator.cmdval = false;
522	break;
523	default:
524	p_vci_initiator.rspack = false;
525	p_vci_initiator.cmdval = false;
526	break;
527	}
528
529	// IRQ signal
530	if(((r_initiator_fsm == M_READ_SUCCESS) \|\|
531	(r_initiator_fsm == M_WRITE_SUCCESS) \|\|
532	(r_initiator_fsm == M_READ_ERROR) \|\|
533	(r_initiator_fsm == M_WRITE_ERROR) ) && r_irq_enable) p_irq = true;
534	else p_irq = false;
535	} // end GenMoore()
536
537	//////////////////////////////////////////////////////////////////////////////
538	tmpl(/**/)::VciBlockDeviceTsarV4( sc_core::sc_module_name name,
539	const soclib::common::MappingTable &mt,
540	const soclib::common::IntTab &srcid,
541	const soclib::common::IntTab &tgtid,
542	const std::string &filename,
543	const uint32_t block_size,
544	const uint32_t burst_size,
545	const uint32_t latency)
546
547	: caba::BaseModule(name),
548	m_segment(mt.getSegment(tgtid)),
549	m_srcid(mt.indexForId(srcid)),
550	m_flits_per_block(block_size/vci_param::B),
551	m_flits_per_burst(burst_size/vci_param::B),
552	m_bursts_per_block(block_size/burst_size),
553	m_latency(latency),
554	p_clk("p_clk"),
555	p_resetn("p_resetn"),
556	p_vci_initiator("p_vci_initiator"),
557	p_vci_target("p_vci_target"),
558	p_irq("p_irq")
559	{
560	SC_METHOD(transition);
561	sensitive_pos << p_clk;
562
563	SC_METHOD(genMoore);
564	sensitive_neg << p_clk;
565
566	if( (block_size != 64 ) &&
567	(block_size != 128) &&
568	(block_size != 256) &&
569	(block_size != 512) &&
570	(block_size != 1024) &&
571	(block_size != 2048) &&
572	(block_size != 4096) )
573	{
574	std::cout << "Error in component VciBlockDeviceTsarV4 : " << name << std::endl;
575	std::cout << "The block size must be 128, 256, 512, 1024, 2048 or 4096 bytes" << std::endl;
576	exit(1);
577	}
578	if( (burst_size != 1 ) &&
579	(burst_size != 2 ) &&
580	(burst_size != 4 ) &&
581	(burst_size != 8 ) &&
582	(burst_size != 16) &&
583	(burst_size != 32) &&
584	(burst_size != 64) )
585	{
586	std::cout << "Error in component VciBlockDeviceTsarV4 : " << name << std::endl;
587	std::cout << "The burst size must be 1, 2, 4, 8, 16, 32 or 64 bytes" << std::endl;
588	exit(1);
589	}
590	if ( m_segment.size() < 32 )
591	{
592	std::cout << "Error in component VciBlockDeviceTsarV4 : " << name << std::endl;
593	std::cout << "The size of the segment cannot be smaller than 32 bytes" << std::endl;
594	exit(1);
595	}
596	if ( (m_segment.baseAddress() & 0x0000001F) != 0 )
597	{
598	std::cout << "Error in component VciBlockDeviceTsarV4 : " << name << std::endl;
599	std::cout << "The base address of the segment must be multiple of 32 bytes" << std::endl;
600	exit(1);
601	}
602	if ( vci_param::B != 4 )
603	{
604	std::cout << "Error in component VciBlockDeviceTsarV4 : " << name << std::endl;
605	std::cout << "The VCI data fields must have 32 bits" << std::endl;
606	exit(1);
607	}
608	m_fd = ::open(filename.c_str(), O_RDWR);
609	if ( m_fd < 0 )
610	{
611	std::cout << "Error in component VciBlockDeviceTsarV4 : " << name << std::endl;
612	std::cout << "Unable to open file " << filename << std::endl;
613	exit(1);
614	}
615	m_device_size = lseek(m_fd, 0, SEEK_END) / block_size;
616	if ( m_device_size > ((uint64_t)1<<32) )
617	{
618	std::cout << "Warning: block device " << name << std::endl;
619	std::cout << "The file " << filename << std::endl;
620	std::cout << "has more blocks than addressable with the 32 bits PIBUS address" << std::endl;
621	m_device_size = ((uint64_t)1<<32);
622	}
623
624	r_local_buffer = new uint32_t[m_flits_per_block];
625
626	} // end constructor
627
628	//////////////////////////
629	tmpl(void)::print_trace()
630	{
631	const char* initiator_str[] = {
632	"IDLE",
633
634	"READ_BLOCK",
635	"READ_BURST",
636	"READ_CMD",
637	"READ_RSP",
638	"READ_TEST",
639	"READ_SUCCESS",
640	"READ_ERROR",
641
642	"WRITE_BURST",
643	"WRITE_CMD",
644	"WRITE_RSP",
645	"WRITE_BLOCK",
646	"WRITE_SUCCESS",
647	"WRITE_ERROR",
648	};
649	const char* target_str[] = {
650	"IDLE ",
651	"WRITE_BUFFER",
652	"READ_BUFFER ",
653	"WRITE_COUNT ",
654	"READ_COUNT ",
655	"WRITE_LBA ",
656	"READ_LBA ",
657	"WRITE_OP ",
658	"READ_STATUS ",
659	"WRITE_IRQEN ",
660	"READ_IRQEN ",
661	"READ_SIZE ",
662	"READ_BLOCK ",
663	"READ_ERROR ",
664	"WRITE_ERROR ",
665	};
666
667	std::cout << "BDEV_TGT : " << target_str[r_target_fsm.read()]
668	<< " BDEV_INI : " << initiator_str[r_initiator_fsm.read()]
669	<< " block = " << r_block_count.read()
670	<< " burst = " << r_burst_count.read()
671	<< " flit = " << r_flit_count.read() <<std::endl;
672	}
673
674
675	}} // end namespace
676
677	// Local Variables:
678	// tab-width: 4
679	// c-basic-offset: 4
680	// c-file-offsets:((innamespace . 0)(inline-open . 0))
681	// indent-tabs-mode: nil
682	// End:
683
684	// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
685

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source: branches/v4/modules/vci_block_device_tsar_v4/caba/source/src/vci_block_device_tsar_v4.cpp @ 407

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