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vci_cc_vcache_wrapper_v4.cpp @ 635

Last change on this file since 635 was 635, checked in by porquet, 10 years ago
cc_vcache_v4: enable ondemand debugging (via xtn commands)
File size: 200.6 KB

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1	/* i- c++ --C
2	* File : vci_cc_vcache_wrapper_v4.cpp
3	* Copyright (c) UPMC, Lip6, SoC
4	* Authors : Alain GREINER, Yang GAO
5	*
6	* SOCLIB_LGPL_HEADER_BEGIN
7	*
8	* This file is part of SoCLib, GNU LGPLv2.1.
9	*
10	* SoCLib is free software; you can redistribute it and/or modify it
11	* under the terms of the GNU Lesser General Public License as published
12	* by the Free Software Foundation; version 2.1 of the License.
13	*
14	* SoCLib is distributed in the hope that it will be useful, but
15	* WITHOUT ANY WARRANTY; without even the implied warranty of
16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17	* Lesser General Public License for more details.
18	*
19	* You should have received a copy of the GNU Lesser General Public
20	* License along with SoCLib; if not, write to the Free Software
21	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
22	* 02110-1301 USA
23	*
24	* SOCLIB_LGPL_HEADER_END
25	*/
26
27	#include <cassert>
28	#include "arithmetics.h"
29	#include "../include/vci_cc_vcache_wrapper_v4.h"
30
31	#define DEBUG_DCACHE 1
32	#define DEBUG_ICACHE 1
33	#define DEBUG_CLEANUP 0
34
35	namespace soclib {
36	namespace caba {
37
38	namespace {
39	const char *icache_fsm_state_str[] = {
40	"ICACHE_IDLE",
41
42	"ICACHE_XTN_TLB_FLUSH",
43	"ICACHE_XTN_CACHE_FLUSH",
44	"ICACHE_XTN_TLB_INVAL",
45	"ICACHE_XTN_CACHE_INVAL_VA",
46	"ICACHE_XTN_CACHE_INVAL_PA",
47	"ICACHE_XTN_CACHE_INVAL_GO",
48
49	"ICACHE_TLB_WAIT",
50
51	"ICACHE_MISS_VICTIM",
52	"ICACHE_MISS_INVAL",
53	"ICACHE_MISS_WAIT",
54	"ICACHE_MISS_UPDT",
55
56	"ICACHE_UNC_WAIT",
57
58	"ICACHE_CC_CHECK",
59	"ICACHE_CC_INVAL",
60	"ICACHE_CC_UPDT",
61
62	};
63	const char *dcache_fsm_state_str[] = {
64	"DCACHE_IDLE",
65
66	"DCACHE_TLB_MISS",
67	"DCACHE_TLB_PTE1_GET",
68	"DCACHE_TLB_PTE1_SELECT",
69	"DCACHE_TLB_PTE1_UPDT",
70	"DCACHE_TLB_PTE2_GET",
71	"DCACHE_TLB_PTE2_SELECT",
72	"DCACHE_TLB_PTE2_UPDT",
73	"DCACHE_TLB_LR_UPDT",
74	"DCACHE_TLB_LR_WAIT",
75	"DCACHE_TLB_RETURN",
76
77	"DCACHE_XTN_SWITCH",
78	"DCACHE_XTN_SYNC",
79	"DCACHE_XTN_IC_INVAL_VA",
80	"DCACHE_XTN_IC_FLUSH",
81	"DCACHE_XTN_IC_INVAL_PA",
82	"DCACHE_XTN_IT_INVAL",
83	"DCACHE_XTN_DC_FLUSH",
84	"DCACHE_XTN_DC_INVAL_VA",
85	"DCACHE_XTN_DC_INVAL_PA",
86	"DCACHE_XTN_DC_INVAL_END",
87	"DCACHE_XTN_DC_INVAL_GO",
88	"DCACHE_XTN_DT_INVAL",
89
90	"DCACHE_DIRTY_PTE_GET",
91	"DCACHE_DIRTY_WAIT",
92
93	"DCACHE_MISS_VICTIM",
94	"DCACHE_MISS_INVAL",
95	"DCACHE_MISS_WAIT",
96	"DCACHE_MISS_UPDT",
97
98	"DCACHE_UNC_WAIT",
99	"DCACHE_LL_WAIT",
100	"DCACHE_SC_WAIT",
101
102	"DCACHE_CC_CHECK",
103	"DCACHE_CC_INVAL",
104	"DCACHE_CC_UPDT",
105
106	"DCACHE_INVAL_TLB_SCAN",
107	};
108	const char *cmd_fsm_state_str[] = {
109	"CMD_IDLE",
110	"CMD_INS_MISS",
111	"CMD_INS_UNC",
112	"CMD_DATA_MISS",
113	"CMD_DATA_UNC",
114	"CMD_DATA_WRITE",
115	"CMD_DATA_LL",
116	"CMD_DATA_SC",
117	"CMD_DATA_CAS",
118	};
119	const char *rsp_fsm_state_str[] = {
120	"RSP_IDLE",
121	"RSP_INS_MISS",
122	"RSP_INS_UNC",
123	"RSP_DATA_MISS",
124	"RSP_DATA_UNC",
125	"RSP_DATA_LL",
126	"RSP_DATA_WRITE",
127	};
128	const char *cleanup_fsm_state_str[] = {
129	"CLEANUP_DATA_IDLE",
130	"CLEANUP_DATA_GO",
131	"CLEANUP_INS_IDLE",
132	"CLEANUP_INS_GO",
133	};
134	const char *tgt_fsm_state_str[] = {
135	"TGT_IDLE",
136	"TGT_UPDT_WORD",
137	"TGT_UPDT_DATA",
138	"TGT_REQ_BROADCAST",
139	"TGT_REQ_ICACHE",
140	"TGT_REQ_DCACHE",
141	"TGT_RSP_BROADCAST",
142	"TGT_RSP_ICACHE",
143	"TGT_RSP_DCACHE",
144	};
145	}
146
147	#define tmpl(...) template<typename vci_param, typename iss_t> __VA_ARGS__ VciCcVCacheWrapperV4<vci_param, iss_t>
148
149	using soclib::common::uint32_log2;
150
151	/////////////////////////////////
152	tmpl(/**/)::VciCcVCacheWrapperV4(
153	sc_module_name name,
154	int proc_id,
155	const soclib::common::MappingTable &mtd,
156	const soclib::common::MappingTable &mtc,
157	const soclib::common::IntTab &initiator_index_d,
158	const soclib::common::IntTab &initiator_index_c,
159	const soclib::common::IntTab &target_index_c,
160	size_t itlb_ways,
161	size_t itlb_sets,
162	size_t dtlb_ways,
163	size_t dtlb_sets,
164	size_t icache_ways,
165	size_t icache_sets,
166	size_t icache_words,
167	size_t dcache_ways,
168	size_t dcache_sets,
169	size_t dcache_words,
170	size_t wbuf_nlines,
171	size_t wbuf_nwords,
172	size_t x_width,
173	size_t y_width,
174	uint32_t memory_cache_local_id,
175	uint32_t max_frozen_cycles,
176	uint32_t debug_start_cycle,
177	bool debug_ok)
178	: soclib::caba::BaseModule(name),
179
180	p_clk("clk"),
181	p_resetn("resetn"),
182	p_vci_ini_d("vci_ini_d"),
183	p_vci_ini_c("vci_ini_c"),
184	p_vci_tgt_c("vci_tgt_d"),
185
186	m_cacheability_table(mtd.getCacheabilityTable()),
187	m_segment(mtc.getSegment(target_index_c)),
188	m_srcid_d(mtd.indexForId(initiator_index_d)),
189	m_srcid_c(mtc.indexForId(initiator_index_c)),
190
191	m_itlb_ways(itlb_ways),
192	m_itlb_sets(itlb_sets),
193
194	m_dtlb_ways(dtlb_ways),
195	m_dtlb_sets(dtlb_sets),
196
197	m_icache_ways(icache_ways),
198	m_icache_sets(icache_sets),
199	m_icache_yzmask((~0)<<(uint32_log2(icache_words) + 2)),
200	m_icache_words(icache_words),
201
202	m_dcache_ways(dcache_ways),
203	m_dcache_sets(dcache_sets),
204	m_dcache_yzmask((~0)<<(uint32_log2(dcache_words) + 2)),
205	m_dcache_words(dcache_words),
206
207	m_x_width(x_width),
208	m_y_width(y_width),
209
210	m_memory_cache_local_id(memory_cache_local_id),
211
212	m_proc_id(proc_id),
213
214	m_max_frozen_cycles(max_frozen_cycles),
215
216	m_paddr_nbits(vci_param::N),
217
218	m_debug_start_cycle(debug_start_cycle),
219	m_debug_ok(debug_ok),
220
221	r_mmu_ptpr("r_mmu_ptpr"),
222	r_mmu_mode("r_mmu_mode"),
223	r_mmu_word_lo("r_mmu_word_lo"),
224	r_mmu_word_hi("r_mmu_word_hi"),
225	r_mmu_ibvar("r_mmu_ibvar"),
226	r_mmu_dbvar("r_mmu_dbvar"),
227	r_mmu_ietr("r_mmu_ietr"),
228	r_mmu_detr("r_mmu_detr"),
229
230	r_icache_fsm("r_icache_fsm"),
231	r_icache_fsm_save("r_icache_fsm_save"),
232
233	r_icache_vci_paddr("r_icache_vci_paddr"),
234	r_icache_vaddr_save("r_icache_vaddr_save"),
235
236	r_icache_miss_way("r_icache_miss_way"),
237	r_icache_miss_set("r_icache_miss_set"),
238	r_icache_miss_word("r_icache_miss_word"),
239	r_icache_miss_inval("r_icache_miss_inval"),
240
241	r_icache_cc_way("r_icache_cc_way"),
242	r_icache_cc_set("r_icache_cc_set"),
243	r_icache_cc_word("r_icache_cc_word"),
244
245	r_icache_flush_count("r_icache_flush_count"),
246
247	r_icache_miss_req("r_icache_miss_req"),
248	r_icache_unc_req("r_icache_unc_req"),
249
250	r_icache_tlb_miss_req("r_icache_tlb_read_req"),
251	r_icache_tlb_rsp_error("r_icache_tlb_rsp_error"),
252
253	r_icache_cleanup_req("r_icache_cleanup_req"),
254	r_icache_cleanup_line("r_icache_cleanup_line"),
255
256	r_dcache_fsm("r_dcache_fsm"),
257	r_dcache_fsm_cc_save("r_dcache_fsm_cc_save"),
258	r_dcache_fsm_scan_save("r_dcache_fsm_scan_save"),
259
260	r_dcache_p0_valid("r_dcache_p0_valid"),
261	r_dcache_p0_vaddr("r_dcache_p0_vaddr"),
262	r_dcache_p0_wdata("r_dcache_p0_wdata"),
263	r_dcache_p0_be("r_dcache_p0_be"),
264	r_dcache_p0_paddr("r_dcache_p0_paddr"),
265	r_dcache_p0_cacheable("r_dcache_p0_cacheable"),
266
267	r_dcache_p1_valid("r_dcache_p1_valid"),
268	r_dcache_p1_wdata("r_dcache_p1_wdata"),
269	r_dcache_p1_be("r_dcache_p1_be"),
270	r_dcache_p1_paddr("r_dcache_p1_paddr"),
271	r_dcache_p1_cache_way("r_dcache_p1_cache_way"),
272	r_dcache_p1_cache_set("r_dcache_p1_cache_set"),
273	r_dcache_p1_cache_word("r_dcache_p1_word_save"),
274
275	r_dcache_dirty_paddr("r_dcache_dirty_paddr"),
276	r_dcache_dirty_way("r_dcache_dirty_way"),
277	r_dcache_dirty_set("r_dcache_dirty_set"),
278
279	r_dcache_vci_paddr("r_dcache_vci_paddr"),
280	r_dcache_vci_miss_req("r_dcache_vci_miss_req"),
281	r_dcache_vci_unc_req("r_dcache_vci_unc_req"),
282	r_dcache_vci_unc_be("r_dcache_vci_unc_be"),
283	r_dcache_vci_cas_req("r_dcache_vci_cas_req"),
284	r_dcache_vci_cas_old("r_dcache_vci_cas_old"),
285	r_dcache_vci_cas_new("r_dcache_vci_cas_new"),
286	r_dcache_vci_ll_req("r_dcache_vci_ll_req"),
287	r_dcache_vci_sc_req("r_dcache_vci_sc_req"),
288	r_dcache_vci_sc_data("r_dcache_vci_sc_data"),
289
290	r_dcache_xtn_way("r_dcache_xtn_way"),
291	r_dcache_xtn_set("r_dcache_xtn_set"),
292
293	r_dcache_pending_unc_write("r_dcache_pending_unc_write"),
294
295	r_dcache_miss_type("r_dcache_miss_type"),
296	r_dcache_miss_word("r_dcache_miss_word"),
297	r_dcache_miss_way("r_dcache_miss_way"),
298	r_dcache_miss_set("r_dcache_miss_set"),
299	r_dcache_miss_inval("r_dcache_miss_inval"),
300
301	r_dcache_cc_way("r_dcache_cc_way"),
302	r_dcache_cc_set("r_dcache_cc_set"),
303	r_dcache_cc_word("r_dcache_cc_word"),
304
305	r_dcache_flush_count("r_dcache_flush_count"),
306
307	r_dcache_tlb_vaddr("r_dcache_tlb_vaddr"),
308	r_dcache_tlb_ins("r_dcache_tlb_ins"),
309	r_dcache_tlb_pte_flags("r_dcache_tlb_pte_flags"),
310	r_dcache_tlb_pte_ppn("r_dcache_tlb_pte_ppn"),
311	r_dcache_tlb_cache_way("r_dcache_tlb_cache_way"),
312	r_dcache_tlb_cache_set("r_dcache_tlb_cache_set"),
313	r_dcache_tlb_cache_word("r_dcache_tlb_cache_word"),
314	r_dcache_tlb_way("r_dcache_tlb_way"),
315	r_dcache_tlb_set("r_dcache_tlb_set"),
316
317	r_dcache_tlb_inval_line("r_dcache_tlb_inval_line"),
318	r_dcache_tlb_inval_count("r_dcache_tlb_inval_count"),
319
320	r_dcache_xtn_req("r_dcache_xtn_req"),
321	r_dcache_xtn_opcode("r_dcache_xtn_opcode"),
322
323	r_dcache_cleanup_req("r_dcache_cleanup_req"),
324	r_dcache_cleanup_line("r_dcache_cleanup_line"),
325
326	r_vci_cmd_fsm("r_vci_cmd_fsm"),
327	r_vci_cmd_min("r_vci_cmd_min"),
328	r_vci_cmd_max("r_vci_cmd_max"),
329	r_vci_cmd_cpt("r_vci_cmd_cpt"),
330	r_vci_cmd_imiss_prio("r_vci_cmd_imiss_prio"),
331
332	r_vci_rsp_fsm("r_vci_rsp_fsm"),
333	r_vci_rsp_cpt("r_vci_rsp_cpt"),
334	r_vci_rsp_ins_error("r_vci_rsp_ins_error"),
335	r_vci_rsp_data_error("r_vci_rsp_data_error"),
336	r_vci_rsp_fifo_icache("r_vci_rsp_fifo_icache", 2), // 2 words depth
337	r_vci_rsp_fifo_dcache("r_vci_rsp_fifo_dcache", 2), // 2 words depth
338
339	r_cleanup_fsm("r_cleanup_fsm"),
340	r_cleanup_trdid("r_cleanup_trdid"),
341	r_cleanup_buffer(4), // up to 4 simultaneous cleanups
342
343	r_tgt_fsm("r_tgt_fsm"),
344	r_tgt_paddr("r_tgt_paddr"),
345	r_tgt_word_count("r_tgt_word_count"),
346	r_tgt_word_min("r_tgt_word_min"),
347	r_tgt_word_max("r_tgt_word_max"),
348	r_tgt_update("r_tgt_update"),
349	r_tgt_update_data("r_tgt_update_data"),
350	r_tgt_srcid("r_tgt_srcid"),
351	r_tgt_pktid("r_tgt_pktid"),
352	r_tgt_trdid("r_tgt_trdid"),
353
354	r_tgt_icache_req("r_tgt_icache_req"),
355	r_tgt_dcache_req("r_tgt_dcache_req"),
356	r_tgt_icache_rsp("r_tgt_icache_rsp"),
357	r_tgt_dcache_rsp("r_tgt_dcache_rsp"),
358
359	r_iss(this->name(), proc_id),
360	r_wbuf("wbuf", wbuf_nwords, wbuf_nlines, dcache_words ),
361	r_icache("icache", icache_ways, icache_sets, icache_words),
362	r_dcache("dcache", dcache_ways, dcache_sets, dcache_words),
363	r_itlb("itlb", proc_id, itlb_ways,itlb_sets,vci_param::N),
364	r_dtlb("dtlb", proc_id, dtlb_ways,dtlb_sets,vci_param::N)
365	{
366	assert( ((icache_words*vci_param::B) < (1<<vci_param::K)) and
367	"Need more PLEN bits.");
368
369	assert( (vci_param::T > 2) and ((1<<(vci_param::T-1)) >= (wbuf_nlines)) and
370	"Need more TRDID bits.");
371
372	assert( (icache_words == dcache_words) and
373	"icache_words and dcache_words parameters must be equal");
374
375	assert( (itlb_sets == dtlb_sets) and
376	"itlb_sets and dtlb_sets parameters must be etqual");
377
378	assert( (itlb_ways == dtlb_ways) and
379	"itlb_ways and dtlb_ways parameters must be etqual");
380
381	r_mmu_params = (uint32_log2(m_dtlb_ways) << 29) \| (uint32_log2(m_dtlb_sets) << 25) \|
382	(uint32_log2(m_dcache_ways) << 22) \| (uint32_log2(m_dcache_sets) << 18) \|
383	(uint32_log2(m_itlb_ways) << 15) \| (uint32_log2(m_itlb_sets) << 11) \|
384	(uint32_log2(m_icache_ways) << 8) \| (uint32_log2(m_icache_sets) << 4) \|
385	(uint32_log2(m_icache_words<<2));
386
387	r_mmu_release = (uint32_t)(1 << 16) \| 0x1;
388
389	r_tgt_buf = new uint32_t[dcache_words];
390	r_tgt_be = new vci_be_t[dcache_words];
391	r_dcache_in_tlb = new bool[dcache_ways*dcache_sets];
392	r_dcache_contains_ptd = new bool[dcache_ways*dcache_sets];
393
394	SC_METHOD(transition);
395	dont_initialize();
396	sensitive << p_clk.pos();
397
398	SC_METHOD(genMoore);
399	dont_initialize();
400	sensitive << p_clk.neg();
401
402	typename iss_t::CacheInfo cache_info;
403	cache_info.has_mmu = true;
404	cache_info.icache_line_size = icache_words*sizeof(uint32_t);
405	cache_info.icache_assoc = icache_ways;
406	cache_info.icache_n_lines = icache_sets;
407	cache_info.dcache_line_size = dcache_words*sizeof(uint32_t);
408	cache_info.dcache_assoc = dcache_ways;
409	cache_info.dcache_n_lines = dcache_sets;
410	r_iss.setCacheInfo(cache_info);
411	}
412
413	/////////////////////////////////////
414	tmpl(/**/)::~VciCcVCacheWrapperV4()
415	/////////////////////////////////////
416	{
417	delete [] r_tgt_be;
418	delete [] r_tgt_buf;
419	delete [] r_dcache_in_tlb;
420	delete [] r_dcache_contains_ptd;
421	}
422
423	////////////////////////
424	tmpl(void)::print_cpi()
425	////////////////////////
426	{
427	std::cout << name() << " CPI = "
428	<< (float)m_cpt_total_cycles/(m_cpt_total_cycles - m_cpt_frz_cycles) << std::endl ;
429	}
430
431	////////////////////////////////////
432	tmpl(void)::print_trace(size_t mode)
433	////////////////////////////////////
434	{
435	// b0 : write buffer trace
436	// b1 : write buffer verbose
437	// b2 : dcache trace
438	// b3 : icache trace
439	// b4 : dtlb trace
440	// b5 : itlb trace
441
442	std::cout << std::dec << "PROC " << name() << std::endl;
443
444	std::cout << " " << m_ireq << std::endl;
445	std::cout << " " << m_irsp << std::endl;
446	std::cout << " " << m_dreq << std::endl;
447	std::cout << " " << m_drsp << std::endl;
448
449	std::cout << " " << icache_fsm_state_str[r_icache_fsm.read()]
450	<< " \| " << dcache_fsm_state_str[r_dcache_fsm.read()]
451	<< " \| " << cmd_fsm_state_str[r_vci_cmd_fsm.read()]
452	<< " \| " << rsp_fsm_state_str[r_vci_rsp_fsm.read()]
453	<< " \| " << tgt_fsm_state_str[r_tgt_fsm.read()]
454	<< " \| " << cleanup_fsm_state_str[r_cleanup_fsm.read()];
455	if (r_dcache_p0_valid.read() ) std::cout << " \| P1_WRITE";
456	if (r_dcache_p1_valid.read() ) std::cout << " \| P2_WRITE";
457	std::cout << std::endl;
458
459	if(mode & 0x01)
460	{
461	r_wbuf.printTrace((mode>>1)&1);
462	}
463	if(mode & 0x04)
464	{
465	std::cout << " Data Cache" << std::endl;
466	r_dcache.printTrace();
467	}
468	if(mode & 0x08)
469	{
470	std::cout << " Instruction Cache" << std::endl;
471	r_icache.printTrace();
472	}
473	if(mode & 0x10)
474	{
475	std::cout << " Data TLB" << std::endl;
476	r_dtlb.printTrace();
477	}
478	if(mode & 0x20)
479	{
480	std::cout << " Instruction TLB" << std::endl;
481	r_itlb.printTrace();
482	}
483	}
484
485	//////////////////////////////////////////
486	tmpl(void)::cache_monitor( paddr_t addr )
487	//////////////////////////////////////////
488	{
489	size_t cache_way;
490	size_t cache_set;
491	size_t cache_word;
492	uint32_t cache_rdata;
493	bool cache_hit = r_dcache.read_neutral( addr,
494	&cache_rdata,
495	&cache_way,
496	&cache_set,
497	&cache_word );
498	bool icache_hit = r_icache.read_neutral( addr,
499	&cache_rdata,
500	&cache_way,
501	&cache_set,
502	&cache_word );
503	if ( cache_hit != m_debug_previous_hit )
504	{
505	std::cout << "PROC " << name()
506	<< " dcache change at cycle " << std::dec << m_cpt_total_cycles
507	<< " for adresse " << std::hex << addr
508	<< " / HIT = " << std::dec << cache_hit << std::endl;
509	m_debug_previous_hit = cache_hit;
510	}
511	if ( icache_hit != m_idebug_previous_hit )
512	{
513	std::cout << "PROC " << name()
514	<< " icache change at cycle " << std::dec << m_cpt_total_cycles
515	<< " for adresse " << std::hex << addr
516	<< " / HIT = " << icache_hit << std::endl;
517	m_idebug_previous_hit = icache_hit;
518	}
519	}
520
521	/*
522	////////////////////////
523	tmpl(void)::print_stats()
524	////////////////////////
525	{
526	float run_cycles = (float)(m_cpt_total_cycles - m_cpt_frz_cycles);
527	std::cout << name() << std::endl
528	<< "- CPI = " << (float)m_cpt_total_cycles/run_cycles << std::endl
529	<< "- READ RATE = " << (float)m_cpt_read/run_cycles << std::endl
530	<< "- WRITE RATE = " << (float)m_cpt_write/run_cycles << std::endl
531	<< "- IMISS_RATE = " << (float)m_cpt_ins_miss/m_cpt_ins_read << std::endl
532	<< "- DMISS RATE = " << (float)m_cpt_data_miss/(m_cpt_read-m_cpt_unc_read) << std::endl
533	<< "- INS MISS COST = " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl
534	<< "- DATA MISS COST = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl
535	<< "- WRITE COST = " << (float)m_cost_write_frz/m_cpt_write << std::endl
536	<< "- UNC COST = " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl
537	<< "- UNCACHED READ RATE = " << (float)m_cpt_unc_read/m_cpt_read << std::endl
538	<< "- CACHED WRITE RATE = " << (float)m_cpt_write_cached/m_cpt_write << std::endl
539	<< "- INS TLB MISS RATE = " << (float)m_cpt_ins_tlb_miss/m_cpt_ins_tlb_read << std::endl
540	<< "- DATA TLB MISS RATE = " << (float)m_cpt_data_tlb_miss/m_cpt_data_tlb_read << std::endl
541	<< "- ITLB MISS COST = " << (float)m_cost_ins_tlb_miss_frz/m_cpt_ins_tlb_miss << std::endl
542	<< "- DTLB MISS COST = " << (float)m_cost_data_tlb_miss_frz/m_cpt_data_tlb_miss << std::endl
543	<< "- ITLB UPDATE ACC COST = " << (float)m_cost_ins_tlb_update_acc_frz/m_cpt_ins_tlb_update_acc << std::endl
544	<< "- DTLB UPDATE ACC COST = " << (float)m_cost_data_tlb_update_acc_frz/m_cpt_data_tlb_update_acc << std::endl
545	<< "- DTLB UPDATE DIRTY COST = " << (float)m_cost_data_tlb_update_dirty_frz/m_cpt_data_tlb_update_dirty << std::endl
546	<< "- ITLB HIT IN DCACHE RATE= " << (float)m_cpt_ins_tlb_hit_dcache/m_cpt_ins_tlb_miss << std::endl
547	<< "- DTLB HIT IN DCACHE RATE= " << (float)m_cpt_data_tlb_hit_dcache/m_cpt_data_tlb_miss << std::endl
548	<< "- DCACHE FROZEN BY ITLB = " << (float)m_cost_ins_tlb_occup_cache_frz/m_cpt_dcache_frz_cycles << std::endl
549	<< "- DCACHE FOR TLB % = " << (float)m_cpt_tlb_occup_dcache/(m_dcache_ways*m_dcache_sets) << std::endl
550	<< "- NB CC BROADCAST = " << m_cpt_cc_broadcast << std::endl
551	<< "- NB CC UPDATE DATA = " << m_cpt_cc_update_data << std::endl
552	<< "- NB CC INVAL DATA = " << m_cpt_cc_inval_data << std::endl
553	<< "- NB CC INVAL INS = " << m_cpt_cc_inval_ins << std::endl
554	<< "- CC BROADCAST COST = " << (float)m_cost_broadcast_frz/m_cpt_cc_broadcast << std::endl
555	<< "- CC UPDATE DATA COST = " << (float)m_cost_updt_data_frz/m_cpt_cc_update_data << std::endl
556	<< "- CC INVAL DATA COST = " << (float)m_cost_inval_data_frz/m_cpt_cc_inval_data << std::endl
557	<< "- CC INVAL INS COST = " << (float)m_cost_inval_ins_frz/m_cpt_cc_inval_ins << std::endl
558	<< "- NB CC CLEANUP DATA = " << m_cpt_cc_cleanup_data << std::endl
559	<< "- NB CC CLEANUP INS = " << m_cpt_cc_cleanup_ins << std::endl
560	<< "- IMISS TRANSACTION = " << (float)m_cost_imiss_transaction/m_cpt_imiss_transaction << std::endl
561	<< "- DMISS TRANSACTION = " << (float)m_cost_dmiss_transaction/m_cpt_dmiss_transaction << std::endl
562	<< "- UNC TRANSACTION = " << (float)m_cost_unc_transaction/m_cpt_unc_transaction << std::endl
563	<< "- WRITE TRANSACTION = " << (float)m_cost_write_transaction/m_cpt_write_transaction << std::endl
564	<< "- WRITE LENGTH = " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl
565	<< "- ITLB MISS TRANSACTION = " << (float)m_cost_itlbmiss_transaction/m_cpt_itlbmiss_transaction << std::endl
566	<< "- DTLB MISS TRANSACTION = " << (float)m_cost_dtlbmiss_transaction/m_cpt_dtlbmiss_transaction << std::endl;
567	}
568
569	////////////////////////
570	tmpl(void)::clear_stats()
571	////////////////////////
572	{
573	m_cpt_dcache_data_read = 0;
574	m_cpt_dcache_data_write = 0;
575	m_cpt_dcache_dir_read = 0;
576	m_cpt_dcache_dir_write = 0;
577	m_cpt_icache_data_read = 0;
578	m_cpt_icache_data_write = 0;
579	m_cpt_icache_dir_read = 0;
580	m_cpt_icache_dir_write = 0;
581
582	m_cpt_frz_cycles = 0;
583	m_cpt_dcache_frz_cycles = 0;
584	m_cpt_total_cycles = 0;
585
586	m_cpt_read = 0;
587	m_cpt_write = 0;
588	m_cpt_data_miss = 0;
589	m_cpt_ins_miss = 0;
590	m_cpt_unc_read = 0;
591	m_cpt_write_cached = 0;
592	m_cpt_ins_read = 0;
593
594	m_cost_write_frz = 0;
595	m_cost_data_miss_frz = 0;
596	m_cost_unc_read_frz = 0;
597	m_cost_ins_miss_frz = 0;
598
599	m_cpt_imiss_transaction = 0;
600	m_cpt_dmiss_transaction = 0;
601	m_cpt_unc_transaction = 0;
602	m_cpt_write_transaction = 0;
603	m_cpt_icache_unc_transaction = 0;
604
605	m_cost_imiss_transaction = 0;
606	m_cost_dmiss_transaction = 0;
607	m_cost_unc_transaction = 0;
608	m_cost_write_transaction = 0;
609	m_cost_icache_unc_transaction = 0;
610	m_length_write_transaction = 0;
611
612	m_cpt_ins_tlb_read = 0;
613	m_cpt_ins_tlb_miss = 0;
614	m_cpt_ins_tlb_update_acc = 0;
615
616	m_cpt_data_tlb_read = 0;
617	m_cpt_data_tlb_miss = 0;
618	m_cpt_data_tlb_update_acc = 0;
619	m_cpt_data_tlb_update_dirty = 0;
620	m_cpt_ins_tlb_hit_dcache = 0;
621	m_cpt_data_tlb_hit_dcache = 0;
622	m_cpt_ins_tlb_occup_cache = 0;
623	m_cpt_data_tlb_occup_cache = 0;
624
625	m_cost_ins_tlb_miss_frz = 0;
626	m_cost_data_tlb_miss_frz = 0;
627	m_cost_ins_tlb_update_acc_frz = 0;
628	m_cost_data_tlb_update_acc_frz = 0;
629	m_cost_data_tlb_update_dirty_frz = 0;
630	m_cost_ins_tlb_occup_cache_frz = 0;
631	m_cost_data_tlb_occup_cache_frz = 0;
632
633	m_cpt_itlbmiss_transaction = 0;
634	m_cpt_itlb_ll_transaction = 0;
635	m_cpt_itlb_sc_transaction = 0;
636	m_cpt_dtlbmiss_transaction = 0;
637	m_cpt_dtlb_ll_transaction = 0;
638	m_cpt_dtlb_sc_transaction = 0;
639	m_cpt_dtlb_ll_dirty_transaction = 0;
640	m_cpt_dtlb_sc_dirty_transaction = 0;
641
642	m_cost_itlbmiss_transaction = 0;
643	m_cost_itlb_ll_transaction = 0;
644	m_cost_itlb_sc_transaction = 0;
645	m_cost_dtlbmiss_transaction = 0;
646	m_cost_dtlb_ll_transaction = 0;
647	m_cost_dtlb_sc_transaction = 0;
648	m_cost_dtlb_ll_dirty_transaction = 0;
649	m_cost_dtlb_sc_dirty_transaction = 0;
650
651	m_cpt_cc_update_data = 0;
652	m_cpt_cc_inval_ins = 0;
653	m_cpt_cc_inval_data = 0;
654	m_cpt_cc_broadcast = 0;
655
656	m_cost_updt_data_frz = 0;
657	m_cost_inval_ins_frz = 0;
658	m_cost_inval_data_frz = 0;
659	m_cost_broadcast_frz = 0;
660
661	m_cpt_cc_cleanup_data = 0;
662	m_cpt_cc_cleanup_ins = 0;
663	}
664
665	*/
666
667	/////////////////////////
668	tmpl(void)::transition()
669	/////////////////////////
670	{
671	#define LLSCLocalTable GenericLLSCLocalTable<8000, 1, paddr_t, vci_trdid_t, vci_data_t>
672	if ( not p_resetn.read() )
673	{
674	r_iss.reset();
675	r_wbuf.reset();
676	r_icache.reset();
677	r_dcache.reset();
678	r_itlb.reset();
679	r_dtlb.reset();
680
681	r_dcache_fsm = DCACHE_IDLE;
682	r_icache_fsm = ICACHE_IDLE;
683	r_vci_cmd_fsm = CMD_IDLE;
684	r_vci_rsp_fsm = RSP_IDLE;
685	r_tgt_fsm = TGT_IDLE;
686	r_cleanup_fsm = CLEANUP_DATA_IDLE;
687
688	// reset dcache directory extension
689	for (size_t i=0 ; i< m_dcache_ways*m_dcache_sets ; i++)
690	{
691	r_dcache_in_tlb[i] = false;
692	r_dcache_contains_ptd[i] = false;
693	}
694
695	// Response FIFOs and cleanup buffer
696	r_vci_rsp_fifo_icache.init();
697	r_vci_rsp_fifo_dcache.init();
698	r_cleanup_buffer.reset();
699
700	// ICACHE & DCACHE activated
701	r_mmu_mode = 0x3;
702
703	// No request from ICACHE FSM to CMD FSM
704	r_icache_miss_req = false;
705	r_icache_unc_req = false;
706
707	// No request from ICACHE_FSM to DCACHE FSM
708	r_icache_tlb_miss_req = false;
709
710	// No request from ICACHE_FSM to CLEANUP FSMs
711	r_icache_cleanup_req = false;
712
713	// No pending write in pipeline
714	r_dcache_p0_valid = false;
715	r_dcache_p1_valid = false;
716
717	// No request from DCACHE_FSM to CMD_FSM
718	r_dcache_vci_miss_req = false;
719	r_dcache_vci_unc_req = false;
720	r_dcache_vci_cas_req = false;
721	r_dcache_vci_ll_req = false;
722	r_dcache_vci_sc_req = false;
723
724	// No uncacheable write pending
725	r_dcache_pending_unc_write = false;
726
727	// No processor XTN request pending
728	r_dcache_xtn_req = false;
729
730	// No request from DCACHE FSM to CLEANUP FSMs
731	r_dcache_cleanup_req = false;
732
733	// No request from TGT FSM to ICACHE/DCACHE FSMs
734	r_tgt_icache_req = false;
735	r_tgt_dcache_req = false;
736
737	// No signalisation of a coherence request matching a pending miss
738	r_icache_miss_inval = false;
739	r_dcache_miss_inval = false;
740
741	// No signalisation of errors
742	r_vci_rsp_ins_error = false;
743	r_vci_rsp_data_error = false;
744
745	// Debug variables
746	m_debug_previous_hit = false;
747	m_idebug_previous_hit = false;
748	m_debug_dcache_fsm = false;
749	m_debug_icache_fsm = false;
750	m_debug_cleanup_fsm = false;
751
752	// activity counters
753	m_cpt_dcache_data_read = 0;
754	m_cpt_dcache_data_write = 0;
755	m_cpt_dcache_dir_read = 0;
756	m_cpt_dcache_dir_write = 0;
757	m_cpt_icache_data_read = 0;
758	m_cpt_icache_data_write = 0;
759	m_cpt_icache_dir_read = 0;
760	m_cpt_icache_dir_write = 0;
761
762	m_cpt_frz_cycles = 0;
763	m_cpt_total_cycles = 0;
764	m_cpt_stop_simulation = 0;
765
766	m_cpt_data_miss = 0;
767	m_cpt_ins_miss = 0;
768	m_cpt_unc_read = 0;
769	m_cpt_write_cached = 0;
770	m_cpt_ins_read = 0;
771
772	m_cost_write_frz = 0;
773	m_cost_data_miss_frz = 0;
774	m_cost_unc_read_frz = 0;
775	m_cost_ins_miss_frz = 0;
776
777	m_cpt_imiss_transaction = 0;
778	m_cpt_dmiss_transaction = 0;
779	m_cpt_unc_transaction = 0;
780	m_cpt_write_transaction = 0;
781	m_cpt_icache_unc_transaction = 0;
782
783	m_cost_imiss_transaction = 0;
784	m_cost_dmiss_transaction = 0;
785	m_cost_unc_transaction = 0;
786	m_cost_write_transaction = 0;
787	m_cost_icache_unc_transaction = 0;
788	m_length_write_transaction = 0;
789
790	m_cpt_ins_tlb_read = 0;
791	m_cpt_ins_tlb_miss = 0;
792	m_cpt_ins_tlb_update_acc = 0;
793
794	m_cpt_data_tlb_read = 0;
795	m_cpt_data_tlb_miss = 0;
796	m_cpt_data_tlb_update_acc = 0;
797	m_cpt_data_tlb_update_dirty = 0;
798	m_cpt_ins_tlb_hit_dcache = 0;
799	m_cpt_data_tlb_hit_dcache = 0;
800	m_cpt_ins_tlb_occup_cache = 0;
801	m_cpt_data_tlb_occup_cache = 0;
802
803	m_cost_ins_tlb_miss_frz = 0;
804	m_cost_data_tlb_miss_frz = 0;
805	m_cost_ins_tlb_update_acc_frz = 0;
806	m_cost_data_tlb_update_acc_frz = 0;
807	m_cost_data_tlb_update_dirty_frz = 0;
808	m_cost_ins_tlb_occup_cache_frz = 0;
809	m_cost_data_tlb_occup_cache_frz = 0;
810
811	m_cpt_ins_tlb_inval = 0;
812	m_cpt_data_tlb_inval = 0;
813	m_cost_ins_tlb_inval_frz = 0;
814	m_cost_data_tlb_inval_frz = 0;
815
816	m_cpt_cc_broadcast = 0;
817
818	m_cost_updt_data_frz = 0;
819	m_cost_inval_ins_frz = 0;
820	m_cost_inval_data_frz = 0;
821	m_cost_broadcast_frz = 0;
822
823	m_cpt_cc_cleanup_data = 0;
824	m_cpt_cc_cleanup_ins = 0;
825
826	m_cpt_itlbmiss_transaction = 0;
827	m_cpt_itlb_ll_transaction = 0;
828	m_cpt_itlb_sc_transaction = 0;
829	m_cpt_dtlbmiss_transaction = 0;
830	m_cpt_dtlb_ll_transaction = 0;
831	m_cpt_dtlb_sc_transaction = 0;
832	m_cpt_dtlb_ll_dirty_transaction = 0;
833	m_cpt_dtlb_sc_dirty_transaction = 0;
834
835	m_cost_itlbmiss_transaction = 0;
836	m_cost_itlb_ll_transaction = 0;
837	m_cost_itlb_sc_transaction = 0;
838	m_cost_dtlbmiss_transaction = 0;
839	m_cost_dtlb_ll_transaction = 0;
840	m_cost_dtlb_sc_transaction = 0;
841	m_cost_dtlb_ll_dirty_transaction = 0;
842	m_cost_dtlb_sc_dirty_transaction = 0;
843	/*
844	m_cpt_dcache_frz_cycles = 0;
845	m_cpt_read = 0;
846	m_cpt_write = 0;
847	m_cpt_cc_update_data = 0;
848	m_cpt_cc_inval_ins = 0;
849	m_cpt_cc_inval_data = 0;
850	*/
851
852	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_icache [i] = 0;
853	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_dcache [i] = 0;
854	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_cmd [i] = 0;
855	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_rsp [i] = 0;
856	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_tgt [i] = 0;
857	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_cmd_cleanup [i] = 0;
858	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_rsp_cleanup [i] = 0;
859
860	// init the llsc local registration table
861	r_llsc_table.init();
862
863	return;
864	}
865
866	// Response FIFOs default values
867	bool vci_rsp_fifo_icache_get = false;
868	bool vci_rsp_fifo_icache_put = false;
869	uint32_t vci_rsp_fifo_icache_data = 0;
870
871	bool vci_rsp_fifo_dcache_get = false;
872	bool vci_rsp_fifo_dcache_put = false;
873	uint32_t vci_rsp_fifo_dcache_data = 0;
874
875	#ifdef INSTRUMENTATION
876	m_cpt_fsm_dcache [r_dcache_fsm.read() ] ++;
877	m_cpt_fsm_icache [r_icache_fsm.read() ] ++;
878	m_cpt_fsm_cmd [r_vci_cmd_fsm.read()] ++;
879	m_cpt_fsm_rsp [r_vci_rsp_fsm.read()] ++;
880	m_cpt_fsm_tgt [r_tgt_fsm.read() ] ++;
881	m_cpt_fsm_cleanup [r_cleanup_fsm.read()] ++;
882	#endif
883
884	m_cpt_total_cycles++;
885
886	m_debug_cleanup_fsm = m_debug_cleanup_fsm \|\|
887	((m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok);
888	m_debug_icache_fsm = m_debug_icache_fsm \|\|
889	((m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok);
890	m_debug_dcache_fsm = m_debug_dcache_fsm \|\|
891	((m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok);
892
893	/////////////////////////////////////////////////////////////////////
894	// The TGT_FSM controls the following ressources:
895	// - r_tgt_fsm
896	// - r_tgt_buf[nwords]
897	// - r_tgt_be[nwords]
898	// - r_tgt_update
899	// - r_tgt_word_min
900	// - r_tgt_word_max
901	// - r_tgt_word_count
902	// - r_tgt_paddr
903	// - r_tgt_srcid
904	// - r_tgt_trdid
905	// - r_tgt_pktid
906	// - r_tgt_icache_req (set)
907	// - r_tgt_dcache_req (set)
908	//
909	// All VCI commands must be CMD_WRITE.
910	// - If the 2 LSB bits of the VCI address are 11, it is a broadcast request.
911	// It is a multicast request otherwise.
912	// - For multicast requests, the ADDRESS[2] bit distinguishes DATA/INS
913	// (0 for data / 1 for instruction), and the ADDRESS[3] bit distinguishes
914	// INVAL/UPDATE (0 for invalidate / 1 for UPDATE).
915	//
916	// For all types of coherence request, the line index (i.e. the Z & Y fields)
917	// is coded on 34 bits, and is contained in the WDATA and BE fields
918	// of the first VCI flit.
919	// - for a multicast invalidate or for a broadcast invalidate request
920	// the VCI packet length is 1 word.
921	// - for an update request the VCI packet length is (n+2) words.
922	// The WDATA field of the second VCI word contains the word index.
923	// The WDATA field of the n following words contains the values.
924	// - for all transaction types, the VCI response is one single word.
925	// In case of errors in the VCI command packet, the simulation
926	// is stopped with an error message.
927	//
928	// This FSM is NOT pipelined : It consumes a new coherence request
929	// on the VCI port only when the previous request is completed.
930	//
931	// The VCI_TGT FSM stores the external request arguments in the
932	// IDLE, UPDT_WORD & UPDT_DATA states. It sets the r_tgt_icache_req
933	// and/or the r_tgt_dcache_req flip-flops to signal the coherence request
934	// to the ICACHE & DCACHE FSMs in the REQ_ICACHE, REQ_DCACHE & REQ_BROADCAST
935	// states. It waits the completion of the coherence request by polling the
936	// r_tgt_*cache_req flip-flops in the RSP_ICACHE, RSP_DCACHE & RSP_BROADCAST
937	// states. These flip-flops are reset by the ICACHE and DCACHE FSMs.
938	// These two FSMs signal if a VCI answer must be send by setting
939	// the r_tgt_icache_rsp and/or the r_tgt_dcache_rsp flip_flops.
940	///////////////////////////////////////////////////////////////////////////////
941
942	switch( r_tgt_fsm.read() )
943	{
944	//////////////
945	case TGT_IDLE:
946	{
947	if ( p_vci_tgt_c.cmdval.read() )
948	{
949	paddr_t address = p_vci_tgt_c.address.read();
950
951	// command checking
952	if ( p_vci_tgt_c.cmd.read() != vci_param::CMD_WRITE)
953	{
954	std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
955	std::cout << "the received VCI coherence command is not a write" << std::endl;
956	exit(0);
957	}
958
959	// address checking
960	if ( ( (address & 0x3) != 0x3 ) && ( not m_segment.contains(address)) )
961	{
962	std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
963	std::cout << "out of segment VCI coherence command received" << std::endl;
964	exit(0);
965	}
966
967	r_tgt_srcid = p_vci_tgt_c.srcid.read();
968	r_tgt_trdid = p_vci_tgt_c.trdid.read();
969	r_tgt_pktid = p_vci_tgt_c.pktid.read();
970
971	if (sizeof(paddr_t) <= 32)
972	{
973	assert(p_vci_tgt_c.be.read() == 0
974	&& "byte enable should be 0 for 32bits paddr");
975	r_tgt_paddr = (paddr_t)p_vci_tgt_c.wdata.read() * m_dcache_words * 4;
976	}
977	else
978	{
979	r_tgt_paddr = (paddr_t)(p_vci_tgt_c.be.read() & 0x3) << 32 \|
980	(paddr_t)p_vci_tgt_c.wdata.read() * m_dcache_words * 4;
981	}
982
983	if ( (address&0x3) == 0x3 ) // broadcast invalidate for data or instruction type
984	{
985	if ( not p_vci_tgt_c.eop.read() )
986	{
987	std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
988	std::cout << "the BROADCAST INVALIDATE command must be one flit" << std::endl;
989	exit(0);
990	}
991	r_tgt_update = false;
992	r_tgt_fsm = TGT_REQ_BROADCAST;
993
994	#ifdef INSTRUMENTATION
995	m_cpt_cc_broadcast++;
996	#endif
997	}
998	else // multi-update or multi-invalidate for data type
999	{
1000	paddr_t cell = address - m_segment.baseAddress();
1001
1002	if (cell == 0) // invalidate data
1003	{
1004	if ( not p_vci_tgt_c.eop.read() )
1005	{
1006	std::cout << "error in VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
1007	std::cout << "the MULTI-INVALIDATE command must be one flit" << std::endl;
1008	exit(0);
1009	}
1010	r_tgt_update = false;
1011	r_tgt_fsm = TGT_REQ_DCACHE;
1012
1013	#ifdef INSTRUMENTATION
1014	m_cpt_cc_inval_dcache++;
1015	#endif
1016	}
1017	else if (cell == 4) // invalidate instruction
1018	{
1019	if ( not p_vci_tgt_c.eop.read() )
1020	{
1021	std::cout << "error in VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
1022	std::cout << "the MULTI-INVALIDATE command must be one flit" << std::endl;
1023	exit(0);
1024	}
1025	r_tgt_update = false;
1026	r_tgt_fsm = TGT_REQ_ICACHE;
1027
1028	#ifdef INSTRUMENTATION
1029	m_cpt_cc_inval_icache++;
1030	#endif
1031	}
1032	else if (cell == 8) // update data
1033	{
1034	if ( p_vci_tgt_c.eop.read() )
1035	{
1036	std::cout << "error in VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
1037	std::cout << "the MULTI-UPDATE command must be N+2 flits" << std::endl;
1038	exit(0);
1039	}
1040	r_tgt_update = true;
1041	r_tgt_update_data = true;
1042	r_tgt_fsm = TGT_UPDT_WORD;
1043
1044	#ifdef INSTRUMENTATION
1045	m_cpt_cc_update_dcache++;
1046	#endif
1047	}
1048	else // update instruction
1049	{
1050	if ( p_vci_tgt_c.eop.read() )
1051	{
1052	std::cout << "error in VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
1053	std::cout << "the MULTI-UPDATE command must be N+2 flits" << std::endl;
1054	exit(0);
1055	}
1056	r_tgt_update = true;
1057	r_tgt_update_data = false;
1058	r_tgt_fsm = TGT_UPDT_WORD;
1059
1060	#ifdef INSTRUMENTATION
1061	m_cpt_cc_update_icache++;
1062	#endif
1063	}
1064	} // end if multi
1065	} // end if cmdval
1066	break;
1067	}
1068	///////////////////
1069	case TGT_UPDT_WORD: // first word index acquisition
1070	{
1071	if (p_vci_tgt_c.cmdval.read())
1072	{
1073	if ( p_vci_tgt_c.eop.read() )
1074	{
1075	std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
1076	std::cout << "the MULTI-UPDATE command must be N+2 flits" << std::endl;
1077	exit(0);
1078	}
1079	for ( size_t i=0 ; i<m_dcache_words ; i++ ) r_tgt_be[i] = false;
1080
1081	r_tgt_word_min = p_vci_tgt_c.wdata.read(); // first modifid word index
1082	r_tgt_word_count = p_vci_tgt_c.wdata.read(); // initializing word index
1083	r_tgt_fsm = TGT_UPDT_DATA;
1084	}
1085	break;
1086	}
1087	///////////////////
1088	case TGT_UPDT_DATA:
1089	{
1090	if (p_vci_tgt_c.cmdval.read())
1091	{
1092	size_t word = r_tgt_word_count.read();
1093	if (word >= m_dcache_words)
1094	{
1095	std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
1096	std::cout << "the reveived MULTI-UPDATE command is wrong" << std::endl;
1097	exit(0);
1098	}
1099	r_tgt_buf[word] = p_vci_tgt_c.wdata.read();
1100	r_tgt_be[word] = p_vci_tgt_c.be.read();
1101	r_tgt_word_count = word + 1;
1102
1103	if (p_vci_tgt_c.eop.read()) // last word
1104	{
1105	r_tgt_word_max = word;
1106	if ( r_tgt_update_data.read() ) r_tgt_fsm = TGT_REQ_DCACHE;
1107	else r_tgt_fsm = TGT_REQ_ICACHE;
1108	}
1109	}
1110	break;
1111	}
1112	///////////////////////
1113	case TGT_REQ_BROADCAST: // set requests to DCACHE & ICACHE FSMs
1114	{
1115	if ( not r_tgt_icache_req.read() and not r_tgt_dcache_req.read() )
1116	{
1117	r_tgt_fsm = TGT_RSP_BROADCAST;
1118	r_tgt_icache_req = true;
1119	r_tgt_dcache_req = true;
1120	}
1121	break;
1122	}
1123	/////////////////////
1124	case TGT_REQ_ICACHE: // set request to ICACHE FSM (if no previous request pending)
1125	{
1126	if ( not r_tgt_icache_req.read() )
1127	{
1128	r_tgt_fsm = TGT_RSP_ICACHE;
1129	r_tgt_icache_req = true;
1130	}
1131	break;
1132	}
1133	////////////////////
1134	case TGT_REQ_DCACHE: // set request to DCACHE FSM (if no previous request pending)
1135	{
1136	if ( not r_tgt_dcache_req.read() )
1137	{
1138	r_tgt_fsm = TGT_RSP_DCACHE;
1139	r_tgt_dcache_req = true;
1140	}
1141	break;
1142	}
1143	///////////////////////
1144	case TGT_RSP_BROADCAST: // waiting acknowledge from both DCACHE & ICACHE FSMs
1145	// no response when r_tgt_*cache_rsp is false
1146	{
1147	if ( not r_tgt_icache_req.read() and not r_tgt_dcache_req.read() ) // both completed
1148	{
1149	if ( r_tgt_icache_rsp.read() or r_tgt_dcache_rsp.read() ) // at least one response
1150	{
1151	if ( p_vci_tgt_c.rspack.read() )
1152	{
1153	// reset dcache first if activated
1154	if (r_tgt_dcache_rsp) r_tgt_dcache_rsp = false;
1155	else r_tgt_icache_rsp = false;
1156	}
1157	}
1158	else
1159	{
1160	r_tgt_fsm = TGT_IDLE;
1161	}
1162	}
1163	break;
1164	}
1165	////////////////////
1166	case TGT_RSP_ICACHE: // waiting acknowledge from ICACHE FSM
1167	{
1168	// no response when r_tgt_icache_rsp is false
1169	if ( not r_tgt_icache_req.read() and (p_vci_tgt_c.rspack.read() or not r_tgt_icache_rsp.read()))
1170	{
1171	r_tgt_fsm = TGT_IDLE;
1172	r_tgt_icache_rsp = false;
1173	}
1174	break;
1175	}
1176	////////////////////
1177	case TGT_RSP_DCACHE:
1178	{
1179	// no response when r_tgt_dcache_rsp is false
1180	if ( not r_tgt_dcache_req.read() and (p_vci_tgt_c.rspack.read() or not r_tgt_dcache_rsp.read()))
1181	{
1182	r_tgt_fsm = TGT_IDLE;
1183	r_tgt_dcache_rsp = false;
1184	}
1185	break;
1186	}
1187	} // end switch TGT_FSM
1188
1189	/////////////////////////////////////////////////////////////////////
1190	// Get data and instruction requests from processor
1191	///////////////////////////////////////////////////////////////////////
1192
1193	r_iss.getRequests(m_ireq, m_dreq);
1194
1195	////////////////////////////////////////////////////////////////////////////////////
1196	// ICACHE_FSM
1197	//
1198	// There is 9 conditions to exit the IDLE state:
1199	// One condition is a coherence request from TGT FSM :
1200	// - Coherence operation => ICACHE_CC_CHEK
1201	// Five configurations corresponding to XTN processor requests sent by DCACHE FSM :
1202	// - Flush TLB => ICACHE_XTN_TLB_FLUSH
1203	// - Flush cache => ICACHE_XTN_CACHE_FLUSH
1204	// - Invalidate a TLB entry => ICACHE_XTN_TLB_INVAL
1205	// - Invalidate a cache line => ICACHE_XTN_CACHE_INVAL_VA@
1206	// - Invalidate a cache line using physical address => ICACHE_XTN_CACHE_INVAL_PA
1207	// three configurations corresponding to instruction processor requests :
1208	// - tlb miss => ICACHE_TLB_WAIT
1209	// - cacheable read miss => ICACHE_MISS_VICTIM
1210	// - uncacheable read miss => ICACHE_UNC_REQ
1211	//
1212	// In case of cache miss, the ICACHE FSM request a VCI transaction to CMD FSM
1213	// using the r_icache_tlb_miss_req flip-flop, that reset this flip-flop when the
1214	// transaction starts. Then the ICACHE FSM goes to the ICACHE_MISS VICTIM
1215	// state to select a slot and request a VCI transaction to the CLEANUP FSM.
1216	// It goes next to the ICACHE_MISS_WAIT state waiting a response from RSP FSM.
1217	// The availability of the missing cache line is signaled by the response fifo,
1218	// and the cache update is done (one word per cycle) in the ICACHE_MISS_UPDT state.
1219	//
1220	// In case of uncacheable address, the ICACHE FSM request an uncached VCI transaction
1221	// to CMD FSM using the r_icache_unc_req flip-flop, that reset this flip-flop
1222	// when the transaction starts. The ICACHE FSM goes to ICACHE_UNC_WAIT to wait
1223	// the response from the RSP FSM, through the response fifo. The missing instruction
1224	// is directly returned to processor in this state.
1225	//
1226	// In case of tlb miss, the ICACHE FSM request to the DCACHE FSM to update the tlb
1227	// using the r_icache_tlb_miss_req flip-flop and the r_icache_tlb_miss_vaddr register,
1228	// and goes to the ICACHE_TLB_WAIT state.
1229	// The tlb update is entirely done by the DCACHE FSM (who becomes the owner of dtlb until
1230	// the update is completed, and reset r_icache_tlb_miss_req to signal the completion.
1231	//
1232	// The DCACHE FSM signals XTN processor requests to ICACHE_FSM
1233	// using the r_dcache_xtn_req flip-flop.
1234	// The request opcode and the address to be invalidated are transmitted
1235	// in the r_dcache_xtn_opcode and r_dcache_p0_wdata registers respectively.
1236	// The r_dcache_xtn_req flip-flop is reset by the ICACHE_FSM when the operation
1237	// is completed.
1238	//
1239	// The r_vci_rsp_ins_error flip-flop is set by the RSP FSM in case of bus error
1240	// in a cache miss or uncacheable read VCI transaction. Nothing is written
1241	// in the response fifo. This flip-flop is reset by the ICACHE-FSM.
1242	////////////////////////////////////////////////////////////////////////////////////////
1243
1244	// default value for m_irsp
1245	m_irsp.valid = false;
1246	m_irsp.error = false;
1247	m_irsp.instruction = 0;
1248
1249	switch( r_icache_fsm.read() )
1250	{
1251	/////////////////
1252	case ICACHE_IDLE: // In this state, we handle processor requests, XTN requests sent
1253	// by DCACHE FSM, and coherence requests with a fixed priority:
1254	// coherence > XTN > instruction
1255	// We access the itlb and dcache in parallel with the virtual address
1256	// for itlb, and with a speculative physical address for icache,
1257	// computed during the previous cycle.
1258	{
1259	// coherence request from the target FSM
1260	if ( r_tgt_icache_req.read() )
1261	{
1262	r_icache_fsm = ICACHE_CC_CHECK;
1263	r_icache_fsm_save = r_icache_fsm.read();
1264	break;
1265	}
1266
1267	// Decoding processor XTN requests sent by DCACHE FSM
1268	// These request are not executed in this IDLE state, because
1269	// they require access to icache or itlb, that are already accessed
1270	if ( r_dcache_xtn_req.read() )
1271	{
1272	if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_PTPR )
1273	{
1274	r_icache_fsm = ICACHE_XTN_TLB_FLUSH;
1275	break;
1276	}
1277	if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ICACHE_FLUSH)
1278	{
1279	r_icache_flush_count = 0;
1280	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH;
1281	break;
1282	}
1283	if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ITLB_INVAL)
1284	{
1285	r_icache_fsm = ICACHE_XTN_TLB_INVAL;
1286	break;
1287	}
1288	if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ICACHE_INVAL)
1289	{
1290	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_VA;
1291	break;
1292	}
1293	if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_MMU_ICACHE_PA_INV)
1294	{
1295	if (sizeof(paddr_t) <= 32) {
1296	assert(r_mmu_word_hi.read() == 0 &&
1297	"high bits should be 0 for 32bit paddr");
1298	r_icache_vci_paddr = (paddr_t)r_mmu_word_lo.read();
1299	} else {
1300	r_icache_vci_paddr =
1301	(paddr_t)r_mmu_word_hi.read() << 32 \|
1302	(paddr_t)r_mmu_word_lo.read();
1303	}
1304	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA;
1305	break;
1306	}
1307	} // end if xtn_req
1308
1309	// processor request
1310	if ( m_ireq.valid )
1311	{
1312	bool cacheable;
1313	paddr_t paddr;
1314
1315	// We register processor request
1316	r_icache_vaddr_save = m_ireq.addr;
1317
1318	// speculative icache access (if cache activated)
1319	// we use the speculative PPN computed during the previous cycle
1320
1321	uint32_t cache_inst = 0;
1322	bool cache_hit = false;
1323
1324	if ( r_mmu_mode.read() & INS_CACHE_MASK )
1325	{
1326	paddr_t spc_paddr = (r_icache_vci_paddr.read() & ~PAGE_K_MASK) \|
1327	((paddr_t)m_ireq.addr & PAGE_K_MASK);
1328
1329	#ifdef INSTRUMENTATION
1330	m_cpt_icache_data_read++;
1331	m_cpt_icache_dir_read++;
1332	#endif
1333	cache_hit = r_icache.read( spc_paddr,
1334	&cache_inst );
1335	}
1336
1337	// systematic itlb access (if tlb activated)
1338	// we use the virtual address
1339
1340	paddr_t tlb_paddr;
1341	pte_info_t tlb_flags;
1342	size_t tlb_way;
1343	size_t tlb_set;
1344	paddr_t tlb_nline;
1345	bool tlb_hit = false;;
1346
1347	if ( r_mmu_mode.read() & INS_TLB_MASK )
1348	{
1349
1350	#ifdef INSTRUMENTATION
1351	m_cpt_itlb_read++;
1352	#endif
1353	tlb_hit = r_itlb.translate( m_ireq.addr,
1354	&tlb_paddr,
1355	&tlb_flags,
1356	&tlb_nline, // unused
1357	&tlb_way, // unused
1358	&tlb_set ); // unused
1359	}
1360
1361	// We compute cacheability, physical address and check access rights:
1362	// - If MMU activated : cacheability is defined by the C bit in the PTE,
1363	// the physical address is obtained from the TLB, and the access rights are
1364	// defined by the U and X bits in the PTE.
1365	// - If MMU not activated : cacheability is defined by the segment table,
1366	// the physical address is equal to the virtual address (identity mapping)
1367	// and there is no access rights checking
1368
1369	if ( not (r_mmu_mode.read() & INS_TLB_MASK) ) // tlb not activated:
1370	{
1371	// cacheability
1372	if ( not (r_mmu_mode.read() & INS_CACHE_MASK) ) cacheable = false;
1373	else cacheable = m_cacheability_table[m_ireq.addr];
1374
1375	// physical address
1376	paddr = (paddr_t)m_ireq.addr;
1377	}
1378	else // itlb activated
1379	{
1380	if ( tlb_hit ) // tlb hit
1381	{
1382	// cacheability
1383	if ( not (r_mmu_mode.read() & INS_CACHE_MASK) ) cacheable = false;
1384	else cacheable = tlb_flags.c;
1385
1386	// physical address
1387	paddr = tlb_paddr;
1388
1389	// access rights checking
1390	if ( not tlb_flags.u && (m_ireq.mode == iss_t::MODE_USER) )
1391	{
1392	r_mmu_ietr = MMU_READ_PRIVILEGE_VIOLATION;
1393	r_mmu_ibvar = m_ireq.addr;
1394	m_irsp.valid = true;
1395	m_irsp.error = true;
1396	m_irsp.instruction = 0;
1397	break;
1398	}
1399	else if ( not tlb_flags.x )
1400	{
1401	r_mmu_ietr = MMU_READ_EXEC_VIOLATION;
1402	r_mmu_ibvar = m_ireq.addr;
1403	m_irsp.valid = true;
1404	m_irsp.error = true;
1405	m_irsp.instruction = 0;
1406	break;
1407	}
1408	}
1409	// in case of TLB miss we send an itlb miss request to DCACHE FSM and break
1410	else
1411	{
1412
1413	#ifdef INSTRUMENTATION
1414	m_cpt_itlb_miss++;
1415	#endif
1416	r_icache_fsm = ICACHE_TLB_WAIT;
1417	r_icache_tlb_miss_req = true;
1418	break;
1419	}
1420	} // end if itlb activated
1421
1422	// physical address registration (for next cycle)
1423	r_icache_vci_paddr = paddr;
1424
1425	// We enter this section only in case of TLB hit:
1426	// Finally, we get the instruction depending on cacheability,
1427	// we send the response to processor, and compute next state
1428	if ( cacheable ) // cacheable read
1429	{
1430	if ( (r_icache_vci_paddr.read() & ~PAGE_K_MASK)
1431	!= (paddr & ~PAGE_K_MASK) ) // speculative access KO
1432	{
1433
1434	#ifdef INSTRUMENTATION
1435	m_cpt_icache_spc_miss++;
1436	#endif
1437	// we return an invalid response and stay in IDLE state
1438	// the cache access will cost one extra cycle.
1439	break;
1440	}
1441
1442	if ( not cache_hit ) // cache miss
1443	{
1444
1445	#ifdef INSTRUMENTATION
1446	m_cpt_icache_miss++;
1447	#endif
1448	r_icache_fsm = ICACHE_MISS_VICTIM;
1449	r_icache_miss_req = true;
1450	}
1451	else // cache hit
1452	{
1453
1454	#ifdef INSTRUMENTATION
1455	m_cpt_ins_read++;
1456	#endif
1457	m_irsp.valid = true;
1458	m_irsp.instruction = cache_inst;
1459	}
1460	}
1461	else // non cacheable read
1462	{
1463	r_icache_unc_req = true;
1464	r_icache_fsm = ICACHE_UNC_WAIT;
1465	}
1466	} // end if m_ireq.valid
1467	break;
1468	}
1469	/////////////////////
1470	case ICACHE_TLB_WAIT: // Waiting the itlb update by the DCACHE FSM after a tlb miss
1471	// the itlb is udated by the DCACHE FSM, as well as the
1472	// r_mmu_ietr and r_mmu_ibvar registers in case of error.
1473	// the itlb is not accessed by ICACHE FSM until DCACHE FSM
1474	// reset the r_icache_tlb_miss_req flip-flop
1475	// external coherence request are accepted in this state.
1476	{
1477	// external coherence request
1478	if ( r_tgt_icache_req.read() )
1479	{
1480	r_icache_fsm = ICACHE_CC_CHECK;
1481	r_icache_fsm_save = r_icache_fsm.read();
1482	break;
1483	}
1484
1485	if ( m_ireq.valid ) m_cost_ins_tlb_miss_frz++;
1486
1487	// DCACHE FSM signals response by reseting the request flip-flop
1488	if ( not r_icache_tlb_miss_req.read() )
1489	{
1490	if ( r_icache_tlb_rsp_error.read() ) // error reported : tlb not updated
1491	{
1492	r_icache_tlb_rsp_error = false;
1493	m_irsp.error = true;
1494	m_irsp.valid = true;
1495	r_icache_fsm = ICACHE_IDLE;
1496	}
1497	else // tlb updated : return to IDLE state
1498	{
1499	r_icache_fsm = ICACHE_IDLE;
1500	}
1501	}
1502	break;
1503	}
1504	//////////////////////////
1505	case ICACHE_XTN_TLB_FLUSH: // invalidate in one cycle all non global TLB entries
1506	{
1507	r_itlb.flush();
1508	r_dcache_xtn_req = false;
1509	r_icache_fsm = ICACHE_IDLE;
1510	break;
1511	}
1512	////////////////////////////
1513	case ICACHE_XTN_CACHE_FLUSH: // Invalidate sequencially all cache lines using
1514	// the r_icache_flush_count register as a slot counter.
1515	// We loop in this state until all slots have been visited.
1516	// A cleanup request is generated for each valid line
1517	// and we are blocked until the previous cleanup is completed
1518	{
1519	if ( not r_icache_cleanup_req.read() )
1520	{
1521	size_t way = r_icache_flush_count.read()/m_icache_sets;
1522	size_t set = r_icache_flush_count.read()%m_icache_sets;
1523	paddr_t nline;
1524	bool cleanup_req = r_icache.inval( way,
1525	set,
1526	&nline );
1527	if ( cleanup_req )
1528	{
1529	r_icache_cleanup_req = true;
1530	r_icache_cleanup_line = nline;
1531	}
1532	r_icache_flush_count = r_icache_flush_count.read() + 1;
1533
1534
1535	if ( r_icache_flush_count.read() == (m_icache_sets*m_icache_ways - 1) )
1536	{
1537	r_dcache_xtn_req = false;
1538	r_icache_fsm = ICACHE_IDLE;
1539	}
1540	}
1541
1542	break;
1543	}
1544	//////////////////////////
1545	case ICACHE_XTN_TLB_INVAL: // invalidate one TLB entry selected by the virtual address
1546	// stored in the r_dcache_p0_wdata register
1547	{
1548	r_itlb.inval(r_dcache_p0_wdata.read());
1549	r_dcache_xtn_req = false;
1550	r_icache_fsm = ICACHE_IDLE;
1551	break;
1552	}
1553	///////////////////////////////
1554	case ICACHE_XTN_CACHE_INVAL_VA: // Selective cache line invalidate with virtual address
1555	// requires 3 cycles (in case of hit on itlb and icache).
1556	// In this state, we access TLB to translate virtual address
1557	// stored in the r_dcache_p0_wdata register.
1558	{
1559	paddr_t paddr;
1560	bool hit;
1561
1562	// read physical address in TLB when MMU activated
1563	if ( r_mmu_mode.read() & INS_TLB_MASK ) // itlb activated
1564	{
1565
1566	#ifdef INSTRUMENTATION
1567	m_cpt_itlb_read++;
1568	#endif
1569	hit = r_itlb.translate(r_dcache_p0_wdata.read(),
1570	&paddr);
1571	}
1572	else // itlb not activated
1573	{
1574	paddr = (paddr_t)r_dcache_p0_wdata.read();
1575	hit = true;
1576	}
1577
1578	if ( hit ) // continue the selective inval process
1579	{
1580	r_icache_vci_paddr = paddr;
1581	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA;
1582	}
1583	else // miss : send a request to DCACHE FSM
1584	{
1585
1586	#ifdef INSTRUMENTATION
1587	m_cpt_itlb_miss++;
1588	#endif
1589	r_icache_tlb_miss_req = true;
1590	r_icache_vaddr_save = r_dcache_p0_wdata.read();
1591	r_icache_fsm = ICACHE_TLB_WAIT;
1592	}
1593	break;
1594	}
1595	///////////////////////////////
1596	case ICACHE_XTN_CACHE_INVAL_PA: // selective invalidate cache line with physical address
1597	// require 2 cycles. In this state, we read dcache,
1598	// with address stored in r_icache_vci_paddr register.
1599	{
1600	uint32_t data;
1601	size_t way;
1602	size_t set;
1603	size_t word;
1604	bool hit = r_icache.read(r_icache_vci_paddr.read(),
1605	&data,
1606	&way,
1607	&set,
1608	&word);
1609	if ( hit ) // inval to be done
1610	{
1611	r_icache_miss_way = way;
1612	r_icache_miss_set = set;
1613	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_GO;
1614	}
1615	else // miss : acknowlege the XTN request and return
1616	{
1617	r_dcache_xtn_req = false;
1618	r_icache_fsm = ICACHE_IDLE;
1619	}
1620	break;
1621	}
1622	///////////////////////////////
1623	case ICACHE_XTN_CACHE_INVAL_GO: // In this state, we invalidate the cache line & cleanup.
1624	// We are blocked if the previous cleanup is not completed
1625	{
1626	paddr_t nline;
1627
1628	if ( not r_icache_cleanup_req.read() )
1629	{
1630	bool hit;
1631	hit = r_icache.inval( r_icache_miss_way.read(),
1632	r_icache_miss_set.read(),
1633	&nline );
1634	assert(hit && "XTN_ICACHE_INVAL way/set should still be in icache");
1635
1636	// request cleanup
1637	r_icache_cleanup_req = true;
1638	r_icache_cleanup_line = nline;
1639	// acknowledge the XTN request and return
1640	r_dcache_xtn_req = false;
1641	r_icache_fsm = ICACHE_IDLE;
1642	}
1643	break;
1644	}
1645
1646	////////////////////////
1647	case ICACHE_MISS_VICTIM: // Selects a victim line
1648	// Set the r_icache_cleanup_req flip-flop
1649	// when the selected slot is not empty
1650	{
1651	m_cost_ins_miss_frz++;
1652
1653	size_t index; // unused
1654	bool hit = r_cleanup_buffer.hit( r_icache_vci_paddr.read()>>(uint32_log2(m_icache_words)+2), &index );
1655	if ( not hit and not r_icache_cleanup_req.read() )
1656	{
1657	bool valid;
1658	size_t way;
1659	size_t set;
1660	paddr_t victim;
1661
1662	valid = r_icache.victim_select(r_icache_vci_paddr.read(),
1663	&victim,
1664	&way,
1665	&set);
1666	r_icache_miss_way = way;
1667	r_icache_miss_set = set;
1668
1669	if ( valid )
1670	{
1671	r_icache_cleanup_req = true;
1672	r_icache_cleanup_line = victim;
1673	r_icache_fsm = ICACHE_MISS_INVAL;
1674	}
1675	else
1676	{
1677	r_icache_fsm = ICACHE_MISS_WAIT;
1678	}
1679	}
1680	break;
1681	}
1682	///////////////////////
1683	case ICACHE_MISS_INVAL: // invalidate the victim line
1684	{
1685	paddr_t nline;
1686	bool hit;
1687
1688	hit = r_icache.inval( r_icache_miss_way.read(),
1689	r_icache_miss_set.read(),
1690	&nline ); // unused
1691	assert(hit && "selected way/set line should be in icache");
1692
1693	r_icache_fsm = ICACHE_MISS_WAIT;
1694	break;
1695	}
1696	//////////////////////
1697	case ICACHE_MISS_WAIT: // waiting a response to a miss request from VCI_RSP FSM
1698	{
1699	if ( m_ireq.valid ) m_cost_ins_miss_frz++;
1700
1701	// external coherence request
1702	if ( r_tgt_icache_req.read() )
1703	{
1704	r_icache_fsm = ICACHE_CC_CHECK;
1705	r_icache_fsm_save = r_icache_fsm.read();
1706	break;
1707	}
1708
1709	if ( r_vci_rsp_ins_error.read() ) // bus error
1710	{
1711	r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS;
1712	r_mmu_ibvar = r_icache_vaddr_save.read();
1713	m_irsp.valid = true;
1714	m_irsp.error = true;
1715	r_vci_rsp_ins_error = false;
1716	r_icache_fsm = ICACHE_IDLE;
1717	}
1718	else if ( r_vci_rsp_fifo_icache.rok() ) // response available
1719	{
1720	r_icache_miss_word = 0;
1721	r_icache_fsm = ICACHE_MISS_UPDT;
1722	}
1723	break;
1724	}
1725	//////////////////////
1726	case ICACHE_MISS_UPDT: // update the cache (one word per cycle)
1727	{
1728	if ( m_ireq.valid ) m_cost_ins_miss_frz++;
1729
1730	if ( r_vci_rsp_fifo_icache.rok() ) // response available
1731	{
1732	if ( r_icache_miss_inval ) // Matching coherence request
1733	// We pop the response FIFO, without updating the cache
1734	// We send a cleanup for the missing line at the last word
1735	// Blocked if the previous cleanup is not completed
1736	{
1737	if ( r_icache_miss_word.read() < m_icache_words-1 ) // not the last word
1738	{
1739	vci_rsp_fifo_icache_get = true;
1740	r_icache_miss_word = r_icache_miss_word.read() + 1;
1741	}
1742	else // last word
1743	{
1744	if ( not r_icache_cleanup_req.read() ) // no pending cleanup
1745	{
1746	vci_rsp_fifo_icache_get = true;
1747	r_icache_cleanup_req = true;
1748	r_icache_cleanup_line = r_icache_vci_paddr.read() >> (uint32_log2(m_icache_words<<2));
1749	r_icache_miss_inval = false;
1750	r_icache_fsm = ICACHE_IDLE;
1751	}
1752	}
1753	}
1754	else // No matching coherence request
1755	// We pop the FIFO and update the cache
1756	// We update the directory at the last word
1757	{
1758
1759	#ifdef INSTRUMENTATION
1760	m_cpt_icache_data_write++;
1761	#endif
1762	r_icache.write( r_icache_miss_way.read(),
1763	r_icache_miss_set.read(),
1764	r_icache_miss_word.read(),
1765	r_vci_rsp_fifo_icache.read() );
1766	vci_rsp_fifo_icache_get = true;
1767	r_icache_miss_word = r_icache_miss_word.read() + 1;
1768	if ( r_icache_miss_word.read() == m_icache_words-1 ) // last word
1769	{
1770
1771	#ifdef INSTRUMENTATION
1772	m_cpt_icache_dir_write++;
1773	#endif
1774	r_icache.victim_update_tag( r_icache_vci_paddr.read(),
1775	r_icache_miss_way.read(),
1776	r_icache_miss_set.read() );
1777	r_icache_fsm = ICACHE_IDLE;
1778	}
1779	}
1780	}
1781	break;
1782	}
1783	////////////////////
1784	case ICACHE_UNC_WAIT: // waiting a response to an uncacheable read from VCI_RSP FSM
1785	//
1786	{
1787	// external coherence request
1788	if ( r_tgt_icache_req.read() )
1789	{
1790	r_icache_fsm = ICACHE_CC_CHECK;
1791	r_icache_fsm_save = r_icache_fsm.read();
1792	break;
1793	}
1794
1795	if ( r_vci_rsp_ins_error.read() ) // bus error
1796	{
1797	r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS;
1798	r_mmu_ibvar = m_ireq.addr;
1799	r_vci_rsp_ins_error = false;
1800	m_irsp.valid = true;
1801	m_irsp.error = true;
1802	r_icache_fsm = ICACHE_IDLE;
1803	}
1804	else if (r_vci_rsp_fifo_icache.rok() ) // instruction available
1805	{
1806	vci_rsp_fifo_icache_get = true;
1807	r_icache_fsm = ICACHE_IDLE;
1808	if ( m_ireq.valid and (m_ireq.addr == r_icache_vaddr_save.read()) ) // request not modified
1809	{
1810	m_irsp.valid = true;
1811	m_irsp.instruction = r_vci_rsp_fifo_icache.read();
1812	}
1813	}
1814	break;
1815	}
1816	/////////////////////
1817	case ICACHE_CC_CHECK: // This state is the entry point of a sub-fsm
1818	// handling coherence requests.
1819	// the return state is defined in r_icache_fsm_save.
1820	{
1821	paddr_t paddr = r_tgt_paddr.read();
1822	paddr_t mask = ~((m_icache_words<<2)-1);
1823
1824	if( (r_icache_fsm_save.read() == ICACHE_MISS_WAIT) and
1825	((r_icache_vci_paddr.read() & mask) == (paddr & mask))) // matching a pending miss
1826	{
1827	r_icache_miss_inval = true; // signaling the matching
1828	r_tgt_icache_req = false; // coherence request completed
1829	r_tgt_icache_rsp = r_tgt_update.read(); // response required if update
1830	r_icache_fsm = r_icache_fsm_save.read();
1831	}
1832	else // no match
1833	{
1834
1835	#ifdef INSTRUMENTATION
1836	m_cpt_icache_dir_read++;
1837	#endif
1838	uint32_t inst;
1839	size_t way;
1840	size_t set;
1841	size_t word;
1842	bool hit = r_icache.read(paddr,
1843	&inst,
1844	&way,
1845	&set,
1846	&word);
1847	r_icache_cc_way = way;
1848	r_icache_cc_set = set;
1849
1850	if ( hit and r_tgt_update.read() ) // hit update
1851	{
1852	r_icache_fsm = ICACHE_CC_UPDT;
1853	r_icache_cc_word = r_tgt_word_min.read();
1854	}
1855	else if ( hit and not r_tgt_update.read() ) // hit inval
1856	{
1857	r_icache_fsm = ICACHE_CC_INVAL;
1858	}
1859	else // miss can happen
1860	{
1861	r_tgt_icache_req = false;
1862	r_tgt_icache_rsp = r_tgt_update.read();
1863	r_icache_fsm = r_icache_fsm_save.read();
1864	}
1865	}
1866	break;
1867	}
1868
1869	/////////////////////
1870	case ICACHE_CC_INVAL: // invalidate a cache line
1871	{
1872	paddr_t nline;
1873	bool hit;
1874	hit = r_icache.inval( r_icache_cc_way.read(),
1875	r_icache_cc_set.read(),
1876	&nline );
1877	assert (hit && "ICACHE_CC_INVAL way/set should still be in icache");
1878	r_tgt_icache_req = false;
1879	r_tgt_icache_rsp = true;
1880	r_icache_fsm = r_icache_fsm_save.read();
1881	break;
1882	}
1883	////////////////////
1884	case ICACHE_CC_UPDT: // write one word per cycle (from word_min to word_max)
1885	{
1886	size_t word = r_icache_cc_word.read();
1887	size_t way = r_icache_cc_way.read();
1888	size_t set = r_icache_cc_set.read();
1889
1890	r_icache.write( way,
1891	set,
1892	word,
1893	r_tgt_buf[word],
1894	r_tgt_be[word] );
1895
1896	r_icache_cc_word = word+1;
1897
1898	if ( word == r_tgt_word_max.read() ) // last word
1899	{
1900	r_tgt_icache_req = false;
1901	r_tgt_icache_rsp = true;
1902	r_icache_fsm = r_icache_fsm_save.read();
1903	}
1904	break;
1905	}
1906
1907	} // end switch r_icache_fsm
1908
1909	////////////////////////////////////////////////////////////////////////////////////
1910	// DCACHE FSM
1911	//
1912	// Both the Cacheability Table, and the MMU cacheable bit are used to define
1913	// the cacheability, depending on the MMU mode.
1914	//
1915	// 1/ Coherence requests :
1916	// There is a coherence request when the tgt_dcache_req flip-flop is set,
1917	// requesting a line invalidation or a line update.
1918	// Coherence requests are taken into account in IDLE, UNC_WAIT, MISS_WAIT states.
1919	// The actions associated to the pre-empted state are not executed, the DCACHE FSM
1920	// goes to the CC_CHECK state to execute the requested action, and returns to the
1921	// pre-empted state.
1922	//
1923	// 2/ TLB miss
1924	// The page tables can be cacheable.
1925	// In case of miss in itlb or dtlb, the tlb miss is handled by a dedicated
1926	// sub-fsm (DCACHE_TLB_MISS state), that handle possible miss in DCACHE,
1927	// this sub-fsm implement the table-walk...
1928	//
1929	// 3/ processor requests :
1930	// Processor READ, WRITE, LL or SC requests are taken in IDLE state only.
1931	// The IDLE state implements a three stages pipe-line to handle write bursts:
1932	// - The physical address is computed by dtlb in stage P0.
1933	// - The registration in wbuf and the dcache hit are computed in stage P1.
1934	// - The dcache update is done in stage P2.
1935	// WRITE or SC requests can require a PTE Dirty bit update (in memory),
1936	// that is done (before handling the processor request) by a dedicated sub-fsm
1937	// (DCACHE_DIRTY_TLB_SET state).
1938	// If a PTE is modified, both the itlb and dtlb are selectively, but sequencially
1939	// cleared by a dedicated sub_fsm (DCACHE_INVAL_TLB_SCAN state).
1940	// If there is no write in the pipe, dcache and dtlb are accessed in parallel,
1941	// (virtual address for itlb, and speculative physical address computed during
1942	// previous cycle for dcache) in order to return the data in one cycle for a READ
1943	// request. We just pay an extra cycle when the speculative access is failing.
1944	//
1945	// 4/ Atomic instructions LL/SC
1946	// The LL/SC address can be cacheable or non cacheable.
1947	// The llsc_local_table holds a registration for an active LL/SC
1948	// operation (with an address, a registration key, an aging counter and a
1949	// valid bit).
1950	// - LL requests from the processor are transmitted as a one flit VCI
1951	// CMD_LOCKED_READ transaction with TYPE_LL as PKTID value. PLEN must
1952	// be 8 as the response is 2 flits long (data and registration key)
1953	// - SC requests from the processor are systematically transmitted to the
1954	// memory cache as 2 flits VCI CMD_NOP (or CMD_STORE_COND)
1955	// transactions, with TYPE_SC as PKTID value (the first flit contains
1956	// the registration key, the second flit contains the data to write in
1957	// case of success).
1958	// The cache is not updated, as this is done in case of success by the
1959	// coherence transaction.
1960	//
1961	// 5/ Non cacheable access:
1962	// This component implement a strong order between non cacheable access
1963	// (read or write) : A new non cacheable VCI transaction starts only when
1964	// the previous non cacheable transaction is completed. Both cacheable and
1965	// non cacheable transactions use the write buffer, but the DCACHE FSM registers
1966	// a non cacheable write transaction posted in the write buffer by setting the
1967	// r_dcache_pending_unc_write flip_flop. All other non cacheable requests
1968	// are stalled until this flip-flop is reset by the VCI_RSP_FSM (when the
1969	// pending non cacheable write transaction completes).
1970	//
1971	// 6/ Error handling:
1972	// When the MMU is not activated, Read Bus Errors are synchronous events,
1973	// but Write Bus Errors are asynchronous events (processor is not frozen).
1974	// - If a Read Bus Error is detected, the VCI_RSP FSM sets the
1975	// r_vci_rsp_data_error flip-flop, without writing any data in the
1976	// r_vci_rsp_fifo_dcache FIFO, and the synchronous error is signaled
1977	// by the DCACHE FSM.
1978	// - If a Write Bus Error is detected, the VCI_RSP FSM signals
1979	// the asynchronous error using the setWriteBerr() method.
1980	// When the MMU is activated bus error are rare events, as the MMU
1981	// checks the physical address before the VCI transaction starts.
1982	////////////////////////////////////////////////////////////////////////////////////////
1983
1984	// default value for m_drsp
1985	m_drsp.valid = false;
1986	m_drsp.error = false;
1987	m_drsp.rdata = 0;
1988
1989	// keep track of the local llsc table access and perform a NOP access if
1990	// necessary at the end of the DCACHE transition function
1991	bool llsc_local_table_access_done = false;
1992
1993	switch ( r_dcache_fsm.read() )
1994	{
1995	case DCACHE_IDLE: // There are 9 conditions to exit the IDLE state :
1996	// 1) Dirty bit update (processor) => DCACHE_DIRTY_GET_PTE
1997	// 2) Coherence request (TGT FSM) => DCACHE_CC_CHECK
1998	// 3) ITLB miss request (ICACHE FSM) => DCACHE_TLB_MISS
1999	// 4) XTN request (processor) => DCACHE_XTN_*
2000	// 5) DTLB miss (processor) => DCACHE_TLB_MISS
2001	// 6) Cacheable read miss (processor) => DCACHE_MISS_VICTIM
2002	// 7) Uncacheable read (processor) => DCACHE_UNC_WAIT
2003	// 8) LL access (processor) => DCACHE_LL_WAIT
2004	// 9) SC access (processor) => DCACHE_SC_WAIT
2005	//
2006	// The dtlb is unconditionally accessed to translate the
2007	// virtual adress from processor.
2008	//
2009	// There is 4 configurations to access the cache,
2010	// depending on the pipe-line state, defined
2011	// by the r_dcache_p0_valid (V0) flip-flop : P1 stage activated
2012	// and r_dcache_p1_valid (V1) flip-flop : P2 stage activated
2013	// V0 / V1 / Data / Directory / comment
2014	// 0 / 0 / read(A0) / read(A0) / read speculative access
2015	// 0 / 1 / write(A2) / nop / read request delayed
2016	// 1 / 0 / nop / read(A1) / read request delayed
2017	// 1 / 1 / write(A2) / read(A1) / read request delayed
2018	{
2019	bool tlb_inval_required = false;
2020	bool write_pipe_frozen = false;
2021
2022	////////////////////////////////////////////////////////////////////////////////
2023	// Handling P2 pipe-line stage
2024	// Inputs are r_dcache_p1_* registers.
2025	// If r_dcache_p1_valid is true, we update the local copy in dcache.
2026	// If the modified cache line has copies in TLBs, we launch a TLB invalidate
2027	// operation, going to DCACHE_INVAL_TLB_SCAN state.
2028
2029	if ( r_dcache_p1_valid.read() ) // P2 stage activated
2030	{
2031	size_t way = r_dcache_p1_cache_way.read();
2032	size_t set = r_dcache_p1_cache_set.read();
2033	size_t word = r_dcache_p1_cache_word.read();
2034	uint32_t wdata = r_dcache_p1_wdata.read();
2035	vci_be_t be = r_dcache_p1_be.read();
2036
2037	r_dcache.write( way,
2038	set,
2039	word,
2040	wdata,
2041	be );
2042	#ifdef INSTRUMENTATION
2043	m_cpt_dcache_data_write++;
2044	#endif
2045	// cache update after a WRITE hit can require itlb & dtlb inval or flush
2046	if ( r_dcache_in_tlb[way*m_dcache_sets+set] )
2047	{
2048	tlb_inval_required = true;
2049	r_dcache_tlb_inval_count = 0;
2050	r_dcache_tlb_inval_line = r_dcache_p1_paddr.read()>>
2051	(uint32_log2(m_dcache_words<<2));
2052	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
2053	}
2054	else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] )
2055	{
2056	r_itlb.reset();
2057	r_dtlb.reset();
2058	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
2059	}
2060
2061	#if DEBUG_DCACHE
2062	if ( m_debug_dcache_fsm )
2063	{
2064	std::cout << " <PROC " << name() << ".DCACHE_IDLE> Cache update in P2 stage" << std::dec
2065	<< " / WAY = " << way
2066	<< " / SET = " << set
2067	<< " / WORD = " << word << std::hex
2068	<< " / DATA = " << wdata
2069	<< " / BE = " << be << std::endl;
2070	}
2071	#endif
2072	} // end P2 stage
2073
2074	///////////////////////////////////////////////////////////////////////////
2075	// Handling P1 pipe-line stage
2076	// Inputs are r_dcache_p0_* registers.
2077	// We must write into wbuf and test the hit in dcache.
2078	// If the write request is non cacheable, and there is a pending
2079	// non cacheable write, or if the write buffer is full, the P0 and P1 stages
2080	// are frozen until the write request registration is possible,
2081	// while the P2 stage is not frozen.
2082	// The r_dcache_p1_valid bit must be computed at all cycles, and
2083	// the P2 stage must be activated if there is a local copy in dcache.
2084
2085	if ( r_dcache_p0_valid.read() ) // P1 stage activated
2086	{
2087	// frozen if write not cacheable, and previous non cacheable write registered
2088	if ( not r_dcache_p0_cacheable.read() and r_dcache_pending_unc_write.read() )
2089	{
2090	r_dcache_p1_valid = false;
2091	write_pipe_frozen = true;
2092	}
2093	else // try a registration into write buffer
2094	{
2095
2096	bool wok = r_wbuf.write( r_dcache_p0_paddr.read(),
2097	r_dcache_p0_be.read(),
2098	r_dcache_p0_wdata.read(),
2099	r_dcache_p0_cacheable.read() );
2100	#ifdef INSTRUMENTATION
2101	m_cpt_wbuf_write++;
2102	#endif
2103	if ( not wok ) // frozen if write buffer full
2104	{
2105	r_dcache_p1_valid = false;
2106	write_pipe_frozen = true;
2107	}
2108	else // update the write_buffer state extension
2109	{
2110	if(not r_dcache_pending_unc_write.read())
2111	r_dcache_pending_unc_write = not r_dcache_p0_cacheable.read();
2112
2113	// read directory to check local copy
2114	size_t cache_way;
2115	size_t cache_set;
2116	size_t cache_word;
2117	bool local_copy;
2118	if ( r_mmu_mode.read() & DATA_CACHE_MASK) // cache activated
2119	{
2120	local_copy = r_dcache.hit( r_dcache_p0_paddr.read(),
2121	&cache_way,
2122	&cache_set,
2123	&cache_word );
2124	#ifdef INSTRUMENTATION
2125	m_cpt_dcache_dir_read++;
2126	#endif
2127	}
2128	else
2129	{
2130	local_copy = false;
2131	}
2132
2133	// store values for P2 pipe stage
2134	if ( local_copy )
2135	{
2136	r_dcache_p1_valid = true;
2137	r_dcache_p1_wdata = r_dcache_p0_wdata.read();
2138	r_dcache_p1_be = r_dcache_p0_be.read();
2139	r_dcache_p1_paddr = r_dcache_p0_paddr.read();
2140	r_dcache_p1_cache_way = cache_way;
2141	r_dcache_p1_cache_set = cache_set;
2142	r_dcache_p1_cache_word = cache_word;
2143	}
2144	else
2145	{
2146	r_dcache_p1_valid = false;
2147	}
2148	}
2149	}
2150	}
2151	else // P1 stage not activated
2152	{
2153	r_dcache_p1_valid = false;
2154	} // end P1 stage
2155
2156	/////////////////////////////////////////////////////////////////////////////////
2157	// handling P0 pipe-line stage
2158	// This stage is controlling r_dcache_fsm and r_dcache_p0_* registers.
2159	// The r_dcache_p0_valid flip-flop is only set in case of a WRITE request.
2160	// - the TLB invalidate requests have the highest priority,
2161	// - then the external coherence requests,
2162	// - then the itlb miss requests,
2163	// - and finally the processor requests.
2164	// If dtlb is activated, there is an unconditionnal access to dtlb,
2165	// for address translation.
2166	// 1) A processor WRITE request is blocked if the Dirty bit mus be set, or if
2167	// dtlb miss. If dtlb is OK, It enters the three stage pipe-line (fully
2168	// handled by the IDLE state), and the processor request is acknowledged.
2169	// 2) A processor READ request generate a simultaneouss access to
2170	// both dcache data and dcache directoty, using speculative PPN, but
2171	// is delayed if the write pipe-line is not empty.
2172	// In case of miss, we wait the VCI response in DCACHE_UNC_WAIT or
2173	// DCACHE_MISS_WAIT states.
2174	// 3) A processor LL request generate a VCI LL transaction. We wait for
2175	// the response in DCACHE_LL_WAIT state.
2176	// 4) A processor SC request is delayed until the write pipe-line is empty.
2177	// A VCI SC transaction is launched, and we wait the VCI response in
2178	// DCACHE_SC_WAIT state. It can be completed by a "long write" if the
2179	// PTE dirty bit must be updated in dtlb, dcache, and RAM.
2180	// The data is not modified in dcache, as it will be done by the
2181	// coherence transaction.
2182
2183	// TLB inval required after a write hit
2184	if ( tlb_inval_required )
2185	{
2186	r_dcache_fsm_scan_save = r_dcache_fsm.read();
2187	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
2188	r_dcache_p0_valid = r_dcache_p0_valid.read() and write_pipe_frozen;
2189	}
2190	// external coherence request
2191	else if ( r_tgt_dcache_req.read() )
2192	{
2193	r_dcache_fsm_cc_save = r_dcache_fsm.read();
2194	r_dcache_fsm = DCACHE_CC_CHECK;
2195	r_dcache_p0_valid = r_dcache_p0_valid.read() and write_pipe_frozen;
2196	}
2197
2198	// processor request
2199	else if ( m_dreq.valid and not write_pipe_frozen )
2200	{
2201	// dcache access using speculative PPN only if pipe-line empty
2202	paddr_t cache_paddr;
2203	size_t cache_way;
2204	size_t cache_set;
2205	size_t cache_word;
2206	uint32_t cache_rdata;
2207	bool cache_hit;
2208
2209	if ( (r_mmu_mode.read() & DATA_CACHE_MASK) and // cache activated
2210	not r_dcache_p0_valid.read() and
2211	not r_dcache_p1_valid.read() ) // pipe-line empty
2212	{
2213	cache_paddr = (r_dcache_p0_paddr.read() & ~PAGE_K_MASK) \|
2214	((paddr_t)m_dreq.addr & PAGE_K_MASK);
2215
2216	cache_hit = r_dcache.read( cache_paddr,
2217	&cache_rdata,
2218	&cache_way,
2219	&cache_set,
2220	&cache_word );
2221	#ifdef INSTRUMENTATION
2222	m_cpt_dcache_dir_read++;
2223	m_cpt_dcache_data_read++;
2224	#endif
2225	}
2226	else
2227	{
2228	cache_hit = false;
2229	} // end dcache access
2230
2231	// systematic dtlb access using virtual address
2232	paddr_t tlb_paddr;
2233	pte_info_t tlb_flags;
2234	size_t tlb_way;
2235	size_t tlb_set;
2236	paddr_t tlb_nline;
2237	bool tlb_hit;
2238
2239	if ( r_mmu_mode.read() & DATA_TLB_MASK ) // DTLB activated
2240	{
2241	tlb_hit = r_dtlb.translate( m_dreq.addr,
2242	&tlb_paddr,
2243	&tlb_flags,
2244	&tlb_nline,
2245	&tlb_way,
2246	&tlb_set );
2247	#ifdef INSTRUMENTATION
2248	m_cpt_dtlb_read++;
2249	#endif
2250	}
2251	else
2252	{
2253	tlb_hit = false;
2254	} // end dtlb access
2255
2256	// register the processor request
2257	r_dcache_p0_vaddr = m_dreq.addr;
2258	r_dcache_p0_be = m_dreq.be;
2259	r_dcache_p0_wdata = m_dreq.wdata;
2260
2261	// Handling READ XTN requests from processor
2262	// They are executed in this DCACHE_IDLE state.
2263	// The processor must not be in user mode
2264	if (m_dreq.type == iss_t::XTN_READ)
2265	{
2266	int xtn_opcode = (int)m_dreq.addr/4;
2267
2268	// checking processor mode:
2269	if (m_dreq.mode == iss_t::MODE_USER)
2270	{
2271	r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION;
2272	r_mmu_dbvar = m_dreq.addr;
2273	m_drsp.valid = true;
2274	m_drsp.error = true;
2275	r_dcache_fsm = DCACHE_IDLE;
2276	}
2277	else
2278	{
2279	switch( xtn_opcode )
2280	{
2281	case iss_t::XTN_INS_ERROR_TYPE:
2282	m_drsp.rdata = r_mmu_ietr.read();
2283	m_drsp.valid = true;
2284	break;
2285
2286	case iss_t::XTN_DATA_ERROR_TYPE:
2287	m_drsp.rdata = r_mmu_detr.read();
2288	m_drsp.valid = true;
2289	break;
2290
2291	case iss_t::XTN_INS_BAD_VADDR:
2292	m_drsp.rdata = r_mmu_ibvar.read();
2293	m_drsp.valid = true;
2294	break;
2295
2296	case iss_t::XTN_DATA_BAD_VADDR:
2297	m_drsp.rdata = r_mmu_dbvar.read();
2298	m_drsp.valid = true;
2299	break;
2300
2301	case iss_t::XTN_PTPR:
2302	m_drsp.rdata = r_mmu_ptpr.read();
2303	m_drsp.valid = true;
2304	break;
2305
2306	case iss_t::XTN_TLB_MODE:
2307	m_drsp.rdata = r_mmu_mode.read();
2308	m_drsp.valid = true;
2309	break;
2310
2311	case iss_t::XTN_MMU_PARAMS:
2312	m_drsp.rdata = r_mmu_params;
2313	m_drsp.valid = true;
2314	break;
2315
2316	case iss_t::XTN_MMU_RELEASE:
2317	m_drsp.rdata = r_mmu_release;
2318	m_drsp.valid = true;
2319	break;
2320
2321	case iss_t::XTN_MMU_WORD_LO:
2322	m_drsp.rdata = r_mmu_word_lo.read();
2323	m_drsp.valid = true;
2324	break;
2325
2326	case iss_t::XTN_MMU_WORD_HI:
2327	m_drsp.rdata = r_mmu_word_hi.read();
2328	m_drsp.valid = true;
2329	break;
2330
2331	default:
2332	r_mmu_detr = MMU_READ_UNDEFINED_XTN;
2333	r_mmu_dbvar = m_dreq.addr;
2334	m_drsp.valid = true;
2335	m_drsp.error = true;
2336	break;
2337	} // end switch xtn_opcode
2338	} // end else
2339	r_dcache_p0_valid = false;
2340	} // end if XTN_READ
2341
2342	// Handling WRITE XTN requests from processor.
2343	// They are not executed in this DCACHE_IDLE state,
2344	// if they require access to the caches or the TLBs
2345	// that are already accessed for speculative read.
2346	// Caches can be invalidated or flushed in user mode,
2347	// and the sync instruction can be executed in user mode
2348	else if (m_dreq.type == iss_t::XTN_WRITE)
2349	{
2350	int xtn_opcode = (int)m_dreq.addr/4;
2351	r_dcache_xtn_opcode = xtn_opcode;
2352
2353	// checking processor mode:
2354	if ( (m_dreq.mode == iss_t::MODE_USER) &&
2355	(xtn_opcode != iss_t:: XTN_SYNC) &&
2356	(xtn_opcode != iss_t::XTN_DCACHE_INVAL) &&
2357	(xtn_opcode != iss_t::XTN_DCACHE_FLUSH) &&
2358	(xtn_opcode != iss_t::XTN_ICACHE_INVAL) &&
2359	(xtn_opcode != iss_t::XTN_ICACHE_FLUSH) )
2360	{
2361	r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION;
2362	r_mmu_dbvar = m_dreq.addr;
2363	m_drsp.valid = true;
2364	m_drsp.error = true;
2365	r_dcache_fsm = DCACHE_IDLE;
2366	}
2367	else
2368	{
2369	switch( xtn_opcode )
2370	{
2371	case iss_t::XTN_PTPR: // itlb & dtlb must be flushed
2372	r_dcache_xtn_req = true;
2373	r_dcache_fsm = DCACHE_XTN_SWITCH;
2374	break;
2375
2376	case iss_t::XTN_TLB_MODE: // no cache or tlb access
2377	r_mmu_mode = m_dreq.wdata;
2378	m_drsp.valid = true;
2379	r_dcache_fsm = DCACHE_IDLE;
2380	break;
2381
2382	case iss_t::XTN_DTLB_INVAL: // dtlb access
2383	r_dcache_fsm = DCACHE_XTN_DT_INVAL;
2384	break;
2385
2386	case iss_t::XTN_ITLB_INVAL: // itlb access
2387	r_dcache_xtn_req = true;
2388	r_dcache_fsm = DCACHE_XTN_IT_INVAL;
2389	break;
2390
2391	case iss_t::XTN_DCACHE_INVAL: // dcache, dtlb & itlb access
2392	r_dcache_fsm = DCACHE_XTN_DC_INVAL_VA;
2393	break;
2394
2395	case iss_t::XTN_MMU_DCACHE_PA_INV: // dcache, dtlb & itlb access
2396	r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA;
2397	if (sizeof(paddr_t) <= 32) {
2398	assert(r_mmu_word_hi.read() == 0 &&
2399	"high bits should be 0 for 32bit paddr");
2400	r_dcache_p0_paddr =
2401	(paddr_t)r_mmu_word_lo.read();
2402	} else {
2403	r_dcache_p0_paddr =
2404	(paddr_t)r_mmu_word_hi.read() << 32 \|
2405	(paddr_t)r_mmu_word_lo.read();
2406	}
2407	break;
2408
2409	case iss_t::XTN_DCACHE_FLUSH: // itlb and dtlb must be reset
2410	r_dcache_flush_count = 0;
2411	r_dcache_fsm = DCACHE_XTN_DC_FLUSH;
2412	break;
2413
2414	case iss_t::XTN_ICACHE_INVAL: // icache and itlb access
2415	r_dcache_xtn_req = true;
2416	r_dcache_fsm = DCACHE_XTN_IC_INVAL_VA;
2417	break;
2418
2419	case iss_t::XTN_MMU_ICACHE_PA_INV: // icache access
2420	r_dcache_xtn_req = true;
2421	r_dcache_fsm = DCACHE_XTN_IC_INVAL_PA;
2422	break;
2423
2424	case iss_t::XTN_ICACHE_FLUSH: // icache access
2425	r_dcache_xtn_req = true;
2426	r_dcache_fsm = DCACHE_XTN_IC_FLUSH;
2427	break;
2428
2429	case iss_t::XTN_SYNC: // wait until write buffer empty
2430	r_dcache_fsm = DCACHE_XTN_SYNC;
2431	break;
2432
2433	case iss_t::XTN_MMU_WORD_LO: // no cache or tlb access
2434	r_mmu_word_lo = m_dreq.wdata;
2435	m_drsp.valid = true;
2436	r_dcache_fsm = DCACHE_IDLE;
2437	break;
2438
2439	case iss_t::XTN_MMU_WORD_HI: // no cache or tlb access
2440	r_mmu_word_hi = m_dreq.wdata;
2441	m_drsp.valid = true;
2442	r_dcache_fsm = DCACHE_IDLE;
2443	break;
2444
2445	case iss_t::XTN_ICACHE_PREFETCH: // not implemented : no action
2446	case iss_t::XTN_DCACHE_PREFETCH: // not implemented : no action
2447	m_drsp.valid = true;
2448	r_dcache_fsm = DCACHE_IDLE;
2449	break;
2450
2451	case iss_t::XTN_DEBUG_MASK: // debug mask
2452	m_debug_dcache_fsm = ((m_dreq.wdata & 0x1) != 0);
2453	m_debug_icache_fsm = ((m_dreq.wdata & 0x2) != 0);
2454	m_debug_cleanup_fsm = ((m_dreq.wdata & 0x4) != 0);
2455	m_drsp.valid = true;
2456	r_dcache_fsm = DCACHE_IDLE;
2457	break;
2458
2459	default:
2460	r_mmu_detr = MMU_WRITE_UNDEFINED_XTN;
2461	r_mmu_dbvar = m_dreq.addr;
2462	m_drsp.valid = true;
2463	m_drsp.error = true;
2464	r_dcache_fsm = DCACHE_IDLE;
2465	break;
2466	} // end switch xtn_opcode
2467	} // end else
2468	r_dcache_p0_valid = false;
2469	} // end if XTN_WRITE
2470
2471	// Handling read/write/ll/sc processor requests.
2472	// The dtlb and dcache can be activated or not.
2473	// We compute the physical address, the cacheability, and check processor request.
2474	// - If DTLB not activated : cacheability is defined by the segment table,
2475	// the physical address is equal to the virtual address (identity mapping)
2476	// - If DTLB activated : cacheability is defined by the C bit in the PTE,
2477	// the physical address is obtained from the TLB, and the U & W bits
2478	// of the PTE are checked.
2479	// The processor request is decoded only if the TLB is not activated or if
2480	// the virtual address hits in tLB and access rights are OK.
2481	// We call the TLB_MISS sub-fsm in case of dtlb miss.
2482	else
2483	{
2484	bool valid_req = false;
2485	bool cacheable = false;
2486	paddr_t paddr = 0;
2487
2488	if ( not (r_mmu_mode.read() & DATA_TLB_MASK) ) // dtlb not activated
2489	{
2490	valid_req = true;
2491
2492	// cacheability
2493	if ( not (r_mmu_mode.read() & DATA_CACHE_MASK) ) cacheable = false;
2494	else cacheable = m_cacheability_table[m_dreq.addr];
2495
2496	// physical address
2497	paddr = (paddr_t)m_dreq.addr;
2498	}
2499	else // dtlb activated
2500	{
2501	if ( tlb_hit ) // tlb hit
2502	{
2503	// cacheability
2504	if ( not (r_mmu_mode.read() & DATA_CACHE_MASK) ) cacheable = false;
2505	else cacheable = tlb_flags.c;
2506
2507	// access rights checking
2508	if ( not tlb_flags.u and (m_dreq.mode == iss_t::MODE_USER))
2509	{
2510	if ( (m_dreq.type == iss_t::DATA_READ) or (m_dreq.type == iss_t::DATA_LL) )
2511	r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION;
2512	else
2513	r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION;
2514
2515	r_mmu_dbvar = m_dreq.addr;
2516	m_drsp.valid = true;
2517	m_drsp.error = true;
2518	m_drsp.rdata = 0;
2519	#if DEBUG_DCACHE
2520	if ( m_debug_dcache_fsm )
2521	{
2522	std::cout << " <PROC " << name() << ".DCACHE_IDLE> HIT in dtlb, but privilege violation" << std::endl;
2523	}
2524	#endif
2525	}
2526	else if ( not tlb_flags.w and
2527	((m_dreq.type == iss_t::DATA_WRITE) or
2528	(m_dreq.type == iss_t::DATA_SC)) )
2529	{
2530	r_mmu_detr = MMU_WRITE_ACCES_VIOLATION;
2531	r_mmu_dbvar = m_dreq.addr;
2532	m_drsp.valid = true;
2533	m_drsp.error = true;
2534	m_drsp.rdata = 0;
2535	#if DEBUG_DCACHE
2536	if ( m_debug_dcache_fsm )
2537	{
2538	std::cout << " <PROC " << name() << ".DCACHE_IDLE> HIT in dtlb, but writable violation" << std::endl;
2539	}
2540	#endif
2541	}
2542	else
2543	{
2544	valid_req = true;
2545	}
2546
2547	// physical address
2548	paddr = tlb_paddr;
2549	}
2550	else // tlb miss
2551	{
2552	r_dcache_tlb_vaddr = m_dreq.addr;
2553	r_dcache_tlb_ins = false;
2554	r_dcache_fsm = DCACHE_TLB_MISS;
2555	}
2556	} // end DTLB activated
2557
2558	if ( valid_req ) // processor request is valid after TLB check
2559	{
2560	// physical address and cacheability registration
2561	r_dcache_p0_paddr = paddr;
2562	r_dcache_p0_cacheable = cacheable;
2563
2564	// READ request
2565	// The read requests are taken only if the write pipe-line is empty.
2566	// If dcache hit, dtlb hit, and speculative PPN OK, data in one cycle.
2567	// If speculative access is KO we just pay one extra cycle.
2568	// If dcache miss, we go to DCACHE_MISS_VICTIM state.
2569	// If uncacheable, we go to DCACHE_UNC_WAIT state.
2570	if ( ((m_dreq.type == iss_t::DATA_READ))
2571	and not r_dcache_p0_valid.read() and not r_dcache_p1_valid.read() )
2572	{
2573	if ( cacheable ) // cacheable read
2574	{
2575	// if the speculative access is illegal, we pay an extra cycle
2576	if ( (r_dcache_p0_paddr.read() & ~PAGE_K_MASK)
2577	!= (paddr & ~PAGE_K_MASK))
2578	{
2579	#ifdef INSTRUMENTATION
2580	m_cpt_dcache_spec_miss++;
2581	#endif
2582	#if DEBUG_DCACHE
2583	if ( m_debug_dcache_fsm )
2584	{
2585	std::cout << " <PROC " << name() << ".DCACHE_IDLE> Speculative access miss" << std::endl;
2586	}
2587	#endif
2588	}
2589	// if cache miss, try to get the missing line
2590	else if ( not cache_hit )
2591	{
2592	#ifdef INSTRUMENTATION
2593	m_cpt_dcache_miss++;
2594	#endif
2595	r_dcache_vci_paddr = paddr;
2596	r_dcache_vci_miss_req = true;
2597	r_dcache_miss_type = PROC_MISS;
2598	r_dcache_fsm = DCACHE_MISS_VICTIM;
2599	}
2600	// if cache hit return the data
2601	else
2602	{
2603	#ifdef INSTRUMENTATION
2604	m_cpt_data_read++;
2605	#endif
2606	m_drsp.valid = true;
2607	m_drsp.rdata = cache_rdata;
2608	#if DEBUG_DCACHE
2609	if ( m_debug_dcache_fsm )
2610	{
2611	std::cout << " <PROC " << name() << ".DCACHE_IDLE> HIT read in dcache"
2612	<< " / PADDR=" << std::hex << paddr
2613	<< std::endl;
2614	}
2615	#endif
2616	}
2617	}
2618	else // uncacheable read
2619	{
2620	r_dcache_vci_paddr = paddr;
2621	r_dcache_vci_unc_be = m_dreq.be;
2622	r_dcache_vci_unc_req = true;
2623	r_dcache_fsm = DCACHE_UNC_WAIT;
2624	}
2625
2626	r_dcache_p0_valid = false;
2627	} // end READ
2628
2629	// LL request
2630	// The LL requests are taken only if the write pipe-line is empty.
2631	// We request an LL transaction to CMD FSM and go to
2632	// DCACHE_LL_WAIT state, that will return the response to
2633	// the processor.
2634	else if ( ((m_dreq.type == iss_t::DATA_LL))
2635	and not r_dcache_p0_valid.read() and not r_dcache_p1_valid.read() )
2636	{
2637	// prepare llsc local table access
2638	table_in.cmd = LLSCLocalTable::LL_CMD ;
2639	table_in.address = paddr;
2640	// access the table
2641	r_llsc_table.exec(table_in, table_out);
2642	llsc_local_table_access_done = true;
2643	// test if the table is done
2644	if(!table_out.done)
2645	{
2646	r_dcache_p0_valid = false;
2647	break;
2648	}
2649	// request an LL CMD and go to DCACHE_LL_WAIT state
2650	r_dcache_vci_ll_req = true;
2651	r_dcache_ll_rsp_count = 0;
2652	r_dcache_p0_valid = false;
2653	r_dcache_vci_paddr = paddr;
2654	r_dcache_fsm = DCACHE_LL_WAIT;
2655	}// end LL
2656
2657	// WRITE request:
2658	// If the TLB is activated and the PTE Dirty bit is not set, we stall
2659	// the processor and set the Dirty bit before handling the write request.
2660	// If we don't need to set the Dirty bit, we can acknowledge
2661	// the processor request, as the write arguments (including the
2662	// physical address) are registered in r_dcache_p0 registers:
2663	// We simply activate the P1 pipeline stage.
2664	else if ( m_dreq.type == iss_t::DATA_WRITE )
2665	{
2666	if ( (r_mmu_mode.read() & DATA_TLB_MASK )
2667	and not tlb_flags.d ) // Dirty bit must be set
2668	{
2669	// The PTE physical address is obtained from the nline value (dtlb),
2670	// and the word index (proper bits of the virtual address)
2671	if ( tlb_flags.b ) // PTE1
2672	{
2673	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2674	(paddr_t)((m_dreq.addr>>19) & 0x3c);
2675	}
2676	else // PTE2
2677	{
2678	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2679	(paddr_t)((m_dreq.addr>>9) & 0x38);
2680	}
2681	r_dcache_fsm = DCACHE_DIRTY_GET_PTE;
2682	r_dcache_p0_valid = false;
2683	}
2684	else // Write request accepted
2685	{
2686	#ifdef INSTRUMENTATION
2687	m_cpt_data_write++;
2688	#endif
2689	table_in.cmd = LLSCLocalTable::SW_CMD ;
2690	table_in.address = paddr;
2691	r_llsc_table.exec(table_in, table_out) ;
2692	llsc_local_table_access_done = true;
2693	if(!table_out.done)
2694	{
2695	r_dcache_p0_valid = false;
2696	break;
2697	}
2698	m_drsp.valid = true;
2699	m_drsp.rdata = 0;
2700	r_dcache_p0_valid = true;
2701	}
2702	} // end WRITE
2703
2704	// SC request:
2705	// The SC requests are taken only if the write pipe-line is empty.
2706	// We test if a DIRTY bit update is required.
2707	// If the TLB is activated and the PTE Dirty bit is not set, we stall
2708	// the processor and set the Dirty bit before handling the write request.
2709	// If we don't need to set the Dirty bit, we request a SC transaction
2710	// to CMD FSM and go to DCACHE_SC_WAIT state, that will return
2711	// the response to the processor.
2712	// We don't check a possible write hit in dcache, as the cache update
2713	// is done by the coherence transaction induced by the SC...
2714	else if ( ( m_dreq.type == iss_t::DATA_SC )
2715	and not r_dcache_p0_valid.read() and not r_dcache_p1_valid.read() )
2716	{
2717	if ( (r_mmu_mode.read() & DATA_TLB_MASK )
2718	and not tlb_flags.d ) // Dirty bit must be set
2719	{
2720	// The PTE physical address is obtained from the nline value (dtlb),
2721	// and the word index (virtual address)
2722	if ( tlb_flags.b ) // PTE1
2723	{
2724	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2725	(paddr_t)((m_dreq.addr>>19) & 0x3c);
2726	}
2727	else // PTE2
2728	{
2729	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2730	(paddr_t)((m_dreq.addr>>9) & 0x38);
2731	}
2732	r_dcache_fsm = DCACHE_DIRTY_GET_PTE;
2733	}
2734	else // SC request accepted
2735	{
2736	#ifdef INSTRUMENTATION
2737	m_cpt_data_sc++;
2738	#endif
2739	// prepare llsc local table access
2740	table_in.cmd = LLSCLocalTable::SC_CMD ;
2741	table_in.address = paddr;
2742	// access the table
2743	r_llsc_table.exec(table_in, table_out) ;
2744	llsc_local_table_access_done = true;
2745	// test if the table is done
2746	if(!table_out.done)
2747	{
2748	r_dcache_p0_valid = false;
2749	break;
2750	}
2751	// test for a local fail
2752	if(table_out.hit)
2753	{
2754	// request an SC CMD and go to DCACHE_SC_WAIT state
2755	r_sc_key = table_out.key;
2756	r_dcache_vci_paddr = paddr;
2757	r_dcache_vci_sc_req = true;
2758	r_dcache_vci_sc_data = m_dreq.wdata;
2759	r_dcache_fsm = DCACHE_SC_WAIT;
2760	}
2761	else // local fail
2762	{
2763	m_drsp.valid = true;
2764	m_drsp.rdata = 0x1;
2765	}
2766	}
2767	r_dcache_p0_valid = false;
2768	} // end SC
2769	else
2770	{
2771	r_dcache_p0_valid = false;
2772	}
2773	} // end valid_req
2774	else
2775	{
2776	r_dcache_p0_valid = false;
2777	}
2778	} // end if read/write/ll/sc request
2779	} // end dreq.valid
2780
2781	// itlb miss request
2782	else if ( r_icache_tlb_miss_req.read() )
2783	{
2784	r_dcache_tlb_ins = true;
2785	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
2786	r_dcache_fsm = DCACHE_TLB_MISS;
2787	r_dcache_p0_valid = r_dcache_p0_valid.read() and write_pipe_frozen;
2788	}
2789	else
2790	{
2791	r_dcache_p0_valid = r_dcache_p0_valid.read() and write_pipe_frozen;
2792	} // end P0 pipe stage
2793	break;
2794	}
2795	/////////////////////
2796	case DCACHE_TLB_MISS: // This is the entry point for the sub-fsm handling all tlb miss.
2797	// Input arguments are:
2798	// - r_dcache_tlb_vaddr
2799	// - r_dcache_tlb_ins (true when itlb miss)
2800	// The sub-fsm access the dcache to find the missing TLB entry,
2801	// and activates the cache miss procedure in case of miss.
2802	// It bypass the first level page table access if possible.
2803	// It uses atomic access to update the R/L access bits
2804	// in the page table if required.
2805	// It directly updates the itlb or dtlb, and writes into the
2806	// r_mmu_ins_* or r_mmu_data* error reporting registers.
2807	{
2808	uint32_t ptba = 0;
2809	bool bypass;
2810	paddr_t pte_paddr;
2811
2812	// evaluate bypass in order to skip first level page table access
2813	if ( r_dcache_tlb_ins.read() ) // itlb miss
2814	{
2815	bypass = r_itlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba);
2816	}
2817	else // dtlb miss
2818	{
2819	bypass = r_dtlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba);
2820	}
2821
2822	if ( not bypass ) // Try to read PTE1/PTD1 in dcache
2823	{
2824	pte_paddr = (paddr_t)r_mmu_ptpr.read() << (INDEX1_NBITS+2) \|
2825	(paddr_t)((r_dcache_tlb_vaddr.read() >> PAGE_M_NBITS) << 2);
2826	r_dcache_tlb_paddr = pte_paddr;
2827	r_dcache_fsm = DCACHE_TLB_PTE1_GET;
2828	}
2829	else // Try to read PTE2 in dcache
2830	{
2831	pte_paddr = (paddr_t)ptba << PAGE_K_NBITS \|
2832	(paddr_t)(r_dcache_tlb_vaddr.read()&PTD_ID2_MASK)>>(PAGE_K_NBITS-3);
2833	r_dcache_tlb_paddr = pte_paddr;
2834	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
2835	}
2836
2837	#if DEBUG_DCACHE
2838	if ( m_debug_dcache_fsm )
2839	{
2840	if ( r_dcache_tlb_ins.read() )
2841	{
2842	std::cout << " <PROC " << name() << ".DCACHE_TLB_MISS> ITLB miss";
2843	}
2844	else
2845	{
2846	std::cout << " <PROC " << name() << ".DCACHE_TLB_MISS> DTLB miss";
2847	}
2848	std::cout << " / VADDR = " << std::hex << r_dcache_tlb_vaddr.read()
2849	<< " / BYPASS = " << bypass
2850	<< " / PTE_ADR = " << pte_paddr << std::endl;
2851	}
2852	#endif
2853
2854	break;
2855	}
2856	/////////////////////////
2857	case DCACHE_TLB_PTE1_GET: // try to read a PT1 entry in dcache
2858	{
2859	uint32_t entry;
2860	size_t way;
2861	size_t set;
2862	size_t word;
2863
2864	bool hit = r_dcache.read( r_dcache_tlb_paddr.read(),
2865	&entry,
2866	&way,
2867	&set,
2868	&word );
2869	#ifdef INSTRUMENTATION
2870	m_cpt_dcache_data_read++;
2871	m_cpt_dcache_dir_read++;
2872	#endif
2873	if ( hit ) // hit in dcache
2874	{
2875	if ( not (entry & PTE_V_MASK) ) // unmapped
2876	{
2877	if ( r_dcache_tlb_ins.read() )
2878	{
2879	r_mmu_ietr = MMU_READ_PT1_UNMAPPED;
2880	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
2881	r_icache_tlb_miss_req = false;
2882	r_icache_tlb_rsp_error = true;
2883	}
2884	else
2885	{
2886	r_mmu_detr = MMU_READ_PT1_UNMAPPED;
2887	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
2888	m_drsp.valid = true;
2889	m_drsp.error = true;
2890	}
2891	r_dcache_fsm = DCACHE_IDLE;
2892
2893	#if DEBUG_DCACHE
2894	if ( m_debug_dcache_fsm )
2895	{
2896	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_GET> HIT in dcache, but unmapped"
2897	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
2898	<< std::dec << " / way = " << way
2899	<< std::dec << " / set = " << set
2900	<< std::dec << " / word = " << word
2901	<< std::hex << " / PTE1 = " << entry << std::endl;
2902	}
2903	#endif
2904
2905	}
2906	else if( entry & PTE_T_MASK ) // PTD : me must access PT2
2907	{
2908	// mark the cache line ac containing a PTD
2909	r_dcache_contains_ptd[m_dcache_sets*way+set] = true;
2910
2911	// register bypass
2912	if ( r_dcache_tlb_ins.read() ) // itlb
2913	{
2914	r_itlb.set_bypass(r_dcache_tlb_vaddr.read(),
2915	entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1),
2916	r_dcache_tlb_paddr.read() >> (uint32_log2(m_icache_words<<2)));
2917	}
2918	else // dtlb
2919	{
2920	r_dtlb.set_bypass(r_dcache_tlb_vaddr.read(),
2921	entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1),
2922	r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2));
2923	}
2924	r_dcache_tlb_paddr = (paddr_t)(entry & ((1<<(m_paddr_nbits-PAGE_K_NBITS))-1)) << PAGE_K_NBITS \|
2925	(paddr_t)(((r_dcache_tlb_vaddr.read() & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3);
2926	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
2927
2928	#if DEBUG_DCACHE
2929	if ( m_debug_dcache_fsm )
2930	{
2931	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_GET> HIT in dcache"
2932	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
2933	<< std::dec << " / way = " << way
2934	<< std::dec << " / set = " << set
2935	<< std::dec << " / word = " << word
2936	<< std::hex << " / PTD = " << entry << std::endl;
2937	}
2938	#endif
2939	}
2940	else // PTE1 : we must update the TLB
2941	{
2942	r_dcache_in_tlb[m_icache_sets*way+set] = true;
2943	r_dcache_tlb_pte_flags = entry;
2944	r_dcache_tlb_cache_way = way;
2945	r_dcache_tlb_cache_set = set;
2946	r_dcache_tlb_cache_word = word;
2947	r_dcache_fsm = DCACHE_TLB_PTE1_SELECT;
2948
2949	#if DEBUG_DCACHE
2950	if ( m_debug_dcache_fsm )
2951	{
2952	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_GET> HIT in dcache"
2953	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
2954	<< std::dec << " / way = " << way
2955	<< std::dec << " / set = " << set
2956	<< std::dec << " / word = " << word
2957	<< std::hex << " / PTE1 = " << entry << std::endl;
2958	}
2959	#endif
2960	}
2961	}
2962	else // we must load the missing cache line in dcache
2963	{
2964	r_dcache_vci_miss_req = true;
2965	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
2966	r_dcache_miss_type = PTE1_MISS;
2967	r_dcache_fsm = DCACHE_MISS_VICTIM;
2968
2969	#if DEBUG_DCACHE
2970	if ( m_debug_dcache_fsm )
2971	{
2972	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_GET> MISS in dcache:"
2973	<< " PTE1 address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
2974	}
2975	#endif
2976	}
2977	break;
2978	}
2979	////////////////////////////
2980	case DCACHE_TLB_PTE1_SELECT: // select a slot for PTE1
2981	{
2982	size_t way;
2983	size_t set;
2984
2985	if ( r_dcache_tlb_ins.read() )
2986	{
2987	r_itlb.select( r_dcache_tlb_vaddr.read(),
2988	true, // PTE1
2989	&way,
2990	&set );
2991	#ifdef INSTRUMENTATION
2992	m_cpt_itlb_read++;
2993	#endif
2994	}
2995	else
2996	{
2997	r_dtlb.select( r_dcache_tlb_vaddr.read(),
2998	true, // PTE1
2999	&way,
3000	&set );
3001	#ifdef INSTRUMENTATION
3002	m_cpt_dtlb_read++;
3003	#endif
3004	}
3005	r_dcache_tlb_way = way;
3006	r_dcache_tlb_set = set;
3007	r_dcache_fsm = DCACHE_TLB_PTE1_UPDT;
3008
3009	#if DEBUG_DCACHE
3010	if ( m_debug_dcache_fsm )
3011	{
3012	if ( r_dcache_tlb_ins.read() )
3013	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_SELECT> Select a slot in ITLB:";
3014	else
3015	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_SELECT> Select a slot in DTLB:";
3016	std::cout << " way = " << std::dec << way
3017	<< " / set = " << set << std::endl;
3018	}
3019	#endif
3020	break;
3021	}
3022	//////////////////////////
3023	case DCACHE_TLB_PTE1_UPDT: // write a new PTE1 in tlb after testing the L/R bit
3024	// - if L/R bit already set, exit the sub-fsm.
3025	// - if not, we update the page table but we dont write
3026	// neither in DCACHE, nor in TLB, as this will be done by
3027	// the coherence mechanism.
3028	{
3029	paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2);
3030	uint32_t pte = r_dcache_tlb_pte_flags.read();
3031	bool pt_updt = false;
3032	bool local = true;
3033
3034	// We should compute the access locality:
3035	// The PPN MSB bits define the destination cluster index.
3036	// The m_srcid_d MSB bits define the source cluster index.
3037	// The number of bits to compare depends on the number of clusters,
3038	// and can be obtained in the mapping table.
3039	// As long as this computation is not done, all access are local.
3040
3041	if ( local ) // local access
3042	{
3043	if ( not ((pte & PTE_L_MASK) == PTE_L_MASK) ) // we must set the L bit
3044	{
3045	pt_updt = true;
3046	r_dcache_vci_cas_old = pte;
3047	r_dcache_vci_cas_new = pte \| PTE_L_MASK;
3048	pte = pte \| PTE_L_MASK;
3049	r_dcache_tlb_pte_flags = pte;
3050	}
3051	}
3052	else // remote access
3053	{
3054	if ( not ((pte & PTE_R_MASK) == PTE_R_MASK) ) // we must set the R bit
3055	{
3056	pt_updt = true;
3057	r_dcache_vci_cas_old = pte;
3058	r_dcache_vci_cas_new = pte \| PTE_R_MASK;
3059	pte = pte \| PTE_R_MASK;
3060	r_dcache_tlb_pte_flags = pte;
3061	}
3062	}
3063
3064	if ( not pt_updt ) // update TLB and return
3065	{
3066	if ( r_dcache_tlb_ins.read() )
3067	{
3068	r_itlb.write( true, // 2M page
3069	pte,
3070	0, // argument unused for a PTE1
3071	r_dcache_tlb_vaddr.read(),
3072	r_dcache_tlb_way.read(),
3073	r_dcache_tlb_set.read(),
3074	nline );
3075	#ifdef INSTRUMENTATION
3076	m_cpt_itlb_write++;
3077	#endif
3078
3079	#if DEBUG_DCACHE
3080	if ( m_debug_dcache_fsm )
3081	{
3082	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_UPDT> write PTE1 in ITLB";
3083	std::cout << " / set = " << std::dec << r_dcache_tlb_set.read()
3084	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3085	r_itlb.printTrace();
3086	}
3087	#endif
3088	}
3089	else
3090	{
3091	r_dtlb.write( true, // 2M page
3092	pte,
3093	0, // argument unused for a PTE1
3094	r_dcache_tlb_vaddr.read(),
3095	r_dcache_tlb_way.read(),
3096	r_dcache_tlb_set.read(),
3097	nline );
3098	#ifdef INSTRUMENTATION
3099	m_cpt_dtlb_write++;
3100	#endif
3101
3102	#if DEBUG_DCACHE
3103	if ( m_debug_dcache_fsm )
3104	{
3105	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_UPDT> write PTE1 in DTLB";
3106	std::cout << " / set = " << std::dec << r_dcache_tlb_set.read()
3107	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3108	r_dtlb.printTrace();
3109	}
3110	#endif
3111	}
3112	r_dcache_fsm = DCACHE_TLB_RETURN;
3113	}
3114	else // update page table but not TLB
3115	{
3116	r_dcache_fsm = DCACHE_TLB_LR_UPDT;
3117
3118	#if DEBUG_DCACHE
3119	if ( m_debug_dcache_fsm )
3120	{
3121	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_UPDT> L/R bit update required"
3122	<< std::endl;
3123	}
3124	#endif
3125	}
3126	break;
3127	}
3128	/////////////////////////
3129	case DCACHE_TLB_PTE2_GET: // Try to get a PTE2 (64 bits) in the dcache
3130	{
3131	uint32_t pte_flags;
3132	uint32_t pte_ppn;
3133	size_t way;
3134	size_t set;
3135	size_t word;
3136
3137	bool hit = r_dcache.read( r_dcache_tlb_paddr.read(),
3138	&pte_flags,
3139	&pte_ppn,
3140	&way,
3141	&set,
3142	&word );
3143	#ifdef INSTRUMENTATION
3144	m_cpt_dcache_data_read++;
3145	m_cpt_dcache_dir_read++;
3146	#endif
3147	if ( hit ) // request hits in dcache
3148	{
3149	if ( not (pte_flags & PTE_V_MASK) ) // unmapped
3150	{
3151	if ( r_dcache_tlb_ins.read() )
3152	{
3153	r_mmu_ietr = MMU_READ_PT2_UNMAPPED;
3154	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3155	r_icache_tlb_miss_req = false;
3156	r_icache_tlb_rsp_error = true;
3157	}
3158	else
3159	{
3160	r_mmu_detr = MMU_READ_PT2_UNMAPPED;
3161	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3162	m_drsp.valid = true;
3163	m_drsp.error = true;
3164	}
3165	r_dcache_fsm = DCACHE_IDLE;
3166
3167	#if DEBUG_DCACHE
3168	if ( m_debug_dcache_fsm )
3169	{
3170	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE2_GET> HIT in dcache, but PTE is unmapped"
3171	<< " PTE_FLAGS = " << std::hex << pte_flags
3172	<< " PTE_PPN = " << std::hex << pte_ppn << std::endl;
3173	}
3174	#endif
3175	}
3176	else // mapped : we must update the TLB
3177	{
3178	r_dcache_in_tlb[m_dcache_sets*way+set] = true;
3179	r_dcache_tlb_pte_flags = pte_flags;
3180	r_dcache_tlb_pte_ppn = pte_ppn;
3181	r_dcache_tlb_cache_way = way;
3182	r_dcache_tlb_cache_set = set;
3183	r_dcache_tlb_cache_word = word;
3184	r_dcache_fsm = DCACHE_TLB_PTE2_SELECT;
3185
3186	#if DEBUG_DCACHE
3187	if ( m_debug_dcache_fsm )
3188	{
3189	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE2_GET> HIT in dcache:"
3190	<< " PTE_FLAGS = " << std::hex << pte_flags
3191	<< " PTE_PPN = " << std::hex << pte_ppn << std::endl;
3192	}
3193	#endif
3194	}
3195	}
3196	else // we must load the missing cache line in dcache
3197	{
3198	r_dcache_fsm = DCACHE_MISS_VICTIM;
3199	r_dcache_vci_miss_req = true;
3200	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
3201	r_dcache_miss_type = PTE2_MISS;
3202
3203	#if DEBUG_DCACHE
3204	if ( m_debug_dcache_fsm )
3205	{
3206	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE2_GET> MISS in dcache:"
3207	<< " PTE address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
3208	}
3209	#endif
3210	}
3211	break;
3212	}
3213	////////////////////////////
3214	case DCACHE_TLB_PTE2_SELECT: // select a slot for PTE2
3215	{
3216	size_t way;
3217	size_t set;
3218
3219	if ( r_dcache_tlb_ins.read() )
3220	{
3221	r_itlb.select( r_dcache_tlb_vaddr.read(),
3222	false, // PTE2
3223	&way,
3224	&set );
3225	#ifdef INSTRUMENTATION
3226	m_cpt_itlb_read++;
3227	#endif
3228	}
3229	else
3230	{
3231	r_dtlb.select( r_dcache_tlb_vaddr.read(),
3232	false, // PTE2
3233	&way,
3234	&set );
3235	#ifdef INSTRUMENTATION
3236	m_cpt_dtlb_read++;
3237	#endif
3238	}
3239
3240	#if DEBUG_DCACHE
3241	if ( m_debug_dcache_fsm )
3242	{
3243	if ( r_dcache_tlb_ins.read() )
3244	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB:";
3245	else
3246	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE2_SELECT> Select a slot in DTLB:";
3247	std::cout << " way = " << std::dec << way
3248	<< " / set = " << set << std::endl;
3249	}
3250	#endif
3251	r_dcache_tlb_way = way;
3252	r_dcache_tlb_set = set;
3253	r_dcache_fsm = DCACHE_TLB_PTE2_UPDT;
3254	break;
3255	}
3256	//////////////////////////
3257	case DCACHE_TLB_PTE2_UPDT: // write a new PTE2 in tlb after testing the L/R bit
3258	// - if L/R bit already set, exit the sub-fsm.
3259	// - if not, we update the page table but we dont write
3260	// neither in DCACHE, nor in TLB, as this will be done by
3261	// the coherence mechanism.
3262	{
3263	paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2);
3264	uint32_t pte_flags = r_dcache_tlb_pte_flags.read();
3265	uint32_t pte_ppn = r_dcache_tlb_pte_ppn.read();
3266	bool pt_updt = false;
3267	bool local = true;
3268
3269	// We should compute the access locality:
3270	// The PPN MSB bits define the destination cluster index.
3271	// The m_srcid_d MSB bits define the source cluster index.
3272	// The number of bits to compare depends on the number of clusters,
3273	// and can be obtained in the mapping table.
3274	// As long as this computation is not done, all access are local.
3275
3276	if ( local ) // local access
3277	{
3278	if ( not ((pte_flags & PTE_L_MASK) == PTE_L_MASK) ) // we must set the L bit
3279	{
3280	pt_updt = true;
3281	r_dcache_vci_cas_old = pte_flags;
3282	r_dcache_vci_cas_new = pte_flags \| PTE_L_MASK;
3283	pte_flags = pte_flags \| PTE_L_MASK;
3284	r_dcache_tlb_pte_flags = pte_flags;
3285	}
3286	}
3287	else // remote access
3288	{
3289	if ( not ((pte_flags & PTE_R_MASK) == PTE_R_MASK) ) // we must set the R bit
3290	{
3291	pt_updt = true;
3292	r_dcache_vci_cas_old = pte_flags;
3293	r_dcache_vci_cas_new = pte_flags \| PTE_R_MASK;
3294	pte_flags = pte_flags \| PTE_R_MASK;
3295	r_dcache_tlb_pte_flags = pte_flags;
3296	}
3297	}
3298
3299	if ( not pt_updt ) // update TLB
3300	{
3301	if ( r_dcache_tlb_ins.read() )
3302	{
3303	r_itlb.write( false, // 4K page
3304	pte_flags,
3305	pte_ppn,
3306	r_dcache_tlb_vaddr.read(),
3307	r_dcache_tlb_way.read(),
3308	r_dcache_tlb_set.read(),
3309	nline );
3310	#ifdef INSTRUMENTATION
3311	m_cpt_itlb_write++;
3312	#endif
3313
3314	#if DEBUG_DCACHE
3315	if ( m_debug_dcache_fsm )
3316	{
3317	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE2_UPDT> write PTE2 in ITLB";
3318	std::cout << " / set = " << std::dec << r_dcache_tlb_set.read()
3319	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3320	r_itlb.printTrace();
3321	}
3322	#endif
3323	}
3324	else
3325	{
3326	r_dtlb.write( false, // 4K page
3327	pte_flags,
3328	pte_ppn,
3329	r_dcache_tlb_vaddr.read(),
3330	r_dcache_tlb_way.read(),
3331	r_dcache_tlb_set.read(),
3332	nline );
3333	#ifdef INSTRUMENTATION
3334	m_cpt_dtlb_write++;
3335	#endif
3336
3337	#if DEBUG_DCACHE
3338	if ( m_debug_dcache_fsm )
3339	{
3340	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE2_UPDT> write PTE2 in DTLB";
3341	std::cout << " / set = " << std::dec << r_dcache_tlb_set.read()
3342	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3343	r_dtlb.printTrace();
3344	}
3345	#endif
3346
3347	}
3348	r_dcache_fsm = DCACHE_TLB_RETURN;
3349	}
3350	else // update page table but not TLB
3351	{
3352	r_dcache_fsm = DCACHE_TLB_LR_UPDT; // dcache and page table update
3353
3354	#if DEBUG_DCACHE
3355	if ( m_debug_dcache_fsm )
3356	{
3357	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE2_UPDT> L/R bit update required"
3358	<< std::endl;
3359	}
3360	#endif
3361	}
3362	break;
3363	}
3364	////////////////////////
3365	case DCACHE_TLB_LR_UPDT: // request a SC transaction to update L/R bit
3366	{
3367	#if DEBUG_DCACHE
3368	if ( m_debug_dcache_fsm )
3369	{
3370	std::cout << " <PROC " << name() << ".DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit" << std::endl;
3371	}
3372	#endif
3373	// r_dcache_vci_cas_old & r_dcache_vci_cas_new registers are already set
3374	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
3375	// prepare llsc local table access
3376	table_in.cmd = LLSCLocalTable::SW_CMD;
3377	table_in.address = r_dcache_tlb_paddr.read();
3378	// access the table
3379	r_llsc_table.exec(table_in, table_out);
3380	llsc_local_table_access_done = true;
3381	// test if the table is done
3382	if(!table_out.done)
3383	break;
3384	// request a CAS CMD and go to DCACHE_TLB_LR_WAIT state
3385	r_dcache_vci_cas_req = true;
3386	r_dcache_fsm = DCACHE_TLB_LR_WAIT;
3387	break;
3388	}
3389	////////////////////////
3390	case DCACHE_TLB_LR_WAIT: // Waiting the response to SC transaction for DIRTY bit.
3391	// We consume the response in rsp FIFO,
3392	// and exit the sub-fsm, but we don't
3393	// analyse the response, because we don't
3394	// care if the L/R bit update is not done.
3395	// We must take the coherence requests because
3396	// there is a risk of dead-lock
3397
3398	{
3399	// external coherence request
3400	if ( r_tgt_dcache_req )
3401	{
3402	r_dcache_fsm = DCACHE_CC_CHECK;
3403	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3404	break;
3405	}
3406
3407	if ( r_vci_rsp_data_error.read() ) // bus error
3408	{
3409	std::cout << "BUS ERROR in DCACHE_TLB_LR_WAIT state" << std::endl;
3410	std::cout << "This should not happen in this state" << std::endl;
3411	exit(0);
3412	}
3413	else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
3414	{
3415	#if DEBUG_DCACHE
3416	if ( m_debug_dcache_fsm )
3417	{
3418	std::cout << " <PROC " << name() << ".DCACHE_TLB_LR_WAIT> SC response received" << std::endl;
3419	}
3420	#endif
3421	vci_rsp_fifo_dcache_get = true;
3422	r_dcache_fsm = DCACHE_TLB_RETURN;
3423	}
3424	break;
3425	}
3426	///////////////////////
3427	case DCACHE_TLB_RETURN: // return to caller depending on tlb miss type
3428	{
3429	#if DEBUG_DCACHE
3430	if ( m_debug_dcache_fsm )
3431	{
3432	std::cout << " <PROC " << name() << ".DCACHE_TLB_RETURN> TLB MISS completed" << std::endl;
3433	}
3434	#endif
3435	if ( r_dcache_tlb_ins.read() ) r_icache_tlb_miss_req = false;
3436	r_dcache_fsm = DCACHE_IDLE;
3437	break;
3438	}
3439	///////////////////////
3440	case DCACHE_XTN_SWITCH: // The r_ptpr registers must be written,
3441	// and both itlb and dtlb must be flushed.
3442	// Caution : the itlb miss requests must be taken
3443	// to avoid dead-lock in case of simultaneous ITLB miss
3444	{
3445	// itlb miss request
3446	if ( r_icache_tlb_miss_req.read() )
3447	{
3448	r_dcache_tlb_ins = true;
3449	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
3450	r_dcache_fsm = DCACHE_TLB_MISS;
3451	break;
3452	}
3453
3454	if ( not r_dcache_xtn_req.read() )
3455	{
3456	r_dtlb.flush();
3457	r_mmu_ptpr = m_dreq.wdata;
3458	r_dcache_fsm = DCACHE_IDLE;
3459	m_drsp.valid = true;
3460	#if DEBUG_DCACHE
3461	if ( m_debug_dcache_fsm )
3462	{
3463	std::cout << "<PROC " << name()
3464	<< " SWITCH PTPR>: PADDR=" << std::hex
3465	<< (m_dreq.wdata << (INDEX1_NBITS+2))
3466	<< std::endl;
3467	}
3468	#endif
3469	}
3470	break;
3471	}
3472	/////////////////////
3473	case DCACHE_XTN_SYNC: // waiting until write buffer empty
3474	// The coherence request must be taken
3475	// as there is a risk of dead-lock
3476	{
3477	// external coherence request
3478	if ( r_tgt_dcache_req.read() )
3479	{
3480	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3481	r_dcache_fsm = DCACHE_CC_CHECK;
3482	}
3483
3484	if ( r_wbuf.empty() )
3485	{
3486	m_drsp.valid = true;
3487	r_dcache_fsm = DCACHE_IDLE;
3488	}
3489	break;
3490	}
3491	////////////////////////
3492	case DCACHE_XTN_IC_FLUSH: // Waiting completion of an XTN request to the ICACHE FSM
3493	case DCACHE_XTN_IC_INVAL_VA: // Caution : the itlb miss requests must be taken
3494	case DCACHE_XTN_IC_INVAL_PA: // because the XTN_ICACHE_INVAL request to icache
3495	case DCACHE_XTN_IT_INVAL: // can generate an itlb miss,
3496	// and because it can exist a simultaneous ITLB miss
3497	{
3498	// external coherence request
3499	if ( r_tgt_dcache_req )
3500	{
3501	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3502	r_dcache_fsm = DCACHE_CC_CHECK;
3503	break;
3504	}
3505
3506	// itlb miss request
3507	if ( r_icache_tlb_miss_req.read() )
3508	{
3509	r_dcache_tlb_ins = true;
3510	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
3511	r_dcache_fsm = DCACHE_TLB_MISS;
3512	break;
3513	}
3514
3515	// test if XTN request to icache completed
3516	if ( not r_dcache_xtn_req.read() )
3517	{
3518	r_dcache_fsm = DCACHE_IDLE;
3519	m_drsp.valid = true;
3520	}
3521	break;
3522	}
3523	/////////////////////////
3524	case DCACHE_XTN_DC_FLUSH: // Invalidate sequencially all cache lines, using
3525	// the r_dcache_flush counter as a slot counter.
3526	// We loop in this state until all slots have been visited.
3527	// A cleanup request is generated for each valid line
3528	// and we are blocked until the previous cleanup is completed
3529	// Finally, both the itlb and dtlb are flushed
3530	// (including global entries)
3531	{
3532	if ( not r_dcache_cleanup_req )
3533	{
3534	paddr_t nline;
3535	size_t way = r_dcache_flush_count.read()/m_icache_sets;
3536	size_t set = r_dcache_flush_count.read()%m_icache_sets;
3537
3538	bool cleanup_req = r_dcache.inval( way,
3539	set,
3540	&nline );
3541	if ( cleanup_req )
3542	{
3543	r_dcache_cleanup_req = true;
3544	r_dcache_cleanup_line = nline;
3545	}
3546
3547	r_dcache_in_tlb[m_dcache_sets*way+set] = false;
3548	r_dcache_contains_ptd[m_dcache_sets*way+set] = false;
3549
3550	r_dcache_flush_count = r_dcache_flush_count.read() + 1;
3551
3552	if ( r_dcache_flush_count.read() == (m_dcache_sets*m_dcache_ways - 1) ) // last
3553	{
3554	r_dtlb.reset();
3555	r_itlb.reset();
3556	r_dcache_fsm = DCACHE_IDLE;
3557	m_drsp.valid = true;
3558	}
3559	}
3560	break;
3561	}
3562	/////////////////////////
3563	case DCACHE_XTN_DT_INVAL: // handling processor XTN_DTLB_INVAL request
3564	{
3565	r_dtlb.inval(r_dcache_p0_wdata.read());
3566	r_dcache_fsm = DCACHE_IDLE;
3567	m_drsp.valid = true;
3568	break;
3569	}
3570	////////////////////////////
3571	case DCACHE_XTN_DC_INVAL_VA: // selective cache line invalidate with virtual address
3572	// requires 3 cycles: access tlb, read cache, inval cache
3573	// we compute the physical address in this state
3574	{
3575	paddr_t paddr;
3576	bool hit;
3577
3578	if ( r_mmu_mode.read() & DATA_TLB_MASK ) // dtlb activated
3579	{
3580	#ifdef INSTRUMENTATION
3581	m_cpt_dtlb_read++;
3582	#endif
3583	hit = r_dtlb.translate( r_dcache_p0_wdata.read(),
3584	&paddr );
3585	}
3586	else // dtlb not activated
3587	{
3588	paddr = (paddr_t)r_dcache_p0_wdata.read();
3589	hit = true;
3590	}
3591
3592	if ( hit ) // tlb hit
3593	{
3594	r_dcache_p0_paddr = paddr;
3595	r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA;
3596	}
3597	else // tlb miss
3598	{
3599	#ifdef INSTRUMENTATION
3600	m_cpt_dtlb_miss++;
3601	#endif
3602	r_dcache_tlb_ins = false; // dtlb
3603	r_dcache_tlb_vaddr = r_dcache_p0_wdata.read();
3604	r_dcache_fsm = DCACHE_TLB_MISS;
3605	}
3606
3607	#if DEBUG_DCACHE
3608	if ( m_debug_dcache_fsm )
3609	{
3610	std::cout << " <PROC " << name() << ".DCACHE_XTN_DC_INVAL_VA> Compute physical address" << std::hex
3611	<< " / VADDR = " << r_dcache_p0_wdata.read()
3612	<< " / PADDR = " << paddr << std::endl;
3613	}
3614	#endif
3615
3616	break;
3617	}
3618	////////////////////////////
3619	case DCACHE_XTN_DC_INVAL_PA: // selective cache line invalidate with physical address
3620	// requires 2 cycles: read cache / inval cache
3621	// In this state we read dcache.
3622	{
3623	uint32_t data;
3624	size_t way;
3625	size_t set;
3626	size_t word;
3627	bool hit = r_dcache.read( r_dcache_p0_paddr.read(),
3628	&data,
3629	&way,
3630	&set,
3631	&word );
3632	#ifdef INSTRUMENTATION
3633	m_cpt_dcache_data_read++;
3634	m_cpt_dcache_dir_read++;
3635	#endif
3636	if ( hit ) // inval to be done
3637	{
3638	r_dcache_xtn_way = way;
3639	r_dcache_xtn_set = set;
3640	r_dcache_fsm = DCACHE_XTN_DC_INVAL_GO;
3641	}
3642	else // miss : nothing to do
3643	{
3644	r_dcache_fsm = DCACHE_IDLE;
3645	m_drsp.valid = true;
3646	}
3647
3648	#if DEBUG_DCACHE
3649	if ( m_debug_dcache_fsm )
3650	{
3651	std::cout << " <PROC " << name() << ".DCACHE_XTN_DC_INVAL_PA> Test hit in dcache" << std::hex
3652	<< " / PADDR = " << r_dcache_p0_paddr.read() << std::dec
3653	<< " / HIT = " << hit
3654	<< " / SET = " << set
3655	<< " / WAY = " << way << std::endl;
3656	}
3657	#endif
3658	break;
3659	}
3660	////////////////////////////
3661	case DCACHE_XTN_DC_INVAL_GO: // In this state, we invalidate the cache line
3662	// Blocked if previous cleanup not completed
3663	// Test if itlb or dtlb inval is required
3664	{
3665	if ( not r_dcache_cleanup_req.read() )
3666	{
3667	paddr_t nline;
3668	size_t way = r_dcache_xtn_way.read();
3669	size_t set = r_dcache_xtn_set.read();
3670	bool hit;
3671
3672	hit = r_dcache.inval( way,
3673	set,
3674	&nline );
3675	assert(hit && "XTN_DC_INVAL way/set should still be in cache");
3676
3677	// request cleanup
3678	r_dcache_cleanup_req = true;
3679	r_dcache_cleanup_line = nline;
3680
3681	// possible itlb & dtlb invalidate
3682	if ( r_dcache_in_tlb[way*m_dcache_sets+set] )
3683	{
3684	r_dcache_tlb_inval_line = nline;
3685	r_dcache_tlb_inval_count = 0;
3686	r_dcache_fsm_scan_save = DCACHE_XTN_DC_INVAL_END;
3687	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
3688	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
3689	}
3690	else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] )
3691	{
3692	r_itlb.reset();
3693	r_dtlb.reset();
3694	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
3695	r_dcache_fsm = DCACHE_IDLE;
3696	m_drsp.valid = true;
3697	}
3698	else
3699	{
3700	r_dcache_fsm = DCACHE_IDLE;
3701	m_drsp.valid = true;
3702	}
3703
3704	#if DEBUG_DCACHE
3705	if ( m_debug_dcache_fsm )
3706	{
3707	std::cout << " <PROC " << name() << ".DCACHE_XTN_DC_INVAL_GO> Actual dcache inval" << std::hex
3708	<< " / NLINE = " << nline << std::endl;
3709	}
3710	#endif
3711	}
3712	break;
3713	}
3714	//////////////////////////////
3715	case DCACHE_XTN_DC_INVAL_END: // send response to processor XTN request
3716	{
3717	r_dcache_fsm = DCACHE_IDLE;
3718	m_drsp.valid = true;
3719	break;
3720	}
3721	////////////////////////
3722	case DCACHE_MISS_VICTIM: // Selects a victim line if there is no pending cleanup
3723	// on the missing line, and if a new cleanup can be posted.
3724	// Set the r_dcache_cleanup_req flip-flop if required
3725	{
3726	size_t index; // unused
3727	bool hit = r_cleanup_buffer.hit( r_dcache_vci_paddr.read()>>(uint32_log2(m_dcache_words)+2), &index );
3728	if ( not hit and not r_dcache_cleanup_req.read() )
3729	{
3730	bool valid;
3731	size_t way;
3732	size_t set;
3733	paddr_t victim;
3734
3735	valid = r_dcache.victim_select( r_dcache_vci_paddr.read(),
3736	&victim,
3737	&way,
3738	&set );
3739	r_dcache_miss_way = way;
3740	r_dcache_miss_set = set;
3741
3742	if ( valid )
3743	{
3744	r_dcache_cleanup_req = true;
3745	r_dcache_cleanup_line = victim;
3746	r_dcache_fsm = DCACHE_MISS_INVAL;
3747	}
3748	else
3749	{
3750	r_dcache_fsm = DCACHE_MISS_WAIT;
3751	}
3752
3753	#if DEBUG_DCACHE
3754	if ( m_debug_dcache_fsm )
3755	{
3756	std::cout << " <PROC " << name() << ".DCACHE_MISS_VICTIM> Select a slot:" << std::dec
3757	<< " / WAY = " << way
3758	<< " / SET = " << set
3759	<< " / VALID = " << valid
3760	<< " / LINE = " << std::hex << victim << std::endl;
3761	}
3762	#endif
3763	}
3764	break;
3765	}
3766	///////////////////////
3767	case DCACHE_MISS_INVAL: // invalidate the victim line
3768	// and possibly request itlb or dtlb invalidate
3769	{
3770	paddr_t nline;
3771	size_t way = r_dcache_miss_way.read();
3772	size_t set = r_dcache_miss_set.read();
3773	bool hit;
3774
3775	hit = r_dcache.inval( way,
3776	set,
3777	&nline );
3778
3779	assert(hit && "selected way/set line should be in dcache");
3780
3781	#if DEBUG_DCACHE
3782	if ( m_debug_dcache_fsm )
3783	{
3784	std::cout << " <PROC " << name() << ".DCACHE_MISS_INVAL> inval line:" << std::dec
3785	<< " / way = " << way
3786	<< " / set = " << set
3787	<< " / nline = " << std::hex << nline << std::endl;
3788	}
3789	#endif
3790	// if selective itlb & dtlb invalidate are required
3791	// the miss response is not handled before invalidate completed
3792	if ( r_dcache_in_tlb[way*m_dcache_sets+set] )
3793	{
3794	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
3795	r_dcache_tlb_inval_line = nline;
3796	r_dcache_tlb_inval_count = 0;
3797	r_dcache_fsm_scan_save = DCACHE_MISS_WAIT;
3798	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
3799	}
3800	else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] )
3801	{
3802	r_itlb.reset();
3803	r_dtlb.reset();
3804	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
3805	r_dcache_fsm = DCACHE_MISS_WAIT;
3806	}
3807	else
3808	{
3809	r_dcache_fsm = DCACHE_MISS_WAIT;
3810	}
3811	break;
3812	}
3813	//////////////////////
3814	case DCACHE_MISS_WAIT: // waiting the response to a miss request from VCI_RSP FSM
3815	// This state is in charge of error signaling
3816	// There is 5 types of error depending on the requester
3817	{
3818	// external coherence request
3819	if ( r_tgt_dcache_req )
3820	{
3821	r_dcache_fsm_cc_save = r_dcache_fsm;
3822	r_dcache_fsm = DCACHE_CC_CHECK;
3823	break;
3824	}
3825
3826	if ( r_vci_rsp_data_error.read() ) // bus error
3827	{
3828	switch ( r_dcache_miss_type.read() )
3829	{
3830	case PROC_MISS:
3831	{
3832	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
3833	r_mmu_dbvar = r_dcache_p0_vaddr.read();
3834	m_drsp.valid = true;
3835	m_drsp.error = true;
3836	r_dcache_fsm = DCACHE_IDLE;
3837	break;
3838	}
3839	case PTE1_MISS:
3840	{
3841	if ( r_dcache_tlb_ins.read() )
3842	{
3843	r_mmu_ietr = MMU_READ_PT1_ILLEGAL_ACCESS;
3844	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3845	r_icache_tlb_miss_req = false;
3846	r_icache_tlb_rsp_error = true;
3847	}
3848	else
3849	{
3850	r_mmu_detr = MMU_READ_PT1_ILLEGAL_ACCESS;
3851	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3852	m_drsp.valid = true;
3853	m_drsp.error = true;
3854	}
3855	r_dcache_fsm = DCACHE_IDLE;
3856	break;
3857	}
3858	case PTE2_MISS:
3859	{
3860	if ( r_dcache_tlb_ins.read() )
3861	{
3862	r_mmu_ietr = MMU_READ_PT2_ILLEGAL_ACCESS;
3863	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3864	r_icache_tlb_miss_req = false;
3865	r_icache_tlb_rsp_error = true;
3866	}
3867	else
3868	{
3869	r_mmu_detr = MMU_READ_PT2_ILLEGAL_ACCESS;
3870	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3871	m_drsp.valid = true;
3872	m_drsp.error = true;
3873	}
3874	r_dcache_fsm = DCACHE_IDLE;
3875	break;
3876	}
3877	} // end switch type
3878	r_vci_rsp_data_error = false;
3879	}
3880	else if ( r_vci_rsp_fifo_dcache.rok() ) // valid response available
3881	{
3882	r_dcache_miss_word = 0;
3883	r_dcache_fsm = DCACHE_MISS_UPDT;
3884	}
3885	break;
3886	}
3887	//////////////////////
3888	case DCACHE_MISS_UPDT: // update the dcache (one word per cycle)
3889	// returns the response depending on the miss type
3890	{
3891	if ( r_vci_rsp_fifo_dcache.rok() ) // one word available
3892	{
3893	if ( r_dcache_miss_inval.read() ) // Matching coherence request
3894	// pop the FIFO, without cache update
3895	// send a cleanup for the missing line
3896	// if the previous cleanup is completed
3897	{
3898	if ( r_dcache_miss_word.read() < (m_dcache_words - 1) ) // not the last
3899	{
3900	vci_rsp_fifo_dcache_get = true;
3901	r_dcache_miss_word = r_dcache_miss_word.read() + 1;
3902	}
3903	else // last word
3904	{
3905	if ( not r_dcache_cleanup_req.read() ) // no pending cleanup
3906	{
3907	vci_rsp_fifo_dcache_get = true;
3908	r_dcache_cleanup_req = true;
3909	r_dcache_cleanup_line = r_dcache_vci_paddr.read() >>
3910	(uint32_log2(m_dcache_words)+2);
3911	r_dcache_miss_inval = false;
3912	r_dcache_fsm = DCACHE_IDLE;
3913	}
3914	}
3915	}
3916	else // No matching coherence request
3917	// pop the FIFO and update the cache
3918	// update the directory at the last word
3919	{
3920	size_t way = r_dcache_miss_way.read();
3921	size_t set = r_dcache_miss_set.read();
3922	size_t word = r_dcache_miss_word.read();
3923
3924	#ifdef INSTRUMENTATION
3925	m_cpt_dcache_data_write++;
3926	#endif
3927	r_dcache.write( way,
3928	set,
3929	word,
3930	r_vci_rsp_fifo_dcache.read());
3931
3932	vci_rsp_fifo_dcache_get = true;
3933	r_dcache_miss_word = r_dcache_miss_word.read() + 1;
3934
3935	// if last word, update directory, set in_tlb & contains_ptd bits
3936	if ( r_dcache_miss_word.read() == (m_dcache_words - 1) )
3937	{
3938
3939	#ifdef INSTRUMENTATION
3940	m_cpt_dcache_dir_write++;
3941	#endif
3942	r_dcache.victim_update_tag( r_dcache_vci_paddr.read(),
3943	r_dcache_miss_way.read(),
3944	r_dcache_miss_set.read() );
3945
3946	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
3947	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
3948
3949	if (r_dcache_miss_type.read()==PTE1_MISS) r_dcache_fsm = DCACHE_TLB_PTE1_GET;
3950	else if (r_dcache_miss_type.read()==PTE2_MISS) r_dcache_fsm = DCACHE_TLB_PTE2_GET;
3951	else r_dcache_fsm = DCACHE_IDLE;
3952	}
3953	}
3954
3955	#if DEBUG_DCACHE
3956	if ( m_debug_dcache_fsm )
3957	{
3958	if ( r_dcache_miss_inval.read() )
3959	{
3960	if ( r_dcache_miss_word.read() < m_dcache_words-1 )
3961	{
3962	std::cout << " <PROC " << name() << ".DCACHE_MISS_UPDT> Matching coherence request:"
3963	<< " pop the FIFO, don't update the cache" << std::endl;
3964	}
3965	else
3966	{
3967	std::cout << " <PROC " << name() << ".DCACHE_MISS_UPDT> Matching coherence request:"
3968	<< " last word : send a cleanup request " << std::endl;
3969	}
3970	}
3971	else
3972	{
3973	std::cout << " <PROC " << name() << ".DCACHE_MISS_UPDT> Write one word:"
3974	<< " address = " << std::hex << r_dcache_vci_paddr.read()
3975	<< " / data = " << r_vci_rsp_fifo_dcache.read()
3976	<< " / way = " << std::dec << r_dcache_miss_way.read()
3977	<< " / set = " << r_dcache_miss_set.read()
3978	<< " / word = " << r_dcache_miss_word.read() << std::endl;
3979	}
3980	}
3981	#endif
3982
3983	} // end if rok
3984	break;
3985	}
3986	/////////////////////
3987	case DCACHE_UNC_WAIT:
3988	{
3989	// external coherence request
3990	if ( r_tgt_dcache_req.read() )
3991	{
3992	r_dcache_fsm_cc_save = r_dcache_fsm;
3993	r_dcache_fsm = DCACHE_CC_CHECK;
3994	break;
3995	}
3996
3997	if ( r_vci_rsp_data_error.read() ) // bus error
3998	{
3999	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
4000	r_mmu_dbvar = m_dreq.addr;
4001	r_vci_rsp_data_error = false;
4002	m_drsp.error = true;
4003	m_drsp.valid = true;
4004	r_dcache_fsm = DCACHE_IDLE;
4005	break;
4006	}
4007	else if ( r_vci_rsp_fifo_dcache.rok() ) // data available
4008	{
4009	// consume data
4010	vci_rsp_fifo_dcache_get = true;
4011	r_dcache_fsm = DCACHE_IDLE;
4012
4013	// acknowledge the processor request if it has not been modified
4014	if ( m_dreq.valid and (m_dreq.addr == r_dcache_p0_vaddr.read()) )
4015	{
4016	m_drsp.valid = true;
4017	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
4018	}
4019	}
4020	break;
4021	}
4022	/////////////////////
4023	case DCACHE_LL_WAIT:
4024	{
4025	// external coherence request
4026	if ( r_tgt_dcache_req.read() )
4027	{
4028	r_dcache_fsm_cc_save = r_dcache_fsm;
4029	r_dcache_fsm = DCACHE_CC_CHECK;
4030	break;
4031	}
4032
4033	if ( r_vci_rsp_data_error.read() ) // bus error
4034	{
4035	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
4036	r_mmu_dbvar = m_dreq.addr;
4037	r_vci_rsp_data_error = false;
4038	m_drsp.error = true;
4039	m_drsp.valid = true;
4040	r_dcache_fsm = DCACHE_IDLE;
4041	break;
4042	}
4043	else if ( r_vci_rsp_fifo_dcache.rok() ) // data available
4044	{
4045	// consume data
4046	vci_rsp_fifo_dcache_get = true;
4047	if(r_dcache_ll_rsp_count.read() == 0) //first flit
4048	{
4049	//access table
4050	table_in.cmd = LLSCLocalTable::LL_RSP ;
4051	table_in.index = 0;//p_vci_ini_d.rtrdid.read() ; // TODO use this ?
4052	table_in.key = r_vci_rsp_fifo_dcache.read();
4053	r_llsc_table.exec(table_in, table_out);
4054	llsc_local_table_access_done = true;
4055	r_dcache_ll_rsp_count = r_dcache_ll_rsp_count.read() + 1 ;
4056	}
4057	else //last flit
4058	{
4059	// acknowledge the processor request if it has not been modified
4060	if ( m_dreq.valid and (m_dreq.addr == r_dcache_p0_vaddr.read()) )
4061	{
4062	m_drsp.valid = true;
4063	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
4064	}
4065	r_dcache_fsm = DCACHE_IDLE;
4066	}
4067	}
4068	break;
4069	}
4070	////////////////////
4071	case DCACHE_SC_WAIT: // waiting VCI response after a processor SC request
4072	{
4073	// external coherence request
4074	if ( r_tgt_dcache_req.read() )
4075	{
4076	r_dcache_fsm_cc_save = r_dcache_fsm;
4077	r_dcache_fsm = DCACHE_CC_CHECK;
4078	break;
4079	}
4080
4081	if ( r_vci_rsp_data_error.read() ) // bus error
4082	{
4083	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
4084	r_mmu_dbvar = m_dreq.addr;
4085	r_vci_rsp_data_error = false;
4086	m_drsp.error = true;
4087	m_drsp.valid = true;
4088	r_dcache_fsm = DCACHE_IDLE;
4089	break;
4090	}
4091	else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
4092	{
4093	// consume response
4094	vci_rsp_fifo_dcache_get = true;
4095	m_drsp.valid = true;
4096	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
4097	r_dcache_fsm = DCACHE_IDLE;
4098	}
4099	break;
4100	}
4101	//////////////////////////
4102	case DCACHE_DIRTY_GET_PTE: // This sub_fsm set the PTE Dirty bit in memory
4103	// before handling a processor WRITE or SC request
4104	// Input argument is r_dcache_dirty_paddr
4105	// In this first state, we get PTE value in dcache
4106	// and post a SC request to CMD FSM
4107	{
4108	// get PTE in dcache
4109	uint32_t pte;
4110	size_t way;
4111	size_t set;
4112	size_t word; // unused
4113	bool hit = r_dcache.read( r_dcache_dirty_paddr.read(),
4114	&pte,
4115	&way,
4116	&set,
4117	&word );
4118	#ifdef INSTRUMENTATION
4119	m_cpt_dcache_data_read++;
4120	m_cpt_dcache_dir_read++;
4121	#endif
4122	assert( hit and "error in DCACHE_DIRTY_TLB_SET: the PTE should be in dcache" );
4123
4124	// request CAS transaction to CMD_FSM
4125	r_dcache_dirty_way = way;
4126	r_dcache_dirty_set = set;
4127	// prepare llsc local table access
4128	table_in.cmd = LLSCLocalTable::SW_CMD;
4129	table_in.address = r_dcache_dirty_paddr.read();
4130	// access the table
4131	r_llsc_table.exec(table_in, table_out);
4132	llsc_local_table_access_done = true;
4133	// test if the table is done
4134	if(!table_out.done)
4135	break;
4136	// request a CAS CMD and go to DCACHE_DIRTY_WAIT state
4137	r_dcache_vci_cas_req = true;
4138	r_dcache_vci_paddr = r_dcache_dirty_paddr.read();
4139	r_dcache_vci_cas_old = pte;
4140	r_dcache_vci_cas_new = pte \| PTE_D_MASK;
4141	r_dcache_fsm = DCACHE_DIRTY_WAIT;
4142
4143	#if DEBUG_DCACHE
4144	if ( m_debug_dcache_fsm )
4145	{
4146	std::cout << " <PROC " << name() << ".DCACHE_DIRTY_GET_PTE> Get PTE in dcache" << std::hex
4147	<< " / PTE_PADDR = " << r_dcache_dirty_paddr.read()
4148	<< " / PTE_VALUE = " << pte << std::dec
4149	<< " / CACHE_SET = " << set
4150	<< " / CACHE_WAY = " << way << std::endl;
4151	}
4152	#endif
4153	break;
4154	}
4155	//////////////////////////
4156	case DCACHE_DIRTY_WAIT: // wait completion of CAS for PTE Dirty bit,
4157	// and return to IDLE state when response is received.
4158	// we don't care if the CAS is a failure:
4159	// - if the CAS is a success, the coherence mechanism
4160	// updates the local copy.
4161	// - if the CAS is a failure, we just retry the write.
4162	{
4163	// external coherence request
4164	if ( r_tgt_dcache_req )
4165	{
4166	r_dcache_fsm_cc_save = r_dcache_fsm;
4167	r_dcache_fsm = DCACHE_CC_CHECK;
4168	break;
4169	}
4170
4171	if ( r_vci_rsp_data_error.read() ) // bus error
4172	{
4173	std::cout << "BUS ERROR in DCACHE_DIRTY_WAIT state" << std::endl;
4174	std::cout << "This should not happen in this state" << std::endl;
4175	exit(0);
4176	}
4177	else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
4178	{
4179	vci_rsp_fifo_dcache_get = true;
4180	r_dcache_fsm = DCACHE_IDLE;
4181
4182	#if DEBUG_DCACHE
4183	if ( m_debug_dcache_fsm )
4184	{
4185	std::cout << " <PROC " << name() << ".DCACHE_DIRTY_WAIT> SC completed" << std::endl;
4186	}
4187	#endif
4188	}
4189	break;
4190	}
4191	/////////////////////
4192	case DCACHE_CC_CHECK: // This state is the entry point for the sub-FSM
4193	// handling coherence requests.
4194	// If there is a matching pending miss on the modified cache
4195	// line this is signaled in the r_dcache_miss inval flip-flop.
4196	// If the updated (or invalidated) cache line has copies in TLBs
4197	// these TLB copies are invalidated.
4198	// The return state is defined in r_dcache_fsm_cc_save
4199	{
4200	paddr_t paddr = r_tgt_paddr.read();
4201	paddr_t mask = ~((m_dcache_words<<2)-1);
4202
4203
4204	if( (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) and
4205	((r_dcache_vci_paddr.read() & mask) == (paddr & mask)) ) // matching pending miss
4206	{
4207	r_dcache_miss_inval = true; // signaling the match
4208	r_tgt_dcache_req = false; // coherence request completed
4209	r_tgt_dcache_rsp = r_tgt_update.read(); // response required if update
4210	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4211
4212	#if DEBUG_DCACHE
4213	if ( m_debug_dcache_fsm )
4214	{
4215	std::cout << " <PROC " << name() << ".DCACHE_CC_CHECK> Coherence request matching a pending miss:"
4216	<< " address = " << std::hex << paddr << std::endl;
4217	}
4218	#endif
4219
4220	}
4221	else // no match for a pending miss
4222	{
4223	uint32_t rdata;
4224	size_t way;
4225	size_t set;
4226	size_t word;
4227
4228	bool hit = r_dcache.read( paddr,
4229	&rdata, // unused
4230	&way,
4231	&set,
4232	&word); // unused
4233	#ifdef INSTRUMENTATION
4234	m_cpt_dcache_data_read++;
4235	m_cpt_dcache_dir_read++;
4236	#endif
4237	r_dcache_cc_way = way;
4238	r_dcache_cc_set = set;
4239
4240	if ( hit and r_tgt_update.read() ) // hit update
4241	{
4242	r_dcache_fsm = DCACHE_CC_UPDT;
4243	r_dcache_cc_word = r_tgt_word_min.read();
4244	}
4245	else if ( hit and not r_tgt_update.read() ) // hit inval
4246	{
4247	r_dcache_fsm = DCACHE_CC_INVAL;
4248	}
4249	else // miss can happen
4250	{
4251	r_tgt_dcache_req = false;
4252	r_tgt_dcache_rsp = r_tgt_update.read();
4253	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4254	}
4255
4256	#if DEBUG_DCACHE
4257	if ( m_debug_dcache_fsm )
4258	{
4259
4260	std::cout << " <PROC " << name() << ".DCACHE_CC_CHECK> Coherence request received :"
4261	<< " address = " << std::hex << paddr << std::dec;
4262	if ( hit )
4263	{
4264	std::cout << " / HIT" << " / way = " << way << " / set = " << set << std::endl;
4265	}
4266	else
4267	{
4268	std::cout << " / MISS" << std::endl;
4269	}
4270	}
4271	#endif
4272
4273	}
4274	break;
4275	}
4276	/////////////////////
4277	case DCACHE_CC_INVAL: // invalidate one cache line after
4278	// invalidation of copies in TLBs
4279	{
4280	paddr_t nline;
4281	size_t way = r_dcache_cc_way.read();
4282	size_t set = r_dcache_cc_set.read();
4283	bool hit;
4284
4285	if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // selective TLB inval
4286	{
4287	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
4288	r_dcache_tlb_inval_line = r_tgt_paddr.read() >> (uint32_log2(m_dcache_words)+2);
4289	r_dcache_tlb_inval_count = 0;
4290	r_dcache_fsm_scan_save = r_dcache_fsm.read();
4291	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4292	}
4293	else // actual cache line inval
4294	{
4295	if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // TLB flush
4296	{
4297	r_itlb.reset();
4298	r_dtlb.reset();
4299	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
4300	}
4301	r_tgt_dcache_rsp = true;
4302	r_tgt_dcache_req = false;
4303	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4304
4305	hit = r_dcache.inval( way,
4306	set,
4307	&nline );
4308	#if DEBUG_DCACHE
4309	if ( m_debug_dcache_fsm )
4310	{
4311	std::cout << " <PROC " << name() << ".DCACHE_CC_INVAL> Invalidate cache line" << std::dec
4312	<< " / WAY = " << way
4313	<< " / SET = " << set << std::endl;
4314	}
4315	#endif
4316
4317	assert(hit && "CC_INVAL way/set should be in dcache");
4318	}
4319	break;
4320	}
4321	///////////////////
4322	case DCACHE_CC_UPDT: // write one word per cycle (from word_min to word_max)
4323	// and test possible copies in TLBs
4324	{
4325	size_t word = r_dcache_cc_word.read();
4326	size_t way = r_dcache_cc_way.read();
4327	size_t set = r_dcache_cc_set.read();
4328	paddr_t nline = r_tgt_paddr.read() >> (uint32_log2(m_dcache_words)+2);
4329
4330	if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // selective TLB inval
4331	{
4332	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
4333	r_dcache_tlb_inval_line = nline;
4334	r_dcache_tlb_inval_count = 0;
4335	r_dcache_fsm_scan_save = r_dcache_fsm.read();
4336	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4337	}
4338	else // cache update
4339	{
4340	if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // TLB flush
4341	{
4342	r_itlb.reset();
4343	r_dtlb.reset();
4344	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
4345	}
4346
4347	r_dcache.write( way,
4348	set,
4349	word,
4350	r_tgt_buf[word],
4351	r_tgt_be[word] );
4352	#ifdef INSTRUMENTATION
4353	m_cpt_dcache_data_write++;
4354	#endif
4355	r_dcache_cc_word = word + 1;
4356
4357	#if DEBUG_DCACHE
4358	if ( m_debug_dcache_fsm )
4359	{
4360	std::cout << " <PROC " << name() << ".DCACHE_CC_UPDT> Update one word" << std::dec
4361	<< " / WAY = " << way
4362	<< " / SET = " << set
4363	<< " / WORD = " << word
4364	<< " / VALUE = " << std::hex << r_tgt_buf[word] << std::endl;
4365	}
4366	#endif
4367	if ( word == r_tgt_word_max.read() ) // last word
4368	{
4369	r_tgt_dcache_rsp = true;
4370	r_tgt_dcache_req = false;
4371	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4372	}
4373	}
4374
4375	break;
4376	}
4377	///////////////////////////
4378	case DCACHE_INVAL_TLB_SCAN: // Scan sequencially all TLB entries for both ITLB & DTLB
4379	// It makes the assumption that (m_itlb_sets == m_dtlb_sets)
4380	// and (m_itlb_ways == m_dtlb_ways)
4381	// We enter this state when a DCACHE line is modified,
4382	// and there is a copy in itlb or dtlb.
4383	// It can be caused by:
4384	// - a coherence inval or updt transaction,
4385	// - a line inval caused by a cache miss
4386	// - a processor XTN inval request,
4387	// - a WRITE hit,
4388	// - a Dirty bit update failure
4389	// Input arguments are:
4390	// - r_dcache_tlb_inval_line
4391	// - r_dcache_tlb_inval_count
4392	// - r_dcache_fsm_cc_save
4393	{
4394	paddr_t line = r_dcache_tlb_inval_line.read(); // nline
4395	size_t way = r_dcache_tlb_inval_count.read()/m_itlb_sets; // way
4396	size_t set = r_dcache_tlb_inval_count.read()%m_itlb_sets; // set
4397	bool ok;
4398
4399	ok = r_itlb.inval( line,
4400	way,
4401	set );
4402	#if DEBUG_DCACHE
4403	if ( m_debug_dcache_fsm and ok )
4404	{
4405	std::cout << " <PROC " << name() << ".DCACHE_INVAL_TLB_SCAN> Invalidate ITLB entry:" << std::hex
4406	<< " line = " << line << std::dec
4407	<< " / set = " << set
4408	<< " / way = " << way << std::endl;
4409	r_itlb.printTrace();
4410	}
4411	#endif
4412	ok = r_dtlb.inval( line,
4413	way,
4414	set );
4415	#if DEBUG_DCACHE
4416	if ( m_debug_dcache_fsm and ok )
4417	{
4418	std::cout << " <PROC " << name() << ".DCACHE_INVAL_TLB_SCAN> Invalidate DTLB entry:" << std::hex
4419	<< " line = " << line << std::dec
4420	<< " / set = " << set
4421	<< " / way = " << way << std::endl;
4422	r_dtlb.printTrace();
4423	}
4424	#endif
4425
4426	// return to the calling state when TLB inval completed
4427	if ( r_dcache_tlb_inval_count.read() == ((m_dtlb_sets*m_dtlb_ways)-1) )
4428	{
4429	r_dcache_fsm = r_dcache_fsm_scan_save.read();
4430	}
4431	r_dcache_tlb_inval_count = r_dcache_tlb_inval_count.read() + 1;
4432	break;
4433	}
4434	} // end switch r_dcache_fsm
4435	// perform a NOP access the the local llsc table if necessary
4436	if(llsc_local_table_access_done == false)
4437	{
4438	table_in.cmd = LLSCLocalTable::NOP;
4439	r_llsc_table.exec(table_in, table_out);
4440	}
4441
4442	///////////////// wbuf update //////////////////////////////////////////////////////
4443	r_wbuf.update();
4444
4445	//////////////// test processor frozen /////////////////////////////////////////////
4446	// The simulation exit if the number of consecutive frozen cycles
4447	// is larger than the m_max_frozen_cycles (constructor parameter)
4448	if ( (m_ireq.valid and not m_irsp.valid) or (m_dreq.valid and not m_drsp.valid) )
4449	{
4450	m_cpt_frz_cycles++; // used for instrumentation
4451	m_cpt_stop_simulation++; // used for debug
4452	if ( m_cpt_stop_simulation > m_max_frozen_cycles )
4453	{
4454	std::cout << std::dec << "ERROR in CC_VCACHE_WRAPPER " << name() << std::endl
4455	<< " stop at cycle " << m_cpt_total_cycles << std::endl
4456	<< " frozen since cycle " << m_cpt_total_cycles - m_max_frozen_cycles << std::endl;
4457	r_iss.dump();
4458	exit(1);
4459	}
4460	}
4461	else
4462	{
4463	m_cpt_stop_simulation = 0;
4464	}
4465
4466	/////////// execute one iss cycle /////////////////////////////////
4467	{
4468	uint32_t it = 0;
4469	for (size_t i=0; i<(size_t)iss_t::n_irq; i++) if(p_irq[i].read()) it \|= (1<<i);
4470	r_iss.executeNCycles(1, m_irsp, m_drsp, it);
4471	}
4472
4473	////////////////////////////////////////////////////////////////////////////
4474	// The VCI_CMD FSM controls the following ressources:
4475	// - r_vci_cmd_fsm
4476	// - r_vci_cmd_min
4477	// - r_vci_cmd_max
4478	// - r_vci_cmd_cpt
4479	// - r_vci_cmd_imiss_prio
4480	// - wbuf (reset)
4481	// - r_icache_miss_req (reset)
4482	// - r_icache_unc_req (reset)
4483	// - r_dcache_vci_miss_req (reset)
4484	// - r_dcache_vci_unc_req (reset)
4485	// - r_dcache_vci_ll_req (reset)
4486	// - r_dcache_vci_sc_req (reset in case of local sc fail)
4487	// - r_dcache_vci_cas_req (reset)
4488	//
4489	// This FSM handles requests from both the DCACHE FSM & the ICACHE FSM.
4490	// There are 8 request types, with the following priorities :
4491	// 1 - Data Read Miss : r_dcache_vci_miss_req and miss in the write buffer
4492	// 2 - Data Read Uncachable : r_dcache_vci_unc_req
4493	// 3 - Instruction Miss : r_icache_miss_req and miss in the write buffer
4494	// 4 - Instruction Uncachable : r_icache_unc_req
4495	// 5 - Data Write : r_wbuf.rok()
4496	// 6 - Data Linked Load : r_dcache_vci_ll_req
4497	// 7 - Data Store Conditionnal: r_dcache_vci_sc_req
4498	// 8 - Compare And Swap : r_dcache_vci_cas_req
4499	//
4500	// As we want to support several simultaneous VCI transactions, the VCI_CMD_FSM
4501	// and the VCI_RSP_FSM are fully desynchronized.
4502	//
4503	// VCI formats:
4504	// According to the VCI advanced specification, all read requests packets
4505	// (data Uncached, Miss data, instruction Uncached, Miss instruction)
4506	// are one word packets.
4507	// For write burst packets, all words are in the same cache line,
4508	// and addresses must be contiguous (the BE field is 0 in case of "holes").
4509	// The sc command packet implements actually a compare-and-swap mechanism
4510	// and the packet contains two flits.
4511	////////////////////////////////////////////////////////////////////////////////////
4512
4513	switch ( r_vci_cmd_fsm.read() )
4514	{
4515	//////////////
4516	case CMD_IDLE:
4517	{
4518	// r_dcache_vci_miss_req and r_icache_miss_req require both a write_buffer access
4519	// to check a possible pending write on the same cache line.
4520	// As there is only one possible access per cycle to write buffer, we implement
4521	// a round-robin priority for this access, using the r_vci_cmd_imiss_prio flip-flop.
4522
4523	size_t wbuf_min;
4524	size_t wbuf_max;
4525
4526	bool dcache_miss_req = r_dcache_vci_miss_req.read()
4527	and ( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() );
4528
4529	bool icache_miss_req = r_icache_miss_req.read()
4530	and ( not r_dcache_vci_miss_req.read() or r_vci_cmd_imiss_prio.read() );
4531
4532	// 1 - Data Read Miss
4533	if ( dcache_miss_req and r_wbuf.miss(r_dcache_vci_paddr.read()) )
4534	{
4535	r_vci_cmd_fsm = CMD_DATA_MISS;
4536	r_dcache_vci_miss_req = false;
4537	r_vci_cmd_imiss_prio = true;
4538	// m_cpt_dmiss_transaction++;
4539	}
4540	// 2 - Data Read Uncachable
4541	else if ( r_dcache_vci_unc_req.read() )
4542	{
4543	r_vci_cmd_fsm = CMD_DATA_UNC;
4544	r_dcache_vci_unc_req = false;
4545	// m_cpt_dunc_transaction++;
4546	}
4547	// 3 - Instruction Miss
4548	else if ( icache_miss_req and r_wbuf.miss(r_icache_vci_paddr.read()) )
4549	{
4550	r_vci_cmd_fsm = CMD_INS_MISS;
4551	r_icache_miss_req = false;
4552	r_vci_cmd_imiss_prio = false;
4553	// m_cpt_imiss_transaction++;
4554	}
4555	// 4 - Instruction Uncachable
4556	else if ( r_icache_unc_req.read() )
4557	{
4558	r_vci_cmd_fsm = CMD_INS_UNC;
4559	r_icache_unc_req = false;
4560	// m_cpt_iunc_transaction++;
4561	}
4562	// 5 - Data Write
4563	else if ( r_wbuf.rok(&wbuf_min, &wbuf_max) )
4564	{
4565	r_vci_cmd_fsm = CMD_DATA_WRITE;
4566	r_vci_cmd_cpt = wbuf_min;
4567	r_vci_cmd_min = wbuf_min;
4568	r_vci_cmd_max = wbuf_max;
4569	// m_cpt_write_transaction++;
4570	// m_length_write_transaction += (wbuf_max-wbuf_min+1);
4571	}
4572	// 6 - Data Linked Load
4573	// must check that all write transaction are completed
4574	else if ( r_dcache_vci_ll_req.read() && r_wbuf.miss(r_dcache_vci_paddr.read()))
4575	{
4576	r_dcache_vci_ll_req = false;
4577	r_vci_cmd_fsm = CMD_DATA_LL;
4578	// r_vci_cmd_cpt = 0;
4579	// m_cpt_sc_transaction++;
4580	}
4581	// 7 - Data Store Conditionnal
4582	// should check that all write transaction are completed ?
4583	else if ( r_dcache_vci_sc_req.read() )
4584	{
4585	r_dcache_vci_sc_req = false;
4586	r_vci_cmd_cpt = 0;
4587	r_vci_cmd_fsm = CMD_DATA_SC;
4588	// m_cpt_sc_transaction++;
4589	}
4590	// 8 - Compare And Swap
4591	// should check that all write transaction are completed ?
4592	else if ( r_dcache_vci_cas_req.read() )
4593	{
4594	r_vci_cmd_fsm = CMD_DATA_CAS;
4595	r_dcache_vci_cas_req = false;
4596	r_vci_cmd_cpt = 0;
4597	// m_cpt_sc_transaction++;
4598	}
4599	break;
4600	}
4601	////////////////////
4602	case CMD_DATA_WRITE:
4603	{
4604	if ( p_vci_ini_d.cmdack.read() )
4605	{
4606	// m_conso_wbuf_read++;
4607	r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
4608	if (r_vci_cmd_cpt == r_vci_cmd_max) // last flit sent
4609	{
4610	r_vci_cmd_fsm = CMD_IDLE ;
4611	r_wbuf.sent() ;
4612	}
4613	}
4614	break;
4615	}
4616	/////////////////
4617	case CMD_DATA_SC:
4618	case CMD_DATA_CAS:
4619	{
4620	// The CAS and SC VCI commands contain two flits
4621	if ( p_vci_ini_d.cmdack.read() )
4622	{
4623	r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
4624	if (r_vci_cmd_cpt == 1) r_vci_cmd_fsm = CMD_IDLE ;
4625	}
4626	break;
4627	}
4628	//////////////////
4629	case CMD_INS_MISS:
4630	case CMD_INS_UNC:
4631	case CMD_DATA_MISS:
4632	case CMD_DATA_UNC:
4633	case CMD_DATA_LL:
4634	{
4635	// all read VCI commands contain one single flit
4636	if ( p_vci_ini_d.cmdack.read() ) r_vci_cmd_fsm = CMD_IDLE;
4637	break;
4638	}
4639
4640	} // end switch r_vci_cmd_fsm
4641
4642	//////////////////////////////////////////////////////////////////////////
4643	// The VCI_RSP FSM controls the following ressources:
4644	// - r_vci_rsp_fsm:
4645	// - r_vci_rsp_fifo_icache (push)
4646	// - r_vci_rsp_fifo_dcache (push)
4647	// - r_vci_rsp_data_error (set)
4648	// - r_vci_rsp_ins_error (set)
4649	// - r_vci_rsp_cpt
4650	// - r_dcache_vci_sc_req (reset when SC response recieved)
4651	//
4652	// As the VCI_RSP and VCI_CMD are fully desynchronized to support several
4653	// simultaneous VCI transactions, this FSM uses the VCI RPKTID field
4654	// to identify the transactions.
4655	//
4656	// VCI vormat:
4657	// This component checks the response packet length and accepts only
4658	// single word packets for write response packets.
4659	//
4660	// Error handling:
4661	// This FSM analyzes the VCI error code and signals directly the Write Bus Error.
4662	// In case of Read Data Error, the VCI_RSP FSM sets the r_vci_rsp_data_error
4663	// flip_flop and the error is signaled by the DCACHE FSM.
4664	// In case of Instruction Error, the VCI_RSP FSM sets the r_vci_rsp_ins_error
4665	// flip_flop and the error is signaled by the ICACHE FSM.
4666	// In case of Cleanup Error, the simulation stops with an error message...
4667	//////////////////////////////////////////////////////////////////////////
4668
4669	switch ( r_vci_rsp_fsm.read() )
4670	{
4671	//////////////
4672	case RSP_IDLE:
4673	{
4674	if ( p_vci_ini_d.rspval.read() )
4675	{
4676	r_vci_rsp_cpt = 0;
4677
4678	if ( (p_vci_ini_d.rpktid.read() & 0x7) == TYPE_READ_DATA_UNC )
4679	{
4680	r_vci_rsp_fsm = RSP_DATA_UNC;
4681	}
4682	else if ( (p_vci_ini_d.rpktid.read() & 0x7) == TYPE_READ_DATA_MISS )
4683	{
4684	r_vci_rsp_fsm = RSP_DATA_MISS;
4685	}
4686	else if ( (p_vci_ini_d.rpktid.read() & 0x7) == TYPE_READ_INS_UNC )
4687	{
4688	r_vci_rsp_fsm = RSP_INS_UNC;
4689	}
4690	else if ( (p_vci_ini_d.rpktid.read() & 0x7) == TYPE_READ_INS_MISS )
4691	{
4692	r_vci_rsp_fsm = RSP_INS_MISS;
4693	}
4694	else if ( (p_vci_ini_d.rpktid.read() & 0x7) == TYPE_WRITE )
4695	{
4696	r_vci_rsp_fsm = RSP_DATA_WRITE;
4697	}
4698	else if ( (p_vci_ini_d.rpktid.read() & 0x7) == TYPE_CAS )
4699	{
4700	r_vci_rsp_fsm = RSP_DATA_UNC;
4701	}
4702	else if ( (p_vci_ini_d.rpktid.read() & 0x7) == TYPE_LL )
4703	{
4704	r_vci_rsp_fsm = RSP_DATA_LL;
4705	}
4706	else if ( (p_vci_ini_d.rpktid.read() & 0x7) == TYPE_SC )
4707	{
4708	r_vci_rsp_fsm = RSP_DATA_UNC;
4709	}
4710	else
4711	{
4712	assert(false and "Unexpected VCI response");
4713	}
4714	}
4715	break;
4716	}
4717	//////////////////
4718	case RSP_INS_MISS:
4719	{
4720	if ( p_vci_ini_d.rspval.read() )
4721	{
4722	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported
4723	{
4724	r_vci_rsp_ins_error = true;
4725	if ( p_vci_ini_d.reop.read() ) r_vci_rsp_fsm = RSP_IDLE;
4726	}
4727	else // no error reported
4728	{
4729	if ( r_vci_rsp_fifo_icache.wok() )
4730	{
4731	assert( (r_vci_rsp_cpt.read() < m_icache_words) and
4732	"The VCI response packet for instruction miss is too long" );
4733
4734	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
4735	vci_rsp_fifo_icache_put = true,
4736	vci_rsp_fifo_icache_data = p_vci_ini_d.rdata.read();
4737	if ( p_vci_ini_d.reop.read() )
4738	{
4739	assert( (r_vci_rsp_cpt.read() == m_icache_words - 1) and
4740	"The VCI response packet for instruction miss is too short");
4741
4742	r_vci_rsp_fsm = RSP_IDLE;
4743	}
4744	}
4745	}
4746	}
4747	break;
4748	}
4749	/////////////////
4750	case RSP_INS_UNC:
4751	{
4752	if (p_vci_ini_d.rspval.read() )
4753	{
4754	assert( p_vci_ini_d.reop.read() and
4755	"illegal VCI response packet for uncachable instruction");
4756
4757	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported
4758	{
4759	r_vci_rsp_ins_error = true;
4760	r_vci_rsp_fsm = RSP_IDLE;
4761	}
4762	else // no error reported
4763	{
4764	if ( r_vci_rsp_fifo_icache.wok())
4765	{
4766	vci_rsp_fifo_icache_put = true;
4767	vci_rsp_fifo_icache_data = p_vci_ini_d.rdata.read();
4768	r_vci_rsp_fsm = RSP_IDLE;
4769	}
4770	}
4771	}
4772	break;
4773	}
4774	///////////////////
4775	case RSP_DATA_MISS:
4776	{
4777	if ( p_vci_ini_d.rspval.read() )
4778	{
4779	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported
4780	{
4781	r_vci_rsp_data_error = true;
4782	if ( p_vci_ini_d.reop.read() ) r_vci_rsp_fsm = RSP_IDLE;
4783	}
4784	else // no error reported
4785	{
4786	if ( r_vci_rsp_fifo_dcache.wok() )
4787	{
4788	assert( (r_vci_rsp_cpt.read() < m_dcache_words) and
4789	"The VCI response packet for data miss is too long");
4790
4791	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
4792	vci_rsp_fifo_dcache_put = true,
4793	vci_rsp_fifo_dcache_data = p_vci_ini_d.rdata.read();
4794	if ( p_vci_ini_d.reop.read() )
4795	{
4796	assert( (r_vci_rsp_cpt.read() == m_dcache_words - 1) and
4797	"The VCI response packet for data miss is too short");
4798
4799	r_vci_rsp_fsm = RSP_IDLE;
4800	}
4801	}
4802	}
4803	}
4804	break;
4805	}
4806	//////////////////
4807	case RSP_DATA_UNC:
4808	{
4809	if (p_vci_ini_d.rspval.read() )
4810	{
4811	assert( p_vci_ini_d.reop.read() and
4812	"illegal VCI response packet for uncachable read data");
4813
4814	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported
4815	{
4816	r_vci_rsp_data_error = true;
4817	r_vci_rsp_fsm = RSP_IDLE;
4818	}
4819	else // no error reported
4820	{
4821	if ( r_vci_rsp_fifo_dcache.wok())
4822	{
4823	vci_rsp_fifo_dcache_put = true;
4824	vci_rsp_fifo_dcache_data = p_vci_ini_d.rdata.read();
4825	r_vci_rsp_fsm = RSP_IDLE;
4826	}
4827	}
4828	}
4829	break;
4830	}
4831	////////////////////
4832	case RSP_DATA_LL:
4833	{
4834	if ( p_vci_ini_d.rspval.read() )
4835	{
4836	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported
4837	{
4838	r_vci_rsp_data_error = true;
4839	r_vci_rsp_fsm = RSP_IDLE;
4840	}
4841	if (r_vci_rsp_cpt.read() == 0) //first flit
4842	{
4843	if(r_vci_rsp_fifo_dcache.wok())
4844	{
4845	assert(!p_vci_ini_d.reop.read() &&
4846	"illegal VCI response packet for LL");
4847	vci_rsp_fifo_dcache_put = true;
4848	vci_rsp_fifo_dcache_data = p_vci_ini_d.rdata.read();
4849	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
4850	}
4851	break;
4852	}
4853	else // last flit
4854	{
4855	if(r_vci_rsp_fifo_dcache.wok())
4856	{
4857	assert(p_vci_ini_d.reop.read() &&
4858	"illegal VCI response packet for LL");
4859	vci_rsp_fifo_dcache_put = true;
4860	vci_rsp_fifo_dcache_data = p_vci_ini_d.rdata.read();
4861	r_vci_rsp_fsm = RSP_IDLE;
4862	}
4863	break;
4864	}
4865	}
4866	break;
4867	}
4868	////////////////////
4869	case RSP_DATA_WRITE:
4870	{
4871	if (p_vci_ini_d.rspval.read())
4872	{
4873	assert( p_vci_ini_d.reop.read() and
4874	"a VCI response packet must contain one flit for a write transaction");
4875
4876	r_vci_rsp_fsm = RSP_IDLE;
4877	uint32_t wbuf_index = p_vci_ini_d.rtrdid.read();
4878	bool cacheable = r_wbuf.completed(wbuf_index);
4879	if ( not cacheable ) r_dcache_pending_unc_write = false;
4880	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) r_iss.setWriteBerr();
4881	}
4882	break;
4883	}
4884	} // end switch r_vci_rsp_fsm
4885
4886	/////////////////////////////////////////////////////////////////////////////////////
4887	// The CLEANUP FSM is in charge to send the cleanup commands on the coherence
4888	// network. It has two clients (DCACHE FSM and ICACHE FSM) that are served
4889	// with a round-robin priority. All cleanup commands are registered in the
4890	// r_cleanup_buffer, because we must avoid to send a Read Miss command
4891	// for line (X) if there is a pending cleanup for line (X): the r_cleanup_buffer
4892	// is tested by the ICACHE FSM and DCACHE FSM before posting a miss request.
4893	// The CLEANUP FSM resets the r_*cache_cleanup request flip-flops as soon as
4894	// the request has been sent and registered in the buffer.
4895	// The buffer itself is cleared when the cleanup response is received.
4896	// We use an assocative registration buffer (CAM) in order to support several
4897	// simultaneous cleanup transactions (up to 4 simultaneous clenups).
4898	// The VCI TRDID field is used to distinguish data/instruction cleanups:
4899	// - if data cleanup : TRDID = 2*index + 0
4900	// - if instruction cleanup : TRDID = 2*index + 1
4901	/////////////////////////////////////////////////////////////////////////////////////
4902
4903	switch ( r_cleanup_fsm.read() )
4904	{
4905	///////////////////////
4906	case CLEANUP_DATA_IDLE: // dcache has highest priority
4907	{
4908	size_t index = 0;
4909	bool ok;
4910	if ( r_dcache_cleanup_req.read() ) // dcache request
4911	{
4912	ok = r_cleanup_buffer.write( r_dcache_cleanup_line.read(),
4913	&index );
4914	if ( ok ) // successful registration
4915	{
4916	r_cleanup_fsm = CLEANUP_DATA_GO;
4917	r_cleanup_trdid = index<<1;
4918	}
4919	}
4920	else if ( r_icache_cleanup_req.read() ) // icache request
4921	{
4922	ok = r_cleanup_buffer.write( r_icache_cleanup_line.read(),
4923	&index );
4924	if ( ok ) // successful registration
4925	{
4926	r_cleanup_fsm = CLEANUP_INS_GO;
4927	r_cleanup_trdid = (index<<1) + 1;
4928	}
4929	}
4930	break;
4931	}
4932	//////////////////////
4933	case CLEANUP_INS_IDLE: // icache has highest priority
4934	{
4935	size_t index = 0;
4936	bool ok;
4937	if ( r_icache_cleanup_req.read() ) // icache request
4938	{
4939	ok = r_cleanup_buffer.write( r_icache_cleanup_line.read(),
4940	&index );
4941	if ( ok ) // successful registration
4942	{
4943	r_cleanup_fsm = CLEANUP_INS_GO;
4944	r_cleanup_trdid = (index<<1) + 1;
4945	}
4946	}
4947	else if ( r_dcache_cleanup_req.read() ) // dcache request
4948	{
4949	ok = r_cleanup_buffer.write( r_dcache_cleanup_line.read(),
4950	&index );
4951	if ( ok ) // successful registration
4952	{
4953	r_cleanup_fsm = CLEANUP_DATA_GO;
4954	r_cleanup_trdid = index<<1;
4955	}
4956	}
4957	break;
4958	}
4959	/////////////////////
4960	case CLEANUP_DATA_GO:
4961	{
4962	if ( p_vci_ini_c.cmdack.read() )
4963	{
4964	r_cleanup_fsm = CLEANUP_INS_IDLE;
4965	r_dcache_cleanup_req = false;
4966
4967	#if DEBUG_CLEANUP
4968	if ( m_debug_cleanup_fsm )
4969	{
4970	std::cout << " <PROC " << name() << ".CLEANUP_DATA_GO> Cleanup request for icache:" << std::hex
4971	<< " address = " << (r_dcache_cleanup_line.read()m_dcache_words4)
4972	<< " / trdid = " << std::dec << r_cleanup_trdid.read() << std::endl;
4973	}
4974	#endif
4975	}
4976	break;
4977	}
4978	////////////////////
4979	case CLEANUP_INS_GO:
4980	{
4981	if ( p_vci_ini_c.cmdack.read() )
4982	{
4983	r_cleanup_fsm = CLEANUP_DATA_IDLE;
4984	r_icache_cleanup_req = false;
4985
4986	#if DEBUG_CLEANUP
4987	if ( m_debug_cleanup_fsm )
4988	{
4989	std::cout << " <PROC " << name() << ".CLEANUP_INS_GO> Cleanup request for dcache:" << std::hex
4990	<< " address = " << (r_icache_cleanup_line.read()m_icache_words4)
4991	<< " / trdid = " << std::dec << r_cleanup_trdid.read() << std::endl;
4992	}
4993	#endif
4994	}
4995	break;
4996	}
4997	} // end switch CLEANUP FSM
4998
4999	//////////////// Handling cleanup responses //////////////////
5000	if ( p_vci_ini_c.rspval.read() )
5001	{
5002	r_cleanup_buffer.inval( p_vci_ini_c.rtrdid.read() >> 1);
5003	}
5004
5005	///////////////// Response FIFOs update //////////////////////
5006	r_vci_rsp_fifo_icache.update(vci_rsp_fifo_icache_get,
5007	vci_rsp_fifo_icache_put,
5008	vci_rsp_fifo_icache_data);
5009
5010	r_vci_rsp_fifo_dcache.update(vci_rsp_fifo_dcache_get,
5011	vci_rsp_fifo_dcache_put,
5012	vci_rsp_fifo_dcache_data);
5013
5014	#undef LLSCLocalTable
5015	} // end transition()
5016
5017	///////////////////////
5018	tmpl(void)::genMoore()
5019	///////////////////////
5020	{
5021	////////////////////////////////////////////////////////////////
5022	// VCI initiator command on the coherence network (cleanup)
5023	// it depends on the CLEANUP FSM state
5024
5025	paddr_t cleanup_nline;
5026	paddr_t address;
5027
5028	if ( r_cleanup_fsm.read() == CLEANUP_DATA_GO )
5029	{
5030	cleanup_nline = r_dcache_cleanup_line.read();
5031	address = (m_x_width + m_y_width) ? (cleanup_nline * m_dcache_words * 4 ) >>
5032	(vci_param::N - m_x_width - m_y_width ) : 0;
5033	}
5034	else if ( r_cleanup_fsm.read() == CLEANUP_INS_GO )
5035	{
5036	cleanup_nline = r_icache_cleanup_line.read();
5037	address = (m_x_width + m_y_width) ? (cleanup_nline * m_icache_words * 4 ) >>
5038	(vci_param::N - m_x_width - m_y_width ) : 0;
5039	}
5040	else
5041	{
5042	cleanup_nline = 0;
5043	address = 0;
5044	}
5045
5046	address <<= vci_param::S - m_x_width - m_y_width;
5047	address \|= m_memory_cache_local_id;
5048	address <<= vci_param::N - vci_param::S;
5049
5050	p_vci_ini_c.cmdval = ((r_cleanup_fsm.read() == CLEANUP_DATA_GO) or
5051	(r_cleanup_fsm.read() == CLEANUP_INS_GO) );
5052	p_vci_ini_c.address = address;
5053	p_vci_ini_c.wdata = (uint32_t) cleanup_nline;
5054	p_vci_ini_c.be = (cleanup_nline >> 32) & 0x3;
5055	p_vci_ini_c.plen = 4;
5056	p_vci_ini_c.cmd = vci_param::CMD_WRITE;
5057	p_vci_ini_c.trdid = r_cleanup_trdid.read();
5058	p_vci_ini_c.pktid = 0;
5059	p_vci_ini_c.srcid = m_srcid_c;
5060	p_vci_ini_c.cons = false;
5061	p_vci_ini_c.wrap = false;
5062	p_vci_ini_c.contig = false;
5063	p_vci_ini_c.clen = 0;
5064	p_vci_ini_c.cfixed = false;
5065	p_vci_ini_c.eop = true;
5066
5067	/////////////////////////////////////////////////////////////////
5068	// VCI initiator response on the coherence network (cleanup)
5069	// We always consume the response, and we don't use it.
5070
5071	p_vci_ini_c.rspack = true;
5072
5073	/////////////////////////////////////////////////////////////////
5074	// VCI initiator command on the direct network
5075	// it depends on the CMD FSM state
5076
5077	bool is_sc_or_cas = (r_vci_cmd_fsm.read() == CMD_DATA_CAS) or
5078	(r_vci_cmd_fsm.read() == CMD_DATA_SC );
5079
5080	p_vci_ini_d.pktid = 0;
5081	p_vci_ini_d.srcid = m_srcid_d;
5082	p_vci_ini_d.cons = is_sc_or_cas;
5083	p_vci_ini_d.contig = not is_sc_or_cas;
5084	p_vci_ini_d.wrap = false;
5085	p_vci_ini_d.clen = 0;
5086	p_vci_ini_d.cfixed = false;
5087
5088	switch ( r_vci_cmd_fsm.read() ) {
5089
5090	case CMD_IDLE:
5091	p_vci_ini_d.cmdval = false;
5092	p_vci_ini_d.address = 0;
5093	p_vci_ini_d.wdata = 0;
5094	p_vci_ini_d.be = 0;
5095	p_vci_ini_d.trdid = 0;
5096	p_vci_ini_d.pktid = 0;
5097	p_vci_ini_d.plen = 0;
5098	p_vci_ini_d.cmd = vci_param::CMD_NOP;
5099	p_vci_ini_d.eop = false;
5100	break;
5101
5102	case CMD_INS_MISS:
5103	p_vci_ini_d.cmdval = true;
5104	p_vci_ini_d.address = r_icache_vci_paddr.read() & m_icache_yzmask;
5105	p_vci_ini_d.wdata = 0;
5106	p_vci_ini_d.be = 0xF;
5107	p_vci_ini_d.trdid = 0;
5108	p_vci_ini_d.pktid = TYPE_READ_INS_MISS;
5109	p_vci_ini_d.plen = m_icache_words<<2;
5110	p_vci_ini_d.cmd = vci_param::CMD_READ;
5111	p_vci_ini_d.eop = true;
5112	break;
5113
5114	case CMD_INS_UNC:
5115	p_vci_ini_d.cmdval = true;
5116	p_vci_ini_d.address = r_icache_vci_paddr.read() & ~0x3;
5117	p_vci_ini_d.wdata = 0;
5118	p_vci_ini_d.be = 0xF;
5119	p_vci_ini_d.trdid = 0;
5120	p_vci_ini_d.pktid = TYPE_READ_INS_UNC;
5121	p_vci_ini_d.plen = 4;
5122	p_vci_ini_d.cmd = vci_param::CMD_READ;
5123	p_vci_ini_d.eop = true;
5124	break;
5125
5126	case CMD_DATA_MISS:
5127	p_vci_ini_d.cmdval = true;
5128	p_vci_ini_d.address = r_dcache_vci_paddr.read() & m_dcache_yzmask;
5129	p_vci_ini_d.wdata = 0;
5130	p_vci_ini_d.be = 0xF;
5131	p_vci_ini_d.trdid = 0;
5132	p_vci_ini_d.pktid = TYPE_READ_DATA_MISS;
5133	p_vci_ini_d.plen = m_dcache_words << 2;
5134	p_vci_ini_d.cmd = vci_param::CMD_READ;
5135	p_vci_ini_d.eop = true;
5136	break;
5137
5138	case CMD_DATA_UNC:
5139	p_vci_ini_d.cmdval = true;
5140	p_vci_ini_d.address = r_dcache_vci_paddr.read() & ~0x3;
5141	p_vci_ini_d.wdata = 0;
5142	p_vci_ini_d.be = r_dcache_vci_unc_be.read();
5143	p_vci_ini_d.trdid = 0;
5144	p_vci_ini_d.pktid = TYPE_READ_DATA_UNC;
5145	p_vci_ini_d.plen = 4;
5146	p_vci_ini_d.cmd = vci_param::CMD_READ;
5147	p_vci_ini_d.eop = true;
5148	break;
5149
5150	case CMD_DATA_WRITE:
5151	p_vci_ini_d.cmdval = true;
5152	p_vci_ini_d.address = r_wbuf.getAddress(r_vci_cmd_cpt.read()) & ~0x3;
5153	p_vci_ini_d.wdata = r_wbuf.getData(r_vci_cmd_cpt.read());
5154	p_vci_ini_d.be = r_wbuf.getBe(r_vci_cmd_cpt.read());
5155	p_vci_ini_d.trdid = r_wbuf.getIndex();
5156	p_vci_ini_d.pktid = TYPE_WRITE;
5157	p_vci_ini_d.plen = (r_vci_cmd_max.read() - r_vci_cmd_min.read() + 1) << 2;
5158	p_vci_ini_d.cmd = vci_param::CMD_WRITE;
5159	p_vci_ini_d.eop = (r_vci_cmd_cpt.read() == r_vci_cmd_max.read());
5160	break;
5161
5162	case CMD_DATA_LL:
5163	p_vci_ini_d.cmdval = true;
5164	p_vci_ini_d.address = r_dcache_vci_paddr.read() & ~0x3;
5165	p_vci_ini_d.wdata = 0;
5166	p_vci_ini_d.be = 0xF;
5167	p_vci_ini_d.trdid = 0; //TODO local table index
5168	p_vci_ini_d.pktid = TYPE_LL;
5169	p_vci_ini_d.plen = 8;
5170	p_vci_ini_d.cmd = vci_param::CMD_LOCKED_READ;
5171	p_vci_ini_d.eop = true;
5172	break;
5173
5174	case CMD_DATA_SC:
5175	p_vci_ini_d.cmdval = true;
5176	p_vci_ini_d.address = r_dcache_vci_paddr.read() & ~0x3;
5177	if ( r_vci_cmd_cpt.read() == 0 ) p_vci_ini_d.wdata = r_sc_key.read();
5178	else p_vci_ini_d.wdata = r_dcache_vci_sc_data.read();
5179	p_vci_ini_d.be = 0xF;
5180	p_vci_ini_d.trdid = 0;
5181	p_vci_ini_d.pktid = TYPE_SC;
5182	p_vci_ini_d.plen = 8;
5183	p_vci_ini_d.cmd = vci_param::CMD_NOP;
5184	p_vci_ini_d.eop = (r_vci_cmd_cpt.read() == 1);
5185	break;
5186
5187	case CMD_DATA_CAS:
5188	p_vci_ini_d.cmdval = true;
5189	p_vci_ini_d.address = r_dcache_vci_paddr.read() & ~0x3;
5190	if ( r_vci_cmd_cpt.read() == 0 ) p_vci_ini_d.wdata = r_dcache_vci_cas_old.read();
5191	else p_vci_ini_d.wdata = r_dcache_vci_cas_new.read();
5192	p_vci_ini_d.be = 0xF;
5193	p_vci_ini_d.trdid = 0;
5194	p_vci_ini_d.pktid = TYPE_CAS;
5195	p_vci_ini_d.plen = 8;
5196	p_vci_ini_d.cmd = vci_param::CMD_NOP;
5197	p_vci_ini_d.eop = (r_vci_cmd_cpt.read() == 1);
5198	break;
5199	} // end switch r_vci_cmd_fsm
5200
5201	//////////////////////////////////////////////////////////
5202	// VCI initiator response on the direct network
5203	// it depends on the VCI RSP state
5204
5205	switch (r_vci_rsp_fsm.read() )
5206	{
5207	case RSP_DATA_WRITE : p_vci_ini_d.rspack = true; break;
5208	case RSP_INS_MISS : p_vci_ini_d.rspack = r_vci_rsp_fifo_icache.wok(); break;
5209	case RSP_INS_UNC : p_vci_ini_d.rspack = r_vci_rsp_fifo_icache.wok(); break;
5210	case RSP_DATA_MISS : p_vci_ini_d.rspack = r_vci_rsp_fifo_dcache.wok(); break;
5211	case RSP_DATA_UNC : p_vci_ini_d.rspack = r_vci_rsp_fifo_dcache.wok(); break;
5212	case RSP_DATA_LL : p_vci_ini_d.rspack = r_vci_rsp_fifo_dcache.wok(); break;
5213	case RSP_IDLE : p_vci_ini_d.rspack = false; break;
5214	} // end switch r_vci_rsp_fsm
5215
5216	////////////////////////////////////////////////////////////////
5217	// VCI target command and response on the coherence network
5218	switch ( r_tgt_fsm.read() )
5219	{
5220	case TGT_IDLE:
5221	case TGT_UPDT_WORD:
5222	case TGT_UPDT_DATA:
5223	p_vci_tgt_c.cmdack = true;
5224	p_vci_tgt_c.rspval = false;
5225	break;
5226
5227	case TGT_RSP_BROADCAST:
5228	p_vci_tgt_c.cmdack = false;
5229	p_vci_tgt_c.rspval = not r_tgt_icache_req.read() and not r_tgt_dcache_req.read()
5230	and ( r_tgt_icache_rsp.read() or r_tgt_dcache_rsp.read() );
5231	p_vci_tgt_c.rsrcid = r_tgt_srcid.read();
5232	p_vci_tgt_c.rpktid = r_tgt_pktid.read();
5233	p_vci_tgt_c.rtrdid = r_tgt_trdid.read();
5234	p_vci_tgt_c.rdata = 0;
5235	p_vci_tgt_c.rerror = 0;
5236	p_vci_tgt_c.reop = true;
5237	break;
5238
5239	case TGT_RSP_ICACHE:
5240	p_vci_tgt_c.cmdack = false;
5241	p_vci_tgt_c.rspval = not r_tgt_icache_req.read() and r_tgt_icache_rsp.read();
5242	p_vci_tgt_c.rsrcid = r_tgt_srcid.read();
5243	p_vci_tgt_c.rpktid = r_tgt_pktid.read();
5244	p_vci_tgt_c.rtrdid = r_tgt_trdid.read();
5245	p_vci_tgt_c.rdata = 0;
5246	p_vci_tgt_c.rerror = 0;
5247	p_vci_tgt_c.reop = true;
5248	break;
5249
5250	case TGT_RSP_DCACHE:
5251	p_vci_tgt_c.cmdack = false;
5252	p_vci_tgt_c.rspval = not r_tgt_dcache_req.read() and r_tgt_dcache_rsp.read();
5253	p_vci_tgt_c.rsrcid = r_tgt_srcid.read();
5254	p_vci_tgt_c.rpktid = r_tgt_pktid.read();
5255	p_vci_tgt_c.rtrdid = r_tgt_trdid.read();
5256	p_vci_tgt_c.rdata = 0;
5257	p_vci_tgt_c.rerror = 0;
5258	p_vci_tgt_c.reop = true;
5259	break;
5260
5261	case TGT_REQ_BROADCAST:
5262	case TGT_REQ_ICACHE:
5263	case TGT_REQ_DCACHE:
5264	p_vci_tgt_c.cmdack = false;
5265	p_vci_tgt_c.rspval = false;
5266	break;
5267
5268	} // end switch TGT_FSM
5269	} // end genMoore
5270
5271	}}
5272
5273	// Local Variables:
5274	// tab-width: 4
5275	// c-basic-offset: 4
5276	// c-file-offsets:((innamespace . 0)(inline-open . 0))
5277	// indent-tabs-mode: nil
5278	// End:
5279
5280	// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4

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source: branches/v4/modules/vci_cc_vcache_wrapper_v4/caba/source/src/vci_cc_vcache_wrapper_v4.cpp @ 635

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