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source: branches/v5/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp @ 351

Last change on this file since 351 was 351, checked in by joannou, 11 years ago
Got rid of intermediate v5 version. _dspin_coherence versions changed to main version for v5. Changed components names and platforms to fit the new names
File size: 231.0 KB

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1	/* -- c++ --
2	* File : vci_cc_vcache_wrapper.cpp
3	* Copyright (c) UPMC, Lip6, SoC
4	* Authors : Alain GREINER, Yang GAO
5	*
6	* SOCLIB_LGPL_HEADER_BEGIN
7	*
8	* This file is part of SoCLib, GNU LGPLv2.1.
9	*
10	* SoCLib is free software; you can redistribute it and/or modify it
11	* under the terms of the GNU Lesser General Public License as published
12	* by the Free Software Foundation; version 2.1 of the License.
13	*
14	* SoCLib is distributed in the hope that it will be useful, but
15	* WITHOUT ANY WARRANTY; without even the implied warranty of
16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17	* Lesser General Public License for more details.
18	*
19	* You should have received a copy of the GNU Lesser General Public
20	* License along with SoCLib; if not, write to the Free Software
21	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
22	* 02110-1301 USA
23	*
24	* SOCLIB_LGPL_HEADER_END
25	*
26	* Maintainers: cesar.fuguet-tortolero@lip6.fr
27	* alexandre.joannou@lip6.fr
28	*/
29
30	#include <cassert>
31	#include "arithmetics.h"
32	#include "../include/vci_cc_vcache_wrapper.h"
33
34	#define DEBUG_DCACHE 1
35	#define DEBUG_ICACHE 1
36	#define DEBUG_CLEANUP 0
37
38	namespace soclib {
39	namespace caba {
40
41	namespace {
42	const char *icache_fsm_state_str[] = {
43	"ICACHE_IDLE",
44
45	"ICACHE_XTN_TLB_FLUSH",
46	"ICACHE_XTN_CACHE_FLUSH",
47	"ICACHE_XTN_CACHE_FLUSH_GO",
48	"ICACHE_XTN_TLB_INVAL",
49	"ICACHE_XTN_CACHE_INVAL_VA",
50	"ICACHE_XTN_CACHE_INVAL_PA",
51	"ICACHE_XTN_CACHE_INVAL_GO",
52
53	"ICACHE_TLB_WAIT",
54
55	"ICACHE_MISS_SELECT",
56	"ICACHE_MISS_CLEAN",
57	"ICACHE_MISS_WAIT",
58	"ICACHE_MISS_DATA_UPDT",
59	"ICACHE_MISS_DIR_UPDT",
60
61	"ICACHE_UNC_WAIT",
62
63	"ICACHE_CC_CHECK",
64	"ICACHE_CC_INVAL",
65	"ICACHE_CC_UPDT",
66	"ICACHE_CC_BROADCAST",
67	"ICACHE_CC_SEND_WAIT",
68	};
69
70	const char *dcache_fsm_state_str[] = {
71	"DCACHE_IDLE",
72
73	"DCACHE_TLB_MISS",
74	"DCACHE_TLB_PTE1_GET",
75	"DCACHE_TLB_PTE1_SELECT",
76	"DCACHE_TLB_PTE1_UPDT",
77	"DCACHE_TLB_PTE2_GET",
78	"DCACHE_TLB_PTE2_SELECT",
79	"DCACHE_TLB_PTE2_UPDT",
80	"DCACHE_TLB_LR_UPDT",
81	"DCACHE_TLB_LR_WAIT",
82	"DCACHE_TLB_RETURN",
83
84	"DCACHE_XTN_SWITCH",
85	"DCACHE_XTN_SYNC",
86	"DCACHE_XTN_IC_INVAL_VA",
87	"DCACHE_XTN_IC_FLUSH",
88	"DCACHE_XTN_IC_INVAL_PA",
89	"DCACHE_XTN_IT_INVAL",
90	"DCACHE_XTN_DC_FLUSH",
91	"DCACHE_XTN_DC_FLUSH_GO",
92	"DCACHE_XTN_DC_INVAL_VA",
93	"DCACHE_XTN_DC_INVAL_PA",
94	"DCACHE_XTN_DC_INVAL_END",
95	"DCACHE_XTN_DC_INVAL_GO",
96	"DCACHE_XTN_DT_INVAL",
97
98	"DCACHE_DIRTY_PTE_GET",
99	"DCACHE_DIRTY_WAIT",
100
101	"DCACHE_MISS_SELECT",
102	"DCACHE_MISS_CLEAN",
103	"DCACHE_MISS_WAIT",
104	"DCACHE_MISS_DATA_UPDT",
105	"DCACHE_MISS_DIR_UPDT",
106
107	"DCACHE_UNC_WAIT",
108	"DCACHE_LL_WAIT",
109	"DCACHE_SC_WAIT",
110
111	"DCACHE_CC_CHECK",
112	"DCACHE_CC_INVAL",
113	"DCACHE_CC_UPDT",
114	"DCACHE_CC_BROADCAST",
115	"DCACHE_CC_SEND_WAIT",
116
117	"DCACHE_INVAL_TLB_SCAN",
118	};
119
120	const char *cmd_fsm_state_str[] = {
121	"CMD_IDLE",
122	"CMD_INS_MISS",
123	"CMD_INS_UNC",
124	"CMD_DATA_MISS",
125	"CMD_DATA_UNC",
126	"CMD_DATA_WRITE",
127	"CMD_DATA_LL",
128	"CMD_DATA_SC",
129	"CMD_DATA_CAS",
130	};
131
132	const char *rsp_fsm_state_str[] = {
133	"RSP_IDLE",
134	"RSP_INS_MISS",
135	"RSP_INS_UNC",
136	"RSP_DATA_MISS",
137	"RSP_DATA_UNC",
138	"RSP_DATA_LL",
139	"RSP_DATA_WRITE",
140	};
141
142	const char *cc_receive_fsm_state_str[] = {
143	"CC_RECEIVE_IDLE",
144	"CC_RECEIVE_CLACK",
145	"CC_RECEIVE_BRDCAST_HEADER",
146	"CC_RECEIVE_BRDCAST_NLINE",
147	"CC_RECEIVE_INVAL_HEADER",
148	"CC_RECEIVE_INVAL_NLINE",
149	"CC_RECEIVE_UPDT_HEADER",
150	"CC_RECEIVE_UPDT_NLINE",
151	"CC_RECEIVE_UPDT_DATA",
152	};
153
154	const char *cc_send_fsm_state_str[] = {
155	"CC_SEND_IDLE",
156	"CC_SEND_CLEANUP_1",
157	"CC_SEND_CLEANUP_2",
158	"CC_SEND_MULTI_ACK",
159	};
160	}
161
162	#define tmpl(...) template<typename vci_param, typename iss_t> __VA_ARGS__ VciCcVCacheWrapper<vci_param, iss_t>
163
164	using namespace soclib::common;
165
166	/////////////////////////////////
167	tmpl(/**/)::VciCcVCacheWrapper(
168	sc_module_name name,
169	const int proc_id,
170	const MappingTable &mtd,
171	const IntTab &srcid,
172	const size_t cc_global_id,
173	const size_t itlb_ways,
174	const size_t itlb_sets,
175	const size_t dtlb_ways,
176	const size_t dtlb_sets,
177	const size_t icache_ways,
178	const size_t icache_sets,
179	const size_t icache_words,
180	const size_t dcache_ways,
181	const size_t dcache_sets,
182	const size_t dcache_words,
183	const size_t wbuf_nlines,
184	const size_t wbuf_nwords,
185	const size_t x_width,
186	const size_t y_width,
187	const uint32_t max_frozen_cycles,
188	const uint32_t debug_start_cycle,
189	const bool debug_ok )
190	: soclib::caba::BaseModule(name),
191
192	p_clk("p_clk"),
193	p_resetn("p_resetn"),
194	p_vci("p_vci"),
195	p_dspin_in("p_dspin_in"),
196	p_dspin_out("p_dspin_out"),
197
198	m_cacheability_table( mtd.getCacheabilityTable() ),
199	m_srcid( mtd.indexForId(srcid) ),
200	m_cc_global_id( cc_global_id ),
201	m_nline_width( vci_param::N - (uint32_log2(dcache_words)) - 2 ),
202	m_itlb_ways( itlb_ways ),
203	m_itlb_sets( itlb_sets ),
204	m_dtlb_ways( dtlb_ways ),
205	m_dtlb_sets( dtlb_sets ),
206	m_icache_ways( icache_ways ),
207	m_icache_sets( icache_sets ),
208	m_icache_yzmask( (~0)<<(uint32_log2(icache_words) + 2) ),
209	m_icache_words( icache_words ),
210	m_dcache_ways( dcache_ways ),
211	m_dcache_sets( dcache_sets ),
212	m_dcache_yzmask( (~0)<<(uint32_log2(dcache_words) + 2) ),
213	m_dcache_words( dcache_words ),
214	m_x_width( x_width ),
215	m_y_width( y_width ),
216	m_proc_id( proc_id ),
217	m_max_frozen_cycles( max_frozen_cycles ),
218	m_paddr_nbits( vci_param::N ),
219	m_debug_start_cycle( debug_start_cycle ),
220	m_debug_ok( debug_ok ),
221
222	r_mmu_ptpr("r_mmu_ptpr"),
223	r_mmu_mode("r_mmu_mode"),
224	r_mmu_word_lo("r_mmu_word_lo"),
225	r_mmu_word_hi("r_mmu_word_hi"),
226	r_mmu_ibvar("r_mmu_ibvar"),
227	r_mmu_dbvar("r_mmu_dbvar"),
228	r_mmu_ietr("r_mmu_ietr"),
229	r_mmu_detr("r_mmu_detr"),
230
231	r_icache_fsm("r_icache_fsm"),
232	r_icache_fsm_save("r_icache_fsm_save"),
233	r_icache_vci_paddr("r_icache_vci_paddr"),
234	r_icache_vaddr_save("r_icache_vaddr_save"),
235
236	r_icache_miss_way("r_icache_miss_way"),
237	r_icache_miss_set("r_icache_miss_set"),
238	r_icache_miss_word("r_icache_miss_word"),
239	r_icache_miss_inval("r_icache_miss_inval"),
240	r_icache_miss_clack("r_icache_miss_clack"),
241
242	r_icache_cc_way("r_icache_cc_way"),
243	r_icache_cc_set("r_icache_cc_set"),
244	r_icache_cc_word("r_icache_cc_word"),
245	r_icache_cc_need_write("r_icache_cc_need_write"),
246
247	r_icache_flush_count("r_icache_flush_count"),
248
249	r_icache_miss_req("r_icache_miss_req"),
250	r_icache_unc_req("r_icache_unc_req"),
251
252	r_icache_tlb_miss_req("r_icache_tlb_read_req"),
253	r_icache_tlb_rsp_error("r_icache_tlb_rsp_error"),
254
255	r_icache_cc_send_req("r_icache_cc_send_req"),
256	r_icache_cc_send_type("r_icache_cc_send_type"),
257	r_icache_cc_send_nline("r_icache_cc_send_nline"),
258	r_icache_cc_send_way("r_icache_cc_send_way"),
259	r_icache_cc_send_updt_tab_idx("r_icache_cc_send_updt_tab_idx"),
260
261	r_dcache_fsm("r_dcache_fsm"),
262	r_dcache_fsm_cc_save("r_dcache_fsm_cc_save"),
263	r_dcache_fsm_scan_save("r_dcache_fsm_scan_save"),
264
265	r_dcache_wbuf_req("r_dcache_wbuf_req"),
266	r_dcache_updt_req("r_dcache_updt_req"),
267	r_dcache_save_vaddr("r_dcache_save_vaddr"),
268	r_dcache_save_wdata("r_dcache_save_wdata"),
269	r_dcache_save_be("r_dcache_save_be"),
270	r_dcache_save_paddr("r_dcache_save_paddr"),
271	r_dcache_save_cacheable("r_dcache_save_cacheable"),
272	r_dcache_save_cache_way("r_dcache_save_cache_way"),
273	r_dcache_save_cache_set("r_dcache_save_cache_set"),
274	r_dcache_save_cache_word("r_dcache_save_cache_word"),
275
276	r_dcache_dirty_paddr("r_dcache_dirty_paddr"),
277	r_dcache_dirty_way("r_dcache_dirty_way"),
278	r_dcache_dirty_set("r_dcache_dirty_set"),
279
280	r_dcache_vci_paddr("r_dcache_vci_paddr"),
281	r_dcache_vci_miss_req("r_dcache_vci_miss_req"),
282	r_dcache_vci_unc_req("r_dcache_vci_unc_req"),
283	r_dcache_vci_unc_be("r_dcache_vci_unc_be"),
284	r_dcache_vci_cas_req("r_dcache_vci_cas_req"),
285	r_dcache_vci_cas_old("r_dcache_vci_cas_old"),
286	r_dcache_vci_cas_new("r_dcache_vci_cas_new"),
287	r_dcache_vci_ll_req("r_dcache_vci_ll_req"),
288	r_dcache_vci_sc_req("r_dcache_vci_sc_req"),
289	r_dcache_vci_sc_data("r_dcache_vci_sc_data"),
290
291	r_dcache_xtn_way("r_dcache_xtn_way"),
292	r_dcache_xtn_set("r_dcache_xtn_set"),
293
294	r_dcache_pending_unc_write("r_dcache_pending_unc_write"),
295
296	r_dcache_miss_type("r_dcache_miss_type"),
297	r_dcache_miss_word("r_dcache_miss_word"),
298	r_dcache_miss_way("r_dcache_miss_way"),
299	r_dcache_miss_set("r_dcache_miss_set"),
300	r_dcache_miss_inval("r_dcache_miss_inval"),
301
302	r_dcache_cc_way("r_dcache_cc_way"),
303	r_dcache_cc_set("r_dcache_cc_set"),
304	r_dcache_cc_word("r_dcache_cc_word"),
305	r_dcache_cc_need_write("r_dcache_cc_need_write"),
306
307	r_dcache_flush_count("r_dcache_flush_count"),
308
309	r_dcache_ll_rsp_count("r_dcache_ll_rsp_count"),
310
311	r_dcache_tlb_vaddr("r_dcache_tlb_vaddr"),
312	r_dcache_tlb_ins("r_dcache_tlb_ins"),
313	r_dcache_tlb_pte_flags("r_dcache_tlb_pte_flags"),
314	r_dcache_tlb_pte_ppn("r_dcache_tlb_pte_ppn"),
315	r_dcache_tlb_cache_way("r_dcache_tlb_cache_way"),
316	r_dcache_tlb_cache_set("r_dcache_tlb_cache_set"),
317	r_dcache_tlb_cache_word("r_dcache_tlb_cache_word"),
318	r_dcache_tlb_way("r_dcache_tlb_way"),
319	r_dcache_tlb_set("r_dcache_tlb_set"),
320
321	r_dcache_tlb_inval_line("r_dcache_tlb_inval_line"),
322	r_dcache_tlb_inval_set("r_dcache_tlb_inval_set"),
323
324	r_dcache_xtn_req("r_dcache_xtn_req"),
325	r_dcache_xtn_opcode("r_dcache_xtn_opcode"),
326
327	r_dcache_cc_send_req("r_dcache_cc_send_req"),
328	r_dcache_cc_send_type("r_dcache_cc_send_type"),
329	r_dcache_cc_send_nline("r_dcache_cc_send_nline"),
330	r_dcache_cc_send_way("r_dcache_cc_send_way"),
331	r_dcache_cc_send_updt_tab_idx("r_dcache_cc_send_updt_tab_idx"),
332
333	r_vci_cmd_fsm("r_vci_cmd_fsm"),
334	r_vci_cmd_min("r_vci_cmd_min"),
335	r_vci_cmd_max("r_vci_cmd_max"),
336	r_vci_cmd_cpt("r_vci_cmd_cpt"),
337	r_vci_cmd_imiss_prio("r_vci_cmd_imiss_prio"),
338
339	r_vci_rsp_fsm("r_vci_rsp_fsm"),
340	r_vci_rsp_cpt("r_vci_rsp_cpt"),
341	r_vci_rsp_ins_error("r_vci_rsp_ins_error"),
342	r_vci_rsp_data_error("r_vci_rsp_data_error"),
343	r_vci_rsp_fifo_icache("r_vci_rsp_fifo_icache", 2), // 2 words depth
344	r_vci_rsp_fifo_dcache("r_vci_rsp_fifo_dcache", 2), // 2 words depth
345
346	r_cc_send_fsm("r_cc_send_fsm"),
347	r_cc_send_last_client("r_cc_send_last_client"),
348
349	r_cc_receive_fsm("r_cc_receive_fsm"),
350	r_cc_receive_data_ins("r_cc_receive_data_ins"),
351	r_cc_receive_word_idx("r_cc_receive_word_idx"),
352	r_cc_receive_updt_fifo_be("r_cc_receive_updt_fifo_be", 2), // 2 words depth
353	r_cc_receive_updt_fifo_data("r_cc_receive_updt_fifo_data", 2), // 2 words depth
354	r_cc_receive_updt_fifo_eop("r_cc_receive_updt_fifo_eop", 2), // 2 words depth
355
356	r_cc_receive_icache_req("r_cc_receive_icache_req"),
357	r_cc_receive_icache_type("r_cc_receive_icache_type"),
358	r_cc_receive_icache_way("r_cc_receive_icache_way"),
359	r_cc_receive_icache_set("r_cc_receive_icache_set"),
360	r_cc_receive_icache_updt_tab_idx("r_cc_receive_icache_updt_tab_idx"),
361	r_cc_receive_icache_nline("r_cc_receive_icache_nline"),
362
363	r_cc_receive_dcache_req("r_cc_receive_dcache_req"),
364	r_cc_receive_dcache_type("r_cc_receive_dcache_type"),
365	r_cc_receive_dcache_way("r_cc_receive_dcache_way"),
366	r_cc_receive_dcache_set("r_cc_receive_dcache_set"),
367	r_cc_receive_dcache_updt_tab_idx("r_cc_receive_dcache_updt_tab_idx"),
368	r_cc_receive_dcache_nline("r_cc_receive_dcache_nline"),
369
370	r_iss(this->name(), proc_id),
371	r_wbuf("wbuf", wbuf_nwords, wbuf_nlines, dcache_words ),
372	r_icache("icache", icache_ways, icache_sets, icache_words),
373	r_dcache("dcache", dcache_ways, dcache_sets, dcache_words),
374	r_itlb("itlb", proc_id, itlb_ways,itlb_sets,vci_param::N),
375	r_dtlb("dtlb", proc_id, dtlb_ways,dtlb_sets,vci_param::N)
376	{
377	assert( ((icache_words*vci_param::B) < (1<<vci_param::K)) and
378	"Need more PLEN bits.");
379
380	assert( (vci_param::T > 2) and ((1<<(vci_param::T-1)) >= (wbuf_nlines)) and
381	"Need more TRDID bits.");
382
383	assert( (icache_words == dcache_words) and
384	"icache_words and dcache_words parameters must be equal");
385
386	assert( (itlb_sets == dtlb_sets) and
387	"itlb_sets and dtlb_sets parameters must be etqual");
388
389	assert( (itlb_ways == dtlb_ways) and
390	"itlb_ways and dtlb_ways parameters must be etqual");
391
392	r_mmu_params = (uint32_log2(m_dtlb_ways) << 29) \| (uint32_log2(m_dtlb_sets) << 25) \|
393	(uint32_log2(m_dcache_ways) << 22) \| (uint32_log2(m_dcache_sets) << 18) \|
394	(uint32_log2(m_itlb_ways) << 15) \| (uint32_log2(m_itlb_sets) << 11) \|
395	(uint32_log2(m_icache_ways) << 8) \| (uint32_log2(m_icache_sets) << 4) \|
396	(uint32_log2(m_icache_words<<2));
397
398	r_mmu_release = (uint32_t)(1 << 16) \| 0x1;
399
400	r_dcache_in_tlb = new bool[dcache_ways*dcache_sets];
401	r_dcache_contains_ptd = new bool[dcache_ways*dcache_sets];
402
403	SC_METHOD(transition);
404	dont_initialize();
405	sensitive << p_clk.pos();
406
407	SC_METHOD(genMoore);
408	dont_initialize();
409	sensitive << p_clk.neg();
410
411	typename iss_t::CacheInfo cache_info;
412	cache_info.has_mmu = true;
413	cache_info.icache_line_size = icache_words*sizeof(uint32_t);
414	cache_info.icache_assoc = icache_ways;
415	cache_info.icache_n_lines = icache_sets;
416	cache_info.dcache_line_size = dcache_words*sizeof(uint32_t);
417	cache_info.dcache_assoc = dcache_ways;
418	cache_info.dcache_n_lines = dcache_sets;
419	r_iss.setCacheInfo(cache_info);
420	}
421
422	/////////////////////////////////////
423	tmpl(/**/)::~VciCcVCacheWrapper()
424	/////////////////////////////////////
425	{
426	delete [] r_dcache_in_tlb;
427	delete [] r_dcache_contains_ptd;
428	}
429
430	////////////////////////
431	tmpl(void)::print_cpi()
432	////////////////////////
433	{
434	std::cout << name() << " CPI = "
435	<< (float)m_cpt_total_cycles/(m_cpt_total_cycles - m_cpt_frz_cycles) << std::endl ;
436	}
437
438	////////////////////////////////////
439	tmpl(void)::print_trace(size_t mode)
440	////////////////////////////////////
441	{
442	// b0 : write buffer trace
443	// b1 : write buffer verbose
444	// b2 : dcache trace
445	// b3 : icache trace
446	// b4 : dtlb trace
447	// b5 : itlb trace
448
449	std::cout << std::dec << "PROC " << name() << std::endl;
450
451	std::cout << " " << m_ireq << std::endl;
452	std::cout << " " << m_irsp << std::endl;
453	std::cout << " " << m_dreq << std::endl;
454	std::cout << " " << m_drsp << std::endl;
455
456	std::cout << " " << icache_fsm_state_str[r_icache_fsm.read()]
457	<< " \| " << dcache_fsm_state_str[r_dcache_fsm.read()]
458	<< " \| " << cmd_fsm_state_str[r_vci_cmd_fsm.read()]
459	<< " \| " << rsp_fsm_state_str[r_vci_rsp_fsm.read()]
460	<< " \| " << cc_receive_fsm_state_str[r_cc_receive_fsm.read()]
461	<< " \| " << cc_send_fsm_state_str[r_cc_send_fsm.read()];
462	if (r_dcache_updt_req.read() ) std::cout << " \| P1_UPDT";
463	if (r_dcache_wbuf_req.read() ) std::cout << " \| P1_WBUF";
464	std::cout << std::endl;
465
466	if(mode & 0x01)
467	{
468	r_wbuf.printTrace((mode>>1)&1);
469	}
470	if(mode & 0x04)
471	{
472	std::cout << " Data Cache" << std::endl;
473	r_dcache.printTrace();
474	}
475	if(mode & 0x08)
476	{
477	std::cout << " Instruction Cache" << std::endl;
478	r_icache.printTrace();
479	}
480	if(mode & 0x10)
481	{
482	std::cout << " Data TLB" << std::endl;
483	r_dtlb.printTrace();
484	}
485	if(mode & 0x20)
486	{
487	std::cout << " Instruction TLB" << std::endl;
488	r_itlb.printTrace();
489	}
490	}
491
492	//////////////////////////////////////////
493	tmpl(void)::cache_monitor( paddr_t addr )
494	//////////////////////////////////////////
495	{
496	size_t cache_way;
497	size_t cache_set;
498	size_t cache_word;
499	uint32_t cache_rdata;
500	bool cache_hit = r_dcache.read_neutral( addr,
501	&cache_rdata,
502	&cache_way,
503	&cache_set,
504	&cache_word );
505	bool icache_hit = r_icache.read_neutral( addr,
506	&cache_rdata,
507	&cache_way,
508	&cache_set,
509	&cache_word );
510	if ( cache_hit != m_debug_previous_hit )
511	{
512	std::cout << "PROC " << name()
513	<< " dcache change at cycle " << std::dec << m_cpt_total_cycles
514	<< " for adresse " << std::hex << addr
515	<< " / HIT = " << std::dec << cache_hit << std::endl;
516	m_debug_previous_hit = cache_hit;
517	}
518	if ( icache_hit != m_idebug_previous_hit )
519	{
520	std::cout << "PROC " << name()
521	<< " icache change at cycle " << std::dec << m_cpt_total_cycles
522	<< " for adresse " << std::hex << addr
523	<< " / HIT = " << icache_hit << std::endl;
524	m_idebug_previous_hit = icache_hit;
525	}
526	}
527
528	/*
529	////////////////////////
530	tmpl(void)::print_stats()
531	////////////////////////
532	{
533	float run_cycles = (float)(m_cpt_total_cycles - m_cpt_frz_cycles);
534	std::cout << name() << std::endl
535	<< "- CPI = " << (float)m_cpt_total_cycles/run_cycles << std::endl
536	<< "- READ RATE = " << (float)m_cpt_read/run_cycles << std::endl
537	<< "- WRITE RATE = " << (float)m_cpt_write/run_cycles << std::endl
538	<< "- IMISS_RATE = " << (float)m_cpt_ins_miss/m_cpt_ins_read << std::endl
539	<< "- DMISS RATE = " << (float)m_cpt_data_miss/(m_cpt_read-m_cpt_unc_read) << std::endl
540	<< "- INS MISS COST = " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl
541	<< "- DATA MISS COST = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl
542	<< "- WRITE COST = " << (float)m_cost_write_frz/m_cpt_write << std::endl
543	<< "- UNC COST = " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl
544	<< "- UNCACHED READ RATE = " << (float)m_cpt_unc_read/m_cpt_read << std::endl
545	<< "- CACHED WRITE RATE = " << (float)m_cpt_write_cached/m_cpt_write << std::endl
546	<< "- INS TLB MISS RATE = " << (float)m_cpt_ins_tlb_miss/m_cpt_ins_tlb_read << std::endl
547	<< "- DATA TLB MISS RATE = " << (float)m_cpt_data_tlb_miss/m_cpt_data_tlb_read << std::endl
548	<< "- ITLB MISS COST = " << (float)m_cost_ins_tlb_miss_frz/m_cpt_ins_tlb_miss << std::endl
549	<< "- DTLB MISS COST = " << (float)m_cost_data_tlb_miss_frz/m_cpt_data_tlb_miss << std::endl
550	<< "- ITLB UPDATE ACC COST = " << (float)m_cost_ins_tlb_update_acc_frz/m_cpt_ins_tlb_update_acc << std::endl
551	<< "- DTLB UPDATE ACC COST = " << (float)m_cost_data_tlb_update_acc_frz/m_cpt_data_tlb_update_acc << std::endl
552	<< "- DTLB UPDATE DIRTY COST = " << (float)m_cost_data_tlb_update_dirty_frz/m_cpt_data_tlb_update_dirty << std::endl
553	<< "- ITLB HIT IN DCACHE RATE= " << (float)m_cpt_ins_tlb_hit_dcache/m_cpt_ins_tlb_miss << std::endl
554	<< "- DTLB HIT IN DCACHE RATE= " << (float)m_cpt_data_tlb_hit_dcache/m_cpt_data_tlb_miss << std::endl
555	<< "- DCACHE FROZEN BY ITLB = " << (float)m_cost_ins_tlb_occup_cache_frz/m_cpt_dcache_frz_cycles << std::endl
556	<< "- DCACHE FOR TLB % = " << (float)m_cpt_tlb_occup_dcache/(m_dcache_ways*m_dcache_sets) << std::endl
557	<< "- NB CC BROADCAST = " << m_cpt_cc_broadcast << std::endl
558	<< "- NB CC UPDATE DATA = " << m_cpt_cc_update_data << std::endl
559	<< "- NB CC INVAL DATA = " << m_cpt_cc_inval_data << std::endl
560	<< "- NB CC INVAL INS = " << m_cpt_cc_inval_ins << std::endl
561	<< "- CC BROADCAST COST = " << (float)m_cost_broadcast_frz/m_cpt_cc_broadcast << std::endl
562	<< "- CC UPDATE DATA COST = " << (float)m_cost_updt_data_frz/m_cpt_cc_update_data << std::endl
563	<< "- CC INVAL DATA COST = " << (float)m_cost_inval_data_frz/m_cpt_cc_inval_data << std::endl
564	<< "- CC INVAL INS COST = " << (float)m_cost_inval_ins_frz/m_cpt_cc_inval_ins << std::endl
565	<< "- NB CC CLEANUP DATA = " << m_cpt_cc_cleanup_data << std::endl
566	<< "- NB CC CLEANUP INS = " << m_cpt_cc_cleanup_ins << std::endl
567	<< "- IMISS TRANSACTION = " << (float)m_cost_imiss_transaction/m_cpt_imiss_transaction << std::endl
568	<< "- DMISS TRANSACTION = " << (float)m_cost_dmiss_transaction/m_cpt_dmiss_transaction << std::endl
569	<< "- UNC TRANSACTION = " << (float)m_cost_unc_transaction/m_cpt_unc_transaction << std::endl
570	<< "- WRITE TRANSACTION = " << (float)m_cost_write_transaction/m_cpt_write_transaction << std::endl
571	<< "- WRITE LENGTH = " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl
572	<< "- ITLB MISS TRANSACTION = " << (float)m_cost_itlbmiss_transaction/m_cpt_itlbmiss_transaction << std::endl
573	<< "- DTLB MISS TRANSACTION = " << (float)m_cost_dtlbmiss_transaction/m_cpt_dtlbmiss_transaction << std::endl;
574	}
575
576	////////////////////////
577	tmpl(void)::clear_stats()
578	////////////////////////
579	{
580	m_cpt_dcache_data_read = 0;
581	m_cpt_dcache_data_write = 0;
582	m_cpt_dcache_dir_read = 0;
583	m_cpt_dcache_dir_write = 0;
584	m_cpt_icache_data_read = 0;
585	m_cpt_icache_data_write = 0;
586	m_cpt_icache_dir_read = 0;
587	m_cpt_icache_dir_write = 0;
588
589	m_cpt_frz_cycles = 0;
590	m_cpt_dcache_frz_cycles = 0;
591	m_cpt_total_cycles = 0;
592
593	m_cpt_read = 0;
594	m_cpt_write = 0;
595	m_cpt_data_miss = 0;
596	m_cpt_ins_miss = 0;
597	m_cpt_unc_read = 0;
598	m_cpt_write_cached = 0;
599	m_cpt_ins_read = 0;
600
601	m_cost_write_frz = 0;
602	m_cost_data_miss_frz = 0;
603	m_cost_unc_read_frz = 0;
604	m_cost_ins_miss_frz = 0;
605
606	m_cpt_imiss_transaction = 0;
607	m_cpt_dmiss_transaction = 0;
608	m_cpt_unc_transaction = 0;
609	m_cpt_write_transaction = 0;
610	m_cpt_icache_unc_transaction = 0;
611
612	m_cost_imiss_transaction = 0;
613	m_cost_dmiss_transaction = 0;
614	m_cost_unc_transaction = 0;
615	m_cost_write_transaction = 0;
616	m_cost_icache_unc_transaction = 0;
617	m_length_write_transaction = 0;
618
619	m_cpt_ins_tlb_read = 0;
620	m_cpt_ins_tlb_miss = 0;
621	m_cpt_ins_tlb_update_acc = 0;
622
623	m_cpt_data_tlb_read = 0;
624	m_cpt_data_tlb_miss = 0;
625	m_cpt_data_tlb_update_acc = 0;
626	m_cpt_data_tlb_update_dirty = 0;
627	m_cpt_ins_tlb_hit_dcache = 0;
628	m_cpt_data_tlb_hit_dcache = 0;
629	m_cpt_ins_tlb_occup_cache = 0;
630	m_cpt_data_tlb_occup_cache = 0;
631
632	m_cost_ins_tlb_miss_frz = 0;
633	m_cost_data_tlb_miss_frz = 0;
634	m_cost_ins_tlb_update_acc_frz = 0;
635	m_cost_data_tlb_update_acc_frz = 0;
636	m_cost_data_tlb_update_dirty_frz = 0;
637	m_cost_ins_tlb_occup_cache_frz = 0;
638	m_cost_data_tlb_occup_cache_frz = 0;
639
640	m_cpt_itlbmiss_transaction = 0;
641	m_cpt_itlb_ll_transaction = 0;
642	m_cpt_itlb_sc_transaction = 0;
643	m_cpt_dtlbmiss_transaction = 0;
644	m_cpt_dtlb_ll_transaction = 0;
645	m_cpt_dtlb_sc_transaction = 0;
646	m_cpt_dtlb_ll_dirty_transaction = 0;
647	m_cpt_dtlb_sc_dirty_transaction = 0;
648
649	m_cost_itlbmiss_transaction = 0;
650	m_cost_itlb_ll_transaction = 0;
651	m_cost_itlb_sc_transaction = 0;
652	m_cost_dtlbmiss_transaction = 0;
653	m_cost_dtlb_ll_transaction = 0;
654	m_cost_dtlb_sc_transaction = 0;
655	m_cost_dtlb_ll_dirty_transaction = 0;
656	m_cost_dtlb_sc_dirty_transaction = 0;
657
658	m_cpt_cc_update_data = 0;
659	m_cpt_cc_inval_ins = 0;
660	m_cpt_cc_inval_data = 0;
661	m_cpt_cc_broadcast = 0;
662
663	m_cost_updt_data_frz = 0;
664	m_cost_inval_ins_frz = 0;
665	m_cost_inval_data_frz = 0;
666	m_cost_broadcast_frz = 0;
667
668	m_cpt_cc_cleanup_data = 0;
669	m_cpt_cc_cleanup_ins = 0;
670	}
671
672	*/
673
674	/////////////////////////
675	tmpl(void)::transition()
676	/////////////////////////
677	{
678	#define LLSCLocalTable GenericLLSCLocalTable<8000, 1, paddr_t, vci_trdid_t, vci_data_t>
679	if ( not p_resetn.read() )
680	{
681	r_iss.reset();
682	r_wbuf.reset();
683	r_icache.reset();
684	r_dcache.reset();
685	r_itlb.reset();
686	r_dtlb.reset();
687
688	r_dcache_fsm = DCACHE_IDLE;
689	r_icache_fsm = ICACHE_IDLE;
690	r_vci_cmd_fsm = CMD_IDLE;
691	r_vci_rsp_fsm = RSP_IDLE;
692	r_cc_receive_fsm = CC_RECEIVE_IDLE;
693	r_cc_send_fsm = CC_SEND_IDLE;
694
695	// reset dcache directory extension
696	for (size_t i=0 ; i< m_dcache_ways*m_dcache_sets ; i++)
697	{
698	r_dcache_in_tlb[i] = false;
699	r_dcache_contains_ptd[i] = false;
700	}
701
702	// Response FIFOs and cleanup buffer
703	r_vci_rsp_fifo_icache.init();
704	r_vci_rsp_fifo_dcache.init();
705
706	// ICACHE & DCACHE activated
707	r_mmu_mode = 0x3;
708
709	// No request from ICACHE FSM to CMD FSM
710	r_icache_miss_req = false;
711	r_icache_unc_req = false;
712
713	// No request from ICACHE_FSM to DCACHE FSM
714	r_icache_tlb_miss_req = false;
715
716	// No request from ICACHE_FSM to CC_SEND FSM
717	r_icache_cc_send_req = false;
718
719	// No pending write in pipeline
720	r_dcache_wbuf_req = false;
721	r_dcache_updt_req = false;
722
723	// No request from DCACHE_FSM to CMD_FSM
724	r_dcache_vci_miss_req = false;
725	r_dcache_vci_unc_req = false;
726	r_dcache_vci_cas_req = false;
727	r_dcache_vci_ll_req = false;
728	r_dcache_vci_sc_req = false;
729
730	// No uncacheable write pending
731	r_dcache_pending_unc_write = false;
732
733	// No processor XTN request pending
734	r_dcache_xtn_req = false;
735
736	// No request from DCACHE FSM to CC_SEND FSM
737	r_dcache_cc_send_req = false;
738
739	// No request from CC_RECEIVE FSM to ICACHE/DCACHE FSMs
740	r_cc_receive_icache_req = false;
741	r_cc_receive_dcache_req = false;
742
743	// last cc_send client was dcache
744	r_cc_send_last_client = false;
745
746	// No pending cleanup after a replacement
747	r_icache_miss_clack = false;
748	r_dcache_miss_clack = false;
749
750	// No signalisation of a coherence request matching a pending miss
751	r_icache_miss_inval = false;
752	r_dcache_miss_inval = false;
753
754	// No signalisation of errors
755	r_vci_rsp_ins_error = false;
756	r_vci_rsp_data_error = false;
757
758	// Debug variables
759	m_debug_previous_hit = false;
760	m_idebug_previous_hit = false;
761	m_debug_dcache_fsm = false;
762	m_debug_icache_fsm = false;
763
764	// activity counters
765	m_cpt_dcache_data_read = 0;
766	m_cpt_dcache_data_write = 0;
767	m_cpt_dcache_dir_read = 0;
768	m_cpt_dcache_dir_write = 0;
769	m_cpt_icache_data_read = 0;
770	m_cpt_icache_data_write = 0;
771	m_cpt_icache_dir_read = 0;
772	m_cpt_icache_dir_write = 0;
773
774	m_cpt_frz_cycles = 0;
775	m_cpt_total_cycles = 0;
776	m_cpt_stop_simulation = 0;
777
778	m_cpt_data_miss = 0;
779	m_cpt_ins_miss = 0;
780	m_cpt_unc_read = 0;
781	m_cpt_write_cached = 0;
782	m_cpt_ins_read = 0;
783
784	m_cost_write_frz = 0;
785	m_cost_data_miss_frz = 0;
786	m_cost_unc_read_frz = 0;
787	m_cost_ins_miss_frz = 0;
788
789	m_cpt_imiss_transaction = 0;
790	m_cpt_dmiss_transaction = 0;
791	m_cpt_unc_transaction = 0;
792	m_cpt_write_transaction = 0;
793	m_cpt_icache_unc_transaction = 0;
794
795	m_cost_imiss_transaction = 0;
796	m_cost_dmiss_transaction = 0;
797	m_cost_unc_transaction = 0;
798	m_cost_write_transaction = 0;
799	m_cost_icache_unc_transaction = 0;
800	m_length_write_transaction = 0;
801
802	m_cpt_ins_tlb_read = 0;
803	m_cpt_ins_tlb_miss = 0;
804	m_cpt_ins_tlb_update_acc = 0;
805
806	m_cpt_data_tlb_read = 0;
807	m_cpt_data_tlb_miss = 0;
808	m_cpt_data_tlb_update_acc = 0;
809	m_cpt_data_tlb_update_dirty = 0;
810	m_cpt_ins_tlb_hit_dcache = 0;
811	m_cpt_data_tlb_hit_dcache = 0;
812	m_cpt_ins_tlb_occup_cache = 0;
813	m_cpt_data_tlb_occup_cache = 0;
814
815	m_cost_ins_tlb_miss_frz = 0;
816	m_cost_data_tlb_miss_frz = 0;
817	m_cost_ins_tlb_update_acc_frz = 0;
818	m_cost_data_tlb_update_acc_frz = 0;
819	m_cost_data_tlb_update_dirty_frz = 0;
820	m_cost_ins_tlb_occup_cache_frz = 0;
821	m_cost_data_tlb_occup_cache_frz = 0;
822
823	m_cpt_ins_tlb_inval = 0;
824	m_cpt_data_tlb_inval = 0;
825	m_cost_ins_tlb_inval_frz = 0;
826	m_cost_data_tlb_inval_frz = 0;
827
828	m_cpt_cc_broadcast = 0;
829
830	m_cost_updt_data_frz = 0;
831	m_cost_inval_ins_frz = 0;
832	m_cost_inval_data_frz = 0;
833	m_cost_broadcast_frz = 0;
834
835	m_cpt_cc_cleanup_data = 0;
836	m_cpt_cc_cleanup_ins = 0;
837
838	m_cpt_itlbmiss_transaction = 0;
839	m_cpt_itlb_ll_transaction = 0;
840	m_cpt_itlb_sc_transaction = 0;
841	m_cpt_dtlbmiss_transaction = 0;
842	m_cpt_dtlb_ll_transaction = 0;
843	m_cpt_dtlb_sc_transaction = 0;
844	m_cpt_dtlb_ll_dirty_transaction = 0;
845	m_cpt_dtlb_sc_dirty_transaction = 0;
846
847	m_cost_itlbmiss_transaction = 0;
848	m_cost_itlb_ll_transaction = 0;
849	m_cost_itlb_sc_transaction = 0;
850	m_cost_dtlbmiss_transaction = 0;
851	m_cost_dtlb_ll_transaction = 0;
852	m_cost_dtlb_sc_transaction = 0;
853	m_cost_dtlb_ll_dirty_transaction = 0;
854	m_cost_dtlb_sc_dirty_transaction = 0;
855	/*
856	m_cpt_dcache_frz_cycles = 0;
857	m_cpt_read = 0;
858	m_cpt_write = 0;
859	m_cpt_cc_update_data = 0;
860	m_cpt_cc_inval_ins = 0;
861	m_cpt_cc_inval_data = 0;
862	*/
863
864	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_icache [i] = 0;
865	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_dcache [i] = 0;
866	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_cmd [i] = 0;
867	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_rsp [i] = 0;
868
869	// init the llsc reservation buffer
870	r_dcache_llsc_valid = false;
871
872	return;
873	}
874
875	// Response FIFOs default values
876	bool vci_rsp_fifo_icache_get = false;
877	bool vci_rsp_fifo_icache_put = false;
878	uint32_t vci_rsp_fifo_icache_data = 0;
879
880	bool vci_rsp_fifo_dcache_get = false;
881	bool vci_rsp_fifo_dcache_put = false;
882	uint32_t vci_rsp_fifo_dcache_data = 0;
883
884	// updt fifo
885	bool cc_receive_updt_fifo_get = false;
886	bool cc_receive_updt_fifo_put = false;
887	uint32_t cc_receive_updt_fifo_be = 0;
888	uint32_t cc_receive_updt_fifo_data = 0;
889	bool cc_receive_updt_fifo_eop = false;
890
891	#ifdef INSTRUMENTATION
892	m_cpt_fsm_dcache [r_dcache_fsm.read() ] ++;
893	m_cpt_fsm_icache [r_icache_fsm.read() ] ++;
894	m_cpt_fsm_cmd [r_vci_cmd_fsm.read()] ++;
895	m_cpt_fsm_rsp [r_vci_rsp_fsm.read()] ++;
896	m_cpt_fsm_tgt [r_tgt_fsm.read() ] ++;
897	m_cpt_fsm_cleanup [r_cleanup_cmd_fsm.read()] ++;
898	#endif
899
900	m_cpt_total_cycles++;
901
902	m_debug_icache_fsm = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok;
903	m_debug_dcache_fsm = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok;
904
905	/////////////////////////////////////////////////////////////////////
906	// Get data and instruction requests from processor
907	///////////////////////////////////////////////////////////////////////
908
909	r_iss.getRequests(m_ireq, m_dreq);
910
911	////////////////////////////////////////////////////////////////////////////////////
912	// ICACHE_FSM
913	//
914	// 1/ Coherence operations
915	// They are handled as interrupts generated by the CC_RECEIVE FSM.
916	// - There is a coherence request when r_tgt_icache_req is set.
917	// They are taken in IDLE, MISS_WAIT, MISS_DIR_UPDT, UNC_WAIT, states.
918	// - There is a cleanup ack request when r_cleanup_icache_req is set.
919	// They are taken in IDLE, MISS_SELECT, MISS_CLEAN, MISS_WAIT,
920	// MISS_DATA_UPDT, MISS_DIR_UPDT and UNC_WAIT states.
921	// - For both types of requests, actions associated to the pre-empted state
922	// are not executed. The DCACHE FSM goes to the proper sub-FSM (CC_CHECK
923	// or CC_CLACK) to execute the requested coherence operation, and returns
924	// to the pre-empted state.
925	//
926	// 2/ Processor requests
927	// They are taken in IDLE state only. In case of cache miss, or uncacheable
928	// instruction, the ICACHE FSM request a VCI transaction to CMD FSM,
929	// using the r_icache_miss_req or r_icache_unc_req flip-flops. These
930	// flip-flops are reset when the transaction starts.
931	// - In case of miss the ICACHE FSM goes to the ICACHE_MISS_SELECT state
932	// to select a slot and possibly request a cleanup transaction to the CC_SEND FSM.
933	// It goes next to the ICACHE_MISS_WAIT state waiting a response from RSP FSM,
934	// The availability of the missing cache line is signaled by the response fifo,
935	// and the cache update is done (one word per cycle) in the ICACHE_MISS_DATA_UPDT
936	// and ICACHE_MISS_DIR_UPDT states.
937	// - In case of uncacheable instruction, the ICACHE FSM goes to ICACHE_UNC_WAIT
938	// to wait the response from the RSP FSM, through the response fifo.
939	// The missing instruction is directly returned to processor in this state.
940	//
941	// 3/ TLB miss
942	// In case of tlb miss, the ICACHE FSM request to the DCACHE FSM to update the
943	// ITLB using the r_icache_tlb_miss_req flip-flop and the r_icache_tlb_miss_vaddr
944	// register, and goes to the ICACHE_TLB_WAIT state.
945	// The tlb update is entirely done by the DCACHE FSM (who becomes the owner
946	// of ITLB until the update is completed, and reset r_icache_tlb_miss_req
947	// to signal the completion.
948	//
949	// 4/ XTN requests
950	// The DCACHE FSM signals XTN processor requests to ICACHE_FSM
951	// using the r_dcache_xtn_req flip-flop.
952	// The request opcode and the address to be invalidated are transmitted
953	// in the r_dcache_xtn_opcode and r_dcache_save_wdata registers respectively.
954	// The r_dcache_xtn_req flip-flop is reset by the ICACHE_FSM when the operation
955	// is completed.
956	//
957	// 5/ Error Handling
958	// The r_vci_rsp_ins_error flip-flop is set by the RSP FSM in case of bus error
959	// in a cache miss or uncacheable read VCI transaction. Nothing is written
960	// in the response fifo. This flip-flop is reset by the ICACHE-FSM.
961	////////////////////////////////////////////////////////////////////////////////////////
962
963	// default value for m_irsp
964	m_irsp.valid = false;
965	m_irsp.error = false;
966	m_irsp.instruction = 0;
967
968	switch( r_icache_fsm.read() )
969	{
970	/////////////////
971	case ICACHE_IDLE: // In this state, we handle processor requests, XTN requests,
972	// and coherence requests with a fixed priority:
973	// 1/ Coherence requests => ICACHE_CC_CHECK
974	// 2/ XTN processor requests (from DCACHE FSM) => ICACHE_XTN_*
975	// 3/ tlb miss => ICACHE_TLB_WAIT
976	// 4/ cacheable read miss => ICACHE_MISS_SELECT
977	// 5/ uncacheable read miss => ICACHE_UNC_REQ
978	{
979	// coherence interrupt
980	if ( r_cc_receive_icache_req.read() )
981	{
982	r_icache_fsm = ICACHE_CC_CHECK;
983	r_icache_fsm_save = r_icache_fsm.read();
984	break;
985	}
986
987	// XTN requests sent by DCACHE FSM
988	// These request are not executed in this IDLE state, because
989	// they require access to icache or itlb, that are already accessed
990	if ( r_dcache_xtn_req.read() )
991	{
992	if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_PTPR )
993	{
994	r_icache_fsm = ICACHE_XTN_TLB_FLUSH;
995	}
996	else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ICACHE_FLUSH)
997	{
998	r_icache_flush_count = 0;
999	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH;
1000	}
1001	else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ITLB_INVAL)
1002	{
1003	r_icache_fsm = ICACHE_XTN_TLB_INVAL;
1004	}
1005	else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ICACHE_INVAL)
1006	{
1007	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_VA;
1008	}
1009	else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_MMU_ICACHE_PA_INV)
1010	{
1011	if (sizeof(paddr_t) <= 32)
1012	{
1013	assert(r_mmu_word_hi.read() == 0 &&
1014	"illegal XTN request in ICACHE: high bits should be 0 for 32bit paddr");
1015	r_icache_vci_paddr = (paddr_t)r_mmu_word_lo.read();
1016	}
1017	else
1018	{
1019	r_icache_vci_paddr = (paddr_t)r_mmu_word_hi.read() << 32 \|
1020	(paddr_t)r_mmu_word_lo.read();
1021	}
1022	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA;
1023	}
1024	else
1025	{
1026	assert( false and
1027	"undefined XTN request received by ICACHE FSM");
1028	}
1029	break;
1030	} // end if xtn_req
1031
1032	// processor request
1033	if ( m_ireq.valid )
1034	{
1035	bool cacheable;
1036	paddr_t paddr;
1037	bool tlb_hit = false;
1038	pte_info_t tlb_flags;
1039	size_t tlb_way;
1040	size_t tlb_set;
1041	paddr_t tlb_nline;
1042	uint32_t cache_inst = 0;
1043	size_t cache_way;
1044	size_t cache_set;
1045	size_t cache_word;
1046	int cache_state = CACHE_SLOT_STATE_EMPTY;
1047
1048	// We register processor request
1049	r_icache_vaddr_save = m_ireq.addr;
1050
1051	// sytematic itlb access (if activated)
1052	if ( r_mmu_mode.read() & INS_TLB_MASK )
1053	{
1054
1055	#ifdef INSTRUMENTATION
1056	m_cpt_itlb_read++;
1057	#endif
1058	tlb_hit = r_itlb.translate( m_ireq.addr,
1059	&paddr,
1060	&tlb_flags,
1061	&tlb_nline, // unused
1062	&tlb_way, // unused
1063	&tlb_set ); // unused
1064	}
1065	else
1066	{
1067	paddr = (paddr_t)m_ireq.addr;
1068	}
1069
1070	// systematic icache access (if activated)
1071	if ( r_mmu_mode.read() & INS_CACHE_MASK )
1072	{
1073
1074
1075	#ifdef INSTRUMENTATION
1076	m_cpt_icache_data_read++;
1077	m_cpt_icache_dir_read++;
1078	#endif
1079	r_icache.read( paddr,
1080	&cache_inst,
1081	&cache_way,
1082	&cache_set,
1083	&cache_word,
1084	&cache_state );
1085	}
1086
1087	// We compute cacheability and check access rights:
1088	// - If MMU activated : cacheability is defined by the C bit in the PTE,
1089	// and the access rights are defined by the U and X bits in the PTE.
1090	// - If MMU not activated : cacheability is defined by the segment table,
1091	// and there is no access rights checking
1092
1093	if ( not (r_mmu_mode.read() & INS_TLB_MASK) ) // tlb not activated:
1094	{
1095	// cacheability
1096	if ( not (r_mmu_mode.read() & INS_CACHE_MASK) ) cacheable = false;
1097	else cacheable = m_cacheability_table[m_ireq.addr];
1098	}
1099	else // itlb activated
1100	{
1101	if ( tlb_hit ) // ITLB hit
1102	{
1103	// cacheability
1104	if ( not (r_mmu_mode.read() & INS_CACHE_MASK) ) cacheable = false;
1105	else cacheable = tlb_flags.c;
1106
1107	// access rights checking
1108	if ( not tlb_flags.u && (m_ireq.mode == iss_t::MODE_USER) )
1109	{
1110	r_mmu_ietr = MMU_READ_PRIVILEGE_VIOLATION;
1111	r_mmu_ibvar = m_ireq.addr;
1112	m_irsp.valid = true;
1113	m_irsp.error = true;
1114	m_irsp.instruction = 0;
1115	break;
1116	}
1117	else if ( not tlb_flags.x )
1118	{
1119	r_mmu_ietr = MMU_READ_EXEC_VIOLATION;
1120	r_mmu_ibvar = m_ireq.addr;
1121	m_irsp.valid = true;
1122	m_irsp.error = true;
1123	m_irsp.instruction = 0;
1124	break;
1125	}
1126	}
1127	else // ITLB miss
1128	{
1129
1130	#ifdef INSTRUMENTATION
1131	m_cpt_itlb_miss++;
1132	#endif
1133	r_icache_fsm = ICACHE_TLB_WAIT;
1134	r_icache_tlb_miss_req = true;
1135	break;
1136	}
1137	} // end if itlb activated
1138
1139	// physical address registration
1140	r_icache_vci_paddr = paddr;
1141
1142	// Finally, we send the response to processor, and compute next state
1143	if ( cacheable )
1144	{
1145	if (cache_state == CACHE_SLOT_STATE_EMPTY) // cache miss
1146	{
1147
1148	#ifdef INSTRUMENTATION
1149	m_cpt_icache_miss++;
1150	#endif
1151	// we request a VCI transaction
1152	r_icache_fsm = ICACHE_MISS_SELECT;
1153	r_icache_miss_req = true;
1154	}
1155	else if (cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup
1156	{
1157	// stalled until cleanup is acknowledged
1158	r_icache_fsm = ICACHE_IDLE;
1159	}
1160	else // cache hit
1161	{
1162
1163	#ifdef INSTRUMENTATION
1164	m_cpt_ins_read++;
1165	#endif
1166	// return instruction to processor
1167	m_irsp.valid = true;
1168	m_irsp.instruction = cache_inst;
1169	r_icache_fsm = ICACHE_IDLE;
1170	}
1171	}
1172	else // non cacheable read
1173	{
1174	r_icache_unc_req = true;
1175	r_icache_fsm = ICACHE_UNC_WAIT;
1176	}
1177	} // end if m_ireq.valid
1178	break;
1179	}
1180	/////////////////////
1181	case ICACHE_TLB_WAIT: // Waiting the itlb update by the DCACHE FSM after a tlb miss
1182	// the itlb is udated by the DCACHE FSM, as well as the
1183	// r_mmu_ietr and r_mmu_ibvar registers in case of error.
1184	// the itlb is not accessed by ICACHE FSM until DCACHE FSM
1185	// reset the r_icache_tlb_miss_req flip-flop
1186	// external coherence request are accepted in this state.
1187	{
1188	// coherence interrupt
1189	if ( r_cc_receive_icache_req.read() )
1190	{
1191	r_icache_fsm = ICACHE_CC_CHECK;
1192	r_icache_fsm_save = r_icache_fsm.read();
1193	break;
1194	}
1195
1196	if ( m_ireq.valid ) m_cost_ins_tlb_miss_frz++;
1197
1198	// DCACHE FSM signals response by reseting the request flip-flop
1199	if ( not r_icache_tlb_miss_req.read() )
1200	{
1201	if ( r_icache_tlb_rsp_error.read() ) // error reported : tlb not updated
1202	{
1203	r_icache_tlb_rsp_error = false;
1204	m_irsp.error = true;
1205	m_irsp.valid = true;
1206	r_icache_fsm = ICACHE_IDLE;
1207	}
1208	else // tlb updated : return to IDLE state
1209	{
1210	r_icache_fsm = ICACHE_IDLE;
1211	}
1212	}
1213	break;
1214	}
1215	//////////////////////////
1216	case ICACHE_XTN_TLB_FLUSH: // invalidate in one cycle all non global TLB entries
1217	{
1218	r_itlb.flush();
1219	r_dcache_xtn_req = false;
1220	r_icache_fsm = ICACHE_IDLE;
1221	break;
1222	}
1223	////////////////////////////
1224	case ICACHE_XTN_CACHE_FLUSH: // Invalidate sequencially all cache lines, using
1225	// r_icache_flush_count as a slot counter,
1226	// looping in this state until all slots are visited.
1227	// It can require two cycles per slot:
1228	// We test here the slot state, and make the actual inval
1229	// (if line is valid) in ICACHE_XTN_CACHE_FLUSH_GO state.
1230	// A cleanup request is generated for each valid line
1231	{
1232	if ( not r_icache_cc_send_req.read() ) // blocked until previous cc_send request is sent
1233	{
1234	int state;
1235	uint32_t tag;
1236	size_t way = r_icache_flush_count.read()/m_icache_sets;
1237	size_t set = r_icache_flush_count.read()%m_icache_sets;
1238
1239	#ifdef INSTRUMENTATION
1240	m_cpt_icache_dir_read++;
1241	#endif
1242	r_icache.read_dir( way,
1243	set,
1244	&tag,
1245	&state );
1246
1247	if ( state == CACHE_SLOT_STATE_VALID ) // inval required
1248	{
1249	// request cleanup
1250	r_icache_cc_send_req = true;
1251	r_icache_cc_send_nline = tag * m_icache_sets;
1252	r_icache_cc_send_way = way;
1253	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1254
1255	// goes to ICACHE_XTN_CACHE_FLUSH_GO to make inval
1256	r_icache_miss_way = way;
1257	r_icache_miss_set = set;
1258	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH_GO;
1259	}
1260	else if ( r_icache_flush_count.read() ==
1261	(m_icache_sets*m_icache_ways - 1) ) // last slot
1262	{
1263	r_dcache_xtn_req = false;
1264	m_drsp.valid = true;
1265	r_icache_fsm = ICACHE_IDLE;
1266	}
1267
1268	// saturation counter, to have the same last slot condition
1269	// in ICACHE_XTN_CACHE_FLUSH and ICACHE_XTN_CACHE_FLUSH_GO states
1270	if ( r_icache_flush_count.read() < (m_icache_sets*m_icache_ways - 1) )
1271	{
1272	r_icache_flush_count = r_icache_flush_count.read() + 1;
1273	}
1274	}
1275	break;
1276	}
1277	///////////////////////////////
1278	case ICACHE_XTN_CACHE_FLUSH_GO: // Switch slot state to ZOMBI for an XTN flush
1279	{
1280	size_t way = r_icache_miss_way.read();
1281	size_t set = r_icache_miss_set.read();
1282
1283	#ifdef INSTRUMENTATION
1284	m_cpt_icache_dir_write++;
1285	#endif
1286
1287	r_icache.write_dir( 0,
1288	way,
1289	set,
1290	CACHE_SLOT_STATE_ZOMBI );
1291
1292	if ( r_icache_flush_count.read() ==
1293	(m_icache_sets*m_icache_ways - 1) ) // last slot
1294	{
1295	r_dcache_xtn_req = false;
1296	m_drsp.valid = true;
1297	r_icache_fsm = ICACHE_IDLE;
1298	}
1299	else
1300	{
1301	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH;
1302	}
1303	break;
1304	}
1305
1306	//////////////////////////
1307	case ICACHE_XTN_TLB_INVAL: // invalidate one TLB entry selected by the virtual address
1308	// stored in the r_dcache_save_wdata register
1309	{
1310	r_itlb.inval(r_dcache_save_wdata.read());
1311	r_dcache_xtn_req = false;
1312	r_icache_fsm = ICACHE_IDLE;
1313	break;
1314	}
1315	///////////////////////////////
1316	case ICACHE_XTN_CACHE_INVAL_VA: // Selective cache line invalidate with virtual address
1317	// requires 3 cycles (in case of hit on itlb and icache).
1318	// In this state, access TLB to translate virtual address
1319	// stored in the r_dcache_save_wdata register.
1320	{
1321	paddr_t paddr;
1322	bool hit;
1323
1324	// read physical address in TLB when MMU activated
1325	if ( r_mmu_mode.read() & INS_TLB_MASK ) // itlb activated
1326	{
1327
1328	#ifdef INSTRUMENTATION
1329	m_cpt_itlb_read++;
1330	#endif
1331	hit = r_itlb.translate(r_dcache_save_wdata.read(),
1332	&paddr);
1333	}
1334	else // itlb not activated
1335	{
1336	paddr = (paddr_t)r_dcache_save_wdata.read();
1337	hit = true;
1338	}
1339
1340	if ( hit ) // continue the selective inval process
1341	{
1342	r_icache_vci_paddr = paddr;
1343	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA;
1344	}
1345	else // miss : send a request to DCACHE FSM
1346	{
1347
1348	#ifdef INSTRUMENTATION
1349	m_cpt_itlb_miss++;
1350	#endif
1351	r_icache_tlb_miss_req = true;
1352	r_icache_vaddr_save = r_dcache_save_wdata.read();
1353	r_icache_fsm = ICACHE_TLB_WAIT;
1354	}
1355	break;
1356	}
1357	///////////////////////////////
1358	case ICACHE_XTN_CACHE_INVAL_PA: // selective invalidate cache line with physical address
1359	// require 2 cycles. In this state, we read directory
1360	// with address stored in r_icache_vci_paddr register.
1361	{
1362	int state;
1363	size_t way;
1364	size_t set;
1365	size_t word;
1366
1367	#ifdef INSTRUMENTATION
1368	m_cpt_icache_dir_read++;
1369	#endif
1370	r_icache.read_dir(r_icache_vci_paddr.read(),
1371	&state,
1372	&way,
1373	&set,
1374	&word);
1375
1376	if ( state == CACHE_SLOT_STATE_VALID ) // inval to be done
1377	{
1378	r_icache_miss_way = way;
1379	r_icache_miss_set = set;
1380	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_GO;
1381	}
1382	else // miss : acknowlege the XTN request and return
1383	{
1384	r_dcache_xtn_req = false;
1385	r_icache_fsm = ICACHE_IDLE;
1386	}
1387	break;
1388	}
1389	///////////////////////////////
1390	case ICACHE_XTN_CACHE_INVAL_GO: // Switch slot to ZOMBI state for an XTN inval
1391	{
1392	if ( not r_icache_cc_send_req.read() ) // blocked until previous cc_send request not sent
1393	{
1394
1395	#ifdef INSTRUMENTATION
1396	m_cpt_icache_dir_write++;
1397	#endif
1398	r_icache.write_dir( 0,
1399	r_icache_miss_way.read(),
1400	r_icache_miss_set.read(),
1401	CACHE_SLOT_STATE_ZOMBI );
1402
1403	// request cleanup
1404	r_icache_cc_send_req = true;
1405	r_icache_cc_send_nline = r_icache_vci_paddr.read() / (m_icache_words<<2);
1406	r_icache_cc_send_way = r_icache_miss_way.read();
1407	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1408
1409	// acknowledge the XTN request and return
1410	r_dcache_xtn_req = false;
1411	r_icache_fsm = ICACHE_IDLE;
1412	}
1413	break;
1414	}
1415	////////////////////////
1416	case ICACHE_MISS_SELECT: // Try to select a slot in associative set,
1417	// if previous cleanup has been sent.
1418	// Waiting in this state if no slot available.
1419	// Set the r_icache_cleanup_req flip-flop
1420	// and the r_icache_miss_clack flip-flop,
1421	// when a cleanup is required
1422	{
1423	if (m_ireq.valid) m_cost_ins_miss_frz++;
1424
1425	// coherence interrupt
1426	if ( r_cc_receive_icache_req.read() )
1427	{
1428	r_icache_fsm = ICACHE_CC_CHECK;
1429	r_icache_fsm_save = r_icache_fsm.read();
1430	break;
1431	}
1432
1433	if ( not r_icache_cc_send_req.read() ) // wait for previous cc_send request to be sent
1434	{
1435	bool found;
1436	bool cleanup;
1437	size_t way;
1438	size_t set;
1439	paddr_t victim;
1440
1441	#ifdef INSTRUMENTATION
1442	m_cpt_icache_dir_read++;
1443	#endif
1444	r_icache.read_select(r_icache_vci_paddr.read(),
1445	&victim,
1446	&way,
1447	&set,
1448	&found,
1449	&cleanup );
1450	if ( found )
1451	{
1452	r_icache_miss_way = way;
1453	r_icache_miss_set = set;
1454
1455	if ( cleanup )
1456	{
1457	r_icache_fsm = ICACHE_MISS_CLEAN;
1458	r_icache_miss_clack = true;
1459	// request cleanup
1460	r_icache_cc_send_req = true;
1461	r_icache_cc_send_nline = victim;
1462	r_icache_cc_send_way = way;
1463	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1464	}
1465	else
1466	{
1467	r_icache_fsm = ICACHE_MISS_WAIT;
1468	}
1469
1470	#if DEBUG_ICACHE
1471	if ( m_debug_dcache_fsm )
1472	{
1473	std::cout << " <PROC " << name()
1474	<< " ICACHE_MISS_SELECT> Select a slot:" << std::dec
1475	<< " / WAY = " << way
1476	<< " / SET = " << set;
1477	if (cleanup) std::cout << " / VICTIM = " << std::hex << victim << std::endl;
1478	else std::cout << std::endl;
1479	}
1480	#endif
1481	}
1482	}
1483	break;
1484	}
1485	///////////////////////
1486	case ICACHE_MISS_CLEAN: // switch the slot to zombi state
1487	{
1488	if (m_ireq.valid) m_cost_ins_miss_frz++;
1489
1490	// coherence interrupt
1491	if ( r_cc_receive_icache_req.read() )
1492	{
1493	r_icache_fsm = ICACHE_CC_CHECK;
1494	r_icache_fsm_save = r_icache_fsm.read();
1495	break;
1496	}
1497
1498	#ifdef INSTRUMENTATION
1499	m_cpt_icache_dir_write++;
1500	#endif
1501	r_icache.write_dir( 0,
1502	r_icache_miss_way.read(),
1503	r_icache_miss_set.read(),
1504	CACHE_SLOT_STATE_ZOMBI);
1505	#if DEBUG_ICACHE
1506	if ( m_debug_dcache_fsm )
1507	{
1508	std::cout << " <PROC " << name()
1509	<< " ICACHE_MISS_CLEAN> Switch to ZOMBI state" << std::dec
1510	<< " / WAY = " << r_icache_miss_way.read()
1511	<< " / SET = " << r_icache_miss_set.read() << std::endl;
1512	}
1513	#endif
1514
1515	r_icache_fsm = ICACHE_MISS_WAIT;
1516	break;
1517	}
1518	//////////////////////
1519	case ICACHE_MISS_WAIT: // waiting response from VCI_RSP FSM
1520	{
1521	if (m_ireq.valid) m_cost_ins_miss_frz++;
1522
1523	// coherence interrupt
1524	if ( r_cc_receive_icache_req.read() )
1525	{
1526	r_icache_fsm = ICACHE_CC_CHECK;
1527	r_icache_fsm_save = r_icache_fsm.read();
1528	break;
1529	}
1530
1531	if ( r_vci_rsp_ins_error.read() ) // bus error
1532	{
1533	r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS;
1534	r_mmu_ibvar = r_icache_vaddr_save.read();
1535	m_irsp.valid = true;
1536	m_irsp.error = true;
1537	r_vci_rsp_ins_error = false;
1538	r_icache_fsm = ICACHE_IDLE;
1539	}
1540	else if ( r_vci_rsp_fifo_icache.rok() ) // response available
1541	{
1542	r_icache_miss_word = 0;
1543	r_icache_fsm = ICACHE_MISS_DATA_UPDT;
1544	}
1545	break;
1546	}
1547	///////////////////////////
1548	case ICACHE_MISS_DATA_UPDT: // update the cache (one word per cycle)
1549	{
1550	if ( m_ireq.valid ) m_cost_ins_miss_frz++;
1551
1552	if ( r_vci_rsp_fifo_icache.rok() ) // response available
1553	{
1554
1555	#ifdef INSTRUMENTATION
1556	m_cpt_icache_data_write++;
1557	#endif
1558	r_icache.write( r_icache_miss_way.read(),
1559	r_icache_miss_set.read(),
1560	r_icache_miss_word.read(),
1561	r_vci_rsp_fifo_icache.read() );
1562	#if DEBUG_ICACHE
1563	if ( m_debug_icache_fsm )
1564	{
1565	std::cout << " <PROC " << name()
1566	<< " ICACHE_MISS_DATA_UPDT> Write one word:"
1567	<< " WDATA = " << r_vci_rsp_fifo_icache.read()
1568	<< " WAY = " << r_icache_miss_way.read()
1569	<< " SET = " << r_icache_miss_set.read()
1570	<< " WORD = " << r_icache_miss_word.read() << std::endl;
1571	}
1572	#endif
1573	vci_rsp_fifo_icache_get = true;
1574	r_icache_miss_word = r_icache_miss_word.read() + 1;
1575
1576	if ( r_icache_miss_word.read() == m_icache_words-1 ) // last word
1577	{
1578	r_icache_fsm = ICACHE_MISS_DIR_UPDT;
1579	}
1580	}
1581	break;
1582	}
1583	//////////////////////////
1584	case ICACHE_MISS_DIR_UPDT: // Stalled if a victim line has been evicted,
1585	// and the cleanup ack has not been received,
1586	// as indicated by r_icache_miss_clack.
1587	// - If no matching coherence request (r_icache_miss_inval)
1588	// switch directory slot to VALID state.
1589	// - If matching coherence request, switch directory slot
1590	// to ZOMBI state, and send a cleanup request.
1591	{
1592	if ( m_ireq.valid ) m_cost_ins_miss_frz++;
1593
1594	// coherence interrupt
1595	if ( r_cc_receive_icache_req.read() )
1596	{
1597	r_icache_fsm = ICACHE_CC_CHECK;
1598	r_icache_fsm_save = r_icache_fsm.read();
1599	break;
1600	}
1601
1602	if ( not r_icache_miss_clack.read() ) // waiting cleanup acknowledge for victim line
1603	{
1604	if ( r_icache_miss_inval ) // Switch slot to ZOMBI state, and new cleanup
1605	{
1606	if ( not r_icache_cc_send_req.read() )
1607	{
1608	r_icache_miss_inval = false;
1609	// request cleanup
1610	r_icache_cc_send_req = true;
1611	r_icache_cc_send_nline = r_icache_vci_paddr.read() / (m_icache_words<<2);
1612	r_icache_cc_send_way = r_icache_miss_way.read();
1613	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1614
1615	#ifdef INSTRUMENTATION
1616	m_cpt_icache_dir_write++;
1617	#endif
1618	r_icache.write_dir( r_icache_vci_paddr.read(),
1619	r_icache_miss_way.read(),
1620	r_icache_miss_set.read(),
1621	CACHE_SLOT_STATE_ZOMBI );
1622	#if DEBUG_ICACHE
1623	if ( m_debug_icache_fsm )
1624	{
1625	std::cout << " <PROC " << name()
1626	<< " ICACHE_MISS_DIR_UPDT> Switch cache slot to ZOMBI state"
1627	<< " PADDR = " << std::hex << r_icache_vci_paddr.read()
1628	<< " WAY = " << std::dec << r_icache_miss_way.read()
1629	<< " SET = " << r_icache_miss_set.read() << std::endl;
1630	}
1631	#endif
1632	}
1633	else
1634	break;
1635	}
1636	else // Switch slot to VALID state
1637	{
1638
1639	#ifdef INSTRUMENTATION
1640	m_cpt_icache_dir_write++;
1641	#endif
1642	r_icache.write_dir( r_icache_vci_paddr.read(),
1643	r_icache_miss_way.read(),
1644	r_icache_miss_set.read(),
1645	CACHE_SLOT_STATE_VALID );
1646	#if DEBUG_ICACHE
1647	if ( m_debug_icache_fsm )
1648	{
1649	std::cout << " <PROC " << name()
1650	<< " ICACHE_MISS_DIR_UPDT> Switch cache slot to VALID state"
1651	<< " PADDR = " << std::hex << r_icache_vci_paddr.read()
1652	<< " WAY = " << std::dec << r_icache_miss_way.read()
1653	<< " SET = " << r_icache_miss_set.read() << std::endl;
1654	}
1655	#endif
1656	}
1657
1658	r_icache_fsm = ICACHE_IDLE;
1659	}
1660	break;
1661	}
1662	////////////////////
1663	case ICACHE_UNC_WAIT: // waiting a response to an uncacheable read from VCI_RSP FSM
1664	{
1665	// coherence interrupt
1666	if ( r_cc_receive_icache_req.read() )
1667	{
1668	r_icache_fsm = ICACHE_CC_CHECK;
1669	r_icache_fsm_save = r_icache_fsm.read();
1670	break;
1671	}
1672
1673	if ( r_vci_rsp_ins_error.read() ) // bus error
1674	{
1675	r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS;
1676	r_mmu_ibvar = m_ireq.addr;
1677	r_vci_rsp_ins_error = false;
1678	m_irsp.valid = true;
1679	m_irsp.error = true;
1680	r_icache_fsm = ICACHE_IDLE;
1681	}
1682	else if (r_vci_rsp_fifo_icache.rok() ) // instruction available
1683	{
1684	vci_rsp_fifo_icache_get = true;
1685	r_icache_fsm = ICACHE_IDLE;
1686	if ( m_ireq.valid and
1687	(m_ireq.addr == r_icache_vaddr_save.read()) ) // request unmodified
1688	{
1689	m_irsp.valid = true;
1690	m_irsp.instruction = r_vci_rsp_fifo_icache.read();
1691	}
1692	}
1693	break;
1694	}
1695	/////////////////////
1696	case ICACHE_CC_CHECK: // This state is the entry point of a sub-fsm
1697	// handling coherence requests.
1698	// if there is a matching pending miss, it is
1699	// signaled in the r_icache_miss_inval flip-flop.
1700	// The return state is defined in r_icache_fsm_save.
1701	{
1702	paddr_t paddr = r_cc_receive_icache_nline.read() * m_icache_words * 4;
1703	paddr_t mask = ~((m_icache_words<<2)-1);
1704
1705	if (r_cc_receive_icache_type.read() == CC_TYPE_CLACK)
1706	// We switch the directory slot to EMPTY state
1707	// and reset r_icache_miss_clack if the cleanup ack
1708	// is matching a pending miss
1709	{
1710
1711	if ( m_ireq.valid ) m_cost_ins_miss_frz++;
1712
1713	#ifdef INSTRUMENTATION
1714	m_cpt_icache_dir_write++;
1715	#endif
1716	r_icache.write_dir( 0,
1717	r_cc_receive_icache_way.read(),
1718	r_cc_receive_icache_set.read(),
1719	CACHE_SLOT_STATE_EMPTY);
1720
1721	if ( (r_icache_miss_set.read() == r_cc_receive_icache_set.read()) and
1722	(r_icache_miss_way.read() == r_cc_receive_icache_way.read()) )
1723	r_icache_miss_clack = false;
1724
1725	r_icache_fsm = r_icache_fsm_save.read() ;
1726	r_cc_receive_icache_req = false;
1727
1728	#if DEBUG_ICACHE
1729	if ( m_debug_icache_fsm )
1730	{
1731	std::cout << " <PROC " << name()
1732	<< " ICACHE_CC_CHECK> CC_TYPE_CLACK slot returns to empty state"
1733	<< " set = " << r_cc_receive_icache_set.read()
1734	<< " / way = " << r_cc_receive_icache_way.read() << std::endl;
1735	}
1736	#endif
1737	}
1738	else if( ((r_icache_fsm_save.read() == ICACHE_MISS_WAIT) or
1739	(r_icache_fsm_save.read() == ICACHE_MISS_DIR_UPDT)) and
1740	((r_icache_vci_paddr.read() & mask) == (paddr & mask)) ) // matching
1741	{
1742	// signaling the matching
1743	r_icache_miss_inval = true;
1744
1745	// in case of update, go to CC_UPDT
1746	// JUST TO POP THE FIFO
1747	if (r_cc_receive_icache_type.read() == CC_TYPE_UPDT)
1748	{
1749	r_icache_fsm = ICACHE_CC_UPDT;
1750	r_icache_cc_word = r_cc_receive_word_idx.read();
1751	// just pop the fifo , don't write in icache
1752	r_icache_cc_need_write = false;
1753	}
1754	// the request is dealt with
1755	else
1756	{
1757	r_cc_receive_icache_req = false;
1758	r_icache_fsm = r_icache_fsm_save.read();
1759	}
1760	#if DEBUG_ICACHE
1761	if ( m_debug_icache_fsm )
1762	{
1763	std::cout << " <PROC " << name()
1764	<< " ICACHE_CC_CHECK> Coherence request matching a pending miss:"
1765	<< " PADDR = " << std::hex << paddr << std::endl;
1766	}
1767	#endif
1768	}
1769	else // no match
1770	{
1771	int state;
1772	size_t way;
1773	size_t set;
1774	size_t word;
1775
1776	#ifdef INSTRUMENTATION
1777	m_cpt_icache_dir_read++;
1778	#endif
1779	r_icache.read_dir(paddr,
1780	&state,
1781	&way,
1782	&set,
1783	&word);
1784
1785	r_icache_cc_way = way;
1786	r_icache_cc_set = set;
1787
1788	if ( state == CACHE_SLOT_STATE_VALID) // hit
1789	{
1790	// need to update the cache state
1791	r_icache_cc_need_write = true;
1792	if (r_cc_receive_icache_type.read() == CC_TYPE_UPDT) // hit update
1793	{
1794	r_icache_fsm = ICACHE_CC_UPDT;
1795	r_icache_cc_word = r_cc_receive_word_idx.read();
1796	}
1797	else if (r_cc_receive_icache_type.read() == CC_TYPE_INVAL) // hit inval
1798	{
1799	r_icache_fsm = ICACHE_CC_INVAL;
1800	}
1801	else if (r_cc_receive_icache_type.read() == CC_TYPE_BRDCAST) // hit broadcast
1802	{
1803	r_icache_fsm = ICACHE_CC_BROADCAST;
1804	}
1805	}
1806	else // miss
1807	{
1808	// multicast acknowledgement required in case of update
1809	if(r_cc_receive_icache_type.read() == CC_TYPE_UPDT)
1810	{
1811	r_icache_fsm = ICACHE_CC_UPDT;
1812	r_icache_cc_word = r_cc_receive_word_idx.read();
1813	// just pop the fifo , don't write in icache
1814	r_icache_cc_need_write = false;
1815	}
1816	else // No response needed
1817	{
1818	r_cc_receive_icache_req = false;
1819	r_icache_fsm = r_icache_fsm_save.read();
1820	}
1821	}
1822	}
1823	break;
1824	}
1825	/////////////////////
1826	case ICACHE_CC_INVAL: // hit inval : switch slot to EMPTY state
1827	{
1828
1829	#if DEBUG_ICACHE
1830	if ( m_debug_icache_fsm )
1831	{
1832	std::cout << " <PROC " << name()
1833	<< " ICACHE_CC_INVAL> slot returns to empty state"
1834	<< " set = " << r_icache_cc_set.read()
1835	<< " / way = " << r_icache_cc_way.read() << std::endl;
1836	}
1837	#endif
1838
1839	#ifdef INSTRUMENTATION
1840	m_cpt_icache_dir_read++;
1841	#endif
1842	if (r_icache_cc_need_write.read())
1843	{
1844	r_icache.write_dir( 0,
1845	r_icache_cc_way.read(),
1846	r_icache_cc_set.read(),
1847	CACHE_SLOT_STATE_EMPTY );
1848	// no need to write in the cache anymore
1849	r_icache_cc_need_write = false;
1850	}
1851
1852	// multicast acknowledgement
1853	// send a request to cc_send_fsm
1854	if(not r_icache_cc_send_req.read()) // cc_send is available
1855	{
1856	// coherence request completed
1857	r_cc_receive_icache_req = false;
1858	// request multicast acknowledgement
1859	r_icache_cc_send_req = true;
1860	r_icache_cc_send_updt_tab_idx = r_cc_receive_icache_updt_tab_idx.read();
1861	r_icache_cc_send_type = CC_TYPE_MULTI_ACK;
1862
1863	r_icache_fsm = r_icache_fsm_save.read();
1864	}
1865	//else wait for previous cc_send request to be sent
1866	break;
1867	}
1868	////////////////////
1869	case ICACHE_CC_UPDT: // hit update : write one word per cycle
1870	{
1871
1872	#if DEBUG_ICACHE
1873	if ( m_debug_icache_fsm )
1874	{
1875	std::cout << " <PROC " << name()
1876	<< " ICACHE_CC_UPDT> Write one word "
1877	<< " set = " << r_icache_cc_set.read()
1878	<< " / way = " << r_icache_cc_way.read()
1879	<< " / word = " << r_icache_cc_word.read() << std::endl;
1880	}
1881	#endif
1882
1883	#ifdef INSTRUMENTATION
1884	m_cpt_icache_data_write++;
1885	#endif
1886	size_t word = r_icache_cc_word.read();
1887	size_t way = r_icache_cc_way.read();
1888	size_t set = r_icache_cc_set.read();
1889
1890	if (r_cc_receive_updt_fifo_be.rok())
1891	{
1892	if (r_icache_cc_need_write.read())
1893	{
1894	r_icache.write( way,
1895	set,
1896	word,
1897	r_cc_receive_updt_fifo_data.read(),
1898	r_cc_receive_updt_fifo_be.read() );
1899
1900	r_icache_cc_word = word+1;
1901	}
1902	if ( r_cc_receive_updt_fifo_eop.read() ) // last word
1903	{
1904	// no need to write in the cache anymore
1905	r_icache_cc_need_write = false;
1906	// wait to send a request to cc_send_fsm
1907	if(not r_icache_cc_send_req.read()) // cc_send is available
1908	{
1909	//consume last flit
1910	cc_receive_updt_fifo_get = true;
1911	// coherence request completed
1912	r_cc_receive_icache_req = false;
1913	// request multicast acknowledgement
1914	r_icache_cc_send_req = true;
1915	r_icache_cc_send_updt_tab_idx = r_cc_receive_icache_updt_tab_idx.read();
1916	r_icache_cc_send_type = CC_TYPE_MULTI_ACK;
1917
1918	r_icache_fsm = r_icache_fsm_save.read();
1919	}
1920	}
1921	else
1922	{
1923	//consume fifo if not eop
1924	cc_receive_updt_fifo_get = true;
1925	}
1926	}
1927	break;
1928	}
1929	/////////////////////////
1930	case ICACHE_CC_BROADCAST: // hit broadcast : switch slot to ZOMBI state
1931	// and request a cleanup
1932	{
1933
1934	#if DEBUG_ICACHE
1935	if ( m_debug_icache_fsm )
1936	{
1937	std::cout << " <PROC " << name()
1938	<< " ICACHE_CC_BROADCAST > Slot goes to zombi state "
1939	<< " set = " << r_icache_cc_set.read()
1940	<< " / way = " << r_icache_cc_way.read() << std::endl;
1941	}
1942	#endif
1943
1944	#ifdef INSTRUMENTATION
1945	m_cpt_icache_dir_write++;
1946	#endif
1947	if (r_icache_cc_need_write.read())
1948	{
1949	r_icache.write_dir( 0,
1950	r_icache_cc_way.read(),
1951	r_icache_cc_set.read(),
1952	CACHE_SLOT_STATE_ZOMBI );
1953	// no need to write in the cache anymore
1954	r_icache_cc_need_write = false;
1955	}
1956
1957	// cleanup
1958	// send a request to cc_send_fsm
1959	if(not r_icache_cc_send_req.read()) // cc_send is available
1960	{
1961	// coherence request completed
1962	r_cc_receive_icache_req = false;
1963	// request cleanup
1964	r_icache_cc_send_req = true;
1965	r_icache_cc_send_nline = r_cc_receive_icache_nline.read();
1966	r_icache_cc_send_way = r_icache_cc_way.read();
1967	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1968
1969	r_icache_fsm = r_icache_fsm_save.read();
1970	}
1971	//else wait for previous cc_send request to be sent
1972	break;
1973	}
1974	} // end switch r_icache_fsm
1975
1976	////////////////////////////////////////////////////////////////////////////////////
1977	// DCACHE FSM
1978	//
1979	// 1/ Coherence operations
1980	// They are handled as interrupts generated by the CC_RECEIVE FSM.
1981	// - There is a coherence request when r_tgt_dcache_req is set.
1982	// They are taken in IDLE, MISS_WAIT, MISS_DIR_UPDT, UNC_WAIT, LL_WAIT
1983	// and SC_WAIT states.
1984	// - There is a cleanup acknowledge request when r_cleanup_dcache_req is set.
1985	// They are taken in IDLE, MISS_SELECT, MISS_CLEAN, MISS_WAIT, MISS_DATA_UPDT,
1986	// MISS_DIR_UPDT, UNC_WAIT, LL_WAIT, SC_WAIT states.
1987	// - For both types of requests, actions associated to the pre-empted state
1988	// are not executed. The DCACHE FSM goes to the proper sub-FSM (CC_CHECK
1989	// or CC_CLACK) to execute the requested coherence operation, and returns
1990	// to the pre-empted state.
1991	//
1992	// 2/ TLB miss
1993	// The page tables are generally cacheable.
1994	// In case of miss in itlb or dtlb, the tlb miss is handled by a dedicated
1995	// sub-fsm (DCACHE_TLB_MISS state), that handle possible miss in DCACHE,
1996	// this sub-fsm implement the table-walk...
1997	//
1998	// 3/ processor requests
1999	// Processor requests are taken in IDLE state only.
2000	// The IDLE state implements a two stages pipe-line to handle write bursts:
2001	// - Both DTLB and DCACHE are accessed in stage P0 (if processor request valid).
2002	// - The registration in wbuf and the dcache update is done in stage P1
2003	// (if the processor request is a write).
2004	// The two r_dcache_wbuf_req and r_dcache_updt_req flip-flops define
2005	// the operations that must be done in P1 stage, and the access type
2006	// (read or write) to the DATA part of DCACHE depends on r_dcache_updt_req.
2007	// READ requests are delayed if a cache update is requested.
2008	// WRITE or SC requests can require a PTE Dirty bit update (in memory),
2009	// that is done (before handling the processor request) by a dedicated sub-fsm.
2010	// If a PTE is modified, both the itlb and dtlb are selectively, but sequencially
2011	// cleared by a dedicated sub_fsm (DCACHE_INVAL_TLB_SCAN state).
2012	//
2013	// 4/ Atomic instructions LL/SC
2014	// The LL/SC address are non cacheable (systematic access to memory).
2015	// The llsc buffer contains a registration for an active LL/SC operation
2016	// (with an address, a registration key, an aging counter and a valid bit).
2017	// - LL requests from the processor are transmitted as a one flit VCI command
2018	// (CMD_LOCKED_READ as CMD, and TYPE_LL as PKTID value). PLEN must
2019	// be 8 as the response is 2 flits long (data and registration key)
2020	// - SC requests from the processor are systematically transmitted to the
2021	// memory cache as 2 flits VCI command (CMD_STORE_COND as CMD, and TYPE_SC
2022	// as PKTID value). The first flit contains the registration key, the second
2023	// flit contains the data to write in case of success.
2024	// The cache is not updated, as this is done in case of success by the
2025	// coherence transaction.
2026	//
2027	// 5/ Non cacheable access:
2028	// This component implement a strong order between non cacheable access
2029	// (read or write) : A new non cacheable VCI transaction starts only when
2030	// the previous non cacheable transaction is completed. Both cacheable and
2031	// non cacheable transactions use the write buffer, but the DCACHE FSM registers
2032	// a non cacheable write transaction posted in the write buffer by setting the
2033	// r_dcache_pending_unc_write flip_flop. All other non cacheable requests
2034	// are stalled until this flip-flop is reset by the VCI_RSP_FSM (when the
2035	// pending non cacheable write transaction completes).
2036	//
2037	// 6/ Error handling:
2038	// When the MMU is not activated, Read Bus Errors are synchronous events,
2039	// but Write Bus Errors are asynchronous events (processor is not frozen).
2040	// - If a Read Bus Error is detected, the VCI_RSP FSM sets the
2041	// r_vci_rsp_data_error flip-flop, without writing any data in the
2042	// r_vci_rsp_fifo_dcache FIFO, and the synchronous error is signaled
2043	// by the DCACHE FSM.
2044	// - If a Write Bus Error is detected, the VCI_RSP FSM signals
2045	// the asynchronous error using the setWriteBerr() method.
2046	// When the MMU is activated bus error are rare events, as the MMU
2047	// checks the physical address before the VCI transaction starts.
2048	////////////////////////////////////////////////////////////////////////////////////////
2049
2050	// default value for m_drsp
2051	m_drsp.valid = false;
2052	m_drsp.error = false;
2053	m_drsp.rdata = 0;
2054
2055	switch ( r_dcache_fsm.read() )
2056	{
2057	case DCACHE_IDLE: // There are 10 conditions to exit the IDLE state :
2058	// 1) ITLB/DTLB inval request (update) => DCACHE_INVAL_TLB_SCAN
2059	// 2) Coherence request (TGT FSM) => DCACHE_CC_CHECK
2060	// 3) ITLB miss request (ICACHE FSM) => DCACHE_TLB_MISS
2061	// 4) XTN request (processor) => DCACHE_XTN_*
2062	// 5) DTLB miss (processor) => DCACHE_TLB_MISS
2063	// 6) Dirty bit update (processor) => DCACHE_DIRTY_GET_PTE
2064	// 7) Cacheable read miss (processor) => DCACHE_MISS_SELECT
2065	// 8) Uncacheable read (processor) => DCACHE_UNC_WAIT
2066	// 9) LL access (processor) => DCACHE_LL_WAIT
2067	// 10) SC access (processor) => DCACHE_SC_WAIT
2068	//
2069	// There is a fixed priority to handle requests to DCACHE:
2070	// 1/ the ITLB/DTLB invalidate requests
2071	// 2/ the coherence requests,
2072	// 3/ the processor requests (including DTLB miss),
2073	// 4/ the ITLB miss requests,
2074	// The address space processor request are handled as follows:
2075	// - WRITE request is blocked if the Dirty bit mus be set.
2076	// If DTLB hit, the P1 stage is activated (writes WBUF, and
2077	// updates DCACHE if DCACHE hit) & processor request acknowledged.
2078	// - READ request generate a simultaneouss access to DCACHE.DATA
2079	// and DCACHE.DIR, but is delayed if DCACHE update required.
2080	//
2081	// There is 4 configurations defining the access type to
2082	// DTLB, DCACHE.DATA, and DCACHE.DIR, depending on the
2083	// dreq.valid (dreq) and r_dcache_updt_req (updt) signals:
2084	// dreq / updt / DTLB / DCACHE.DIR / DCACHE.DATA /
2085	// 0 / 0 / NOP / NOP / NOP /
2086	// 0 / 1 / NOP / NOP / WRITE /
2087	// 1 / 0 / READ / READ / NOP /
2088	// 1 / 1 / READ / READ / WRITE /
2089	// Those two registers are set at each cycle from the 3 signals
2090	// updt_request, wbuf_request, wbuf_write_miss.
2091	{
2092	paddr_t paddr; // physical address
2093	pte_info_t tlb_flags;
2094	size_t tlb_way;
2095	size_t tlb_set;
2096	paddr_t tlb_nline;
2097	size_t cache_way;
2098	size_t cache_set;
2099	size_t cache_word;
2100	uint32_t cache_rdata = 0;
2101	bool tlb_hit = false;
2102	int cache_state = CACHE_SLOT_STATE_EMPTY;
2103
2104	bool tlb_inval_required = false; // request TLB inval after cache update
2105	bool wbuf_write_miss = false; // miss a WBUF write request
2106	bool updt_request = false; // request DCACHE update in P1 stage
2107	bool wbuf_request = false; // request WBUF write in P1 stage
2108
2109	// physical address computation : systematic DTLB access if activated)
2110	if ( m_dreq.valid )
2111	{
2112	if ( r_mmu_mode.read() & DATA_TLB_MASK ) // DTLB activated
2113	{
2114	tlb_hit = r_dtlb.translate( m_dreq.addr,
2115	&paddr,
2116	&tlb_flags,
2117	&tlb_nline,
2118	&tlb_way,
2119	&tlb_set );
2120	#ifdef INSTRUMENTATION
2121	m_cpt_dtlb_read++;
2122	#endif
2123	}
2124	else // identity mapping
2125	{
2126	paddr = (paddr_t)m_dreq.addr;
2127	}
2128	} // end physical address computation
2129
2130	// systematic DCACHE access depending on r_dcache_updt_req (if activated)
2131	if ( r_mmu_mode.read() & DATA_CACHE_MASK)
2132	{
2133	if ( m_dreq.valid and r_dcache_updt_req.read() ) // read DIR and write DATA
2134	{
2135	r_dcache.read_dir( paddr,
2136	&cache_state,
2137	&cache_way,
2138	&cache_set,
2139	&cache_word );
2140
2141	r_dcache.write( r_dcache_save_cache_way.read(),
2142	r_dcache_save_cache_set.read(),
2143	r_dcache_save_cache_word.read(),
2144	r_dcache_save_wdata.read(),
2145	r_dcache_save_be.read() );
2146	#ifdef INSTRUMENTATION
2147	m_cpt_dcache_dir_read++;
2148	m_cpt_dcache_data_write++;
2149	#endif
2150	}
2151	else if ( m_dreq.valid and not r_dcache_updt_req.read() ) // read DIR and DATA
2152	{
2153	r_dcache.read( paddr,
2154	&cache_rdata,
2155	&cache_way,
2156	&cache_set,
2157	&cache_word,
2158	&cache_state );
2159	#ifdef INSTRUMENTATION
2160	m_cpt_dcache_dir_read++;
2161	m_cpt_dcache_data_read++;
2162	#endif
2163	}
2164	else if ( not m_dreq.valid and r_dcache_updt_req.read() ) // write DATA
2165	{
2166	r_dcache.write( r_dcache_save_cache_way.read(),
2167	r_dcache_save_cache_set.read(),
2168	r_dcache_save_cache_word.read(),
2169	r_dcache_save_wdata.read(),
2170	r_dcache_save_be.read() );
2171	#ifdef INSTRUMENTATION
2172	m_cpt_dcache_data_write++;
2173	#endif
2174	}
2175	} // end dcache access
2176
2177	// DCACHE update in P1 stage can require ITLB / DTLB inval or flush
2178	if ( r_dcache_updt_req.read() )
2179	{
2180	size_t way = r_dcache_save_cache_way.read();
2181	size_t set = r_dcache_save_cache_set.read();
2182
2183	if ( r_dcache_in_tlb[way*m_dcache_sets+set] )
2184	{
2185	tlb_inval_required = true;
2186	r_dcache_tlb_inval_set = 0;
2187	r_dcache_tlb_inval_line = r_dcache_save_paddr.read()>>
2188	(uint32_log2(m_dcache_words<<2));
2189	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
2190	}
2191	else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] )
2192	{
2193	r_itlb.reset();
2194	r_dtlb.reset();
2195	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
2196	}
2197
2198	#if DEBUG_DCACHE
2199	if ( m_debug_dcache_fsm )
2200	{
2201	std::cout << " <PROC " << name()
2202	<< " DCACHE_IDLE> Cache update in P1 stage" << std::dec
2203	<< " / WAY = " << r_dcache_save_cache_way.read()
2204	<< " / SET = " << r_dcache_save_cache_set.read()
2205	<< " / WORD = " << r_dcache_save_cache_word.read() << std::hex
2206	<< " / DATA = " << r_dcache_save_wdata.read()
2207	<< " / BE = " << r_dcache_save_be.read() << std::endl;
2208	}
2209	#endif
2210	} // end test TLB inval
2211
2212	// Try WBUF update in P1 stage
2213	// Miss if the write request is non cacheable, and there is a pending
2214	// non cacheable write, or if the write buffer is full.
2215	if ( r_dcache_wbuf_req.read() )
2216	{
2217	// miss if write not cacheable, and previous non cacheable write registered
2218	if ( not r_dcache_save_cacheable.read() and r_dcache_pending_unc_write.read() )
2219	{
2220	wbuf_write_miss = true;
2221	}
2222	else // try a registration into write buffer
2223	{
2224	bool wok = r_wbuf.write( r_dcache_save_paddr.read(),
2225	r_dcache_save_be.read(),
2226	r_dcache_save_wdata.read(),
2227	r_dcache_save_cacheable.read() );
2228	#ifdef INSTRUMENTATION
2229	m_cpt_wbuf_write++;
2230	#endif
2231	if ( not wok ) // miss if write buffer full
2232	{
2233	wbuf_write_miss = true;
2234	}
2235	else // update the write_buffer state extension
2236	{
2237	if(not r_dcache_pending_unc_write.read())
2238	r_dcache_pending_unc_write = not r_dcache_save_cacheable.read();
2239	}
2240	}
2241	} // end WBUF update
2242
2243	// Computing the response to processor,
2244	// and the next value for r_dcache_fsm
2245
2246	// itlb/dtlb invalidation self-request
2247	if ( tlb_inval_required )
2248	{
2249	r_dcache_fsm_scan_save = r_dcache_fsm.read();
2250	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
2251	}
2252
2253	// coherence request (from CC_RECEIVE FSM)
2254	else if ( r_cc_receive_dcache_req.read() )
2255	{
2256	r_dcache_fsm = DCACHE_CC_CHECK;
2257	r_dcache_fsm_cc_save = r_dcache_fsm.read();
2258	}
2259
2260	// processor request (READ, WRITE, LL, SC, XTN_READ, XTN_WRITE)
2261	// we don't take the processor request, and registers
2262	// are frozen in case of wbuf_write_miss
2263	else if ( m_dreq.valid and not wbuf_write_miss )
2264	{
2265	// register processor request and DCACHE response
2266	r_dcache_save_vaddr = m_dreq.addr;
2267	r_dcache_save_be = m_dreq.be;
2268	r_dcache_save_wdata = m_dreq.wdata;
2269	r_dcache_save_paddr = paddr;
2270	r_dcache_save_cache_way = cache_way;
2271	r_dcache_save_cache_set = cache_set;
2272	r_dcache_save_cache_word = cache_word;
2273
2274	// READ XTN requests from processor
2275	// They are executed in this DCACHE_IDLE state.
2276	// The processor must not be in user mode
2277	if (m_dreq.type == iss_t::XTN_READ)
2278	{
2279	int xtn_opcode = (int)m_dreq.addr/4;
2280
2281	// checking processor mode:
2282	if (m_dreq.mode == iss_t::MODE_USER)
2283	{
2284	r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION;
2285	r_mmu_dbvar = m_dreq.addr;
2286	m_drsp.valid = true;
2287	m_drsp.error = true;
2288	m_drsp.rdata = 0;
2289	r_dcache_fsm = DCACHE_IDLE;
2290	}
2291	else
2292	{
2293	switch( xtn_opcode )
2294	{
2295	case iss_t::XTN_INS_ERROR_TYPE:
2296	m_drsp.rdata = r_mmu_ietr.read();
2297	m_drsp.valid = true;
2298	m_drsp.error = false;
2299	break;
2300
2301	case iss_t::XTN_DATA_ERROR_TYPE:
2302	m_drsp.rdata = r_mmu_detr.read();
2303	m_drsp.valid = true;
2304	m_drsp.error = false;
2305	break;
2306
2307	case iss_t::XTN_INS_BAD_VADDR:
2308	m_drsp.rdata = r_mmu_ibvar.read();
2309	m_drsp.valid = true;
2310	m_drsp.error = false;
2311	break;
2312
2313	case iss_t::XTN_DATA_BAD_VADDR:
2314	m_drsp.rdata = r_mmu_dbvar.read();
2315	m_drsp.valid = true;
2316	m_drsp.error = false;
2317	break;
2318
2319	case iss_t::XTN_PTPR:
2320	m_drsp.rdata = r_mmu_ptpr.read();
2321	m_drsp.valid = true;
2322	m_drsp.error = false;
2323	break;
2324
2325	case iss_t::XTN_TLB_MODE:
2326	m_drsp.rdata = r_mmu_mode.read();
2327	m_drsp.valid = true;
2328	m_drsp.error = false;
2329	break;
2330
2331	case iss_t::XTN_MMU_PARAMS:
2332	m_drsp.rdata = r_mmu_params;
2333	m_drsp.valid = true;
2334	m_drsp.error = false;
2335	break;
2336
2337	case iss_t::XTN_MMU_RELEASE:
2338	m_drsp.rdata = r_mmu_release;
2339	m_drsp.valid = true;
2340	m_drsp.error = false;
2341	break;
2342
2343	case iss_t::XTN_MMU_WORD_LO:
2344	m_drsp.rdata = r_mmu_word_lo.read();
2345	m_drsp.valid = true;
2346	m_drsp.error = false;
2347	break;
2348
2349	case iss_t::XTN_MMU_WORD_HI:
2350	m_drsp.rdata = r_mmu_word_hi.read();
2351	m_drsp.valid = true;
2352	m_drsp.error = false;
2353	break;
2354
2355	default:
2356	r_mmu_detr = MMU_READ_UNDEFINED_XTN;
2357	r_mmu_dbvar = m_dreq.addr;
2358	m_drsp.valid = true;
2359	m_drsp.error = true;
2360	m_drsp.rdata = 0;
2361	break;
2362	} // end switch xtn_opcode
2363	} // end else
2364	} // end if XTN_READ
2365
2366	// Handling WRITE XTN requests from processor.
2367	// They are not executed in this DCACHE_IDLE state
2368	// if they require access to the caches or the TLBs
2369	// that are already accessed.
2370	// Caches can be invalidated or flushed in user mode,
2371	// and the sync instruction can be executed in user mode
2372	else if (m_dreq.type == iss_t::XTN_WRITE)
2373	{
2374	int xtn_opcode = (int)m_dreq.addr/4;
2375	r_dcache_xtn_opcode = xtn_opcode;
2376
2377	// checking processor mode:
2378	if ( (m_dreq.mode == iss_t::MODE_USER) &&
2379	(xtn_opcode != iss_t:: XTN_SYNC) &&
2380	(xtn_opcode != iss_t::XTN_DCACHE_INVAL) &&
2381	(xtn_opcode != iss_t::XTN_DCACHE_FLUSH) &&
2382	(xtn_opcode != iss_t::XTN_ICACHE_INVAL) &&
2383	(xtn_opcode != iss_t::XTN_ICACHE_FLUSH) )
2384	{
2385	r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION;
2386	r_mmu_dbvar = m_dreq.addr;
2387	m_drsp.valid = true;
2388	m_drsp.error = true;
2389	m_drsp.rdata = 0;
2390	r_dcache_fsm = DCACHE_IDLE;
2391	}
2392	else
2393	{
2394	switch( xtn_opcode )
2395	{
2396	case iss_t::XTN_PTPR: // itlb & dtlb must be flushed
2397	r_dcache_xtn_req = true;
2398	r_dcache_fsm = DCACHE_XTN_SWITCH;
2399	break;
2400
2401	case iss_t::XTN_TLB_MODE: // no cache or tlb access
2402	r_mmu_mode = m_dreq.wdata;
2403	m_drsp.valid = true;
2404	r_dcache_fsm = DCACHE_IDLE;
2405	break;
2406
2407	case iss_t::XTN_DTLB_INVAL: // dtlb access
2408	r_dcache_fsm = DCACHE_XTN_DT_INVAL;
2409	break;
2410
2411	case iss_t::XTN_ITLB_INVAL: // itlb access
2412	r_dcache_xtn_req = true;
2413	r_dcache_fsm = DCACHE_XTN_IT_INVAL;
2414	break;
2415
2416	case iss_t::XTN_DCACHE_INVAL: // dcache, dtlb & itlb access
2417	r_dcache_fsm = DCACHE_XTN_DC_INVAL_VA;
2418	break;
2419
2420	case iss_t::XTN_MMU_DCACHE_PA_INV: // dcache, dtlb & itlb access
2421	r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA;
2422	if (sizeof(paddr_t) <= 32)
2423	{
2424	assert(r_mmu_word_hi.read() == 0 &&
2425	"high bits should be 0 for 32bit paddr");
2426	r_dcache_save_paddr = (paddr_t)r_mmu_word_lo.read();
2427	}
2428	else
2429	{
2430	r_dcache_save_paddr = (paddr_t)r_mmu_word_hi.read() << 32 \|
2431	(paddr_t)r_mmu_word_lo.read();
2432	}
2433	break;
2434
2435	case iss_t::XTN_DCACHE_FLUSH: // itlb and dtlb must be reset
2436	r_dcache_flush_count = 0;
2437	r_dcache_fsm = DCACHE_XTN_DC_FLUSH;
2438	break;
2439
2440	case iss_t::XTN_ICACHE_INVAL: // icache and itlb access
2441	r_dcache_xtn_req = true;
2442	r_dcache_fsm = DCACHE_XTN_IC_INVAL_VA;
2443	break;
2444
2445	case iss_t::XTN_MMU_ICACHE_PA_INV: // icache access
2446	r_dcache_xtn_req = true;
2447	r_dcache_fsm = DCACHE_XTN_IC_INVAL_PA;
2448	break;
2449
2450	case iss_t::XTN_ICACHE_FLUSH: // icache access
2451	r_dcache_xtn_req = true;
2452	r_dcache_fsm = DCACHE_XTN_IC_FLUSH;
2453	break;
2454
2455	case iss_t::XTN_SYNC: // wait until write buffer empty
2456	r_dcache_fsm = DCACHE_XTN_SYNC;
2457	break;
2458
2459	case iss_t::XTN_MMU_WORD_LO: // no cache or tlb access
2460	r_mmu_word_lo = m_dreq.wdata;
2461	m_drsp.valid = true;
2462	r_dcache_fsm = DCACHE_IDLE;
2463	break;
2464
2465	case iss_t::XTN_MMU_WORD_HI: // no cache or tlb access
2466	r_mmu_word_hi = m_dreq.wdata;
2467	m_drsp.valid = true;
2468	r_dcache_fsm = DCACHE_IDLE;
2469	break;
2470
2471	case iss_t::XTN_MMU_LL_RESET: // no cache or tlb access
2472	r_dcache_llsc_valid = false;
2473	m_drsp.valid = true;
2474	r_dcache_fsm = DCACHE_IDLE;
2475	break;
2476
2477	case iss_t::XTN_ICACHE_PREFETCH: // not implemented : no action
2478	case iss_t::XTN_DCACHE_PREFETCH: // not implemented : no action
2479	m_drsp.valid = true;
2480	r_dcache_fsm = DCACHE_IDLE;
2481	break;
2482
2483	default:
2484	r_mmu_detr = MMU_WRITE_UNDEFINED_XTN;
2485	r_mmu_dbvar = m_dreq.addr;
2486	m_drsp.valid = true;
2487	m_drsp.error = true;
2488	r_dcache_fsm = DCACHE_IDLE;
2489	break;
2490	} // end switch xtn_opcode
2491	} // end else
2492	} // end if XTN_WRITE
2493
2494	// Handling processor requests to address space (READ/WRITE/LL/SC)
2495	// The dtlb and dcache can be activated or not.
2496	// We compute the cacheability, and check processor request validity:
2497	// - If DTLB not activated : cacheability is defined by the segment table,
2498	// and there is no access rights checking.
2499	// - If DTLB activated : cacheability is defined by the C bit in the PTE,
2500	// and the U & W bits of the PTE are checked, as well as the DTLB hit.
2501	// Jumps to the TLB_MISS sub-fsm in case of dtlb miss.
2502	else
2503	{
2504	bool valid_req;
2505	bool cacheable;
2506
2507	if ( not (r_mmu_mode.read() & DATA_TLB_MASK) ) // dtlb not activated
2508	{
2509	valid_req = true;
2510
2511	if ( not (r_mmu_mode.read() & DATA_CACHE_MASK) ) cacheable = false;
2512	else cacheable = m_cacheability_table[m_dreq.addr];
2513	}
2514	else // dtlb activated
2515	{
2516	if ( tlb_hit ) // tlb hit
2517	{
2518	// cacheability
2519	if ( not (r_mmu_mode.read() & DATA_CACHE_MASK) ) cacheable = false;
2520	else cacheable = tlb_flags.c;
2521
2522	// access rights checking
2523	if ( not tlb_flags.u and (m_dreq.mode == iss_t::MODE_USER))
2524	{
2525	if ( (m_dreq.type == iss_t::DATA_READ) or
2526	(m_dreq.type == iss_t::DATA_LL) )
2527	{
2528	r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION;
2529	}
2530	else
2531	{
2532	r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION;
2533	}
2534	valid_req = false;
2535	r_mmu_dbvar = m_dreq.addr;
2536	m_drsp.valid = true;
2537	m_drsp.error = true;
2538	m_drsp.rdata = 0;
2539	#if DEBUG_DCACHE
2540	if ( m_debug_dcache_fsm )
2541	{
2542	std::cout << " <PROC " << name()
2543	<< ".DCACHE_IDLE> HIT in dtlb, but privilege violation" << std::endl;
2544	}
2545	#endif
2546	}
2547	else if ( not tlb_flags.w and
2548	((m_dreq.type == iss_t::DATA_WRITE) or
2549	(m_dreq.type == iss_t::DATA_SC)) )
2550	{
2551	r_mmu_detr = MMU_WRITE_ACCES_VIOLATION;
2552	valid_req = false;
2553	r_mmu_dbvar = m_dreq.addr;
2554	m_drsp.valid = true;
2555	m_drsp.error = true;
2556	m_drsp.rdata = 0;
2557	#if DEBUG_DCACHE
2558	if ( m_debug_dcache_fsm )
2559	{
2560	std::cout << " <PROC " << name()
2561	<< ".DCACHE_IDLE> HIT in dtlb, but writable violation" << std::endl;
2562	}
2563	#endif
2564	}
2565	else
2566	{
2567	valid_req = true;
2568	}
2569	}
2570	else // tlb miss
2571	{
2572	valid_req = false;
2573	r_dcache_tlb_vaddr = m_dreq.addr;
2574	r_dcache_tlb_ins = false;
2575	r_dcache_fsm = DCACHE_TLB_MISS;
2576	}
2577	} // end DTLB activated
2578
2579	if ( valid_req ) // processor request is valid after TLB check
2580	{
2581	r_dcache_save_cacheable = cacheable;
2582
2583	// READ request
2584	// The read requests are taken only if there is no cache update.
2585	// We request a VCI transaction to CMD FSM if miss or uncachable
2586	if ( ((m_dreq.type == iss_t::DATA_READ))
2587	and not r_dcache_updt_req.read() )
2588	{
2589	if ( cacheable ) // cacheable read
2590	{
2591	if ( cache_state == CACHE_SLOT_STATE_EMPTY ) // cache miss
2592	{
2593	#ifdef INSTRUMENTATION
2594	m_cpt_dcache_miss++;
2595	#endif
2596	// request a VCI DMISS transaction
2597	r_dcache_vci_paddr = paddr;
2598	r_dcache_vci_miss_req = true;
2599	r_dcache_miss_type = PROC_MISS;
2600	r_dcache_fsm = DCACHE_MISS_SELECT;
2601	#if DEBUG_DCACHE
2602	if ( m_debug_dcache_fsm )
2603	{
2604	std::cout << " <PROC " << name()
2605	<< ".DCACHE_IDLE> READ MISS in dcache" << std::endl;
2606	}
2607	#endif
2608	}
2609	else if (cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup
2610	{
2611	// stalled until cleanup is acknowledged
2612	r_dcache_fsm = DCACHE_IDLE;
2613	}
2614	else // cache hit
2615	{
2616	#ifdef INSTRUMENTATION
2617	m_cpt_data_read++;
2618	#endif
2619	// returns data to processor
2620	m_drsp.valid = true;
2621	m_drsp.error = false;
2622	m_drsp.rdata = cache_rdata;
2623	#if DEBUG_DCACHE
2624	if ( m_debug_dcache_fsm )
2625	{
2626	std::cout << " <PROC " << name()
2627	<< ".DCACHE_IDLE> READ HIT in dcache" << std::endl;
2628	}
2629	#endif
2630	}
2631	}
2632	else // uncacheable read
2633	{
2634	r_dcache_vci_paddr = paddr;
2635	r_dcache_vci_unc_be = m_dreq.be;
2636	r_dcache_vci_unc_req = true;
2637	r_dcache_fsm = DCACHE_UNC_WAIT;
2638	#if DEBUG_DCACHE
2639	if ( m_debug_dcache_fsm )
2640	{
2641	std::cout << " <PROC " << name()
2642	<< ".DCACHE_IDLE> READ UNCACHEABLE in dcache" << std::endl;
2643	}
2644	#endif
2645	}
2646	} // end READ
2647
2648	// LL request (non cachable)
2649	// We request a VCI LL transaction to CMD FSM and register
2650	// the LL/SC operation in llsc buffer.
2651	else if (m_dreq.type == iss_t::DATA_LL)
2652	{
2653	// register paddr in LLSC buffer
2654	r_dcache_llsc_paddr = paddr;
2655	r_dcache_llsc_count = LLSC_TIMEOUT;
2656	r_dcache_llsc_valid = true;
2657
2658	// request an LL VCI transaction and go to DCACHE_LL_WAIT state
2659	r_dcache_vci_ll_req = true;
2660	r_dcache_vci_paddr = paddr;
2661	r_dcache_ll_rsp_count = 0;
2662	r_dcache_fsm = DCACHE_LL_WAIT;
2663
2664	}// end LL
2665
2666	// WRITE request:
2667	// If the TLB is activated and the PTE Dirty bit is not set, we stall
2668	// the processor and set the Dirty bit before handling the write request,
2669	// going to the DCACHE_DIRTY_GT_PTE state.
2670	// If we don't need to set the Dirty bit, we can acknowledge
2671	// the processor request, as the write arguments (including the
2672	// physical address) are registered in r_dcache_save registers,
2673	// and the write will be done in the P1 pipeline stage.
2674	else if ( m_dreq.type == iss_t::DATA_WRITE )
2675	{
2676	if ( (r_mmu_mode.read() & DATA_TLB_MASK )
2677	and not tlb_flags.d ) // Dirty bit must be set
2678	{
2679	// The PTE physical address is obtained from the nline value (dtlb),
2680	// and from the virtual address (word index)
2681	if ( tlb_flags.b ) // PTE1
2682	{
2683	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2684	(paddr_t)((m_dreq.addr>>19) & 0x3c);
2685	}
2686	else // PTE2
2687	{
2688	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2689	(paddr_t)((m_dreq.addr>>9) & 0x38);
2690	}
2691	r_dcache_fsm = DCACHE_DIRTY_GET_PTE;
2692	}
2693	else // Write request accepted
2694	{
2695	#ifdef INSTRUMENTATION
2696	m_cpt_data_write++;
2697	#endif
2698	// cleaning llsc buffer if address matching
2699	if ( paddr == r_dcache_llsc_paddr.read() )
2700	r_dcache_llsc_valid = false;
2701
2702	// response to processor
2703	m_drsp.valid = true;
2704
2705	// activating P1 stage
2706	wbuf_request = true;
2707	updt_request = (cache_state == CACHE_SLOT_STATE_VALID);
2708	}
2709	} // end WRITE
2710
2711	// SC request:
2712	// If the TLB is activated and the PTE Dirty bit is not set, we stall
2713	// the processor and set the Dirty bit before handling the write request,
2714	// going to the DCACHE_DIRTY_GT_PTE state.
2715	// If we don't need to set the Dirty bit, we test the llsc buffer:
2716	// If failure, we send a negative response to processor.
2717	// If success, we request a SC transaction to CMD FSM and go
2718	// to DCACHE_SC_WAIT state.
2719	// We don't check a possible write hit in dcache, as the cache update
2720	// is done by the coherence transaction induced by the SC...
2721	else if ( m_dreq.type == iss_t::DATA_SC )
2722	{
2723	if ( (r_mmu_mode.read() & DATA_TLB_MASK )
2724	and not tlb_flags.d ) // Dirty bit must be set
2725	{
2726	// The PTE physical address is obtained from the nline value (dtlb),
2727	// and the word index (virtual address)
2728	if ( tlb_flags.b ) // PTE1
2729	{
2730	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2731	(paddr_t)((m_dreq.addr>>19) & 0x3c);
2732	}
2733	else // PTE2
2734	{
2735	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2736	(paddr_t)((m_dreq.addr>>9) & 0x38);
2737	}
2738	r_dcache_fsm = DCACHE_DIRTY_GET_PTE;
2739	m_drsp.valid = false;
2740	m_drsp.error = false;
2741	m_drsp.rdata = 0;
2742	}
2743	else // SC request accepted
2744	{
2745	#ifdef INSTRUMENTATION
2746	m_cpt_data_sc++;
2747	#endif
2748	// checking local success
2749	if( r_dcache_llsc_valid.read() and
2750	(r_dcache_llsc_paddr.read() == paddr) ) // local success
2751	{
2752	// request an SC CMD and go to DCACHE_SC_WAIT state
2753	r_dcache_vci_paddr = paddr;
2754	r_dcache_vci_sc_req = true;
2755	r_dcache_vci_sc_data = m_dreq.wdata;
2756	r_dcache_fsm = DCACHE_SC_WAIT;
2757	}
2758	else // local fail
2759	{
2760	m_drsp.valid = true;
2761	m_drsp.error = false;
2762	m_drsp.rdata = 0x1;
2763	}
2764	}
2765	} // end SC
2766	} // end valid_req
2767	} // end if read/write/ll/sc request
2768	} // end processor request
2769
2770	// itlb miss request
2771	else if ( r_icache_tlb_miss_req.read() and not wbuf_write_miss )
2772	{
2773	r_dcache_tlb_ins = true;
2774	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
2775	r_dcache_fsm = DCACHE_TLB_MISS;
2776	}
2777
2778	// Computing requests for P1 stage : r_dcache_wbuf_req & r_dcache_updt_req
2779	r_dcache_updt_req = updt_request;
2780	r_dcache_wbuf_req = wbuf_request or
2781	(r_dcache_wbuf_req.read() and wbuf_write_miss);
2782	break;
2783	}
2784	/////////////////////
2785	case DCACHE_TLB_MISS: // This is the entry point for the sub-fsm handling all tlb miss.
2786	// Input arguments are:
2787	// - r_dcache_tlb_vaddr
2788	// - r_dcache_tlb_ins (true when itlb miss)
2789	// The sub-fsm access the dcache to find the missing TLB entry,
2790	// and activates the cache miss procedure in case of miss.
2791	// It bypass the first level page table access if possible.
2792	// It uses atomic access to update the R/L access bits
2793	// in the page table if required.
2794	// It directly updates the itlb or dtlb, and writes into the
2795	// r_mmu_ins_* or r_mmu_data* error reporting registers.
2796	{
2797	uint32_t ptba = 0;
2798	bool bypass;
2799	paddr_t pte_paddr;
2800
2801	// evaluate bypass in order to skip first level page table access
2802	if ( r_dcache_tlb_ins.read() ) // itlb miss
2803	{
2804	bypass = r_itlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba);
2805	}
2806	else // dtlb miss
2807	{
2808	bypass = r_dtlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba);
2809	}
2810
2811	if ( not bypass ) // Try to read PTE1/PTD1 in dcache
2812	{
2813	pte_paddr = (paddr_t)r_mmu_ptpr.read() << (INDEX1_NBITS+2) \|
2814	(paddr_t)((r_dcache_tlb_vaddr.read() >> PAGE_M_NBITS) << 2);
2815	r_dcache_tlb_paddr = pte_paddr;
2816	r_dcache_fsm = DCACHE_TLB_PTE1_GET;
2817	}
2818	else // Try to read PTE2 in dcache
2819	{
2820	pte_paddr = (paddr_t)ptba << PAGE_K_NBITS \|
2821	(paddr_t)(r_dcache_tlb_vaddr.read()&PTD_ID2_MASK)>>(PAGE_K_NBITS-3);
2822	r_dcache_tlb_paddr = pte_paddr;
2823	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
2824	}
2825
2826	#if DEBUG_DCACHE
2827	if ( m_debug_dcache_fsm )
2828	{
2829	if ( r_dcache_tlb_ins.read() )
2830	{
2831	std::cout << " <PROC " << name() << ".DCACHE_TLB_MISS> ITLB miss";
2832	}
2833	else
2834	{
2835	std::cout << " <PROC " << name() << ".DCACHE_TLB_MISS> DTLB miss";
2836	}
2837	std::cout << " / VADDR = " << std::hex << r_dcache_tlb_vaddr.read()
2838	<< " / BYPASS = " << bypass
2839	<< " / PTE_ADR = " << pte_paddr << std::endl;
2840	}
2841	#endif
2842
2843	break;
2844	}
2845	/////////////////////////
2846	case DCACHE_TLB_PTE1_GET: // try to read a PT1 entry in dcache
2847	{
2848	// coherence request (from CC_RECEIVE FSM)
2849	if ( r_cc_receive_dcache_req.read() )
2850	{
2851	r_dcache_fsm = DCACHE_CC_CHECK;
2852	r_dcache_fsm_cc_save = r_dcache_fsm.read();
2853	break;
2854	}
2855
2856	uint32_t entry;
2857	size_t way;
2858	size_t set;
2859	size_t word;
2860	int cache_state;
2861	r_dcache.read( r_dcache_tlb_paddr.read(),
2862	&entry,
2863	&way,
2864	&set,
2865	&word,
2866	&cache_state );
2867	#ifdef INSTRUMENTATION
2868	m_cpt_dcache_data_read++;
2869	m_cpt_dcache_dir_read++;
2870	#endif
2871	if ( cache_state == CACHE_SLOT_STATE_VALID ) // hit in dcache
2872	{
2873	if ( not (entry & PTE_V_MASK) ) // unmapped
2874	{
2875	if ( r_dcache_tlb_ins.read() )
2876	{
2877	r_mmu_ietr = MMU_READ_PT1_UNMAPPED;
2878	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
2879	r_icache_tlb_miss_req = false;
2880	r_icache_tlb_rsp_error = true;
2881	}
2882	else
2883	{
2884	r_mmu_detr = MMU_READ_PT1_UNMAPPED;
2885	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
2886	m_drsp.valid = true;
2887	m_drsp.error = true;
2888	}
2889	r_dcache_fsm = DCACHE_IDLE;
2890
2891	#if DEBUG_DCACHE
2892	if ( m_debug_dcache_fsm )
2893	{
2894	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_GET> HIT in dcache, but unmapped"
2895	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
2896	<< std::dec << " / way = " << way
2897	<< std::dec << " / set = " << set
2898	<< std::dec << " / word = " << word
2899	<< std::hex << " / PTE1 = " << entry << std::endl;
2900	}
2901	#endif
2902
2903	}
2904	else if( entry & PTE_T_MASK ) // PTD : me must access PT2
2905	{
2906	// mark the cache line ac containing a PTD
2907	r_dcache_contains_ptd[m_dcache_sets*way+set] = true;
2908
2909	// register bypass
2910	if ( r_dcache_tlb_ins.read() ) // itlb
2911	{
2912	r_itlb.set_bypass(r_dcache_tlb_vaddr.read(),
2913	entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1),
2914	r_dcache_tlb_paddr.read() / (m_icache_words<<2) );
2915	}
2916	else // dtlb
2917	{
2918	r_dtlb.set_bypass(r_dcache_tlb_vaddr.read(),
2919	entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1),
2920	r_dcache_tlb_paddr.read() / (m_dcache_words<<2) );
2921	}
2922	r_dcache_tlb_paddr =
2923	(paddr_t)(entry & ((1<<(m_paddr_nbits-PAGE_K_NBITS))-1)) << PAGE_K_NBITS \|
2924	(paddr_t)(((r_dcache_tlb_vaddr.read() & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3);
2925	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
2926
2927	#if DEBUG_DCACHE
2928	if ( m_debug_dcache_fsm )
2929	{
2930	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_GET> HIT in dcache"
2931	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
2932	<< std::dec << " / way = " << way
2933	<< std::dec << " / set = " << set
2934	<< std::dec << " / word = " << word
2935	<< std::hex << " / PTD = " << entry << std::endl;
2936	}
2937	#endif
2938	}
2939	else // PTE1 : we must update the TLB
2940	{
2941	r_dcache_in_tlb[m_icache_sets*way+set] = true;
2942	r_dcache_tlb_pte_flags = entry;
2943	r_dcache_tlb_cache_way = way;
2944	r_dcache_tlb_cache_set = set;
2945	r_dcache_tlb_cache_word = word;
2946	r_dcache_fsm = DCACHE_TLB_PTE1_SELECT;
2947
2948	#if DEBUG_DCACHE
2949	if ( m_debug_dcache_fsm )
2950	{
2951	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_GET> HIT in dcache"
2952	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
2953	<< std::dec << " / way = " << way
2954	<< std::dec << " / set = " << set
2955	<< std::dec << " / word = " << word
2956	<< std::hex << " / PTE1 = " << entry << std::endl;
2957	}
2958	#endif
2959	}
2960	}
2961	else if ( cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup
2962	{
2963	// stalled until cleanup is acknowledged
2964	r_dcache_fsm = DCACHE_TLB_PTE1_GET;
2965	}
2966	else // we must load the missing cache line in dcache
2967	{
2968	r_dcache_vci_miss_req = true;
2969	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
2970	r_dcache_save_paddr = r_dcache_tlb_paddr.read();
2971	r_dcache_miss_type = PTE1_MISS;
2972	r_dcache_fsm = DCACHE_MISS_SELECT;
2973
2974	#if DEBUG_DCACHE
2975	if ( m_debug_dcache_fsm )
2976	{
2977	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_GET> MISS in dcache:"
2978	<< " PTE1 address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
2979	}
2980	#endif
2981	}
2982	break;
2983	}
2984	////////////////////////////
2985	case DCACHE_TLB_PTE1_SELECT: // select a slot for PTE1
2986	{
2987	size_t way;
2988	size_t set;
2989
2990	if ( r_dcache_tlb_ins.read() )
2991	{
2992	r_itlb.select( r_dcache_tlb_vaddr.read(),
2993	true, // PTE1
2994	&way,
2995	&set );
2996	#ifdef INSTRUMENTATION
2997	m_cpt_itlb_read++;
2998	#endif
2999	}
3000	else
3001	{
3002	r_dtlb.select( r_dcache_tlb_vaddr.read(),
3003	true, // PTE1
3004	&way,
3005	&set );
3006	#ifdef INSTRUMENTATION
3007	m_cpt_dtlb_read++;
3008	#endif
3009	}
3010	r_dcache_tlb_way = way;
3011	r_dcache_tlb_set = set;
3012	r_dcache_fsm = DCACHE_TLB_PTE1_UPDT;
3013
3014	#if DEBUG_DCACHE
3015	if ( m_debug_dcache_fsm )
3016	{
3017	if ( r_dcache_tlb_ins.read() )
3018	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_SELECT> Select a slot in ITLB:";
3019	else
3020	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_SELECT> Select a slot in DTLB:";
3021	std::cout << " way = " << std::dec << way
3022	<< " / set = " << set << std::endl;
3023	}
3024	#endif
3025	break;
3026	}
3027	//////////////////////////
3028	case DCACHE_TLB_PTE1_UPDT: // write a new PTE1 in tlb after testing the L/R bit
3029	// - if L/R bit already set, exit the sub-fsm.
3030	// - if not, we update the page table but we dont write
3031	// neither in DCACHE, nor in TLB, as this will be done by
3032	// the coherence mechanism.
3033	{
3034	paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2);
3035	uint32_t pte = r_dcache_tlb_pte_flags.read();
3036	bool pt_updt = false;
3037	bool local = true;
3038
3039	// We should compute the access locality:
3040	// The PPN MSB bits define the destination cluster index.
3041	// The m_srcid MSB bits define the source cluster index.
3042	// The number of bits to compare depends on the number of clusters,
3043	// and can be obtained in the mapping table.
3044	// As long as this computation is not done, all access are local.
3045
3046	if ( local ) // local access
3047	{
3048	if ( not ((pte & PTE_L_MASK) == PTE_L_MASK) ) // we must set the L bit
3049	{
3050	pt_updt = true;
3051	r_dcache_vci_cas_old = pte;
3052	r_dcache_vci_cas_new = pte \| PTE_L_MASK;
3053	pte = pte \| PTE_L_MASK;
3054	r_dcache_tlb_pte_flags = pte;
3055	}
3056	}
3057	else // remote access
3058	{
3059	if ( not ((pte & PTE_R_MASK) == PTE_R_MASK) ) // we must set the R bit
3060	{
3061	pt_updt = true;
3062	r_dcache_vci_cas_old = pte;
3063	r_dcache_vci_cas_new = pte \| PTE_R_MASK;
3064	pte = pte \| PTE_R_MASK;
3065	r_dcache_tlb_pte_flags = pte;
3066	}
3067	}
3068
3069	if ( not pt_updt ) // update TLB and return
3070	{
3071	if ( r_dcache_tlb_ins.read() )
3072	{
3073	r_itlb.write( true, // 2M page
3074	pte,
3075	0, // argument unused for a PTE1
3076	r_dcache_tlb_vaddr.read(),
3077	r_dcache_tlb_way.read(),
3078	r_dcache_tlb_set.read(),
3079	nline );
3080	#ifdef INSTRUMENTATION
3081	m_cpt_itlb_write++;
3082	#endif
3083
3084	#if DEBUG_DCACHE
3085	if ( m_debug_dcache_fsm )
3086	{
3087	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_UPDT> write PTE1 in ITLB";
3088	std::cout << " / set = " << std::dec << r_dcache_tlb_set.read()
3089	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3090	r_itlb.printTrace();
3091	}
3092	#endif
3093	}
3094	else
3095	{
3096	r_dtlb.write( true, // 2M page
3097	pte,
3098	0, // argument unused for a PTE1
3099	r_dcache_tlb_vaddr.read(),
3100	r_dcache_tlb_way.read(),
3101	r_dcache_tlb_set.read(),
3102	nline );
3103	#ifdef INSTRUMENTATION
3104	m_cpt_dtlb_write++;
3105	#endif
3106
3107	#if DEBUG_DCACHE
3108	if ( m_debug_dcache_fsm )
3109	{
3110	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_UPDT> write PTE1 in DTLB";
3111	std::cout << " / set = " << std::dec << r_dcache_tlb_set.read()
3112	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3113	r_dtlb.printTrace();
3114	}
3115	#endif
3116	}
3117	r_dcache_fsm = DCACHE_TLB_RETURN;
3118	}
3119	else // update page table but not TLB
3120	{
3121	r_dcache_fsm = DCACHE_TLB_LR_UPDT;
3122
3123	#if DEBUG_DCACHE
3124	if ( m_debug_dcache_fsm )
3125	{
3126	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_UPDT> L/R bit update required"
3127	<< std::endl;
3128	}
3129	#endif
3130	}
3131	break;
3132	}
3133	/////////////////////////
3134	case DCACHE_TLB_PTE2_GET: // Try to get a PTE2 (64 bits) in the dcache
3135	{
3136	// coherence request (from CC_RECEIVE FSM)
3137	if ( r_cc_receive_dcache_req.read() )
3138	{
3139	r_dcache_fsm = DCACHE_CC_CHECK;
3140	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3141	break;
3142	}
3143
3144	uint32_t pte_flags;
3145	uint32_t pte_ppn;
3146	size_t way;
3147	size_t set;
3148	size_t word;
3149	int cache_state;
3150
3151	r_dcache.read( r_dcache_tlb_paddr.read(),
3152	&pte_flags,
3153	&pte_ppn,
3154	&way,
3155	&set,
3156	&word,
3157	&cache_state );
3158	#ifdef INSTRUMENTATION
3159	m_cpt_dcache_data_read++;
3160	m_cpt_dcache_dir_read++;
3161	#endif
3162	if ( cache_state == CACHE_SLOT_STATE_VALID ) // hit in dcache
3163	{
3164	if ( not (pte_flags & PTE_V_MASK) ) // unmapped
3165	{
3166	if ( r_dcache_tlb_ins.read() )
3167	{
3168	r_mmu_ietr = MMU_READ_PT2_UNMAPPED;
3169	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3170	r_icache_tlb_miss_req = false;
3171	r_icache_tlb_rsp_error = true;
3172	}
3173	else
3174	{
3175	r_mmu_detr = MMU_READ_PT2_UNMAPPED;
3176	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3177	m_drsp.valid = true;
3178	m_drsp.error = true;
3179	}
3180	r_dcache_fsm = DCACHE_IDLE;
3181
3182	#if DEBUG_DCACHE
3183	if ( m_debug_dcache_fsm )
3184	{
3185	std::cout << " <PROC " << name()
3186	<< " DCACHE_TLB_PTE2_GET> HIT in dcache, but PTE is unmapped"
3187	<< " PTE_FLAGS = " << std::hex << pte_flags
3188	<< " PTE_PPN = " << std::hex << pte_ppn << std::endl;
3189	}
3190	#endif
3191	}
3192	else // mapped : we must update the TLB
3193	{
3194	r_dcache_in_tlb[m_dcache_sets*way+set] = true;
3195	r_dcache_tlb_pte_flags = pte_flags;
3196	r_dcache_tlb_pte_ppn = pte_ppn;
3197	r_dcache_tlb_cache_way = way;
3198	r_dcache_tlb_cache_set = set;
3199	r_dcache_tlb_cache_word = word;
3200	r_dcache_fsm = DCACHE_TLB_PTE2_SELECT;
3201
3202	#if DEBUG_DCACHE
3203	if ( m_debug_dcache_fsm )
3204	{
3205	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE2_GET> HIT in dcache:"
3206	<< " PTE_FLAGS = " << std::hex << pte_flags
3207	<< " PTE_PPN = " << std::hex << pte_ppn << std::endl;
3208	}
3209	#endif
3210	}
3211	}
3212	else if ( cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup
3213	{
3214	// stalled until cleanup is acknowledged
3215	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
3216	}
3217	else // we must load the missing cache line in dcache
3218	{
3219	r_dcache_fsm = DCACHE_MISS_SELECT;
3220	r_dcache_vci_miss_req = true;
3221	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
3222	r_dcache_save_paddr = r_dcache_tlb_paddr.read();
3223	r_dcache_miss_type = PTE2_MISS;
3224
3225	#if DEBUG_DCACHE
3226	if ( m_debug_dcache_fsm )
3227	{
3228	std::cout << " <PROC " << name()
3229	<< " DCACHE_TLB_PTE2_GET> MISS in dcache:"
3230	<< " PTE address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
3231	}
3232	#endif
3233	}
3234	break;
3235	}
3236	////////////////////////////
3237	case DCACHE_TLB_PTE2_SELECT: // select a slot for PTE2
3238	{
3239	size_t way;
3240	size_t set;
3241
3242	if ( r_dcache_tlb_ins.read() )
3243	{
3244	r_itlb.select( r_dcache_tlb_vaddr.read(),
3245	false, // PTE2
3246	&way,
3247	&set );
3248	#ifdef INSTRUMENTATION
3249	m_cpt_itlb_read++;
3250	#endif
3251	}
3252	else
3253	{
3254	r_dtlb.select( r_dcache_tlb_vaddr.read(),
3255	false, // PTE2
3256	&way,
3257	&set );
3258	#ifdef INSTRUMENTATION
3259	m_cpt_dtlb_read++;
3260	#endif
3261	}
3262
3263	#if DEBUG_DCACHE
3264	if ( m_debug_dcache_fsm )
3265	{
3266	if ( r_dcache_tlb_ins.read() )
3267	std::cout << " <PROC " << name()
3268	<< " DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB:";
3269	else
3270	std::cout << " <PROC " << name()
3271	<< " DCACHE_TLB_PTE2_SELECT> Select a slot in DTLB:";
3272	std::cout << " way = " << std::dec << way
3273	<< " / set = " << set << std::endl;
3274	}
3275	#endif
3276	r_dcache_tlb_way = way;
3277	r_dcache_tlb_set = set;
3278	r_dcache_fsm = DCACHE_TLB_PTE2_UPDT;
3279	break;
3280	}
3281	//////////////////////////
3282	case DCACHE_TLB_PTE2_UPDT: // write a new PTE2 in tlb after testing the L/R bit
3283	// - if L/R bit already set, exit the sub-fsm.
3284	// - if not, we update the page table but we dont write
3285	// neither in DCACHE, nor in TLB, as this will be done by
3286	// the coherence mechanism.
3287	{
3288	paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2);
3289	uint32_t pte_flags = r_dcache_tlb_pte_flags.read();
3290	uint32_t pte_ppn = r_dcache_tlb_pte_ppn.read();
3291	bool pt_updt = false;
3292	bool local = true;
3293
3294	// We should compute the access locality:
3295	// The PPN MSB bits define the destination cluster index.
3296	// The m_srcid MSB bits define the source cluster index.
3297	// The number of bits to compare depends on the number of clusters,
3298	// and can be obtained in the mapping table.
3299	// As long as this computation is not done, all access are local.
3300
3301	if ( local ) // local access
3302	{
3303	if ( not ((pte_flags & PTE_L_MASK) == PTE_L_MASK) ) // we must set the L bit
3304	{
3305	pt_updt = true;
3306	r_dcache_vci_cas_old = pte_flags;
3307	r_dcache_vci_cas_new = pte_flags \| PTE_L_MASK;
3308	pte_flags = pte_flags \| PTE_L_MASK;
3309	r_dcache_tlb_pte_flags = pte_flags;
3310	}
3311	}
3312	else // remote access
3313	{
3314	if ( not ((pte_flags & PTE_R_MASK) == PTE_R_MASK) ) // we must set the R bit
3315	{
3316	pt_updt = true;
3317	r_dcache_vci_cas_old = pte_flags;
3318	r_dcache_vci_cas_new = pte_flags \| PTE_R_MASK;
3319	pte_flags = pte_flags \| PTE_R_MASK;
3320	r_dcache_tlb_pte_flags = pte_flags;
3321	}
3322	}
3323
3324	if ( not pt_updt ) // update TLB
3325	{
3326	if ( r_dcache_tlb_ins.read() )
3327	{
3328	r_itlb.write( false, // 4K page
3329	pte_flags,
3330	pte_ppn,
3331	r_dcache_tlb_vaddr.read(),
3332	r_dcache_tlb_way.read(),
3333	r_dcache_tlb_set.read(),
3334	nline );
3335	#ifdef INSTRUMENTATION
3336	m_cpt_itlb_write++;
3337	#endif
3338
3339	#if DEBUG_DCACHE
3340	if ( m_debug_dcache_fsm )
3341	{
3342	std::cout << " <PROC " << name()
3343	<< " DCACHE_TLB_PTE2_UPDT> write PTE2 in ITLB"
3344	<< " / set = " << std::dec << r_dcache_tlb_set.read()
3345	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3346	r_itlb.printTrace();
3347	}
3348	#endif
3349	}
3350	else
3351	{
3352	r_dtlb.write( false, // 4K page
3353	pte_flags,
3354	pte_ppn,
3355	r_dcache_tlb_vaddr.read(),
3356	r_dcache_tlb_way.read(),
3357	r_dcache_tlb_set.read(),
3358	nline );
3359	#ifdef INSTRUMENTATION
3360	m_cpt_dtlb_write++;
3361	#endif
3362
3363	#if DEBUG_DCACHE
3364	if ( m_debug_dcache_fsm )
3365	{
3366	std::cout << " <PROC " << name()
3367	<< " DCACHE_TLB_PTE2_UPDT> write PTE2 in DTLB"
3368	<< " / set = " << std::dec << r_dcache_tlb_set.read()
3369	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3370	r_dtlb.printTrace();
3371	}
3372	#endif
3373
3374	}
3375	r_dcache_fsm = DCACHE_TLB_RETURN;
3376	}
3377	else // update page table but not TLB
3378	{
3379	r_dcache_fsm = DCACHE_TLB_LR_UPDT; // dcache and page table update
3380
3381	#if DEBUG_DCACHE
3382	if ( m_debug_dcache_fsm )
3383	{
3384	std::cout << " <PROC " << name()
3385	<< " DCACHE_TLB_PTE2_UPDT> L/R bit update required" << std::endl;
3386	}
3387	#endif
3388	}
3389	break;
3390	}
3391	////////////////////////
3392	case DCACHE_TLB_LR_UPDT: // request a CAS transaction to update L/R bit
3393	{
3394	#if DEBUG_DCACHE
3395	if ( m_debug_dcache_fsm )
3396	{
3397	std::cout << " <PROC " << name()
3398	<< " DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit" << std::endl;
3399	}
3400	#endif
3401	// r_dcache_vci_cas_old & r_dcache_vci_cas_new registers are already set
3402	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
3403
3404	// checking llsc reservation buffer
3405	if ( r_dcache_llsc_paddr.read() == r_dcache_tlb_paddr.read() )
3406	r_dcache_llsc_valid = false;
3407
3408	// request a CAS CMD and go to DCACHE_TLB_LR_WAIT state
3409	r_dcache_vci_cas_req = true;
3410	r_dcache_fsm = DCACHE_TLB_LR_WAIT;
3411	break;
3412	}
3413	////////////////////////
3414	case DCACHE_TLB_LR_WAIT: // Waiting the response to SC transaction for DIRTY bit.
3415	// We consume the response in rsp FIFO,
3416	// and exit the sub-fsm, but we don't
3417	// analyse the response, because we don't
3418	// care if the L/R bit update is not done.
3419	// We must take the coherence requests because
3420	// there is a risk of dead-lock
3421
3422	{
3423	// coherence request (from CC_RECEIVE FSM)
3424	if ( r_cc_receive_dcache_req.read() )
3425	{
3426	r_dcache_fsm = DCACHE_CC_CHECK;
3427	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3428	break;
3429	}
3430
3431	if ( r_vci_rsp_data_error.read() ) // bus error
3432	{
3433	std::cout << "BUS ERROR in DCACHE_TLB_LR_WAIT state" << std::endl;
3434	std::cout << "This should not happen in this state" << std::endl;
3435	exit(0);
3436	}
3437	else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
3438	{
3439	#if DEBUG_DCACHE
3440	if ( m_debug_dcache_fsm )
3441	{
3442	std::cout << " <PROC " << name()
3443	<< " DCACHE_TLB_LR_WAIT> SC response received" << std::endl;
3444	}
3445	#endif
3446	vci_rsp_fifo_dcache_get = true;
3447	r_dcache_fsm = DCACHE_TLB_RETURN;
3448	}
3449	break;
3450	}
3451	///////////////////////
3452	case DCACHE_TLB_RETURN: // return to caller depending on tlb miss type
3453	{
3454	#if DEBUG_DCACHE
3455	if ( m_debug_dcache_fsm )
3456	{
3457	std::cout << " <PROC " << name()
3458	<< " DCACHE_TLB_RETURN> TLB MISS completed" << std::endl;
3459	}
3460	#endif
3461	if ( r_dcache_tlb_ins.read() ) r_icache_tlb_miss_req = false;
3462	r_dcache_fsm = DCACHE_IDLE;
3463	break;
3464	}
3465	///////////////////////
3466	case DCACHE_XTN_SWITCH: // The r_ptpr registers must be written,
3467	// and both itlb and dtlb must be flushed.
3468	// Caution : the itlb miss requests must be taken
3469	// to avoid dead-lock in case of simultaneous ITLB miss
3470	{
3471	// itlb miss request
3472	if ( r_icache_tlb_miss_req.read() )
3473	{
3474	r_dcache_tlb_ins = true;
3475	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
3476	r_dcache_fsm = DCACHE_TLB_MISS;
3477	break;
3478	}
3479
3480	if ( not r_dcache_xtn_req.read() )
3481	{
3482	r_dtlb.flush();
3483	r_mmu_ptpr = m_dreq.wdata;
3484	r_dcache_fsm = DCACHE_IDLE;
3485	m_drsp.valid = true;
3486	}
3487	break;
3488	}
3489	/////////////////////
3490	case DCACHE_XTN_SYNC: // waiting until write buffer empty
3491	// The coherence request must be taken
3492	// as there is a risk of dead-lock
3493	{
3494	// coherence request (from CC_RECEIVE FSM)
3495	if ( r_cc_receive_dcache_req.read() )
3496	{
3497	r_dcache_fsm = DCACHE_CC_CHECK;
3498	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3499	}
3500
3501	if ( r_wbuf.empty() )
3502	{
3503	m_drsp.valid = true;
3504	r_dcache_fsm = DCACHE_IDLE;
3505	}
3506	break;
3507	}
3508	////////////////////////
3509	case DCACHE_XTN_IC_FLUSH: // Waiting completion of an XTN request to the ICACHE FSM
3510	case DCACHE_XTN_IC_INVAL_VA: // Caution : the itlb miss requests must be taken
3511	case DCACHE_XTN_IC_INVAL_PA: // because the XTN_ICACHE_INVAL request to icache
3512	case DCACHE_XTN_IT_INVAL: // can generate an itlb miss,
3513	// and because it can exist a simultaneous ITLB miss
3514	{
3515	// coherence request (from CC_RECEIVE FSM)
3516	if ( r_cc_receive_dcache_req.read() )
3517	{
3518	r_dcache_fsm = DCACHE_CC_CHECK;
3519	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3520	break;
3521	}
3522
3523	// itlb miss request
3524	if ( r_icache_tlb_miss_req.read() )
3525	{
3526	r_dcache_tlb_ins = true;
3527	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
3528	r_dcache_fsm = DCACHE_TLB_MISS;
3529	break;
3530	}
3531
3532	// test if XTN request to icache completed
3533	if ( not r_dcache_xtn_req.read() )
3534	{
3535	r_dcache_fsm = DCACHE_IDLE;
3536	m_drsp.valid = true;
3537	}
3538	break;
3539	}
3540	/////////////////////////
3541	case DCACHE_XTN_DC_FLUSH: // Invalidate sequencially all cache lines, using
3542	// r_dcache_flush_count as a slot counter,
3543	// looping in this state until all slots have been visited.
3544	// It can require two cycles per slot:
3545	// We test here the slot state, and make the actual inval
3546	// (if line is valid) in DCACHE_XTN_DC_FLUSH_GO state.
3547	// A cleanup request is generated for each valid line.
3548	// returns to IDLE and flush TLBs when last slot
3549	{
3550	if ( not r_dcache_cc_send_req.read() ) // blocked until previous cc_send request is sent
3551	{
3552	int state;
3553	uint32_t tag;
3554	size_t way = r_dcache_flush_count.read()/m_dcache_sets;
3555	size_t set = r_dcache_flush_count.read()%m_dcache_sets;
3556
3557	#ifdef INSTRUMENTATION
3558	m_cpt_dcache_dir_read++;
3559	#endif
3560	r_dcache.read_dir( way,
3561	set,
3562	&tag,
3563	&state );
3564
3565	if ( state == CACHE_SLOT_STATE_VALID ) // inval required
3566	{
3567	// request cleanup
3568	r_dcache_cc_send_req = true;
3569	r_dcache_cc_send_nline = tag * m_dcache_sets;
3570	r_dcache_cc_send_way = way;
3571	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
3572
3573	// goes to DCACHE_XTN_DC_FLUSH_GO to inval directory
3574	r_dcache_miss_way = way;
3575	r_dcache_miss_set = set;
3576	r_dcache_fsm = DCACHE_XTN_DC_FLUSH_GO;
3577	}
3578	else if ( r_dcache_flush_count.read() ==
3579	(m_dcache_sets*m_dcache_ways - 1) ) // last slot
3580	{
3581	r_dtlb.reset();
3582	r_itlb.reset();
3583	r_dcache_fsm = DCACHE_IDLE;
3584	m_drsp.valid = true;
3585	}
3586
3587	// saturation counter
3588	if ( r_dcache_flush_count.read() < (m_dcache_sets*m_dcache_ways - 1) )
3589	r_dcache_flush_count = r_dcache_flush_count.read() + 1;
3590	}
3591	break;
3592	}
3593	////////////////////////////
3594	case DCACHE_XTN_DC_FLUSH_GO: // Switch the cache slot to ZOMBI state
3595	// and reset directory extension.
3596	// returns to IDLE and flush TLBs when last slot
3597	{
3598	size_t way = r_dcache_miss_way.read();
3599	size_t set = r_dcache_miss_set.read();
3600
3601	r_dcache_in_tlb[m_dcache_sets*way+set] = false;
3602	r_dcache_contains_ptd[m_dcache_sets*way+set] = false;
3603
3604	#ifdef INSTRUMENTATION
3605	m_cpt_dcache_dir_write++;
3606	#endif
3607	r_dcache.write_dir( 0,
3608	way,
3609	set,
3610	CACHE_SLOT_STATE_ZOMBI );
3611
3612	if ( r_dcache_flush_count.read() ==
3613	(m_dcache_sets*m_dcache_ways - 1) ) // last slot
3614	{
3615	r_dtlb.reset();
3616	r_itlb.reset();
3617	r_dcache_fsm = DCACHE_IDLE;
3618	m_drsp.valid = true;
3619	}
3620	else
3621	{
3622	r_dcache_fsm = DCACHE_XTN_DC_FLUSH;
3623	}
3624	break;
3625	}
3626	/////////////////////////
3627	case DCACHE_XTN_DT_INVAL: // handling processor XTN_DTLB_INVAL request
3628	{
3629	r_dtlb.inval(r_dcache_save_wdata.read());
3630	r_dcache_fsm = DCACHE_IDLE;
3631	m_drsp.valid = true;
3632	break;
3633	}
3634	////////////////////////////
3635	case DCACHE_XTN_DC_INVAL_VA: // selective cache line invalidate with virtual address
3636	// requires 3 cycles: access tlb, read cache, inval cache
3637	// we compute the physical address in this state
3638	{
3639	paddr_t paddr;
3640	bool hit;
3641
3642	if ( r_mmu_mode.read() & DATA_TLB_MASK ) // dtlb activated
3643	{
3644
3645	#ifdef INSTRUMENTATION
3646	m_cpt_dtlb_read++;
3647	#endif
3648	hit = r_dtlb.translate( r_dcache_save_wdata.read(),
3649	&paddr );
3650	}
3651	else // dtlb not activated
3652	{
3653	paddr = (paddr_t)r_dcache_save_wdata.read();
3654	hit = true;
3655	}
3656
3657	if ( hit ) // tlb hit
3658	{
3659	r_dcache_save_paddr = paddr;
3660	r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA;
3661	}
3662	else // tlb miss
3663	{
3664
3665	#ifdef INSTRUMENTATION
3666	m_cpt_dtlb_miss++;
3667	#endif
3668	r_dcache_tlb_ins = false; // dtlb
3669	r_dcache_tlb_vaddr = r_dcache_save_wdata.read();
3670	r_dcache_fsm = DCACHE_TLB_MISS;
3671	}
3672
3673	#if DEBUG_DCACHE
3674	if ( m_debug_dcache_fsm )
3675	{
3676	std::cout << " <PROC " << name()
3677	<< " DCACHE_XTN_DC_INVAL_VA> Compute physical address" << std::hex
3678	<< " / VADDR = " << r_dcache_save_wdata.read()
3679	<< " / PADDR = " << paddr << std::endl;
3680	}
3681	#endif
3682
3683	break;
3684	}
3685	////////////////////////////
3686	case DCACHE_XTN_DC_INVAL_PA: // selective cache line invalidate with physical address
3687	// requires 2 cycles: read cache / inval cache
3688	// In this state we read dcache.
3689	{
3690	size_t way;
3691	size_t set;
3692	size_t word;
3693	int state;
3694
3695	#ifdef INSTRUMENTATION
3696	m_cpt_dcache_dir_read++;
3697	#endif
3698	r_dcache.read_dir( r_dcache_save_paddr.read(),
3699	&state,
3700	&way,
3701	&set,
3702	&word );
3703
3704	if ( state == CACHE_SLOT_STATE_VALID ) // inval to be done
3705	{
3706	r_dcache_xtn_way = way;
3707	r_dcache_xtn_set = set;
3708	r_dcache_fsm = DCACHE_XTN_DC_INVAL_GO;
3709	}
3710	else // miss : nothing to do
3711	{
3712	r_dcache_fsm = DCACHE_IDLE;
3713	m_drsp.valid = true;
3714	}
3715
3716	#if DEBUG_DCACHE
3717	if ( m_debug_dcache_fsm )
3718	{
3719	std::cout << " <PROC " << name()
3720	<< " DCACHE_XTN_DC_INVAL_PA> Test hit in dcache" << std::hex
3721	<< " / PADDR = " << r_dcache_save_paddr.read() << std::dec
3722	<< " / HIT = " << (state == CACHE_SLOT_STATE_VALID)
3723	<< " / SET = " << set
3724	<< " / WAY = " << way << std::endl;
3725	}
3726	#endif
3727	break;
3728	}
3729	////////////////////////////
3730	case DCACHE_XTN_DC_INVAL_GO: // In this state, we invalidate the cache line
3731	// Blocked if previous cleanup not completed
3732	// Test if itlb or dtlb inval is required
3733	{
3734	if ( not r_dcache_cc_send_req.read() ) // blocked until previous cc_send request is sent
3735	{
3736	size_t way = r_dcache_xtn_way.read();
3737	size_t set = r_dcache_xtn_set.read();
3738	paddr_t nline = r_dcache_save_paddr.read() / (m_dcache_words<<2);
3739
3740	#ifdef INSTRUMENTATION
3741	m_cpt_dcache_dir_write++;
3742	#endif
3743	r_dcache.write_dir( 0,
3744	way,
3745	set,
3746	CACHE_SLOT_STATE_EMPTY );
3747
3748	// request cleanup
3749	r_dcache_cc_send_req = true;
3750	r_dcache_cc_send_nline = nline;
3751	r_dcache_cc_send_way = way;
3752	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
3753
3754	// possible itlb & dtlb invalidate
3755	if ( r_dcache_in_tlb[way*m_dcache_sets+set] )
3756	{
3757	r_dcache_tlb_inval_line = nline;
3758	r_dcache_tlb_inval_set = 0;
3759	r_dcache_fsm_scan_save = DCACHE_XTN_DC_INVAL_END;
3760	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
3761	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
3762	}
3763	else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] )
3764	{
3765	r_itlb.reset();
3766	r_dtlb.reset();
3767	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
3768	r_dcache_fsm = DCACHE_IDLE;
3769	m_drsp.valid = true;
3770	}
3771	else
3772	{
3773	r_dcache_fsm = DCACHE_IDLE;
3774	m_drsp.valid = true;
3775	}
3776
3777	#if DEBUG_DCACHE
3778	if ( m_debug_dcache_fsm )
3779	{
3780	std::cout << " <PROC " << name()
3781	<< " DCACHE_XTN_DC_INVAL_GO> Actual dcache inval" << std::hex
3782	<< " / PADDR = " << r_dcache_save_paddr.read() << std::endl;
3783	}
3784	#endif
3785	}
3786	break;
3787	}
3788	//////////////////////////////
3789	case DCACHE_XTN_DC_INVAL_END: // send response to processor XTN request
3790	{
3791	r_dcache_fsm = DCACHE_IDLE;
3792	m_drsp.valid = true;
3793	break;
3794	}
3795	////////////////////////
3796	case DCACHE_MISS_SELECT: // Try to select a slot in associative set
3797	// if previous cleanup has been sent.
3798	// Waiting in this state if no slot available
3799	// Set the r_dcache_cleanup_req flip-flop
3800	// and the r_dcache_miss_clack flip-flop
3801	// when a cleanup is required
3802	{
3803	if ( m_dreq.valid) m_cost_data_miss_frz++;
3804
3805	// coherence request (from CC_RECEIVE FSM)
3806	if ( r_cc_receive_dcache_req.read() )
3807	{
3808	r_dcache_fsm = DCACHE_CC_CHECK;
3809	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3810	break;
3811	}
3812
3813	if ( not r_dcache_cc_send_req.read() ) // blocked until previous cc_send request is sent
3814	{
3815	bool found;
3816	bool cleanup;
3817	size_t way;
3818	size_t set;
3819	paddr_t victim;
3820
3821	#ifdef INSTRUMENTATION
3822	m_cpt_dcache_dir_read++;
3823	#endif
3824	r_dcache.read_select( r_dcache_save_paddr.read(),
3825	&victim,
3826	&way,
3827	&set,
3828	&found,
3829	&cleanup );
3830	if ( found )
3831	{
3832	r_dcache_miss_way = way;
3833	r_dcache_miss_set = set;
3834
3835	if ( cleanup )
3836	{
3837	r_dcache_miss_clack = true;
3838	r_dcache_fsm = DCACHE_MISS_CLEAN;
3839	// request cleanup
3840	r_dcache_cc_send_req = true;
3841	r_dcache_cc_send_nline = victim;
3842	r_dcache_cc_send_way = way;
3843	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
3844	}
3845	else
3846	{
3847	r_dcache_fsm = DCACHE_MISS_WAIT;
3848	}
3849
3850	#if DEBUG_DCACHE
3851	if ( m_debug_dcache_fsm )
3852	{
3853	std::cout << " <PROC " << name()
3854	<< " DCACHE_MISS_SELECT> Select a slot:" << std::dec
3855	<< " / WAY = " << way
3856	<< " / SET = " << set
3857	<< " / PADDR = " << std::hex << r_dcache_save_paddr.read();
3858	if(cleanup) std::cout << " / VICTIM = " << std::hex << victim << std::endl;
3859	else std::cout << std::endl;
3860	}
3861	#endif
3862	} // end found
3863	}
3864	break;
3865	}
3866	///////////////////////
3867	case DCACHE_MISS_CLEAN: // switch the slot to ZOMBI state
3868	// and possibly request itlb or dtlb invalidate
3869	{
3870	if ( m_dreq.valid) m_cost_data_miss_frz++;
3871
3872	// coherence request (from CC_RECEIVE FSM)
3873	if ( r_cc_receive_dcache_req.read() )
3874	{
3875	r_dcache_fsm = DCACHE_CC_CHECK;
3876	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3877	break;
3878	}
3879
3880	size_t way = r_dcache_miss_way.read();
3881	size_t set = r_dcache_miss_set.read();
3882	paddr_t nline = r_dcache_save_paddr.read() / (m_dcache_words<<2);
3883
3884	#ifdef INSTRUMENTATION
3885	m_cpt_dcache_dir_read++;
3886	#endif
3887	r_dcache.write_dir( 0,
3888	way,
3889	set,
3890	CACHE_SLOT_STATE_ZOMBI );
3891	#if DEBUG_DCACHE
3892	if ( m_debug_dcache_fsm )
3893	{
3894	std::cout << " <PROC " << name()
3895	<< " DCACHE_MISS_CLEAN> Switch to ZOMBI state" << std::dec
3896	<< " / way = " << way
3897	<< " / set = " << set << std::endl;
3898	}
3899	#endif
3900	// if selective itlb & dtlb invalidate are required
3901	// the miss response is not handled before invalidate completed
3902	if ( r_dcache_in_tlb[way*m_dcache_sets+set] )
3903	{
3904	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
3905	r_dcache_tlb_inval_line = nline;
3906	r_dcache_tlb_inval_set = 0;
3907	r_dcache_fsm_scan_save = DCACHE_MISS_WAIT;
3908	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
3909	}
3910	else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] )
3911	{
3912	r_itlb.reset();
3913	r_dtlb.reset();
3914	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
3915	r_dcache_fsm = DCACHE_MISS_WAIT;
3916	}
3917	else
3918	{
3919	r_dcache_fsm = DCACHE_MISS_WAIT;
3920	}
3921	break;
3922	}
3923	//////////////////////
3924	case DCACHE_MISS_WAIT: // waiting the response to a miss request from VCI_RSP FSM
3925	// This state is in charge of error signaling
3926	// There is 5 types of error depending on the requester
3927	{
3928	if ( m_dreq.valid) m_cost_data_miss_frz++;
3929
3930	/**/
3931	#if DEBUG_DCACHE
3932	if ( m_debug_dcache_fsm )
3933	{
3934	std::cout << " <PROC " << name()
3935	<< " r_cc_receive_dcache_req = " << r_cc_receive_dcache_req.read() << std::endl;
3936	std::cout << " <PROC " << name()
3937	<< " r_dcache_miss_inval = " << r_dcache_miss_inval.read() << std::endl;
3938	}
3939	#endif
3940
3941	// coherence request (from CC_RECEIVE FSM)
3942	if ( r_cc_receive_dcache_req.read() )
3943	{
3944	r_dcache_fsm = DCACHE_CC_CHECK;
3945	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3946	break;
3947	}
3948
3949	if ( r_vci_rsp_data_error.read() ) // bus error
3950	{
3951	switch ( r_dcache_miss_type.read() )
3952	{
3953	case PROC_MISS:
3954	{
3955	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
3956	r_mmu_dbvar = r_dcache_save_vaddr.read();
3957	m_drsp.valid = true;
3958	m_drsp.error = true;
3959	r_dcache_fsm = DCACHE_IDLE;
3960	break;
3961	}
3962	case PTE1_MISS:
3963	{
3964	if ( r_dcache_tlb_ins.read() )
3965	{
3966	r_mmu_ietr = MMU_READ_PT1_ILLEGAL_ACCESS;
3967	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3968	r_icache_tlb_miss_req = false;
3969	r_icache_tlb_rsp_error = true;
3970	}
3971	else
3972	{
3973	r_mmu_detr = MMU_READ_PT1_ILLEGAL_ACCESS;
3974	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3975	m_drsp.valid = true;
3976	m_drsp.error = true;
3977	}
3978	r_dcache_fsm = DCACHE_IDLE;
3979	break;
3980	}
3981	case PTE2_MISS:
3982	{
3983	if ( r_dcache_tlb_ins.read() )
3984	{
3985	r_mmu_ietr = MMU_READ_PT2_ILLEGAL_ACCESS;
3986	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3987	r_icache_tlb_miss_req = false;
3988	r_icache_tlb_rsp_error = true;
3989	}
3990	else
3991	{
3992	r_mmu_detr = MMU_READ_PT2_ILLEGAL_ACCESS;
3993	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3994	m_drsp.valid = true;
3995	m_drsp.error = true;
3996	}
3997	r_dcache_fsm = DCACHE_IDLE;
3998	break;
3999	}
4000	} // end switch type
4001	r_vci_rsp_data_error = false;
4002	}
4003	else if ( r_vci_rsp_fifo_dcache.rok() ) // valid response available
4004	{
4005	r_dcache_miss_word = 0;
4006	r_dcache_fsm = DCACHE_MISS_DATA_UPDT;
4007	}
4008	break;
4009	}
4010	//////////////////////////
4011	case DCACHE_MISS_DATA_UPDT: // update the dcache (one word per cycle)
4012	{
4013	if ( m_dreq.valid) m_cost_data_miss_frz++;
4014
4015	/**/
4016	#if DEBUG_DCACHE
4017	if ( m_debug_dcache_fsm )
4018	{
4019	std::cout << " <PROC " << name()
4020	<< " r_cc_receive_dcache_req = " << r_cc_receive_dcache_req.read() << std::endl;
4021	std::cout << " <PROC " << name()
4022	<< " r_dcache_miss_inval = " << r_dcache_miss_inval.read() << std::endl;
4023	}
4024	#endif
4025
4026	if ( r_vci_rsp_fifo_dcache.rok() ) // one word available
4027	{
4028	#ifdef INSTRUMENTATION
4029	m_cpt_dcache_data_write++;
4030	#endif
4031	r_dcache.write( r_dcache_miss_way.read(),
4032	r_dcache_miss_set.read(),
4033	r_dcache_miss_word.read(),
4034	r_vci_rsp_fifo_dcache.read() );
4035	#if DEBUG_DCACHE
4036	if ( m_debug_dcache_fsm )
4037	{
4038	std::cout << " <PROC " << name()
4039	<< " DCACHE_MISS_DATA_UPDT> Write one word:"
4040	<< " / DATA = " << r_vci_rsp_fifo_dcache.read()
4041	<< " / WAY = " << std::dec << r_dcache_miss_way.read()
4042	<< " / SET = " << r_dcache_miss_set.read()
4043	<< " / WORD = " << r_dcache_miss_word.read() << std::endl;
4044	}
4045	#endif
4046	vci_rsp_fifo_dcache_get = true;
4047	r_dcache_miss_word = r_dcache_miss_word.read() + 1;
4048
4049	if ( r_dcache_miss_word.read() == (m_dcache_words-1) ) // last word
4050	{
4051	r_dcache_fsm = DCACHE_MISS_DIR_UPDT;
4052	}
4053	}
4054	break;
4055	}
4056	//////////////////////////
4057	case DCACHE_MISS_DIR_UPDT: // Stalled if a victim line has been evicted
4058	// and the cleanup ack has not been received,
4059	// as indicated by the r_dcache_miss clack.
4060	// - If no matching coherence request (r_dcache_inval_miss)
4061	// switch directory slot to VALID state.
4062	// - If matching coherence request, switch directory slot
4063	// to ZOMBI state, and send a cleanup request.
4064	{
4065	if ( m_dreq.valid) m_cost_data_miss_frz++;
4066
4067	/**/
4068	#if DEBUG_DCACHE
4069	if ( m_debug_dcache_fsm )
4070	{
4071	std::cout << " <PROC " << name()
4072	<< " r_cc_receive_dcache_req = " << r_cc_receive_dcache_req.read() << std::endl;
4073	std::cout << " <PROC " << name()
4074	<< " r_dcache_miss_inval = " << r_dcache_miss_inval.read() << std::endl;
4075	}
4076	#endif
4077
4078	// coherence request (from CC_RECEIVE FSM)
4079	if ( r_cc_receive_dcache_req.read() )
4080	{
4081	r_dcache_fsm = DCACHE_CC_CHECK;
4082	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4083	break;
4084	}
4085
4086	if ( not r_dcache_miss_clack.read() ) // waiting cleanup acknowledge
4087	{
4088	if ( r_dcache_miss_inval.read() ) // switch slot to ZOMBI state, and new cleanup
4089	{
4090	if ( not r_dcache_cc_send_req.read() ) // blocked until previous cc_send request is sent
4091	{
4092	r_dcache_miss_inval = false;
4093	// request cleanup
4094	r_dcache_cc_send_req = true;
4095	r_dcache_cc_send_nline = r_dcache_save_paddr.read()/(m_dcache_words<<2);
4096	r_dcache_cc_send_way = r_dcache_miss_way.read();
4097	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
4098
4099	#ifdef INSTRUMENTATION
4100	m_cpt_dcache_dir_write++;
4101	#endif
4102	r_dcache.write_dir( r_dcache_save_paddr.read(),
4103	r_dcache_miss_way.read(),
4104	r_dcache_miss_set.read(),
4105	CACHE_SLOT_STATE_ZOMBI );
4106	#if DEBUG_DCACHE
4107	if ( m_debug_dcache_fsm )
4108	{
4109	std::cout << " <PROC " << name()
4110	<< " DCACHE_MISS_DIR_UPDT> Switch slot to ZOMBI state"
4111	<< " PADDR = " << std::hex << r_dcache_save_paddr.read()
4112	<< " / WAY = " << std::dec << r_dcache_miss_way.read()
4113	<< " / SET = " << r_dcache_miss_set.read() << std::endl;
4114	}
4115	#endif
4116	}
4117	else
4118	break;
4119	}
4120	else // switch slot to VALID state
4121	{
4122
4123	#ifdef INSTRUMENTATION
4124	m_cpt_dcache_dir_write++;
4125	#endif
4126	r_dcache.write_dir( r_dcache_save_paddr.read(),
4127	r_dcache_miss_way.read(),
4128	r_dcache_miss_set.read(),
4129	CACHE_SLOT_STATE_VALID );
4130
4131	#if DEBUG_DCACHE
4132	if ( m_debug_dcache_fsm )
4133	{
4134	std::cout << " <PROC " << name()
4135	<< " DCACHE_MISS_DIR_UPDT> Switch slot to VALID state"
4136	<< " PADDR = " << std::hex << r_dcache_save_paddr.read()
4137	<< " / WAY = " << std::dec << r_dcache_miss_way.read()
4138	<< " / SET = " << r_dcache_miss_set.read() << std::endl;
4139
4140	r_dcache.printTrace();
4141
4142
4143	}
4144	#endif
4145	// reset directory extension
4146	size_t way = r_dcache_miss_way.read();
4147	size_t set = r_dcache_miss_set.read();
4148	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
4149	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
4150	}
4151	if (r_dcache_miss_type.read()==PTE1_MISS) r_dcache_fsm = DCACHE_TLB_PTE1_GET;
4152	else if (r_dcache_miss_type.read()==PTE2_MISS) r_dcache_fsm = DCACHE_TLB_PTE2_GET;
4153	else r_dcache_fsm = DCACHE_IDLE;
4154	}
4155	break;
4156	}
4157	/////////////////////
4158	case DCACHE_UNC_WAIT: // waiting a response to an uncacheable read
4159	{
4160	// coherence request (from CC_RECEIVE FSM)
4161	if ( r_cc_receive_dcache_req.read() )
4162	{
4163	r_dcache_fsm = DCACHE_CC_CHECK;
4164	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4165	break;
4166	}
4167
4168	if ( r_vci_rsp_data_error.read() ) // bus error
4169	{
4170	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
4171	r_mmu_dbvar = m_dreq.addr;
4172	r_vci_rsp_data_error = false;
4173	m_drsp.error = true;
4174	m_drsp.valid = true;
4175	r_dcache_fsm = DCACHE_IDLE;
4176	break;
4177	}
4178	else if ( r_vci_rsp_fifo_dcache.rok() ) // data available
4179	{
4180	// consume data
4181	vci_rsp_fifo_dcache_get = true;
4182	r_dcache_fsm = DCACHE_IDLE;
4183
4184	// acknowledge the processor request if it has not been modified
4185	if ( m_dreq.valid and (m_dreq.addr == r_dcache_save_vaddr.read()) )
4186	{
4187	m_drsp.valid = true;
4188	m_drsp.error = false;
4189	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
4190	}
4191	}
4192	break;
4193	}
4194	/////////////////////
4195	case DCACHE_LL_WAIT: // waiting VCI response to a LL transaction
4196	{
4197	// coherence request (from CC_RECEIVE FSM)
4198	if ( r_cc_receive_dcache_req.read() )
4199	{
4200	r_dcache_fsm = DCACHE_CC_CHECK;
4201	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4202	break;
4203	}
4204
4205	if ( r_vci_rsp_data_error.read() ) // bus error
4206	{
4207	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
4208	r_mmu_dbvar = m_dreq.addr;
4209	r_vci_rsp_data_error = false;
4210	m_drsp.error = true;
4211	m_drsp.valid = true;
4212	r_dcache_fsm = DCACHE_IDLE;
4213	break;
4214	}
4215	else if ( r_vci_rsp_fifo_dcache.rok() ) // data available
4216	{
4217	// consume data
4218	vci_rsp_fifo_dcache_get = true;
4219
4220	if(r_dcache_ll_rsp_count.read() == 0) // first flit
4221	{
4222	// set key value in llsc reservation buffer
4223	r_dcache_llsc_key = r_vci_rsp_fifo_dcache.read();
4224	r_dcache_ll_rsp_count = r_dcache_ll_rsp_count.read() + 1 ;
4225	}
4226	else // last flit
4227	{
4228	// acknowledge the processor request if it has not been modified
4229	if ( m_dreq.valid and (m_dreq.addr == r_dcache_save_vaddr.read()) )
4230	{
4231	m_drsp.valid = true;
4232	m_drsp.error = false;
4233	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
4234	}
4235	r_dcache_fsm = DCACHE_IDLE;
4236	}
4237	}
4238	break;
4239	}
4240	////////////////////
4241	case DCACHE_SC_WAIT: // waiting VCI response to a SC transaction
4242	{
4243	// coherence request (from CC_RECEIVE FSM)
4244	if ( r_cc_receive_dcache_req.read() )
4245	{
4246	r_dcache_fsm = DCACHE_CC_CHECK;
4247	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4248	break;
4249	}
4250
4251	if ( r_vci_rsp_data_error.read() ) // bus error
4252	{
4253	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
4254	r_mmu_dbvar = m_dreq.addr;
4255	r_vci_rsp_data_error = false;
4256	m_drsp.error = true;
4257	m_drsp.valid = true;
4258	r_dcache_fsm = DCACHE_IDLE;
4259	break;
4260	}
4261	else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
4262	{
4263	// consume response
4264	vci_rsp_fifo_dcache_get = true;
4265	m_drsp.valid = true;
4266	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
4267	r_dcache_fsm = DCACHE_IDLE;
4268	}
4269	break;
4270	}
4271	//////////////////////////
4272	case DCACHE_DIRTY_GET_PTE: // This sub_fsm set the PTE Dirty bit in memory
4273	// before handling a processor WRITE or SC request
4274	// Input argument is r_dcache_dirty_paddr
4275	// In this first state, we get PTE value in dcache
4276	// and post a CAS request to CMD FSM
4277	{
4278	// get PTE in dcache
4279	uint32_t pte;
4280	size_t way;
4281	size_t set;
4282	size_t word; // unused
4283	int state;
4284
4285	#ifdef INSTRUMENTATION
4286	m_cpt_dcache_data_read++;
4287	m_cpt_dcache_dir_read++;
4288	#endif
4289	r_dcache.read( r_dcache_dirty_paddr.read(),
4290	&pte,
4291	&way,
4292	&set,
4293	&word,
4294	&state );
4295
4296	assert( (state == CACHE_SLOT_STATE_VALID) and
4297	"error in DCACHE_DIRTY_TLB_SET: the PTE should be in dcache" );
4298
4299	// request CAS transaction to CMD_FSM
4300	r_dcache_dirty_way = way;
4301	r_dcache_dirty_set = set;
4302
4303	// check llsc reservation buffer
4304	if (r_dcache_llsc_paddr.read() == r_dcache_dirty_paddr.read() )
4305	r_dcache_llsc_valid = false;
4306
4307	// request a CAS CMD and go to DCACHE_DIRTY_WAIT state
4308	r_dcache_vci_cas_req = true;
4309	r_dcache_vci_paddr = r_dcache_dirty_paddr.read();
4310	r_dcache_vci_cas_old = pte;
4311	r_dcache_vci_cas_new = pte \| PTE_D_MASK;
4312	r_dcache_fsm = DCACHE_DIRTY_WAIT;
4313
4314	#if DEBUG_DCACHE
4315	if ( m_debug_dcache_fsm )
4316	{
4317	std::cout << " <PROC " << name()
4318	<< " DCACHE_DIRTY_GET_PTE> CAS request" << std::hex
4319	<< " / PTE_PADDR = " << r_dcache_dirty_paddr.read()
4320	<< " / PTE_VALUE = " << pte << std::dec
4321	<< " / SET = " << set
4322	<< " / WAY = " << way << std::endl;
4323	}
4324	#endif
4325	break;
4326	}
4327	///////////////////////
4328	case DCACHE_DIRTY_WAIT: // wait completion of CAS for PTE Dirty bit,
4329	// and return to IDLE state when response is received.
4330	// we don't care if the CAS is a failure:
4331	// - if the CAS is a success, the coherence mechanism
4332	// updates the local copy.
4333	// - if the CAS is a failure, we just retry the write.
4334	{
4335	// coherence request (from CC_RECEIVE FSM)
4336	if ( r_cc_receive_dcache_req.read() )
4337	{
4338	r_dcache_fsm = DCACHE_CC_CHECK;
4339	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4340	break;
4341	}
4342
4343	if ( r_vci_rsp_data_error.read() ) // bus error
4344	{
4345	std::cout << "BUS ERROR in DCACHE_DIRTY_WAIT state" << std::endl;
4346	std::cout << "This should not happen in this state" << std::endl;
4347	exit(0);
4348	}
4349	else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
4350	{
4351	vci_rsp_fifo_dcache_get = true;
4352	r_dcache_fsm = DCACHE_IDLE;
4353
4354	#if DEBUG_DCACHE
4355	if ( m_debug_dcache_fsm )
4356	{
4357	std::cout << " <PROC " << name()
4358	<< " DCACHE_DIRTY_WAIT> CAS completed" << std::endl;
4359	}
4360	#endif
4361	}
4362	break;
4363	}
4364	/////////////////////
4365	case DCACHE_CC_CHECK: // This state is the entry point for the sub-FSM
4366	// handling coherence requests for DCACHE.
4367	// If there is a matching pending miss on the modified cache
4368	// line this is signaled in the r_dcache_miss inval flip-flop.
4369	// If the updated (or invalidated) cache line has copies in TLBs
4370	// these TLB copies are invalidated.
4371	// The return state is defined in r_dcache_fsm_cc_save
4372	{
4373	paddr_t paddr = r_cc_receive_dcache_nline.read() * m_dcache_words * 4;
4374	paddr_t mask = ~((m_dcache_words<<2)-1);
4375
4376	#if DEBUG_DCACHE
4377	if ( m_debug_dcache_fsm )
4378	{
4379	std::cout << " <PROC " << name()
4380	<< " DCACHE_CC_CHECK> paddr = " << paddr
4381	<< " r_dcache_vci_paddr = " << r_dcache_vci_paddr.read()
4382	<< " mask = " << mask
4383	<< " (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) = " << (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT)
4384	<< " (r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT) = " << (r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT)
4385	<< " ((r_dcache_vci_paddr.read() & mask) == (paddr & mask)) = " << ((r_dcache_vci_paddr.read() & mask) == (paddr & mask))
4386	<<std::endl;
4387	}
4388	#endif
4389
4390	if (r_cc_receive_dcache_type.read() == CC_TYPE_CLACK)
4391	// We switch the directory slot to EMPTY state
4392	// and reset r_icache_miss_clack if the cleanup ack
4393	// is matching a pending miss.
4394	{
4395
4396	if ( m_dreq.valid ) m_cost_data_miss_frz++;
4397
4398	#ifdef INSTRUMENTATION
4399	m_cpt_dcache_dir_write++;
4400	#endif
4401	r_dcache.write_dir( 0,
4402	r_cc_receive_dcache_way.read(),
4403	r_cc_receive_dcache_set.read(),
4404	CACHE_SLOT_STATE_EMPTY);
4405
4406	if ( (r_dcache_miss_set.read() == r_cc_receive_dcache_set.read()) and
4407	(r_dcache_miss_way.read() == r_cc_receive_dcache_way.read()) )
4408	r_dcache_miss_clack = false;
4409
4410	r_dcache_fsm = r_dcache_fsm_cc_save.read() ;
4411	r_cc_receive_dcache_req = false;
4412	#if DEBUG_DCACHE
4413	if ( m_debug_dcache_fsm )
4414	{
4415	std::cout << " <PROC " << name()
4416	<< " DCACHE_CC_CHECK> CC_TYPE_CLACK Switch slot to EMPTY state"
4417	<< " set = " << r_cc_receive_dcache_set.read()
4418	<< " / way = " << r_cc_receive_dcache_way.read() << std::endl;
4419	}
4420	#endif
4421	}
4422	else if( ((r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) or
4423	(r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT)) and
4424	((r_dcache_vci_paddr.read() & mask) == (paddr & mask)) ) // matching
4425	{
4426	// signaling matching
4427	r_dcache_miss_inval = true;
4428
4429	// in case of update, go to CC_UPDT
4430	// JUST TO POP THE FIFO
4431	if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT)
4432	{
4433	r_dcache_fsm = DCACHE_CC_UPDT;
4434	r_dcache_cc_word = r_cc_receive_word_idx.read();
4435	// just pop the fifo , don't write in icache
4436	r_dcache_cc_need_write = false;
4437	}
4438	// the request is dealt with
4439	else
4440	{
4441	r_cc_receive_dcache_req = false;
4442	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4443	}
4444
4445	#if DEBUG_DCACHE
4446	if ( m_debug_dcache_fsm )
4447	{
4448	std::cout << " <PROC " << name()
4449	<< " DCACHE_CC_CHECK> Coherence request matching a pending miss:"
4450	<< " PADDR = " << std::hex << paddr << std::endl;
4451	}
4452	#endif
4453
4454	}
4455	else // no match
4456	{
4457	int state;
4458	size_t way;
4459	size_t set;
4460	size_t word;
4461
4462	#ifdef INSTRUMENTATION
4463	m_cpt_dcache_dir_read++;
4464	#endif
4465	r_dcache.read_dir( paddr,
4466	&state,
4467	&way,
4468	&set,
4469	&word ); // unused
4470
4471	r_dcache_cc_way = way;
4472	r_dcache_cc_set = set;
4473
4474	if ( state == CACHE_SLOT_STATE_VALID) // hit
4475	{
4476	// need to update the cache state
4477	r_dcache_cc_need_write = true;
4478	if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT) // hit update
4479	{
4480	r_dcache_fsm = DCACHE_CC_UPDT;
4481	r_dcache_cc_word = r_cc_receive_word_idx.read();
4482	}
4483	else if (r_cc_receive_dcache_type.read() == CC_TYPE_INVAL) // hit inval
4484	{
4485	r_dcache_fsm = DCACHE_CC_INVAL;
4486	}
4487	else if ( r_cc_receive_dcache_type.read() == CC_TYPE_BRDCAST) // hit broadcast
4488	{
4489	r_dcache_fsm = DCACHE_CC_BROADCAST;
4490	}
4491	}
4492	else // miss
4493	{
4494	// multicast acknowledgement required in case of update
4495	if(r_cc_receive_dcache_type.read() == CC_TYPE_UPDT)
4496	{
4497	r_dcache_fsm = DCACHE_CC_UPDT;
4498	r_dcache_cc_word = r_cc_receive_word_idx.read();
4499	// just pop the fifo , don't write in icache
4500	r_dcache_cc_need_write = false;
4501	}
4502	else // No response needed
4503	{
4504	r_cc_receive_dcache_req = false;
4505	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4506	}
4507	}
4508
4509	#if DEBUG_DCACHE
4510	if ( m_debug_dcache_fsm )
4511	{
4512	std::cout << " <PROC " << name()
4513	<< " DCACHE_CC_CHECK> Coherence request received:"
4514	<< " PADDR = " << std::hex << paddr
4515	<< " / TYPE = " << std::dec << r_cc_receive_dcache_type.read()
4516	<< " / HIT = " << (state == CACHE_SLOT_STATE_VALID) << std::endl;
4517	}
4518	#endif
4519	}
4520	break;
4521	}
4522	/////////////////////
4523	case DCACHE_CC_INVAL: // hit inval: switch slot to EMPTY state,
4524	// after possible invalidation of copies in TLBs
4525	{
4526	size_t way = r_dcache_cc_way.read();
4527	size_t set = r_dcache_cc_set.read();
4528
4529	if (r_dcache_cc_need_write.read())
4530	{
4531	if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // selective TLB inval
4532	{
4533	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
4534	r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read();
4535	r_dcache_tlb_inval_set = 0;
4536	r_dcache_fsm_scan_save = r_dcache_fsm.read();
4537	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4538	break;
4539	}
4540	else
4541	{
4542	if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // TLB flush
4543	{
4544	r_itlb.reset();
4545	r_dtlb.reset();
4546	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
4547
4548	#if DEBUG_DCACHE
4549	if ( m_debug_dcache_fsm )
4550	{
4551	std::cout << " <PROC " << name()
4552	<< " DCACHE_CC_INVAL> Flush DTLB & ITLB" << std::endl;
4553	}
4554	#endif
4555	}
4556
4557	r_dcache.write_dir( 0,
4558	way,
4559	set,
4560	CACHE_SLOT_STATE_EMPTY );
4561
4562	r_dcache_cc_need_write = false;
4563
4564	#if DEBUG_DCACHE
4565	if ( m_debug_dcache_fsm )
4566	{
4567	std::cout << " <PROC " << name()
4568	<< " DCACHE_CC_INVAL> Switch slot to EMPTY state:" << std::dec
4569	<< " / WAY = " << way
4570	<< " / SET = " << set << std::endl;
4571	}
4572	#endif
4573	}
4574	}
4575	// multicast acknowledgement
4576	// send a request to cc_send_fsm
4577	if(not r_dcache_cc_send_req.read()) // cc_send is available
4578	{
4579	// coherence request completed
4580	r_cc_receive_dcache_req = false;
4581	// request multicast acknowledgement
4582	r_dcache_cc_send_req = true;
4583	r_dcache_cc_send_updt_tab_idx = r_cc_receive_dcache_updt_tab_idx.read();
4584	r_dcache_cc_send_type = CC_TYPE_MULTI_ACK;
4585
4586	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4587	}
4588	//else wait for previous cc_send request to be sent
4589	break;
4590	}
4591	///////////////////
4592	case DCACHE_CC_UPDT: // hit update: write one word per cycle,
4593	// after possible invalidation of copies in TLBs
4594	{
4595	size_t word = r_dcache_cc_word.read();
4596	size_t way = r_dcache_cc_way.read();
4597	size_t set = r_dcache_cc_set.read();
4598
4599	if (r_cc_receive_updt_fifo_be.rok())
4600	{
4601	if (r_dcache_cc_need_write.read())
4602	{
4603	if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // selective TLB inval
4604	{
4605	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
4606	r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read();
4607	r_dcache_tlb_inval_set = 0;
4608	r_dcache_fsm_scan_save = r_dcache_fsm.read();
4609	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4610	break;
4611	}
4612
4613	if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // TLB flush
4614	{
4615	r_itlb.reset();
4616	r_dtlb.reset();
4617	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
4618
4619	#if DEBUG_DCACHE
4620	if ( m_debug_dcache_fsm )
4621	{
4622	std::cout << " <PROC " << name()
4623	<< " DCACHE_CC_UPDT> Flush DTLB & ITLB" << std::endl;
4624	}
4625	#endif
4626	}
4627
4628	#ifdef INSTRUMENTATION
4629	m_cpt_dcache_data_write++;
4630	#endif
4631	r_dcache.write( way,
4632	set,
4633	word,
4634	r_cc_receive_updt_fifo_data.read(),
4635	r_cc_receive_updt_fifo_be.read() );
4636
4637	r_dcache_cc_word = word + 1;
4638
4639	#if DEBUG_DCACHE
4640	if ( m_debug_dcache_fsm )
4641	{
4642	std::cout << " <PROC " << name()
4643	<< " DCACHE_CC_UPDT> Write one word" << std::dec
4644	<< " / WAY = " << way
4645	<< " / SET = " << set
4646	<< " / WORD = " << word
4647	<< " / VALUE = " << std::hex << r_cc_receive_updt_fifo_data.read() << std::endl;
4648	}
4649	#endif
4650	}
4651
4652	if ( r_cc_receive_updt_fifo_eop.read() ) // last word
4653	{
4654	// no need to write in the cache anymore
4655	r_dcache_cc_need_write = false;
4656
4657	// wait to send a request to cc_send_fsm
4658	if(not r_icache_cc_send_req.read())
4659	// cc_send is available
4660	{
4661	//consume last fifo flit if eop and request to cc_send possible
4662	cc_receive_updt_fifo_get = true;
4663
4664	// coherence request completed
4665	r_cc_receive_dcache_req = false;
4666
4667	// request multicast acknowledgement
4668	r_dcache_cc_send_req = true;
4669	r_dcache_cc_send_updt_tab_idx = r_cc_receive_dcache_updt_tab_idx.read();
4670	r_dcache_cc_send_type = CC_TYPE_MULTI_ACK;
4671
4672	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4673	}
4674	}
4675	else
4676	{
4677	//consume fifo if not eop
4678	cc_receive_updt_fifo_get = true;
4679	}
4680	}
4681	break;
4682	}
4683	/////////////////////////
4684	case DCACHE_CC_BROADCAST: // hit broadcast : switch state to ZOMBI state
4685	// and request a cleanup, after possible
4686	// invalidation of copies in TLBs
4687	{
4688	size_t way = r_dcache_cc_way.read();
4689	size_t set = r_dcache_cc_set.read();
4690	paddr_t nline = r_cc_receive_dcache_nline.read();
4691
4692	if (r_dcache_cc_need_write.read())
4693	{
4694	if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // selective TLB inval
4695	{
4696	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
4697	r_dcache_tlb_inval_line = nline;
4698	r_dcache_tlb_inval_set = 0;
4699	r_dcache_fsm_scan_save = r_dcache_fsm.read();
4700	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4701	break;
4702	}
4703	else
4704	{
4705	if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // TLB flush
4706	{
4707	r_itlb.reset();
4708	r_dtlb.reset();
4709	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
4710
4711	#if DEBUG_DCACHE
4712	if ( m_debug_dcache_fsm )
4713	{
4714	std::cout << " <PROC " << name()
4715	<< " DCACHE_CC_BROADCAST> Flush DTLB & ITLB" << std::endl;
4716	}
4717	#endif
4718	}
4719
4720	#ifdef INSTRUMENTATION
4721	m_cpt_dcache_dir_write++;
4722	#endif
4723	r_dcache.write_dir( 0,
4724	way,
4725	set,
4726	CACHE_SLOT_STATE_ZOMBI );
4727
4728	r_dcache_cc_need_write = false;
4729	#if DEBUG_DCACHE
4730	if ( m_debug_dcache_fsm )
4731	{
4732	std::cout << " <PROC " << name()
4733	<< " DCACHE_CC_BROADCAST > Slot goes to ZOMBI state "
4734	<< " SET = " << set
4735	<< " / WAY = " << way << std::endl;
4736	}
4737	#endif
4738	}
4739	}
4740	// cleanup
4741	// send a request to cc_send_fsm
4742	if(not r_dcache_cc_send_req.read()) // cc_send is available
4743	{
4744	// coherence request completed
4745	r_cc_receive_dcache_req = false;
4746	// request cleanup
4747	r_dcache_cc_send_req = true;
4748	r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read();
4749	r_dcache_cc_send_way = r_dcache_cc_way.read();
4750	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
4751
4752	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4753	}
4754	//else wait for previous cc_send request to be sent
4755	break;
4756	}
4757	///////////////////////////
4758	case DCACHE_INVAL_TLB_SCAN: // Scan sequencially all sets for both ITLB & DTLB
4759	// It makes assumption: m_itlb_sets == m_dtlb_sets
4760	// All ways are handled in parallel.
4761	// We enter this state when a DCACHE line is modified,
4762	// and there is a copy in itlb or dtlb.
4763	// It can be caused by:
4764	// - a coherence inval or updt transaction,
4765	// - a line inval caused by a cache miss
4766	// - a processor XTN inval request,
4767	// - a WRITE hit,
4768	// - a Dirty bit update
4769	// Input arguments are:
4770	// - r_dcache_tlb_inval_line
4771	// - r_dcache_tlb_inval_set
4772	// - r_dcache_fsm_scan_save
4773	{
4774	paddr_t line = r_dcache_tlb_inval_line.read();
4775	size_t set = r_dcache_tlb_inval_set.read();
4776	size_t way;
4777	bool ok;
4778
4779	for ( way = 0 ; way < m_itlb_ways ; way++ )
4780	{
4781	ok = r_itlb.inval( line, way, set );
4782
4783	#if DEBUG_DCACHE
4784	if ( m_debug_dcache_fsm and ok )
4785	{
4786	std::cout << " <PROC " << name()
4787	<< ".DCACHE_INVAL_TLB_SCAN> Invalidate ITLB entry:" << std::hex
4788	<< " line = " << line << std::dec
4789	<< " / set = " << set
4790	<< " / way = " << way << std::endl;
4791	}
4792	#endif
4793	}
4794
4795	for ( way = 0 ; way < m_dtlb_ways ; way++ )
4796	{
4797	ok = r_dtlb.inval( line, way, set );
4798
4799	#if DEBUG_DCACHE
4800	if ( m_debug_dcache_fsm and ok )
4801	{
4802	std::cout << " <PROC " << name()
4803	<< ".DCACHE_INVAL_TLB_SCAN> Invalidate DTLB entry:" << std::hex
4804	<< " line = " << line << std::dec
4805	<< " / set = " << set
4806	<< " / way = " << way << std::endl;
4807	}
4808	#endif
4809	}
4810
4811	// return to the calling state when TLB inval completed
4812	if ( r_dcache_tlb_inval_set.read() == (m_dtlb_sets-1) )
4813	{
4814	r_dcache_fsm = r_dcache_fsm_scan_save.read();
4815	}
4816	r_dcache_tlb_inval_set = r_dcache_tlb_inval_set.read() + 1;
4817	break;
4818	}
4819	} // end switch r_dcache_fsm
4820
4821	///////////////// wbuf update ///////////////////////////////////////////////////////
4822	r_wbuf.update();
4823
4824	///////////////// llsc update ///////////////////////////////////////////////////////
4825	if (r_dcache_llsc_valid.read()) r_dcache_llsc_count = r_dcache_llsc_count.read() - 1;
4826	if (r_dcache_llsc_count.read() == 1) r_dcache_llsc_valid = false;
4827
4828	//////////////// test processor frozen //////////////////////////////////////////////
4829	// The simulation exit if the number of consecutive frozen cycles
4830	// is larger than the m_max_frozen_cycles (constructor parameter)
4831	if ( (m_ireq.valid and not m_irsp.valid) or (m_dreq.valid and not m_drsp.valid) )
4832	{
4833	m_cpt_frz_cycles++; // used for instrumentation
4834	m_cpt_stop_simulation++; // used for debug
4835	if ( m_cpt_stop_simulation > m_max_frozen_cycles )
4836	{
4837	std::cout << std::dec << "ERROR in CC_VCACHE_WRAPPER " << name() << std::endl
4838	<< " stop at cycle " << m_cpt_total_cycles << std::endl
4839	<< " frozen since cycle " << m_cpt_total_cycles - m_max_frozen_cycles
4840	<< std::endl;
4841	r_iss.dump();
4842	exit(1);
4843	}
4844	}
4845	else
4846	{
4847	m_cpt_stop_simulation = 0;
4848	}
4849
4850	/////////// execute one iss cycle /////////////////////////////////
4851	{
4852	uint32_t it = 0;
4853	for (size_t i=0; i<(size_t)iss_t::n_irq; i++) if(p_irq[i].read()) it \|= (1<<i);
4854	r_iss.executeNCycles(1, m_irsp, m_drsp, it);
4855	}
4856
4857	////////////////////////////////////////////////////////////////////////////
4858	// The VCI_CMD FSM controls the following ressources:
4859	// - r_vci_cmd_fsm
4860	// - r_vci_cmd_min
4861	// - r_vci_cmd_max
4862	// - r_vci_cmd_cpt
4863	// - r_vci_cmd_imiss_prio
4864	// - wbuf (reset)
4865	// - r_icache_miss_req (reset)
4866	// - r_icache_unc_req (reset)
4867	// - r_dcache_vci_miss_req (reset)
4868	// - r_dcache_vci_unc_req (reset)
4869	// - r_dcache_vci_ll_req (reset)
4870	// - r_dcache_vci_sc_req (reset in case of local sc fail)
4871	// - r_dcache_vci_cas_req (reset)
4872	//
4873	// This FSM handles requests from both the DCACHE FSM & the ICACHE FSM.
4874	// There are 8 request types, with the following priorities :
4875	// 1 - Data Read Miss : r_dcache_vci_miss_req and miss in the write buffer
4876	// 2 - Data Read Uncachable : r_dcache_vci_unc_req
4877	// 3 - Instruction Miss : r_icache_miss_req and miss in the write buffer
4878	// 4 - Instruction Uncachable : r_icache_unc_req
4879	// 5 - Data Write : r_wbuf.rok()
4880	// 6 - Data Linked Load : r_dcache_vci_ll_req
4881	// 7 - Data Store Conditionnal: r_dcache_vci_sc_req
4882	// 8 - Compare And Swap : r_dcache_vci_cas_req
4883	//
4884	// As we want to support several simultaneous VCI transactions, the VCI_CMD_FSM
4885	// and the VCI_RSP_FSM are fully desynchronized.
4886	//
4887	// VCI formats:
4888	// According to the VCI advanced specification, all read requests packets
4889	// (data Uncached, Miss data, instruction Uncached, Miss instruction)
4890	// are one word packets.
4891	// For write burst packets, all words are in the same cache line,
4892	// and addresses must be contiguous (the BE field is 0 in case of "holes").
4893	// The sc command packet implements actually a compare-and-swap mechanism
4894	// and the packet contains two flits.
4895	////////////////////////////////////////////////////////////////////////////////////
4896
4897	switch ( r_vci_cmd_fsm.read() )
4898	{
4899	//////////////
4900	case CMD_IDLE:
4901	{
4902	// DDACHE read requests (r_dcache_vci_miss_req or r_dcache_vci_ll_req), and
4903	// ICACHE read requests (r_icache_miss_req) require both a write_buffer access
4904	// to check a possible pending write on the same cache line.
4905	// As there is only one possible access per cycle to write buffer, we implement
4906	// a round-robin priority between DCACHE and ICACHE for this access,
4907	// using the r_vci_cmd_imiss_prio flip-flop.
4908
4909	size_t wbuf_min;
4910	size_t wbuf_max;
4911
4912	bool dcache_unc_req = r_dcache_vci_unc_req.read() and
4913	( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() );
4914
4915	bool dcache_miss_req = r_dcache_vci_miss_req.read() and
4916	( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() );
4917
4918	bool dcache_ll_req = r_dcache_vci_ll_req.read() and
4919	( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() );
4920
4921	bool icache_miss_req = r_icache_miss_req.read() and
4922	( not (r_dcache_vci_miss_req.read() or
4923	r_dcache_vci_ll_req.read() or
4924	r_dcache_vci_unc_req.read())
4925	or r_vci_cmd_imiss_prio.read() ) ;
4926
4927	// 1 - Data Read Miss
4928	if ( dcache_miss_req and r_wbuf.miss(r_dcache_vci_paddr.read()) )
4929	{
4930	r_vci_cmd_fsm = CMD_DATA_MISS;
4931	r_dcache_vci_miss_req = false;
4932	r_vci_cmd_imiss_prio = true;
4933	// m_cpt_dmiss_transaction++;
4934	}
4935	// 2 - Data Read Uncachable
4936	else if ( dcache_unc_req and r_wbuf.miss(r_dcache_vci_paddr.read()))
4937	{
4938	r_vci_cmd_fsm = CMD_DATA_UNC;
4939	r_dcache_vci_unc_req = false;
4940	// m_cpt_dunc_transaction++;
4941	}
4942	// 3 - Data Linked Load
4943	else if ( dcache_ll_req and r_wbuf.miss(r_dcache_vci_paddr.read()))
4944	{
4945	r_dcache_vci_ll_req = false;
4946	r_vci_cmd_fsm = CMD_DATA_LL;
4947	// m_cpt_ll_transaction++;
4948	}
4949	// 4 - Instruction Miss
4950	else if ( icache_miss_req and r_wbuf.miss(r_icache_vci_paddr.read()) )
4951	{
4952	r_vci_cmd_fsm = CMD_INS_MISS;
4953	r_icache_miss_req = false;
4954	r_vci_cmd_imiss_prio = false;
4955	// m_cpt_imiss_transaction++;
4956	}
4957	// 5 - Instruction Uncachable
4958	else if ( r_icache_unc_req.read() )
4959	{
4960	r_vci_cmd_fsm = CMD_INS_UNC;
4961	r_icache_unc_req = false;
4962	// m_cpt_iunc_transaction++;
4963	}
4964	// 6 - Data Write
4965	else if ( r_wbuf.rok(&wbuf_min, &wbuf_max) )
4966	{
4967	r_vci_cmd_fsm = CMD_DATA_WRITE;
4968	r_vci_cmd_cpt = wbuf_min;
4969	r_vci_cmd_min = wbuf_min;
4970	r_vci_cmd_max = wbuf_max;
4971	// m_cpt_write_transaction++;
4972	// m_length_write_transaction += (wbuf_max-wbuf_min+1);
4973	}
4974	// 7 - Data Store Conditionnal
4975	else if ( r_dcache_vci_sc_req.read() )
4976	{
4977	r_dcache_vci_sc_req = false;
4978	r_vci_cmd_cpt = 0;
4979	r_vci_cmd_fsm = CMD_DATA_SC;
4980	// m_cpt_sc_transaction++;
4981	}
4982	// 8 - Compare And Swap
4983	else if ( r_dcache_vci_cas_req.read() )
4984	{
4985	r_vci_cmd_fsm = CMD_DATA_CAS;
4986	r_dcache_vci_cas_req = false;
4987	r_vci_cmd_cpt = 0;
4988	// m_cpt_cas_transaction++;
4989	}
4990	break;
4991	}
4992	////////////////////
4993	case CMD_DATA_WRITE:
4994	{
4995	if ( p_vci.cmdack.read() )
4996	{
4997	r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
4998	if (r_vci_cmd_cpt == r_vci_cmd_max) // last flit sent
4999	{
5000	r_vci_cmd_fsm = CMD_IDLE ;
5001	r_wbuf.sent() ;
5002	}
5003	}
5004	break;
5005	}
5006	/////////////////
5007	case CMD_DATA_SC:
5008	case CMD_DATA_CAS:
5009	{
5010	// The CAS and SC VCI commands contain two flits
5011	if ( p_vci.cmdack.read() )
5012	{
5013	r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
5014	if (r_vci_cmd_cpt == 1) r_vci_cmd_fsm = CMD_IDLE ;
5015	}
5016	break;
5017	}
5018	//////////////////
5019	case CMD_INS_MISS:
5020	case CMD_INS_UNC:
5021	case CMD_DATA_MISS:
5022	case CMD_DATA_UNC:
5023	case CMD_DATA_LL:
5024	{
5025	// all read VCI commands contain one single flit
5026	if ( p_vci.cmdack.read() ) r_vci_cmd_fsm = CMD_IDLE;
5027	break;
5028	}
5029
5030	} // end switch r_vci_cmd_fsm
5031
5032	//////////////////////////////////////////////////////////////////////////
5033	// The VCI_RSP FSM controls the following ressources:
5034	// - r_vci_rsp_fsm:
5035	// - r_vci_rsp_fifo_icache (push)
5036	// - r_vci_rsp_fifo_dcache (push)
5037	// - r_vci_rsp_data_error (set)
5038	// - r_vci_rsp_ins_error (set)
5039	// - r_vci_rsp_cpt
5040	// - r_dcache_vci_sc_req (reset when SC response recieved)
5041	//
5042	// As the VCI_RSP and VCI_CMD are fully desynchronized to support several
5043	// simultaneous VCI transactions, this FSM uses the VCI RPKTID field
5044	// to identify the transactions.
5045	//
5046	// VCI vormat:
5047	// This component checks the response packet length and accepts only
5048	// single word packets for write response packets.
5049	//
5050	// Error handling:
5051	// This FSM analyzes the VCI error code and signals directly the Write Bus Error.
5052	// In case of Read Data Error, the VCI_RSP FSM sets the r_vci_rsp_data_error
5053	// flip_flop and the error is signaled by the DCACHE FSM.
5054	// In case of Instruction Error, the VCI_RSP FSM sets the r_vci_rsp_ins_error
5055	// flip_flop and the error is signaled by the ICACHE FSM.
5056	// In case of Cleanup Error, the simulation stops with an error message...
5057	//////////////////////////////////////////////////////////////////////////
5058
5059	switch ( r_vci_rsp_fsm.read() )
5060	{
5061	//////////////
5062	case RSP_IDLE:
5063	{
5064	if ( p_vci.rspval.read() )
5065	{
5066	r_vci_rsp_cpt = 0;
5067
5068	if ( (p_vci.rpktid.read() & 0x7) == TYPE_READ_DATA_UNC )
5069	{
5070	r_vci_rsp_fsm = RSP_DATA_UNC;
5071	}
5072	else if ( (p_vci.rpktid.read() & 0x7) == TYPE_READ_DATA_MISS )
5073	{
5074	r_vci_rsp_fsm = RSP_DATA_MISS;
5075	}
5076	else if ( (p_vci.rpktid.read() & 0x7) == TYPE_READ_INS_UNC )
5077	{
5078	r_vci_rsp_fsm = RSP_INS_UNC;
5079	}
5080	else if ( (p_vci.rpktid.read() & 0x7) == TYPE_READ_INS_MISS )
5081	{
5082	r_vci_rsp_fsm = RSP_INS_MISS;
5083	}
5084	else if ( (p_vci.rpktid.read() & 0x7) == TYPE_WRITE )
5085	{
5086	r_vci_rsp_fsm = RSP_DATA_WRITE;
5087	}
5088	else if ( (p_vci.rpktid.read() & 0x7) == TYPE_CAS )
5089	{
5090	r_vci_rsp_fsm = RSP_DATA_UNC;
5091	}
5092	else if ( (p_vci.rpktid.read() & 0x7) == TYPE_LL )
5093	{
5094	r_vci_rsp_fsm = RSP_DATA_LL;
5095	}
5096	else if ( (p_vci.rpktid.read() & 0x7) == TYPE_SC )
5097	{
5098	r_vci_rsp_fsm = RSP_DATA_UNC;
5099	}
5100	else
5101	{
5102	assert(false and "Unexpected VCI response");
5103	}
5104	}
5105	break;
5106	}
5107	//////////////////
5108	case RSP_INS_MISS:
5109	{
5110	if ( p_vci.rspval.read() )
5111	{
5112	if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported
5113	{
5114	r_vci_rsp_ins_error = true;
5115	if ( p_vci.reop.read() ) r_vci_rsp_fsm = RSP_IDLE;
5116	}
5117	else // no error reported
5118	{
5119	if ( r_vci_rsp_fifo_icache.wok() )
5120	{
5121	assert( (r_vci_rsp_cpt.read() < m_icache_words) and
5122	"The VCI response packet for instruction miss is too long" );
5123
5124	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
5125	vci_rsp_fifo_icache_put = true,
5126	vci_rsp_fifo_icache_data = p_vci.rdata.read();
5127	if ( p_vci.reop.read() )
5128	{
5129	assert( (r_vci_rsp_cpt.read() == m_icache_words - 1) and
5130	"The VCI response packet for instruction miss is too short");
5131
5132	r_vci_rsp_fsm = RSP_IDLE;
5133	}
5134	}
5135	}
5136	}
5137	break;
5138	}
5139	/////////////////
5140	case RSP_INS_UNC:
5141	{
5142	if (p_vci.rspval.read() )
5143	{
5144	assert( p_vci.reop.read() and
5145	"illegal VCI response packet for uncachable instruction");
5146
5147	if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported
5148	{
5149	r_vci_rsp_ins_error = true;
5150	r_vci_rsp_fsm = RSP_IDLE;
5151	}
5152	else // no error reported
5153	{
5154	if ( r_vci_rsp_fifo_icache.wok())
5155	{
5156	vci_rsp_fifo_icache_put = true;
5157	vci_rsp_fifo_icache_data = p_vci.rdata.read();
5158	r_vci_rsp_fsm = RSP_IDLE;
5159	}
5160	}
5161	}
5162	break;
5163	}
5164	///////////////////
5165	case RSP_DATA_MISS:
5166	{
5167	if ( p_vci.rspval.read() )
5168	{
5169	if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported
5170	{
5171	r_vci_rsp_data_error = true;
5172	if ( p_vci.reop.read() ) r_vci_rsp_fsm = RSP_IDLE;
5173	}
5174	else // no error reported
5175	{
5176	if ( r_vci_rsp_fifo_dcache.wok() )
5177	{
5178	assert( (r_vci_rsp_cpt.read() < m_dcache_words) and
5179	"The VCI response packet for data miss is too long");
5180
5181	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
5182	vci_rsp_fifo_dcache_put = true,
5183	vci_rsp_fifo_dcache_data = p_vci.rdata.read();
5184	if ( p_vci.reop.read() )
5185	{
5186	assert( (r_vci_rsp_cpt.read() == m_dcache_words - 1) and
5187	"The VCI response packet for data miss is too short");
5188
5189	r_vci_rsp_fsm = RSP_IDLE;
5190	}
5191	}
5192	}
5193	}
5194	break;
5195	}
5196	//////////////////
5197	case RSP_DATA_UNC:
5198	{
5199	if (p_vci.rspval.read() )
5200	{
5201	assert( p_vci.reop.read() and
5202	"illegal VCI response packet for uncachable read data");
5203
5204	if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported
5205	{
5206	r_vci_rsp_data_error = true;
5207	r_vci_rsp_fsm = RSP_IDLE;
5208	}
5209	else // no error reported
5210	{
5211	if ( r_vci_rsp_fifo_dcache.wok())
5212	{
5213	vci_rsp_fifo_dcache_put = true;
5214	vci_rsp_fifo_dcache_data = p_vci.rdata.read();
5215	r_vci_rsp_fsm = RSP_IDLE;
5216	}
5217	}
5218	}
5219	break;
5220	}
5221	////////////////////
5222	case RSP_DATA_LL:
5223	{
5224	if ( p_vci.rspval.read() )
5225	{
5226	if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported
5227	{
5228	r_vci_rsp_data_error = true;
5229	r_vci_rsp_fsm = RSP_IDLE;
5230	}
5231	if (r_vci_rsp_cpt.read() == 0) //first flit
5232	{
5233	if(r_vci_rsp_fifo_dcache.wok())
5234	{
5235	assert(!p_vci.reop.read() &&
5236	"illegal VCI response packet for LL");
5237	vci_rsp_fifo_dcache_put = true;
5238	vci_rsp_fifo_dcache_data = p_vci.rdata.read();
5239	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
5240	}
5241	break;
5242	}
5243	else // last flit
5244	{
5245	if(r_vci_rsp_fifo_dcache.wok())
5246	{
5247	assert(p_vci.reop.read() &&
5248	"illegal VCI response packet for LL");
5249	vci_rsp_fifo_dcache_put = true;
5250	vci_rsp_fifo_dcache_data = p_vci.rdata.read();
5251	r_vci_rsp_fsm = RSP_IDLE;
5252	}
5253	break;
5254	}
5255	}
5256	break;
5257	}
5258	////////////////////
5259	case RSP_DATA_WRITE:
5260	{
5261	if (p_vci.rspval.read())
5262	{
5263	assert( p_vci.reop.read() and
5264	"a VCI response packet must contain one flit for a write transaction");
5265
5266	r_vci_rsp_fsm = RSP_IDLE;
5267	uint32_t wbuf_index = p_vci.rtrdid.read();
5268	bool cacheable = r_wbuf.completed(wbuf_index);
5269	if ( not cacheable ) r_dcache_pending_unc_write = false;
5270	if ( (p_vci.rerror.read()&0x1) != 0 ) r_iss.setWriteBerr();
5271	}
5272	break;
5273	}
5274	} // end switch r_vci_rsp_fsm
5275
5276	/////////////////////////////////////////////////////////////////////////////////////
5277	// The CC_SEND FSM is in charge of sending cleanups and the multicast
5278	// acknowledgements on the coherence network. It has two clients (DCACHE FSM
5279	// and ICACHE FSM) that are served with a round-robin priority.
5280	// The CC_SEND FSM resets the r_*cache_cc_send_req request flip-flops as
5281	// soon as the request has been sent.
5282	/////////////////////////////////////////////////////////////////////////////////////
5283	switch ( r_cc_send_fsm.read() )
5284	{
5285	///////////////////////////
5286	case CC_SEND_IDLE:
5287	{
5288	///////////////////////////////////////////////////////
5289	// handling round robin between icache and dcache : //
5290	// we first check for the last client and listen for //
5291	// a request of the other, then update the client //
5292	///////////////////////////////////////////////////////
5293	// r_cc_send_last_client : 0 dcache / 1 icache
5294	bool update_last_client = r_cc_send_last_client.read();
5295	if ( r_cc_send_last_client.read() == 0 ) // last client was dcache
5296	{
5297	if (r_icache_cc_send_req.read()) // request from icache
5298	update_last_client = 1; // update last client to icache
5299	}
5300	else // last client was icache
5301	{
5302	if (r_dcache_cc_send_req.read()) // request from dcache
5303	update_last_client = 0; // update last client to dcache
5304	}
5305	r_cc_send_last_client = update_last_client;
5306
5307	// if there is an actual request
5308	if (r_dcache_cc_send_req.read() or r_icache_cc_send_req.read())
5309	{
5310	// test if the new client is dcache and has a cleanup request
5311	if ( (update_last_client == 0) and (r_dcache_cc_send_type.read() == CC_TYPE_CLEANUP))
5312	r_cc_send_fsm = CC_SEND_CLEANUP_1;
5313	// test if the new client is dcache and has a multi acknowledgement request
5314	else if ( (update_last_client == 0) and (r_dcache_cc_send_type.read() == CC_TYPE_MULTI_ACK))
5315	r_cc_send_fsm = CC_SEND_MULTI_ACK;
5316	// test if the new client is icache and has a cleanup request
5317	else if ( (update_last_client == 1) and (r_icache_cc_send_type.read() == CC_TYPE_CLEANUP))
5318	r_cc_send_fsm = CC_SEND_CLEANUP_1;
5319	// test if the new client is icache and has a multi acknowledgement request
5320	else if ( (update_last_client == 1) and (r_icache_cc_send_type.read() == CC_TYPE_MULTI_ACK))
5321	r_cc_send_fsm = CC_SEND_MULTI_ACK;
5322	}
5323	break;
5324	}
5325	///////////////////////////
5326	case CC_SEND_CLEANUP_1:
5327	{
5328	/**/
5329	#if DEBUG_DCACHE
5330	if ( m_debug_dcache_fsm )
5331	{
5332	std::cout << " <PROC " << name()
5333	<< " r_dcache_cc_send_nline = " << r_dcache_cc_send_nline.read() << std::endl;
5334	}
5335	#endif
5336	// wait for the first flit to be consumed
5337	if (p_dspin_out.read.read())
5338	r_cc_send_fsm = CC_SEND_CLEANUP_2;
5339
5340	break;
5341	}
5342	///////////////////////////
5343	case CC_SEND_CLEANUP_2:
5344	/**/
5345	#if DEBUG_DCACHE
5346	if ( m_debug_dcache_fsm )
5347	{
5348	std::cout << " <PROC " << name()
5349	<< " r_dcache_cc_send_nline = " << r_dcache_cc_send_nline.read() << std::endl;
5350	}
5351	#endif
5352	{
5353	assert( p_dspin_out.read.read() and
5354	"The interconnect should accept the second cleanup flit instantly" );
5355
5356	// wait for the second flit to be consumed
5357	if (p_dspin_out.read.read())
5358	{
5359	if (r_cc_send_last_client.read() == 0) // dcache active request
5360	r_dcache_cc_send_req = false; // reset dcache request
5361	else // icache active request
5362	r_icache_cc_send_req = false; // reset icache request
5363
5364	// go back to idle state
5365	r_cc_send_fsm = CC_SEND_IDLE;
5366	}
5367	break;
5368	}
5369	///////////////////////////
5370	case CC_SEND_MULTI_ACK:
5371	{
5372	// wait for the flit to be consumed
5373	if(p_dspin_out.read.read())
5374	{
5375	if(r_cc_send_last_client.read() == 0) // dcache active request
5376	r_dcache_cc_send_req = false; // reset dcache request
5377	else // icache active request
5378	r_icache_cc_send_req = false; // reset icache request
5379	// go back to idle state
5380	r_cc_send_fsm = CC_SEND_IDLE;
5381	}
5382	break;
5383	}
5384	} // end switch CC_SEND FSM
5385
5386	///////////////////////////////////////////////////////////////////////////////
5387	// C_RECEIVE FSM
5388	// This FSM receive all coherence packets on a DSPIN40 port.
5389	// There is 4 packet types:
5390	// - CC_DATA_INVAL : DCACHE invalidate request
5391	// - CC_DATA_UPDT : DCACHE update request (multi-words)
5392	// - CC_INST_INVAL : ICACHE invalidate request
5393	// - CC_INST_UPDT : ICACHE update request (multi-words)
5394	// - CC_BROADCAST : Broadcast invalidate request (both DCACHE & ICACHE)
5395	// - CC_DATA_CLACK : DCACHE cleanup acknowledge
5396	// - CC_INST_CLACK : ICACHE cleanup acknowledge
5397	//////////////////////////////////////////////////////////////////////////////
5398	switch( r_cc_receive_fsm.read() )
5399	{
5400	/////////////////////
5401	case CC_RECEIVE_IDLE:
5402	{
5403	/**/
5404	#if DEBUG_DCACHE
5405	if ( m_debug_dcache_fsm )
5406	{
5407	std::cout << " <PROC " << name()
5408	<< " r_cc_receive_dcache_req = " << r_cc_receive_dcache_req.read() << std::endl;
5409	std::cout << " <PROC " << name()
5410	<< " r_dcache_miss_inval = " << r_dcache_miss_inval.read() << std::endl;
5411	}
5412	#endif
5413	// a coherence request has arrived
5414	if (p_dspin_in.write.read())
5415	{
5416	// initialize dspin received data
5417	uint64_t receive_data = p_dspin_in.data.read();
5418	// initialize coherence packet type
5419	uint64_t receive_type = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::FROM_MC_TYPE);
5420	// initialize data/ins flip_flop (0 data / 1 ins)
5421	r_cc_receive_data_ins = (bool)(receive_type & 0x1);
5422	// test for a broadcast
5423	if (DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::FROM_MC_BC))
5424	{
5425	r_cc_receive_fsm = CC_RECEIVE_BRDCAST_HEADER;
5426	}
5427	// test for a CLACK
5428	else if ((receive_type == DspinDhccpParam::TYPE_CLEANUP_ACK_DATA) or
5429	(receive_type == DspinDhccpParam::TYPE_CLEANUP_ACK_INST))
5430	{
5431	r_cc_receive_fsm = CC_RECEIVE_CLACK;
5432	}
5433	// test for a multi updt
5434	else if ((receive_type == DspinDhccpParam::TYPE_MULTI_UPDT_DATA) or
5435	(receive_type == DspinDhccpParam::TYPE_MULTI_UPDT_INST))
5436	{
5437	r_cc_receive_fsm = CC_RECEIVE_UPDT_HEADER;
5438	}
5439	// test for a multi inval
5440	else
5441	{
5442	r_cc_receive_fsm = CC_RECEIVE_INVAL_HEADER;
5443	}
5444	}
5445	break;
5446	}
5447	//////////////////////
5448	case CC_RECEIVE_CLACK:
5449	{
5450	// initialize dspin received data
5451	uint64_t receive_data = p_dspin_in.data.read();
5452
5453	// for data CLACK, wait for dcache to take the request
5454	if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()))
5455	{
5456	// request dcache to handle the CLACK
5457	r_cc_receive_dcache_req = true;
5458	r_cc_receive_dcache_set = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::CLEANUP_ACK_SET) & ((1ULL<<(uint32_log2(m_dcache_sets)))-1);
5459	r_cc_receive_dcache_way = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::CLEANUP_ACK_WAY) & ((1ULL<<(uint32_log2(m_dcache_ways)))-1);
5460	r_cc_receive_dcache_type = CC_TYPE_CLACK;
5461	// get back to idle state
5462	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5463	break;
5464	}
5465	// for ins CLACK, wait for icache to take the request
5466	if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()))
5467	{
5468	// request icache to handle the CLACK
5469	r_cc_receive_icache_req = true;
5470	r_cc_receive_icache_set = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::CLEANUP_ACK_SET) & ((1ULL<<(uint32_log2(m_icache_sets)))-1);
5471	r_cc_receive_icache_way = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::CLEANUP_ACK_WAY) & ((1ULL<<(uint32_log2(m_icache_ways)))-1);
5472	r_cc_receive_icache_type = CC_TYPE_CLACK;
5473	// get back to idle state
5474	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5475	break;
5476	}
5477	// keep waiting for the correct cache to accept the request
5478	break;
5479	}
5480	///////////////////////////////
5481	case CC_RECEIVE_BRDCAST_HEADER:
5482	{
5483	/**/
5484	#if DEBUG_DCACHE
5485	if ( m_debug_dcache_fsm )
5486	{
5487	std::cout << " <PROC " << name()
5488	<< " r_cc_receive_dcache_req = " << r_cc_receive_dcache_req.read() << std::endl;
5489	std::cout << " <PROC " << name()
5490	<< " r_dcache_miss_inval = " << r_dcache_miss_inval.read() << std::endl;
5491	}
5492	#endif
5493	// no actual data in the HEADER, just skip to second flit
5494	r_cc_receive_fsm = CC_RECEIVE_BRDCAST_NLINE;
5495	break;
5496	}
5497	//////////////////////////////
5498	case CC_RECEIVE_BRDCAST_NLINE:
5499	{
5500	/**/
5501	#if DEBUG_DCACHE
5502	if ( m_debug_dcache_fsm )
5503	{
5504	std::cout << " <PROC " << name()
5505	<< " r_cc_receive_dcache_req = " << r_cc_receive_dcache_req.read() << std::endl;
5506	std::cout << " <PROC " << name()
5507	<< " r_dcache_miss_inval = " << r_dcache_miss_inval.read() << std::endl;
5508	}
5509	#endif
5510	// initialize dspin received data
5511	uint64_t receive_data = p_dspin_in.data.read();
5512	// wait for both dcache and icache to take the request
5513	// TODO maybe we need to wait for both only to leave the state, but
5514	// not to actually post a request to an available cache => need a
5515	// flip_flop to check that ?
5516	if (not (r_cc_receive_icache_req.read()) and not (r_cc_receive_dcache_req.read()))
5517	{
5518	// request dcache to handle the BROADCAST
5519	r_cc_receive_dcache_req = true;
5520	r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::BROADCAST_NLINE);
5521	r_cc_receive_dcache_type = CC_TYPE_BRDCAST;
5522	// request icache to handle the BROADCAST
5523	r_cc_receive_icache_req = true;
5524	r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::BROADCAST_NLINE);
5525	r_cc_receive_icache_type = CC_TYPE_BRDCAST;
5526	// get back to idle state
5527	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5528	break;
5529	}
5530	// keep waiting for the caches to accept the request
5531	break;
5532	}
5533	/////////////////////////////
5534	case CC_RECEIVE_INVAL_HEADER:
5535	{
5536	// sample updt tab index in the HEADER, then skip to second flit
5537	uint64_t receive_data = p_dspin_in.data.read();
5538	// for data INVAL, wait for dcache to take the request
5539	if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()))
5540	{
5541	r_cc_receive_dcache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_UPDT_INDEX);
5542	r_cc_receive_fsm = CC_RECEIVE_INVAL_NLINE;
5543	break;
5544	}
5545	// for ins INVAL, wait for icache to take the request
5546	if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()))
5547	{
5548	r_cc_receive_icache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_UPDT_INDEX);
5549	r_cc_receive_fsm = CC_RECEIVE_INVAL_NLINE;
5550	break;
5551	}
5552	// keep waiting for the correct cache to accept the request
5553	break;
5554	}
5555	////////////////////////////
5556	case CC_RECEIVE_INVAL_NLINE:
5557	{
5558	// sample nline in the second flit
5559	uint64_t receive_data = p_dspin_in.data.read();
5560	// for data INVAL, wait for dcache to take the request
5561	if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()))
5562	{
5563	// request dcache to handle the INVAL
5564	r_cc_receive_dcache_req = true;
5565	r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_NLINE);
5566	r_cc_receive_dcache_type = CC_TYPE_INVAL;
5567	// get back to idle state
5568	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5569	break;
5570	}
5571	// for ins INVAL, wait for icache to take the request
5572	if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()))
5573	{
5574	// request icache to handle the INVAL
5575	r_cc_receive_icache_req = true;
5576	r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_NLINE);
5577	r_cc_receive_icache_type = CC_TYPE_INVAL;
5578	// get back to idle state
5579	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5580	break;
5581	}
5582	// we should never get there
5583	assert ( false && "CC_RECEIVE_INVAL_NLINE : incoherent handling of either r_cc_receive_data_ins or r_cc_receive_*cache_req\n");
5584	}
5585	////////////////////////////
5586	case CC_RECEIVE_UPDT_HEADER:
5587	{
5588	// sample updt tab index in the HEADER, than skip to second flit
5589	uint64_t receive_data = p_dspin_in.data.read();
5590	// for data INVAL, wait for dcache to take the request and fifo to
5591	// be empty
5592	if ((r_cc_receive_data_ins.read() == 0) and not r_cc_receive_dcache_req.read() and r_cc_receive_updt_fifo_be.empty())
5593	{
5594	r_cc_receive_dcache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_UPDT_INDEX);
5595	r_cc_receive_fsm = CC_RECEIVE_UPDT_NLINE;
5596	break;
5597	}
5598	// for ins INVAL, wait for icache to take the request and fifo to be
5599	// empty
5600	if ((r_cc_receive_data_ins.read() == 1) and not r_cc_receive_icache_req.read() and r_cc_receive_updt_fifo_be.empty())
5601	{
5602	r_cc_receive_icache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_UPDT_INDEX);
5603	r_cc_receive_fsm = CC_RECEIVE_UPDT_NLINE;
5604	break;
5605	}
5606	// keep waiting for the correct cache to accept the request
5607	break;
5608	}
5609	///////////////////////////
5610	case CC_RECEIVE_UPDT_NLINE:
5611	{
5612	// sample nline and word index in the second flit
5613	uint64_t receive_data = p_dspin_in.data.read();
5614	// for data INVAL, wait for dcache to take the request and fifo to
5615	// be empty
5616	if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()) and r_cc_receive_updt_fifo_be.empty())
5617	{
5618	r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_NLINE);
5619	r_cc_receive_word_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_WORD_INDEX);
5620	r_cc_receive_dcache_type = CC_TYPE_UPDT;
5621	// get back to idle state
5622	r_cc_receive_fsm = CC_RECEIVE_UPDT_DATA;
5623	break;
5624	}
5625	// for ins INVAL, wait for icache to take the request and fifo to be
5626	// empty
5627	if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()) and r_cc_receive_updt_fifo_be.empty())
5628	{
5629	r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_NLINE);
5630	r_cc_receive_word_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_WORD_INDEX);
5631	r_cc_receive_icache_type = CC_TYPE_UPDT;
5632	// get back to idle state
5633	r_cc_receive_fsm = CC_RECEIVE_UPDT_DATA;
5634	break;
5635	}
5636	// we should never get there
5637	assert ( false && "CC_RECEIVE_UPDT_NLINE : incoherent handling of either r_cc_receive_data_ins or r_cc_receive_*cache_req or r_cc_receive_fifo\n");
5638	break;
5639	}
5640	//////////////////////////
5641	case CC_RECEIVE_UPDT_DATA:
5642	{
5643	if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()))
5644	r_cc_receive_dcache_req = true;
5645	if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()))
5646	r_cc_receive_icache_req = true;
5647
5648	// sample data, be and eop
5649	uint64_t receive_data = p_dspin_in.data.read();
5650	// wait for the fifo
5651	if (r_cc_receive_updt_fifo_be.wok())
5652	{
5653	cc_receive_updt_fifo_be = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_BE);
5654	cc_receive_updt_fifo_data = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_DATA);
5655	// sample eop to test for state exit
5656	bool flit_eop = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::FROM_MC_EOP);
5657	cc_receive_updt_fifo_eop = flit_eop;
5658	cc_receive_updt_fifo_put = true;
5659	if(flit_eop)
5660	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5661	}
5662	break;
5663	}
5664	} // end switch CC_RECEIVE FSM
5665
5666	///////////////// Response FIFOs update //////////////////////
5667	r_vci_rsp_fifo_icache.update(vci_rsp_fifo_icache_get,
5668	vci_rsp_fifo_icache_put,
5669	vci_rsp_fifo_icache_data);
5670
5671	r_vci_rsp_fifo_dcache.update(vci_rsp_fifo_dcache_get,
5672	vci_rsp_fifo_dcache_put,
5673	vci_rsp_fifo_dcache_data);
5674
5675	///////////////// updt FIFO update //////////////////////
5676	//TODO check this
5677	r_cc_receive_updt_fifo_be.update(cc_receive_updt_fifo_get,
5678	cc_receive_updt_fifo_put,
5679	cc_receive_updt_fifo_be);
5680	r_cc_receive_updt_fifo_data.update(cc_receive_updt_fifo_get,
5681	cc_receive_updt_fifo_put,
5682	cc_receive_updt_fifo_data);
5683	r_cc_receive_updt_fifo_eop.update(cc_receive_updt_fifo_get,
5684	cc_receive_updt_fifo_put,
5685	cc_receive_updt_fifo_eop);
5686
5687	} // end transition()
5688
5689	///////////////////////
5690	tmpl(void)::genMoore()
5691	///////////////////////
5692	{
5693
5694	// VCI initiator command on the direct network
5695	// it depends on the CMD FSM state
5696
5697	bool is_sc_or_cas = (r_vci_cmd_fsm.read() == CMD_DATA_CAS) or
5698	(r_vci_cmd_fsm.read() == CMD_DATA_SC );
5699
5700	p_vci.pktid = 0;
5701	p_vci.srcid = m_srcid;
5702	p_vci.cons = is_sc_or_cas;
5703	p_vci.contig = not is_sc_or_cas;
5704	p_vci.wrap = false;
5705	p_vci.clen = 0;
5706	p_vci.cfixed = false;
5707
5708	switch ( r_vci_cmd_fsm.read() ) {
5709
5710	case CMD_IDLE:
5711	p_vci.cmdval = false;
5712	p_vci.address = 0;
5713	p_vci.wdata = 0;
5714	p_vci.be = 0;
5715	p_vci.trdid = 0;
5716	p_vci.pktid = 0;
5717	p_vci.plen = 0;
5718	p_vci.cmd = vci_param::CMD_NOP;
5719	p_vci.eop = false;
5720	break;
5721
5722	case CMD_INS_MISS:
5723	p_vci.cmdval = true;
5724	p_vci.address = r_icache_vci_paddr.read() & m_icache_yzmask;
5725	p_vci.wdata = 0;
5726	p_vci.be = 0xF;
5727	p_vci.trdid = 0;
5728	p_vci.pktid = TYPE_READ_INS_MISS;
5729	p_vci.plen = m_icache_words<<2;
5730	p_vci.cmd = vci_param::CMD_READ;
5731	p_vci.eop = true;
5732	break;
5733
5734	case CMD_INS_UNC:
5735	p_vci.cmdval = true;
5736	p_vci.address = r_icache_vci_paddr.read() & ~0x3;
5737	p_vci.wdata = 0;
5738	p_vci.be = 0xF;
5739	p_vci.trdid = 0;
5740	p_vci.pktid = TYPE_READ_INS_UNC;
5741	p_vci.plen = 4;
5742	p_vci.cmd = vci_param::CMD_READ;
5743	p_vci.eop = true;
5744	break;
5745
5746	case CMD_DATA_MISS:
5747	p_vci.cmdval = true;
5748	p_vci.address = r_dcache_vci_paddr.read() & m_dcache_yzmask;
5749	p_vci.wdata = 0;
5750	p_vci.be = 0xF;
5751	p_vci.trdid = 0;
5752	p_vci.pktid = TYPE_READ_DATA_MISS;
5753	p_vci.plen = m_dcache_words << 2;
5754	p_vci.cmd = vci_param::CMD_READ;
5755	p_vci.eop = true;
5756	break;
5757
5758	case CMD_DATA_UNC:
5759	p_vci.cmdval = true;
5760	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
5761	p_vci.wdata = 0;
5762	p_vci.be = r_dcache_vci_unc_be.read();
5763	p_vci.trdid = 0;
5764	p_vci.pktid = TYPE_READ_DATA_UNC;
5765	p_vci.plen = 4;
5766	p_vci.cmd = vci_param::CMD_READ;
5767	p_vci.eop = true;
5768	break;
5769
5770	case CMD_DATA_WRITE:
5771	p_vci.cmdval = true;
5772	p_vci.address = r_wbuf.getAddress(r_vci_cmd_cpt.read()) & ~0x3;
5773	p_vci.wdata = r_wbuf.getData(r_vci_cmd_cpt.read());
5774	p_vci.be = r_wbuf.getBe(r_vci_cmd_cpt.read());
5775	p_vci.trdid = r_wbuf.getIndex();
5776	p_vci.pktid = TYPE_WRITE;
5777	p_vci.plen = (r_vci_cmd_max.read() - r_vci_cmd_min.read() + 1) << 2;
5778	p_vci.cmd = vci_param::CMD_WRITE;
5779	p_vci.eop = (r_vci_cmd_cpt.read() == r_vci_cmd_max.read());
5780	break;
5781
5782	case CMD_DATA_LL:
5783	p_vci.cmdval = true;
5784	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
5785	p_vci.wdata = 0;
5786	p_vci.be = 0xF;
5787	p_vci.trdid = 0;
5788	p_vci.pktid = TYPE_LL;
5789	p_vci.plen = 8;
5790	p_vci.cmd = vci_param::CMD_LOCKED_READ;
5791	p_vci.eop = true;
5792	break;
5793
5794	case CMD_DATA_SC:
5795	p_vci.cmdval = true;
5796	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
5797	if ( r_vci_cmd_cpt.read() == 0 ) p_vci.wdata = r_dcache_llsc_key.read();
5798	else p_vci.wdata = r_dcache_vci_sc_data.read();
5799	p_vci.be = 0xF;
5800	p_vci.trdid = 0;
5801	p_vci.pktid = TYPE_SC;
5802	p_vci.plen = 8;
5803	p_vci.cmd = vci_param::CMD_NOP;
5804	p_vci.eop = (r_vci_cmd_cpt.read() == 1);
5805	break;
5806
5807	case CMD_DATA_CAS:
5808	p_vci.cmdval = true;
5809	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
5810	if ( r_vci_cmd_cpt.read() == 0 ) p_vci.wdata = r_dcache_vci_cas_old.read();
5811	else p_vci.wdata = r_dcache_vci_cas_new.read();
5812	p_vci.be = 0xF;
5813	p_vci.trdid = 0;
5814	p_vci.pktid = TYPE_CAS;
5815	p_vci.plen = 8;
5816	p_vci.cmd = vci_param::CMD_NOP;
5817	p_vci.eop = (r_vci_cmd_cpt.read() == 1);
5818	break;
5819	} // end switch r_vci_cmd_fsm
5820
5821	// VCI initiator response on the direct network
5822	// it depends on the VCI_RSP FSM
5823
5824	switch (r_vci_rsp_fsm.read() )
5825	{
5826	case RSP_DATA_WRITE : p_vci.rspack = true; break;
5827	case RSP_INS_MISS : p_vci.rspack = r_vci_rsp_fifo_icache.wok(); break;
5828	case RSP_INS_UNC : p_vci.rspack = r_vci_rsp_fifo_icache.wok(); break;
5829	case RSP_DATA_MISS : p_vci.rspack = r_vci_rsp_fifo_dcache.wok(); break;
5830	case RSP_DATA_UNC : p_vci.rspack = r_vci_rsp_fifo_dcache.wok(); break;
5831	case RSP_DATA_LL : p_vci.rspack = r_vci_rsp_fifo_dcache.wok(); break;
5832	case RSP_IDLE : p_vci.rspack = false; break;
5833	} // end switch r_vci_rsp_fsm
5834
5835
5836	// Send coherence packets on DSPIN L2M
5837	// it depends on the CC_SEND FSM
5838
5839	uint64_t dspin_send_data = 0;
5840	switch ( r_cc_send_fsm.read() )
5841	{
5842	//////////////////
5843	case CC_SEND_IDLE:
5844	{
5845	p_dspin_out.write = false;
5846	break;
5847	}
5848	///////////////////////
5849	case CC_SEND_CLEANUP_1:
5850	{
5851	// initialize dspin send data
5852	DspinDhccpParam::dspin_set(dspin_send_data,
5853	0,
5854	DspinDhccpParam::FROM_L1_EOP);
5855	DspinDhccpParam::dspin_set(dspin_send_data,
5856	m_cc_global_id,
5857	DspinDhccpParam::CLEANUP_SRCID);
5858	DspinDhccpParam::dspin_set(dspin_send_data,
5859	0,
5860	DspinDhccpParam::FROM_L1_BC);
5861
5862	if(r_cc_send_last_client.read() == 0) // dcache active request
5863	{
5864	uint64_t dest = (uint64_t)r_dcache_cc_send_nline.read()
5865	>> (m_nline_width - m_x_width - m_y_width)
5866	<< (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
5867
5868	DspinDhccpParam::dspin_set(dspin_send_data,
5869	dest,
5870	DspinDhccpParam::CLEANUP_DEST);
5871
5872	DspinDhccpParam::dspin_set(dspin_send_data,
5873	r_dcache_cc_send_nline.read() & 0x300000000ULL,
5874	DspinDhccpParam::CLEANUP_NLINE_MSB);
5875
5876	DspinDhccpParam::dspin_set(dspin_send_data,
5877	r_dcache_cc_send_way.read(),
5878	DspinDhccpParam::CLEANUP_WAY_INDEX);
5879
5880	DspinDhccpParam::dspin_set(dspin_send_data,
5881	DspinDhccpParam::TYPE_CLEANUP_DATA,
5882	DspinDhccpParam::FROM_L1_TYPE);
5883	}
5884	else // icache active request
5885	{
5886	uint64_t dest = (uint64_t)r_icache_cc_send_nline.read()
5887	>> (m_nline_width - m_x_width - m_y_width)
5888	<< (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
5889
5890	DspinDhccpParam::dspin_set(dspin_send_data,
5891	dest,
5892	DspinDhccpParam::CLEANUP_DEST);
5893
5894	DspinDhccpParam::dspin_set(dspin_send_data,
5895	r_icache_cc_send_nline.read() & 0x300000000ULL,
5896	DspinDhccpParam::CLEANUP_NLINE_MSB);
5897
5898	DspinDhccpParam::dspin_set(dspin_send_data,
5899	r_icache_cc_send_way.read(),
5900	DspinDhccpParam::CLEANUP_WAY_INDEX);
5901
5902	DspinDhccpParam::dspin_set(dspin_send_data,
5903	DspinDhccpParam::TYPE_CLEANUP_INST,
5904	DspinDhccpParam::FROM_L1_TYPE);
5905	}
5906	// send flit
5907	p_dspin_out.data = dspin_send_data;
5908	p_dspin_out.write = true;
5909	break;
5910	}
5911	///////////////////////
5912	case CC_SEND_CLEANUP_2:
5913	{
5914	// initialize dspin send data
5915	DspinDhccpParam::dspin_set(dspin_send_data,
5916	1,
5917	DspinDhccpParam::FROM_L1_EOP);
5918
5919	if(r_cc_send_last_client.read() == 0) // dcache active request
5920	{
5921	DspinDhccpParam::dspin_set(dspin_send_data,
5922	r_dcache_cc_send_nline.read() & 0xFFFFFFFFULL,
5923	DspinDhccpParam::CLEANUP_NLINE_LSB);
5924	}
5925	else // icache active request
5926	{
5927	DspinDhccpParam::dspin_set(dspin_send_data,
5928	r_icache_cc_send_nline.read() & 0xFFFFFFFFULL,
5929	DspinDhccpParam::CLEANUP_NLINE_LSB);
5930	}
5931	// send flit
5932	p_dspin_out.data = dspin_send_data;
5933	p_dspin_out.write = true;
5934	break;
5935	}
5936	///////////////////////
5937	case CC_SEND_MULTI_ACK:
5938	{
5939	// initialize dspin send data
5940	DspinDhccpParam::dspin_set(dspin_send_data,
5941	1,
5942	DspinDhccpParam::FROM_L1_EOP);
5943	DspinDhccpParam::dspin_set(dspin_send_data,
5944	0,
5945	DspinDhccpParam::FROM_L1_BC);
5946	DspinDhccpParam::dspin_set(dspin_send_data,
5947	DspinDhccpParam::TYPE_MULTI_ACK,
5948	DspinDhccpParam::FROM_L1_TYPE);
5949
5950	if(r_cc_send_last_client.read() == 0) // dcache active request
5951	{
5952	uint64_t dest = (uint64_t)r_dcache_cc_send_nline.read()
5953	>> (m_nline_width - m_x_width - m_y_width)
5954	<< (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
5955
5956	DspinDhccpParam::dspin_set(dspin_send_data,
5957	dest,
5958	DspinDhccpParam::MULTI_ACK_DEST);
5959
5960	DspinDhccpParam::dspin_set(dspin_send_data,
5961	r_dcache_cc_send_updt_tab_idx.read(),
5962	DspinDhccpParam::MULTI_ACK_UPDT_INDEX);
5963	}
5964	else // icache active request
5965	{
5966	uint64_t dest = (uint64_t)r_icache_cc_send_nline.read()
5967	>> (m_nline_width - m_x_width - m_y_width)
5968	<< (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
5969
5970
5971	DspinDhccpParam::dspin_set(dspin_send_data,
5972	dest,
5973	DspinDhccpParam::MULTI_ACK_DEST);
5974
5975	DspinDhccpParam::dspin_set(dspin_send_data,
5976	r_icache_cc_send_updt_tab_idx.read(),
5977	DspinDhccpParam::MULTI_ACK_UPDT_INDEX);
5978	}
5979	// send flit
5980	p_dspin_out.data = dspin_send_data;
5981	p_dspin_out.write = true;
5982	break;
5983	}
5984	} // end switch CC_SEND FSM
5985
5986	// Receive coherence packets
5987	// It depends on the CC_RECEIVE FSM
5988
5989	switch( r_cc_receive_fsm.read() )
5990	{
5991	/////////////////////
5992	case CC_RECEIVE_IDLE:
5993	{
5994	p_dspin_in.read = false;
5995	break;
5996	}
5997	//////////////////////
5998	case CC_RECEIVE_CLACK:
5999	{
6000	if (((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read())) or
6001	((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read())))
6002	p_dspin_in.read = true;
6003	else
6004	p_dspin_in.read = false;
6005	break;
6006	}
6007	///////////////////////////////
6008	case CC_RECEIVE_BRDCAST_HEADER:
6009	{
6010	p_dspin_in.read = true;
6011	break;
6012	}
6013	//////////////////////////////
6014	case CC_RECEIVE_BRDCAST_NLINE:
6015	{
6016	// TODO maybe we need to wait for both only to leave the state, but
6017	// not to actually post a request to an available cache => need a
6018	// flip_flop to check that ?
6019	if (not (r_cc_receive_icache_req.read()) and not (r_cc_receive_dcache_req.read()))
6020	p_dspin_in.read = true;
6021	else
6022	p_dspin_in.read = false;
6023	break;
6024	}
6025	/////////////////////////////
6026	case CC_RECEIVE_INVAL_HEADER:
6027	{
6028	if (((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read())) or
6029	((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read())))
6030	p_dspin_in.read = true;
6031	else
6032	p_dspin_in.read = false;
6033	break;
6034	}
6035	////////////////////////////
6036	case CC_RECEIVE_INVAL_NLINE:
6037	{
6038	p_dspin_in.read = true;
6039	break;
6040	}
6041	////////////////////////////
6042	case CC_RECEIVE_UPDT_HEADER:
6043	{
6044	if (((r_cc_receive_data_ins.read() == 0) and
6045	not r_cc_receive_dcache_req.read() and
6046	r_cc_receive_updt_fifo_be.empty())
6047	or
6048	((r_cc_receive_data_ins.read() == 1) and
6049	not r_cc_receive_icache_req.read()) and
6050	r_cc_receive_updt_fifo_be.empty())
6051	p_dspin_in.read = true;
6052	else
6053	p_dspin_in.read = false;
6054	break;
6055	}
6056	///////////////////////////
6057	case CC_RECEIVE_UPDT_NLINE:
6058	{
6059	if (((r_cc_receive_data_ins.read() == 0) and
6060	not (r_cc_receive_dcache_req.read()) and
6061	r_cc_receive_updt_fifo_be.empty())
6062	or
6063	((r_cc_receive_data_ins.read() == 1) and
6064	not (r_cc_receive_icache_req.read()) and
6065	r_cc_receive_updt_fifo_be.empty()))
6066	p_dspin_in.read = true;
6067	else
6068	p_dspin_in.read = false;
6069	break;
6070	}
6071	//////////////////////////
6072	case CC_RECEIVE_UPDT_DATA:
6073	{
6074	if (r_cc_receive_updt_fifo_be.wok())
6075	p_dspin_in.read = true;
6076	else
6077	p_dspin_in.read = false;
6078	break;
6079	}
6080	} // end switch CC_RECEIVE FSM
6081
6082	} // end genMoore
6083
6084	}}
6085
6086	// Local Variables:
6087	// tab-width: 4
6088	// c-basic-offset: 4
6089	// c-file-offsets:((innamespace . 0)(inline-open . 0))
6090	// indent-tabs-mode: nil
6091	// End:
6092
6093	// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4

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