Context Navigation

source: branches/v5/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp @ 366

Last change on this file since 366 was 366, checked in by joannou, 11 years ago

In vci_cc_vcache_wrapper v5,

now using the new generic_cache_tsar write_dir method (that does not affect the tag)

File size: 228.3 KB

Line
1	/* -- c++ --
2	* File : vci_cc_vcache_wrapper.cpp
3	* Copyright (c) UPMC, Lip6, SoC
4	* Authors : Alain GREINER, Yang GAO
5	*
6	* SOCLIB_LGPL_HEADER_BEGIN
7	*
8	* This file is part of SoCLib, GNU LGPLv2.1.
9	*
10	* SoCLib is free software; you can redistribute it and/or modify it
11	* under the terms of the GNU Lesser General Public License as published
12	* by the Free Software Foundation; version 2.1 of the License.
13	*
14	* SoCLib is distributed in the hope that it will be useful, but
15	* WITHOUT ANY WARRANTY; without even the implied warranty of
16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17	* Lesser General Public License for more details.
18	*
19	* You should have received a copy of the GNU Lesser General Public
20	* License along with SoCLib; if not, write to the Free Software
21	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
22	* 02110-1301 USA
23	*
24	* SOCLIB_LGPL_HEADER_END
25	*
26	* Maintainers: cesar.fuguet-tortolero@lip6.fr
27	* alexandre.joannou@lip6.fr
28	*/
29
30	#include <cassert>
31	#include "arithmetics.h"
32	#include "../include/vci_cc_vcache_wrapper.h"
33
34	#define DEBUG_DCACHE 1
35	#define DEBUG_ICACHE 1
36	#define DEBUG_CLEANUP 1
37
38	namespace soclib {
39	namespace caba {
40
41	namespace {
42	const char *icache_fsm_state_str[] = {
43	"ICACHE_IDLE",
44
45	"ICACHE_XTN_TLB_FLUSH",
46	"ICACHE_XTN_CACHE_FLUSH",
47	"ICACHE_XTN_CACHE_FLUSH_GO",
48	"ICACHE_XTN_TLB_INVAL",
49	"ICACHE_XTN_CACHE_INVAL_VA",
50	"ICACHE_XTN_CACHE_INVAL_PA",
51	"ICACHE_XTN_CACHE_INVAL_GO",
52
53	"ICACHE_TLB_WAIT",
54
55	"ICACHE_MISS_SELECT",
56	"ICACHE_MISS_CLEAN",
57	"ICACHE_MISS_WAIT",
58	"ICACHE_MISS_DATA_UPDT",
59	"ICACHE_MISS_DIR_UPDT",
60
61	"ICACHE_UNC_WAIT",
62
63	"ICACHE_CC_CHECK",
64	"ICACHE_CC_INVAL",
65	"ICACHE_CC_UPDT",
66	"ICACHE_CC_BROADCAST",
67	"ICACHE_CC_SEND_WAIT",
68	};
69
70	const char *dcache_fsm_state_str[] = {
71	"DCACHE_IDLE",
72
73	"DCACHE_TLB_MISS",
74	"DCACHE_TLB_PTE1_GET",
75	"DCACHE_TLB_PTE1_SELECT",
76	"DCACHE_TLB_PTE1_UPDT",
77	"DCACHE_TLB_PTE2_GET",
78	"DCACHE_TLB_PTE2_SELECT",
79	"DCACHE_TLB_PTE2_UPDT",
80	"DCACHE_TLB_LR_UPDT",
81	"DCACHE_TLB_LR_WAIT",
82	"DCACHE_TLB_RETURN",
83
84	"DCACHE_XTN_SWITCH",
85	"DCACHE_XTN_SYNC",
86	"DCACHE_XTN_IC_INVAL_VA",
87	"DCACHE_XTN_IC_FLUSH",
88	"DCACHE_XTN_IC_INVAL_PA",
89	"DCACHE_XTN_IT_INVAL",
90	"DCACHE_XTN_DC_FLUSH",
91	"DCACHE_XTN_DC_FLUSH_GO",
92	"DCACHE_XTN_DC_INVAL_VA",
93	"DCACHE_XTN_DC_INVAL_PA",
94	"DCACHE_XTN_DC_INVAL_END",
95	"DCACHE_XTN_DC_INVAL_GO",
96	"DCACHE_XTN_DT_INVAL",
97
98	"DCACHE_DIRTY_PTE_GET",
99	"DCACHE_DIRTY_WAIT",
100
101	"DCACHE_MISS_SELECT",
102	"DCACHE_MISS_CLEAN",
103	"DCACHE_MISS_WAIT",
104	"DCACHE_MISS_DATA_UPDT",
105	"DCACHE_MISS_DIR_UPDT",
106
107	"DCACHE_UNC_WAIT",
108	"DCACHE_LL_WAIT",
109	"DCACHE_SC_WAIT",
110
111	"DCACHE_CC_CHECK",
112	"DCACHE_CC_INVAL",
113	"DCACHE_CC_UPDT",
114	"DCACHE_CC_BROADCAST",
115	"DCACHE_CC_SEND_WAIT",
116
117	"DCACHE_INVAL_TLB_SCAN",
118	};
119
120	const char *cmd_fsm_state_str[] = {
121	"CMD_IDLE",
122	"CMD_INS_MISS",
123	"CMD_INS_UNC",
124	"CMD_DATA_MISS",
125	"CMD_DATA_UNC",
126	"CMD_DATA_WRITE",
127	"CMD_DATA_LL",
128	"CMD_DATA_SC",
129	"CMD_DATA_CAS",
130	};
131
132	const char *rsp_fsm_state_str[] = {
133	"RSP_IDLE",
134	"RSP_INS_MISS",
135	"RSP_INS_UNC",
136	"RSP_DATA_MISS",
137	"RSP_DATA_UNC",
138	"RSP_DATA_LL",
139	"RSP_DATA_WRITE",
140	};
141
142	const char *cc_receive_fsm_state_str[] = {
143	"CC_RECEIVE_IDLE",
144	"CC_RECEIVE_CLACK",
145	"CC_RECEIVE_BRDCAST_HEADER",
146	"CC_RECEIVE_BRDCAST_NLINE",
147	"CC_RECEIVE_INVAL_HEADER",
148	"CC_RECEIVE_INVAL_NLINE",
149	"CC_RECEIVE_UPDT_HEADER",
150	"CC_RECEIVE_UPDT_NLINE",
151	"CC_RECEIVE_UPDT_DATA",
152	};
153
154	const char *cc_send_fsm_state_str[] = {
155	"CC_SEND_IDLE",
156	"CC_SEND_CLEANUP_1",
157	"CC_SEND_CLEANUP_2",
158	"CC_SEND_MULTI_ACK",
159	};
160	}
161
162	#define tmpl(...) template<typename vci_param, typename iss_t> __VA_ARGS__ VciCcVCacheWrapper<vci_param, iss_t>
163
164	using namespace soclib::common;
165
166	/////////////////////////////////
167	tmpl(/**/)::VciCcVCacheWrapper(
168	sc_module_name name,
169	const int proc_id,
170	const MappingTable &mtd,
171	const IntTab &srcid,
172	const size_t cc_global_id,
173	const size_t itlb_ways,
174	const size_t itlb_sets,
175	const size_t dtlb_ways,
176	const size_t dtlb_sets,
177	const size_t icache_ways,
178	const size_t icache_sets,
179	const size_t icache_words,
180	const size_t dcache_ways,
181	const size_t dcache_sets,
182	const size_t dcache_words,
183	const size_t wbuf_nlines,
184	const size_t wbuf_nwords,
185	const size_t x_width,
186	const size_t y_width,
187	const uint32_t max_frozen_cycles,
188	const uint32_t debug_start_cycle,
189	const bool debug_ok )
190	: soclib::caba::BaseModule(name),
191
192	p_clk("p_clk"),
193	p_resetn("p_resetn"),
194	p_vci("p_vci"),
195	p_dspin_in("p_dspin_in"),
196	p_dspin_out("p_dspin_out"),
197
198	m_cacheability_table( mtd.getCacheabilityTable() ),
199	m_srcid( mtd.indexForId(srcid) ),
200	m_cc_global_id( cc_global_id ),
201	m_nline_width( vci_param::N - (uint32_log2(dcache_words)) - 2 ),
202	m_itlb_ways( itlb_ways ),
203	m_itlb_sets( itlb_sets ),
204	m_dtlb_ways( dtlb_ways ),
205	m_dtlb_sets( dtlb_sets ),
206	m_icache_ways( icache_ways ),
207	m_icache_sets( icache_sets ),
208	m_icache_yzmask( (~0)<<(uint32_log2(icache_words) + 2) ),
209	m_icache_words( icache_words ),
210	m_dcache_ways( dcache_ways ),
211	m_dcache_sets( dcache_sets ),
212	m_dcache_yzmask( (~0)<<(uint32_log2(dcache_words) + 2) ),
213	m_dcache_words( dcache_words ),
214	m_x_width( x_width ),
215	m_y_width( y_width ),
216	m_proc_id( proc_id ),
217	m_max_frozen_cycles( max_frozen_cycles ),
218	m_paddr_nbits( vci_param::N ),
219	m_debug_start_cycle( debug_start_cycle ),
220	m_debug_ok( debug_ok ),
221
222	r_mmu_ptpr("r_mmu_ptpr"),
223	r_mmu_mode("r_mmu_mode"),
224	r_mmu_word_lo("r_mmu_word_lo"),
225	r_mmu_word_hi("r_mmu_word_hi"),
226	r_mmu_ibvar("r_mmu_ibvar"),
227	r_mmu_dbvar("r_mmu_dbvar"),
228	r_mmu_ietr("r_mmu_ietr"),
229	r_mmu_detr("r_mmu_detr"),
230
231	r_icache_fsm("r_icache_fsm"),
232	r_icache_fsm_save("r_icache_fsm_save"),
233	r_icache_vci_paddr("r_icache_vci_paddr"),
234	r_icache_vaddr_save("r_icache_vaddr_save"),
235
236	r_icache_miss_way("r_icache_miss_way"),
237	r_icache_miss_set("r_icache_miss_set"),
238	r_icache_miss_word("r_icache_miss_word"),
239	r_icache_miss_inval("r_icache_miss_inval"),
240	r_icache_miss_clack("r_icache_miss_clack"),
241
242	r_icache_cc_way("r_icache_cc_way"),
243	r_icache_cc_set("r_icache_cc_set"),
244	r_icache_cc_word("r_icache_cc_word"),
245	r_icache_cc_need_write("r_icache_cc_need_write"),
246
247	r_icache_flush_count("r_icache_flush_count"),
248
249	r_icache_miss_req("r_icache_miss_req"),
250	r_icache_unc_req("r_icache_unc_req"),
251
252	r_icache_tlb_miss_req("r_icache_tlb_read_req"),
253	r_icache_tlb_rsp_error("r_icache_tlb_rsp_error"),
254
255	r_icache_cc_send_req("r_icache_cc_send_req"),
256	r_icache_cc_send_type("r_icache_cc_send_type"),
257	r_icache_cc_send_nline("r_icache_cc_send_nline"),
258	r_icache_cc_send_way("r_icache_cc_send_way"),
259	r_icache_cc_send_updt_tab_idx("r_icache_cc_send_updt_tab_idx"),
260
261	r_dcache_fsm("r_dcache_fsm"),
262	r_dcache_fsm_cc_save("r_dcache_fsm_cc_save"),
263	r_dcache_fsm_scan_save("r_dcache_fsm_scan_save"),
264
265	r_dcache_wbuf_req("r_dcache_wbuf_req"),
266	r_dcache_updt_req("r_dcache_updt_req"),
267	r_dcache_save_vaddr("r_dcache_save_vaddr"),
268	r_dcache_save_wdata("r_dcache_save_wdata"),
269	r_dcache_save_be("r_dcache_save_be"),
270	r_dcache_save_paddr("r_dcache_save_paddr"),
271	r_dcache_save_cacheable("r_dcache_save_cacheable"),
272	r_dcache_save_cache_way("r_dcache_save_cache_way"),
273	r_dcache_save_cache_set("r_dcache_save_cache_set"),
274	r_dcache_save_cache_word("r_dcache_save_cache_word"),
275
276	r_dcache_dirty_paddr("r_dcache_dirty_paddr"),
277	r_dcache_dirty_way("r_dcache_dirty_way"),
278	r_dcache_dirty_set("r_dcache_dirty_set"),
279
280	r_dcache_vci_paddr("r_dcache_vci_paddr"),
281	r_dcache_vci_miss_req("r_dcache_vci_miss_req"),
282	r_dcache_vci_unc_req("r_dcache_vci_unc_req"),
283	r_dcache_vci_unc_be("r_dcache_vci_unc_be"),
284	r_dcache_vci_cas_req("r_dcache_vci_cas_req"),
285	r_dcache_vci_cas_old("r_dcache_vci_cas_old"),
286	r_dcache_vci_cas_new("r_dcache_vci_cas_new"),
287	r_dcache_vci_ll_req("r_dcache_vci_ll_req"),
288	r_dcache_vci_sc_req("r_dcache_vci_sc_req"),
289	r_dcache_vci_sc_data("r_dcache_vci_sc_data"),
290
291	r_dcache_xtn_way("r_dcache_xtn_way"),
292	r_dcache_xtn_set("r_dcache_xtn_set"),
293
294	r_dcache_pending_unc_write("r_dcache_pending_unc_write"),
295
296	r_dcache_miss_type("r_dcache_miss_type"),
297	r_dcache_miss_word("r_dcache_miss_word"),
298	r_dcache_miss_way("r_dcache_miss_way"),
299	r_dcache_miss_set("r_dcache_miss_set"),
300	r_dcache_miss_inval("r_dcache_miss_inval"),
301
302	r_dcache_cc_way("r_dcache_cc_way"),
303	r_dcache_cc_set("r_dcache_cc_set"),
304	r_dcache_cc_word("r_dcache_cc_word"),
305	r_dcache_cc_need_write("r_dcache_cc_need_write"),
306
307	r_dcache_flush_count("r_dcache_flush_count"),
308
309	r_dcache_ll_rsp_count("r_dcache_ll_rsp_count"),
310
311	r_dcache_tlb_vaddr("r_dcache_tlb_vaddr"),
312	r_dcache_tlb_ins("r_dcache_tlb_ins"),
313	r_dcache_tlb_pte_flags("r_dcache_tlb_pte_flags"),
314	r_dcache_tlb_pte_ppn("r_dcache_tlb_pte_ppn"),
315	r_dcache_tlb_cache_way("r_dcache_tlb_cache_way"),
316	r_dcache_tlb_cache_set("r_dcache_tlb_cache_set"),
317	r_dcache_tlb_cache_word("r_dcache_tlb_cache_word"),
318	r_dcache_tlb_way("r_dcache_tlb_way"),
319	r_dcache_tlb_set("r_dcache_tlb_set"),
320
321	r_dcache_tlb_inval_line("r_dcache_tlb_inval_line"),
322	r_dcache_tlb_inval_set("r_dcache_tlb_inval_set"),
323
324	r_dcache_xtn_req("r_dcache_xtn_req"),
325	r_dcache_xtn_opcode("r_dcache_xtn_opcode"),
326
327	r_dcache_cc_send_req("r_dcache_cc_send_req"),
328	r_dcache_cc_send_type("r_dcache_cc_send_type"),
329	r_dcache_cc_send_nline("r_dcache_cc_send_nline"),
330	r_dcache_cc_send_way("r_dcache_cc_send_way"),
331	r_dcache_cc_send_updt_tab_idx("r_dcache_cc_send_updt_tab_idx"),
332
333	r_vci_cmd_fsm("r_vci_cmd_fsm"),
334	r_vci_cmd_min("r_vci_cmd_min"),
335	r_vci_cmd_max("r_vci_cmd_max"),
336	r_vci_cmd_cpt("r_vci_cmd_cpt"),
337	r_vci_cmd_imiss_prio("r_vci_cmd_imiss_prio"),
338
339	r_vci_rsp_fsm("r_vci_rsp_fsm"),
340	r_vci_rsp_cpt("r_vci_rsp_cpt"),
341	r_vci_rsp_ins_error("r_vci_rsp_ins_error"),
342	r_vci_rsp_data_error("r_vci_rsp_data_error"),
343	r_vci_rsp_fifo_icache("r_vci_rsp_fifo_icache", 2), // 2 words depth
344	r_vci_rsp_fifo_dcache("r_vci_rsp_fifo_dcache", 2), // 2 words depth
345
346	r_cc_send_fsm("r_cc_send_fsm"),
347	r_cc_send_last_client("r_cc_send_last_client"),
348
349	r_cc_receive_fsm("r_cc_receive_fsm"),
350	r_cc_receive_data_ins("r_cc_receive_data_ins"),
351	r_cc_receive_word_idx("r_cc_receive_word_idx"),
352	r_cc_receive_updt_fifo_be("r_cc_receive_updt_fifo_be", 2), // 2 words depth
353	r_cc_receive_updt_fifo_data("r_cc_receive_updt_fifo_data", 2), // 2 words depth
354	r_cc_receive_updt_fifo_eop("r_cc_receive_updt_fifo_eop", 2), // 2 words depth
355
356	r_cc_receive_icache_req("r_cc_receive_icache_req"),
357	r_cc_receive_icache_type("r_cc_receive_icache_type"),
358	r_cc_receive_icache_way("r_cc_receive_icache_way"),
359	r_cc_receive_icache_set("r_cc_receive_icache_set"),
360	r_cc_receive_icache_updt_tab_idx("r_cc_receive_icache_updt_tab_idx"),
361	r_cc_receive_icache_nline("r_cc_receive_icache_nline"),
362
363	r_cc_receive_dcache_req("r_cc_receive_dcache_req"),
364	r_cc_receive_dcache_type("r_cc_receive_dcache_type"),
365	r_cc_receive_dcache_way("r_cc_receive_dcache_way"),
366	r_cc_receive_dcache_set("r_cc_receive_dcache_set"),
367	r_cc_receive_dcache_updt_tab_idx("r_cc_receive_dcache_updt_tab_idx"),
368	r_cc_receive_dcache_nline("r_cc_receive_dcache_nline"),
369
370	r_iss(this->name(), proc_id),
371	r_wbuf("wbuf", wbuf_nwords, wbuf_nlines, dcache_words ),
372	r_icache("icache", icache_ways, icache_sets, icache_words),
373	r_dcache("dcache", dcache_ways, dcache_sets, dcache_words),
374	r_itlb("itlb", proc_id, itlb_ways,itlb_sets,vci_param::N),
375	r_dtlb("dtlb", proc_id, dtlb_ways,dtlb_sets,vci_param::N)
376	{
377	assert( ((icache_words*vci_param::B) < (1<<vci_param::K)) and
378	"Need more PLEN bits.");
379
380	assert( (vci_param::T > 2) and ((1<<(vci_param::T-1)) >= (wbuf_nlines)) and
381	"Need more TRDID bits.");
382
383	assert( (icache_words == dcache_words) and
384	"icache_words and dcache_words parameters must be equal");
385
386	assert( (itlb_sets == dtlb_sets) and
387	"itlb_sets and dtlb_sets parameters must be etqual");
388
389	assert( (itlb_ways == dtlb_ways) and
390	"itlb_ways and dtlb_ways parameters must be etqual");
391
392	r_mmu_params = (uint32_log2(m_dtlb_ways) << 29) \| (uint32_log2(m_dtlb_sets) << 25) \|
393	(uint32_log2(m_dcache_ways) << 22) \| (uint32_log2(m_dcache_sets) << 18) \|
394	(uint32_log2(m_itlb_ways) << 15) \| (uint32_log2(m_itlb_sets) << 11) \|
395	(uint32_log2(m_icache_ways) << 8) \| (uint32_log2(m_icache_sets) << 4) \|
396	(uint32_log2(m_icache_words<<2));
397
398	r_mmu_release = (uint32_t)(1 << 16) \| 0x1;
399
400	r_dcache_in_tlb = new bool[dcache_ways*dcache_sets];
401	r_dcache_contains_ptd = new bool[dcache_ways*dcache_sets];
402
403	SC_METHOD(transition);
404	dont_initialize();
405	sensitive << p_clk.pos();
406
407	SC_METHOD(genMoore);
408	dont_initialize();
409	sensitive << p_clk.neg();
410
411	typename iss_t::CacheInfo cache_info;
412	cache_info.has_mmu = true;
413	cache_info.icache_line_size = icache_words*sizeof(uint32_t);
414	cache_info.icache_assoc = icache_ways;
415	cache_info.icache_n_lines = icache_sets;
416	cache_info.dcache_line_size = dcache_words*sizeof(uint32_t);
417	cache_info.dcache_assoc = dcache_ways;
418	cache_info.dcache_n_lines = dcache_sets;
419	r_iss.setCacheInfo(cache_info);
420	}
421
422	/////////////////////////////////////
423	tmpl(/**/)::~VciCcVCacheWrapper()
424	/////////////////////////////////////
425	{
426	delete [] r_dcache_in_tlb;
427	delete [] r_dcache_contains_ptd;
428	}
429
430	////////////////////////
431	tmpl(void)::print_cpi()
432	////////////////////////
433	{
434	std::cout << name() << " CPI = "
435	<< (float)m_cpt_total_cycles/(m_cpt_total_cycles - m_cpt_frz_cycles) << std::endl ;
436	}
437
438	////////////////////////////////////
439	tmpl(void)::print_trace(size_t mode)
440	////////////////////////////////////
441	{
442	// b0 : write buffer trace
443	// b1 : write buffer verbose
444	// b2 : dcache trace
445	// b3 : icache trace
446	// b4 : dtlb trace
447	// b5 : itlb trace
448
449	std::cout << std::dec << "PROC " << name() << std::endl;
450
451	std::cout << " " << m_ireq << std::endl;
452	std::cout << " " << m_irsp << std::endl;
453	std::cout << " " << m_dreq << std::endl;
454	std::cout << " " << m_drsp << std::endl;
455
456	std::cout << " " << icache_fsm_state_str[r_icache_fsm.read()]
457	<< " \| " << dcache_fsm_state_str[r_dcache_fsm.read()]
458	<< " \| " << cmd_fsm_state_str[r_vci_cmd_fsm.read()]
459	<< " \| " << rsp_fsm_state_str[r_vci_rsp_fsm.read()]
460	<< " \| " << cc_receive_fsm_state_str[r_cc_receive_fsm.read()]
461	<< " \| " << cc_send_fsm_state_str[r_cc_send_fsm.read()];
462	if (r_dcache_updt_req.read() ) std::cout << " \| P1_UPDT";
463	if (r_dcache_wbuf_req.read() ) std::cout << " \| P1_WBUF";
464	std::cout << std::endl;
465
466	if(mode & 0x01)
467	{
468	r_wbuf.printTrace((mode>>1)&1);
469	}
470	if(mode & 0x04)
471	{
472	std::cout << " Data Cache" << std::endl;
473	r_dcache.printTrace();
474	}
475	if(mode & 0x08)
476	{
477	std::cout << " Instruction Cache" << std::endl;
478	r_icache.printTrace();
479	}
480	if(mode & 0x10)
481	{
482	std::cout << " Data TLB" << std::endl;
483	r_dtlb.printTrace();
484	}
485	if(mode & 0x20)
486	{
487	std::cout << " Instruction TLB" << std::endl;
488	r_itlb.printTrace();
489	}
490	}
491
492	//////////////////////////////////////////
493	tmpl(void)::cache_monitor( paddr_t addr )
494	//////////////////////////////////////////
495	{
496	size_t cache_way;
497	size_t cache_set;
498	size_t cache_word;
499	uint32_t cache_rdata;
500	bool cache_hit = r_dcache.read_neutral( addr,
501	&cache_rdata,
502	&cache_way,
503	&cache_set,
504	&cache_word );
505	bool icache_hit = r_icache.read_neutral( addr,
506	&cache_rdata,
507	&cache_way,
508	&cache_set,
509	&cache_word );
510	if ( cache_hit != m_debug_previous_hit )
511	{
512	std::cout << "PROC " << name()
513	<< " dcache change at cycle " << std::dec << m_cpt_total_cycles
514	<< " for adresse " << std::hex << addr
515	<< " / HIT = " << std::dec << cache_hit << std::endl;
516	m_debug_previous_hit = cache_hit;
517	}
518	if ( icache_hit != m_idebug_previous_hit )
519	{
520	std::cout << "PROC " << name()
521	<< " icache change at cycle " << std::dec << m_cpt_total_cycles
522	<< " for adresse " << std::hex << addr
523	<< " / HIT = " << icache_hit << std::endl;
524	m_idebug_previous_hit = icache_hit;
525	}
526	}
527
528	/*
529	////////////////////////
530	tmpl(void)::print_stats()
531	////////////////////////
532	{
533	float run_cycles = (float)(m_cpt_total_cycles - m_cpt_frz_cycles);
534	std::cout << name() << std::endl
535	<< "- CPI = " << (float)m_cpt_total_cycles/run_cycles << std::endl
536	<< "- READ RATE = " << (float)m_cpt_read/run_cycles << std::endl
537	<< "- WRITE RATE = " << (float)m_cpt_write/run_cycles << std::endl
538	<< "- IMISS_RATE = " << (float)m_cpt_ins_miss/m_cpt_ins_read << std::endl
539	<< "- DMISS RATE = " << (float)m_cpt_data_miss/(m_cpt_read-m_cpt_unc_read) << std::endl
540	<< "- INS MISS COST = " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl
541	<< "- DATA MISS COST = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl
542	<< "- WRITE COST = " << (float)m_cost_write_frz/m_cpt_write << std::endl
543	<< "- UNC COST = " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl
544	<< "- UNCACHED READ RATE = " << (float)m_cpt_unc_read/m_cpt_read << std::endl
545	<< "- CACHED WRITE RATE = " << (float)m_cpt_write_cached/m_cpt_write << std::endl
546	<< "- INS TLB MISS RATE = " << (float)m_cpt_ins_tlb_miss/m_cpt_ins_tlb_read << std::endl
547	<< "- DATA TLB MISS RATE = " << (float)m_cpt_data_tlb_miss/m_cpt_data_tlb_read << std::endl
548	<< "- ITLB MISS COST = " << (float)m_cost_ins_tlb_miss_frz/m_cpt_ins_tlb_miss << std::endl
549	<< "- DTLB MISS COST = " << (float)m_cost_data_tlb_miss_frz/m_cpt_data_tlb_miss << std::endl
550	<< "- ITLB UPDATE ACC COST = " << (float)m_cost_ins_tlb_update_acc_frz/m_cpt_ins_tlb_update_acc << std::endl
551	<< "- DTLB UPDATE ACC COST = " << (float)m_cost_data_tlb_update_acc_frz/m_cpt_data_tlb_update_acc << std::endl
552	<< "- DTLB UPDATE DIRTY COST = " << (float)m_cost_data_tlb_update_dirty_frz/m_cpt_data_tlb_update_dirty << std::endl
553	<< "- ITLB HIT IN DCACHE RATE= " << (float)m_cpt_ins_tlb_hit_dcache/m_cpt_ins_tlb_miss << std::endl
554	<< "- DTLB HIT IN DCACHE RATE= " << (float)m_cpt_data_tlb_hit_dcache/m_cpt_data_tlb_miss << std::endl
555	<< "- DCACHE FROZEN BY ITLB = " << (float)m_cost_ins_tlb_occup_cache_frz/m_cpt_dcache_frz_cycles << std::endl
556	<< "- DCACHE FOR TLB % = " << (float)m_cpt_tlb_occup_dcache/(m_dcache_ways*m_dcache_sets) << std::endl
557	<< "- NB CC BROADCAST = " << m_cpt_cc_broadcast << std::endl
558	<< "- NB CC UPDATE DATA = " << m_cpt_cc_update_data << std::endl
559	<< "- NB CC INVAL DATA = " << m_cpt_cc_inval_data << std::endl
560	<< "- NB CC INVAL INS = " << m_cpt_cc_inval_ins << std::endl
561	<< "- CC BROADCAST COST = " << (float)m_cost_broadcast_frz/m_cpt_cc_broadcast << std::endl
562	<< "- CC UPDATE DATA COST = " << (float)m_cost_updt_data_frz/m_cpt_cc_update_data << std::endl
563	<< "- CC INVAL DATA COST = " << (float)m_cost_inval_data_frz/m_cpt_cc_inval_data << std::endl
564	<< "- CC INVAL INS COST = " << (float)m_cost_inval_ins_frz/m_cpt_cc_inval_ins << std::endl
565	<< "- NB CC CLEANUP DATA = " << m_cpt_cc_cleanup_data << std::endl
566	<< "- NB CC CLEANUP INS = " << m_cpt_cc_cleanup_ins << std::endl
567	<< "- IMISS TRANSACTION = " << (float)m_cost_imiss_transaction/m_cpt_imiss_transaction << std::endl
568	<< "- DMISS TRANSACTION = " << (float)m_cost_dmiss_transaction/m_cpt_dmiss_transaction << std::endl
569	<< "- UNC TRANSACTION = " << (float)m_cost_unc_transaction/m_cpt_unc_transaction << std::endl
570	<< "- WRITE TRANSACTION = " << (float)m_cost_write_transaction/m_cpt_write_transaction << std::endl
571	<< "- WRITE LENGTH = " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl
572	<< "- ITLB MISS TRANSACTION = " << (float)m_cost_itlbmiss_transaction/m_cpt_itlbmiss_transaction << std::endl
573	<< "- DTLB MISS TRANSACTION = " << (float)m_cost_dtlbmiss_transaction/m_cpt_dtlbmiss_transaction << std::endl;
574	}
575
576	////////////////////////
577	tmpl(void)::clear_stats()
578	////////////////////////
579	{
580	m_cpt_dcache_data_read = 0;
581	m_cpt_dcache_data_write = 0;
582	m_cpt_dcache_dir_read = 0;
583	m_cpt_dcache_dir_write = 0;
584	m_cpt_icache_data_read = 0;
585	m_cpt_icache_data_write = 0;
586	m_cpt_icache_dir_read = 0;
587	m_cpt_icache_dir_write = 0;
588
589	m_cpt_frz_cycles = 0;
590	m_cpt_dcache_frz_cycles = 0;
591	m_cpt_total_cycles = 0;
592
593	m_cpt_read = 0;
594	m_cpt_write = 0;
595	m_cpt_data_miss = 0;
596	m_cpt_ins_miss = 0;
597	m_cpt_unc_read = 0;
598	m_cpt_write_cached = 0;
599	m_cpt_ins_read = 0;
600
601	m_cost_write_frz = 0;
602	m_cost_data_miss_frz = 0;
603	m_cost_unc_read_frz = 0;
604	m_cost_ins_miss_frz = 0;
605
606	m_cpt_imiss_transaction = 0;
607	m_cpt_dmiss_transaction = 0;
608	m_cpt_unc_transaction = 0;
609	m_cpt_write_transaction = 0;
610	m_cpt_icache_unc_transaction = 0;
611
612	m_cost_imiss_transaction = 0;
613	m_cost_dmiss_transaction = 0;
614	m_cost_unc_transaction = 0;
615	m_cost_write_transaction = 0;
616	m_cost_icache_unc_transaction = 0;
617	m_length_write_transaction = 0;
618
619	m_cpt_ins_tlb_read = 0;
620	m_cpt_ins_tlb_miss = 0;
621	m_cpt_ins_tlb_update_acc = 0;
622
623	m_cpt_data_tlb_read = 0;
624	m_cpt_data_tlb_miss = 0;
625	m_cpt_data_tlb_update_acc = 0;
626	m_cpt_data_tlb_update_dirty = 0;
627	m_cpt_ins_tlb_hit_dcache = 0;
628	m_cpt_data_tlb_hit_dcache = 0;
629	m_cpt_ins_tlb_occup_cache = 0;
630	m_cpt_data_tlb_occup_cache = 0;
631
632	m_cost_ins_tlb_miss_frz = 0;
633	m_cost_data_tlb_miss_frz = 0;
634	m_cost_ins_tlb_update_acc_frz = 0;
635	m_cost_data_tlb_update_acc_frz = 0;
636	m_cost_data_tlb_update_dirty_frz = 0;
637	m_cost_ins_tlb_occup_cache_frz = 0;
638	m_cost_data_tlb_occup_cache_frz = 0;
639
640	m_cpt_itlbmiss_transaction = 0;
641	m_cpt_itlb_ll_transaction = 0;
642	m_cpt_itlb_sc_transaction = 0;
643	m_cpt_dtlbmiss_transaction = 0;
644	m_cpt_dtlb_ll_transaction = 0;
645	m_cpt_dtlb_sc_transaction = 0;
646	m_cpt_dtlb_ll_dirty_transaction = 0;
647	m_cpt_dtlb_sc_dirty_transaction = 0;
648
649	m_cost_itlbmiss_transaction = 0;
650	m_cost_itlb_ll_transaction = 0;
651	m_cost_itlb_sc_transaction = 0;
652	m_cost_dtlbmiss_transaction = 0;
653	m_cost_dtlb_ll_transaction = 0;
654	m_cost_dtlb_sc_transaction = 0;
655	m_cost_dtlb_ll_dirty_transaction = 0;
656	m_cost_dtlb_sc_dirty_transaction = 0;
657
658	m_cpt_cc_update_data = 0;
659	m_cpt_cc_inval_ins = 0;
660	m_cpt_cc_inval_data = 0;
661	m_cpt_cc_broadcast = 0;
662
663	m_cost_updt_data_frz = 0;
664	m_cost_inval_ins_frz = 0;
665	m_cost_inval_data_frz = 0;
666	m_cost_broadcast_frz = 0;
667
668	m_cpt_cc_cleanup_data = 0;
669	m_cpt_cc_cleanup_ins = 0;
670	}
671
672	*/
673
674	/////////////////////////
675	tmpl(void)::transition()
676	/////////////////////////
677	{
678	#define LLSCLocalTable GenericLLSCLocalTable<8000, 1, paddr_t, vci_trdid_t, vci_data_t>
679	if ( not p_resetn.read() )
680	{
681	r_iss.reset();
682	r_wbuf.reset();
683	r_icache.reset();
684	r_dcache.reset();
685	r_itlb.reset();
686	r_dtlb.reset();
687
688	r_dcache_fsm = DCACHE_IDLE;
689	r_icache_fsm = ICACHE_IDLE;
690	r_vci_cmd_fsm = CMD_IDLE;
691	r_vci_rsp_fsm = RSP_IDLE;
692	r_cc_receive_fsm = CC_RECEIVE_IDLE;
693	r_cc_send_fsm = CC_SEND_IDLE;
694
695	// reset dcache directory extension
696	for (size_t i=0 ; i< m_dcache_ways*m_dcache_sets ; i++)
697	{
698	r_dcache_in_tlb[i] = false;
699	r_dcache_contains_ptd[i] = false;
700	}
701
702	// Response FIFOs and cleanup buffer
703	r_vci_rsp_fifo_icache.init();
704	r_vci_rsp_fifo_dcache.init();
705
706	// ICACHE & DCACHE activated
707	r_mmu_mode = 0x3;
708
709	// No request from ICACHE FSM to CMD FSM
710	r_icache_miss_req = false;
711	r_icache_unc_req = false;
712
713	// No request from ICACHE_FSM to DCACHE FSM
714	r_icache_tlb_miss_req = false;
715
716	// No request from ICACHE_FSM to CC_SEND FSM
717	r_icache_cc_send_req = false;
718
719	// No pending write in pipeline
720	r_dcache_wbuf_req = false;
721	r_dcache_updt_req = false;
722
723	// No request from DCACHE_FSM to CMD_FSM
724	r_dcache_vci_miss_req = false;
725	r_dcache_vci_unc_req = false;
726	r_dcache_vci_cas_req = false;
727	r_dcache_vci_ll_req = false;
728	r_dcache_vci_sc_req = false;
729
730	// No uncacheable write pending
731	r_dcache_pending_unc_write = false;
732
733	// No processor XTN request pending
734	r_dcache_xtn_req = false;
735
736	// No request from DCACHE FSM to CC_SEND FSM
737	r_dcache_cc_send_req = false;
738
739	// No request from CC_RECEIVE FSM to ICACHE/DCACHE FSMs
740	r_cc_receive_icache_req = false;
741	r_cc_receive_dcache_req = false;
742
743	// last cc_send client was dcache
744	r_cc_send_last_client = false;
745
746	// No pending cleanup after a replacement
747	r_icache_miss_clack = false;
748	r_dcache_miss_clack = false;
749
750	// No signalisation of a coherence request matching a pending miss
751	r_icache_miss_inval = false;
752	r_dcache_miss_inval = false;
753
754	// No signalisation of errors
755	r_vci_rsp_ins_error = false;
756	r_vci_rsp_data_error = false;
757
758	// Debug variables
759	m_debug_previous_hit = false;
760	m_idebug_previous_hit = false;
761	m_debug_dcache_fsm = false;
762	m_debug_icache_fsm = false;
763
764	// activity counters
765	m_cpt_dcache_data_read = 0;
766	m_cpt_dcache_data_write = 0;
767	m_cpt_dcache_dir_read = 0;
768	m_cpt_dcache_dir_write = 0;
769	m_cpt_icache_data_read = 0;
770	m_cpt_icache_data_write = 0;
771	m_cpt_icache_dir_read = 0;
772	m_cpt_icache_dir_write = 0;
773
774	m_cpt_frz_cycles = 0;
775	m_cpt_total_cycles = 0;
776	m_cpt_stop_simulation = 0;
777
778	m_cpt_data_miss = 0;
779	m_cpt_ins_miss = 0;
780	m_cpt_unc_read = 0;
781	m_cpt_write_cached = 0;
782	m_cpt_ins_read = 0;
783
784	m_cost_write_frz = 0;
785	m_cost_data_miss_frz = 0;
786	m_cost_unc_read_frz = 0;
787	m_cost_ins_miss_frz = 0;
788
789	m_cpt_imiss_transaction = 0;
790	m_cpt_dmiss_transaction = 0;
791	m_cpt_unc_transaction = 0;
792	m_cpt_write_transaction = 0;
793	m_cpt_icache_unc_transaction = 0;
794
795	m_cost_imiss_transaction = 0;
796	m_cost_dmiss_transaction = 0;
797	m_cost_unc_transaction = 0;
798	m_cost_write_transaction = 0;
799	m_cost_icache_unc_transaction = 0;
800	m_length_write_transaction = 0;
801
802	m_cpt_ins_tlb_read = 0;
803	m_cpt_ins_tlb_miss = 0;
804	m_cpt_ins_tlb_update_acc = 0;
805
806	m_cpt_data_tlb_read = 0;
807	m_cpt_data_tlb_miss = 0;
808	m_cpt_data_tlb_update_acc = 0;
809	m_cpt_data_tlb_update_dirty = 0;
810	m_cpt_ins_tlb_hit_dcache = 0;
811	m_cpt_data_tlb_hit_dcache = 0;
812	m_cpt_ins_tlb_occup_cache = 0;
813	m_cpt_data_tlb_occup_cache = 0;
814
815	m_cost_ins_tlb_miss_frz = 0;
816	m_cost_data_tlb_miss_frz = 0;
817	m_cost_ins_tlb_update_acc_frz = 0;
818	m_cost_data_tlb_update_acc_frz = 0;
819	m_cost_data_tlb_update_dirty_frz = 0;
820	m_cost_ins_tlb_occup_cache_frz = 0;
821	m_cost_data_tlb_occup_cache_frz = 0;
822
823	m_cpt_ins_tlb_inval = 0;
824	m_cpt_data_tlb_inval = 0;
825	m_cost_ins_tlb_inval_frz = 0;
826	m_cost_data_tlb_inval_frz = 0;
827
828	m_cpt_cc_broadcast = 0;
829
830	m_cost_updt_data_frz = 0;
831	m_cost_inval_ins_frz = 0;
832	m_cost_inval_data_frz = 0;
833	m_cost_broadcast_frz = 0;
834
835	m_cpt_cc_cleanup_data = 0;
836	m_cpt_cc_cleanup_ins = 0;
837
838	m_cpt_itlbmiss_transaction = 0;
839	m_cpt_itlb_ll_transaction = 0;
840	m_cpt_itlb_sc_transaction = 0;
841	m_cpt_dtlbmiss_transaction = 0;
842	m_cpt_dtlb_ll_transaction = 0;
843	m_cpt_dtlb_sc_transaction = 0;
844	m_cpt_dtlb_ll_dirty_transaction = 0;
845	m_cpt_dtlb_sc_dirty_transaction = 0;
846
847	m_cost_itlbmiss_transaction = 0;
848	m_cost_itlb_ll_transaction = 0;
849	m_cost_itlb_sc_transaction = 0;
850	m_cost_dtlbmiss_transaction = 0;
851	m_cost_dtlb_ll_transaction = 0;
852	m_cost_dtlb_sc_transaction = 0;
853	m_cost_dtlb_ll_dirty_transaction = 0;
854	m_cost_dtlb_sc_dirty_transaction = 0;
855	/*
856	m_cpt_dcache_frz_cycles = 0;
857	m_cpt_read = 0;
858	m_cpt_write = 0;
859	m_cpt_cc_update_data = 0;
860	m_cpt_cc_inval_ins = 0;
861	m_cpt_cc_inval_data = 0;
862	*/
863
864	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_icache [i] = 0;
865	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_dcache [i] = 0;
866	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_cmd [i] = 0;
867	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_rsp [i] = 0;
868
869	// init the llsc reservation buffer
870	r_dcache_llsc_valid = false;
871
872	return;
873	}
874
875	// Response FIFOs default values
876	bool vci_rsp_fifo_icache_get = false;
877	bool vci_rsp_fifo_icache_put = false;
878	uint32_t vci_rsp_fifo_icache_data = 0;
879
880	bool vci_rsp_fifo_dcache_get = false;
881	bool vci_rsp_fifo_dcache_put = false;
882	uint32_t vci_rsp_fifo_dcache_data = 0;
883
884	// updt fifo
885	bool cc_receive_updt_fifo_get = false;
886	bool cc_receive_updt_fifo_put = false;
887	uint32_t cc_receive_updt_fifo_be = 0;
888	uint32_t cc_receive_updt_fifo_data = 0;
889	bool cc_receive_updt_fifo_eop = false;
890
891	#ifdef INSTRUMENTATION
892	m_cpt_fsm_dcache [r_dcache_fsm.read() ] ++;
893	m_cpt_fsm_icache [r_icache_fsm.read() ] ++;
894	m_cpt_fsm_cmd [r_vci_cmd_fsm.read()] ++;
895	m_cpt_fsm_rsp [r_vci_rsp_fsm.read()] ++;
896	m_cpt_fsm_tgt [r_tgt_fsm.read() ] ++;
897	m_cpt_fsm_cleanup [r_cleanup_cmd_fsm.read()] ++;
898	#endif
899
900	m_cpt_total_cycles++;
901
902	m_debug_icache_fsm = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok;
903	m_debug_dcache_fsm = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok;
904
905	/////////////////////////////////////////////////////////////////////
906	// Get data and instruction requests from processor
907	///////////////////////////////////////////////////////////////////////
908
909	r_iss.getRequests(m_ireq, m_dreq);
910
911	////////////////////////////////////////////////////////////////////////////////////
912	// ICACHE_FSM
913	//
914	// 1/ Coherence operations
915	// They are handled as interrupts generated by the CC_RECEIVE FSM.
916	// - There is a coherence request when r_tgt_icache_req is set.
917	// They are taken in IDLE, MISS_WAIT, MISS_DIR_UPDT, UNC_WAIT, states.
918	// - There is a cleanup ack request when r_cleanup_icache_req is set.
919	// They are taken in IDLE, MISS_SELECT, MISS_CLEAN, MISS_WAIT,
920	// MISS_DATA_UPDT, MISS_DIR_UPDT and UNC_WAIT states.
921	// - For both types of requests, actions associated to the pre-empted state
922	// are not executed. The DCACHE FSM goes to the proper sub-FSM (CC_CHECK
923	// or CC_CLACK) to execute the requested coherence operation, and returns
924	// to the pre-empted state.
925	//
926	// 2/ Processor requests
927	// They are taken in IDLE state only. In case of cache miss, or uncacheable
928	// instruction, the ICACHE FSM request a VCI transaction to CMD FSM,
929	// using the r_icache_miss_req or r_icache_unc_req flip-flops. These
930	// flip-flops are reset when the transaction starts.
931	// - In case of miss the ICACHE FSM goes to the ICACHE_MISS_SELECT state
932	// to select a slot and possibly request a cleanup transaction to the CC_SEND FSM.
933	// It goes next to the ICACHE_MISS_WAIT state waiting a response from RSP FSM,
934	// The availability of the missing cache line is signaled by the response fifo,
935	// and the cache update is done (one word per cycle) in the ICACHE_MISS_DATA_UPDT
936	// and ICACHE_MISS_DIR_UPDT states.
937	// - In case of uncacheable instruction, the ICACHE FSM goes to ICACHE_UNC_WAIT
938	// to wait the response from the RSP FSM, through the response fifo.
939	// The missing instruction is directly returned to processor in this state.
940	//
941	// 3/ TLB miss
942	// In case of tlb miss, the ICACHE FSM request to the DCACHE FSM to update the
943	// ITLB using the r_icache_tlb_miss_req flip-flop and the r_icache_tlb_miss_vaddr
944	// register, and goes to the ICACHE_TLB_WAIT state.
945	// The tlb update is entirely done by the DCACHE FSM (who becomes the owner
946	// of ITLB until the update is completed, and reset r_icache_tlb_miss_req
947	// to signal the completion.
948	//
949	// 4/ XTN requests
950	// The DCACHE FSM signals XTN processor requests to ICACHE_FSM
951	// using the r_dcache_xtn_req flip-flop.
952	// The request opcode and the address to be invalidated are transmitted
953	// in the r_dcache_xtn_opcode and r_dcache_save_wdata registers respectively.
954	// The r_dcache_xtn_req flip-flop is reset by the ICACHE_FSM when the operation
955	// is completed.
956	//
957	// 5/ Error Handling
958	// The r_vci_rsp_ins_error flip-flop is set by the RSP FSM in case of bus error
959	// in a cache miss or uncacheable read VCI transaction. Nothing is written
960	// in the response fifo. This flip-flop is reset by the ICACHE-FSM.
961	////////////////////////////////////////////////////////////////////////////////////////
962
963	// default value for m_irsp
964	m_irsp.valid = false;
965	m_irsp.error = false;
966	m_irsp.instruction = 0;
967
968	switch( r_icache_fsm.read() )
969	{
970	/////////////////
971	case ICACHE_IDLE: // In this state, we handle processor requests, XTN requests,
972	// and coherence requests with a fixed priority:
973	// 1/ Coherence requests => ICACHE_CC_CHECK
974	// 2/ XTN processor requests (from DCACHE FSM) => ICACHE_XTN_*
975	// 3/ tlb miss => ICACHE_TLB_WAIT
976	// 4/ cacheable read miss => ICACHE_MISS_SELECT
977	// 5/ uncacheable read miss => ICACHE_UNC_REQ
978	{
979	// coherence interrupt
980	if ( r_cc_receive_icache_req.read() )
981	{
982	r_icache_fsm = ICACHE_CC_CHECK;
983	r_icache_fsm_save = r_icache_fsm.read();
984	break;
985	}
986
987	// XTN requests sent by DCACHE FSM
988	// These request are not executed in this IDLE state, because
989	// they require access to icache or itlb, that are already accessed
990	if ( r_dcache_xtn_req.read() )
991	{
992	if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_PTPR )
993	{
994	r_icache_fsm = ICACHE_XTN_TLB_FLUSH;
995	}
996	else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ICACHE_FLUSH)
997	{
998	r_icache_flush_count = 0;
999	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH;
1000	}
1001	else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ITLB_INVAL)
1002	{
1003	r_icache_fsm = ICACHE_XTN_TLB_INVAL;
1004	}
1005	else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ICACHE_INVAL)
1006	{
1007	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_VA;
1008	}
1009	else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_MMU_ICACHE_PA_INV)
1010	{
1011	if (sizeof(paddr_t) <= 32)
1012	{
1013	assert(r_mmu_word_hi.read() == 0 &&
1014	"illegal XTN request in ICACHE: high bits should be 0 for 32bit paddr");
1015	r_icache_vci_paddr = (paddr_t)r_mmu_word_lo.read();
1016	}
1017	else
1018	{
1019	r_icache_vci_paddr = (paddr_t)r_mmu_word_hi.read() << 32 \|
1020	(paddr_t)r_mmu_word_lo.read();
1021	}
1022	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA;
1023	}
1024	else
1025	{
1026	assert( false and
1027	"undefined XTN request received by ICACHE FSM");
1028	}
1029	break;
1030	} // end if xtn_req
1031
1032	// processor request
1033	if ( m_ireq.valid )
1034	{
1035	bool cacheable;
1036	paddr_t paddr;
1037	bool tlb_hit = false;
1038	pte_info_t tlb_flags;
1039	size_t tlb_way;
1040	size_t tlb_set;
1041	paddr_t tlb_nline;
1042	uint32_t cache_inst = 0;
1043	size_t cache_way;
1044	size_t cache_set;
1045	size_t cache_word;
1046	int cache_state = CACHE_SLOT_STATE_EMPTY;
1047
1048	// We register processor request
1049	r_icache_vaddr_save = m_ireq.addr;
1050
1051	// sytematic itlb access (if activated)
1052	if ( r_mmu_mode.read() & INS_TLB_MASK )
1053	{
1054
1055	#ifdef INSTRUMENTATION
1056	m_cpt_itlb_read++;
1057	#endif
1058	tlb_hit = r_itlb.translate( m_ireq.addr,
1059	&paddr,
1060	&tlb_flags,
1061	&tlb_nline, // unused
1062	&tlb_way, // unused
1063	&tlb_set ); // unused
1064	}
1065	else
1066	{
1067	paddr = (paddr_t)m_ireq.addr;
1068	}
1069
1070	// systematic icache access (if activated)
1071	if ( r_mmu_mode.read() & INS_CACHE_MASK )
1072	{
1073
1074
1075	#ifdef INSTRUMENTATION
1076	m_cpt_icache_data_read++;
1077	m_cpt_icache_dir_read++;
1078	#endif
1079	r_icache.read( paddr,
1080	&cache_inst,
1081	&cache_way,
1082	&cache_set,
1083	&cache_word,
1084	&cache_state );
1085	}
1086
1087	// We compute cacheability and check access rights:
1088	// - If MMU activated : cacheability is defined by the C bit in the PTE,
1089	// and the access rights are defined by the U and X bits in the PTE.
1090	// - If MMU not activated : cacheability is defined by the segment table,
1091	// and there is no access rights checking
1092
1093	if ( not (r_mmu_mode.read() & INS_TLB_MASK) ) // tlb not activated:
1094	{
1095	// cacheability
1096	if ( not (r_mmu_mode.read() & INS_CACHE_MASK) ) cacheable = false;
1097	else cacheable = m_cacheability_table[m_ireq.addr];
1098	}
1099	else // itlb activated
1100	{
1101	if ( tlb_hit ) // ITLB hit
1102	{
1103	// cacheability
1104	if ( not (r_mmu_mode.read() & INS_CACHE_MASK) ) cacheable = false;
1105	else cacheable = tlb_flags.c;
1106
1107	// access rights checking
1108	if ( not tlb_flags.u && (m_ireq.mode == iss_t::MODE_USER) )
1109	{
1110	r_mmu_ietr = MMU_READ_PRIVILEGE_VIOLATION;
1111	r_mmu_ibvar = m_ireq.addr;
1112	m_irsp.valid = true;
1113	m_irsp.error = true;
1114	m_irsp.instruction = 0;
1115	break;
1116	}
1117	else if ( not tlb_flags.x )
1118	{
1119	r_mmu_ietr = MMU_READ_EXEC_VIOLATION;
1120	r_mmu_ibvar = m_ireq.addr;
1121	m_irsp.valid = true;
1122	m_irsp.error = true;
1123	m_irsp.instruction = 0;
1124	break;
1125	}
1126	}
1127	else // ITLB miss
1128	{
1129
1130	#ifdef INSTRUMENTATION
1131	m_cpt_itlb_miss++;
1132	#endif
1133	r_icache_fsm = ICACHE_TLB_WAIT;
1134	r_icache_tlb_miss_req = true;
1135	break;
1136	}
1137	} // end if itlb activated
1138
1139	// physical address registration
1140	r_icache_vci_paddr = paddr;
1141
1142	// Finally, we send the response to processor, and compute next state
1143	if ( cacheable )
1144	{
1145	if (cache_state == CACHE_SLOT_STATE_EMPTY) // cache miss
1146	{
1147
1148	#ifdef INSTRUMENTATION
1149	m_cpt_icache_miss++;
1150	#endif
1151	// we request a VCI transaction
1152	r_icache_fsm = ICACHE_MISS_SELECT;
1153	r_icache_miss_req = true;
1154	}
1155	else if (cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup
1156	{
1157	// stalled until cleanup is acknowledged
1158	r_icache_fsm = ICACHE_IDLE;
1159	}
1160	else // cache hit
1161	{
1162
1163	#ifdef INSTRUMENTATION
1164	m_cpt_ins_read++;
1165	#endif
1166	// return instruction to processor
1167	m_irsp.valid = true;
1168	m_irsp.instruction = cache_inst;
1169	r_icache_fsm = ICACHE_IDLE;
1170	}
1171	}
1172	else // non cacheable read
1173	{
1174	r_icache_unc_req = true;
1175	r_icache_fsm = ICACHE_UNC_WAIT;
1176	}
1177	} // end if m_ireq.valid
1178	break;
1179	}
1180	/////////////////////
1181	case ICACHE_TLB_WAIT: // Waiting the itlb update by the DCACHE FSM after a tlb miss
1182	// the itlb is udated by the DCACHE FSM, as well as the
1183	// r_mmu_ietr and r_mmu_ibvar registers in case of error.
1184	// the itlb is not accessed by ICACHE FSM until DCACHE FSM
1185	// reset the r_icache_tlb_miss_req flip-flop
1186	// external coherence request are accepted in this state.
1187	{
1188	// coherence interrupt
1189	if ( r_cc_receive_icache_req.read() )
1190	{
1191	r_icache_fsm = ICACHE_CC_CHECK;
1192	r_icache_fsm_save = r_icache_fsm.read();
1193	break;
1194	}
1195
1196	if ( m_ireq.valid ) m_cost_ins_tlb_miss_frz++;
1197
1198	// DCACHE FSM signals response by reseting the request flip-flop
1199	if ( not r_icache_tlb_miss_req.read() )
1200	{
1201	if ( r_icache_tlb_rsp_error.read() ) // error reported : tlb not updated
1202	{
1203	r_icache_tlb_rsp_error = false;
1204	m_irsp.error = true;
1205	m_irsp.valid = true;
1206	r_icache_fsm = ICACHE_IDLE;
1207	}
1208	else // tlb updated : return to IDLE state
1209	{
1210	r_icache_fsm = ICACHE_IDLE;
1211	}
1212	}
1213	break;
1214	}
1215	//////////////////////////
1216	case ICACHE_XTN_TLB_FLUSH: // invalidate in one cycle all non global TLB entries
1217	{
1218	r_itlb.flush();
1219	r_dcache_xtn_req = false;
1220	r_icache_fsm = ICACHE_IDLE;
1221	break;
1222	}
1223	////////////////////////////
1224	case ICACHE_XTN_CACHE_FLUSH: // Invalidate sequencially all cache lines, using
1225	// r_icache_flush_count as a slot counter,
1226	// looping in this state until all slots are visited.
1227	// It can require two cycles per slot:
1228	// We test here the slot state, and make the actual inval
1229	// (if line is valid) in ICACHE_XTN_CACHE_FLUSH_GO state.
1230	// A cleanup request is generated for each valid line
1231	{
1232	if ( not r_icache_cc_send_req.read() ) // blocked until previous cc_send request is sent
1233	{
1234	int state;
1235	uint32_t tag;
1236	size_t way = r_icache_flush_count.read()/m_icache_sets;
1237	size_t set = r_icache_flush_count.read()%m_icache_sets;
1238
1239	#ifdef INSTRUMENTATION
1240	m_cpt_icache_dir_read++;
1241	#endif
1242	r_icache.read_dir( way,
1243	set,
1244	&tag,
1245	&state );
1246
1247	if ( state == CACHE_SLOT_STATE_VALID ) // inval required
1248	{
1249	// request cleanup
1250	r_icache_cc_send_req = true;
1251	r_icache_cc_send_nline = tag * m_icache_sets;
1252	r_icache_cc_send_way = way;
1253	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1254
1255	// goes to ICACHE_XTN_CACHE_FLUSH_GO to make inval
1256	r_icache_miss_way = way;
1257	r_icache_miss_set = set;
1258	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH_GO;
1259	}
1260	else if ( r_icache_flush_count.read() ==
1261	(m_icache_sets*m_icache_ways - 1) ) // last slot
1262	{
1263	r_dcache_xtn_req = false;
1264	m_drsp.valid = true;
1265	r_icache_fsm = ICACHE_IDLE;
1266	}
1267
1268	// saturation counter, to have the same last slot condition
1269	// in ICACHE_XTN_CACHE_FLUSH and ICACHE_XTN_CACHE_FLUSH_GO states
1270	if ( r_icache_flush_count.read() < (m_icache_sets*m_icache_ways - 1) )
1271	{
1272	r_icache_flush_count = r_icache_flush_count.read() + 1;
1273	}
1274	}
1275	break;
1276	}
1277	///////////////////////////////
1278	case ICACHE_XTN_CACHE_FLUSH_GO: // Switch slot state to ZOMBI for an XTN flush
1279	{
1280	size_t way = r_icache_miss_way.read();
1281	size_t set = r_icache_miss_set.read();
1282
1283	#ifdef INSTRUMENTATION
1284	m_cpt_icache_dir_write++;
1285	#endif
1286
1287	r_icache.write_dir( way,
1288	set,
1289	CACHE_SLOT_STATE_ZOMBI );
1290
1291	if ( r_icache_flush_count.read() ==
1292	(m_icache_sets*m_icache_ways - 1) ) // last slot
1293	{
1294	r_dcache_xtn_req = false;
1295	m_drsp.valid = true;
1296	r_icache_fsm = ICACHE_IDLE;
1297	}
1298	else
1299	{
1300	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH;
1301	}
1302	break;
1303	}
1304
1305	//////////////////////////
1306	case ICACHE_XTN_TLB_INVAL: // invalidate one TLB entry selected by the virtual address
1307	// stored in the r_dcache_save_wdata register
1308	{
1309	r_itlb.inval(r_dcache_save_wdata.read());
1310	r_dcache_xtn_req = false;
1311	r_icache_fsm = ICACHE_IDLE;
1312	break;
1313	}
1314	///////////////////////////////
1315	case ICACHE_XTN_CACHE_INVAL_VA: // Selective cache line invalidate with virtual address
1316	// requires 3 cycles (in case of hit on itlb and icache).
1317	// In this state, access TLB to translate virtual address
1318	// stored in the r_dcache_save_wdata register.
1319	{
1320	paddr_t paddr;
1321	bool hit;
1322
1323	// read physical address in TLB when MMU activated
1324	if ( r_mmu_mode.read() & INS_TLB_MASK ) // itlb activated
1325	{
1326
1327	#ifdef INSTRUMENTATION
1328	m_cpt_itlb_read++;
1329	#endif
1330	hit = r_itlb.translate(r_dcache_save_wdata.read(),
1331	&paddr);
1332	}
1333	else // itlb not activated
1334	{
1335	paddr = (paddr_t)r_dcache_save_wdata.read();
1336	hit = true;
1337	}
1338
1339	if ( hit ) // continue the selective inval process
1340	{
1341	r_icache_vci_paddr = paddr;
1342	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA;
1343	}
1344	else // miss : send a request to DCACHE FSM
1345	{
1346
1347	#ifdef INSTRUMENTATION
1348	m_cpt_itlb_miss++;
1349	#endif
1350	r_icache_tlb_miss_req = true;
1351	r_icache_vaddr_save = r_dcache_save_wdata.read();
1352	r_icache_fsm = ICACHE_TLB_WAIT;
1353	}
1354	break;
1355	}
1356	///////////////////////////////
1357	case ICACHE_XTN_CACHE_INVAL_PA: // selective invalidate cache line with physical address
1358	// require 2 cycles. In this state, we read directory
1359	// with address stored in r_icache_vci_paddr register.
1360	{
1361	int state;
1362	size_t way;
1363	size_t set;
1364	size_t word;
1365
1366	#ifdef INSTRUMENTATION
1367	m_cpt_icache_dir_read++;
1368	#endif
1369	r_icache.read_dir(r_icache_vci_paddr.read(),
1370	&state,
1371	&way,
1372	&set,
1373	&word);
1374
1375	if ( state == CACHE_SLOT_STATE_VALID ) // inval to be done
1376	{
1377	r_icache_miss_way = way;
1378	r_icache_miss_set = set;
1379	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_GO;
1380	}
1381	else // miss : acknowlege the XTN request and return
1382	{
1383	r_dcache_xtn_req = false;
1384	r_icache_fsm = ICACHE_IDLE;
1385	}
1386	break;
1387	}
1388	///////////////////////////////
1389	case ICACHE_XTN_CACHE_INVAL_GO: // Switch slot to ZOMBI state for an XTN inval
1390	{
1391	if ( not r_icache_cc_send_req.read() ) // blocked until previous cc_send request not sent
1392	{
1393
1394	#ifdef INSTRUMENTATION
1395	m_cpt_icache_dir_write++;
1396	#endif
1397	r_icache.write_dir( r_icache_miss_way.read(),
1398	r_icache_miss_set.read(),
1399	CACHE_SLOT_STATE_ZOMBI );
1400
1401	// request cleanup
1402	r_icache_cc_send_req = true;
1403	r_icache_cc_send_nline = r_icache_vci_paddr.read() / (m_icache_words<<2);
1404	r_icache_cc_send_way = r_icache_miss_way.read();
1405	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1406
1407	// acknowledge the XTN request and return
1408	r_dcache_xtn_req = false;
1409	r_icache_fsm = ICACHE_IDLE;
1410	}
1411	break;
1412	}
1413	////////////////////////
1414	case ICACHE_MISS_SELECT: // Try to select a slot in associative set,
1415	// if previous cleanup has been sent.
1416	// Waiting in this state if no slot available.
1417	// Set the r_icache_cleanup_req flip-flop
1418	// and the r_icache_miss_clack flip-flop,
1419	// when a cleanup is required
1420	{
1421	if (m_ireq.valid) m_cost_ins_miss_frz++;
1422
1423	// coherence interrupt
1424	if ( r_cc_receive_icache_req.read() )
1425	{
1426	r_icache_fsm = ICACHE_CC_CHECK;
1427	r_icache_fsm_save = r_icache_fsm.read();
1428	break;
1429	}
1430
1431	if ( not r_icache_cc_send_req.read() ) // wait for previous cc_send request to be sent
1432	{
1433	bool found;
1434	bool cleanup;
1435	size_t way;
1436	size_t set;
1437	paddr_t victim;
1438
1439	#ifdef INSTRUMENTATION
1440	m_cpt_icache_dir_read++;
1441	#endif
1442	r_icache.read_select(r_icache_vci_paddr.read(),
1443	&victim,
1444	&way,
1445	&set,
1446	&found,
1447	&cleanup );
1448	if ( found )
1449	{
1450	r_icache_miss_way = way;
1451	r_icache_miss_set = set;
1452
1453	if ( cleanup )
1454	{
1455	r_icache_fsm = ICACHE_MISS_CLEAN;
1456	r_icache_miss_clack = true;
1457	// request cleanup
1458	r_icache_cc_send_req = true;
1459	r_icache_cc_send_nline = victim;
1460	r_icache_cc_send_way = way;
1461	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1462	}
1463	else
1464	{
1465	r_icache_fsm = ICACHE_MISS_WAIT;
1466	}
1467
1468	#if DEBUG_ICACHE
1469	if ( m_debug_dcache_fsm )
1470	{
1471	std::cout << " <PROC " << name()
1472	<< " ICACHE_MISS_SELECT> Select a slot:" << std::dec
1473	<< " / WAY = " << way
1474	<< " / SET = " << set;
1475	if (cleanup) std::cout << " / VICTIM = " << std::hex << victim << std::endl;
1476	else std::cout << std::endl;
1477	}
1478	#endif
1479	}
1480	}
1481	break;
1482	}
1483	///////////////////////
1484	case ICACHE_MISS_CLEAN: // switch the slot to zombi state
1485	{
1486	if (m_ireq.valid) m_cost_ins_miss_frz++;
1487
1488	#ifdef INSTRUMENTATION
1489	m_cpt_icache_dir_write++;
1490	#endif
1491	r_icache.write_dir( r_icache_miss_way.read(),
1492	r_icache_miss_set.read(),
1493	CACHE_SLOT_STATE_ZOMBI);
1494	#if DEBUG_ICACHE
1495	if ( m_debug_dcache_fsm )
1496	{
1497	std::cout << " <PROC " << name()
1498	<< " ICACHE_MISS_CLEAN> Switch to ZOMBI state" << std::dec
1499	<< " / WAY = " << r_icache_miss_way.read()
1500	<< " / SET = " << r_icache_miss_set.read() << std::endl;
1501	}
1502	#endif
1503
1504	r_icache_fsm = ICACHE_MISS_WAIT;
1505	break;
1506	}
1507	//////////////////////
1508	case ICACHE_MISS_WAIT: // waiting response from VCI_RSP FSM
1509	{
1510	if (m_ireq.valid) m_cost_ins_miss_frz++;
1511
1512	// coherence interrupt
1513	if ( r_cc_receive_icache_req.read() )
1514	{
1515	r_icache_fsm = ICACHE_CC_CHECK;
1516	r_icache_fsm_save = r_icache_fsm.read();
1517	break;
1518	}
1519
1520	if ( r_vci_rsp_ins_error.read() ) // bus error
1521	{
1522	r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS;
1523	r_mmu_ibvar = r_icache_vaddr_save.read();
1524	m_irsp.valid = true;
1525	m_irsp.error = true;
1526	r_vci_rsp_ins_error = false;
1527	r_icache_fsm = ICACHE_IDLE;
1528	}
1529	else if ( r_vci_rsp_fifo_icache.rok() ) // response available
1530	{
1531	r_icache_miss_word = 0;
1532	r_icache_fsm = ICACHE_MISS_DATA_UPDT;
1533	}
1534	break;
1535	}
1536	///////////////////////////
1537	case ICACHE_MISS_DATA_UPDT: // update the cache (one word per cycle)
1538	{
1539	if ( m_ireq.valid ) m_cost_ins_miss_frz++;
1540
1541	if ( r_vci_rsp_fifo_icache.rok() ) // response available
1542	{
1543
1544	#ifdef INSTRUMENTATION
1545	m_cpt_icache_data_write++;
1546	#endif
1547	r_icache.write( r_icache_miss_way.read(),
1548	r_icache_miss_set.read(),
1549	r_icache_miss_word.read(),
1550	r_vci_rsp_fifo_icache.read() );
1551	#if DEBUG_ICACHE
1552	if ( m_debug_icache_fsm )
1553	{
1554	std::cout << " <PROC " << name()
1555	<< " ICACHE_MISS_DATA_UPDT> Write one word:"
1556	<< " WDATA = " << r_vci_rsp_fifo_icache.read()
1557	<< " WAY = " << r_icache_miss_way.read()
1558	<< " SET = " << r_icache_miss_set.read()
1559	<< " WORD = " << r_icache_miss_word.read() << std::endl;
1560	}
1561	#endif
1562	vci_rsp_fifo_icache_get = true;
1563	r_icache_miss_word = r_icache_miss_word.read() + 1;
1564
1565	if ( r_icache_miss_word.read() == m_icache_words-1 ) // last word
1566	{
1567	r_icache_fsm = ICACHE_MISS_DIR_UPDT;
1568	}
1569	}
1570	break;
1571	}
1572	//////////////////////////
1573	case ICACHE_MISS_DIR_UPDT: // Stalled if a victim line has been evicted,
1574	// and the cleanup ack has not been received,
1575	// as indicated by r_icache_miss_clack.
1576	// - If no matching coherence request (r_icache_miss_inval)
1577	// switch directory slot to VALID state.
1578	// - If matching coherence request, switch directory slot
1579	// to ZOMBI state, and send a cleanup request.
1580	{
1581	if ( m_ireq.valid ) m_cost_ins_miss_frz++;
1582
1583	// coherence interrupt
1584	if ( r_cc_receive_icache_req.read() )
1585	{
1586	r_icache_fsm = ICACHE_CC_CHECK;
1587	r_icache_fsm_save = r_icache_fsm.read();
1588	break;
1589	}
1590
1591	if ( not r_icache_miss_clack.read() ) // waiting cleanup acknowledge for victim line
1592	{
1593	if ( r_icache_miss_inval ) // Switch slot to ZOMBI state, and new cleanup
1594	{
1595	if ( not r_icache_cc_send_req.read() )
1596	{
1597	r_icache_miss_inval = false;
1598	// request cleanup
1599	r_icache_cc_send_req = true;
1600	r_icache_cc_send_nline = r_icache_vci_paddr.read() / (m_icache_words<<2);
1601	r_icache_cc_send_way = r_icache_miss_way.read();
1602	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1603
1604	#ifdef INSTRUMENTATION
1605	m_cpt_icache_dir_write++;
1606	#endif
1607	r_icache.write_dir( r_icache_vci_paddr.read(),
1608	r_icache_miss_way.read(),
1609	r_icache_miss_set.read(),
1610	CACHE_SLOT_STATE_ZOMBI );
1611	#if DEBUG_ICACHE
1612	if ( m_debug_icache_fsm )
1613	{
1614	std::cout << " <PROC " << name()
1615	<< " ICACHE_MISS_DIR_UPDT> Switch cache slot to ZOMBI state"
1616	<< " PADDR = " << std::hex << r_icache_vci_paddr.read()
1617	<< " WAY = " << std::dec << r_icache_miss_way.read()
1618	<< " SET = " << r_icache_miss_set.read() << std::endl;
1619	}
1620	#endif
1621	}
1622	else
1623	break;
1624	}
1625	else // Switch slot to VALID state
1626	{
1627
1628	#ifdef INSTRUMENTATION
1629	m_cpt_icache_dir_write++;
1630	#endif
1631	r_icache.write_dir( r_icache_vci_paddr.read(),
1632	r_icache_miss_way.read(),
1633	r_icache_miss_set.read(),
1634	CACHE_SLOT_STATE_VALID );
1635	#if DEBUG_ICACHE
1636	if ( m_debug_icache_fsm )
1637	{
1638	std::cout << " <PROC " << name()
1639	<< " ICACHE_MISS_DIR_UPDT> Switch cache slot to VALID state"
1640	<< " PADDR = " << std::hex << r_icache_vci_paddr.read()
1641	<< " WAY = " << std::dec << r_icache_miss_way.read()
1642	<< " SET = " << r_icache_miss_set.read() << std::endl;
1643	}
1644	#endif
1645	}
1646
1647	r_icache_fsm = ICACHE_IDLE;
1648	}
1649	break;
1650	}
1651	////////////////////
1652	case ICACHE_UNC_WAIT: // waiting a response to an uncacheable read from VCI_RSP FSM
1653	{
1654	// coherence interrupt
1655	if ( r_cc_receive_icache_req.read() )
1656	{
1657	r_icache_fsm = ICACHE_CC_CHECK;
1658	r_icache_fsm_save = r_icache_fsm.read();
1659	break;
1660	}
1661
1662	if ( r_vci_rsp_ins_error.read() ) // bus error
1663	{
1664	r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS;
1665	r_mmu_ibvar = m_ireq.addr;
1666	r_vci_rsp_ins_error = false;
1667	m_irsp.valid = true;
1668	m_irsp.error = true;
1669	r_icache_fsm = ICACHE_IDLE;
1670	}
1671	else if (r_vci_rsp_fifo_icache.rok() ) // instruction available
1672	{
1673	vci_rsp_fifo_icache_get = true;
1674	r_icache_fsm = ICACHE_IDLE;
1675	if ( m_ireq.valid and
1676	(m_ireq.addr == r_icache_vaddr_save.read()) ) // request unmodified
1677	{
1678	m_irsp.valid = true;
1679	m_irsp.instruction = r_vci_rsp_fifo_icache.read();
1680	}
1681	}
1682	break;
1683	}
1684	/////////////////////
1685	case ICACHE_CC_CHECK: // This state is the entry point of a sub-fsm
1686	// handling coherence requests.
1687	// if there is a matching pending miss, it is
1688	// signaled in the r_icache_miss_inval flip-flop.
1689	// The return state is defined in r_icache_fsm_save.
1690	{
1691	paddr_t paddr = r_cc_receive_icache_nline.read() * m_icache_words * 4;
1692	paddr_t mask = ~((m_icache_words<<2)-1);
1693
1694	if (r_cc_receive_icache_type.read() == CC_TYPE_CLACK)
1695	// We switch the directory slot to EMPTY state
1696	// and reset r_icache_miss_clack if the cleanup ack
1697	// is matching a pending miss
1698	{
1699
1700	if ( m_ireq.valid ) m_cost_ins_miss_frz++;
1701
1702	#ifdef INSTRUMENTATION
1703	m_cpt_icache_dir_write++;
1704	#endif
1705	r_icache.write_dir( 0,
1706	r_cc_receive_icache_way.read(),
1707	r_cc_receive_icache_set.read(),
1708	CACHE_SLOT_STATE_EMPTY);
1709
1710	if ( (r_icache_miss_set.read() == r_cc_receive_icache_set.read()) and
1711	(r_icache_miss_way.read() == r_cc_receive_icache_way.read()) )
1712	r_icache_miss_clack = false;
1713
1714	r_icache_fsm = r_icache_fsm_save.read() ;
1715	r_cc_receive_icache_req = false;
1716
1717	#if DEBUG_ICACHE
1718	if ( m_debug_icache_fsm )
1719	{
1720	std::cout << " <PROC " << name()
1721	<< " ICACHE_CC_CHECK> CC_TYPE_CLACK slot returns to empty state"
1722	<< " set = " << r_cc_receive_icache_set.read()
1723	<< " / way = " << r_cc_receive_icache_way.read() << std::endl;
1724	}
1725	#endif
1726	}
1727	else if( ((r_icache_fsm_save.read() == ICACHE_MISS_SELECT) or
1728	(r_icache_fsm_save.read() == ICACHE_MISS_WAIT) or
1729	(r_icache_fsm_save.read() == ICACHE_MISS_DIR_UPDT)) and
1730	((r_icache_vci_paddr.read() & mask) == (paddr & mask)) ) // matching
1731	{
1732	// signaling the matching
1733	r_icache_miss_inval = true;
1734
1735	// in case of update, go to CC_UPDT
1736	// JUST TO POP THE FIFO
1737	if (r_cc_receive_icache_type.read() == CC_TYPE_UPDT)
1738	{
1739	r_icache_fsm = ICACHE_CC_UPDT;
1740	r_icache_cc_word = r_cc_receive_word_idx.read();
1741	// just pop the fifo , don't write in icache
1742	r_icache_cc_need_write = false;
1743	}
1744	// the request is dealt with
1745	else
1746	{
1747	r_cc_receive_icache_req = false;
1748	r_icache_fsm = r_icache_fsm_save.read();
1749	}
1750	#if DEBUG_ICACHE
1751	if ( m_debug_icache_fsm )
1752	{
1753	std::cout << " <PROC " << name()
1754	<< " ICACHE_CC_CHECK> Coherence request matching a pending miss:"
1755	<< " PADDR = " << std::hex << paddr << std::endl;
1756	}
1757	#endif
1758	}
1759	else // no match
1760	{
1761	int state;
1762	size_t way;
1763	size_t set;
1764	size_t word;
1765
1766	#ifdef INSTRUMENTATION
1767	m_cpt_icache_dir_read++;
1768	#endif
1769	r_icache.read_dir(paddr,
1770	&state,
1771	&way,
1772	&set,
1773	&word);
1774
1775	r_icache_cc_way = way;
1776	r_icache_cc_set = set;
1777
1778	if ( state == CACHE_SLOT_STATE_VALID) // hit
1779	{
1780	// need to update the cache state
1781	r_icache_cc_need_write = true;
1782	if (r_cc_receive_icache_type.read() == CC_TYPE_UPDT) // hit update
1783	{
1784	r_icache_fsm = ICACHE_CC_UPDT;
1785	r_icache_cc_word = r_cc_receive_word_idx.read();
1786	}
1787	else if (r_cc_receive_icache_type.read() == CC_TYPE_INVAL) // hit inval
1788	{
1789	r_icache_fsm = ICACHE_CC_INVAL;
1790	}
1791	else if (r_cc_receive_icache_type.read() == CC_TYPE_BRDCAST) // hit broadcast
1792	{
1793	r_icache_fsm = ICACHE_CC_BROADCAST;
1794	}
1795	}
1796	else // miss
1797	{
1798	// multicast acknowledgement required in case of update
1799	if(r_cc_receive_icache_type.read() == CC_TYPE_UPDT)
1800	{
1801	r_icache_fsm = ICACHE_CC_UPDT;
1802	r_icache_cc_word = r_cc_receive_word_idx.read();
1803	// just pop the fifo , don't write in icache
1804	r_icache_cc_need_write = false;
1805	}
1806	else // No response needed
1807	{
1808	r_cc_receive_icache_req = false;
1809	r_icache_fsm = r_icache_fsm_save.read();
1810	}
1811	}
1812	}
1813	break;
1814	}
1815	/////////////////////
1816	case ICACHE_CC_INVAL: // hit inval : switch slot to EMPTY state
1817	{
1818
1819	#if DEBUG_ICACHE
1820	if ( m_debug_icache_fsm )
1821	{
1822	std::cout << " <PROC " << name()
1823	<< " ICACHE_CC_INVAL> slot returns to empty state"
1824	<< " set = " << r_icache_cc_set.read()
1825	<< " / way = " << r_icache_cc_way.read() << std::endl;
1826	}
1827	#endif
1828
1829	#ifdef INSTRUMENTATION
1830	m_cpt_icache_dir_read++;
1831	#endif
1832	if (r_icache_cc_need_write.read())
1833	{
1834	r_icache.write_dir( 0,
1835	r_icache_cc_way.read(),
1836	r_icache_cc_set.read(),
1837	CACHE_SLOT_STATE_EMPTY );
1838	// no need to write in the cache anymore
1839	r_icache_cc_need_write = false;
1840	}
1841
1842	// multicast acknowledgement
1843	// send a request to cc_send_fsm
1844	if(not r_icache_cc_send_req.read()) // cc_send is available
1845	{
1846	// coherence request completed
1847	r_cc_receive_icache_req = false;
1848	// request multicast acknowledgement
1849	r_icache_cc_send_req = true;
1850	r_icache_cc_send_updt_tab_idx = r_cc_receive_icache_updt_tab_idx.read();
1851	r_icache_cc_send_type = CC_TYPE_MULTI_ACK;
1852
1853	r_icache_fsm = r_icache_fsm_save.read();
1854	}
1855	//else wait for previous cc_send request to be sent
1856	break;
1857	}
1858	////////////////////
1859	case ICACHE_CC_UPDT: // hit update : write one word per cycle
1860	{
1861
1862	#if DEBUG_ICACHE
1863	if ( m_debug_icache_fsm )
1864	{
1865	std::cout << " <PROC " << name()
1866	<< " ICACHE_CC_UPDT> Write one word "
1867	<< " set = " << r_icache_cc_set.read()
1868	<< " / way = " << r_icache_cc_way.read()
1869	<< " / word = " << r_icache_cc_word.read() << std::endl;
1870	}
1871	#endif
1872
1873	#ifdef INSTRUMENTATION
1874	m_cpt_icache_data_write++;
1875	#endif
1876	size_t word = r_icache_cc_word.read();
1877	size_t way = r_icache_cc_way.read();
1878	size_t set = r_icache_cc_set.read();
1879
1880	if (r_cc_receive_updt_fifo_be.rok())
1881	{
1882	if (r_icache_cc_need_write.read())
1883	{
1884	r_icache.write( way,
1885	set,
1886	word,
1887	r_cc_receive_updt_fifo_data.read(),
1888	r_cc_receive_updt_fifo_be.read() );
1889
1890	r_icache_cc_word = word+1;
1891	}
1892	if ( r_cc_receive_updt_fifo_eop.read() ) // last word
1893	{
1894	// no need to write in the cache anymore
1895	r_icache_cc_need_write = false;
1896	// wait to send a request to cc_send_fsm
1897	if(not r_icache_cc_send_req.read()) // cc_send is available
1898	{
1899	//consume last flit
1900	cc_receive_updt_fifo_get = true;
1901	// coherence request completed
1902	r_cc_receive_icache_req = false;
1903	// request multicast acknowledgement
1904	r_icache_cc_send_req = true;
1905	r_icache_cc_send_updt_tab_idx = r_cc_receive_icache_updt_tab_idx.read();
1906	r_icache_cc_send_type = CC_TYPE_MULTI_ACK;
1907
1908	r_icache_fsm = r_icache_fsm_save.read();
1909	}
1910	}
1911	else
1912	{
1913	//consume fifo if not eop
1914	cc_receive_updt_fifo_get = true;
1915	}
1916	}
1917	break;
1918	}
1919	/////////////////////////
1920	case ICACHE_CC_BROADCAST: // hit broadcast : switch slot to ZOMBI state
1921	// and request a cleanup
1922	{
1923
1924	#if DEBUG_ICACHE
1925	if ( m_debug_icache_fsm )
1926	{
1927	std::cout << " <PROC " << name()
1928	<< " ICACHE_CC_BROADCAST > Slot goes to zombi state "
1929	<< " set = " << r_icache_cc_set.read()
1930	<< " / way = " << r_icache_cc_way.read() << std::endl;
1931	}
1932	#endif
1933
1934	#ifdef INSTRUMENTATION
1935	m_cpt_icache_dir_write++;
1936	#endif
1937	if (r_icache_cc_need_write.read())
1938	{
1939	r_icache.write_dir( r_icache_cc_way.read(),
1940	r_icache_cc_set.read(),
1941	CACHE_SLOT_STATE_ZOMBI );
1942	// no need to write in the cache anymore
1943	r_icache_cc_need_write = false;
1944	}
1945
1946	// cleanup
1947	// send a request to cc_send_fsm
1948	if(not r_icache_cc_send_req.read()) // cc_send is available
1949	{
1950	// coherence request completed
1951	r_cc_receive_icache_req = false;
1952	// request cleanup
1953	r_icache_cc_send_req = true;
1954	r_icache_cc_send_nline = r_cc_receive_icache_nline.read();
1955	r_icache_cc_send_way = r_icache_cc_way.read();
1956	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1957
1958	r_icache_fsm = r_icache_fsm_save.read();
1959	}
1960	//else wait for previous cc_send request to be sent
1961	break;
1962	}
1963	} // end switch r_icache_fsm
1964
1965	////////////////////////////////////////////////////////////////////////////////////
1966	// DCACHE FSM
1967	//
1968	// 1/ Coherence operations
1969	// They are handled as interrupts generated by the CC_RECEIVE FSM.
1970	// - There is a coherence request when r_tgt_dcache_req is set.
1971	// They are taken in IDLE, MISS_WAIT, MISS_DIR_UPDT, UNC_WAIT, LL_WAIT
1972	// and SC_WAIT states.
1973	// - There is a cleanup acknowledge request when r_cleanup_dcache_req is set.
1974	// They are taken in IDLE, MISS_SELECT, MISS_CLEAN, MISS_WAIT, MISS_DATA_UPDT,
1975	// MISS_DIR_UPDT, UNC_WAIT, LL_WAIT, SC_WAIT states.
1976	// - For both types of requests, actions associated to the pre-empted state
1977	// are not executed. The DCACHE FSM goes to the proper sub-FSM (CC_CHECK
1978	// or CC_CLACK) to execute the requested coherence operation, and returns
1979	// to the pre-empted state.
1980	//
1981	// 2/ TLB miss
1982	// The page tables are generally cacheable.
1983	// In case of miss in itlb or dtlb, the tlb miss is handled by a dedicated
1984	// sub-fsm (DCACHE_TLB_MISS state), that handle possible miss in DCACHE,
1985	// this sub-fsm implement the table-walk...
1986	//
1987	// 3/ processor requests
1988	// Processor requests are taken in IDLE state only.
1989	// The IDLE state implements a two stages pipe-line to handle write bursts:
1990	// - Both DTLB and DCACHE are accessed in stage P0 (if processor request valid).
1991	// - The registration in wbuf and the dcache update is done in stage P1
1992	// (if the processor request is a write).
1993	// The two r_dcache_wbuf_req and r_dcache_updt_req flip-flops define
1994	// the operations that must be done in P1 stage, and the access type
1995	// (read or write) to the DATA part of DCACHE depends on r_dcache_updt_req.
1996	// READ requests are delayed if a cache update is requested.
1997	// WRITE or SC requests can require a PTE Dirty bit update (in memory),
1998	// that is done (before handling the processor request) by a dedicated sub-fsm.
1999	// If a PTE is modified, both the itlb and dtlb are selectively, but sequencially
2000	// cleared by a dedicated sub_fsm (DCACHE_INVAL_TLB_SCAN state).
2001	//
2002	// 4/ Atomic instructions LL/SC
2003	// The LL/SC address are non cacheable (systematic access to memory).
2004	// The llsc buffer contains a registration for an active LL/SC operation
2005	// (with an address, a registration key, an aging counter and a valid bit).
2006	// - LL requests from the processor are transmitted as a one flit VCI command
2007	// (CMD_LOCKED_READ as CMD, and TYPE_LL as PKTID value). PLEN must
2008	// be 8 as the response is 2 flits long (data and registration key)
2009	// - SC requests from the processor are systematically transmitted to the
2010	// memory cache as 2 flits VCI command (CMD_STORE_COND as CMD, and TYPE_SC
2011	// as PKTID value). The first flit contains the registration key, the second
2012	// flit contains the data to write in case of success.
2013	// The cache is not updated, as this is done in case of success by the
2014	// coherence transaction.
2015	//
2016	// 5/ Non cacheable access:
2017	// This component implement a strong order between non cacheable access
2018	// (read or write) : A new non cacheable VCI transaction starts only when
2019	// the previous non cacheable transaction is completed. Both cacheable and
2020	// non cacheable transactions use the write buffer, but the DCACHE FSM registers
2021	// a non cacheable write transaction posted in the write buffer by setting the
2022	// r_dcache_pending_unc_write flip_flop. All other non cacheable requests
2023	// are stalled until this flip-flop is reset by the VCI_RSP_FSM (when the
2024	// pending non cacheable write transaction completes).
2025	//
2026	// 6/ Error handling:
2027	// When the MMU is not activated, Read Bus Errors are synchronous events,
2028	// but Write Bus Errors are asynchronous events (processor is not frozen).
2029	// - If a Read Bus Error is detected, the VCI_RSP FSM sets the
2030	// r_vci_rsp_data_error flip-flop, without writing any data in the
2031	// r_vci_rsp_fifo_dcache FIFO, and the synchronous error is signaled
2032	// by the DCACHE FSM.
2033	// - If a Write Bus Error is detected, the VCI_RSP FSM signals
2034	// the asynchronous error using the setWriteBerr() method.
2035	// When the MMU is activated bus error are rare events, as the MMU
2036	// checks the physical address before the VCI transaction starts.
2037	////////////////////////////////////////////////////////////////////////////////////////
2038
2039	// default value for m_drsp
2040	m_drsp.valid = false;
2041	m_drsp.error = false;
2042	m_drsp.rdata = 0;
2043
2044	switch ( r_dcache_fsm.read() )
2045	{
2046	case DCACHE_IDLE: // There are 10 conditions to exit the IDLE state :
2047	// 1) ITLB/DTLB inval request (update) => DCACHE_INVAL_TLB_SCAN
2048	// 2) Coherence request (TGT FSM) => DCACHE_CC_CHECK
2049	// 3) ITLB miss request (ICACHE FSM) => DCACHE_TLB_MISS
2050	// 4) XTN request (processor) => DCACHE_XTN_*
2051	// 5) DTLB miss (processor) => DCACHE_TLB_MISS
2052	// 6) Dirty bit update (processor) => DCACHE_DIRTY_GET_PTE
2053	// 7) Cacheable read miss (processor) => DCACHE_MISS_SELECT
2054	// 8) Uncacheable read (processor) => DCACHE_UNC_WAIT
2055	// 9) LL access (processor) => DCACHE_LL_WAIT
2056	// 10) SC access (processor) => DCACHE_SC_WAIT
2057	//
2058	// There is a fixed priority to handle requests to DCACHE:
2059	// 1/ the ITLB/DTLB invalidate requests
2060	// 2/ the coherence requests,
2061	// 3/ the processor requests (including DTLB miss),
2062	// 4/ the ITLB miss requests,
2063	// The address space processor request are handled as follows:
2064	// - WRITE request is blocked if the Dirty bit mus be set.
2065	// If DTLB hit, the P1 stage is activated (writes WBUF, and
2066	// updates DCACHE if DCACHE hit) & processor request acknowledged.
2067	// - READ request generate a simultaneouss access to DCACHE.DATA
2068	// and DCACHE.DIR, but is delayed if DCACHE update required.
2069	//
2070	// There is 4 configurations defining the access type to
2071	// DTLB, DCACHE.DATA, and DCACHE.DIR, depending on the
2072	// dreq.valid (dreq) and r_dcache_updt_req (updt) signals:
2073	// dreq / updt / DTLB / DCACHE.DIR / DCACHE.DATA /
2074	// 0 / 0 / NOP / NOP / NOP /
2075	// 0 / 1 / NOP / NOP / WRITE /
2076	// 1 / 0 / READ / READ / NOP /
2077	// 1 / 1 / READ / READ / WRITE /
2078	// Those two registers are set at each cycle from the 3 signals
2079	// updt_request, wbuf_request, wbuf_write_miss.
2080	{
2081	paddr_t paddr; // physical address
2082	pte_info_t tlb_flags;
2083	size_t tlb_way;
2084	size_t tlb_set;
2085	paddr_t tlb_nline;
2086	size_t cache_way;
2087	size_t cache_set;
2088	size_t cache_word;
2089	uint32_t cache_rdata = 0;
2090	bool tlb_hit = false;
2091	int cache_state = CACHE_SLOT_STATE_EMPTY;
2092
2093	bool tlb_inval_required = false; // request TLB inval after cache update
2094	bool wbuf_write_miss = false; // miss a WBUF write request
2095	bool updt_request = false; // request DCACHE update in P1 stage
2096	bool wbuf_request = false; // request WBUF write in P1 stage
2097
2098	// physical address computation : systematic DTLB access if activated)
2099	if ( m_dreq.valid )
2100	{
2101	if ( r_mmu_mode.read() & DATA_TLB_MASK ) // DTLB activated
2102	{
2103	tlb_hit = r_dtlb.translate( m_dreq.addr,
2104	&paddr,
2105	&tlb_flags,
2106	&tlb_nline,
2107	&tlb_way,
2108	&tlb_set );
2109	#ifdef INSTRUMENTATION
2110	m_cpt_dtlb_read++;
2111	#endif
2112	}
2113	else // identity mapping
2114	{
2115	paddr = (paddr_t)m_dreq.addr;
2116	}
2117	} // end physical address computation
2118
2119	// systematic DCACHE access depending on r_dcache_updt_req (if activated)
2120	if ( r_mmu_mode.read() & DATA_CACHE_MASK)
2121	{
2122	if ( m_dreq.valid and r_dcache_updt_req.read() ) // read DIR and write DATA
2123	{
2124	r_dcache.read_dir( paddr,
2125	&cache_state,
2126	&cache_way,
2127	&cache_set,
2128	&cache_word );
2129
2130	r_dcache.write( r_dcache_save_cache_way.read(),
2131	r_dcache_save_cache_set.read(),
2132	r_dcache_save_cache_word.read(),
2133	r_dcache_save_wdata.read(),
2134	r_dcache_save_be.read() );
2135	#ifdef INSTRUMENTATION
2136	m_cpt_dcache_dir_read++;
2137	m_cpt_dcache_data_write++;
2138	#endif
2139	}
2140	else if ( m_dreq.valid and not r_dcache_updt_req.read() ) // read DIR and DATA
2141	{
2142	r_dcache.read( paddr,
2143	&cache_rdata,
2144	&cache_way,
2145	&cache_set,
2146	&cache_word,
2147	&cache_state );
2148
2149	#ifdef INSTRUMENTATION
2150	m_cpt_dcache_dir_read++;
2151	m_cpt_dcache_data_read++;
2152	#endif
2153	}
2154	else if ( not m_dreq.valid and r_dcache_updt_req.read() ) // write DATA
2155	{
2156	r_dcache.write( r_dcache_save_cache_way.read(),
2157	r_dcache_save_cache_set.read(),
2158	r_dcache_save_cache_word.read(),
2159	r_dcache_save_wdata.read(),
2160	r_dcache_save_be.read() );
2161	#ifdef INSTRUMENTATION
2162	m_cpt_dcache_data_write++;
2163	#endif
2164	}
2165	} // end dcache access
2166
2167	// DCACHE update in P1 stage can require ITLB / DTLB inval or flush
2168	if ( r_dcache_updt_req.read() )
2169	{
2170	size_t way = r_dcache_save_cache_way.read();
2171	size_t set = r_dcache_save_cache_set.read();
2172
2173	if ( r_dcache_in_tlb[way*m_dcache_sets+set] )
2174	{
2175	tlb_inval_required = true;
2176	r_dcache_tlb_inval_set = 0;
2177	r_dcache_tlb_inval_line = r_dcache_save_paddr.read()>>
2178	(uint32_log2(m_dcache_words<<2));
2179	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
2180	}
2181	else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] )
2182	{
2183	r_itlb.reset();
2184	r_dtlb.reset();
2185	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
2186	}
2187
2188	#if DEBUG_DCACHE
2189	if ( m_debug_dcache_fsm )
2190	{
2191	std::cout << " <PROC " << name()
2192	<< " DCACHE_IDLE> Cache update in P1 stage" << std::dec
2193	<< " / WAY = " << r_dcache_save_cache_way.read()
2194	<< " / SET = " << r_dcache_save_cache_set.read()
2195	<< " / WORD = " << r_dcache_save_cache_word.read() << std::hex
2196	<< " / DATA = " << r_dcache_save_wdata.read()
2197	<< " / BE = " << r_dcache_save_be.read() << std::endl;
2198	}
2199	#endif
2200	} // end test TLB inval
2201
2202	// Try WBUF update in P1 stage
2203	// Miss if the write request is non cacheable, and there is a pending
2204	// non cacheable write, or if the write buffer is full.
2205	if ( r_dcache_wbuf_req.read() )
2206	{
2207	// miss if write not cacheable, and previous non cacheable write registered
2208	if ( not r_dcache_save_cacheable.read() and r_dcache_pending_unc_write.read() )
2209	{
2210	wbuf_write_miss = true;
2211	}
2212	else // try a registration into write buffer
2213	{
2214	bool wok = r_wbuf.write( r_dcache_save_paddr.read(),
2215	r_dcache_save_be.read(),
2216	r_dcache_save_wdata.read(),
2217	r_dcache_save_cacheable.read() );
2218	#ifdef INSTRUMENTATION
2219	m_cpt_wbuf_write++;
2220	#endif
2221	if ( not wok ) // miss if write buffer full
2222	{
2223	wbuf_write_miss = true;
2224	}
2225	else // update the write_buffer state extension
2226	{
2227	if(not r_dcache_pending_unc_write.read())
2228	r_dcache_pending_unc_write = not r_dcache_save_cacheable.read();
2229	}
2230	}
2231	} // end WBUF update
2232
2233	// Computing the response to processor,
2234	// and the next value for r_dcache_fsm
2235
2236	// itlb/dtlb invalidation self-request
2237	if ( tlb_inval_required )
2238	{
2239	r_dcache_fsm_scan_save = r_dcache_fsm.read();
2240	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
2241	}
2242
2243	// coherence request (from CC_RECEIVE FSM)
2244	else if ( r_cc_receive_dcache_req.read() )
2245	{
2246	r_dcache_fsm = DCACHE_CC_CHECK;
2247	r_dcache_fsm_cc_save = r_dcache_fsm.read();
2248	}
2249
2250	// processor request (READ, WRITE, LL, SC, XTN_READ, XTN_WRITE)
2251	// we don't take the processor request, and registers
2252	// are frozen in case of wbuf_write_miss
2253	else if ( m_dreq.valid and not wbuf_write_miss )
2254	{
2255	// register processor request and DCACHE response
2256	r_dcache_save_vaddr = m_dreq.addr;
2257	r_dcache_save_be = m_dreq.be;
2258	r_dcache_save_wdata = m_dreq.wdata;
2259	r_dcache_save_paddr = paddr;
2260	r_dcache_save_cache_way = cache_way;
2261	r_dcache_save_cache_set = cache_set;
2262	r_dcache_save_cache_word = cache_word;
2263
2264	// READ XTN requests from processor
2265	// They are executed in this DCACHE_IDLE state.
2266	// The processor must not be in user mode
2267	if (m_dreq.type == iss_t::XTN_READ)
2268	{
2269	int xtn_opcode = (int)m_dreq.addr/4;
2270
2271	// checking processor mode:
2272	if (m_dreq.mode == iss_t::MODE_USER)
2273	{
2274	r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION;
2275	r_mmu_dbvar = m_dreq.addr;
2276	m_drsp.valid = true;
2277	m_drsp.error = true;
2278	m_drsp.rdata = 0;
2279	r_dcache_fsm = DCACHE_IDLE;
2280	}
2281	else
2282	{
2283	switch( xtn_opcode )
2284	{
2285	case iss_t::XTN_INS_ERROR_TYPE:
2286	m_drsp.rdata = r_mmu_ietr.read();
2287	m_drsp.valid = true;
2288	m_drsp.error = false;
2289	break;
2290
2291	case iss_t::XTN_DATA_ERROR_TYPE:
2292	m_drsp.rdata = r_mmu_detr.read();
2293	m_drsp.valid = true;
2294	m_drsp.error = false;
2295	break;
2296
2297	case iss_t::XTN_INS_BAD_VADDR:
2298	m_drsp.rdata = r_mmu_ibvar.read();
2299	m_drsp.valid = true;
2300	m_drsp.error = false;
2301	break;
2302
2303	case iss_t::XTN_DATA_BAD_VADDR:
2304	m_drsp.rdata = r_mmu_dbvar.read();
2305	m_drsp.valid = true;
2306	m_drsp.error = false;
2307	break;
2308
2309	case iss_t::XTN_PTPR:
2310	m_drsp.rdata = r_mmu_ptpr.read();
2311	m_drsp.valid = true;
2312	m_drsp.error = false;
2313	break;
2314
2315	case iss_t::XTN_TLB_MODE:
2316	m_drsp.rdata = r_mmu_mode.read();
2317	m_drsp.valid = true;
2318	m_drsp.error = false;
2319	break;
2320
2321	case iss_t::XTN_MMU_PARAMS:
2322	m_drsp.rdata = r_mmu_params;
2323	m_drsp.valid = true;
2324	m_drsp.error = false;
2325	break;
2326
2327	case iss_t::XTN_MMU_RELEASE:
2328	m_drsp.rdata = r_mmu_release;
2329	m_drsp.valid = true;
2330	m_drsp.error = false;
2331	break;
2332
2333	case iss_t::XTN_MMU_WORD_LO:
2334	m_drsp.rdata = r_mmu_word_lo.read();
2335	m_drsp.valid = true;
2336	m_drsp.error = false;
2337	break;
2338
2339	case iss_t::XTN_MMU_WORD_HI:
2340	m_drsp.rdata = r_mmu_word_hi.read();
2341	m_drsp.valid = true;
2342	m_drsp.error = false;
2343	break;
2344
2345	default:
2346	r_mmu_detr = MMU_READ_UNDEFINED_XTN;
2347	r_mmu_dbvar = m_dreq.addr;
2348	m_drsp.valid = true;
2349	m_drsp.error = true;
2350	m_drsp.rdata = 0;
2351	break;
2352	} // end switch xtn_opcode
2353	} // end else
2354	} // end if XTN_READ
2355
2356	// Handling WRITE XTN requests from processor.
2357	// They are not executed in this DCACHE_IDLE state
2358	// if they require access to the caches or the TLBs
2359	// that are already accessed.
2360	// Caches can be invalidated or flushed in user mode,
2361	// and the sync instruction can be executed in user mode
2362	else if (m_dreq.type == iss_t::XTN_WRITE)
2363	{
2364	int xtn_opcode = (int)m_dreq.addr/4;
2365	r_dcache_xtn_opcode = xtn_opcode;
2366
2367	// checking processor mode:
2368	if ( (m_dreq.mode == iss_t::MODE_USER) &&
2369	(xtn_opcode != iss_t::XTN_SYNC) &&
2370	(xtn_opcode != iss_t::XTN_DCACHE_INVAL) &&
2371	(xtn_opcode != iss_t::XTN_DCACHE_FLUSH) &&
2372	(xtn_opcode != iss_t::XTN_ICACHE_INVAL) &&
2373	(xtn_opcode != iss_t::XTN_ICACHE_FLUSH) )
2374	{
2375	r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION;
2376	r_mmu_dbvar = m_dreq.addr;
2377	m_drsp.valid = true;
2378	m_drsp.error = true;
2379	m_drsp.rdata = 0;
2380	r_dcache_fsm = DCACHE_IDLE;
2381	}
2382	else
2383	{
2384	switch( xtn_opcode )
2385	{
2386	case iss_t::XTN_PTPR: // itlb & dtlb must be flushed
2387	r_dcache_xtn_req = true;
2388	r_dcache_fsm = DCACHE_XTN_SWITCH;
2389	break;
2390
2391	case iss_t::XTN_TLB_MODE: // no cache or tlb access
2392	r_mmu_mode = m_dreq.wdata;
2393	m_drsp.valid = true;
2394	r_dcache_fsm = DCACHE_IDLE;
2395	break;
2396
2397	case iss_t::XTN_DTLB_INVAL: // dtlb access
2398	r_dcache_fsm = DCACHE_XTN_DT_INVAL;
2399	break;
2400
2401	case iss_t::XTN_ITLB_INVAL: // itlb access
2402	r_dcache_xtn_req = true;
2403	r_dcache_fsm = DCACHE_XTN_IT_INVAL;
2404	break;
2405
2406	case iss_t::XTN_DCACHE_INVAL: // dcache, dtlb & itlb access
2407	r_dcache_fsm = DCACHE_XTN_DC_INVAL_VA;
2408	break;
2409
2410	case iss_t::XTN_MMU_DCACHE_PA_INV: // dcache, dtlb & itlb access
2411	r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA;
2412	if (sizeof(paddr_t) <= 32)
2413	{
2414	assert(r_mmu_word_hi.read() == 0 &&
2415	"high bits should be 0 for 32bit paddr");
2416	r_dcache_save_paddr = (paddr_t)r_mmu_word_lo.read();
2417	}
2418	else
2419	{
2420	r_dcache_save_paddr = (paddr_t)r_mmu_word_hi.read() << 32 \|
2421	(paddr_t)r_mmu_word_lo.read();
2422	}
2423	break;
2424
2425	case iss_t::XTN_DCACHE_FLUSH: // itlb and dtlb must be reset
2426	r_dcache_flush_count = 0;
2427	r_dcache_fsm = DCACHE_XTN_DC_FLUSH;
2428	break;
2429
2430	case iss_t::XTN_ICACHE_INVAL: // icache and itlb access
2431	r_dcache_xtn_req = true;
2432	r_dcache_fsm = DCACHE_XTN_IC_INVAL_VA;
2433	break;
2434
2435	case iss_t::XTN_MMU_ICACHE_PA_INV: // icache access
2436	r_dcache_xtn_req = true;
2437	r_dcache_fsm = DCACHE_XTN_IC_INVAL_PA;
2438	break;
2439
2440	case iss_t::XTN_ICACHE_FLUSH: // icache access
2441	r_dcache_xtn_req = true;
2442	r_dcache_fsm = DCACHE_XTN_IC_FLUSH;
2443	break;
2444
2445	case iss_t::XTN_SYNC: // wait until write buffer empty
2446	r_dcache_fsm = DCACHE_XTN_SYNC;
2447	break;
2448
2449	case iss_t::XTN_MMU_WORD_LO: // no cache or tlb access
2450	r_mmu_word_lo = m_dreq.wdata;
2451	m_drsp.valid = true;
2452	r_dcache_fsm = DCACHE_IDLE;
2453	break;
2454
2455	case iss_t::XTN_MMU_WORD_HI: // no cache or tlb access
2456	r_mmu_word_hi = m_dreq.wdata;
2457	m_drsp.valid = true;
2458	r_dcache_fsm = DCACHE_IDLE;
2459	break;
2460
2461	case iss_t::XTN_MMU_LL_RESET: // no cache or tlb access
2462	r_dcache_llsc_valid = false;
2463	m_drsp.valid = true;
2464	r_dcache_fsm = DCACHE_IDLE;
2465	break;
2466
2467	case iss_t::XTN_ICACHE_PREFETCH: // not implemented : no action
2468	case iss_t::XTN_DCACHE_PREFETCH: // not implemented : no action
2469	m_drsp.valid = true;
2470	r_dcache_fsm = DCACHE_IDLE;
2471	break;
2472
2473	default:
2474	r_mmu_detr = MMU_WRITE_UNDEFINED_XTN;
2475	r_mmu_dbvar = m_dreq.addr;
2476	m_drsp.valid = true;
2477	m_drsp.error = true;
2478	r_dcache_fsm = DCACHE_IDLE;
2479	break;
2480	} // end switch xtn_opcode
2481	} // end else
2482	} // end if XTN_WRITE
2483
2484	// Handling processor requests to address space (READ/WRITE/LL/SC)
2485	// The dtlb and dcache can be activated or not.
2486	// We compute the cacheability, and check processor request validity:
2487	// - If DTLB not activated : cacheability is defined by the segment table,
2488	// and there is no access rights checking.
2489	// - If DTLB activated : cacheability is defined by the C bit in the PTE,
2490	// and the U & W bits of the PTE are checked, as well as the DTLB hit.
2491	// Jumps to the TLB_MISS sub-fsm in case of dtlb miss.
2492	else
2493	{
2494	bool valid_req;
2495	bool cacheable;
2496
2497	if ( not (r_mmu_mode.read() & DATA_TLB_MASK) ) // dtlb not activated
2498	{
2499	valid_req = true;
2500
2501	if ( not (r_mmu_mode.read() & DATA_CACHE_MASK) ) cacheable = false;
2502	else cacheable = m_cacheability_table[m_dreq.addr];
2503	}
2504	else // dtlb activated
2505	{
2506	if ( tlb_hit ) // tlb hit
2507	{
2508	// cacheability
2509	if ( not (r_mmu_mode.read() & DATA_CACHE_MASK) ) cacheable = false;
2510	else cacheable = tlb_flags.c;
2511
2512	// access rights checking
2513	if ( not tlb_flags.u and (m_dreq.mode == iss_t::MODE_USER))
2514	{
2515	if ( (m_dreq.type == iss_t::DATA_READ) or
2516	(m_dreq.type == iss_t::DATA_LL) )
2517	{
2518	r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION;
2519	}
2520	else
2521	{
2522	r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION;
2523	}
2524	valid_req = false;
2525	r_mmu_dbvar = m_dreq.addr;
2526	m_drsp.valid = true;
2527	m_drsp.error = true;
2528	m_drsp.rdata = 0;
2529	#if DEBUG_DCACHE
2530	if ( m_debug_dcache_fsm )
2531	{
2532	std::cout << " <PROC " << name()
2533	<< ".DCACHE_IDLE> HIT in dtlb, but privilege violation" << std::endl;
2534	}
2535	#endif
2536	}
2537	else if ( not tlb_flags.w and
2538	((m_dreq.type == iss_t::DATA_WRITE) or
2539	(m_dreq.type == iss_t::DATA_SC)) )
2540	{
2541	r_mmu_detr = MMU_WRITE_ACCES_VIOLATION;
2542	valid_req = false;
2543	r_mmu_dbvar = m_dreq.addr;
2544	m_drsp.valid = true;
2545	m_drsp.error = true;
2546	m_drsp.rdata = 0;
2547	#if DEBUG_DCACHE
2548	if ( m_debug_dcache_fsm )
2549	{
2550	std::cout << " <PROC " << name()
2551	<< ".DCACHE_IDLE> HIT in dtlb, but writable violation" << std::endl;
2552	}
2553	#endif
2554	}
2555	else
2556	{
2557	valid_req = true;
2558	}
2559	}
2560	else // tlb miss
2561	{
2562	valid_req = false;
2563	r_dcache_tlb_vaddr = m_dreq.addr;
2564	r_dcache_tlb_ins = false;
2565	r_dcache_fsm = DCACHE_TLB_MISS;
2566	}
2567	} // end DTLB activated
2568
2569	if ( valid_req ) // processor request is valid after TLB check
2570	{
2571	r_dcache_save_cacheable = cacheable;
2572
2573	// READ request
2574	// The read requests are taken only if there is no cache update.
2575	// We request a VCI transaction to CMD FSM if miss or uncachable
2576
2577	if ( ((m_dreq.type == iss_t::DATA_READ))
2578	and not r_dcache_updt_req.read() )
2579	{
2580	if ( cacheable ) // cacheable read
2581	{
2582	if ( cache_state == CACHE_SLOT_STATE_EMPTY ) // cache miss
2583	{
2584	#ifdef INSTRUMENTATION
2585	m_cpt_dcache_miss++;
2586	#endif
2587	// request a VCI DMISS transaction
2588	r_dcache_vci_paddr = paddr;
2589	r_dcache_vci_miss_req = true;
2590	r_dcache_miss_type = PROC_MISS;
2591	r_dcache_fsm = DCACHE_MISS_SELECT;
2592	#if DEBUG_DCACHE
2593	if ( m_debug_dcache_fsm )
2594	{
2595	std::cout << " <PROC " << name()
2596	<< ".DCACHE_IDLE> READ MISS in dcache" << std::endl;
2597	}
2598	#endif
2599	}
2600	else if (cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup
2601	{
2602	// stalled until cleanup is acknowledged
2603	r_dcache_fsm = DCACHE_IDLE;
2604	}
2605	else // cache hit
2606	{
2607	#ifdef INSTRUMENTATION
2608	m_cpt_data_read++;
2609	#endif
2610	// returns data to processor
2611	m_drsp.valid = true;
2612	m_drsp.error = false;
2613	m_drsp.rdata = cache_rdata;
2614	#if DEBUG_DCACHE
2615	if ( m_debug_dcache_fsm )
2616	{
2617	std::cout << " <PROC " << name()
2618	<< ".DCACHE_IDLE> READ HIT in dcache" << std::endl;
2619	}
2620	#endif
2621	}
2622	}
2623	else // uncacheable read
2624	{
2625	r_dcache_vci_paddr = paddr;
2626	r_dcache_vci_unc_be = m_dreq.be;
2627	r_dcache_vci_unc_req = true;
2628	r_dcache_fsm = DCACHE_UNC_WAIT;
2629	#if DEBUG_DCACHE
2630	if ( m_debug_dcache_fsm )
2631	{
2632	std::cout << " <PROC " << name()
2633	<< ".DCACHE_IDLE> READ UNCACHEABLE in dcache" << std::endl;
2634	}
2635	#endif
2636	}
2637	} // end READ
2638
2639	// LL request (non cachable)
2640	// We request a VCI LL transaction to CMD FSM and register
2641	// the LL/SC operation in llsc buffer.
2642	else if (m_dreq.type == iss_t::DATA_LL)
2643	{
2644	// register paddr in LLSC buffer
2645	r_dcache_llsc_paddr = paddr;
2646	r_dcache_llsc_count = LLSC_TIMEOUT;
2647	r_dcache_llsc_valid = true;
2648
2649	// request an LL VCI transaction and go to DCACHE_LL_WAIT state
2650	r_dcache_vci_ll_req = true;
2651	r_dcache_vci_paddr = paddr;
2652	r_dcache_ll_rsp_count = 0;
2653	r_dcache_fsm = DCACHE_LL_WAIT;
2654
2655	}// end LL
2656
2657	// WRITE request:
2658	// If the TLB is activated and the PTE Dirty bit is not set, we stall
2659	// the processor and set the Dirty bit before handling the write request,
2660	// going to the DCACHE_DIRTY_GT_PTE state.
2661	// If we don't need to set the Dirty bit, we can acknowledge
2662	// the processor request, as the write arguments (including the
2663	// physical address) are registered in r_dcache_save registers,
2664	// and the write will be done in the P1 pipeline stage.
2665	else if ( m_dreq.type == iss_t::DATA_WRITE )
2666	{
2667	if ( (r_mmu_mode.read() & DATA_TLB_MASK )
2668	and not tlb_flags.d ) // Dirty bit must be set
2669	{
2670	// The PTE physical address is obtained from the nline value (dtlb),
2671	// and from the virtual address (word index)
2672	if ( tlb_flags.b ) // PTE1
2673	{
2674	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2675	(paddr_t)((m_dreq.addr>>19) & 0x3c);
2676	}
2677	else // PTE2
2678	{
2679	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2680	(paddr_t)((m_dreq.addr>>9) & 0x38);
2681	}
2682	r_dcache_fsm = DCACHE_DIRTY_GET_PTE;
2683	}
2684	else // Write request accepted
2685	{
2686	#ifdef INSTRUMENTATION
2687	m_cpt_data_write++;
2688	#endif
2689	// cleaning llsc buffer if address matching
2690	if ( paddr == r_dcache_llsc_paddr.read() )
2691	r_dcache_llsc_valid = false;
2692
2693	// response to processor
2694	m_drsp.valid = true;
2695
2696	// activating P1 stage
2697	wbuf_request = true;
2698	updt_request = (cache_state == CACHE_SLOT_STATE_VALID);
2699	}
2700	} // end WRITE
2701
2702	// SC request:
2703	// If the TLB is activated and the PTE Dirty bit is not set, we stall
2704	// the processor and set the Dirty bit before handling the write request,
2705	// going to the DCACHE_DIRTY_GT_PTE state.
2706	// If we don't need to set the Dirty bit, we test the llsc buffer:
2707	// If failure, we send a negative response to processor.
2708	// If success, we request a SC transaction to CMD FSM and go
2709	// to DCACHE_SC_WAIT state.
2710	// We don't check a possible write hit in dcache, as the cache update
2711	// is done by the coherence transaction induced by the SC...
2712	else if ( m_dreq.type == iss_t::DATA_SC )
2713	{
2714	if ( (r_mmu_mode.read() & DATA_TLB_MASK )
2715	and not tlb_flags.d ) // Dirty bit must be set
2716	{
2717	// The PTE physical address is obtained from the nline value (dtlb),
2718	// and the word index (virtual address)
2719	if ( tlb_flags.b ) // PTE1
2720	{
2721	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2722	(paddr_t)((m_dreq.addr>>19) & 0x3c);
2723	}
2724	else // PTE2
2725	{
2726	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2727	(paddr_t)((m_dreq.addr>>9) & 0x38);
2728	}
2729	r_dcache_fsm = DCACHE_DIRTY_GET_PTE;
2730	m_drsp.valid = false;
2731	m_drsp.error = false;
2732	m_drsp.rdata = 0;
2733	}
2734	else // SC request accepted
2735	{
2736	#ifdef INSTRUMENTATION
2737	m_cpt_data_sc++;
2738	#endif
2739	// checking local success
2740	if( r_dcache_llsc_valid.read() and
2741	(r_dcache_llsc_paddr.read() == paddr) ) // local success
2742	{
2743	// request an SC CMD and go to DCACHE_SC_WAIT state
2744	r_dcache_vci_paddr = paddr;
2745	r_dcache_vci_sc_req = true;
2746	r_dcache_vci_sc_data = m_dreq.wdata;
2747	r_dcache_fsm = DCACHE_SC_WAIT;
2748	}
2749	else // local fail
2750	{
2751	m_drsp.valid = true;
2752	m_drsp.error = false;
2753	m_drsp.rdata = 0x1;
2754	}
2755	}
2756	} // end SC
2757	} // end valid_req
2758	} // end if read/write/ll/sc request
2759	} // end processor request
2760
2761	// itlb miss request
2762	else if ( r_icache_tlb_miss_req.read() and not wbuf_write_miss )
2763	{
2764	r_dcache_tlb_ins = true;
2765	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
2766	r_dcache_fsm = DCACHE_TLB_MISS;
2767	}
2768
2769	// Computing requests for P1 stage : r_dcache_wbuf_req & r_dcache_updt_req
2770	r_dcache_updt_req = updt_request;
2771	r_dcache_wbuf_req = wbuf_request or
2772	(r_dcache_wbuf_req.read() and wbuf_write_miss);
2773	break;
2774	}
2775	/////////////////////
2776	case DCACHE_TLB_MISS: // This is the entry point for the sub-fsm handling all tlb miss.
2777	// Input arguments are:
2778	// - r_dcache_tlb_vaddr
2779	// - r_dcache_tlb_ins (true when itlb miss)
2780	// The sub-fsm access the dcache to find the missing TLB entry,
2781	// and activates the cache miss procedure in case of miss.
2782	// It bypass the first level page table access if possible.
2783	// It uses atomic access to update the R/L access bits
2784	// in the page table if required.
2785	// It directly updates the itlb or dtlb, and writes into the
2786	// r_mmu_ins_* or r_mmu_data* error reporting registers.
2787	{
2788	uint32_t ptba = 0;
2789	bool bypass;
2790	paddr_t pte_paddr;
2791
2792	// evaluate bypass in order to skip first level page table access
2793	if ( r_dcache_tlb_ins.read() ) // itlb miss
2794	{
2795	bypass = r_itlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba);
2796	}
2797	else // dtlb miss
2798	{
2799	bypass = r_dtlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba);
2800	}
2801
2802	if ( not bypass ) // Try to read PTE1/PTD1 in dcache
2803	{
2804	pte_paddr = (paddr_t)r_mmu_ptpr.read() << (INDEX1_NBITS+2) \|
2805	(paddr_t)((r_dcache_tlb_vaddr.read() >> PAGE_M_NBITS) << 2);
2806	r_dcache_tlb_paddr = pte_paddr;
2807	r_dcache_fsm = DCACHE_TLB_PTE1_GET;
2808	}
2809	else // Try to read PTE2 in dcache
2810	{
2811	pte_paddr = (paddr_t)ptba << PAGE_K_NBITS \|
2812	(paddr_t)(r_dcache_tlb_vaddr.read()&PTD_ID2_MASK)>>(PAGE_K_NBITS-3);
2813	r_dcache_tlb_paddr = pte_paddr;
2814	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
2815	}
2816
2817	#if DEBUG_DCACHE
2818	if ( m_debug_dcache_fsm )
2819	{
2820	if ( r_dcache_tlb_ins.read() )
2821	{
2822	std::cout << " <PROC " << name() << ".DCACHE_TLB_MISS> ITLB miss";
2823	}
2824	else
2825	{
2826	std::cout << " <PROC " << name() << ".DCACHE_TLB_MISS> DTLB miss";
2827	}
2828	std::cout << " / VADDR = " << std::hex << r_dcache_tlb_vaddr.read()
2829	<< " / BYPASS = " << bypass
2830	<< " / PTE_ADR = " << pte_paddr << std::endl;
2831	}
2832	#endif
2833
2834	break;
2835	}
2836	/////////////////////////
2837	case DCACHE_TLB_PTE1_GET: // try to read a PT1 entry in dcache
2838	{
2839	// coherence request (from CC_RECEIVE FSM)
2840	if ( r_cc_receive_dcache_req.read() )
2841	{
2842	r_dcache_fsm = DCACHE_CC_CHECK;
2843	r_dcache_fsm_cc_save = r_dcache_fsm.read();
2844	break;
2845	}
2846
2847	uint32_t entry;
2848	size_t way;
2849	size_t set;
2850	size_t word;
2851	int cache_state;
2852	r_dcache.read( r_dcache_tlb_paddr.read(),
2853	&entry,
2854	&way,
2855	&set,
2856	&word,
2857	&cache_state );
2858	#ifdef INSTRUMENTATION
2859	m_cpt_dcache_data_read++;
2860	m_cpt_dcache_dir_read++;
2861	#endif
2862	if ( cache_state == CACHE_SLOT_STATE_VALID ) // hit in dcache
2863	{
2864	if ( not (entry & PTE_V_MASK) ) // unmapped
2865	{
2866	if ( r_dcache_tlb_ins.read() )
2867	{
2868	r_mmu_ietr = MMU_READ_PT1_UNMAPPED;
2869	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
2870	r_icache_tlb_miss_req = false;
2871	r_icache_tlb_rsp_error = true;
2872	}
2873	else
2874	{
2875	r_mmu_detr = MMU_READ_PT1_UNMAPPED;
2876	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
2877	m_drsp.valid = true;
2878	m_drsp.error = true;
2879	}
2880	r_dcache_fsm = DCACHE_IDLE;
2881
2882	#if DEBUG_DCACHE
2883	if ( m_debug_dcache_fsm )
2884	{
2885	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_GET> HIT in dcache, but unmapped"
2886	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
2887	<< std::dec << " / way = " << way
2888	<< std::dec << " / set = " << set
2889	<< std::dec << " / word = " << word
2890	<< std::hex << " / PTE1 = " << entry << std::endl;
2891	}
2892	#endif
2893
2894	}
2895	else if( entry & PTE_T_MASK ) // PTD : me must access PT2
2896	{
2897	// mark the cache line ac containing a PTD
2898	r_dcache_contains_ptd[m_dcache_sets*way+set] = true;
2899
2900	// register bypass
2901	if ( r_dcache_tlb_ins.read() ) // itlb
2902	{
2903	r_itlb.set_bypass(r_dcache_tlb_vaddr.read(),
2904	entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1),
2905	r_dcache_tlb_paddr.read() / (m_icache_words<<2) );
2906	}
2907	else // dtlb
2908	{
2909	r_dtlb.set_bypass(r_dcache_tlb_vaddr.read(),
2910	entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1),
2911	r_dcache_tlb_paddr.read() / (m_dcache_words<<2) );
2912	}
2913	r_dcache_tlb_paddr =
2914	(paddr_t)(entry & ((1<<(m_paddr_nbits-PAGE_K_NBITS))-1)) << PAGE_K_NBITS \|
2915	(paddr_t)(((r_dcache_tlb_vaddr.read() & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3);
2916	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
2917
2918	#if DEBUG_DCACHE
2919	if ( m_debug_dcache_fsm )
2920	{
2921	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_GET> HIT in dcache"
2922	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
2923	<< std::dec << " / way = " << way
2924	<< std::dec << " / set = " << set
2925	<< std::dec << " / word = " << word
2926	<< std::hex << " / PTD = " << entry << std::endl;
2927	}
2928	#endif
2929	}
2930	else // PTE1 : we must update the TLB
2931	{
2932	r_dcache_in_tlb[m_icache_sets*way+set] = true;
2933	r_dcache_tlb_pte_flags = entry;
2934	r_dcache_tlb_cache_way = way;
2935	r_dcache_tlb_cache_set = set;
2936	r_dcache_tlb_cache_word = word;
2937	r_dcache_fsm = DCACHE_TLB_PTE1_SELECT;
2938
2939	#if DEBUG_DCACHE
2940	if ( m_debug_dcache_fsm )
2941	{
2942	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_GET> HIT in dcache"
2943	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
2944	<< std::dec << " / way = " << way
2945	<< std::dec << " / set = " << set
2946	<< std::dec << " / word = " << word
2947	<< std::hex << " / PTE1 = " << entry << std::endl;
2948	}
2949	#endif
2950	}
2951	}
2952	else if ( cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup
2953	{
2954	// stalled until cleanup is acknowledged
2955	r_dcache_fsm = DCACHE_TLB_PTE1_GET;
2956	}
2957	else // we must load the missing cache line in dcache
2958	{
2959	r_dcache_vci_miss_req = true;
2960	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
2961	r_dcache_save_paddr = r_dcache_tlb_paddr.read();
2962	r_dcache_miss_type = PTE1_MISS;
2963	r_dcache_fsm = DCACHE_MISS_SELECT;
2964
2965	#if DEBUG_DCACHE
2966	if ( m_debug_dcache_fsm )
2967	{
2968	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_GET> MISS in dcache:"
2969	<< " PTE1 address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
2970	}
2971	#endif
2972	}
2973	break;
2974	}
2975	////////////////////////////
2976	case DCACHE_TLB_PTE1_SELECT: // select a slot for PTE1
2977	{
2978	size_t way;
2979	size_t set;
2980
2981	if ( r_dcache_tlb_ins.read() )
2982	{
2983	r_itlb.select( r_dcache_tlb_vaddr.read(),
2984	true, // PTE1
2985	&way,
2986	&set );
2987	#ifdef INSTRUMENTATION
2988	m_cpt_itlb_read++;
2989	#endif
2990	}
2991	else
2992	{
2993	r_dtlb.select( r_dcache_tlb_vaddr.read(),
2994	true, // PTE1
2995	&way,
2996	&set );
2997	#ifdef INSTRUMENTATION
2998	m_cpt_dtlb_read++;
2999	#endif
3000	}
3001	r_dcache_tlb_way = way;
3002	r_dcache_tlb_set = set;
3003	r_dcache_fsm = DCACHE_TLB_PTE1_UPDT;
3004
3005	#if DEBUG_DCACHE
3006	if ( m_debug_dcache_fsm )
3007	{
3008	if ( r_dcache_tlb_ins.read() )
3009	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_SELECT> Select a slot in ITLB:";
3010	else
3011	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_SELECT> Select a slot in DTLB:";
3012	std::cout << " way = " << std::dec << way
3013	<< " / set = " << set << std::endl;
3014	}
3015	#endif
3016	break;
3017	}
3018	//////////////////////////
3019	case DCACHE_TLB_PTE1_UPDT: // write a new PTE1 in tlb after testing the L/R bit
3020	// - if L/R bit already set, exit the sub-fsm.
3021	// - if not, we update the page table but we dont write
3022	// neither in DCACHE, nor in TLB, as this will be done by
3023	// the coherence mechanism.
3024	{
3025	paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2);
3026	uint32_t pte = r_dcache_tlb_pte_flags.read();
3027	bool pt_updt = false;
3028	bool local = true;
3029
3030	// We should compute the access locality:
3031	// The PPN MSB bits define the destination cluster index.
3032	// The m_srcid MSB bits define the source cluster index.
3033	// The number of bits to compare depends on the number of clusters,
3034	// and can be obtained in the mapping table.
3035	// As long as this computation is not done, all access are local.
3036
3037	if ( local ) // local access
3038	{
3039	if ( not ((pte & PTE_L_MASK) == PTE_L_MASK) ) // we must set the L bit
3040	{
3041	pt_updt = true;
3042	r_dcache_vci_cas_old = pte;
3043	r_dcache_vci_cas_new = pte \| PTE_L_MASK;
3044	pte = pte \| PTE_L_MASK;
3045	r_dcache_tlb_pte_flags = pte;
3046	}
3047	}
3048	else // remote access
3049	{
3050	if ( not ((pte & PTE_R_MASK) == PTE_R_MASK) ) // we must set the R bit
3051	{
3052	pt_updt = true;
3053	r_dcache_vci_cas_old = pte;
3054	r_dcache_vci_cas_new = pte \| PTE_R_MASK;
3055	pte = pte \| PTE_R_MASK;
3056	r_dcache_tlb_pte_flags = pte;
3057	}
3058	}
3059
3060	if ( not pt_updt ) // update TLB and return
3061	{
3062	if ( r_dcache_tlb_ins.read() )
3063	{
3064	r_itlb.write( true, // 2M page
3065	pte,
3066	0, // argument unused for a PTE1
3067	r_dcache_tlb_vaddr.read(),
3068	r_dcache_tlb_way.read(),
3069	r_dcache_tlb_set.read(),
3070	nline );
3071	#ifdef INSTRUMENTATION
3072	m_cpt_itlb_write++;
3073	#endif
3074
3075	#if DEBUG_DCACHE
3076	if ( m_debug_dcache_fsm )
3077	{
3078	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_UPDT> write PTE1 in ITLB";
3079	std::cout << " / set = " << std::dec << r_dcache_tlb_set.read()
3080	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3081	r_itlb.printTrace();
3082	}
3083	#endif
3084	}
3085	else
3086	{
3087	r_dtlb.write( true, // 2M page
3088	pte,
3089	0, // argument unused for a PTE1
3090	r_dcache_tlb_vaddr.read(),
3091	r_dcache_tlb_way.read(),
3092	r_dcache_tlb_set.read(),
3093	nline );
3094	#ifdef INSTRUMENTATION
3095	m_cpt_dtlb_write++;
3096	#endif
3097
3098	#if DEBUG_DCACHE
3099	if ( m_debug_dcache_fsm )
3100	{
3101	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_UPDT> write PTE1 in DTLB";
3102	std::cout << " / set = " << std::dec << r_dcache_tlb_set.read()
3103	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3104	r_dtlb.printTrace();
3105	}
3106	#endif
3107	}
3108	r_dcache_fsm = DCACHE_TLB_RETURN;
3109	}
3110	else // update page table but not TLB
3111	{
3112	r_dcache_fsm = DCACHE_TLB_LR_UPDT;
3113
3114	#if DEBUG_DCACHE
3115	if ( m_debug_dcache_fsm )
3116	{
3117	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_UPDT> L/R bit update required"
3118	<< std::endl;
3119	}
3120	#endif
3121	}
3122	break;
3123	}
3124	/////////////////////////
3125	case DCACHE_TLB_PTE2_GET: // Try to get a PTE2 (64 bits) in the dcache
3126	{
3127	// coherence request (from CC_RECEIVE FSM)
3128	if ( r_cc_receive_dcache_req.read() )
3129	{
3130	r_dcache_fsm = DCACHE_CC_CHECK;
3131	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3132	break;
3133	}
3134
3135	uint32_t pte_flags;
3136	uint32_t pte_ppn;
3137	size_t way;
3138	size_t set;
3139	size_t word;
3140	int cache_state;
3141
3142	r_dcache.read( r_dcache_tlb_paddr.read(),
3143	&pte_flags,
3144	&pte_ppn,
3145	&way,
3146	&set,
3147	&word,
3148	&cache_state );
3149	#ifdef INSTRUMENTATION
3150	m_cpt_dcache_data_read++;
3151	m_cpt_dcache_dir_read++;
3152	#endif
3153	if ( cache_state == CACHE_SLOT_STATE_VALID ) // hit in dcache
3154	{
3155	if ( not (pte_flags & PTE_V_MASK) ) // unmapped
3156	{
3157	if ( r_dcache_tlb_ins.read() )
3158	{
3159	r_mmu_ietr = MMU_READ_PT2_UNMAPPED;
3160	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3161	r_icache_tlb_miss_req = false;
3162	r_icache_tlb_rsp_error = true;
3163	}
3164	else
3165	{
3166	r_mmu_detr = MMU_READ_PT2_UNMAPPED;
3167	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3168	m_drsp.valid = true;
3169	m_drsp.error = true;
3170	}
3171	r_dcache_fsm = DCACHE_IDLE;
3172
3173	#if DEBUG_DCACHE
3174	if ( m_debug_dcache_fsm )
3175	{
3176	std::cout << " <PROC " << name()
3177	<< " DCACHE_TLB_PTE2_GET> HIT in dcache, but PTE is unmapped"
3178	<< " PTE_FLAGS = " << std::hex << pte_flags
3179	<< " PTE_PPN = " << std::hex << pte_ppn << std::endl;
3180	}
3181	#endif
3182	}
3183	else // mapped : we must update the TLB
3184	{
3185	r_dcache_in_tlb[m_dcache_sets*way+set] = true;
3186	r_dcache_tlb_pte_flags = pte_flags;
3187	r_dcache_tlb_pte_ppn = pte_ppn;
3188	r_dcache_tlb_cache_way = way;
3189	r_dcache_tlb_cache_set = set;
3190	r_dcache_tlb_cache_word = word;
3191	r_dcache_fsm = DCACHE_TLB_PTE2_SELECT;
3192
3193	#if DEBUG_DCACHE
3194	if ( m_debug_dcache_fsm )
3195	{
3196	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE2_GET> HIT in dcache:"
3197	<< " PTE_FLAGS = " << std::hex << pte_flags
3198	<< " PTE_PPN = " << std::hex << pte_ppn << std::endl;
3199	}
3200	#endif
3201	}
3202	}
3203	else if ( cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup
3204	{
3205	// stalled until cleanup is acknowledged
3206	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
3207	}
3208	else // we must load the missing cache line in dcache
3209	{
3210	r_dcache_fsm = DCACHE_MISS_SELECT;
3211	r_dcache_vci_miss_req = true;
3212	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
3213	r_dcache_save_paddr = r_dcache_tlb_paddr.read();
3214	r_dcache_miss_type = PTE2_MISS;
3215
3216	#if DEBUG_DCACHE
3217	if ( m_debug_dcache_fsm )
3218	{
3219	std::cout << " <PROC " << name()
3220	<< " DCACHE_TLB_PTE2_GET> MISS in dcache:"
3221	<< " PTE address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
3222	}
3223	#endif
3224	}
3225	break;
3226	}
3227	////////////////////////////
3228	case DCACHE_TLB_PTE2_SELECT: // select a slot for PTE2
3229	{
3230	size_t way;
3231	size_t set;
3232
3233	if ( r_dcache_tlb_ins.read() )
3234	{
3235	r_itlb.select( r_dcache_tlb_vaddr.read(),
3236	false, // PTE2
3237	&way,
3238	&set );
3239	#ifdef INSTRUMENTATION
3240	m_cpt_itlb_read++;
3241	#endif
3242	}
3243	else
3244	{
3245	r_dtlb.select( r_dcache_tlb_vaddr.read(),
3246	false, // PTE2
3247	&way,
3248	&set );
3249	#ifdef INSTRUMENTATION
3250	m_cpt_dtlb_read++;
3251	#endif
3252	}
3253
3254	#if DEBUG_DCACHE
3255	if ( m_debug_dcache_fsm )
3256	{
3257	if ( r_dcache_tlb_ins.read() )
3258	std::cout << " <PROC " << name()
3259	<< " DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB:";
3260	else
3261	std::cout << " <PROC " << name()
3262	<< " DCACHE_TLB_PTE2_SELECT> Select a slot in DTLB:";
3263	std::cout << " way = " << std::dec << way
3264	<< " / set = " << set << std::endl;
3265	}
3266	#endif
3267	r_dcache_tlb_way = way;
3268	r_dcache_tlb_set = set;
3269	r_dcache_fsm = DCACHE_TLB_PTE2_UPDT;
3270	break;
3271	}
3272	//////////////////////////
3273	case DCACHE_TLB_PTE2_UPDT: // write a new PTE2 in tlb after testing the L/R bit
3274	// - if L/R bit already set, exit the sub-fsm.
3275	// - if not, we update the page table but we dont write
3276	// neither in DCACHE, nor in TLB, as this will be done by
3277	// the coherence mechanism.
3278	{
3279	paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2);
3280	uint32_t pte_flags = r_dcache_tlb_pte_flags.read();
3281	uint32_t pte_ppn = r_dcache_tlb_pte_ppn.read();
3282	bool pt_updt = false;
3283	bool local = true;
3284
3285	// We should compute the access locality:
3286	// The PPN MSB bits define the destination cluster index.
3287	// The m_srcid MSB bits define the source cluster index.
3288	// The number of bits to compare depends on the number of clusters,
3289	// and can be obtained in the mapping table.
3290	// As long as this computation is not done, all access are local.
3291
3292	if ( local ) // local access
3293	{
3294	if ( not ((pte_flags & PTE_L_MASK) == PTE_L_MASK) ) // we must set the L bit
3295	{
3296	pt_updt = true;
3297	r_dcache_vci_cas_old = pte_flags;
3298	r_dcache_vci_cas_new = pte_flags \| PTE_L_MASK;
3299	pte_flags = pte_flags \| PTE_L_MASK;
3300	r_dcache_tlb_pte_flags = pte_flags;
3301	}
3302	}
3303	else // remote access
3304	{
3305	if ( not ((pte_flags & PTE_R_MASK) == PTE_R_MASK) ) // we must set the R bit
3306	{
3307	pt_updt = true;
3308	r_dcache_vci_cas_old = pte_flags;
3309	r_dcache_vci_cas_new = pte_flags \| PTE_R_MASK;
3310	pte_flags = pte_flags \| PTE_R_MASK;
3311	r_dcache_tlb_pte_flags = pte_flags;
3312	}
3313	}
3314
3315	if ( not pt_updt ) // update TLB
3316	{
3317	if ( r_dcache_tlb_ins.read() )
3318	{
3319	r_itlb.write( false, // 4K page
3320	pte_flags,
3321	pte_ppn,
3322	r_dcache_tlb_vaddr.read(),
3323	r_dcache_tlb_way.read(),
3324	r_dcache_tlb_set.read(),
3325	nline );
3326	#ifdef INSTRUMENTATION
3327	m_cpt_itlb_write++;
3328	#endif
3329
3330	#if DEBUG_DCACHE
3331	if ( m_debug_dcache_fsm )
3332	{
3333	std::cout << " <PROC " << name()
3334	<< " DCACHE_TLB_PTE2_UPDT> write PTE2 in ITLB"
3335	<< " / set = " << std::dec << r_dcache_tlb_set.read()
3336	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3337	r_itlb.printTrace();
3338	}
3339	#endif
3340	}
3341	else
3342	{
3343	r_dtlb.write( false, // 4K page
3344	pte_flags,
3345	pte_ppn,
3346	r_dcache_tlb_vaddr.read(),
3347	r_dcache_tlb_way.read(),
3348	r_dcache_tlb_set.read(),
3349	nline );
3350	#ifdef INSTRUMENTATION
3351	m_cpt_dtlb_write++;
3352	#endif
3353
3354	#if DEBUG_DCACHE
3355	if ( m_debug_dcache_fsm )
3356	{
3357	std::cout << " <PROC " << name()
3358	<< " DCACHE_TLB_PTE2_UPDT> write PTE2 in DTLB"
3359	<< " / set = " << std::dec << r_dcache_tlb_set.read()
3360	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3361	r_dtlb.printTrace();
3362	}
3363	#endif
3364
3365	}
3366	r_dcache_fsm = DCACHE_TLB_RETURN;
3367	}
3368	else // update page table but not TLB
3369	{
3370	r_dcache_fsm = DCACHE_TLB_LR_UPDT; // dcache and page table update
3371
3372	#if DEBUG_DCACHE
3373	if ( m_debug_dcache_fsm )
3374	{
3375	std::cout << " <PROC " << name()
3376	<< " DCACHE_TLB_PTE2_UPDT> L/R bit update required" << std::endl;
3377	}
3378	#endif
3379	}
3380	break;
3381	}
3382	////////////////////////
3383	case DCACHE_TLB_LR_UPDT: // request a CAS transaction to update L/R bit
3384	{
3385	#if DEBUG_DCACHE
3386	if ( m_debug_dcache_fsm )
3387	{
3388	std::cout << " <PROC " << name()
3389	<< " DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit" << std::endl;
3390	}
3391	#endif
3392	// r_dcache_vci_cas_old & r_dcache_vci_cas_new registers are already set
3393	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
3394
3395	// checking llsc reservation buffer
3396	if ( r_dcache_llsc_paddr.read() == r_dcache_tlb_paddr.read() )
3397	r_dcache_llsc_valid = false;
3398
3399	// request a CAS CMD and go to DCACHE_TLB_LR_WAIT state
3400	r_dcache_vci_cas_req = true;
3401	r_dcache_fsm = DCACHE_TLB_LR_WAIT;
3402	break;
3403	}
3404	////////////////////////
3405	case DCACHE_TLB_LR_WAIT: // Waiting the response to SC transaction for DIRTY bit.
3406	// We consume the response in rsp FIFO,
3407	// and exit the sub-fsm, but we don't
3408	// analyse the response, because we don't
3409	// care if the L/R bit update is not done.
3410	// We must take the coherence requests because
3411	// there is a risk of dead-lock
3412
3413	{
3414	// coherence request (from CC_RECEIVE FSM)
3415	if ( r_cc_receive_dcache_req.read() )
3416	{
3417	r_dcache_fsm = DCACHE_CC_CHECK;
3418	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3419	break;
3420	}
3421
3422	if ( r_vci_rsp_data_error.read() ) // bus error
3423	{
3424	std::cout << "BUS ERROR in DCACHE_TLB_LR_WAIT state" << std::endl;
3425	std::cout << "This should not happen in this state" << std::endl;
3426	exit(0);
3427	}
3428	else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
3429	{
3430	#if DEBUG_DCACHE
3431	if ( m_debug_dcache_fsm )
3432	{
3433	std::cout << " <PROC " << name()
3434	<< " DCACHE_TLB_LR_WAIT> SC response received" << std::endl;
3435	}
3436	#endif
3437	vci_rsp_fifo_dcache_get = true;
3438	r_dcache_fsm = DCACHE_TLB_RETURN;
3439	}
3440	break;
3441	}
3442	///////////////////////
3443	case DCACHE_TLB_RETURN: // return to caller depending on tlb miss type
3444	{
3445	#if DEBUG_DCACHE
3446	if ( m_debug_dcache_fsm )
3447	{
3448	std::cout << " <PROC " << name()
3449	<< " DCACHE_TLB_RETURN> TLB MISS completed" << std::endl;
3450	}
3451	#endif
3452	if ( r_dcache_tlb_ins.read() ) r_icache_tlb_miss_req = false;
3453	r_dcache_fsm = DCACHE_IDLE;
3454	break;
3455	}
3456	///////////////////////
3457	case DCACHE_XTN_SWITCH: // The r_ptpr registers must be written,
3458	// and both itlb and dtlb must be flushed.
3459	// Caution : the itlb miss requests must be taken
3460	// to avoid dead-lock in case of simultaneous ITLB miss
3461	{
3462	// itlb miss request
3463	if ( r_icache_tlb_miss_req.read() )
3464	{
3465	r_dcache_tlb_ins = true;
3466	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
3467	r_dcache_fsm = DCACHE_TLB_MISS;
3468	break;
3469	}
3470
3471	if ( not r_dcache_xtn_req.read() )
3472	{
3473	r_dtlb.flush();
3474	r_mmu_ptpr = m_dreq.wdata;
3475	r_dcache_fsm = DCACHE_IDLE;
3476	m_drsp.valid = true;
3477	}
3478	break;
3479	}
3480	/////////////////////
3481	case DCACHE_XTN_SYNC: // waiting until write buffer empty
3482	// The coherence request must be taken
3483	// as there is a risk of dead-lock
3484	{
3485	// coherence request (from CC_RECEIVE FSM)
3486	if ( r_cc_receive_dcache_req.read() )
3487	{
3488	r_dcache_fsm = DCACHE_CC_CHECK;
3489	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3490	}
3491
3492	if ( r_wbuf.empty() )
3493	{
3494	m_drsp.valid = true;
3495	r_dcache_fsm = DCACHE_IDLE;
3496	}
3497	break;
3498	}
3499	////////////////////////
3500	case DCACHE_XTN_IC_FLUSH: // Waiting completion of an XTN request to the ICACHE FSM
3501	case DCACHE_XTN_IC_INVAL_VA: // Caution : the itlb miss requests must be taken
3502	case DCACHE_XTN_IC_INVAL_PA: // because the XTN_ICACHE_INVAL request to icache
3503	case DCACHE_XTN_IT_INVAL: // can generate an itlb miss,
3504	// and because it can exist a simultaneous ITLB miss
3505	{
3506	// coherence request (from CC_RECEIVE FSM)
3507	if ( r_cc_receive_dcache_req.read() )
3508	{
3509	r_dcache_fsm = DCACHE_CC_CHECK;
3510	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3511	break;
3512	}
3513
3514	// itlb miss request
3515	if ( r_icache_tlb_miss_req.read() )
3516	{
3517	r_dcache_tlb_ins = true;
3518	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
3519	r_dcache_fsm = DCACHE_TLB_MISS;
3520	break;
3521	}
3522
3523	// test if XTN request to icache completed
3524	if ( not r_dcache_xtn_req.read() )
3525	{
3526	r_dcache_fsm = DCACHE_IDLE;
3527	m_drsp.valid = true;
3528	}
3529	break;
3530	}
3531	/////////////////////////
3532	case DCACHE_XTN_DC_FLUSH: // Invalidate sequencially all cache lines, using
3533	// r_dcache_flush_count as a slot counter,
3534	// looping in this state until all slots have been visited.
3535	// It can require two cycles per slot:
3536	// We test here the slot state, and make the actual inval
3537	// (if line is valid) in DCACHE_XTN_DC_FLUSH_GO state.
3538	// A cleanup request is generated for each valid line.
3539	// returns to IDLE and flush TLBs when last slot
3540	{
3541	if ( not r_dcache_cc_send_req.read() ) // blocked until previous cc_send request is sent
3542	{
3543	int state;
3544	uint32_t tag;
3545	size_t way = r_dcache_flush_count.read()/m_dcache_sets;
3546	size_t set = r_dcache_flush_count.read()%m_dcache_sets;
3547
3548	#ifdef INSTRUMENTATION
3549	m_cpt_dcache_dir_read++;
3550	#endif
3551	r_dcache.read_dir( way,
3552	set,
3553	&tag,
3554	&state );
3555
3556	if ( state == CACHE_SLOT_STATE_VALID ) // inval required
3557	{
3558	// request cleanup
3559	r_dcache_cc_send_req = true;
3560	r_dcache_cc_send_nline = tag * m_dcache_sets;
3561	r_dcache_cc_send_way = way;
3562	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
3563
3564	// goes to DCACHE_XTN_DC_FLUSH_GO to inval directory
3565	r_dcache_miss_way = way;
3566	r_dcache_miss_set = set;
3567	r_dcache_fsm = DCACHE_XTN_DC_FLUSH_GO;
3568	}
3569	else if ( r_dcache_flush_count.read() ==
3570	(m_dcache_sets*m_dcache_ways - 1) ) // last slot
3571	{
3572	r_dtlb.reset();
3573	r_itlb.reset();
3574	r_dcache_fsm = DCACHE_IDLE;
3575	m_drsp.valid = true;
3576	}
3577
3578	// saturation counter
3579	if ( r_dcache_flush_count.read() < (m_dcache_sets*m_dcache_ways - 1) )
3580	r_dcache_flush_count = r_dcache_flush_count.read() + 1;
3581	}
3582	break;
3583	}
3584	////////////////////////////
3585	case DCACHE_XTN_DC_FLUSH_GO: // Switch the cache slot to ZOMBI state
3586	// and reset directory extension.
3587	// returns to IDLE and flush TLBs when last slot
3588	{
3589	size_t way = r_dcache_miss_way.read();
3590	size_t set = r_dcache_miss_set.read();
3591
3592	r_dcache_in_tlb[m_dcache_sets*way+set] = false;
3593	r_dcache_contains_ptd[m_dcache_sets*way+set] = false;
3594
3595	#ifdef INSTRUMENTATION
3596	m_cpt_dcache_dir_write++;
3597	#endif
3598	r_dcache.write_dir( way,
3599	set,
3600	CACHE_SLOT_STATE_ZOMBI );
3601
3602	if ( r_dcache_flush_count.read() ==
3603	(m_dcache_sets*m_dcache_ways - 1) ) // last slot
3604	{
3605	r_dtlb.reset();
3606	r_itlb.reset();
3607	r_dcache_fsm = DCACHE_IDLE;
3608	m_drsp.valid = true;
3609	}
3610	else
3611	{
3612	r_dcache_fsm = DCACHE_XTN_DC_FLUSH;
3613	}
3614	break;
3615	}
3616	/////////////////////////
3617	case DCACHE_XTN_DT_INVAL: // handling processor XTN_DTLB_INVAL request
3618	{
3619	r_dtlb.inval(r_dcache_save_wdata.read());
3620	r_dcache_fsm = DCACHE_IDLE;
3621	m_drsp.valid = true;
3622	break;
3623	}
3624	////////////////////////////
3625	case DCACHE_XTN_DC_INVAL_VA: // selective cache line invalidate with virtual address
3626	// requires 3 cycles: access tlb, read cache, inval cache
3627	// we compute the physical address in this state
3628	{
3629	paddr_t paddr;
3630	bool hit;
3631
3632	if ( r_mmu_mode.read() & DATA_TLB_MASK ) // dtlb activated
3633	{
3634
3635	#ifdef INSTRUMENTATION
3636	m_cpt_dtlb_read++;
3637	#endif
3638	hit = r_dtlb.translate( r_dcache_save_wdata.read(),
3639	&paddr );
3640	}
3641	else // dtlb not activated
3642	{
3643	paddr = (paddr_t)r_dcache_save_wdata.read();
3644	hit = true;
3645	}
3646
3647	if ( hit ) // tlb hit
3648	{
3649	r_dcache_save_paddr = paddr;
3650	r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA;
3651	}
3652	else // tlb miss
3653	{
3654
3655	#ifdef INSTRUMENTATION
3656	m_cpt_dtlb_miss++;
3657	#endif
3658	r_dcache_tlb_ins = false; // dtlb
3659	r_dcache_tlb_vaddr = r_dcache_save_wdata.read();
3660	r_dcache_fsm = DCACHE_TLB_MISS;
3661	}
3662
3663	#if DEBUG_DCACHE
3664	if ( m_debug_dcache_fsm )
3665	{
3666	std::cout << " <PROC " << name()
3667	<< " DCACHE_XTN_DC_INVAL_VA> Compute physical address" << std::hex
3668	<< " / VADDR = " << r_dcache_save_wdata.read()
3669	<< " / PADDR = " << paddr << std::endl;
3670	}
3671	#endif
3672
3673	break;
3674	}
3675	////////////////////////////
3676	case DCACHE_XTN_DC_INVAL_PA: // selective cache line invalidate with physical address
3677	// requires 2 cycles: read cache / inval cache
3678	// In this state we read dcache.
3679	{
3680	size_t way;
3681	size_t set;
3682	size_t word;
3683	int state;
3684
3685	#ifdef INSTRUMENTATION
3686	m_cpt_dcache_dir_read++;
3687	#endif
3688	r_dcache.read_dir( r_dcache_save_paddr.read(),
3689	&state,
3690	&way,
3691	&set,
3692	&word );
3693
3694	if ( state == CACHE_SLOT_STATE_VALID ) // inval to be done
3695	{
3696	r_dcache_xtn_way = way;
3697	r_dcache_xtn_set = set;
3698	r_dcache_fsm = DCACHE_XTN_DC_INVAL_GO;
3699	}
3700	else // miss : nothing to do
3701	{
3702	r_dcache_fsm = DCACHE_IDLE;
3703	m_drsp.valid = true;
3704	}
3705
3706	#if DEBUG_DCACHE
3707	if ( m_debug_dcache_fsm )
3708	{
3709	std::cout << " <PROC " << name()
3710	<< " DCACHE_XTN_DC_INVAL_PA> Test hit in dcache" << std::hex
3711	<< " / PADDR = " << r_dcache_save_paddr.read() << std::dec
3712	<< " / HIT = " << (state == CACHE_SLOT_STATE_VALID)
3713	<< " / SET = " << set
3714	<< " / WAY = " << way << std::endl;
3715	}
3716	#endif
3717	break;
3718	}
3719	////////////////////////////
3720	case DCACHE_XTN_DC_INVAL_GO: // In this state, we invalidate the cache line
3721	// Blocked if previous cleanup not completed
3722	// Test if itlb or dtlb inval is required
3723	{
3724	if ( not r_dcache_cc_send_req.read() ) // blocked until previous cc_send request is sent
3725	{
3726	size_t way = r_dcache_xtn_way.read();
3727	size_t set = r_dcache_xtn_set.read();
3728	paddr_t nline = r_dcache_save_paddr.read() / (m_dcache_words<<2);
3729
3730	#ifdef INSTRUMENTATION
3731	m_cpt_dcache_dir_write++;
3732	#endif
3733	r_dcache.write_dir( way,
3734	set,
3735	CACHE_SLOT_STATE_ZOMBI );
3736
3737	// request cleanup
3738	r_dcache_cc_send_req = true;
3739	r_dcache_cc_send_nline = nline;
3740	r_dcache_cc_send_way = way;
3741	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
3742
3743	// possible itlb & dtlb invalidate
3744	if ( r_dcache_in_tlb[way*m_dcache_sets+set] )
3745	{
3746	r_dcache_tlb_inval_line = nline;
3747	r_dcache_tlb_inval_set = 0;
3748	r_dcache_fsm_scan_save = DCACHE_XTN_DC_INVAL_END;
3749	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
3750	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
3751	}
3752	else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] )
3753	{
3754	r_itlb.reset();
3755	r_dtlb.reset();
3756	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
3757	r_dcache_fsm = DCACHE_IDLE;
3758	m_drsp.valid = true;
3759	}
3760	else
3761	{
3762	r_dcache_fsm = DCACHE_IDLE;
3763	m_drsp.valid = true;
3764	}
3765
3766	#if DEBUG_DCACHE
3767	if ( m_debug_dcache_fsm )
3768	{
3769	std::cout << " <PROC " << name()
3770	<< " DCACHE_XTN_DC_INVAL_GO> Actual dcache inval" << std::hex
3771	<< " / PADDR = " << r_dcache_save_paddr.read() << std::endl;
3772	}
3773	#endif
3774	}
3775	break;
3776	}
3777	//////////////////////////////
3778	case DCACHE_XTN_DC_INVAL_END: // send response to processor XTN request
3779	{
3780	r_dcache_fsm = DCACHE_IDLE;
3781	m_drsp.valid = true;
3782	break;
3783	}
3784	////////////////////////
3785	case DCACHE_MISS_SELECT: // Try to select a slot in associative set
3786	// if previous cleanup has been sent.
3787	// Waiting in this state if no slot available
3788	// Set the r_dcache_cleanup_req flip-flop
3789	// and the r_dcache_miss_clack flip-flop
3790	// when a cleanup is required
3791	{
3792	if ( m_dreq.valid) m_cost_data_miss_frz++;
3793
3794	// coherence request (from CC_RECEIVE FSM)
3795	if ( r_cc_receive_dcache_req.read() )
3796	{
3797	r_dcache_fsm = DCACHE_CC_CHECK;
3798	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3799	break;
3800	}
3801
3802	if ( not r_dcache_cc_send_req.read() ) // blocked until previous cc_send request is sent
3803	{
3804	bool found;
3805	bool cleanup;
3806	size_t way;
3807	size_t set;
3808	paddr_t victim;
3809
3810	#ifdef INSTRUMENTATION
3811	m_cpt_dcache_dir_read++;
3812	#endif
3813	r_dcache.read_select( r_dcache_save_paddr.read(),
3814	&victim,
3815	&way,
3816	&set,
3817	&found,
3818	&cleanup );
3819
3820	if ( found )
3821	{
3822	r_dcache_miss_way = way;
3823	r_dcache_miss_set = set;
3824
3825	if ( cleanup )
3826	{
3827	r_dcache_miss_clack = true;
3828	r_dcache_fsm = DCACHE_MISS_CLEAN;
3829	// request cleanup
3830	r_dcache_cc_send_req = true;
3831	r_dcache_cc_send_nline = victim;
3832	r_dcache_cc_send_way = way;
3833	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
3834	}
3835	else
3836	{
3837	r_dcache_fsm = DCACHE_MISS_WAIT;
3838	}
3839
3840	#if DEBUG_DCACHE
3841	if ( m_debug_dcache_fsm )
3842	{
3843	std::cout << " <PROC " << name()
3844	<< " DCACHE_MISS_SELECT> Select a slot:" << std::dec
3845	<< " / WAY = " << way
3846	<< " / SET = " << set
3847	<< " / PADDR = " << std::hex << r_dcache_save_paddr.read();
3848	if(cleanup) std::cout << " / VICTIM = " << std::hex << victim << std::endl;
3849	else std::cout << std::endl;
3850	}
3851	#endif
3852	} // end found
3853	}
3854	break;
3855	}
3856	///////////////////////
3857	case DCACHE_MISS_CLEAN: // switch the slot to ZOMBI state
3858	// and possibly request itlb or dtlb invalidate
3859	{
3860	if ( m_dreq.valid) m_cost_data_miss_frz++;
3861
3862	size_t way = r_dcache_miss_way.read();
3863	size_t set = r_dcache_miss_set.read();
3864	paddr_t nline = r_dcache_save_paddr.read() / (m_dcache_words<<2);
3865
3866	#ifdef INSTRUMENTATION
3867	m_cpt_dcache_dir_read++;
3868	#endif
3869	r_dcache.write_dir( way,
3870	set,
3871	CACHE_SLOT_STATE_ZOMBI );
3872	#if DEBUG_DCACHE
3873	if ( m_debug_dcache_fsm )
3874	{
3875	std::cout << " <PROC " << name()
3876	<< " DCACHE_MISS_CLEAN> Switch to ZOMBI state" << std::dec
3877	<< " / way = " << way
3878	<< " / set = " << set << std::endl;
3879	}
3880	#endif
3881	// if selective itlb & dtlb invalidate are required
3882	// the miss response is not handled before invalidate completed
3883	if ( r_dcache_in_tlb[way*m_dcache_sets+set] )
3884	{
3885	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
3886	r_dcache_tlb_inval_line = nline;
3887	r_dcache_tlb_inval_set = 0;
3888	r_dcache_fsm_scan_save = DCACHE_MISS_WAIT;
3889	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
3890	}
3891	else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] )
3892	{
3893	r_itlb.reset();
3894	r_dtlb.reset();
3895	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
3896	r_dcache_fsm = DCACHE_MISS_WAIT;
3897	}
3898	else
3899	{
3900	r_dcache_fsm = DCACHE_MISS_WAIT;
3901	}
3902	break;
3903	}
3904	//////////////////////
3905	case DCACHE_MISS_WAIT: // waiting the response to a miss request from VCI_RSP FSM
3906	// This state is in charge of error signaling
3907	// There is 5 types of error depending on the requester
3908	{
3909	if ( m_dreq.valid) m_cost_data_miss_frz++;
3910
3911	// coherence request (from CC_RECEIVE FSM)
3912	if ( r_cc_receive_dcache_req.read() )
3913	{
3914	r_dcache_fsm = DCACHE_CC_CHECK;
3915	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3916	break;
3917	}
3918
3919	if ( r_vci_rsp_data_error.read() ) // bus error
3920	{
3921	switch ( r_dcache_miss_type.read() )
3922	{
3923	case PROC_MISS:
3924	{
3925	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
3926	r_mmu_dbvar = r_dcache_save_vaddr.read();
3927	m_drsp.valid = true;
3928	m_drsp.error = true;
3929	r_dcache_fsm = DCACHE_IDLE;
3930	break;
3931	}
3932	case PTE1_MISS:
3933	{
3934	if ( r_dcache_tlb_ins.read() )
3935	{
3936	r_mmu_ietr = MMU_READ_PT1_ILLEGAL_ACCESS;
3937	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3938	r_icache_tlb_miss_req = false;
3939	r_icache_tlb_rsp_error = true;
3940	}
3941	else
3942	{
3943	r_mmu_detr = MMU_READ_PT1_ILLEGAL_ACCESS;
3944	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3945	m_drsp.valid = true;
3946	m_drsp.error = true;
3947	}
3948	r_dcache_fsm = DCACHE_IDLE;
3949	break;
3950	}
3951	case PTE2_MISS:
3952	{
3953	if ( r_dcache_tlb_ins.read() )
3954	{
3955	r_mmu_ietr = MMU_READ_PT2_ILLEGAL_ACCESS;
3956	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3957	r_icache_tlb_miss_req = false;
3958	r_icache_tlb_rsp_error = true;
3959	}
3960	else
3961	{
3962	r_mmu_detr = MMU_READ_PT2_ILLEGAL_ACCESS;
3963	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3964	m_drsp.valid = true;
3965	m_drsp.error = true;
3966	}
3967	r_dcache_fsm = DCACHE_IDLE;
3968	break;
3969	}
3970	} // end switch type
3971	r_vci_rsp_data_error = false;
3972	}
3973	else if ( r_vci_rsp_fifo_dcache.rok() ) // valid response available
3974	{
3975	r_dcache_miss_word = 0;
3976	r_dcache_fsm = DCACHE_MISS_DATA_UPDT;
3977	}
3978	break;
3979	}
3980	//////////////////////////
3981	case DCACHE_MISS_DATA_UPDT: // update the dcache (one word per cycle)
3982	{
3983	if ( m_dreq.valid) m_cost_data_miss_frz++;
3984
3985	if ( r_vci_rsp_fifo_dcache.rok() ) // one word available
3986	{
3987	#ifdef INSTRUMENTATION
3988	m_cpt_dcache_data_write++;
3989	#endif
3990	r_dcache.write( r_dcache_miss_way.read(),
3991	r_dcache_miss_set.read(),
3992	r_dcache_miss_word.read(),
3993	r_vci_rsp_fifo_dcache.read() );
3994	#if DEBUG_DCACHE
3995	if ( m_debug_dcache_fsm )
3996	{
3997	std::cout << " <PROC " << name()
3998	<< " DCACHE_MISS_DATA_UPDT> Write one word:"
3999	<< " / DATA = " << r_vci_rsp_fifo_dcache.read()
4000	<< " / WAY = " << std::dec << r_dcache_miss_way.read()
4001	<< " / SET = " << r_dcache_miss_set.read()
4002	<< " / WORD = " << r_dcache_miss_word.read() << std::endl;
4003	}
4004	#endif
4005	vci_rsp_fifo_dcache_get = true;
4006	r_dcache_miss_word = r_dcache_miss_word.read() + 1;
4007
4008	if ( r_dcache_miss_word.read() == (m_dcache_words-1) ) // last word
4009	{
4010	r_dcache_fsm = DCACHE_MISS_DIR_UPDT;
4011	}
4012	}
4013	break;
4014	}
4015	//////////////////////////
4016	case DCACHE_MISS_DIR_UPDT: // Stalled if a victim line has been evicted
4017	// and the cleanup ack has not been received,
4018	// as indicated by the r_dcache_miss clack.
4019	// - If no matching coherence request (r_dcache_inval_miss)
4020	// switch directory slot to VALID state.
4021	// - If matching coherence request, switch directory slot
4022	// to ZOMBI state, and send a cleanup request.
4023	{
4024	if ( m_dreq.valid) m_cost_data_miss_frz++;
4025
4026	// coherence request (from CC_RECEIVE FSM)
4027	if ( r_cc_receive_dcache_req.read() )
4028	{
4029	r_dcache_fsm = DCACHE_CC_CHECK;
4030	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4031	break;
4032	}
4033
4034	if ( not r_dcache_miss_clack.read() ) // waiting cleanup acknowledge
4035	{
4036	if ( r_dcache_miss_inval.read() ) // switch slot to ZOMBI state, and new cleanup
4037	{
4038	if ( not r_dcache_cc_send_req.read() ) // blocked until previous cc_send request is sent
4039	{
4040	r_dcache_miss_inval = false;
4041	// request cleanup
4042	r_dcache_cc_send_req = true;
4043	r_dcache_cc_send_nline = r_dcache_save_paddr.read()/(m_dcache_words<<2);
4044	r_dcache_cc_send_way = r_dcache_miss_way.read();
4045	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
4046
4047	#ifdef INSTRUMENTATION
4048	m_cpt_dcache_dir_write++;
4049	#endif
4050	r_dcache.write_dir( r_dcache_save_paddr.read(),
4051	r_dcache_miss_way.read(),
4052	r_dcache_miss_set.read(),
4053	CACHE_SLOT_STATE_ZOMBI );
4054	#if DEBUG_DCACHE
4055	if ( m_debug_dcache_fsm )
4056	{
4057	std::cout << " <PROC " << name()
4058	<< " DCACHE_MISS_DIR_UPDT> Switch slot to ZOMBI state"
4059	<< " PADDR = " << std::hex << r_dcache_save_paddr.read()
4060	<< " / WAY = " << std::dec << r_dcache_miss_way.read()
4061	<< " / SET = " << r_dcache_miss_set.read() << std::endl;
4062	}
4063	#endif
4064	}
4065	else
4066	break;
4067	}
4068	else // switch slot to VALID state
4069	{
4070
4071	#ifdef INSTRUMENTATION
4072	m_cpt_dcache_dir_write++;
4073	#endif
4074	r_dcache.write_dir( r_dcache_save_paddr.read(),
4075	r_dcache_miss_way.read(),
4076	r_dcache_miss_set.read(),
4077	CACHE_SLOT_STATE_VALID );
4078
4079	#if DEBUG_DCACHE
4080	if ( m_debug_dcache_fsm )
4081	{
4082	std::cout << " <PROC " << name()
4083	<< " DCACHE_MISS_DIR_UPDT> Switch slot to VALID state"
4084	<< " PADDR = " << std::hex << r_dcache_save_paddr.read()
4085	<< " / WAY = " << std::dec << r_dcache_miss_way.read()
4086	<< " / SET = " << r_dcache_miss_set.read() << std::endl;
4087
4088	r_dcache.printTrace();
4089
4090
4091	}
4092	#endif
4093	// reset directory extension
4094	size_t way = r_dcache_miss_way.read();
4095	size_t set = r_dcache_miss_set.read();
4096	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
4097	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
4098	}
4099	if (r_dcache_miss_type.read()==PTE1_MISS) r_dcache_fsm = DCACHE_TLB_PTE1_GET;
4100	else if (r_dcache_miss_type.read()==PTE2_MISS) r_dcache_fsm = DCACHE_TLB_PTE2_GET;
4101	else r_dcache_fsm = DCACHE_IDLE;
4102	}
4103	break;
4104	}
4105	/////////////////////
4106	case DCACHE_UNC_WAIT: // waiting a response to an uncacheable read
4107	{
4108	// coherence request (from CC_RECEIVE FSM)
4109	if ( r_cc_receive_dcache_req.read() )
4110	{
4111	r_dcache_fsm = DCACHE_CC_CHECK;
4112	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4113	break;
4114	}
4115
4116	if ( r_vci_rsp_data_error.read() ) // bus error
4117	{
4118	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
4119	r_mmu_dbvar = m_dreq.addr;
4120	r_vci_rsp_data_error = false;
4121	m_drsp.error = true;
4122	m_drsp.valid = true;
4123	r_dcache_fsm = DCACHE_IDLE;
4124	break;
4125	}
4126	else if ( r_vci_rsp_fifo_dcache.rok() ) // data available
4127	{
4128	// consume data
4129	vci_rsp_fifo_dcache_get = true;
4130	r_dcache_fsm = DCACHE_IDLE;
4131
4132	// acknowledge the processor request if it has not been modified
4133	if ( m_dreq.valid and (m_dreq.addr == r_dcache_save_vaddr.read()) )
4134	{
4135	m_drsp.valid = true;
4136	m_drsp.error = false;
4137	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
4138	}
4139	}
4140	break;
4141	}
4142	/////////////////////
4143	case DCACHE_LL_WAIT: // waiting VCI response to a LL transaction
4144	{
4145	// coherence request (from CC_RECEIVE FSM)
4146	if ( r_cc_receive_dcache_req.read() )
4147	{
4148	r_dcache_fsm = DCACHE_CC_CHECK;
4149	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4150	break;
4151	}
4152
4153	if ( r_vci_rsp_data_error.read() ) // bus error
4154	{
4155	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
4156	r_mmu_dbvar = m_dreq.addr;
4157	r_vci_rsp_data_error = false;
4158	m_drsp.error = true;
4159	m_drsp.valid = true;
4160	r_dcache_fsm = DCACHE_IDLE;
4161	break;
4162	}
4163	else if ( r_vci_rsp_fifo_dcache.rok() ) // data available
4164	{
4165	// consume data
4166	vci_rsp_fifo_dcache_get = true;
4167
4168	if(r_dcache_ll_rsp_count.read() == 0) // first flit
4169	{
4170	// set key value in llsc reservation buffer
4171	r_dcache_llsc_key = r_vci_rsp_fifo_dcache.read();
4172	r_dcache_ll_rsp_count = r_dcache_ll_rsp_count.read() + 1 ;
4173	}
4174	else // last flit
4175	{
4176	// acknowledge the processor request if it has not been modified
4177	if ( m_dreq.valid and (m_dreq.addr == r_dcache_save_vaddr.read()) )
4178	{
4179	m_drsp.valid = true;
4180	m_drsp.error = false;
4181	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
4182	}
4183	r_dcache_fsm = DCACHE_IDLE;
4184	}
4185	}
4186	break;
4187	}
4188	////////////////////
4189	case DCACHE_SC_WAIT: // waiting VCI response to a SC transaction
4190	{
4191	// coherence request (from CC_RECEIVE FSM)
4192	if ( r_cc_receive_dcache_req.read() )
4193	{
4194	r_dcache_fsm = DCACHE_CC_CHECK;
4195	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4196	break;
4197	}
4198
4199	if ( r_vci_rsp_data_error.read() ) // bus error
4200	{
4201	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
4202	r_mmu_dbvar = m_dreq.addr;
4203	r_vci_rsp_data_error = false;
4204	m_drsp.error = true;
4205	m_drsp.valid = true;
4206	r_dcache_fsm = DCACHE_IDLE;
4207	break;
4208	}
4209	else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
4210	{
4211	// consume response
4212	vci_rsp_fifo_dcache_get = true;
4213	m_drsp.valid = true;
4214	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
4215	r_dcache_fsm = DCACHE_IDLE;
4216	}
4217	break;
4218	}
4219	//////////////////////////
4220	case DCACHE_DIRTY_GET_PTE: // This sub_fsm set the PTE Dirty bit in memory
4221	// before handling a processor WRITE or SC request
4222	// Input argument is r_dcache_dirty_paddr
4223	// In this first state, we get PTE value in dcache
4224	// and post a CAS request to CMD FSM
4225	{
4226	// get PTE in dcache
4227	uint32_t pte;
4228	size_t way;
4229	size_t set;
4230	size_t word; // unused
4231	int state;
4232
4233	#ifdef INSTRUMENTATION
4234	m_cpt_dcache_data_read++;
4235	m_cpt_dcache_dir_read++;
4236	#endif
4237	r_dcache.read( r_dcache_dirty_paddr.read(),
4238	&pte,
4239	&way,
4240	&set,
4241	&word,
4242	&state );
4243
4244	assert( (state == CACHE_SLOT_STATE_VALID) and
4245	"error in DCACHE_DIRTY_TLB_SET: the PTE should be in dcache" );
4246
4247	// request CAS transaction to CMD_FSM
4248	r_dcache_dirty_way = way;
4249	r_dcache_dirty_set = set;
4250
4251	// check llsc reservation buffer
4252	if (r_dcache_llsc_paddr.read() == r_dcache_dirty_paddr.read() )
4253	r_dcache_llsc_valid = false;
4254
4255	// request a CAS CMD and go to DCACHE_DIRTY_WAIT state
4256	r_dcache_vci_cas_req = true;
4257	r_dcache_vci_paddr = r_dcache_dirty_paddr.read();
4258	r_dcache_vci_cas_old = pte;
4259	r_dcache_vci_cas_new = pte \| PTE_D_MASK;
4260	r_dcache_fsm = DCACHE_DIRTY_WAIT;
4261
4262	#if DEBUG_DCACHE
4263	if ( m_debug_dcache_fsm )
4264	{
4265	std::cout << " <PROC " << name()
4266	<< " DCACHE_DIRTY_GET_PTE> CAS request" << std::hex
4267	<< " / PTE_PADDR = " << r_dcache_dirty_paddr.read()
4268	<< " / PTE_VALUE = " << pte << std::dec
4269	<< " / SET = " << set
4270	<< " / WAY = " << way << std::endl;
4271	}
4272	#endif
4273	break;
4274	}
4275	///////////////////////
4276	case DCACHE_DIRTY_WAIT: // wait completion of CAS for PTE Dirty bit,
4277	// and return to IDLE state when response is received.
4278	// we don't care if the CAS is a failure:
4279	// - if the CAS is a success, the coherence mechanism
4280	// updates the local copy.
4281	// - if the CAS is a failure, we just retry the write.
4282	{
4283	// coherence request (from CC_RECEIVE FSM)
4284	if ( r_cc_receive_dcache_req.read() )
4285	{
4286	r_dcache_fsm = DCACHE_CC_CHECK;
4287	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4288	break;
4289	}
4290
4291	if ( r_vci_rsp_data_error.read() ) // bus error
4292	{
4293	std::cout << "BUS ERROR in DCACHE_DIRTY_WAIT state" << std::endl;
4294	std::cout << "This should not happen in this state" << std::endl;
4295	exit(0);
4296	}
4297	else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
4298	{
4299	vci_rsp_fifo_dcache_get = true;
4300	r_dcache_fsm = DCACHE_IDLE;
4301
4302	#if DEBUG_DCACHE
4303	if ( m_debug_dcache_fsm )
4304	{
4305	std::cout << " <PROC " << name()
4306	<< " DCACHE_DIRTY_WAIT> CAS completed" << std::endl;
4307	}
4308	#endif
4309	}
4310	break;
4311	}
4312	/////////////////////
4313	case DCACHE_CC_CHECK: // This state is the entry point for the sub-FSM
4314	// handling coherence requests for DCACHE.
4315	// If there is a matching pending miss on the modified cache
4316	// line this is signaled in the r_dcache_miss inval flip-flop.
4317	// If the updated (or invalidated) cache line has copies in TLBs
4318	// these TLB copies are invalidated.
4319	// The return state is defined in r_dcache_fsm_cc_save
4320	{
4321	paddr_t paddr = r_cc_receive_dcache_nline.read() * m_dcache_words * 4;
4322	paddr_t mask = ~((m_dcache_words<<2)-1);
4323
4324	#if DEBUG_DCACHE
4325	if ( m_debug_dcache_fsm )
4326	{
4327	std::cout << " <PROC " << name()
4328	<< " DCACHE_CC_CHECK> paddr = " << paddr
4329	<< " r_dcache_vci_paddr = " << r_dcache_vci_paddr.read()
4330	<< " mask = " << mask
4331	<< " (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) = " << (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT)
4332	<< " (r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT) = " << (r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT)
4333	<< " ((r_dcache_vci_paddr.read() & mask) == (paddr & mask)) = " << ((r_dcache_vci_paddr.read() & mask) == (paddr & mask))
4334	<<std::endl;
4335	}
4336	#endif
4337
4338	if (r_cc_receive_dcache_type.read() == CC_TYPE_CLACK)
4339	// We switch the directory slot to EMPTY state
4340	// and reset r_icache_miss_clack if the cleanup ack
4341	// is matching a pending miss.
4342	{
4343
4344	if ( m_dreq.valid ) m_cost_data_miss_frz++;
4345
4346	#ifdef INSTRUMENTATION
4347	m_cpt_dcache_dir_write++;
4348	#endif
4349	r_dcache.write_dir( 0,
4350	r_cc_receive_dcache_way.read(),
4351	r_cc_receive_dcache_set.read(),
4352	CACHE_SLOT_STATE_EMPTY);
4353
4354	if ( (r_dcache_miss_set.read() == r_cc_receive_dcache_set.read()) and
4355	(r_dcache_miss_way.read() == r_cc_receive_dcache_way.read()) )
4356	r_dcache_miss_clack = false;
4357
4358	r_dcache_fsm = r_dcache_fsm_cc_save.read() ;
4359	r_cc_receive_dcache_req = false;
4360	#if DEBUG_DCACHE
4361	if ( m_debug_dcache_fsm )
4362	{
4363	std::cout << " <PROC " << name()
4364	<< " DCACHE_CC_CHECK> CC_TYPE_CLACK Switch slot to EMPTY state"
4365	<< " set = " << r_cc_receive_dcache_set.read()
4366	<< " / way = " << r_cc_receive_dcache_way.read() << std::endl;
4367	}
4368	#endif
4369	}
4370	else if( ((r_dcache_fsm_cc_save == DCACHE_MISS_SELECT) or
4371	(r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) or
4372	(r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT)) and
4373	((r_dcache_vci_paddr.read() & mask) == (paddr & mask)) ) // matching
4374	{
4375	// signaling matching
4376	r_dcache_miss_inval = true;
4377
4378	// in case of update, go to CC_UPDT
4379	// JUST TO POP THE FIFO
4380	if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT)
4381	{
4382	r_dcache_fsm = DCACHE_CC_UPDT;
4383	r_dcache_cc_word = r_cc_receive_word_idx.read();
4384	// just pop the fifo , don't write in icache
4385	r_dcache_cc_need_write = false;
4386	}
4387	// the request is dealt with
4388	else
4389	{
4390	r_cc_receive_dcache_req = false;
4391	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4392	}
4393
4394	#if DEBUG_DCACHE
4395	if ( m_debug_dcache_fsm )
4396	{
4397	std::cout << " <PROC " << name()
4398	<< " DCACHE_CC_CHECK> Coherence request matching a pending miss:"
4399	<< " PADDR = " << std::hex << paddr << std::endl;
4400	}
4401	#endif
4402
4403	}
4404	else // no match
4405	{
4406	int state;
4407	size_t way;
4408	size_t set;
4409	size_t word;
4410
4411	#ifdef INSTRUMENTATION
4412	m_cpt_dcache_dir_read++;
4413	#endif
4414	r_dcache.read_dir( paddr,
4415	&state,
4416	&way,
4417	&set,
4418	&word ); // unused
4419
4420	r_dcache_cc_way = way;
4421	r_dcache_cc_set = set;
4422
4423	if ( state == CACHE_SLOT_STATE_VALID) // hit
4424	{
4425	// need to update the cache state
4426	r_dcache_cc_need_write = true;
4427	if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT) // hit update
4428	{
4429	r_dcache_fsm = DCACHE_CC_UPDT;
4430	r_dcache_cc_word = r_cc_receive_word_idx.read();
4431	}
4432	else if (r_cc_receive_dcache_type.read() == CC_TYPE_INVAL) // hit inval
4433	{
4434	r_dcache_fsm = DCACHE_CC_INVAL;
4435	}
4436	else if ( r_cc_receive_dcache_type.read() == CC_TYPE_BRDCAST) // hit broadcast
4437	{
4438	r_dcache_fsm = DCACHE_CC_BROADCAST;
4439	}
4440	}
4441	else // miss
4442	{
4443	// multicast acknowledgement required in case of update
4444	if(r_cc_receive_dcache_type.read() == CC_TYPE_UPDT)
4445	{
4446	r_dcache_fsm = DCACHE_CC_UPDT;
4447	r_dcache_cc_word = r_cc_receive_word_idx.read();
4448	// just pop the fifo , don't write in icache
4449	r_dcache_cc_need_write = false;
4450	}
4451	else // No response needed
4452	{
4453	r_cc_receive_dcache_req = false;
4454	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4455	}
4456	}
4457
4458	#if DEBUG_DCACHE
4459	if ( m_debug_dcache_fsm )
4460	{
4461	std::cout << " <PROC " << name()
4462	<< " DCACHE_CC_CHECK> Coherence request received:"
4463	<< " PADDR = " << std::hex << paddr
4464	<< " / TYPE = " << std::dec << r_cc_receive_dcache_type.read()
4465	<< " / HIT = " << (state == CACHE_SLOT_STATE_VALID) << std::endl;
4466	}
4467	#endif
4468	}
4469	break;
4470	}
4471	/////////////////////
4472	case DCACHE_CC_INVAL: // hit inval: switch slot to EMPTY state,
4473	// after possible invalidation of copies in TLBs
4474	{
4475	size_t way = r_dcache_cc_way.read();
4476	size_t set = r_dcache_cc_set.read();
4477
4478	if (r_dcache_cc_need_write.read())
4479	{
4480	if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // selective TLB inval
4481	{
4482	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
4483	r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read();
4484	r_dcache_tlb_inval_set = 0;
4485	r_dcache_fsm_scan_save = r_dcache_fsm.read();
4486	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4487	break;
4488	}
4489	else
4490	{
4491	if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // TLB flush
4492	{
4493	r_itlb.reset();
4494	r_dtlb.reset();
4495	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
4496
4497	#if DEBUG_DCACHE
4498	if ( m_debug_dcache_fsm )
4499	{
4500	std::cout << " <PROC " << name()
4501	<< " DCACHE_CC_INVAL> Flush DTLB & ITLB" << std::endl;
4502	}
4503	#endif
4504	}
4505
4506	r_dcache.write_dir( 0,
4507	way,
4508	set,
4509	CACHE_SLOT_STATE_EMPTY );
4510
4511	r_dcache_cc_need_write = false;
4512
4513	#if DEBUG_DCACHE
4514	if ( m_debug_dcache_fsm )
4515	{
4516	std::cout << " <PROC " << name()
4517	<< " DCACHE_CC_INVAL> Switch slot to EMPTY state:" << std::dec
4518	<< " / WAY = " << way
4519	<< " / SET = " << set << std::endl;
4520	}
4521	#endif
4522	}
4523	}
4524	// multicast acknowledgement
4525	// send a request to cc_send_fsm
4526	if(not r_dcache_cc_send_req.read()) // cc_send is available
4527	{
4528	// coherence request completed
4529	r_cc_receive_dcache_req = false;
4530	// request multicast acknowledgement
4531	r_dcache_cc_send_req = true;
4532	r_dcache_cc_send_updt_tab_idx = r_cc_receive_dcache_updt_tab_idx.read();
4533	r_dcache_cc_send_type = CC_TYPE_MULTI_ACK;
4534
4535	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4536	}
4537	//else wait for previous cc_send request to be sent
4538	break;
4539	}
4540	///////////////////
4541	case DCACHE_CC_UPDT: // hit update: write one word per cycle,
4542	// after possible invalidation of copies in TLBs
4543	{
4544	size_t word = r_dcache_cc_word.read();
4545	size_t way = r_dcache_cc_way.read();
4546	size_t set = r_dcache_cc_set.read();
4547
4548	if (r_cc_receive_updt_fifo_be.rok())
4549	{
4550	if (r_dcache_cc_need_write.read())
4551	{
4552	if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // selective TLB inval
4553	{
4554	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
4555	r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read();
4556	r_dcache_tlb_inval_set = 0;
4557	r_dcache_fsm_scan_save = r_dcache_fsm.read();
4558	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4559	break;
4560	}
4561
4562	if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // TLB flush
4563	{
4564	r_itlb.reset();
4565	r_dtlb.reset();
4566	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
4567
4568	#if DEBUG_DCACHE
4569	if ( m_debug_dcache_fsm )
4570	{
4571	std::cout << " <PROC " << name()
4572	<< " DCACHE_CC_UPDT> Flush DTLB & ITLB" << std::endl;
4573	}
4574	#endif
4575	}
4576
4577	#ifdef INSTRUMENTATION
4578	m_cpt_dcache_data_write++;
4579	#endif
4580	r_dcache.write( way,
4581	set,
4582	word,
4583	r_cc_receive_updt_fifo_data.read(),
4584	r_cc_receive_updt_fifo_be.read() );
4585
4586	r_dcache_cc_word = word + 1;
4587
4588	#if DEBUG_DCACHE
4589	if ( m_debug_dcache_fsm )
4590	{
4591	std::cout << " <PROC " << name()
4592	<< " DCACHE_CC_UPDT> Write one word" << std::dec
4593	<< " / WAY = " << way
4594	<< " / SET = " << set
4595	<< " / WORD = " << word
4596	<< " / VALUE = " << std::hex << r_cc_receive_updt_fifo_data.read() << std::endl;
4597	}
4598	#endif
4599	}
4600
4601	if ( r_cc_receive_updt_fifo_eop.read() ) // last word
4602	{
4603	// no need to write in the cache anymore
4604	r_dcache_cc_need_write = false;
4605
4606	// wait to send a request to cc_send_fsm
4607	if(not r_icache_cc_send_req.read())
4608	// cc_send is available
4609	{
4610	//consume last fifo flit if eop and request to cc_send possible
4611	cc_receive_updt_fifo_get = true;
4612
4613	// coherence request completed
4614	r_cc_receive_dcache_req = false;
4615
4616	// request multicast acknowledgement
4617	r_dcache_cc_send_req = true;
4618	r_dcache_cc_send_updt_tab_idx = r_cc_receive_dcache_updt_tab_idx.read();
4619	r_dcache_cc_send_type = CC_TYPE_MULTI_ACK;
4620
4621	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4622	}
4623	}
4624	else
4625	{
4626	//consume fifo if not eop
4627	cc_receive_updt_fifo_get = true;
4628	}
4629	}
4630	break;
4631	}
4632	/////////////////////////
4633	case DCACHE_CC_BROADCAST: // hit broadcast : switch state to ZOMBI state
4634	// and request a cleanup, after possible
4635	// invalidation of copies in TLBs
4636	{
4637	size_t way = r_dcache_cc_way.read();
4638	size_t set = r_dcache_cc_set.read();
4639	paddr_t nline = r_cc_receive_dcache_nline.read();
4640
4641	if (r_dcache_cc_need_write.read())
4642	{
4643	if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // selective TLB inval
4644	{
4645	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
4646	r_dcache_tlb_inval_line = nline;
4647	r_dcache_tlb_inval_set = 0;
4648	r_dcache_fsm_scan_save = r_dcache_fsm.read();
4649	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4650	break;
4651	}
4652	else
4653	{
4654	if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // TLB flush
4655	{
4656	r_itlb.reset();
4657	r_dtlb.reset();
4658	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
4659
4660	#if DEBUG_DCACHE
4661	if ( m_debug_dcache_fsm )
4662	{
4663	std::cout << " <PROC " << name()
4664	<< " DCACHE_CC_BROADCAST> Flush DTLB & ITLB" << std::endl;
4665	}
4666	#endif
4667	}
4668
4669	#ifdef INSTRUMENTATION
4670	m_cpt_dcache_dir_write++;
4671	#endif
4672	r_dcache.write_dir( way,
4673	set,
4674	CACHE_SLOT_STATE_ZOMBI );
4675
4676	r_dcache_cc_need_write = false;
4677	#if DEBUG_DCACHE
4678	if ( m_debug_dcache_fsm )
4679	{
4680	std::cout << " <PROC " << name()
4681	<< " DCACHE_CC_BROADCAST > Slot goes to ZOMBI state "
4682	<< " SET = " << set
4683	<< " / WAY = " << way << std::endl;
4684	}
4685	#endif
4686	}
4687	}
4688	// cleanup
4689	// send a request to cc_send_fsm
4690	if(not r_dcache_cc_send_req.read()) // cc_send is available
4691	{
4692	// coherence request completed
4693	r_cc_receive_dcache_req = false;
4694	// request cleanup
4695	r_dcache_cc_send_req = true;
4696	r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read();
4697	r_dcache_cc_send_way = r_dcache_cc_way.read();
4698	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
4699
4700	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4701	}
4702	//else wait for previous cc_send request to be sent
4703	break;
4704	}
4705	///////////////////////////
4706	case DCACHE_INVAL_TLB_SCAN: // Scan sequencially all sets for both ITLB & DTLB
4707	// It makes assumption: m_itlb_sets == m_dtlb_sets
4708	// All ways are handled in parallel.
4709	// We enter this state when a DCACHE line is modified,
4710	// and there is a copy in itlb or dtlb.
4711	// It can be caused by:
4712	// - a coherence inval or updt transaction,
4713	// - a line inval caused by a cache miss
4714	// - a processor XTN inval request,
4715	// - a WRITE hit,
4716	// - a Dirty bit update
4717	// Input arguments are:
4718	// - r_dcache_tlb_inval_line
4719	// - r_dcache_tlb_inval_set
4720	// - r_dcache_fsm_scan_save
4721	{
4722	paddr_t line = r_dcache_tlb_inval_line.read();
4723	size_t set = r_dcache_tlb_inval_set.read();
4724	size_t way;
4725	bool ok;
4726
4727	for ( way = 0 ; way < m_itlb_ways ; way++ )
4728	{
4729	ok = r_itlb.inval( line, way, set );
4730
4731	#if DEBUG_DCACHE
4732	if ( m_debug_dcache_fsm and ok )
4733	{
4734	std::cout << " <PROC " << name()
4735	<< ".DCACHE_INVAL_TLB_SCAN> Invalidate ITLB entry:" << std::hex
4736	<< " line = " << line << std::dec
4737	<< " / set = " << set
4738	<< " / way = " << way << std::endl;
4739	}
4740	#endif
4741	}
4742
4743	for ( way = 0 ; way < m_dtlb_ways ; way++ )
4744	{
4745	ok = r_dtlb.inval( line, way, set );
4746
4747	#if DEBUG_DCACHE
4748	if ( m_debug_dcache_fsm and ok )
4749	{
4750	std::cout << " <PROC " << name()
4751	<< ".DCACHE_INVAL_TLB_SCAN> Invalidate DTLB entry:" << std::hex
4752	<< " line = " << line << std::dec
4753	<< " / set = " << set
4754	<< " / way = " << way << std::endl;
4755	}
4756	#endif
4757	}
4758
4759	// return to the calling state when TLB inval completed
4760	if ( r_dcache_tlb_inval_set.read() == (m_dtlb_sets-1) )
4761	{
4762	r_dcache_fsm = r_dcache_fsm_scan_save.read();
4763	}
4764	r_dcache_tlb_inval_set = r_dcache_tlb_inval_set.read() + 1;
4765	break;
4766	}
4767	} // end switch r_dcache_fsm
4768
4769	///////////////// wbuf update ///////////////////////////////////////////////////////
4770	r_wbuf.update();
4771
4772	///////////////// llsc update ///////////////////////////////////////////////////////
4773	if (r_dcache_llsc_valid.read()) r_dcache_llsc_count = r_dcache_llsc_count.read() - 1;
4774	if (r_dcache_llsc_count.read() == 1) r_dcache_llsc_valid = false;
4775
4776	//////////////// test processor frozen //////////////////////////////////////////////
4777	// The simulation exit if the number of consecutive frozen cycles
4778	// is larger than the m_max_frozen_cycles (constructor parameter)
4779	if ( (m_ireq.valid and not m_irsp.valid) or (m_dreq.valid and not m_drsp.valid) )
4780	{
4781	m_cpt_frz_cycles++; // used for instrumentation
4782	m_cpt_stop_simulation++; // used for debug
4783	if ( m_cpt_stop_simulation > m_max_frozen_cycles )
4784	{
4785	std::cout << std::dec << "ERROR in CC_VCACHE_WRAPPER " << name() << std::endl
4786	<< " stop at cycle " << m_cpt_total_cycles << std::endl
4787	<< " frozen since cycle " << m_cpt_total_cycles - m_max_frozen_cycles
4788	<< std::endl;
4789	r_iss.dump();
4790	exit(1);
4791	}
4792	}
4793	else
4794	{
4795	m_cpt_stop_simulation = 0;
4796	}
4797
4798	/////////// execute one iss cycle /////////////////////////////////
4799	{
4800	uint32_t it = 0;
4801	for (size_t i=0; i<(size_t)iss_t::n_irq; i++) if(p_irq[i].read()) it \|= (1<<i);
4802	r_iss.executeNCycles(1, m_irsp, m_drsp, it);
4803	}
4804
4805	////////////////////////////////////////////////////////////////////////////
4806	// The VCI_CMD FSM controls the following ressources:
4807	// - r_vci_cmd_fsm
4808	// - r_vci_cmd_min
4809	// - r_vci_cmd_max
4810	// - r_vci_cmd_cpt
4811	// - r_vci_cmd_imiss_prio
4812	// - wbuf (reset)
4813	// - r_icache_miss_req (reset)
4814	// - r_icache_unc_req (reset)
4815	// - r_dcache_vci_miss_req (reset)
4816	// - r_dcache_vci_unc_req (reset)
4817	// - r_dcache_vci_ll_req (reset)
4818	// - r_dcache_vci_sc_req (reset in case of local sc fail)
4819	// - r_dcache_vci_cas_req (reset)
4820	//
4821	// This FSM handles requests from both the DCACHE FSM & the ICACHE FSM.
4822	// There are 8 request types, with the following priorities :
4823	// 1 - Data Read Miss : r_dcache_vci_miss_req and miss in the write buffer
4824	// 2 - Data Read Uncachable : r_dcache_vci_unc_req
4825	// 3 - Instruction Miss : r_icache_miss_req and miss in the write buffer
4826	// 4 - Instruction Uncachable : r_icache_unc_req
4827	// 5 - Data Write : r_wbuf.rok()
4828	// 6 - Data Linked Load : r_dcache_vci_ll_req
4829	// 7 - Data Store Conditionnal: r_dcache_vci_sc_req
4830	// 8 - Compare And Swap : r_dcache_vci_cas_req
4831	//
4832	// As we want to support several simultaneous VCI transactions, the VCI_CMD_FSM
4833	// and the VCI_RSP_FSM are fully desynchronized.
4834	//
4835	// VCI formats:
4836	// According to the VCI advanced specification, all read requests packets
4837	// (data Uncached, Miss data, instruction Uncached, Miss instruction)
4838	// are one word packets.
4839	// For write burst packets, all words are in the same cache line,
4840	// and addresses must be contiguous (the BE field is 0 in case of "holes").
4841	// The sc command packet implements actually a compare-and-swap mechanism
4842	// and the packet contains two flits.
4843	////////////////////////////////////////////////////////////////////////////////////
4844
4845	switch ( r_vci_cmd_fsm.read() )
4846	{
4847	//////////////
4848	case CMD_IDLE:
4849	{
4850	// DDACHE read requests (r_dcache_vci_miss_req or r_dcache_vci_ll_req), and
4851	// ICACHE read requests (r_icache_miss_req) require both a write_buffer access
4852	// to check a possible pending write on the same cache line.
4853	// As there is only one possible access per cycle to write buffer, we implement
4854	// a round-robin priority between DCACHE and ICACHE for this access,
4855	// using the r_vci_cmd_imiss_prio flip-flop.
4856
4857	size_t wbuf_min;
4858	size_t wbuf_max;
4859
4860	bool dcache_unc_req = r_dcache_vci_unc_req.read() and
4861	( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() );
4862
4863	bool dcache_miss_req = r_dcache_vci_miss_req.read() and
4864	( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() );
4865
4866	bool dcache_ll_req = r_dcache_vci_ll_req.read() and
4867	( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() );
4868
4869	bool icache_miss_req = r_icache_miss_req.read() and
4870	( not (r_dcache_vci_miss_req.read() or
4871	r_dcache_vci_ll_req.read() or
4872	r_dcache_vci_unc_req.read())
4873	or r_vci_cmd_imiss_prio.read() );
4874
4875
4876	// 1 - Data Read Miss
4877	if ( dcache_miss_req and r_wbuf.miss(r_dcache_vci_paddr.read()) )
4878	{
4879	r_vci_cmd_fsm = CMD_DATA_MISS;
4880	r_dcache_vci_miss_req = false;
4881	r_vci_cmd_imiss_prio = true;
4882	// m_cpt_dmiss_transaction++;
4883	}
4884	// 2 - Data Read Uncachable
4885	else if ( dcache_unc_req and r_wbuf.miss(r_dcache_vci_paddr.read()))
4886	{
4887	r_vci_cmd_fsm = CMD_DATA_UNC;
4888	r_dcache_vci_unc_req = false;
4889	// m_cpt_dunc_transaction++;
4890	}
4891	// 3 - Data Linked Load
4892	else if ( dcache_ll_req and r_wbuf.miss(r_dcache_vci_paddr.read()))
4893	{
4894	r_dcache_vci_ll_req = false;
4895	r_vci_cmd_fsm = CMD_DATA_LL;
4896	// m_cpt_ll_transaction++;
4897	}
4898	// 4 - Instruction Miss
4899	else if ( icache_miss_req and r_wbuf.miss(r_icache_vci_paddr.read()) )
4900	{
4901	r_vci_cmd_fsm = CMD_INS_MISS;
4902	r_icache_miss_req = false;
4903	r_vci_cmd_imiss_prio = false;
4904	// m_cpt_imiss_transaction++;
4905	}
4906	// 5 - Instruction Uncachable
4907	else if ( r_icache_unc_req.read() )
4908	{
4909	r_vci_cmd_fsm = CMD_INS_UNC;
4910	r_icache_unc_req = false;
4911	// m_cpt_iunc_transaction++;
4912	}
4913	// 6 - Data Write
4914	else if ( r_wbuf.rok(&wbuf_min, &wbuf_max) )
4915	{
4916	r_vci_cmd_fsm = CMD_DATA_WRITE;
4917	r_vci_cmd_cpt = wbuf_min;
4918	r_vci_cmd_min = wbuf_min;
4919	r_vci_cmd_max = wbuf_max;
4920	// m_cpt_write_transaction++;
4921	// m_length_write_transaction += (wbuf_max-wbuf_min+1);
4922	}
4923	// 7 - Data Store Conditionnal
4924	else if ( r_dcache_vci_sc_req.read() )
4925	{
4926	r_dcache_vci_sc_req = false;
4927	r_vci_cmd_cpt = 0;
4928	r_vci_cmd_fsm = CMD_DATA_SC;
4929	// m_cpt_sc_transaction++;
4930	}
4931	// 8 - Compare And Swap
4932	else if ( r_dcache_vci_cas_req.read() )
4933	{
4934	r_vci_cmd_fsm = CMD_DATA_CAS;
4935	r_dcache_vci_cas_req = false;
4936	r_vci_cmd_cpt = 0;
4937	// m_cpt_cas_transaction++;
4938	}
4939	break;
4940	}
4941	////////////////////
4942	case CMD_DATA_WRITE:
4943	{
4944	if ( p_vci.cmdack.read() )
4945	{
4946	r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
4947	if (r_vci_cmd_cpt == r_vci_cmd_max) // last flit sent
4948	{
4949	r_vci_cmd_fsm = CMD_IDLE ;
4950	r_wbuf.sent() ;
4951	}
4952	}
4953	break;
4954	}
4955	/////////////////
4956	case CMD_DATA_SC:
4957	case CMD_DATA_CAS:
4958	{
4959	// The CAS and SC VCI commands contain two flits
4960	if ( p_vci.cmdack.read() )
4961	{
4962	r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
4963	if (r_vci_cmd_cpt == 1) r_vci_cmd_fsm = CMD_IDLE ;
4964	}
4965	break;
4966	}
4967	//////////////////
4968	case CMD_INS_MISS:
4969	case CMD_INS_UNC:
4970	case CMD_DATA_MISS:
4971	case CMD_DATA_UNC:
4972	case CMD_DATA_LL:
4973	{
4974	// all read VCI commands contain one single flit
4975	if ( p_vci.cmdack.read() ) r_vci_cmd_fsm = CMD_IDLE;
4976	break;
4977	}
4978
4979	} // end switch r_vci_cmd_fsm
4980
4981	//////////////////////////////////////////////////////////////////////////
4982	// The VCI_RSP FSM controls the following ressources:
4983	// - r_vci_rsp_fsm:
4984	// - r_vci_rsp_fifo_icache (push)
4985	// - r_vci_rsp_fifo_dcache (push)
4986	// - r_vci_rsp_data_error (set)
4987	// - r_vci_rsp_ins_error (set)
4988	// - r_vci_rsp_cpt
4989	// - r_dcache_vci_sc_req (reset when SC response recieved)
4990	//
4991	// As the VCI_RSP and VCI_CMD are fully desynchronized to support several
4992	// simultaneous VCI transactions, this FSM uses the VCI RPKTID field
4993	// to identify the transactions.
4994	//
4995	// VCI vormat:
4996	// This component checks the response packet length and accepts only
4997	// single word packets for write response packets.
4998	//
4999	// Error handling:
5000	// This FSM analyzes the VCI error code and signals directly the Write Bus Error.
5001	// In case of Read Data Error, the VCI_RSP FSM sets the r_vci_rsp_data_error
5002	// flip_flop and the error is signaled by the DCACHE FSM.
5003	// In case of Instruction Error, the VCI_RSP FSM sets the r_vci_rsp_ins_error
5004	// flip_flop and the error is signaled by the ICACHE FSM.
5005	// In case of Cleanup Error, the simulation stops with an error message...
5006	//////////////////////////////////////////////////////////////////////////
5007
5008	switch ( r_vci_rsp_fsm.read() )
5009	{
5010	//////////////
5011	case RSP_IDLE:
5012	{
5013	if ( p_vci.rspval.read() )
5014	{
5015	r_vci_rsp_cpt = 0;
5016
5017	if ( (p_vci.rpktid.read() & 0x7) == TYPE_READ_DATA_UNC )
5018	{
5019	r_vci_rsp_fsm = RSP_DATA_UNC;
5020	}
5021	else if ( (p_vci.rpktid.read() & 0x7) == TYPE_READ_DATA_MISS )
5022	{
5023	r_vci_rsp_fsm = RSP_DATA_MISS;
5024	}
5025	else if ( (p_vci.rpktid.read() & 0x7) == TYPE_READ_INS_UNC )
5026	{
5027	r_vci_rsp_fsm = RSP_INS_UNC;
5028	}
5029	else if ( (p_vci.rpktid.read() & 0x7) == TYPE_READ_INS_MISS )
5030	{
5031	r_vci_rsp_fsm = RSP_INS_MISS;
5032	}
5033	else if ( (p_vci.rpktid.read() & 0x7) == TYPE_WRITE )
5034	{
5035	r_vci_rsp_fsm = RSP_DATA_WRITE;
5036	}
5037	else if ( (p_vci.rpktid.read() & 0x7) == TYPE_CAS )
5038	{
5039	r_vci_rsp_fsm = RSP_DATA_UNC;
5040	}
5041	else if ( (p_vci.rpktid.read() & 0x7) == TYPE_LL )
5042	{
5043	r_vci_rsp_fsm = RSP_DATA_LL;
5044	}
5045	else if ( (p_vci.rpktid.read() & 0x7) == TYPE_SC )
5046	{
5047	r_vci_rsp_fsm = RSP_DATA_UNC;
5048	}
5049	else
5050	{
5051	assert(false and "Unexpected VCI response");
5052	}
5053	}
5054	break;
5055	}
5056	//////////////////
5057	case RSP_INS_MISS:
5058	{
5059	if ( p_vci.rspval.read() )
5060	{
5061	if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported
5062	{
5063	r_vci_rsp_ins_error = true;
5064	if ( p_vci.reop.read() ) r_vci_rsp_fsm = RSP_IDLE;
5065	}
5066	else // no error reported
5067	{
5068	if ( r_vci_rsp_fifo_icache.wok() )
5069	{
5070	assert( (r_vci_rsp_cpt.read() < m_icache_words) and
5071	"The VCI response packet for instruction miss is too long" );
5072
5073	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
5074	vci_rsp_fifo_icache_put = true,
5075	vci_rsp_fifo_icache_data = p_vci.rdata.read();
5076	if ( p_vci.reop.read() )
5077	{
5078	assert( (r_vci_rsp_cpt.read() == m_icache_words - 1) and
5079	"The VCI response packet for instruction miss is too short");
5080
5081	r_vci_rsp_fsm = RSP_IDLE;
5082	}
5083	}
5084	}
5085	}
5086	break;
5087	}
5088	/////////////////
5089	case RSP_INS_UNC:
5090	{
5091	if (p_vci.rspval.read() )
5092	{
5093	assert( p_vci.reop.read() and
5094	"illegal VCI response packet for uncachable instruction");
5095
5096	if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported
5097	{
5098	r_vci_rsp_ins_error = true;
5099	r_vci_rsp_fsm = RSP_IDLE;
5100	}
5101	else // no error reported
5102	{
5103	if ( r_vci_rsp_fifo_icache.wok())
5104	{
5105	vci_rsp_fifo_icache_put = true;
5106	vci_rsp_fifo_icache_data = p_vci.rdata.read();
5107	r_vci_rsp_fsm = RSP_IDLE;
5108	}
5109	}
5110	}
5111	break;
5112	}
5113	///////////////////
5114	case RSP_DATA_MISS:
5115	{
5116	if ( p_vci.rspval.read() )
5117	{
5118	if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported
5119	{
5120	r_vci_rsp_data_error = true;
5121	if ( p_vci.reop.read() ) r_vci_rsp_fsm = RSP_IDLE;
5122	}
5123	else // no error reported
5124	{
5125	if ( r_vci_rsp_fifo_dcache.wok() )
5126	{
5127	assert( (r_vci_rsp_cpt.read() < m_dcache_words) and
5128	"The VCI response packet for data miss is too long");
5129
5130	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
5131	vci_rsp_fifo_dcache_put = true,
5132	vci_rsp_fifo_dcache_data = p_vci.rdata.read();
5133	if ( p_vci.reop.read() )
5134	{
5135	assert( (r_vci_rsp_cpt.read() == m_dcache_words - 1) and
5136	"The VCI response packet for data miss is too short");
5137
5138	r_vci_rsp_fsm = RSP_IDLE;
5139	}
5140	}
5141	}
5142	}
5143	break;
5144	}
5145	//////////////////
5146	case RSP_DATA_UNC:
5147	{
5148	if (p_vci.rspval.read() )
5149	{
5150	assert( p_vci.reop.read() and
5151	"illegal VCI response packet for uncachable read data");
5152
5153	if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported
5154	{
5155	r_vci_rsp_data_error = true;
5156	r_vci_rsp_fsm = RSP_IDLE;
5157	}
5158	else // no error reported
5159	{
5160	if ( r_vci_rsp_fifo_dcache.wok())
5161	{
5162	vci_rsp_fifo_dcache_put = true;
5163	vci_rsp_fifo_dcache_data = p_vci.rdata.read();
5164	r_vci_rsp_fsm = RSP_IDLE;
5165	}
5166	}
5167	}
5168	break;
5169	}
5170	////////////////////
5171	case RSP_DATA_LL:
5172	{
5173	if ( p_vci.rspval.read() )
5174	{
5175	if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported
5176	{
5177	r_vci_rsp_data_error = true;
5178	r_vci_rsp_fsm = RSP_IDLE;
5179	}
5180	if (r_vci_rsp_cpt.read() == 0) //first flit
5181	{
5182	if(r_vci_rsp_fifo_dcache.wok())
5183	{
5184	assert(!p_vci.reop.read() &&
5185	"illegal VCI response packet for LL");
5186	vci_rsp_fifo_dcache_put = true;
5187	vci_rsp_fifo_dcache_data = p_vci.rdata.read();
5188	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
5189	}
5190	break;
5191	}
5192	else // last flit
5193	{
5194	if(r_vci_rsp_fifo_dcache.wok())
5195	{
5196	assert(p_vci.reop.read() &&
5197	"illegal VCI response packet for LL");
5198	vci_rsp_fifo_dcache_put = true;
5199	vci_rsp_fifo_dcache_data = p_vci.rdata.read();
5200	r_vci_rsp_fsm = RSP_IDLE;
5201	}
5202	break;
5203	}
5204	}
5205	break;
5206	}
5207	////////////////////
5208	case RSP_DATA_WRITE:
5209	{
5210	if (p_vci.rspval.read())
5211	{
5212	assert( p_vci.reop.read() and
5213	"a VCI response packet must contain one flit for a write transaction");
5214
5215	r_vci_rsp_fsm = RSP_IDLE;
5216	uint32_t wbuf_index = p_vci.rtrdid.read();
5217	bool cacheable = r_wbuf.completed(wbuf_index);
5218	if ( not cacheable ) r_dcache_pending_unc_write = false;
5219	if ( (p_vci.rerror.read()&0x1) != 0 ) r_iss.setWriteBerr();
5220	}
5221	break;
5222	}
5223	} // end switch r_vci_rsp_fsm
5224
5225	/////////////////////////////////////////////////////////////////////////////////////
5226	// The CC_SEND FSM is in charge of sending cleanups and the multicast
5227	// acknowledgements on the coherence network. It has two clients (DCACHE FSM
5228	// and ICACHE FSM) that are served with a round-robin priority.
5229	// The CC_SEND FSM resets the r_*cache_cc_send_req request flip-flops as
5230	// soon as the request has been sent.
5231	/////////////////////////////////////////////////////////////////////////////////////
5232	switch ( r_cc_send_fsm.read() )
5233	{
5234	///////////////////////////
5235	case CC_SEND_IDLE:
5236	{
5237	///////////////////////////////////////////////////////
5238	// handling round robin between icache and dcache : //
5239	// we first check for the last client and listen for //
5240	// a request of the other, then update the client //
5241	///////////////////////////////////////////////////////
5242	// r_cc_send_last_client : 0 dcache / 1 icache
5243	bool update_last_client = r_cc_send_last_client.read();
5244	if ( r_cc_send_last_client.read() == 0 ) // last client was dcache
5245	{
5246	if (r_icache_cc_send_req.read()) // request from icache
5247	update_last_client = 1; // update last client to icache
5248	}
5249	else // last client was icache
5250	{
5251	if (r_dcache_cc_send_req.read()) // request from dcache
5252	update_last_client = 0; // update last client to dcache
5253	}
5254	r_cc_send_last_client = update_last_client;
5255
5256	// if there is an actual request
5257	if (r_dcache_cc_send_req.read() or r_icache_cc_send_req.read())
5258	{
5259	// test if the new client is dcache and has a cleanup request
5260	if ( (update_last_client == 0) and (r_dcache_cc_send_type.read() == CC_TYPE_CLEANUP))
5261	r_cc_send_fsm = CC_SEND_CLEANUP_1;
5262	// test if the new client is dcache and has a multi acknowledgement request
5263	else if ( (update_last_client == 0) and (r_dcache_cc_send_type.read() == CC_TYPE_MULTI_ACK))
5264	r_cc_send_fsm = CC_SEND_MULTI_ACK;
5265	// test if the new client is icache and has a cleanup request
5266	else if ( (update_last_client == 1) and (r_icache_cc_send_type.read() == CC_TYPE_CLEANUP))
5267	r_cc_send_fsm = CC_SEND_CLEANUP_1;
5268	// test if the new client is icache and has a multi acknowledgement request
5269	else if ( (update_last_client == 1) and (r_icache_cc_send_type.read() == CC_TYPE_MULTI_ACK))
5270	r_cc_send_fsm = CC_SEND_MULTI_ACK;
5271	}
5272	break;
5273	}
5274	///////////////////////////
5275	case CC_SEND_CLEANUP_1:
5276	{
5277	// wait for the first flit to be consumed
5278	if (p_dspin_out.read.read())
5279	r_cc_send_fsm = CC_SEND_CLEANUP_2;
5280
5281	break;
5282	}
5283	///////////////////////////
5284	case CC_SEND_CLEANUP_2:
5285	{
5286	// wait for the second flit to be consumed
5287	if (p_dspin_out.read.read())
5288	{
5289	if (r_cc_send_last_client.read() == 0) // dcache active request
5290	r_dcache_cc_send_req = false; // reset dcache request
5291	else // icache active request
5292	r_icache_cc_send_req = false; // reset icache request
5293
5294	// go back to idle state
5295	r_cc_send_fsm = CC_SEND_IDLE;
5296	}
5297	break;
5298	}
5299	///////////////////////////
5300	case CC_SEND_MULTI_ACK:
5301	{
5302	// wait for the flit to be consumed
5303	if(p_dspin_out.read.read())
5304	{
5305	if(r_cc_send_last_client.read() == 0) // dcache active request
5306	r_dcache_cc_send_req = false; // reset dcache request
5307	else // icache active request
5308	r_icache_cc_send_req = false; // reset icache request
5309	// go back to idle state
5310	r_cc_send_fsm = CC_SEND_IDLE;
5311	}
5312	break;
5313	}
5314	} // end switch CC_SEND FSM
5315
5316	///////////////////////////////////////////////////////////////////////////////
5317	// C_RECEIVE FSM
5318	// This FSM receive all coherence packets on a DSPIN40 port.
5319	// There is 4 packet types:
5320	// - CC_DATA_INVAL : DCACHE invalidate request
5321	// - CC_DATA_UPDT : DCACHE update request (multi-words)
5322	// - CC_INST_INVAL : ICACHE invalidate request
5323	// - CC_INST_UPDT : ICACHE update request (multi-words)
5324	// - CC_BROADCAST : Broadcast invalidate request (both DCACHE & ICACHE)
5325	// - CC_DATA_CLACK : DCACHE cleanup acknowledge
5326	// - CC_INST_CLACK : ICACHE cleanup acknowledge
5327	//////////////////////////////////////////////////////////////////////////////
5328	switch( r_cc_receive_fsm.read() )
5329	{
5330	/////////////////////
5331	case CC_RECEIVE_IDLE:
5332	{
5333	// a coherence request has arrived
5334	if (p_dspin_in.write.read())
5335	{
5336	// initialize dspin received data
5337	uint64_t receive_data = p_dspin_in.data.read();
5338	// initialize coherence packet type
5339	uint64_t receive_type = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::FROM_MC_TYPE);
5340	// initialize data/ins flip_flop (0 data / 1 ins)
5341	r_cc_receive_data_ins = (bool)(receive_type & 0x1);
5342	// test for a broadcast
5343	if (DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::FROM_MC_BC))
5344	{
5345	r_cc_receive_fsm = CC_RECEIVE_BRDCAST_HEADER;
5346	}
5347	// test for a CLACK
5348	else if ((receive_type == DspinDhccpParam::TYPE_CLEANUP_ACK_DATA) or
5349	(receive_type == DspinDhccpParam::TYPE_CLEANUP_ACK_INST))
5350	{
5351	r_cc_receive_fsm = CC_RECEIVE_CLACK;
5352	}
5353	// test for a multi updt
5354	else if ((receive_type == DspinDhccpParam::TYPE_MULTI_UPDT_DATA) or
5355	(receive_type == DspinDhccpParam::TYPE_MULTI_UPDT_INST))
5356	{
5357	r_cc_receive_fsm = CC_RECEIVE_UPDT_HEADER;
5358	}
5359	// test for a multi inval
5360	else
5361	{
5362	r_cc_receive_fsm = CC_RECEIVE_INVAL_HEADER;
5363	}
5364	}
5365	break;
5366	}
5367	//////////////////////
5368	case CC_RECEIVE_CLACK:
5369	{
5370	// initialize dspin received data
5371	uint64_t receive_data = p_dspin_in.data.read();
5372
5373	// for data CLACK, wait for dcache to take the request
5374	if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()))
5375	{
5376	// request dcache to handle the CLACK
5377	r_cc_receive_dcache_req = true;
5378	r_cc_receive_dcache_set = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::CLEANUP_ACK_SET) & ((1ULL<<(uint32_log2(m_dcache_sets)))-1);
5379	r_cc_receive_dcache_way = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::CLEANUP_ACK_WAY) & ((1ULL<<(uint32_log2(m_dcache_ways)))-1);
5380	r_cc_receive_dcache_type = CC_TYPE_CLACK;
5381	// get back to idle state
5382	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5383	break;
5384	}
5385	// for ins CLACK, wait for icache to take the request
5386	if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()))
5387	{
5388	// request icache to handle the CLACK
5389	r_cc_receive_icache_req = true;
5390	r_cc_receive_icache_set = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::CLEANUP_ACK_SET) & ((1ULL<<(uint32_log2(m_icache_sets)))-1);
5391	r_cc_receive_icache_way = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::CLEANUP_ACK_WAY) & ((1ULL<<(uint32_log2(m_icache_ways)))-1);
5392	r_cc_receive_icache_type = CC_TYPE_CLACK;
5393	// get back to idle state
5394	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5395	break;
5396	}
5397	// keep waiting for the correct cache to accept the request
5398	break;
5399	}
5400	///////////////////////////////
5401	case CC_RECEIVE_BRDCAST_HEADER:
5402	{
5403	// no actual data in the HEADER, just skip to second flit
5404	r_cc_receive_fsm = CC_RECEIVE_BRDCAST_NLINE;
5405	break;
5406	}
5407	//////////////////////////////
5408	case CC_RECEIVE_BRDCAST_NLINE:
5409	{
5410	// initialize dspin received data
5411	uint64_t receive_data = p_dspin_in.data.read();
5412	// wait for both dcache and icache to take the request
5413	// TODO maybe we need to wait for both only to leave the state, but
5414	// not to actually post a request to an available cache => need a
5415	// flip_flop to check that ?
5416	if (not (r_cc_receive_icache_req.read()) and not (r_cc_receive_dcache_req.read()) and (p_dspin_in.write.read()))
5417	{
5418	// request dcache to handle the BROADCAST
5419	r_cc_receive_dcache_req = true;
5420	r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::BROADCAST_NLINE);
5421	r_cc_receive_dcache_type = CC_TYPE_BRDCAST;
5422	// request icache to handle the BROADCAST
5423	r_cc_receive_icache_req = true;
5424	r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::BROADCAST_NLINE);
5425	r_cc_receive_icache_type = CC_TYPE_BRDCAST;
5426	// get back to idle state
5427	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5428	break;
5429	}
5430	// keep waiting for the caches to accept the request
5431	break;
5432	}
5433	/////////////////////////////
5434	case CC_RECEIVE_INVAL_HEADER:
5435	{
5436	// sample updt tab index in the HEADER, then skip to second flit
5437	uint64_t receive_data = p_dspin_in.data.read();
5438	// for data INVAL, wait for dcache to take the request
5439	if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()))
5440	{
5441	r_cc_receive_dcache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_UPDT_INDEX);
5442	r_cc_receive_fsm = CC_RECEIVE_INVAL_NLINE;
5443	break;
5444	}
5445	// for ins INVAL, wait for icache to take the request
5446	if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()))
5447	{
5448	r_cc_receive_icache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_UPDT_INDEX);
5449	r_cc_receive_fsm = CC_RECEIVE_INVAL_NLINE;
5450	break;
5451	}
5452	// keep waiting for the correct cache to accept the request
5453	break;
5454	}
5455	////////////////////////////
5456	case CC_RECEIVE_INVAL_NLINE:
5457	{
5458	// sample nline in the second flit
5459	uint64_t receive_data = p_dspin_in.data.read();
5460	// for data INVAL, wait for dcache to take the request
5461	if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()) and (p_dspin_in.write.read()))
5462	{
5463	// request dcache to handle the INVAL
5464	r_cc_receive_dcache_req = true;
5465	r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_NLINE);
5466	r_cc_receive_dcache_type = CC_TYPE_INVAL;
5467	// get back to idle state
5468	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5469	break;
5470	}
5471	// for ins INVAL, wait for icache to take the request
5472	if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()) and (p_dspin_in.write.read()))
5473	{
5474	// request icache to handle the INVAL
5475	r_cc_receive_icache_req = true;
5476	r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_NLINE);
5477	r_cc_receive_icache_type = CC_TYPE_INVAL;
5478	// get back to idle state
5479	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5480	break;
5481	}
5482	// we should never get there
5483	assert ( false && "CC_RECEIVE_INVAL_NLINE : incoherent handling of either r_cc_receive_data_ins or r_cc_receive_*cache_req\n");
5484	}
5485	////////////////////////////
5486	case CC_RECEIVE_UPDT_HEADER:
5487	{
5488	// sample updt tab index in the HEADER, than skip to second flit
5489	uint64_t receive_data = p_dspin_in.data.read();
5490	// for data INVAL, wait for dcache to take the request and fifo to
5491	// be empty
5492	if ((r_cc_receive_data_ins.read() == 0) and not r_cc_receive_dcache_req.read() and r_cc_receive_updt_fifo_be.empty())
5493	{
5494	r_cc_receive_dcache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_UPDT_INDEX);
5495	r_cc_receive_fsm = CC_RECEIVE_UPDT_NLINE;
5496	break;
5497	}
5498	// for ins INVAL, wait for icache to take the request and fifo to be
5499	// empty
5500	if ((r_cc_receive_data_ins.read() == 1) and not r_cc_receive_icache_req.read() and r_cc_receive_updt_fifo_be.empty())
5501	{
5502	r_cc_receive_icache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_UPDT_INDEX);
5503	r_cc_receive_fsm = CC_RECEIVE_UPDT_NLINE;
5504	break;
5505	}
5506	// keep waiting for the correct cache to accept the request
5507	break;
5508	}
5509	///////////////////////////
5510	case CC_RECEIVE_UPDT_NLINE:
5511	{
5512	// sample nline and word index in the second flit
5513	uint64_t receive_data = p_dspin_in.data.read();
5514	// for data INVAL, wait for dcache to take the request and fifo to
5515	// be empty
5516	if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()) and r_cc_receive_updt_fifo_be.empty() and (p_dspin_in.write.read()))
5517	{
5518	r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_NLINE);
5519	r_cc_receive_word_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_WORD_INDEX);
5520	r_cc_receive_dcache_type = CC_TYPE_UPDT;
5521	// get back to idle state
5522	r_cc_receive_fsm = CC_RECEIVE_UPDT_DATA;
5523	break;
5524	}
5525	// for ins INVAL, wait for icache to take the request and fifo to be
5526	// empty
5527	if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()) and r_cc_receive_updt_fifo_be.empty() and (p_dspin_in.write.read()))
5528	{
5529	r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_NLINE);
5530	r_cc_receive_word_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_WORD_INDEX);
5531	r_cc_receive_icache_type = CC_TYPE_UPDT;
5532	// get back to idle state
5533	r_cc_receive_fsm = CC_RECEIVE_UPDT_DATA;
5534	break;
5535	}
5536	// we should never get there
5537	assert ( false && "CC_RECEIVE_UPDT_NLINE : incoherent handling of either r_cc_receive_data_ins or r_cc_receive_*cache_req or r_cc_receive_fifo\n");
5538	break;
5539	}
5540	//////////////////////////
5541	case CC_RECEIVE_UPDT_DATA:
5542	{
5543	if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()) and (p_dspin_in.write.read()))
5544	r_cc_receive_dcache_req = true;
5545	if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()) and (p_dspin_in.write.read()))
5546	r_cc_receive_icache_req = true;
5547
5548	// sample data, be and eop
5549	uint64_t receive_data = p_dspin_in.data.read();
5550	// wait for the fifo
5551	if (r_cc_receive_updt_fifo_be.wok() and (p_dspin_in.write.read()))
5552	{
5553	cc_receive_updt_fifo_be = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_BE);
5554	cc_receive_updt_fifo_data = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_DATA);
5555	// sample eop to test for state exit
5556	bool flit_eop = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::FROM_MC_EOP);
5557	cc_receive_updt_fifo_eop = flit_eop;
5558	cc_receive_updt_fifo_put = true;
5559	if(flit_eop)
5560	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5561	}
5562	break;
5563	}
5564	} // end switch CC_RECEIVE FSM
5565
5566	///////////////// Response FIFOs update //////////////////////
5567	r_vci_rsp_fifo_icache.update(vci_rsp_fifo_icache_get,
5568	vci_rsp_fifo_icache_put,
5569	vci_rsp_fifo_icache_data);
5570
5571	r_vci_rsp_fifo_dcache.update(vci_rsp_fifo_dcache_get,
5572	vci_rsp_fifo_dcache_put,
5573	vci_rsp_fifo_dcache_data);
5574
5575	///////////////// updt FIFO update //////////////////////
5576	//TODO check this
5577	r_cc_receive_updt_fifo_be.update(cc_receive_updt_fifo_get,
5578	cc_receive_updt_fifo_put,
5579	cc_receive_updt_fifo_be);
5580	r_cc_receive_updt_fifo_data.update(cc_receive_updt_fifo_get,
5581	cc_receive_updt_fifo_put,
5582	cc_receive_updt_fifo_data);
5583	r_cc_receive_updt_fifo_eop.update(cc_receive_updt_fifo_get,
5584	cc_receive_updt_fifo_put,
5585	cc_receive_updt_fifo_eop);
5586
5587	} // end transition()
5588
5589	///////////////////////
5590	tmpl(void)::genMoore()
5591	///////////////////////
5592	{
5593
5594	// VCI initiator command on the direct network
5595	// it depends on the CMD FSM state
5596
5597	bool is_sc_or_cas = (r_vci_cmd_fsm.read() == CMD_DATA_CAS) or
5598	(r_vci_cmd_fsm.read() == CMD_DATA_SC );
5599
5600	p_vci.pktid = 0;
5601	p_vci.srcid = m_srcid;
5602	p_vci.cons = is_sc_or_cas;
5603	p_vci.contig = not is_sc_or_cas;
5604	p_vci.wrap = false;
5605	p_vci.clen = 0;
5606	p_vci.cfixed = false;
5607
5608	switch ( r_vci_cmd_fsm.read() ) {
5609
5610	case CMD_IDLE:
5611	p_vci.cmdval = false;
5612	p_vci.address = 0;
5613	p_vci.wdata = 0;
5614	p_vci.be = 0;
5615	p_vci.trdid = 0;
5616	p_vci.pktid = 0;
5617	p_vci.plen = 0;
5618	p_vci.cmd = vci_param::CMD_NOP;
5619	p_vci.eop = false;
5620	break;
5621
5622	case CMD_INS_MISS:
5623	p_vci.cmdval = true;
5624	p_vci.address = r_icache_vci_paddr.read() & m_icache_yzmask;
5625	p_vci.wdata = 0;
5626	p_vci.be = 0xF;
5627	p_vci.trdid = 0;
5628	p_vci.pktid = TYPE_READ_INS_MISS;
5629	p_vci.plen = m_icache_words<<2;
5630	p_vci.cmd = vci_param::CMD_READ;
5631	p_vci.eop = true;
5632	break;
5633
5634	case CMD_INS_UNC:
5635	p_vci.cmdval = true;
5636	p_vci.address = r_icache_vci_paddr.read() & ~0x3;
5637	p_vci.wdata = 0;
5638	p_vci.be = 0xF;
5639	p_vci.trdid = 0;
5640	p_vci.pktid = TYPE_READ_INS_UNC;
5641	p_vci.plen = 4;
5642	p_vci.cmd = vci_param::CMD_READ;
5643	p_vci.eop = true;
5644	break;
5645
5646	case CMD_DATA_MISS:
5647	p_vci.cmdval = true;
5648	p_vci.address = r_dcache_vci_paddr.read() & m_dcache_yzmask;
5649	p_vci.wdata = 0;
5650	p_vci.be = 0xF;
5651	p_vci.trdid = 0;
5652	p_vci.pktid = TYPE_READ_DATA_MISS;
5653	p_vci.plen = m_dcache_words << 2;
5654	p_vci.cmd = vci_param::CMD_READ;
5655	p_vci.eop = true;
5656	break;
5657
5658	case CMD_DATA_UNC:
5659	p_vci.cmdval = true;
5660	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
5661	p_vci.wdata = 0;
5662	p_vci.be = r_dcache_vci_unc_be.read();
5663	p_vci.trdid = 0;
5664	p_vci.pktid = TYPE_READ_DATA_UNC;
5665	p_vci.plen = 4;
5666	p_vci.cmd = vci_param::CMD_READ;
5667	p_vci.eop = true;
5668	break;
5669
5670	case CMD_DATA_WRITE:
5671	p_vci.cmdval = true;
5672	p_vci.address = r_wbuf.getAddress(r_vci_cmd_cpt.read()) & ~0x3;
5673	p_vci.wdata = r_wbuf.getData(r_vci_cmd_cpt.read());
5674	p_vci.be = r_wbuf.getBe(r_vci_cmd_cpt.read());
5675	p_vci.trdid = r_wbuf.getIndex();
5676	p_vci.pktid = TYPE_WRITE;
5677	p_vci.plen = (r_vci_cmd_max.read() - r_vci_cmd_min.read() + 1) << 2;
5678	p_vci.cmd = vci_param::CMD_WRITE;
5679	p_vci.eop = (r_vci_cmd_cpt.read() == r_vci_cmd_max.read());
5680	break;
5681
5682	case CMD_DATA_LL:
5683	p_vci.cmdval = true;
5684	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
5685	p_vci.wdata = 0;
5686	p_vci.be = 0xF;
5687	p_vci.trdid = 0;
5688	p_vci.pktid = TYPE_LL;
5689	p_vci.plen = 8;
5690	p_vci.cmd = vci_param::CMD_LOCKED_READ;
5691	p_vci.eop = true;
5692	break;
5693
5694	case CMD_DATA_SC:
5695	p_vci.cmdval = true;
5696	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
5697	if ( r_vci_cmd_cpt.read() == 0 ) p_vci.wdata = r_dcache_llsc_key.read();
5698	else p_vci.wdata = r_dcache_vci_sc_data.read();
5699	p_vci.be = 0xF;
5700	p_vci.trdid = 0;
5701	p_vci.pktid = TYPE_SC;
5702	p_vci.plen = 8;
5703	p_vci.cmd = vci_param::CMD_NOP;
5704	p_vci.eop = (r_vci_cmd_cpt.read() == 1);
5705	break;
5706
5707	case CMD_DATA_CAS:
5708	p_vci.cmdval = true;
5709	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
5710	if ( r_vci_cmd_cpt.read() == 0 ) p_vci.wdata = r_dcache_vci_cas_old.read();
5711	else p_vci.wdata = r_dcache_vci_cas_new.read();
5712	p_vci.be = 0xF;
5713	p_vci.trdid = 0;
5714	p_vci.pktid = TYPE_CAS;
5715	p_vci.plen = 8;
5716	p_vci.cmd = vci_param::CMD_NOP;
5717	p_vci.eop = (r_vci_cmd_cpt.read() == 1);
5718	break;
5719	} // end switch r_vci_cmd_fsm
5720
5721	// VCI initiator response on the direct network
5722	// it depends on the VCI_RSP FSM
5723
5724	switch (r_vci_rsp_fsm.read() )
5725	{
5726	case RSP_DATA_WRITE : p_vci.rspack = true; break;
5727	case RSP_INS_MISS : p_vci.rspack = r_vci_rsp_fifo_icache.wok(); break;
5728	case RSP_INS_UNC : p_vci.rspack = r_vci_rsp_fifo_icache.wok(); break;
5729	case RSP_DATA_MISS : p_vci.rspack = r_vci_rsp_fifo_dcache.wok(); break;
5730	case RSP_DATA_UNC : p_vci.rspack = r_vci_rsp_fifo_dcache.wok(); break;
5731	case RSP_DATA_LL : p_vci.rspack = r_vci_rsp_fifo_dcache.wok(); break;
5732	case RSP_IDLE : p_vci.rspack = false; break;
5733	} // end switch r_vci_rsp_fsm
5734
5735
5736	// Send coherence packets on DSPIN L2M
5737	// it depends on the CC_SEND FSM
5738
5739	uint64_t dspin_send_data = 0;
5740	switch ( r_cc_send_fsm.read() )
5741	{
5742	//////////////////
5743	case CC_SEND_IDLE:
5744	{
5745	p_dspin_out.write = false;
5746	break;
5747	}
5748	///////////////////////
5749	case CC_SEND_CLEANUP_1:
5750	{
5751	// initialize dspin send data
5752	DspinDhccpParam::dspin_set(dspin_send_data,
5753	0,
5754	DspinDhccpParam::FROM_L1_EOP);
5755	DspinDhccpParam::dspin_set(dspin_send_data,
5756	m_cc_global_id,
5757	DspinDhccpParam::CLEANUP_SRCID);
5758	DspinDhccpParam::dspin_set(dspin_send_data,
5759	0,
5760	DspinDhccpParam::FROM_L1_BC);
5761
5762	if(r_cc_send_last_client.read() == 0) // dcache active request
5763	{
5764	uint64_t dest = (uint64_t)r_dcache_cc_send_nline.read()
5765	>> (m_nline_width - m_x_width - m_y_width)
5766	<< (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
5767
5768	DspinDhccpParam::dspin_set(dspin_send_data,
5769	dest,
5770	DspinDhccpParam::CLEANUP_DEST);
5771
5772	DspinDhccpParam::dspin_set(dspin_send_data,
5773	r_dcache_cc_send_nline.read() & 0x300000000ULL,
5774	DspinDhccpParam::CLEANUP_NLINE_MSB);
5775
5776	DspinDhccpParam::dspin_set(dspin_send_data,
5777	r_dcache_cc_send_way.read(),
5778	DspinDhccpParam::CLEANUP_WAY_INDEX);
5779
5780	DspinDhccpParam::dspin_set(dspin_send_data,
5781	DspinDhccpParam::TYPE_CLEANUP_DATA,
5782	DspinDhccpParam::FROM_L1_TYPE);
5783	}
5784	else // icache active request
5785	{
5786	uint64_t dest = (uint64_t)r_icache_cc_send_nline.read()
5787	>> (m_nline_width - m_x_width - m_y_width)
5788	<< (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
5789
5790	DspinDhccpParam::dspin_set(dspin_send_data,
5791	dest,
5792	DspinDhccpParam::CLEANUP_DEST);
5793
5794	DspinDhccpParam::dspin_set(dspin_send_data,
5795	r_icache_cc_send_nline.read() & 0x300000000ULL,
5796	DspinDhccpParam::CLEANUP_NLINE_MSB);
5797
5798	DspinDhccpParam::dspin_set(dspin_send_data,
5799	r_icache_cc_send_way.read(),
5800	DspinDhccpParam::CLEANUP_WAY_INDEX);
5801
5802	DspinDhccpParam::dspin_set(dspin_send_data,
5803	DspinDhccpParam::TYPE_CLEANUP_INST,
5804	DspinDhccpParam::FROM_L1_TYPE);
5805	}
5806	// send flit
5807	p_dspin_out.data = dspin_send_data;
5808	p_dspin_out.write = true;
5809	break;
5810	}
5811	///////////////////////
5812	case CC_SEND_CLEANUP_2:
5813	{
5814	// initialize dspin send data
5815	DspinDhccpParam::dspin_set(dspin_send_data,
5816	1,
5817	DspinDhccpParam::FROM_L1_EOP);
5818
5819	if(r_cc_send_last_client.read() == 0) // dcache active request
5820	{
5821	DspinDhccpParam::dspin_set(dspin_send_data,
5822	r_dcache_cc_send_nline.read() & 0xFFFFFFFFULL,
5823	DspinDhccpParam::CLEANUP_NLINE_LSB);
5824	}
5825	else // icache active request
5826	{
5827	DspinDhccpParam::dspin_set(dspin_send_data,
5828	r_icache_cc_send_nline.read() & 0xFFFFFFFFULL,
5829	DspinDhccpParam::CLEANUP_NLINE_LSB);
5830	}
5831	// send flit
5832	p_dspin_out.data = dspin_send_data;
5833	p_dspin_out.write = true;
5834	break;
5835	}
5836	///////////////////////
5837	case CC_SEND_MULTI_ACK:
5838	{
5839	// initialize dspin send data
5840	DspinDhccpParam::dspin_set(dspin_send_data,
5841	1,
5842	DspinDhccpParam::FROM_L1_EOP);
5843	DspinDhccpParam::dspin_set(dspin_send_data,
5844	0,
5845	DspinDhccpParam::FROM_L1_BC);
5846	DspinDhccpParam::dspin_set(dspin_send_data,
5847	DspinDhccpParam::TYPE_MULTI_ACK,
5848	DspinDhccpParam::FROM_L1_TYPE);
5849
5850	if(r_cc_send_last_client.read() == 0) // dcache active request
5851	{
5852	uint64_t dest = (uint64_t)r_dcache_cc_send_nline.read()
5853	>> (m_nline_width - m_x_width - m_y_width)
5854	<< (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
5855
5856	DspinDhccpParam::dspin_set(dspin_send_data,
5857	dest,
5858	DspinDhccpParam::MULTI_ACK_DEST);
5859
5860	DspinDhccpParam::dspin_set(dspin_send_data,
5861	r_dcache_cc_send_updt_tab_idx.read(),
5862	DspinDhccpParam::MULTI_ACK_UPDT_INDEX);
5863	}
5864	else // icache active request
5865	{
5866	uint64_t dest = (uint64_t)r_icache_cc_send_nline.read()
5867	>> (m_nline_width - m_x_width - m_y_width)
5868	<< (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
5869
5870
5871	DspinDhccpParam::dspin_set(dspin_send_data,
5872	dest,
5873	DspinDhccpParam::MULTI_ACK_DEST);
5874
5875	DspinDhccpParam::dspin_set(dspin_send_data,
5876	r_icache_cc_send_updt_tab_idx.read(),
5877	DspinDhccpParam::MULTI_ACK_UPDT_INDEX);
5878	}
5879	// send flit
5880	p_dspin_out.data = dspin_send_data;
5881	p_dspin_out.write = true;
5882
5883	break;
5884	}
5885	} // end switch CC_SEND FSM
5886
5887	// Receive coherence packets
5888	// It depends on the CC_RECEIVE FSM
5889
5890	switch( r_cc_receive_fsm.read() )
5891	{
5892	/////////////////////
5893	case CC_RECEIVE_IDLE:
5894	{
5895	p_dspin_in.read = false;
5896	break;
5897	}
5898	//////////////////////
5899	case CC_RECEIVE_CLACK:
5900	{
5901	if (((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read())) or
5902	((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read())))
5903	p_dspin_in.read = true;
5904	else
5905	p_dspin_in.read = false;
5906	break;
5907	}
5908	///////////////////////////////
5909	case CC_RECEIVE_BRDCAST_HEADER:
5910	{
5911	p_dspin_in.read = true;
5912	break;
5913	}
5914	//////////////////////////////
5915	case CC_RECEIVE_BRDCAST_NLINE:
5916	{
5917	// TODO maybe we need to wait for both only to leave the state, but
5918	// not to actually post a request to an available cache => need a
5919	// flip_flop to check that ?
5920	if (not (r_cc_receive_icache_req.read()) and not (r_cc_receive_dcache_req.read()))
5921	p_dspin_in.read = true;
5922	else
5923	p_dspin_in.read = false;
5924	break;
5925	}
5926	/////////////////////////////
5927	case CC_RECEIVE_INVAL_HEADER:
5928	{
5929	if (((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read())) or
5930	((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read())))
5931	p_dspin_in.read = true;
5932	else
5933	p_dspin_in.read = false;
5934	break;
5935	}
5936	////////////////////////////
5937	case CC_RECEIVE_INVAL_NLINE:
5938	{
5939	p_dspin_in.read = true;
5940	break;
5941	}
5942	////////////////////////////
5943	case CC_RECEIVE_UPDT_HEADER:
5944	{
5945	if (((r_cc_receive_data_ins.read() == 0) and
5946	not r_cc_receive_dcache_req.read() and
5947	r_cc_receive_updt_fifo_be.empty())
5948	or
5949	((r_cc_receive_data_ins.read() == 1) and
5950	not r_cc_receive_icache_req.read()) and
5951	r_cc_receive_updt_fifo_be.empty())
5952	p_dspin_in.read = true;
5953	else
5954	p_dspin_in.read = false;
5955	break;
5956	}
5957	///////////////////////////
5958	case CC_RECEIVE_UPDT_NLINE:
5959	{
5960	if (((r_cc_receive_data_ins.read() == 0) and
5961	not (r_cc_receive_dcache_req.read()) and
5962	r_cc_receive_updt_fifo_be.empty())
5963	or
5964	((r_cc_receive_data_ins.read() == 1) and
5965	not (r_cc_receive_icache_req.read()) and
5966	r_cc_receive_updt_fifo_be.empty()))
5967	p_dspin_in.read = true;
5968	else
5969	p_dspin_in.read = false;
5970	break;
5971	}
5972	//////////////////////////
5973	case CC_RECEIVE_UPDT_DATA:
5974	{
5975	if (r_cc_receive_updt_fifo_be.wok())
5976	p_dspin_in.read = true;
5977	else
5978	p_dspin_in.read = false;
5979	break;
5980	}
5981	} // end switch CC_RECEIVE FSM
5982
5983	} // end genMoore
5984
5985	}}
5986
5987	// Local Variables:
5988	// tab-width: 4
5989	// c-basic-offset: 4
5990	// c-file-offsets:((innamespace . 0)(inline-open . 0))
5991	// indent-tabs-mode: nil
5992	// End:
5993
5994	// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4

Note: See TracBrowser for help on using the repository browser.

Download in other formats:

Project-Id-Version: Trac 0.12
Report-Msgid-Bugs-To: trac-dev@googlegroups.com
POT-Creation-Date: 2018-07-07 16:55+0000
PO-Revision-Date: 2010-07-19 23:05+0200
Last-Translator: Jeroen Ruigrok van der Werven <asmodai@in-nomine.org>
Language: en_US
Language-Team: en_US <trac-dev@googlegroups.com>
Plural-Forms: nplurals=2; plural=(n != 1)
MIME-Version: 1.0
Content-Type: text/plain; charset=utf-8
Content-Transfer-Encoding: 8bit
Generated-By: Babel 2.8.0