source: branches/v5/modules/vci_cc_vcache_wrapper_dspin_coherence/caba/source/include/vci_cc_vcache_wrapper_dspin_coherence.h @ 331

Last change on this file since 331 was 331, checked in by joannou, 11 years ago

Renaming all files form vci_cc_vcache_wrapper_dspin_coherence and vci_mem_cache_dspin_coherence
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1/* -*- c++ -*-
2 * File : vci_cc_vcache_wrapper.h
3 * Copyright (c) UPMC, Lip6, SoC
4 * Authors : Alain GREINER, Yang GAO
5 * Date : 27/11/2011
6 *
7 * SOCLIB_LGPL_HEADER_BEGIN
8 *
9 * This file is part of SoCLib, GNU LGPLv2.1.
10 *
11 * SoCLib is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU Lesser General Public License as published
13 * by the Free Software Foundation; version 2.1 of the License.
14 *
15 * SoCLib is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
18 * Lesser General Public License for more details.
19 *
20 * You should have received a copy of the GNU Lesser General Public
21 * License along with SoCLib; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
23 * 02110-1301 USA
24 *
25 * SOCLIB_LGPL_HEADER_END
26 *
27 * Maintainers: cesar.fuguet-tortolero@lip6.fr
28 *              alexandre.joannou@lip6.fr
29 */
30
31#ifndef SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER_H
32#define SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER_H
33
34#include <inttypes.h>
35#include <systemc>
36#include "caba_base_module.h"
37#include "multi_write_buffer.h"
38#include "generic_fifo.h"
39#include "generic_tlb.h"
40#include "generic_cache.h"
41#include "vci_initiator.h"
42#include "dspin_interface.h"
43#include "dspin_dhccp_param.h"
44#include "mapping_table.h"
45#include "static_assert.h"
46#include "iss2.h"
47
48#define LLSC_TIMEOUT    10000
49
50namespace soclib {
51namespace caba {
52
53using namespace sc_core;
54
55////////////////////////////////////////////
56template<typename vci_param, typename iss_t>
57class VciCcVCacheWrapper
58////////////////////////////////////////////
59    : public soclib::caba::BaseModule
60{
61    typedef uint32_t vaddr_t;
62    typedef uint32_t tag_t;
63    typedef uint32_t type_t;
64    typedef typename iss_t::DataOperationType data_op_t;
65
66    typedef typename vci_param::addr_t  paddr_t;
67    typedef typename vci_param::data_t  vci_data_t;
68    typedef typename vci_param::be_t    vci_be_t;
69    typedef typename vci_param::srcid_t vci_srcid_t;
70    typedef typename vci_param::trdid_t vci_trdid_t;
71    typedef typename vci_param::pktid_t vci_pktid_t;
72    typedef typename vci_param::plen_t  vci_plen_t;
73
74    enum icache_fsm_state_e {
75        ICACHE_IDLE,
76        // handling XTN processor requests
77        ICACHE_XTN_TLB_FLUSH,
78        ICACHE_XTN_CACHE_FLUSH,
79        ICACHE_XTN_CACHE_FLUSH_GO,
80        ICACHE_XTN_TLB_INVAL,
81        ICACHE_XTN_CACHE_INVAL_VA,
82        ICACHE_XTN_CACHE_INVAL_PA,
83        ICACHE_XTN_CACHE_INVAL_GO,
84        // handling tlb miss
85        ICACHE_TLB_WAIT,
86        // handling cache miss
87        ICACHE_MISS_SELECT,
88        ICACHE_MISS_CLEAN,
89        ICACHE_MISS_WAIT,
90        ICACHE_MISS_DATA_UPDT,
91        ICACHE_MISS_DIR_UPDT,
92        // handling unc read
93        ICACHE_UNC_WAIT,
94        // handling coherence requests
95        ICACHE_CC_CHECK,
96        ICACHE_CC_INVAL,
97        ICACHE_CC_UPDT,
98        ICACHE_CC_BROADCAST,
99        ICACHE_CC_SEND_WAIT,
100    };
101
102    enum dcache_fsm_state_e {
103        DCACHE_IDLE,
104        // handling itlb & dtlb miss
105        DCACHE_TLB_MISS,
106        DCACHE_TLB_PTE1_GET,
107        DCACHE_TLB_PTE1_SELECT,
108        DCACHE_TLB_PTE1_UPDT,
109        DCACHE_TLB_PTE2_GET,
110        DCACHE_TLB_PTE2_SELECT,
111        DCACHE_TLB_PTE2_UPDT,
112        DCACHE_TLB_LR_UPDT,
113        DCACHE_TLB_LR_WAIT,
114        DCACHE_TLB_RETURN,
115            // handling processor XTN requests
116        DCACHE_XTN_SWITCH,
117        DCACHE_XTN_SYNC,
118        DCACHE_XTN_IC_INVAL_VA,
119        DCACHE_XTN_IC_FLUSH,
120        DCACHE_XTN_IC_INVAL_PA,
121        DCACHE_XTN_IT_INVAL,
122        DCACHE_XTN_DC_FLUSH,
123        DCACHE_XTN_DC_FLUSH_GO,
124        DCACHE_XTN_DC_INVAL_VA,
125        DCACHE_XTN_DC_INVAL_PA,
126        DCACHE_XTN_DC_INVAL_END,
127        DCACHE_XTN_DC_INVAL_GO,
128        DCACHE_XTN_DT_INVAL,
129        //handling dirty bit update
130        DCACHE_DIRTY_GET_PTE,
131        DCACHE_DIRTY_WAIT,
132            // handling processor miss requests
133        DCACHE_MISS_SELECT,
134        DCACHE_MISS_CLEAN,
135        DCACHE_MISS_WAIT,
136        DCACHE_MISS_DATA_UPDT,
137        DCACHE_MISS_DIR_UPDT,
138        // handling processor unc, ll and sc requests
139        DCACHE_UNC_WAIT,
140        DCACHE_LL_WAIT,
141        DCACHE_SC_WAIT,
142        // handling coherence requests
143        DCACHE_CC_CHECK,
144        DCACHE_CC_INVAL,
145        DCACHE_CC_UPDT,
146        DCACHE_CC_BROADCAST,
147        DCACHE_CC_SEND_WAIT,
148        // handling TLB inval (after a coherence or XTN request)
149        DCACHE_INVAL_TLB_SCAN,
150    };
151
152    enum cmd_fsm_state_e {
153        CMD_IDLE,
154        CMD_INS_MISS,
155        CMD_INS_UNC,
156        CMD_DATA_MISS,
157        CMD_DATA_UNC,
158        CMD_DATA_WRITE,
159        CMD_DATA_LL,
160        CMD_DATA_SC,
161        CMD_DATA_CAS,
162    };
163
164    enum rsp_fsm_state_e {
165        RSP_IDLE,
166        RSP_INS_MISS,
167        RSP_INS_UNC,
168        RSP_DATA_MISS,
169        RSP_DATA_UNC,
170        RSP_DATA_LL,
171        RSP_DATA_WRITE,
172    };
173
174    enum cc_receive_fsm_state_e {
175        CC_RECEIVE_IDLE,
176        CC_RECEIVE_CLACK,
177        CC_RECEIVE_BRDCAST_HEADER,
178        CC_RECEIVE_BRDCAST_NLINE,
179        CC_RECEIVE_INVAL_HEADER,
180        CC_RECEIVE_INVAL_NLINE,
181        CC_RECEIVE_UPDT_HEADER,
182        CC_RECEIVE_UPDT_NLINE,
183        CC_RECEIVE_UPDT_DATA,
184    };
185
186    enum cc_send_fsm_state_e {
187        CC_SEND_IDLE,
188        CC_SEND_CLEANUP_1,
189        CC_SEND_CLEANUP_2,
190        CC_SEND_MULTI_ACK,
191    };
192
193    /* transaction type, pktid field */
194    enum transaction_type_e
195    {
196        // b3 unused
197        // b2 READ / NOT READ
198        // if READ
199        //  b1 DATA / INS
200        //  b0 UNC / MISS
201        // else
202        //  b1 accÚs table llsc type SW / other
203        //  b2 WRITE/CAS/LL/SC
204        TYPE_READ_DATA_UNC          = 0x0,
205        TYPE_READ_DATA_MISS         = 0x1,
206        TYPE_READ_INS_UNC           = 0x2,
207        TYPE_READ_INS_MISS          = 0x3,
208        TYPE_WRITE                  = 0x4,
209        TYPE_CAS                    = 0x5,
210        TYPE_LL                     = 0x6,
211        TYPE_SC                     = 0x7
212    };
213
214    /* SC return values */
215    enum sc_status_type_e
216    {
217        SC_SUCCESS  =   0x00000000,
218        SC_FAIL     =   0x00000001
219    };
220
221    // cc_send_type
222    typedef enum {
223        CC_TYPE_CLEANUP,
224        CC_TYPE_MULTI_ACK,
225    } cc_send_t;
226
227    // cc_receive_type
228    typedef enum {
229        CC_TYPE_CLACK,
230        CC_TYPE_BRDCAST,
231        CC_TYPE_INVAL,
232        CC_TYPE_UPDT,
233    } cc_receive_t;
234
235    // TLB Mode : ITLB / DTLB / ICACHE / DCACHE
236    enum {
237        INS_TLB_MASK    = 0x8,
238        DATA_TLB_MASK   = 0x4,
239        INS_CACHE_MASK  = 0x2,
240        DATA_CACHE_MASK = 0x1,
241    };
242
243    // Error Type
244    enum mmu_error_type_e
245    {
246        MMU_NONE                      = 0x0000, // None
247        MMU_WRITE_PT1_UNMAPPED        = 0x0001, // Write & Page fault on PT1
248        MMU_WRITE_PT2_UNMAPPED        = 0x0002, // Write & Page fault on PT2
249        MMU_WRITE_PRIVILEGE_VIOLATION = 0x0004, // Write & Protected access in user mode
250        MMU_WRITE_ACCES_VIOLATION     = 0x0008, // Write to non writable page
251        MMU_WRITE_UNDEFINED_XTN       = 0x0020, // Write & undefined external access
252        MMU_WRITE_PT1_ILLEGAL_ACCESS  = 0x0040, // Write & Bus Error accessing PT1
253        MMU_WRITE_PT2_ILLEGAL_ACCESS  = 0x0080, // Write & Bus Error accessing PT2
254        MMU_WRITE_DATA_ILLEGAL_ACCESS = 0x0100, // Write & Bus Error in cache access
255        MMU_READ_PT1_UNMAPPED         = 0x1001, // Read & Page fault on PT1
256        MMU_READ_PT2_UNMAPPED         = 0x1002, // Read & Page fault on PT2
257        MMU_READ_PRIVILEGE_VIOLATION  = 0x1004, // Read & Protected access in user mode
258        MMU_READ_EXEC_VIOLATION       = 0x1010, // Read & Exec access to a non exec page
259        MMU_READ_UNDEFINED_XTN        = 0x1020, // Read & Undefined external access
260        MMU_READ_PT1_ILLEGAL_ACCESS   = 0x1040, // Read & Bus Error accessing PT1
261        MMU_READ_PT2_ILLEGAL_ACCESS   = 0x1080, // Read & Bus Error accessing PT2
262        MMU_READ_DATA_ILLEGAL_ACCESS  = 0x1100, // Read & Bus Error in cache access
263    };
264
265    // miss types for data cache
266    enum dcache_miss_type_e
267    {
268        PTE1_MISS,
269        PTE2_MISS,
270        PROC_MISS,
271    };
272
273    enum transaction_type_d_e
274    {
275        // b0 : 1 if cached
276        // b1 : 1 if instruction
277        TYPE_DATA_UNC     = 0x0,
278        TYPE_DATA_MISS    = 0x1,
279        TYPE_INS_UNC      = 0x2,
280        TYPE_INS_MISS     = 0x3,
281    };
282
283public:
284    sc_in<bool>                             p_clk;
285    sc_in<bool>                             p_resetn;
286    sc_in<bool>                             p_irq[iss_t::n_irq];
287    soclib::caba::VciInitiator<vci_param>   p_vci_ini_d;
288    soclib::caba::DspinInput <40> p_dspin_in;
289    soclib::caba::DspinOutput<33> p_dspin_out;
290
291private:
292
293    // STRUCTURAL PARAMETERS
294    soclib::common::AddressDecodingTable<uint32_t, bool>        m_cacheability_table;
295    const soclib::common::Segment                               m_segment;
296    const vci_srcid_t                                           m_srcid_d;
297    const vci_srcid_t                                           m_srcid_c;
298
299    const size_t                                                m_itlb_ways;
300    const size_t                                                m_itlb_sets;
301
302    const size_t                                                m_dtlb_ways;
303    const size_t                                                m_dtlb_sets;
304
305    const size_t                                                m_icache_ways;
306    const size_t                                                m_icache_sets;
307    const paddr_t                                               m_icache_yzmask;
308    const size_t                                                m_icache_words;
309
310    const size_t                                                m_dcache_ways;
311    const size_t                                                m_dcache_sets;
312    const paddr_t                                               m_dcache_yzmask;
313    const size_t                                                m_dcache_words;
314
315    const size_t                        m_x_width;
316    const size_t                        m_y_width;
317
318    const size_t                        m_memory_cache_local_id;
319    const size_t                        m_proc_id;
320    const uint32_t                                              m_max_frozen_cycles;
321    const size_t                                                m_paddr_nbits;
322
323    ////////////////////////////////////////
324    // Communication with processor ISS
325    ////////////////////////////////////////
326    typename iss_t::InstructionRequest  m_ireq;
327    typename iss_t::InstructionResponse m_irsp;
328    typename iss_t::DataRequest         m_dreq;
329    typename iss_t::DataResponse        m_drsp;
330
331    /////////////////////////////////////////////
332    // debug variables (for each FSM)
333    /////////////////////////////////////////////
334    uint32_t                            m_debug_start_cycle;
335    bool                                m_debug_ok;
336    bool                                m_debug_previous_hit;
337    bool                                m_idebug_previous_hit;
338    bool                                m_debug_dcache_fsm;
339    bool                                m_debug_icache_fsm;
340    bool                                m_debug_inval_itlb_fsm;
341    bool                                m_debug_inval_dtlb_fsm;
342
343    ///////////////////////////////
344    // Software visible REGISTERS
345    ///////////////////////////////
346    sc_signal<uint32_t>     r_mmu_ptpr;                 // page table pointer register
347    sc_signal<uint32_t>     r_mmu_mode;                 // mmu mode register
348    sc_signal<uint32_t>     r_mmu_word_lo;              // mmu misc data low
349    sc_signal<uint32_t>     r_mmu_word_hi;              // mmu misc data hight
350    sc_signal<uint32_t>     r_mmu_ibvar;                // mmu bad instruction address
351    sc_signal<uint32_t>     r_mmu_dbvar;                // mmu bad data address
352    sc_signal<uint32_t>     r_mmu_ietr;                 // mmu instruction error type
353    sc_signal<uint32_t>     r_mmu_detr;                 // mmu data error type
354    uint32_t                r_mmu_params;                       // read-only
355    uint32_t                r_mmu_release;                      // read_only
356
357
358    //////////////////////////////
359    // ICACHE FSM REGISTERS
360    //////////////////////////////
361    sc_signal<int>          r_icache_fsm;               // state register
362    sc_signal<int>          r_icache_fsm_save;          // return state for coherence op
363    sc_signal<paddr_t>      r_icache_vci_paddr;         // physical address
364    sc_signal<uint32_t>     r_icache_vaddr_save;        // virtual address from processor
365
366    // icache miss handling
367    sc_signal<size_t>       r_icache_miss_way;              // selected way for cache update
368    sc_signal<size_t>       r_icache_miss_set;              // selected set for cache update
369    sc_signal<size_t>       r_icache_miss_word;             // word index ( cache update)
370    sc_signal<bool>         r_icache_miss_inval;        // coherence request matching a miss
371    sc_signal<bool>         r_icache_miss_clack;        // waiting for a cleanup acknowledge
372
373    // coherence request handling
374    sc_signal<size_t>       r_icache_cc_way;                // selected way for cc update/inval
375    sc_signal<size_t>       r_icache_cc_set;                // selected set for cc update/inval
376    sc_signal<size_t>       r_icache_cc_word;               // word counter for cc update
377    sc_signal<bool>         r_icache_cc_need_write;     // activate the cache for writing
378
379    // icache flush handling
380    sc_signal<size_t>       r_icache_flush_count;           // slot counter used for cache flush
381
382    // communication between ICACHE FSM and VCI_CMD FSM
383    sc_signal<bool>         r_icache_miss_req;           // cached read miss
384    sc_signal<bool>         r_icache_unc_req;            // uncached read miss
385
386    // communication between ICACHE FSM and DCACHE FSM
387    sc_signal<bool>             r_icache_tlb_miss_req;       // (set icache/reset dcache)
388    sc_signal<bool>         r_icache_tlb_rsp_error;      // tlb miss response error
389
390    // communication between ICACHE FSM and CC_SEND FSM
391    sc_signal<bool>         r_icache_cc_send_req;           // ICACHE cc_send request
392    sc_signal<cc_send_t>    r_icache_cc_send_type;          // ICACHE cc_send request type
393    sc_signal<paddr_t>      r_icache_cc_send_nline;         // ICACHE cc_send nline
394    sc_signal<size_t>       r_icache_cc_send_way;           // ICACHE cc_send way
395    sc_signal<size_t>       r_icache_cc_send_updt_tab_idx;  // ICACHE cc_send update table index
396
397    ///////////////////////////////
398    // DCACHE FSM REGISTERS
399    ///////////////////////////////
400    sc_signal<int>          r_dcache_fsm;               // state register
401    sc_signal<int>          r_dcache_fsm_cc_save;       // return state for coherence op
402    sc_signal<int>          r_dcache_fsm_scan_save;     // return state for tlb scan op
403    // registers written in P0 stage (used in P1 stage)
404    sc_signal<bool>         r_dcache_wbuf_req;          // WBUF must be written in P1 stage
405    sc_signal<bool>         r_dcache_updt_req;          // DCACHE must be updated in P1 stage
406    sc_signal<uint32_t>     r_dcache_save_vaddr;        // virtual address (from proc)
407    sc_signal<uint32_t>     r_dcache_save_wdata;        // write data (from proc)
408    sc_signal<vci_be_t>     r_dcache_save_be;           // byte enable (from proc)
409    sc_signal<paddr_t>      r_dcache_save_paddr;        // physical address
410    sc_signal<bool>         r_dcache_save_cacheable;    // address cacheable
411    sc_signal<size_t>       r_dcache_save_cache_way;    // selected way (from dcache)
412    sc_signal<size_t>       r_dcache_save_cache_set;    // selected set (from dcache)
413    sc_signal<size_t>       r_dcache_save_cache_word;   // selected word (from dcache)
414    // registers used by the Dirty bit sub-fsm
415    sc_signal<paddr_t>      r_dcache_dirty_paddr;       // PTE physical address
416    sc_signal<size_t>       r_dcache_dirty_way;         // way to invalidate in dcache
417    sc_signal<size_t>       r_dcache_dirty_set;         // set to invalidate in dcache
418
419    // communication between DCACHE FSM and VCI_CMD FSM
420    sc_signal<paddr_t>      r_dcache_vci_paddr;             // physical address for VCI command
421    sc_signal<bool>         r_dcache_vci_miss_req;      // read miss request
422    sc_signal<bool>         r_dcache_vci_unc_req;       // uncacheable read request
423    sc_signal<bool>         r_dcache_vci_unc_be;        // uncacheable read byte enable
424    sc_signal<bool>         r_dcache_vci_cas_req;       // atomic write request CAS
425    sc_signal<uint32_t>     r_dcache_vci_cas_old;       // previous data value for a CAS
426    sc_signal<uint32_t>     r_dcache_vci_cas_new;       // new data value for a CAS
427    sc_signal<bool>         r_dcache_vci_ll_req;        // atomic read request LL
428    sc_signal<bool>         r_dcache_vci_sc_req;        // atomic write request SC
429    sc_signal<vci_data_t>   r_dcache_vci_sc_data;       // SC data (command)
430
431    // register used for XTN inval
432    sc_signal<size_t>       r_dcache_xtn_way;               // selected way (from dcache)
433    sc_signal<size_t>       r_dcache_xtn_set;               // selected set (from dcache)
434
435    // write buffer state extension
436    sc_signal<bool>         r_dcache_pending_unc_write; // pending uncacheable write in WBUF
437
438    // handling dcache miss
439    sc_signal<int>              r_dcache_miss_type;                 // depending on the requester
440    sc_signal<size_t>       r_dcache_miss_word;             // word index for cache update
441    sc_signal<size_t>       r_dcache_miss_way;              // selected way for cache update
442    sc_signal<size_t>       r_dcache_miss_set;              // selected set for cache update
443    sc_signal<bool>         r_dcache_miss_inval;        // coherence request matching a miss
444    sc_signal<bool>         r_dcache_miss_clack;        // waiting for a cleanup acknowledge
445
446    // handling coherence requests
447    sc_signal<size_t>       r_dcache_cc_way;                // selected way for cc update/inval
448    sc_signal<size_t>       r_dcache_cc_set;                // selected set for cc update/inval
449    sc_signal<size_t>       r_dcache_cc_word;               // word counter for cc update
450    sc_signal<bool>         r_dcache_cc_need_write;     // activate the cache for writing
451
452    // dcache flush handling
453    sc_signal<size_t>       r_dcache_flush_count;           // slot counter used for cache flush
454
455    // ll response handling
456    sc_signal<size_t>       r_dcache_ll_rsp_count;          // flit counter used for ll rsp
457
458    // used by the TLB miss sub-fsm
459    sc_signal<uint32_t>     r_dcache_tlb_vaddr;             // virtual address for a tlb miss
460    sc_signal<bool>         r_dcache_tlb_ins;               // target tlb (itlb if true)
461    sc_signal<paddr_t>      r_dcache_tlb_paddr;             // physical address of pte
462    sc_signal<uint32_t>     r_dcache_tlb_pte_flags;         // pte1 or first word of pte2
463    sc_signal<uint32_t>     r_dcache_tlb_pte_ppn;           // second word of pte2
464    sc_signal<size_t>       r_dcache_tlb_cache_way;         // selected way in dcache
465    sc_signal<size_t>       r_dcache_tlb_cache_set;         // selected set in dcache
466    sc_signal<size_t>       r_dcache_tlb_cache_word;    // selected word in dcache
467    sc_signal<size_t>       r_dcache_tlb_way;               // selected way in tlb
468    sc_signal<size_t>       r_dcache_tlb_set;               // selected set in tlb
469
470    // ITLB and DTLB invalidation
471    sc_signal<paddr_t>      r_dcache_tlb_inval_line;    // line index
472    sc_signal<size_t>       r_dcache_tlb_inval_set;     // tlb set counter
473
474    // communication between DCACHE FSM and ICACHE FSM
475    sc_signal<bool>         r_dcache_xtn_req;           // xtn request (caused by processor)
476    sc_signal<int>          r_dcache_xtn_opcode;        // xtn request type
477
478    // communication between DCACHE FSM and CC_SEND FSM
479    sc_signal<bool>         r_dcache_cc_send_req;           // DCACHE cc_send request
480    sc_signal<cc_send_t>    r_dcache_cc_send_type;          // DCACHE cc_send request type
481    sc_signal<paddr_t>      r_dcache_cc_send_nline;         // DCACHE cc_send nline
482    sc_signal<size_t>       r_dcache_cc_send_way;           // DCACHE cc_send way
483    sc_signal<size_t>       r_dcache_cc_send_updt_tab_idx;  // DCACHE cc_send update table index
484
485    // dcache directory extension
486    bool                    *r_dcache_in_tlb;           // copy exist in dtlb or itlb
487    bool                    *r_dcache_contains_ptd;     // cache line contains a PTD
488
489    ///////////////////////////////////
490    // VCI_CMD FSM REGISTERS
491    ///////////////////////////////////
492    sc_signal<int>          r_vci_cmd_fsm;
493    sc_signal<size_t>       r_vci_cmd_min;                  // used for write bursts
494    sc_signal<size_t>       r_vci_cmd_max;                  // used for write bursts
495    sc_signal<size_t>       r_vci_cmd_cpt;                  // used for write bursts
496    sc_signal<bool>         r_vci_cmd_imiss_prio;           // round-robin between imiss & dmiss
497
498    ///////////////////////////////////
499    // VCI_RSP FSM REGISTERS
500    ///////////////////////////////////
501    sc_signal<int>          r_vci_rsp_fsm;
502    sc_signal<size_t>       r_vci_rsp_cpt;
503    sc_signal<bool>         r_vci_rsp_ins_error;
504    sc_signal<bool>         r_vci_rsp_data_error;
505    GenericFifo<uint32_t>   r_vci_rsp_fifo_icache;          // response FIFO to ICACHE FSM
506    GenericFifo<uint32_t>   r_vci_rsp_fifo_dcache;          // response FIFO to DCACHE FSM
507
508    ///////////////////////////////////
509    //  CC_SEND FSM REGISTER
510    ///////////////////////////////////
511    sc_signal<int>          r_cc_send_fsm;          // state register
512    sc_signal<bool>         r_cc_send_last_client;  // round robin flip-flop : 0 dcache / 1 icache
513
514    ///////////////////////////////////
515    //  CC_RECEIVE FSM REGISTER
516    ///////////////////////////////////
517    sc_signal<int>          r_cc_receive_fsm;          // state register
518    sc_signal<bool>         r_cc_receive_data_ins;     // request concerning : 0 dcache / 1 icache
519
520    // communication cc updt FIFO between CC_RECEIVE FSM and ICACHE/DCACHE FSM
521    sc_signal<size_t>       r_cc_receive_word_idx;  // word index
522    GenericFifo<uint32_t>   r_cc_receive_updt_fifo_be;
523    GenericFifo<uint32_t>   r_cc_receive_updt_fifo_data;
524    GenericFifo<bool>       r_cc_receive_updt_fifo_eop;
525
526    // communication between CC_RECEIVE FSM and ICACHE FSM
527    sc_signal<bool>         r_cc_receive_icache_req;       // cc_receive to icache request
528    sc_signal<cc_receive_t> r_cc_receive_icache_type;      // cc_receive type of coherence request
529    sc_signal<size_t>       r_cc_receive_icache_way;       // cc_receive to icache way
530    sc_signal<size_t>       r_cc_receive_icache_set;       // cc_receive to icache set
531    sc_signal<size_t>       r_cc_receive_icache_updt_tab_idx;  // cc_receive update table index
532    sc_signal<paddr_t>      r_cc_receive_icache_nline;     // cache line physical address
533
534    // communication between CC_RECEIVE FSM and DCACHE FSM
535    sc_signal<bool>         r_cc_receive_dcache_req;       // cc_receive to dcache request
536    sc_signal<cc_receive_t> r_cc_receive_dcache_type;      // cc_receive type of coherence request
537    sc_signal<size_t>       r_cc_receive_dcache_way;       // cc_receive to dcache way
538    sc_signal<size_t>       r_cc_receive_dcache_set;       // cc_receive to dcache set
539    sc_signal<size_t>       r_cc_receive_dcache_updt_tab_idx;  // cc_receive update table index
540    sc_signal<paddr_t>      r_cc_receive_dcache_nline;     // cache line physical address
541
542    //////////////////////////////////////////////////////////////////
543    // processor, write buffer, caches , TLBs
544    //////////////////////////////////////////////////////////////////
545
546    iss_t                       r_iss;
547    MultiWriteBuffer<paddr_t>   r_wbuf;
548    GenericCache<paddr_t>       r_icache;
549    GenericCache<paddr_t>       r_dcache;
550    GenericTlb<paddr_t>         r_itlb;
551    GenericTlb<paddr_t>         r_dtlb;
552
553    //////////////////////////////////////////////////////////////////
554    // llsc registration buffer
555    //////////////////////////////////////////////////////////////////
556
557    sc_signal<paddr_t>                     r_dcache_llsc_paddr;
558    sc_signal<uint32_t>                    r_dcache_llsc_key;
559    sc_signal<uint32_t>                    r_dcache_llsc_count;
560    sc_signal<bool>                        r_dcache_llsc_valid;
561
562    ////////////////////////////////
563    // Activity counters
564    ////////////////////////////////
565    uint32_t m_cpt_dcache_data_read;        // DCACHE DATA READ
566    uint32_t m_cpt_dcache_data_write;       // DCACHE DATA WRITE
567    uint32_t m_cpt_dcache_dir_read;         // DCACHE DIR READ
568    uint32_t m_cpt_dcache_dir_write;        // DCACHE DIR WRITE
569
570    uint32_t m_cpt_icache_data_read;        // ICACHE DATA READ
571    uint32_t m_cpt_icache_data_write;       // ICACHE DATA WRITE
572    uint32_t m_cpt_icache_dir_read;         // ICACHE DIR READ
573    uint32_t m_cpt_icache_dir_write;        // ICACHE DIR WRITE
574
575    uint32_t m_cpt_frz_cycles;              // number of cycles where the cpu is frozen
576    uint32_t m_cpt_total_cycles;                // total number of cycles
577
578    // Cache activity counters
579    uint32_t m_cpt_data_read;               // total number of read data
580    uint32_t m_cpt_data_write;              // total number of write data
581    uint32_t m_cpt_data_miss;               // number of read miss
582    uint32_t m_cpt_ins_miss;                // number of instruction miss
583    uint32_t m_cpt_unc_read;                // number of read uncached
584    uint32_t m_cpt_write_cached;            // number of cached write
585    uint32_t m_cpt_ins_read;                // number of instruction read
586    uint32_t m_cpt_ins_spc_miss;            // number of speculative instruction miss
587
588    uint32_t m_cost_write_frz;              // number of frozen cycles related to write buffer
589    uint32_t m_cost_data_miss_frz;          // number of frozen cycles related to data miss
590    uint32_t m_cost_unc_read_frz;           // number of frozen cycles related to uncached read
591    uint32_t m_cost_ins_miss_frz;           // number of frozen cycles related to ins miss
592
593    uint32_t m_cpt_imiss_transaction;       // number of VCI instruction miss transactions
594    uint32_t m_cpt_dmiss_transaction;       // number of VCI data miss transactions
595    uint32_t m_cpt_unc_transaction;         // number of VCI uncached read transactions
596    uint32_t m_cpt_write_transaction;       // number of VCI write transactions
597    uint32_t m_cpt_icache_unc_transaction;
598
599    uint32_t m_cost_imiss_transaction;      // cumulated duration for VCI IMISS transactions
600    uint32_t m_cost_dmiss_transaction;      // cumulated duration for VCI DMISS transactions
601    uint32_t m_cost_unc_transaction;        // cumulated duration for VCI UNC transactions
602    uint32_t m_cost_write_transaction;      // cumulated duration for VCI WRITE transactions
603    uint32_t m_cost_icache_unc_transaction; // cumulated duration for VCI IUNC transactions
604    uint32_t m_length_write_transaction;    // cumulated length for VCI WRITE transactions
605
606    // TLB activity counters
607    uint32_t m_cpt_ins_tlb_read;            // number of instruction tlb read
608    uint32_t m_cpt_ins_tlb_miss;            // number of instruction tlb miss
609    uint32_t m_cpt_ins_tlb_update_acc;      // number of instruction tlb update
610    uint32_t m_cpt_ins_tlb_occup_cache;     // number of instruction tlb occupy data cache line
611    uint32_t m_cpt_ins_tlb_hit_dcache;      // number of instruction tlb hit in data cache
612
613    uint32_t m_cpt_data_tlb_read;           // number of data tlb read
614    uint32_t m_cpt_data_tlb_miss;           // number of data tlb miss
615    uint32_t m_cpt_data_tlb_update_acc;     // number of data tlb update
616    uint32_t m_cpt_data_tlb_update_dirty;   // number of data tlb update dirty
617    uint32_t m_cpt_data_tlb_hit_dcache;     // number of data tlb hit in data cache
618    uint32_t m_cpt_data_tlb_occup_cache;    // number of data tlb occupy data cache line
619    uint32_t m_cpt_tlb_occup_dcache;
620
621    uint32_t m_cost_ins_tlb_miss_frz;       // number of frozen cycles related to instruction tlb miss
622    uint32_t m_cost_data_tlb_miss_frz;      // number of frozen cycles related to data tlb miss
623    uint32_t m_cost_ins_tlb_update_acc_frz;    // number of frozen cycles related to instruction tlb update acc
624    uint32_t m_cost_data_tlb_update_acc_frz;   // number of frozen cycles related to data tlb update acc
625    uint32_t m_cost_data_tlb_update_dirty_frz; // number of frozen cycles related to data tlb update dirty
626    uint32_t m_cost_ins_tlb_occup_cache_frz;   // number of frozen cycles related to instruction tlb miss operate in dcache
627    uint32_t m_cost_data_tlb_occup_cache_frz;  // number of frozen cycles related to data tlb miss operate in dcache
628
629    uint32_t m_cpt_itlbmiss_transaction;       // number of itlb miss transactions
630    uint32_t m_cpt_itlb_ll_transaction;        // number of itlb ll acc transactions
631    uint32_t m_cpt_itlb_sc_transaction;        // number of itlb sc acc transactions
632    uint32_t m_cpt_dtlbmiss_transaction;       // number of dtlb miss transactions
633    uint32_t m_cpt_dtlb_ll_transaction;        // number of dtlb ll acc transactions
634    uint32_t m_cpt_dtlb_sc_transaction;        // number of dtlb sc acc transactions
635    uint32_t m_cpt_dtlb_ll_dirty_transaction;  // number of dtlb ll dirty transactions
636    uint32_t m_cpt_dtlb_sc_dirty_transaction;  // number of dtlb sc dirty transactions
637
638    uint32_t m_cost_itlbmiss_transaction;       // cumulated duration for VCI instruction TLB miss transactions
639    uint32_t m_cost_itlb_ll_transaction;        // cumulated duration for VCI instruction TLB ll acc transactions
640    uint32_t m_cost_itlb_sc_transaction;        // cumulated duration for VCI instruction TLB sc acc transactions
641    uint32_t m_cost_dtlbmiss_transaction;       // cumulated duration for VCI data TLB miss transactions
642    uint32_t m_cost_dtlb_ll_transaction;        // cumulated duration for VCI data TLB ll acc transactions
643    uint32_t m_cost_dtlb_sc_transaction;        // cumulated duration for VCI data TLB sc acc transactions
644    uint32_t m_cost_dtlb_ll_dirty_transaction;  // cumulated duration for VCI data TLB ll dirty transactions
645    uint32_t m_cost_dtlb_sc_dirty_transaction;  // cumulated duration for VCI data TLB sc dirty transactions
646
647    // coherence activity counters
648    uint32_t m_cpt_cc_update_icache;            // number of coherence update instruction commands
649    uint32_t m_cpt_cc_update_dcache;            // number of coherence update data commands
650    uint32_t m_cpt_cc_inval_icache;             // number of coherence inval instruction commands
651    uint32_t m_cpt_cc_inval_dcache;             // number of coherence inval data commands
652    uint32_t m_cpt_cc_broadcast;                // number of coherence broadcast commands
653
654    uint32_t m_cost_updt_data_frz;              // number of frozen cycles related to coherence update data packets
655    uint32_t m_cost_inval_ins_frz;              // number of frozen cycles related to coherence inval instruction packets
656    uint32_t m_cost_inval_data_frz;             // number of frozen cycles related to coherence inval data packets
657    uint32_t m_cost_broadcast_frz;              // number of frozen cycles related to coherence broadcast packets
658
659    uint32_t m_cpt_cc_cleanup_ins;              // number of coherence cleanup packets
660    uint32_t m_cpt_cc_cleanup_data;             // number of coherence cleanup packets
661
662    uint32_t m_cpt_icleanup_transaction;        // number of instruction cleanup transactions
663    uint32_t m_cpt_dcleanup_transaction;        // number of instructinumber of data cleanup transactions
664    uint32_t m_cost_icleanup_transaction;       // cumulated duration for VCI instruction cleanup transactions
665    uint32_t m_cost_dcleanup_transaction;       // cumulated duration for VCI data cleanup transactions
666
667    uint32_t m_cost_ins_tlb_inval_frz;      // number of frozen cycles related to checking ins tlb invalidate
668    uint32_t m_cpt_ins_tlb_inval;           // number of ins tlb invalidate
669
670    uint32_t m_cost_data_tlb_inval_frz;     // number of frozen cycles related to checking data tlb invalidate
671    uint32_t m_cpt_data_tlb_inval;          // number of data tlb invalidate
672
673    // FSM activity counters
674    uint32_t m_cpt_fsm_icache     [64];
675    uint32_t m_cpt_fsm_dcache     [64];
676    uint32_t m_cpt_fsm_cmd        [64];
677    uint32_t m_cpt_fsm_rsp        [64];
678    uint32_t m_cpt_fsm_cc_receive [64];
679    uint32_t m_cpt_fsm_cc_send    [64];
680
681    uint32_t m_cpt_stop_simulation;             // used to stop simulation if frozen
682
683protected:
684    SC_HAS_PROCESS(VciCcVCacheWrapper);
685
686public:
687    VciCcVCacheWrapper(
688        sc_module_name insname,
689        int proc_id,
690        const soclib::common::MappingTable &mtp,
691        const soclib::common::MappingTable &mtc,
692        const soclib::common::IntTab &initiator_index_d,
693        const soclib::common::IntTab &initiator_index_c,
694        const soclib::common::IntTab &target_index_d,
695        size_t   itlb_ways,
696        size_t   itlb_sets,
697        size_t   dtlb_ways,
698        size_t   dtlb_sets,
699        size_t   icache_ways,
700        size_t   icache_sets,
701        size_t   icache_words,
702        size_t   dcache_ways,
703        size_t   dcache_sets,
704        size_t   dcache_words,
705        size_t   wbuf_nlines,
706        size_t   wbuf_nwords,
707        size_t   x_width,
708        size_t   y_width,
709        uint32_t memory_cache_local_id,
710        uint32_t max_frozen_cycles,
711        uint32_t debug_start_cycle,
712        bool     debug_ok);
713
714    ~VciCcVCacheWrapper();
715
716    void print_cpi();
717    void print_stats();
718    void clear_stats();
719    void print_trace(size_t mode = 0);
720    void cache_monitor(paddr_t addr);
721    inline void iss_set_debug_mask(uint v) {
722        r_iss.set_debug_mask(v);
723    }
724
725private:
726    void transition();
727    void genMoore();
728
729    soclib_static_assert((int)iss_t::SC_ATOMIC == (int)vci_param::STORE_COND_ATOMIC);
730    soclib_static_assert((int)iss_t::SC_NOT_ATOMIC == (int)vci_param::STORE_COND_NOT_ATOMIC);
731};
732
733}}
734
735#endif /* SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER_H */
736
737// Local Variables:
738// tab-width: 4
739// c-basic-offset: 4
740// c-file-offsets:((innamespace . 0)(inline-open . 0))
741// indent-tabs-mode: nil
742// End:
743
744// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
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