source: branches/v5/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h @ 440

Last change on this file since 440 was 440, checked in by cfuguet, 11 years ago

Merging branch/v5/vci_mem_cache with trunk modifications to
start the development of new coherence protocol modifications
in this component
File size: 40.6 KB
Line 
1/* -*- c++ -*-
2 * File         : vci_mem_cache.h
3 * Date         : 26/10/2008
4 * Copyright    : UPMC / LIP6
5 * Authors      : Alain Greiner / Eric Guthmuller
6 *
7 * SOCLIB_LGPL_HEADER_BEGIN
8 *
9 * This file is part of SoCLib, GNU LGPLv2.1.
10 *
11 * SoCLib is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU Lesser General Public License as published
13 * by the Free Software Foundation; version 2.1 of the License.
14 *
15 * SoCLib is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
18 * Lesser General Public License for more details.
19 *
20 * You should have received a copy of the GNU Lesser General Public
21 * License along with SoCLib; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
23 * 02110-1301 USA
24 *
25 * SOCLIB_LGPL_HEADER_END
26 *
27 * Maintainers: alain eric.guthmuller@polytechnique.edu
28 *              cesar.fuguet-tortolero@lip6.fr
29 *              alexandre.joannou@lip6.fr
30 */
31
32#ifndef SOCLIB_CABA_MEM_CACHE_H
33#define SOCLIB_CABA_MEM_CACHE_H
34
35#include <inttypes.h>
36#include <systemc>
37#include <list>
38#include <cassert>
39#include "arithmetics.h"
40#include "alloc_elems.h"
41#include "caba_base_module.h"
42#include "vci_target.h"
43#include "vci_initiator.h"
44#include "generic_fifo.h"
45#include "mapping_table.h"
46#include "int_tab.h"
47#include "generic_llsc_global_table.h"
48#include "mem_cache_directory.h"
49#include "xram_transaction.h"
50#include "update_tab.h"
51#include "dspin_interface.h"
52#include "dspin_dhccp_param.h"
53
54#define TRT_ENTRIES      4      // Number of entries in TRT
55#define UPT_ENTRIES      4      // Number of entries in UPT
56#define HEAP_ENTRIES     1024   // Number of entries in HEAP
57
58namespace soclib {  namespace caba {
59
60  using namespace sc_core;
61
62  template<typename vci_param_int, 
63           typename vci_param_ext,
64           size_t   dspin_in_width,
65           size_t   dspin_out_width>
66    class VciMemCache
67    : public soclib::caba::BaseModule
68    {
69      typedef typename vci_param_int::fast_addr_t  addr_t;
70
71      typedef typename sc_dt::sc_uint<64>          wide_data_t;
72
73      typedef uint32_t data_t;
74      typedef uint32_t tag_t;
75      typedef uint32_t be_t;
76      typedef uint32_t copy_t;
77
78      /* States of the TGT_CMD fsm */
79      enum tgt_cmd_fsm_state_e
80      {
81        TGT_CMD_IDLE,
82        TGT_CMD_ERROR,
83        TGT_CMD_READ,
84        TGT_CMD_WRITE,
85        TGT_CMD_CAS,
86        TGT_CMD_CONFIG
87      };
88
89      /* States of the TGT_RSP fsm */
90      enum tgt_rsp_fsm_state_e
91      {
92        TGT_RSP_CONFIG_IDLE,
93        TGT_RSP_TGT_CMD_IDLE,
94        TGT_RSP_READ_IDLE,
95        TGT_RSP_WRITE_IDLE,
96        TGT_RSP_CAS_IDLE,
97        TGT_RSP_XRAM_IDLE,
98        TGT_RSP_MULTI_ACK_IDLE,
99        TGT_RSP_CLEANUP_IDLE,
100        TGT_RSP_CONFIG,
101        TGT_RSP_TGT_CMD,
102        TGT_RSP_READ,
103        TGT_RSP_WRITE,
104        TGT_RSP_CAS,
105        TGT_RSP_XRAM,
106        TGT_RSP_MULTI_ACK,
107        TGT_RSP_CLEANUP
108      };
109
110      /* States of the DSPIN_TGT fsm */
111      enum cc_receive_fsm_state_e
112      {
113        CC_RECEIVE_IDLE,
114        CC_RECEIVE_CLEANUP,
115        CC_RECEIVE_CLEANUP_EOP,
116        CC_RECEIVE_MULTI_ACK
117      };
118
119      /* States of the CC_SEND fsm */
120      enum cc_send_fsm_state_e
121      {
122        CC_SEND_CONFIG_IDLE,
123        CC_SEND_XRAM_RSP_IDLE,
124        CC_SEND_WRITE_IDLE,
125        CC_SEND_CAS_IDLE,
126        CC_SEND_CLEANUP_IDLE,
127        CC_SEND_CONFIG_INVAL_HEADER,
128        CC_SEND_CONFIG_INVAL_NLINE,
129        CC_SEND_CONFIG_BRDCAST_HEADER,
130        CC_SEND_CONFIG_BRDCAST_NLINE,
131        CC_SEND_CLEANUP_ACK,
132        CC_SEND_XRAM_RSP_BRDCAST_HEADER,
133        CC_SEND_XRAM_RSP_BRDCAST_NLINE,
134        CC_SEND_XRAM_RSP_INVAL_HEADER,
135        CC_SEND_XRAM_RSP_INVAL_NLINE,
136        CC_SEND_WRITE_BRDCAST_HEADER,
137        CC_SEND_WRITE_BRDCAST_NLINE,
138        CC_SEND_WRITE_UPDT_HEADER,
139        CC_SEND_WRITE_UPDT_NLINE,
140        CC_SEND_WRITE_UPDT_DATA,
141        CC_SEND_CAS_BRDCAST_HEADER,
142        CC_SEND_CAS_BRDCAST_NLINE,
143        CC_SEND_CAS_UPDT_HEADER,
144        CC_SEND_CAS_UPDT_NLINE,
145        CC_SEND_CAS_UPDT_DATA,
146        CC_SEND_CAS_UPDT_DATA_HIGH
147      };
148
149      /* States of the MULTI_ACK fsm */
150      enum multi_ack_fsm_state_e
151      {
152        MULTI_ACK_IDLE,
153        MULTI_ACK_UPT_LOCK,
154        MULTI_ACK_UPT_CLEAR,
155        MULTI_ACK_WRITE_RSP,
156        MULTI_ACK_CONFIG_ACK
157      };
158
159      /* States of the CONFIG fsm */
160      enum config_fsm_state_e
161      {
162        CONFIG_IDLE,
163        CONFIG_LOOP,
164        CONFIG_RSP,
165        CONFIG_DIR_REQ,
166        CONFIG_DIR_ACCESS,
167        CONFIG_DIR_UPT_LOCK,
168        CONFIG_BC_SEND,
169        CONFIG_BC_WAIT,
170        CONFIG_INV_SEND,
171        CONFIG_HEAP_REQ,
172        CONFIG_HEAP_SCAN,
173        CONFIG_HEAP_LAST,
174        CONFIG_INV_WAIT
175      };
176
177      /* States of the READ fsm */
178      enum read_fsm_state_e
179      {
180        READ_IDLE,
181        READ_DIR_REQ,
182        READ_DIR_LOCK,
183        READ_DIR_HIT,
184        READ_HEAP_REQ,
185        READ_HEAP_LOCK,
186        READ_HEAP_WRITE,
187        READ_HEAP_ERASE,
188        READ_HEAP_LAST,
189        READ_RSP,
190        READ_TRT_LOCK,
191        READ_TRT_SET,
192        READ_TRT_REQ
193      };
194
195      /* States of the WRITE fsm */
196      enum write_fsm_state_e
197      {
198        WRITE_IDLE,
199        WRITE_NEXT,
200        WRITE_DIR_REQ,
201        WRITE_DIR_LOCK,
202        WRITE_DIR_READ,
203        WRITE_DIR_HIT,
204        WRITE_UPT_LOCK,
205        WRITE_UPT_HEAP_LOCK,
206        WRITE_UPT_REQ,
207        WRITE_UPT_NEXT,
208        WRITE_UPT_DEC,
209        WRITE_RSP,
210        WRITE_MISS_TRT_LOCK,
211        WRITE_MISS_TRT_DATA,
212        WRITE_MISS_TRT_SET,
213        WRITE_MISS_XRAM_REQ,
214        WRITE_BC_TRT_LOCK,
215        WRITE_BC_UPT_LOCK,
216        WRITE_BC_DIR_INVAL,
217        WRITE_BC_CC_SEND,
218        WRITE_BC_XRAM_REQ,
219        WRITE_WAIT
220      };
221
222      /* States of the IXR_RSP fsm */
223      enum ixr_rsp_fsm_state_e
224      {
225        IXR_RSP_IDLE,
226        IXR_RSP_ACK,
227        IXR_RSP_TRT_ERASE,
228        IXR_RSP_TRT_READ
229      };
230
231      /* States of the XRAM_RSP fsm */
232      enum xram_rsp_fsm_state_e
233      {
234        XRAM_RSP_IDLE,
235        XRAM_RSP_TRT_COPY,
236        XRAM_RSP_TRT_DIRTY,
237        XRAM_RSP_DIR_LOCK,
238        XRAM_RSP_DIR_UPDT,
239        XRAM_RSP_DIR_RSP,
240        XRAM_RSP_INVAL_LOCK,
241        XRAM_RSP_INVAL_WAIT,
242        XRAM_RSP_INVAL,
243        XRAM_RSP_WRITE_DIRTY,
244        XRAM_RSP_HEAP_REQ,
245        XRAM_RSP_HEAP_ERASE,
246        XRAM_RSP_HEAP_LAST,
247        XRAM_RSP_ERROR_ERASE,
248        XRAM_RSP_ERROR_RSP
249      };
250
251      /* States of the IXR_CMD fsm */
252      enum ixr_cmd_fsm_state_e
253      {
254        IXR_CMD_READ_IDLE,
255        IXR_CMD_WRITE_IDLE,
256        IXR_CMD_CAS_IDLE,
257        IXR_CMD_XRAM_IDLE,
258        IXR_CMD_READ,
259        IXR_CMD_WRITE,
260        IXR_CMD_CAS,
261        IXR_CMD_XRAM
262      };
263
264      /* States of the CAS fsm */
265      enum cas_fsm_state_e
266      {
267        CAS_IDLE,
268        CAS_DIR_REQ,
269        CAS_DIR_LOCK,
270        CAS_DIR_HIT_READ,
271        CAS_DIR_HIT_COMPARE,
272        CAS_DIR_HIT_WRITE,
273        CAS_UPT_LOCK,
274        CAS_UPT_HEAP_LOCK,
275        CAS_UPT_REQ,
276        CAS_UPT_NEXT,
277        CAS_BC_TRT_LOCK,
278        CAS_BC_UPT_LOCK,
279        CAS_BC_DIR_INVAL,
280        CAS_BC_CC_SEND,
281        CAS_BC_XRAM_REQ,
282        CAS_RSP_FAIL,
283        CAS_RSP_SUCCESS,
284        CAS_MISS_TRT_LOCK,
285        CAS_MISS_TRT_SET,
286        CAS_MISS_XRAM_REQ,
287        CAS_WAIT
288      };
289
290      /* States of the CLEANUP fsm */
291      enum cleanup_fsm_state_e
292      {
293        CLEANUP_IDLE,
294        CLEANUP_GET_NLINE,
295        CLEANUP_DIR_REQ,
296        CLEANUP_DIR_LOCK,
297        CLEANUP_DIR_WRITE,
298        CLEANUP_HEAP_REQ,
299        CLEANUP_HEAP_LOCK,
300        CLEANUP_HEAP_SEARCH,
301        CLEANUP_HEAP_CLEAN,
302        CLEANUP_HEAP_FREE,
303        CLEANUP_UPT_LOCK,
304        CLEANUP_UPT_DECREMENT,
305        CLEANUP_UPT_CLEAR,
306        CLEANUP_WRITE_RSP,
307        CLEANUP_CONFIG_ACK,
308        CLEANUP_SEND_CLACK
309      };
310
311      /* States of the ALLOC_DIR fsm */
312      enum alloc_dir_fsm_state_e
313      {
314        ALLOC_DIR_RESET,
315        ALLOC_DIR_CONFIG,
316        ALLOC_DIR_READ,
317        ALLOC_DIR_WRITE,
318        ALLOC_DIR_CAS,
319        ALLOC_DIR_CLEANUP,
320        ALLOC_DIR_XRAM_RSP
321      };
322
323      /* States of the ALLOC_TRT fsm */
324      enum alloc_trt_fsm_state_e
325      {
326        ALLOC_TRT_READ,
327        ALLOC_TRT_WRITE,
328        ALLOC_TRT_CAS,
329        ALLOC_TRT_XRAM_RSP,
330        ALLOC_TRT_IXR_RSP
331      };
332
333      /* States of the ALLOC_UPT fsm */
334      enum alloc_upt_fsm_state_e
335      {
336        ALLOC_UPT_CONFIG,
337        ALLOC_UPT_WRITE,
338        ALLOC_UPT_XRAM_RSP,
339        ALLOC_UPT_MULTI_ACK,
340        ALLOC_UPT_CLEANUP,
341        ALLOC_UPT_CAS
342      };
343
344      /* States of the ALLOC_HEAP fsm */
345      enum alloc_heap_fsm_state_e
346      {
347        ALLOC_HEAP_RESET,
348        ALLOC_HEAP_READ,
349        ALLOC_HEAP_WRITE,
350        ALLOC_HEAP_CAS,
351        ALLOC_HEAP_CLEANUP,
352        ALLOC_HEAP_XRAM_RSP,
353        ALLOC_HEAP_CONFIG
354      };
355
356      /* transaction type, pktid field */
357      enum transaction_type_e
358      {
359          // b3 unused
360          // b2 READ / NOT READ
361          // Si READ
362          //  b1 DATA / INS
363          //  b0 UNC / MISS
364          // Si NOT READ
365          //  b1 accÚs table llsc type SW / other
366          //  b2 WRITE/CAS/LL/SC
367          TYPE_READ_DATA_UNC          = 0x0,
368          TYPE_READ_DATA_MISS         = 0x1,
369          TYPE_READ_INS_UNC           = 0x2,
370          TYPE_READ_INS_MISS          = 0x3,
371          TYPE_WRITE                  = 0x4,
372          TYPE_CAS                    = 0x5,
373          TYPE_LL                     = 0x6,
374          TYPE_SC                     = 0x7
375      };
376
377      /* SC return values */
378      enum sc_status_type_e
379      {
380          SC_SUCCESS  =   0x00000000,
381          SC_FAIL     =   0x00000001
382      };
383
384      /* Configuration commands */
385      enum cmd_config_type_e
386      {
387          CMD_CONFIG_INVAL = 0,
388          CMD_CONFIG_SYNC  = 1
389      };
390
391      // debug variables (for each FSM)
392      bool         m_debug;
393      bool         m_debug_previous_hit;
394      size_t       m_debug_previous_count;
395
396      bool         m_monitor_ok;
397      addr_t       m_monitor_base;
398      addr_t       m_monitor_length;
399
400      // instrumentation counters
401      uint32_t     m_cpt_cycles;        // Counter of cycles
402
403      uint32_t     m_cpt_read;          // Number of READ transactions
404      uint32_t     m_cpt_read_remote;   // number of remote READ transactions
405      uint32_t     m_cpt_read_flits;    // number of flits for READs
406      uint32_t     m_cpt_read_cost;     // Number of (flits * distance) for READs
407
408      uint32_t     m_cpt_read_miss;     // Number of MISS READ
409
410      uint32_t     m_cpt_write;         // Number of WRITE transactions
411      uint32_t     m_cpt_write_remote;  // number of remote WRITE transactions
412      uint32_t     m_cpt_write_flits;   // number of flits for WRITEs
413      uint32_t     m_cpt_write_cost;    // Number of (flits * distance) for WRITEs
414
415      uint32_t     m_cpt_write_miss;    // Number of MISS WRITE
416      uint32_t     m_cpt_write_cells;   // Cumulated length for WRITE transactions
417      uint32_t     m_cpt_write_dirty;   // Cumulated length for WRITE transactions
418      uint32_t     m_cpt_update;        // Number of UPDATE transactions
419      uint32_t     m_cpt_trt_rb;        // Read blocked by a hit in trt
420      uint32_t     m_cpt_trt_full;      // Transaction blocked due to a full trt
421      uint32_t     m_cpt_update_mult;   // Number of targets for UPDATE
422      uint32_t     m_cpt_inval;         // Number of INVAL  transactions
423      uint32_t     m_cpt_inval_mult;    // Number of targets for INVAL
424      uint32_t     m_cpt_inval_brdcast; // Number of BROADCAST INVAL
425      uint32_t     m_cpt_cleanup;       // Number of CLEANUP transactions
426      uint32_t     m_cpt_ll;            // Number of LL transactions
427      uint32_t     m_cpt_sc;            // Number of SC transactions
428      uint32_t     m_cpt_cas;           // Number of CAS transactions
429
430      uint32_t     m_cpt_cleanup_cost;  // Number of (flits * distance) for CLEANUPs
431
432      uint32_t     m_cpt_update_flits;  // Number of flits for UPDATEs
433      uint32_t     m_cpt_update_cost;   // Number of (flits * distance) for UPDATEs
434
435      uint32_t     m_cpt_inval_cost;    // Number of (flits * distance) for INVALs
436
437      uint32_t     m_cpt_get;
438
439      uint32_t     m_cpt_put;
440
441      size_t       m_prev_count;
442
443      protected:
444
445      SC_HAS_PROCESS(VciMemCache);
446
447      public:
448      sc_in<bool>                                 p_clk;
449      sc_in<bool>                                 p_resetn;
450      soclib::caba::VciTarget<vci_param_int>      p_vci_tgt;
451      soclib::caba::VciInitiator<vci_param_ext>   p_vci_ixr;
452      soclib::caba::DspinInput<dspin_in_width>    p_dspin_in;
453      soclib::caba::DspinOutput<dspin_out_width>  p_dspin_out;
454
455      VciMemCache(
456          sc_module_name name,                                // Instance Name
457          const soclib::common::MappingTable &mtp,            // Mapping table INT network
458          const soclib::common::MappingTable &mtx,            // Mapping table RAM network
459          const soclib::common::IntTab       &srcid_x,        // global index RAM network
460          const soclib::common::IntTab       &tgtid_d,        // global index INT network
461          const size_t                       cc_global_id,    // global index CC network
462          const size_t                       nways,           // Number of ways per set
463          const size_t                       nsets,           // Number of sets
464          const size_t                       nwords,          // Number of words per line
465          const size_t                       max_copies,      // max number of copies
466          const size_t                       heap_size=HEAP_ENTRIES,
467          const size_t                       trt_lines=TRT_ENTRIES, 
468          const size_t                       upt_lines=UPT_ENTRIES,     
469          const size_t                       debug_start_cycle=0,
470          const bool                         debug_ok=false );
471
472      ~VciMemCache();
473
474      void print_stats();
475      void print_trace();
476      void copies_monitor(addr_t addr);
477      void start_monitor(addr_t addr, addr_t length);
478      void stop_monitor();
479
480      private:
481
482      void transition();
483      void genMoore();
484      void check_monitor( const char *buf, addr_t addr, data_t data, bool read);
485
486      // Component attributes
487      std::list<soclib::common::Segment> m_seglist;          // segments allocated
488      size_t                             m_nseg;             // number of segments
489      soclib::common::Segment            **m_seg;            // array of segments pointers
490      size_t                             m_seg_config;       // config segment index
491      const size_t                       m_srcid_x;          // global index on RAM network
492      const size_t                       m_initiators;       // Number of initiators
493      const size_t                       m_heap_size;        // Size of the heap
494      const size_t                       m_ways;             // Number of ways in a set
495      const size_t                       m_sets;             // Number of cache sets
496      const size_t                       m_words;            // Number of words in a line
497      const size_t                       m_cc_global_id;     // global_index on cc network
498      size_t                             m_debug_start_cycle;
499      bool                               m_debug_ok;
500      uint32_t                           m_trt_lines;
501      TransactionTab                     m_trt;              // xram transaction table
502      uint32_t                           m_upt_lines;
503      UpdateTab                          m_upt;              // pending update & invalidate
504      CacheDirectory                     m_cache_directory;  // data cache directory
505      CacheData                          m_cache_data;       // data array[set][way][word]
506      HeapDirectory                      m_heap;             // heap for copies
507      size_t                             m_max_copies;       // max number of copies in heap
508      GenericLLSCGlobalTable
509      < 32  ,    // number of slots
510        4096,    // number of processors in the system
511        8000,    // registration life (# of LL operations)
512        addr_t >                         m_llsc_table;       // ll/sc registration table
513
514      // adress masks
515      const soclib::common::AddressMaskingTable<addr_t>   m_x;
516      const soclib::common::AddressMaskingTable<addr_t>   m_y;
517      const soclib::common::AddressMaskingTable<addr_t>   m_z;
518      const soclib::common::AddressMaskingTable<addr_t>   m_nline;
519
520      // broadcast address
521      uint32_t                           m_broadcast_boundaries;
522
523      //////////////////////////////////////////////////
524      // Registers controlled by the TGT_CMD fsm
525      //////////////////////////////////////////////////
526
527      sc_signal<int>         r_tgt_cmd_fsm;
528
529      // Fifo between TGT_CMD fsm and READ fsm
530      GenericFifo<addr_t>    m_cmd_read_addr_fifo;
531      GenericFifo<size_t>    m_cmd_read_length_fifo;
532      GenericFifo<size_t>    m_cmd_read_srcid_fifo;
533      GenericFifo<size_t>    m_cmd_read_trdid_fifo;
534      GenericFifo<size_t>    m_cmd_read_pktid_fifo;
535
536      // Fifo between TGT_CMD fsm and WRITE fsm
537      GenericFifo<addr_t>    m_cmd_write_addr_fifo;
538      GenericFifo<bool>      m_cmd_write_eop_fifo;
539      GenericFifo<size_t>    m_cmd_write_srcid_fifo;
540      GenericFifo<size_t>    m_cmd_write_trdid_fifo;
541      GenericFifo<size_t>    m_cmd_write_pktid_fifo;
542      GenericFifo<data_t>    m_cmd_write_data_fifo;
543      GenericFifo<be_t>      m_cmd_write_be_fifo;
544
545      // Fifo between TGT_CMD fsm and CAS fsm
546      GenericFifo<addr_t>    m_cmd_cas_addr_fifo;
547      GenericFifo<bool>      m_cmd_cas_eop_fifo;
548      GenericFifo<size_t>    m_cmd_cas_srcid_fifo;
549      GenericFifo<size_t>    m_cmd_cas_trdid_fifo;
550      GenericFifo<size_t>    m_cmd_cas_pktid_fifo;
551      GenericFifo<data_t>    m_cmd_cas_wdata_fifo;
552
553      // Fifo between CC_RECEIVE fsm and CLEANUP fsm
554      GenericFifo<uint64_t>  m_cc_receive_to_cleanup_fifo;
555     
556      // Fifo between CC_RECEIVE fsm and MULTI_ACK fsm
557      GenericFifo<uint64_t>  m_cc_receive_to_multi_ack_fifo;
558
559      // Buffer between TGT_CMD fsm and TGT_RSP fsm
560      // (segmentation violation response request)
561      sc_signal<bool>     r_tgt_cmd_to_tgt_rsp_req;
562
563      sc_signal<uint32_t> r_tgt_cmd_to_tgt_rsp_rdata;
564      sc_signal<size_t>   r_tgt_cmd_to_tgt_rsp_error;
565      sc_signal<size_t>   r_tgt_cmd_to_tgt_rsp_srcid;
566      sc_signal<size_t>   r_tgt_cmd_to_tgt_rsp_trdid;
567      sc_signal<size_t>   r_tgt_cmd_to_tgt_rsp_pktid;
568
569      sc_signal<addr_t>   r_tgt_cmd_config_addr;
570      sc_signal<size_t>   r_tgt_cmd_config_cmd;
571
572      ///////////////////////////////////////////////////////
573      // Registers controlled by the CONFIG fsm
574      ///////////////////////////////////////////////////////
575
576      sc_signal<int>      r_config_fsm;            // FSM state
577      sc_signal<bool>     r_config_lock;           // lock protecting exclusive access
578      sc_signal<int>      r_config_cmd;            // config request status
579      sc_signal<addr_t>   r_config_address;        // target buffer physical address
580      sc_signal<size_t>   r_config_srcid;          // config request srcid
581      sc_signal<size_t>   r_config_trdid;          // config request trdid
582      sc_signal<size_t>   r_config_pktid;          // config request pktid
583      sc_signal<size_t>   r_config_nlines;         // number of lines covering the buffer
584      sc_signal<size_t>   r_config_dir_way;        // DIR: selected way
585      sc_signal<size_t>   r_config_dir_count;      // DIR: number of copies
586      sc_signal<bool>     r_config_dir_is_cnt;     // DIR: counter mode (broadcast required)
587      sc_signal<size_t>   r_config_dir_copy_srcid; // DIR: first copy SRCID
588      sc_signal<bool>     r_config_dir_copy_inst;  // DIR: first copy L1 type
589      sc_signal<size_t>   r_config_dir_next_ptr;   // DIR: index of next copy in HEAP
590      sc_signal<size_t>   r_config_heap_next;      // current pointer to scan HEAP
591
592      sc_signal<size_t>   r_config_upt_index;  // UPT index
593
594      // Buffer between CONFIG fsm and TGT_RSP fsm (send a done response to L1 cache)
595      sc_signal<bool>     r_config_to_tgt_rsp_req;    // valid request
596      sc_signal<bool>     r_config_to_tgt_rsp_error;  // error response
597      sc_signal<size_t>   r_config_to_tgt_rsp_srcid;  // Transaction srcid
598      sc_signal<size_t>   r_config_to_tgt_rsp_trdid;  // Transaction trdid
599      sc_signal<size_t>   r_config_to_tgt_rsp_pktid;  // Transaction pktid
600
601      // Buffer between CONFIG fsm and CC_SEND fsm (multi-inval / broadcast-inval)
602      sc_signal<bool>     r_config_to_cc_send_multi_req;    // multi-inval request
603      sc_signal<bool>     r_config_to_cc_send_brdcast_req;  // broadcast-inval request
604      sc_signal<addr_t>   r_config_to_cc_send_nline;        // line index
605      sc_signal<size_t>   r_config_to_cc_send_trdid;        // UPT index
606      GenericFifo<bool>   m_config_to_cc_send_inst_fifo;    // fifo for the L1 type
607      GenericFifo<size_t> m_config_to_cc_send_srcid_fifo;   // fifo for owners srcid
608
609#if L1_MULTI_CACHE
610      GenericFifo<size_t> m_config_to_cc_send_cache_id_fifo; // fifo for cache_id
611#endif
612
613      ///////////////////////////////////////////////////////
614      // Registers controlled by the READ fsm
615      ///////////////////////////////////////////////////////
616
617      sc_signal<int>      r_read_fsm;          // FSM state
618      sc_signal<size_t>   r_read_copy;         // Srcid of the first copy
619      sc_signal<size_t>   r_read_copy_cache;   // Srcid of the first copy
620      sc_signal<bool>     r_read_copy_inst;    // Type of the first copy
621      sc_signal<tag_t>    r_read_tag;          // cache line tag (in directory)
622      sc_signal<bool>     r_read_is_cnt;       // is_cnt bit (in directory)
623      sc_signal<bool>     r_read_lock;         // lock bit (in directory)
624      sc_signal<bool>     r_read_dirty;        // dirty bit (in directory)
625      sc_signal<size_t>   r_read_count;        // number of copies
626      sc_signal<size_t>   r_read_ptr;          // pointer to the heap
627      sc_signal<data_t> * r_read_data;         // data (one cache line)
628      sc_signal<size_t>   r_read_way;          // associative way (in cache)
629      sc_signal<size_t>   r_read_trt_index;    // Transaction Table index
630      sc_signal<size_t>   r_read_next_ptr;     // Next entry to point to
631      sc_signal<bool>     r_read_last_free;    // Last free entry
632      sc_signal<addr_t>   r_read_ll_key;       // LL key from the llsc_global_table
633
634      // Buffer between READ fsm and IXR_CMD fsm (ask a missing cache line to XRAM)
635      sc_signal<bool>     r_read_to_ixr_cmd_req;    // valid request
636      sc_signal<addr_t>   r_read_to_ixr_cmd_nline;  // cache line index
637      sc_signal<size_t>   r_read_to_ixr_cmd_trdid;  // index in Transaction Table
638
639      // Buffer between READ fsm and TGT_RSP fsm (send a hit read response to L1 cache)
640      sc_signal<bool>     r_read_to_tgt_rsp_req;    // valid request
641      sc_signal<size_t>   r_read_to_tgt_rsp_srcid;  // Transaction srcid
642      sc_signal<size_t>   r_read_to_tgt_rsp_trdid;  // Transaction trdid
643      sc_signal<size_t>   r_read_to_tgt_rsp_pktid;  // Transaction pktid
644      sc_signal<data_t> * r_read_to_tgt_rsp_data;   // data (one cache line)
645      sc_signal<size_t>   r_read_to_tgt_rsp_word;   // first word of the response
646      sc_signal<size_t>   r_read_to_tgt_rsp_length; // length of the response
647      sc_signal<addr_t>   r_read_to_tgt_rsp_ll_key; // LL key from the llsc_global_table
648
649      ///////////////////////////////////////////////////////////////
650      // Registers controlled by the WRITE fsm
651      ///////////////////////////////////////////////////////////////
652
653      sc_signal<int>      r_write_fsm;        // FSM state
654      sc_signal<addr_t>   r_write_address;    // first word address
655      sc_signal<size_t>   r_write_word_index; // first word index in line
656      sc_signal<size_t>   r_write_word_count; // number of words in line
657      sc_signal<size_t>   r_write_srcid;      // transaction srcid
658      sc_signal<size_t>   r_write_trdid;      // transaction trdid
659      sc_signal<size_t>   r_write_pktid;      // transaction pktid
660      sc_signal<data_t> * r_write_data;       // data (one cache line)
661      sc_signal<be_t>   * r_write_be;         // one byte enable per word
662      sc_signal<bool>     r_write_byte;       // (BE != 0X0) and (BE != 0xF)
663      sc_signal<bool>     r_write_is_cnt;     // is_cnt bit (in directory)
664      sc_signal<bool>     r_write_lock;       // lock bit (in directory)
665      sc_signal<tag_t>    r_write_tag;        // cache line tag (in directory)
666      sc_signal<size_t>   r_write_copy;       // first owner of the line
667      sc_signal<size_t>   r_write_copy_cache; // first owner of the line
668      sc_signal<bool>     r_write_copy_inst;  // is this owner a ICache ?
669      sc_signal<size_t>   r_write_count;      // number of copies
670      sc_signal<size_t>   r_write_ptr;        // pointer to the heap
671      sc_signal<size_t>   r_write_next_ptr;   // next pointer to the heap
672      sc_signal<bool>     r_write_to_dec;     // need to decrement update counter
673      sc_signal<size_t>   r_write_way;        // way of the line
674      sc_signal<size_t>   r_write_trt_index;  // index in Transaction Table
675      sc_signal<size_t>   r_write_upt_index;  // index in Update Table
676      sc_signal<bool>     r_write_sc_fail;    // sc command failed
677      sc_signal<bool>     r_write_pending_sc; // sc command pending
678
679      // Buffer between WRITE fsm and TGT_RSP fsm (acknowledge a write command from L1)
680      sc_signal<bool>     r_write_to_tgt_rsp_req;     // valid request
681      sc_signal<size_t>   r_write_to_tgt_rsp_srcid;   // transaction srcid
682      sc_signal<size_t>   r_write_to_tgt_rsp_trdid;   // transaction trdid
683      sc_signal<size_t>   r_write_to_tgt_rsp_pktid;   // transaction pktid
684      sc_signal<bool>     r_write_to_tgt_rsp_sc_fail; // sc command failed
685
686      // Buffer between WRITE fsm and IXR_CMD fsm (ask a missing cache line to XRAM)
687      sc_signal<bool>     r_write_to_ixr_cmd_req;   // valid request
688      sc_signal<bool>     r_write_to_ixr_cmd_write; // write request
689      sc_signal<addr_t>   r_write_to_ixr_cmd_nline; // cache line index
690      sc_signal<data_t> * r_write_to_ixr_cmd_data;  // cache line data
691      sc_signal<size_t>   r_write_to_ixr_cmd_trdid; // index in Transaction Table
692
693      // Buffer between WRITE fsm and CC_SEND fsm (Update/Invalidate L1 caches)
694      sc_signal<bool>     r_write_to_cc_send_multi_req;     // valid multicast request
695      sc_signal<bool>     r_write_to_cc_send_brdcast_req;   // valid brdcast request
696      sc_signal<addr_t>   r_write_to_cc_send_nline;         // cache line index
697      sc_signal<size_t>   r_write_to_cc_send_trdid;         // index in Update Table
698      sc_signal<data_t> * r_write_to_cc_send_data;          // data (one cache line)
699      sc_signal<be_t>   * r_write_to_cc_send_be;            // word enable
700      sc_signal<size_t>   r_write_to_cc_send_count;         // number of words in line
701      sc_signal<size_t>   r_write_to_cc_send_index;         // index of first word in line
702      GenericFifo<bool>   m_write_to_cc_send_inst_fifo;     // fifo for the L1 type
703      GenericFifo<size_t> m_write_to_cc_send_srcid_fifo;    // fifo for srcids
704
705#if L1_MULTI_CACHE
706      GenericFifo<size_t> m_write_to_cc_send_cache_id_fifo; // fifo for srcids
707#endif
708
709      // Buffer between WRITE fsm and MULTI_ACK fsm (Decrement UPT entry)
710      sc_signal<bool>     r_write_to_multi_ack_req;       // valid request
711      sc_signal<size_t>   r_write_to_multi_ack_upt_index; // index in update table
712
713      /////////////////////////////////////////////////////////
714      // Registers controlled by MULTI_ACK fsm
715      //////////////////////////////////////////////////////////
716
717      sc_signal<int>      r_multi_ack_fsm;       // FSM state
718      sc_signal<size_t>   r_multi_ack_upt_index; // index in the Update Table
719      sc_signal<size_t>   r_multi_ack_srcid;     // pending write srcid
720      sc_signal<size_t>   r_multi_ack_trdid;     // pending write trdid
721      sc_signal<size_t>   r_multi_ack_pktid;     // pending write pktid
722      sc_signal<addr_t>   r_multi_ack_nline;     // pending write nline
723
724      // signaling completion of multi-inval to CONFIG fsm
725      sc_signal<bool>     r_multi_ack_to_config_ack; 
726
727      // Buffer between MULTI_ACK fsm and TGT_RSP fsm (complete write/update transaction)
728      sc_signal<bool>     r_multi_ack_to_tgt_rsp_req;   // valid request
729      sc_signal<size_t>   r_multi_ack_to_tgt_rsp_srcid; // Transaction srcid
730      sc_signal<size_t>   r_multi_ack_to_tgt_rsp_trdid; // Transaction trdid
731      sc_signal<size_t>   r_multi_ack_to_tgt_rsp_pktid; // Transaction pktid
732
733      ///////////////////////////////////////////////////////
734      // Registers controlled by CLEANUP fsm
735      ///////////////////////////////////////////////////////
736
737      sc_signal<int>      r_cleanup_fsm;           // FSM state
738      sc_signal<size_t>   r_cleanup_srcid;         // transaction srcid
739      sc_signal<bool>     r_cleanup_inst;          // Instruction or Data ?
740      sc_signal<size_t>   r_cleanup_way_index;     // L1 Cache Way index
741      sc_signal<addr_t>   r_cleanup_nline;         // cache line index
742
743#if L1_MULTI_CACHE
744      sc_signal<size_t>   r_cleanup_pktid;         // transaction pktid
745#endif
746
747      sc_signal<copy_t>   r_cleanup_copy;          // first copy
748      sc_signal<copy_t>   r_cleanup_copy_cache;    // first copy
749      sc_signal<size_t>   r_cleanup_copy_inst;     // type of the first copy
750      sc_signal<copy_t>   r_cleanup_count;         // number of copies
751      sc_signal<size_t>   r_cleanup_ptr;           // pointer to the heap
752      sc_signal<size_t>   r_cleanup_prev_ptr;      // previous pointer to the heap
753      sc_signal<size_t>   r_cleanup_prev_srcid;    // srcid of previous heap entry
754      sc_signal<size_t>   r_cleanup_prev_cache_id; // srcid of previous heap entry
755      sc_signal<bool>     r_cleanup_prev_inst;     // inst bit of previous heap entry
756      sc_signal<size_t>   r_cleanup_next_ptr;      // next pointer to the heap
757      sc_signal<tag_t>    r_cleanup_tag;           // cache line tag (in directory)
758      sc_signal<bool>     r_cleanup_is_cnt;        // inst bit (in directory)
759      sc_signal<bool>     r_cleanup_lock;          // lock bit (in directory)
760      sc_signal<bool>     r_cleanup_dirty;         // dirty bit (in directory)
761      sc_signal<size_t>   r_cleanup_way;           // associative way (in cache)
762
763      sc_signal<size_t>   r_cleanup_write_srcid;   // srcid of write rsp
764      sc_signal<size_t>   r_cleanup_write_trdid;   // trdid of write rsp
765      sc_signal<size_t>   r_cleanup_write_pktid;   // pktid of write rsp
766
767      sc_signal<bool>     r_cleanup_need_rsp;      // write response required
768      sc_signal<bool>     r_cleanup_need_ack;      // config acknowledge required
769
770      sc_signal<size_t>   r_cleanup_index;         // index of the INVAL line (in the UPT)
771
772      // signaling completion of broadcast-inval to CONFIG fsm
773      sc_signal<bool>     r_cleanup_to_config_ack; 
774       
775      // Buffer between CLEANUP fsm and TGT_RSP fsm (acknowledge a write command from L1)
776      sc_signal<bool>     r_cleanup_to_tgt_rsp_req;   // valid request
777      sc_signal<size_t>   r_cleanup_to_tgt_rsp_srcid; // transaction srcid
778      sc_signal<size_t>   r_cleanup_to_tgt_rsp_trdid; // transaction trdid
779      sc_signal<size_t>   r_cleanup_to_tgt_rsp_pktid; // transaction pktid
780
781      // Buffer between CLEANUP fsm and CC_SEND fsm (acknowledge a cleanup command from L1)
782      sc_signal<bool>     r_cleanup_to_cc_send_req;       // valid request
783      sc_signal<size_t>   r_cleanup_to_cc_send_srcid;     // L1 srcid
784      sc_signal<size_t>   r_cleanup_to_cc_send_set_index; // L1 set index
785      sc_signal<size_t>   r_cleanup_to_cc_send_way_index; // L1 way index
786      sc_signal<bool>     r_cleanup_to_cc_send_inst;      // Instruction Cleanup Ack
787
788      ///////////////////////////////////////////////////////
789      // Registers controlled by CAS fsm
790      ///////////////////////////////////////////////////////
791
792      sc_signal<int>      r_cas_fsm;        // FSM state
793      sc_signal<data_t>   r_cas_wdata;      // write data word
794      sc_signal<data_t> * r_cas_rdata;      // read data word
795      sc_signal<uint32_t> r_cas_lfsr;       // lfsr for random introducing
796      sc_signal<size_t>   r_cas_cpt;        // size of command
797      sc_signal<copy_t>   r_cas_copy;       // Srcid of the first copy
798      sc_signal<copy_t>   r_cas_copy_cache; // Srcid of the first copy
799      sc_signal<bool>     r_cas_copy_inst;  // Type of the first copy
800      sc_signal<size_t>   r_cas_count;      // number of copies
801      sc_signal<size_t>   r_cas_ptr;        // pointer to the heap
802      sc_signal<size_t>   r_cas_next_ptr;   // next pointer to the heap
803      sc_signal<bool>     r_cas_is_cnt;     // is_cnt bit (in directory)
804      sc_signal<bool>     r_cas_dirty;      // dirty bit (in directory)
805      sc_signal<size_t>   r_cas_way;        // way in directory
806      sc_signal<size_t>   r_cas_set;        // set in directory
807      sc_signal<data_t>   r_cas_tag;        // cache line tag (in directory)
808      sc_signal<size_t>   r_cas_trt_index;  // Transaction Table index
809      sc_signal<size_t>   r_cas_upt_index;  // Update Table index
810      sc_signal<data_t> * r_cas_data;       // cache line data
811
812      // Buffer between CAS fsm and IXR_CMD fsm (XRAM write)
813      sc_signal<bool>     r_cas_to_ixr_cmd_req;   // valid request
814      sc_signal<addr_t>   r_cas_to_ixr_cmd_nline; // cache line index
815      sc_signal<size_t>   r_cas_to_ixr_cmd_trdid; // index in Transaction Table
816      sc_signal<bool>     r_cas_to_ixr_cmd_write; // write request
817      sc_signal<data_t> * r_cas_to_ixr_cmd_data;  // cache line data
818
819
820      // Buffer between CAS fsm and TGT_RSP fsm
821      sc_signal<bool>     r_cas_to_tgt_rsp_req;   // valid request
822      sc_signal<data_t>   r_cas_to_tgt_rsp_data;  // read data word
823      sc_signal<size_t>   r_cas_to_tgt_rsp_srcid; // Transaction srcid
824      sc_signal<size_t>   r_cas_to_tgt_rsp_trdid; // Transaction trdid
825      sc_signal<size_t>   r_cas_to_tgt_rsp_pktid; // Transaction pktid
826
827      // Buffer between CAS fsm and CC_SEND fsm (Update/Invalidate L1 caches)
828      sc_signal<bool>     r_cas_to_cc_send_multi_req;     // valid request
829      sc_signal<bool>     r_cas_to_cc_send_brdcast_req;   // brdcast request
830      sc_signal<addr_t>   r_cas_to_cc_send_nline;         // cache line index
831      sc_signal<size_t>   r_cas_to_cc_send_trdid;         // index in Update Table
832      sc_signal<data_t>   r_cas_to_cc_send_wdata;         // data (one word)
833      sc_signal<bool>     r_cas_to_cc_send_is_long;       // it is a 64 bits CAS
834      sc_signal<data_t>   r_cas_to_cc_send_wdata_high;    // data high (one word)
835      sc_signal<size_t>   r_cas_to_cc_send_index;         // index of the word in line
836      GenericFifo<bool>   m_cas_to_cc_send_inst_fifo;     // fifo for the L1 type
837      GenericFifo<size_t> m_cas_to_cc_send_srcid_fifo;    // fifo for srcids
838
839#if L1_MULTI_CACHE
840      GenericFifo<size_t> m_cas_to_cc_send_cache_id_fifo; // fifo for srcids
841#endif
842
843      ////////////////////////////////////////////////////
844      // Registers controlled by the IXR_RSP fsm
845      ////////////////////////////////////////////////////
846
847      sc_signal<int>      r_ixr_rsp_fsm;       // FSM state
848      sc_signal<size_t>   r_ixr_rsp_trt_index; // TRT entry index
849      sc_signal<size_t>   r_ixr_rsp_cpt;       // word counter
850
851      // Buffer between IXR_RSP fsm and XRAM_RSP fsm  (response from the XRAM)
852      sc_signal<bool>   * r_ixr_rsp_to_xram_rsp_rok; // A xram response is ready
853
854      ////////////////////////////////////////////////////
855      // Registers controlled by the XRAM_RSP fsm
856      ////////////////////////////////////////////////////
857
858      sc_signal<int>      r_xram_rsp_fsm;               // FSM state
859      sc_signal<size_t>   r_xram_rsp_trt_index;         // TRT entry index
860      TransactionTabEntry r_xram_rsp_trt_buf;           // TRT entry local buffer
861      sc_signal<bool>     r_xram_rsp_victim_inval;      // victim line invalidate
862      sc_signal<bool>     r_xram_rsp_victim_is_cnt;     // victim line inst bit
863      sc_signal<bool>     r_xram_rsp_victim_dirty;      // victim line dirty bit
864      sc_signal<size_t>   r_xram_rsp_victim_way;        // victim line way
865      sc_signal<size_t>   r_xram_rsp_victim_set;        // victim line set
866      sc_signal<addr_t>   r_xram_rsp_victim_nline;      // victim line index
867      sc_signal<copy_t>   r_xram_rsp_victim_copy;       // victim line first copy
868      sc_signal<copy_t>   r_xram_rsp_victim_copy_cache; // victim line first copy
869      sc_signal<bool>     r_xram_rsp_victim_copy_inst;  // victim line type of first copy
870      sc_signal<size_t>   r_xram_rsp_victim_count;      // victim line number of copies
871      sc_signal<size_t>   r_xram_rsp_victim_ptr;        // victim line pointer to the heap
872      sc_signal<data_t> * r_xram_rsp_victim_data;       // victim line data
873      sc_signal<size_t>   r_xram_rsp_upt_index;         // UPT entry index
874      sc_signal<size_t>   r_xram_rsp_next_ptr;          // Next pointer to the heap
875
876      // Buffer between XRAM_RSP fsm and TGT_RSP fsm  (response to L1 cache)
877      sc_signal<bool>     r_xram_rsp_to_tgt_rsp_req;    // Valid request
878      sc_signal<size_t>   r_xram_rsp_to_tgt_rsp_srcid;  // Transaction srcid
879      sc_signal<size_t>   r_xram_rsp_to_tgt_rsp_trdid;  // Transaction trdid
880      sc_signal<size_t>   r_xram_rsp_to_tgt_rsp_pktid;  // Transaction pktid
881      sc_signal<data_t> * r_xram_rsp_to_tgt_rsp_data;   // data (one cache line)
882      sc_signal<size_t>   r_xram_rsp_to_tgt_rsp_word;   // first word index
883      sc_signal<size_t>   r_xram_rsp_to_tgt_rsp_length; // length of the response
884      sc_signal<bool>     r_xram_rsp_to_tgt_rsp_rerror; // send error to requester
885      sc_signal<addr_t>   r_xram_rsp_to_tgt_rsp_ll_key; // LL key from llsc_global_table
886
887      // Buffer between XRAM_RSP fsm and CC_SEND fsm (Inval L1 Caches)
888      sc_signal<bool>     r_xram_rsp_to_cc_send_multi_req;     // Valid request
889      sc_signal<bool>     r_xram_rsp_to_cc_send_brdcast_req;   // Broadcast request
890      sc_signal<addr_t>   r_xram_rsp_to_cc_send_nline;         // cache line index;
891      sc_signal<size_t>   r_xram_rsp_to_cc_send_trdid;         // index of UPT entry
892      GenericFifo<bool>   m_xram_rsp_to_cc_send_inst_fifo;     // fifo for the L1 type
893      GenericFifo<size_t> m_xram_rsp_to_cc_send_srcid_fifo;    // fifo for srcids
894
895#if L1_MULTI_CACHE
896      GenericFifo<size_t> m_xram_rsp_to_cc_send_cache_id_fifo; // fifo for srcids
897#endif
898
899      // Buffer between XRAM_RSP fsm and IXR_CMD fsm (XRAM write)
900      sc_signal<bool>     r_xram_rsp_to_ixr_cmd_req;   // Valid request
901      sc_signal<addr_t>   r_xram_rsp_to_ixr_cmd_nline; // cache line index
902      sc_signal<data_t> * r_xram_rsp_to_ixr_cmd_data;  // cache line data
903      sc_signal<size_t>   r_xram_rsp_to_ixr_cmd_trdid; // index in transaction table
904
905      ////////////////////////////////////////////////////
906      // Registers controlled by the IXR_CMD fsm
907      ////////////////////////////////////////////////////
908
909      sc_signal<int>      r_ixr_cmd_fsm;
910      sc_signal<size_t>   r_ixr_cmd_cpt;
911
912      ////////////////////////////////////////////////////
913      // Registers controlled by TGT_RSP fsm
914      ////////////////////////////////////////////////////
915
916      sc_signal<int>      r_tgt_rsp_fsm;
917      sc_signal<size_t>   r_tgt_rsp_cpt;
918      sc_signal<bool>     r_tgt_rsp_key_sent;
919
920      ////////////////////////////////////////////////////
921      // Registers controlled by CC_SEND fsm
922      ////////////////////////////////////////////////////
923
924      sc_signal<int>      r_cc_send_fsm;
925      sc_signal<size_t>   r_cc_send_cpt;
926      sc_signal<bool>     r_cc_send_inst;
927
928      ////////////////////////////////////////////////////
929      // Registers controlled by CC_RECEIVE fsm
930      ////////////////////////////////////////////////////
931
932      sc_signal<int>      r_cc_receive_fsm;
933
934      ////////////////////////////////////////////////////
935      // Registers controlled by ALLOC_DIR fsm
936      ////////////////////////////////////////////////////
937
938      sc_signal<int>      r_alloc_dir_fsm;
939      sc_signal<unsigned> r_alloc_dir_reset_cpt;
940
941      ////////////////////////////////////////////////////
942      // Registers controlled by ALLOC_TRT fsm
943      ////////////////////////////////////////////////////
944
945      sc_signal<int>      r_alloc_trt_fsm;
946
947      ////////////////////////////////////////////////////
948      // Registers controlled by ALLOC_UPT fsm
949      ////////////////////////////////////////////////////
950
951      sc_signal<int>      r_alloc_upt_fsm;
952
953      ////////////////////////////////////////////////////
954      // Registers controlled by ALLOC_HEAP fsm
955      ////////////////////////////////////////////////////
956
957      sc_signal<int>      r_alloc_heap_fsm;
958      sc_signal<unsigned> r_alloc_heap_reset_cpt;
959    }; // end class VciMemCache
960
961}}
962
963#endif
964
965// Local Variables:
966// tab-width: 2
967// c-basic-offset: 2
968// c-file-offsets:((innamespace . 0)(inline-open . 0))
969// indent-tabs-mode: nil
970// End:
971
972// vim: filetype=cpp:expandtab:shiftwidth=2:tabstop=2:softtabstop=2
973
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