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source: branches/wt_ideal/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp @ 920

Last change on this file since 920 was 920, checked in by meunier, 9 years ago
Adding branch wt_ideal -- "ideal" write-through
File size: 170.9 KB

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1	/* -- c++ --
2	* File : vci_cc_vcache_wrapper.cpp
3	* Copyright (c) UPMC, Lip6, SoC
4	* Authors : Alain GREINER, Yang GAO
5	*
6	* SOCLIB_LGPL_HEADER_BEGIN
7	*
8	* This file is part of SoCLib, GNU LGPLv2.1.
9	*
10	* SoCLib is free software; you can redistribute it and/or modify it
11	* under the terms of the GNU Lesser General Public License as published
12	* by the Free Software Foundation; version 2.1 of the License.
13	*
14	* SoCLib is distributed in the hope that it will be useful, but
15	* WITHOUT ANY WARRANTY; without even the implied warranty of
16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17	* Lesser General Public License for more details.
18	*
19	* You should have received a copy of the GNU Lesser General Public
20	* License along with SoCLib; if not, write to the Free Software
21	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
22	* 02110-1301 USA
23	*
24	* SOCLIB_LGPL_HEADER_END
25	*
26	* Maintainers: cesar.fuguet-tortolero@lip6.fr
27	* alexandre.joannou@lip6.fr
28	*/
29
30	#include <cassert>
31	#include <signal.h>
32
33	#include "arithmetics.h"
34	#include "../include/vci_cc_vcache_wrapper.h"
35
36	#define DEBUG_DCACHE 1
37	#define DEBUG_ICACHE 1
38	#define DEBUG_CMD 0
39
40	namespace soclib {
41	namespace caba {
42
43	namespace {
44	const char * icache_fsm_state_str[] = {
45	"ICACHE_IDLE",
46
47	"ICACHE_XTN_TLB_FLUSH",
48	"ICACHE_XTN_CACHE_FLUSH",
49	"ICACHE_XTN_CACHE_FLUSH_GO",
50	"ICACHE_XTN_TLB_INVAL",
51	"ICACHE_XTN_CACHE_INVAL_VA",
52	"ICACHE_XTN_CACHE_INVAL_PA",
53	"ICACHE_XTN_CACHE_INVAL_GO",
54
55	"ICACHE_TLB_WAIT",
56
57	"ICACHE_MISS_SELECT",
58	"ICACHE_MISS_CLEAN",
59	"ICACHE_MISS_WAIT",
60	"ICACHE_MISS_DATA_UPDT",
61	"ICACHE_MISS_DIR_UPDT",
62
63	"ICACHE_UNC_WAIT",
64	};
65
66	const char * dcache_fsm_state_str[] = {
67	"DCACHE_IDLE",
68
69	"DCACHE_TLB_MISS",
70	"DCACHE_TLB_PTE1_GET",
71	"DCACHE_TLB_PTE1_SELECT",
72	"DCACHE_TLB_PTE1_UPDT",
73	"DCACHE_TLB_PTE2_GET",
74	"DCACHE_TLB_PTE2_SELECT",
75	"DCACHE_TLB_PTE2_UPDT",
76	"DCACHE_TLB_LR_UPDT",
77	"DCACHE_TLB_LR_WAIT",
78	"DCACHE_TLB_RETURN",
79
80	"DCACHE_XTN_SWITCH",
81	"DCACHE_XTN_SYNC",
82	"DCACHE_XTN_IC_INVAL_VA",
83	"DCACHE_XTN_IC_FLUSH",
84	"DCACHE_XTN_IC_INVAL_PA",
85	"DCACHE_XTN_IC_PADDR_EXT",
86	"DCACHE_XTN_IT_INVAL",
87	"DCACHE_XTN_DC_FLUSH",
88	"DCACHE_XTN_DC_FLUSH_GO",
89	"DCACHE_XTN_DC_INVAL_VA",
90	"DCACHE_XTN_DC_INVAL_PA",
91	"DCACHE_XTN_DC_INVAL_END",
92	"DCACHE_XTN_DC_INVAL_GO",
93	"DCACHE_XTN_DT_INVAL",
94
95	"DCACHE_DIRTY_GET_PTE",
96	"DCACHE_DIRTY_WAIT",
97
98	"DCACHE_MISS_SELECT",
99	"DCACHE_MISS_VICTIM_CHECK",
100	"DCACHE_MISS_WAIT",
101	"DCACHE_MISS_DATA_UPDT",
102	"DCACHE_MISS_DIR_UPDT",
103
104	"DCACHE_UNC_WAIT",
105	"DCACHE_LL_WAIT",
106	"DCACHE_SC_WAIT",
107
108	"DCACHE_INVAL_TLB_SCAN",
109	};
110
111	const char * cmd_fsm_state_str[] = {
112	"CMD_IDLE",
113	"CMD_INS_MISS",
114	"CMD_INS_UNC",
115	"CMD_DATA_MISS",
116	"CMD_DATA_UNC_READ",
117	"CMD_DATA_UNC_WRITE",
118	"CMD_DATA_WRITE",
119	"CMD_DATA_LL",
120	"CMD_DATA_SC",
121	"CMD_DATA_CAS",
122	};
123
124	const char * vci_pktid_type_str[] = {
125	"TYPE_DATA_UNC",
126	"TYPE_READ_DATA_MISS",
127	"TYPE_READ_INS_UNC",
128	"TYPE_READ_INS_MISS",
129	"TYPE_WRITE",
130	"TYPE_CAS",
131	"TYPE_LL",
132	"TYPE_SC",
133	};
134
135	const char * vci_cmd_type_str[] = {
136	"NOP or STORE_COND",
137	"READ",
138	"WRITE",
139	"LOCKED_READ"
140	};
141
142	const char * rsp_fsm_state_str[] = {
143	"RSP_IDLE",
144	"RSP_INS_MISS",
145	"RSP_INS_UNC",
146	"RSP_DATA_MISS",
147	"RSP_DATA_UNC",
148	"RSP_DATA_LL",
149	"RSP_DATA_WRITE",
150	};
151
152	}
153
154	#define tmpl(...) \
155	template<typename vci_param, \
156	size_t dspin_in_width, \
157	size_t dspin_out_width, \
158	typename iss_t> __VA_ARGS__ \
159	VciCcVCacheWrapper<vci_param, dspin_in_width, dspin_out_width, iss_t>
160
161	using namespace soclib::common;
162
163	/////////////////////////////////
164	tmpl(/**/)::VciCcVCacheWrapper(
165	sc_module_name name,
166	const int proc_id,
167	const MappingTable &mtd,
168	const IntTab &srcid,
169	const size_t cc_global_id,
170	const size_t itlb_ways,
171	const size_t itlb_sets,
172	const size_t dtlb_ways,
173	const size_t dtlb_sets,
174	const size_t icache_ways,
175	const size_t icache_sets,
176	const size_t icache_words,
177	const size_t dcache_ways,
178	const size_t dcache_sets,
179	const size_t dcache_words,
180	const size_t wbuf_nlines,
181	const size_t wbuf_nwords,
182	const size_t x_width,
183	const size_t y_width,
184	const uint32_t max_frozen_cycles,
185	const uint32_t debug_start_cycle,
186	const bool debug_ok)
187	: soclib::caba::BaseModule(name),
188
189	p_clk("p_clk"),
190	p_resetn("p_resetn"),
191	p_vci("p_vci"),
192	p_dspin_m2p("p_dspin_m2p"),
193	p_dspin_p2m("p_dspin_p2m"),
194	p_dspin_clack("p_dspin_clack"),
195
196	m_cacheability_table( mtd.getCacheabilityTable()),
197	m_srcid(mtd.indexForId(srcid)),
198	m_cc_global_id(cc_global_id),
199	m_nline_width(vci_param::N - (uint32_log2(dcache_words)) - 2),
200	m_itlb_ways(itlb_ways),
201	m_itlb_sets(itlb_sets),
202	m_dtlb_ways(dtlb_ways),
203	m_dtlb_sets(dtlb_sets),
204	m_icache_ways(icache_ways),
205	m_icache_sets(icache_sets),
206	m_icache_yzmask((~0) << (uint32_log2(icache_words) + 2)),
207	m_icache_words(icache_words),
208	m_dcache_ways(dcache_ways),
209	m_dcache_sets(dcache_sets),
210	m_dcache_yzmask((~0) << (uint32_log2(dcache_words) + 2)),
211	m_dcache_words(dcache_words),
212	m_x_width(x_width),
213	m_y_width(y_width),
214	m_proc_id(proc_id),
215	m_max_frozen_cycles(max_frozen_cycles),
216	m_paddr_nbits(vci_param::N),
217	m_debug_start_cycle(debug_start_cycle),
218	m_debug_ok(debug_ok),
219	m_dcache_paddr_ext_reset(0),
220	m_icache_paddr_ext_reset(0),
221
222	r_mmu_ptpr("r_mmu_ptpr"),
223	r_mmu_mode("r_mmu_mode"),
224	r_mmu_word_lo("r_mmu_word_lo"),
225	r_mmu_word_hi("r_mmu_word_hi"),
226	r_mmu_ibvar("r_mmu_ibvar"),
227	r_mmu_dbvar("r_mmu_dbvar"),
228	r_mmu_ietr("r_mmu_ietr"),
229	r_mmu_detr("r_mmu_detr"),
230
231	r_icache_fsm("r_icache_fsm"),
232	r_icache_fsm_save("r_icache_fsm_save"),
233	r_icache_vci_paddr("r_icache_vci_paddr"),
234	r_icache_vaddr_save("r_icache_vaddr_save"),
235
236	r_icache_miss_way("r_icache_miss_way"),
237	r_icache_miss_set("r_icache_miss_set"),
238	r_icache_miss_word("r_icache_miss_word"),
239	r_icache_miss_clack("r_icache_miss_clack"),
240
241	r_icache_flush_count("r_icache_flush_count"),
242
243	r_icache_miss_req("r_icache_miss_req"),
244	r_icache_unc_req("r_icache_unc_req"),
245
246	r_icache_tlb_miss_req("r_icache_tlb_read_req"),
247	r_icache_tlb_rsp_error("r_icache_tlb_rsp_error"),
248
249	r_dcache_fsm("r_dcache_fsm"),
250	r_dcache_fsm_scan_save("r_dcache_fsm_scan_save"),
251
252	r_dcache_wbuf_req("r_dcache_wbuf_req"),
253	r_dcache_updt_req("r_dcache_updt_req"),
254	r_dcache_save_vaddr("r_dcache_save_vaddr"),
255	r_dcache_save_wdata("r_dcache_save_wdata"),
256	r_dcache_save_be("r_dcache_save_be"),
257	r_dcache_save_paddr("r_dcache_save_paddr"),
258	r_dcache_save_cache_way("r_dcache_save_cache_way"),
259	r_dcache_save_cache_set("r_dcache_save_cache_set"),
260	r_dcache_save_cache_word("r_dcache_save_cache_word"),
261
262	r_dcache_dirty_paddr("r_dcache_dirty_paddr"),
263	r_dcache_dirty_way("r_dcache_dirty_way"),
264	r_dcache_dirty_set("r_dcache_dirty_set"),
265
266	r_dcache_vci_paddr("r_dcache_vci_paddr"),
267	r_dcache_vci_wdata("r_dcache_vci_wdata"),
268	r_dcache_vci_miss_req("r_dcache_vci_miss_req"),
269	r_dcache_vci_unc_req("r_dcache_vci_unc_req"),
270	r_dcache_vci_unc_be("r_dcache_vci_unc_be"),
271	r_dcache_vci_unc_write("r_dcache_vci_unc_write"),
272	r_dcache_vci_cas_req("r_dcache_vci_cas_req"),
273	r_dcache_vci_cas_old("r_dcache_vci_cas_old"),
274	r_dcache_vci_cas_new("r_dcache_vci_cas_new"),
275	r_dcache_vci_ll_req("r_dcache_vci_ll_req"),
276	r_dcache_vci_sc_req("r_dcache_vci_sc_req"),
277	r_dcache_vci_sc_data("r_dcache_vci_sc_data"),
278
279	r_dcache_xtn_way("r_dcache_xtn_way"),
280	r_dcache_xtn_set("r_dcache_xtn_set"),
281
282	r_dcache_miss_type("r_dcache_miss_type"),
283	r_dcache_miss_word("r_dcache_miss_word"),
284	r_dcache_miss_way("r_dcache_miss_way"),
285	r_dcache_miss_set("r_dcache_miss_set"),
286	r_dcache_miss_victim("r_dcache_miss_victim"),
287
288	r_dcache_flush_count("r_dcache_flush_count"),
289
290	r_dcache_ll_rsp_count("r_dcache_ll_rsp_count"),
291
292	r_dcache_tlb_vaddr("r_dcache_tlb_vaddr"),
293	r_dcache_tlb_ins("r_dcache_tlb_ins"),
294	r_dcache_tlb_pte_flags("r_dcache_tlb_pte_flags"),
295	r_dcache_tlb_pte_ppn("r_dcache_tlb_pte_ppn"),
296	r_dcache_tlb_cache_way("r_dcache_tlb_cache_way"),
297	r_dcache_tlb_cache_set("r_dcache_tlb_cache_set"),
298	r_dcache_tlb_cache_word("r_dcache_tlb_cache_word"),
299	r_dcache_tlb_way("r_dcache_tlb_way"),
300	r_dcache_tlb_set("r_dcache_tlb_set"),
301
302	r_dcache_tlb_inval_line("r_dcache_tlb_inval_line"),
303	r_dcache_tlb_inval_set("r_dcache_tlb_inval_set"),
304
305	r_dcache_xtn_req("r_dcache_xtn_req"),
306	r_dcache_xtn_opcode("r_dcache_xtn_opcode"),
307
308	r_vci_cmd_fsm("r_vci_cmd_fsm"),
309	r_vci_cmd_min("r_vci_cmd_min"),
310	r_vci_cmd_max("r_vci_cmd_max"),
311	r_vci_cmd_cpt("r_vci_cmd_cpt"),
312	r_vci_cmd_imiss_prio("r_vci_cmd_imiss_prio"),
313
314	r_vci_rsp_fsm("r_vci_rsp_fsm"),
315	r_vci_rsp_cpt("r_vci_rsp_cpt"),
316	r_vci_rsp_ins_error("r_vci_rsp_ins_error"),
317	r_vci_rsp_data_error("r_vci_rsp_data_error"),
318	r_vci_rsp_fifo_icache("r_vci_rsp_fifo_icache", 2), // 2 words depth
319	r_vci_rsp_fifo_dcache("r_vci_rsp_fifo_dcache", 2), // 2 words depth
320
321	r_iss(this->name(), proc_id),
322	r_wbuf("wbuf", wbuf_nwords, wbuf_nlines, dcache_words ),
323	r_icache("icache", icache_ways, icache_sets, icache_words),
324	r_dcache("dcache", dcache_ways, dcache_sets, dcache_words),
325	r_itlb("itlb", proc_id, itlb_ways,itlb_sets,vci_param::N),
326	r_dtlb("dtlb", proc_id, dtlb_ways,dtlb_sets,vci_param::N),
327
328	m_dpending_updates(),
329	m_ipending_updates()
330	{
331	std::cout << " - Building VciCcVcacheWrapper : " << name << std::endl;
332
333	assert(((icache_words*vci_param::B) < (1 << vci_param::K)) and
334	"Need more PLEN bits.");
335
336	assert((vci_param::T > 2) and ((1 << (vci_param::T - 1)) >= (wbuf_nlines)) and
337	"Need more TRDID bits.");
338
339	assert((icache_words == dcache_words) and
340	"icache_words and dcache_words parameters must be equal");
341
342	assert((itlb_sets == dtlb_sets) and
343	"itlb_sets and dtlb_sets parameters must be etqual");
344
345	assert((itlb_ways == dtlb_ways) and
346	"itlb_ways and dtlb_ways parameters must be etqual");
347
348	r_mmu_params = (uint32_log2(m_dtlb_ways) << 29) \| (uint32_log2(m_dtlb_sets) << 25) \|
349	(uint32_log2(m_dcache_ways) << 22) \| (uint32_log2(m_dcache_sets) << 18) \|
350	(uint32_log2(m_itlb_ways) << 15) \| (uint32_log2(m_itlb_sets) << 11) \|
351	(uint32_log2(m_icache_ways) << 8) \| (uint32_log2(m_icache_sets) << 4) \|
352	(uint32_log2(m_icache_words << 2));
353
354	r_mmu_release = (uint32_t) (1 << 16) \| 0x1;
355
356	r_dcache_in_tlb = new bool[dcache_ways * dcache_sets];
357	r_dcache_contains_ptd = new bool[dcache_ways * dcache_sets];
358
359	SC_METHOD(transition);
360	dont_initialize();
361	sensitive << p_clk.pos();
362
363	SC_METHOD(genMoore);
364	dont_initialize();
365	sensitive << p_clk.neg();
366
367	typename iss_t::CacheInfo cache_info;
368	cache_info.has_mmu = true;
369	cache_info.icache_line_size = icache_words * sizeof(uint32_t);
370	cache_info.icache_assoc = icache_ways;
371	cache_info.icache_n_lines = icache_sets;
372	cache_info.dcache_line_size = dcache_words * sizeof(uint32_t);
373	cache_info.dcache_assoc = dcache_ways;
374	cache_info.dcache_n_lines = dcache_sets;
375	r_iss.setCacheInfo(cache_info);
376	}
377
378	/////////////////////////////////////
379	tmpl(/**/)::~VciCcVCacheWrapper()
380	/////////////////////////////////////
381	{
382	delete [] r_dcache_in_tlb;
383	delete [] r_dcache_contains_ptd;
384	}
385
386
387	//////////////////////////////////////////////////////////////////////////////////////////
388	tmpl(void)::cache_direct_update(uint64_t addr, uint32_t value, uint32_t be, int32_t srcid)
389	//////////////////////////////////////////////////////////////////////////////////////////
390	{
391
392	bool cache_hit;
393	size_t cache_way = 0;
394	size_t cache_set = 0;
395	size_t cache_word = 0;
396	uint32_t cache_rdata = 0;
397
398	if (srcid != m_srcid)
399	{
400	// We ignore the update if it was a consequence of a write by the same L1 cache
401	paddr_t mask = ~((m_dcache_words << 2) - 1);
402
403	// Test if hit in dcache
404	cache_hit = r_dcache.read_neutral(addr,
405	&cache_rdata,
406	&cache_way,
407	&cache_set,
408	&cache_word);
409
410	if (cache_hit)
411	{
412	r_dcache.write(cache_way, cache_set, cache_word, value, be);
413	#if DEBUG_DCACHE
414	if (m_debug_dcache_fsm)
415	{
416	std::cout << " <DCache " << name() << " Direct Update>"
417	<< " ADDR = " << std::hex << addr
418	<< " / VALUE = " << value
419	<< " / BE = " << be << std::endl;
420	}
421	#endif
422	// DCACHE update can require ITLB / DTLB inval or flush
423	if (r_dcache_contains_ptd[cache_way * m_dcache_sets + cache_set])
424	{
425	#if DEBUG_DCACHE
426	if (m_debug_dcache_fsm)
427	{
428	std::cout << " <Cache " << name() << " Reset TLBs>" << std::endl;
429	}
430	#endif
431	r_itlb.reset();
432	r_dtlb.reset();
433	r_dcache_contains_ptd[cache_way * m_dcache_sets + cache_set] = false;
434	r_dcache_in_tlb[cache_way * m_dcache_sets + cache_set] = false;
435	}
436	else if (r_dcache_in_tlb[cache_way * m_dcache_sets + cache_set])
437	{
438	#if DEBUG_DCACHE
439	if (m_debug_dcache_fsm)
440	{
441	std::cout << " <Cache " << name() << " Scan TLBs>" << std::endl;
442	}
443	#endif
444	for (uint32_t set = 0; set < m_dcache_sets; set++)
445	{
446	size_t way;
447	paddr_t line = addr / (m_dcache_words << 2);
448	for (way = 0; way < m_itlb_ways; way++)
449	{
450	r_itlb.inval(line, way, set);
451	}
452	for (way = 0; way < m_dtlb_ways; way++)
453	{
454	r_dtlb.inval(line, way, set);
455	}
456	}
457	r_dcache_in_tlb[cache_way * m_dcache_sets + cache_set] = false;
458	}
459	}
460	else if ((r_dcache_fsm == DCACHE_MISS_SELECT \|\|
461	r_dcache_fsm == DCACHE_MISS_VICTIM_CHECK \|\|
462	r_dcache_fsm == DCACHE_MISS_WAIT \|\|
463	r_dcache_fsm == DCACHE_MISS_DATA_UPDT \|\|
464	r_dcache_fsm == DCACHE_MISS_DIR_UPDT) &&
465	(addr & mask) == (r_dcache_save_paddr.read() & mask))
466	{
467	// Test if there is currently a miss on the line containing the address
468	// In case we are in DCACHE_MISS_DIR_UPDT, the transition function has not yet
469	// been evaluated, otherwise it would have resulted in a cache_hit
470	#if DEBUG_DCACHE
471	if (m_debug_dcache_fsm)
472	{
473	std::cout << " <DCache " << name() << " Direct Update>"
474	<< " Adding pending update for DCACHE: " << std::hex
475	<< " ADDR = " << addr
476	<< " / VALUE = " << value
477	<< " / BE = " << be
478	<< " / SAVE_ADDR = " << r_dcache_save_paddr.read()
479	<< std::dec << std::endl;
480	}
481	#endif
482	VcacheUpdate up(addr, value, be);
483	m_dpending_updates.push_back(up);
484	}
485
486	// Test if hit in icache
487	cache_hit = r_icache.read_neutral(addr,
488	&cache_rdata,
489	&cache_way,
490	&cache_set,
491	&cache_word);
492
493	if (cache_hit)
494	{
495	r_icache.write(cache_way, cache_set, cache_word, value, be);
496	#if DEBUG_ICACHE
497	if (m_debug_dcache_fsm)
498	{
499	std::cout << " <ICache " << name() << " Direct Update>"
500	<< " ADDR = " << std::hex << addr
501	<< " / VALUE = " << value
502	<< " / BE = " << be << std::endl;
503	}
504	#endif
505	}
506	else if ((r_icache_fsm == ICACHE_MISS_SELECT \|\|
507	r_icache_fsm == ICACHE_MISS_WAIT \|\|
508	r_icache_fsm == ICACHE_MISS_DATA_UPDT \|\|
509	r_icache_fsm == ICACHE_MISS_DIR_UPDT) &&
510	(addr & mask) == (r_icache_vci_paddr.read() & mask))
511	{
512	#if DEBUG_ICACHE
513	if (m_debug_icache_fsm)
514	{
515	std::cout << " <ICache " << name() << " Direct Update>"
516	<< " Adding pending update for ICACHE: " << std::hex
517	<< " ADDR = " << addr
518	<< " / VALUE = " << value
519	<< " / BE = " << be << std::endl;
520	}
521	#endif
522	// Test if there is currently a miss on the line containing the address
523	// In case we are in ICACHE_MISS_DIR_UPDT, the transition function has not yet
524	// been evaluated, otherwise it would have resulted in a cache_hit
525	VcacheUpdate up(addr, value, be);
526	m_ipending_updates.push_back(up);
527	}
528	}
529	}
530
531
532	////////////////////////
533	tmpl(void)::print_cpi()
534	////////////////////////
535	{
536	std::cout << name() << " CPI = "
537	<< (float)m_cpt_total_cycles/(m_cpt_total_cycles - m_cpt_frz_cycles) << std::endl;
538	}
539
540	////////////////////////////////////
541	tmpl(void)::print_trace(size_t mode)
542	////////////////////////////////////
543	{
544	// b0 : write buffer trace
545	// b1 : dump processor registers
546	// b2 : dcache trace
547	// b3 : icache trace
548	// b4 : dtlb trace
549	// b5 : itlb trace
550	// b6 : SR (ISS register 32)
551
552	std::cout << std::dec << "PROC " << name() << std::endl;
553
554	std::cout << " " << m_ireq << std::endl;
555	std::cout << " " << m_irsp << std::endl;
556	std::cout << " " << m_dreq << std::endl;
557	std::cout << " " << m_drsp << std::endl;
558
559	std::cout << " " << icache_fsm_state_str[r_icache_fsm.read()]
560	<< " \| " << dcache_fsm_state_str[r_dcache_fsm.read()]
561	<< " \| " << cmd_fsm_state_str[r_vci_cmd_fsm.read()]
562	<< " \| " << rsp_fsm_state_str[r_vci_rsp_fsm.read()]
563	<< " \| MMU = " << r_mmu_mode.read();
564
565	if (r_dcache_updt_req.read()) std::cout << " \| P1_UPDT";
566	if (r_dcache_wbuf_req.read()) std::cout << " \| P1_WBUF";
567	std::cout << std::endl;
568
569	if (mode & 0x01) {
570	if (r_icache_miss_req.read()) std::cout << " IMISS_REQ" << std::endl;
571	if (r_icache_unc_req.read()) std::cout << " IUNC_REQ" << std::endl;
572	if (r_dcache_vci_miss_req.read()) std::cout << " DMISS_REQ" << std::endl;
573	if (r_dcache_vci_unc_req.read()) std::cout << " DUNC_REQ" << std::endl;
574
575	r_wbuf.printTrace((mode >> 1) & 1);
576	}
577	if (mode & 0x02) {
578	r_iss.dump();
579	}
580	if (mode & 0x04) {
581	std::cout << " Data Cache" << std::endl;
582	r_dcache.printTrace();
583	}
584	if (mode & 0x08) {
585	std::cout << " Instruction Cache" << std::endl;
586	r_icache.printTrace();
587	}
588	if (mode & 0x10) {
589	std::cout << " Data TLB" << std::endl;
590	r_dtlb.printTrace();
591	}
592	if (mode & 0x20) {
593	std::cout << " Instruction TLB" << std::endl;
594	r_itlb.printTrace();
595	}
596	if (mode & 0x40) {
597	uint32_t status = r_iss.debugGetRegisterValue(32);
598	std::cout << name();
599	if (status != m_previous_status ) std::cout << " NEW ";
600	std::cout << " status = " << std::hex << status << " " << std::endl;
601	m_previous_status = status;
602	}
603	}
604
605	//////////////////////////////////////////
606	tmpl(void)::cache_monitor(paddr_t addr)
607	//////////////////////////////////////////
608	{
609	bool cache_hit;
610	size_t cache_way = 0;
611	size_t cache_set = 0;
612	size_t cache_word = 0;
613	uint32_t cache_rdata = 0;
614
615	cache_hit = r_dcache.read_neutral(addr,
616	&cache_rdata,
617	&cache_way,
618	&cache_set,
619	&cache_word);
620
621	if (cache_hit != m_debug_previous_d_hit) {
622	std::cout << "Monitor PROC " << name()
623	<< " DCACHE at cycle " << std::dec << m_cpt_total_cycles
624	<< " / HIT = " << cache_hit
625	<< " / PADDR = " << std::hex << addr
626	<< " / DATA = " << cache_rdata
627	<< " / WAY = " << cache_way << std::endl;
628	m_debug_previous_d_hit = cache_hit;
629	}
630
631	cache_hit = r_icache.read_neutral(addr,
632	&cache_rdata,
633	&cache_way,
634	&cache_set,
635	&cache_word);
636
637	if (cache_hit != m_debug_previous_i_hit) {
638	std::cout << "Monitor PROC " << name()
639	<< " ICACHE at cycle " << std::dec << m_cpt_total_cycles
640	<< " / HIT = " << cache_hit
641	<< " / PADDR = " << std::hex << addr
642	<< " / DATA = " << cache_rdata
643	<< " / WAY = " << cache_way << std::endl;
644	m_debug_previous_i_hit = cache_hit;
645	}
646	}
647
648
649	/////////////////////////
650	tmpl(void)::transition()
651	/////////////////////////
652	{
653	if (not p_resetn.read()) {
654	r_iss.reset();
655	r_wbuf.reset();
656	r_icache.reset();
657	r_dcache.reset();
658	r_itlb.reset();
659	r_dtlb.reset();
660
661	r_dcache_fsm = DCACHE_IDLE;
662	r_icache_fsm = ICACHE_IDLE;
663	r_vci_cmd_fsm = CMD_IDLE;
664	r_vci_rsp_fsm = RSP_IDLE;
665
666	// reset data physical address extension
667	r_dcache_paddr_ext = m_dcache_paddr_ext_reset;
668
669	// reset inst physical address extension
670	r_icache_paddr_ext = m_icache_paddr_ext_reset;
671
672	// reset dcache directory extension
673	for (size_t i = 0; i< m_dcache_ways * m_dcache_sets; i++) {
674	r_dcache_in_tlb[i] = false;
675	r_dcache_contains_ptd[i] = false;
676	}
677
678	// Response FIFOs and cleanup buffer
679	r_vci_rsp_fifo_icache.init();
680	r_vci_rsp_fifo_dcache.init();
681
682	// ICACHE & DCACHE activated
683	// ITLB & DTLB desactivated
684	r_mmu_mode = 0x3;
685
686	// No request from ICACHE FSM to CMD FSM
687	r_icache_miss_req = false;
688	r_icache_unc_req = false;
689
690	// No request from ICACHE_FSM to DCACHE FSM
691	r_icache_tlb_miss_req = false;
692
693	// No pending write in pipeline
694	r_dcache_wbuf_req = false;
695	r_dcache_updt_req = false;
696
697	// No request from DCACHE_FSM to CMD_FSM
698	r_dcache_vci_miss_req = false;
699	r_dcache_vci_unc_req = false;
700	r_dcache_vci_cas_req = false;
701	r_dcache_vci_ll_req = false;
702	r_dcache_vci_sc_req = false;
703
704	r_dcache_miss_type = 0;
705	r_dcache_miss_word = 0;
706	r_dcache_miss_way = 0;
707	r_dcache_miss_set = 0;
708	r_dcache_miss_victim = 0;
709
710	// No processor XTN request pending
711	r_dcache_xtn_req = false;
712
713	// No signalisation of errors
714	r_vci_rsp_ins_error = false;
715	r_vci_rsp_data_error = false;
716
717	// Debug variables
718	m_debug_previous_i_hit = false;
719	m_debug_previous_d_hit = false;
720	m_debug_icache_fsm = false;
721	m_debug_dcache_fsm = false;
722	m_debug_cmd_fsm = false;
723
724	// activity counters
725	m_cpt_dcache_data_read = 0;
726	m_cpt_dcache_data_write = 0;
727	m_cpt_dcache_dir_read = 0;
728	m_cpt_dcache_dir_write = 0;
729	m_cpt_icache_data_read = 0;
730	m_cpt_icache_data_write = 0;
731	m_cpt_icache_dir_read = 0;
732	m_cpt_icache_dir_write = 0;
733
734	m_cpt_frz_cycles = 0;
735	m_cpt_total_cycles = 0;
736	m_cpt_stop_simulation = 0;
737
738	m_cpt_data_miss = 0;
739	m_cpt_ins_miss = 0;
740	m_cpt_unc_read = 0;
741	m_cpt_write_cached = 0;
742	m_cpt_ins_read = 0;
743
744	m_cost_write_frz = 0;
745	m_cost_data_miss_frz = 0;
746	m_cost_unc_read_frz = 0;
747	m_cost_ins_miss_frz = 0;
748
749	m_cpt_imiss_transaction = 0;
750	m_cpt_dmiss_transaction = 0;
751	m_cpt_unc_transaction = 0;
752	m_cpt_write_transaction = 0;
753	m_cpt_icache_unc_transaction = 0;
754
755	m_cost_imiss_transaction = 0;
756	m_cost_dmiss_transaction = 0;
757	m_cost_unc_transaction = 0;
758	m_cost_write_transaction = 0;
759	m_cost_icache_unc_transaction = 0;
760	m_length_write_transaction = 0;
761
762	m_cpt_ins_tlb_read = 0;
763	m_cpt_ins_tlb_miss = 0;
764	m_cpt_ins_tlb_update_acc = 0;
765
766	m_cpt_data_tlb_read = 0;
767	m_cpt_data_tlb_miss = 0;
768	m_cpt_data_tlb_update_acc = 0;
769	m_cpt_data_tlb_update_dirty = 0;
770	m_cpt_ins_tlb_hit_dcache = 0;
771	m_cpt_data_tlb_hit_dcache = 0;
772	m_cpt_ins_tlb_occup_cache = 0;
773	m_cpt_data_tlb_occup_cache = 0;
774
775	m_cost_ins_tlb_miss_frz = 0;
776	m_cost_data_tlb_miss_frz = 0;
777	m_cost_ins_tlb_update_acc_frz = 0;
778	m_cost_data_tlb_update_acc_frz = 0;
779	m_cost_data_tlb_update_dirty_frz = 0;
780	m_cost_ins_tlb_occup_cache_frz = 0;
781	m_cost_data_tlb_occup_cache_frz = 0;
782
783	m_cpt_ins_tlb_inval = 0;
784	m_cpt_data_tlb_inval = 0;
785	m_cost_ins_tlb_inval_frz = 0;
786	m_cost_data_tlb_inval_frz = 0;
787
788	m_cpt_cc_broadcast = 0;
789
790	m_cost_updt_data_frz = 0;
791	m_cost_inval_ins_frz = 0;
792	m_cost_inval_data_frz = 0;
793	m_cost_broadcast_frz = 0;
794
795	m_cpt_itlbmiss_transaction = 0;
796	m_cpt_itlb_ll_transaction = 0;
797	m_cpt_itlb_sc_transaction = 0;
798	m_cpt_dtlbmiss_transaction = 0;
799	m_cpt_dtlb_ll_transaction = 0;
800	m_cpt_dtlb_sc_transaction = 0;
801	m_cpt_dtlb_ll_dirty_transaction = 0;
802	m_cpt_dtlb_sc_dirty_transaction = 0;
803
804	m_cost_itlbmiss_transaction = 0;
805	m_cost_itlb_ll_transaction = 0;
806	m_cost_itlb_sc_transaction = 0;
807	m_cost_dtlbmiss_transaction = 0;
808	m_cost_dtlb_ll_transaction = 0;
809	m_cost_dtlb_sc_transaction = 0;
810	m_cost_dtlb_ll_dirty_transaction = 0;
811	m_cost_dtlb_sc_dirty_transaction = 0;
812
813	m_dpending_updates.clear();
814	m_ipending_updates.clear();
815
816	for (uint32_t i = 0; i < 32; ++i) m_cpt_fsm_icache[i] = 0;
817	for (uint32_t i = 0; i < 32; ++i) m_cpt_fsm_dcache[i] = 0;
818	for (uint32_t i = 0; i < 32; ++i) m_cpt_fsm_cmd[i] = 0;
819	for (uint32_t i = 0; i < 32; ++i) m_cpt_fsm_rsp[i] = 0;
820
821	// init the llsc reservation buffer
822	r_dcache_llsc_valid = false;
823	m_monitor_ok = false;
824
825	return;
826	}
827
828	// Response FIFOs default values
829	bool vci_rsp_fifo_icache_get = false;
830	bool vci_rsp_fifo_icache_put = false;
831	uint32_t vci_rsp_fifo_icache_data = 0;
832
833	bool vci_rsp_fifo_dcache_get = false;
834	bool vci_rsp_fifo_dcache_put = false;
835	uint32_t vci_rsp_fifo_dcache_data = 0;
836
837	#ifdef INSTRUMENTATION
838	m_cpt_fsm_dcache[r_dcache_fsm.read()]++;
839	m_cpt_fsm_icache[r_icache_fsm.read()]++;
840	m_cpt_fsm_cmd[r_vci_cmd_fsm.read()]++;
841	m_cpt_fsm_rsp[r_vci_rsp_fsm.read()]++;
842	m_cpt_fsm_tgt[r_tgt_fsm.read()]++;
843	m_cpt_fsm_cleanup[r_cleanup_cmd_fsm.read()]++;
844	#endif
845
846	m_cpt_total_cycles++;
847
848	m_debug_icache_fsm = m_debug_icache_fsm \|\|
849	((m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok);
850	m_debug_dcache_fsm = m_debug_dcache_fsm \|\|
851	((m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok);
852	m_debug_cmd_fsm = m_debug_cmd_fsm \|\|
853	((m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok);
854
855	/////////////////////////////////////////////////////////////////////
856	// Get data and instruction requests from processor
857	///////////////////////////////////////////////////////////////////////
858
859	r_iss.getRequests(m_ireq, m_dreq);
860
861	////////////////////////////////////////////////////////////////////////////////////
862	// ICACHE_FSM
863	//
864	// 1/ Coherence operations
865	// They are handled as interrupts generated by the CC_RECEIVE FSM.
866	// - There is a coherence request when r_tgt_icache_req is set.
867	// They are taken in IDLE, MISS_WAIT, MISS_DIR_UPDT, UNC_WAIT, states.
868	// - There is a cleanup ack request when r_cleanup_icache_req is set.
869	// They are taken in IDLE, MISS_SELECT, MISS_CLEAN, MISS_WAIT,
870	// MISS_DATA_UPDT, MISS_DIR_UPDT and UNC_WAIT states.
871	// - For both types of requests, actions associated to the pre-empted state
872	// are not executed. The DCACHE FSM goes to the proper sub-FSM (CC_CHECK
873	// or CC_CLACK) to execute the requested coherence operation, and returns
874	// to the pre-empted state.
875	//
876	// 2/ Processor requests
877	// They are taken in IDLE state only. In case of cache miss, or uncacheable
878	// instruction, the ICACHE FSM request a VCI transaction to CMD FSM,
879	// using the r_icache_miss_req or r_icache_unc_req flip-flops. These
880	// flip-flops are reset when the transaction starts.
881	// - In case of miss the ICACHE FSM goes to the ICACHE_MISS_SELECT state
882	// to select a slot and possibly request a cleanup transaction to the CC_SEND FSM.
883	// It goes next to the ICACHE_MISS_WAIT state waiting a response from RSP FSM,
884	// The availability of the missing cache line is signaled by the response fifo,
885	// and the cache update is done (one word per cycle) in the ICACHE_MISS_DATA_UPDT
886	// and ICACHE_MISS_DIR_UPDT states.
887	// - In case of uncacheable instruction, the ICACHE FSM goes to ICACHE_UNC_WAIT
888	// to wait the response from the RSP FSM, through the response fifo.
889	// The missing instruction is directly returned to processor in this state.
890	//
891	// 3/ TLB miss
892	// In case of tlb miss, the ICACHE FSM request to the DCACHE FSM to update the
893	// ITLB using the r_icache_tlb_miss_req flip-flop and the r_icache_tlb_miss_vaddr
894	// register, and goes to the ICACHE_TLB_WAIT state.
895	// The tlb update is entirely done by the DCACHE FSM (who becomes the owner
896	// of ITLB until the update is completed, and reset r_icache_tlb_miss_req
897	// to signal the completion.
898	//
899	// 4/ XTN requests
900	// The DCACHE FSM signals XTN processor requests to ICACHE_FSM
901	// using the r_dcache_xtn_req flip-flop.
902	// The request opcode and the address to be invalidated are transmitted
903	// in the r_dcache_xtn_opcode and r_dcache_save_wdata registers respectively.
904	// The r_dcache_xtn_req flip-flop is reset by the ICACHE_FSM when the operation
905	// is completed.
906	//
907	// 5/ Error Handling
908	// The r_vci_rsp_ins_error flip-flop is set by the RSP FSM in case of bus error
909	// in a cache miss or uncacheable read VCI transaction. Nothing is written
910	// in the response fifo. This flip-flop is reset by the ICACHE-FSM.
911	////////////////////////////////////////////////////////////////////////////////////////
912
913	// default value for m_irsp
914	m_irsp.valid = false;
915	m_irsp.error = false;
916	m_irsp.instruction = 0;
917
918	switch (r_icache_fsm.read()) {
919	/////////////////
920	case ICACHE_IDLE: // In this state, we handle processor requests, XTN requests,
921	// and coherence requests with a fixed priority:
922	// 1/ Coherence requests => ICACHE_CC_CHECK
923	// 2/ XTN processor requests (from DCACHE FSM) => ICACHE_XTN_*
924	// 3/ tlb miss => ICACHE_TLB_WAIT
925	// 4/ cacheable read miss => ICACHE_MISS_SELECT
926	// 5/ uncacheable read miss => ICACHE_UNC_REQ
927	{
928	// XTN requests sent by DCACHE FSM
929	// These request are not executed in this IDLE state (except XTN_INST_PADDR_EXT),
930	// because they require access to icache or itlb, that are already accessed
931	if (r_dcache_xtn_req.read()) {
932	if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_PTPR ) {
933	r_icache_fsm = ICACHE_XTN_TLB_FLUSH;
934	}
935	else if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_ICACHE_FLUSH) {
936	r_icache_flush_count = 0;
937	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH;
938	}
939	else if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_ITLB_INVAL) {
940	r_icache_fsm = ICACHE_XTN_TLB_INVAL;
941	}
942	else if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_ICACHE_INVAL) {
943	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_VA;
944	}
945	else if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_MMU_ICACHE_PA_INV) {
946	if (sizeof(paddr_t) <= 32) {
947	assert(r_mmu_word_hi.read() == 0 &&
948	"illegal XTN request in ICACHE: high bits should be 0 for 32bit paddr");
949	r_icache_vci_paddr = (paddr_t) r_mmu_word_lo.read();
950	}
951	else {
952	r_icache_vci_paddr = (paddr_t) r_mmu_word_hi.read() << 32 \|
953	(paddr_t) r_mmu_word_lo.read();
954	}
955	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA;
956	}
957	else if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_INST_PADDR_EXT) {
958	r_icache_paddr_ext = r_dcache_save_wdata.read();
959	r_dcache_xtn_req = false;
960	}
961	else {
962	assert(false and
963	"undefined XTN request received by ICACHE FSM");
964	}
965	break;
966	} // end if xtn_req
967
968	// processor request
969	if (m_ireq.valid) {
970	bool cacheable;
971	paddr_t paddr;
972	bool tlb_hit = false;
973	pte_info_t tlb_flags;
974	size_t tlb_way;
975	size_t tlb_set;
976	paddr_t tlb_nline;
977	uint32_t cache_inst = 0;
978	size_t cache_way;
979	size_t cache_set;
980	size_t cache_word;
981	int cache_state = CACHE_SLOT_STATE_INVALID;
982
983	// We register processor request
984	r_icache_vaddr_save = m_ireq.addr;
985	paddr = (paddr_t) m_ireq.addr;
986
987	// sytematic itlb access (if activated)
988	if (r_mmu_mode.read() & INS_TLB_MASK) {
989
990	#ifdef INSTRUMENTATION
991	m_cpt_itlb_read++;
992	#endif
993	tlb_hit = r_itlb.translate(m_ireq.addr,
994	&paddr,
995	&tlb_flags,
996	&tlb_nline, // unused
997	&tlb_way, // unused
998	&tlb_set); // unused
999	}
1000	else if (vci_param::N > 32) {
1001	paddr = paddr \| ((paddr_t) r_icache_paddr_ext.read() << 32);
1002	}
1003
1004	// systematic icache access (if activated)
1005	if (r_mmu_mode.read() & INS_CACHE_MASK) {
1006
1007
1008	#ifdef INSTRUMENTATION
1009	m_cpt_icache_data_read++;
1010	m_cpt_icache_dir_read++;
1011	#endif
1012	r_icache.read(paddr,
1013	&cache_inst,
1014	&cache_way,
1015	&cache_set,
1016	&cache_word,
1017	&cache_state);
1018	}
1019
1020	// We compute cacheability and check access rights:
1021	// - If MMU activated : cacheability is defined by the C bit in the PTE,
1022	// and the access rights are defined by the U and X bits in the PTE.
1023	// - If MMU not activated : cacheability is defined by the segment table,
1024	// and there is no access rights checking
1025
1026	if (not (r_mmu_mode.read() & INS_TLB_MASK)) {
1027	// tlb not activated:
1028	// cacheability
1029	if (not (r_mmu_mode.read() & INS_CACHE_MASK)) {
1030	cacheable = false;
1031	}
1032	else {
1033	cacheable = m_cacheability_table[(uint64_t) m_ireq.addr];
1034	}
1035	}
1036	else
1037	{
1038	// itlb activated
1039	if (tlb_hit)
1040	{
1041	// ITLB hit
1042	// cacheability
1043	if (not (r_mmu_mode.read() & INS_CACHE_MASK))
1044	{
1045	cacheable = false;
1046	}
1047	else
1048	{
1049	cacheable = tlb_flags.c;
1050	}
1051
1052	// access rights checking
1053	if (not tlb_flags.u && (m_ireq.mode == iss_t::MODE_USER))
1054	{
1055	r_mmu_ietr = MMU_READ_PRIVILEGE_VIOLATION;
1056	r_mmu_ibvar = m_ireq.addr;
1057	m_irsp.valid = true;
1058	m_irsp.error = true;
1059	m_irsp.instruction = 0;
1060	break;
1061	}
1062	else if (not tlb_flags.x)
1063	{
1064	r_mmu_ietr = MMU_READ_EXEC_VIOLATION;
1065	r_mmu_ibvar = m_ireq.addr;
1066	m_irsp.valid = true;
1067	m_irsp.error = true;
1068	m_irsp.instruction = 0;
1069	break;
1070	}
1071	}
1072	else
1073	{
1074	// ITLB miss
1075
1076	#ifdef INSTRUMENTATION
1077	m_cpt_itlb_miss++;
1078	#endif
1079	r_icache_fsm = ICACHE_TLB_WAIT;
1080	r_icache_tlb_miss_req = true;
1081	break;
1082	}
1083	} // end if itlb activated
1084
1085	// physical address registration
1086	r_icache_vci_paddr = paddr;
1087
1088	// Finally, we send the response to processor, and compute next state
1089	if (cacheable) {
1090	if (cache_state == CACHE_SLOT_STATE_INVALID) {
1091	// cache miss
1092	#ifdef INSTRUMENTATION
1093	m_cpt_icache_miss++;
1094	#endif
1095	// we request a VCI transaction
1096	r_icache_fsm = ICACHE_MISS_SELECT;
1097	#if DEBUG_ICACHE
1098	if (m_debug_icache_fsm) {
1099	std::cout << " <PROC " << name() << " ICACHE_IDLE> READ MISS in icache"
1100	<< " : PADDR = " << std::hex << paddr << std::endl;
1101	}
1102	#endif
1103	r_icache_miss_req = true;
1104	}
1105	else {
1106	// cache hit
1107	#ifdef INSTRUMENTATION
1108	m_cpt_ins_read++;
1109	#endif
1110	// return instruction to processor
1111	m_irsp.valid = true;
1112	m_irsp.instruction = cache_inst;
1113	r_icache_fsm = ICACHE_IDLE;
1114	#if DEBUG_ICACHE
1115	if (m_debug_icache_fsm) {
1116	std::cout << " <PROC " << name() << " ICACHE_IDLE> READ HIT in icache"
1117	<< " : PADDR = " << std::hex << paddr
1118	<< " / INST = " << cache_inst << std::endl;
1119	}
1120	#endif
1121	}
1122	}
1123	else {
1124	// non cacheable read
1125	r_icache_unc_req = true;
1126	r_icache_fsm = ICACHE_UNC_WAIT;
1127
1128	#if DEBUG_ICACHE
1129	if (m_debug_icache_fsm) {
1130	std::cout << " <PROC " << name()
1131	<< " ICACHE_IDLE> READ UNCACHEABLE in icache"
1132	<< " : PADDR = " << std::hex << paddr << std::endl;
1133	}
1134	#endif
1135	}
1136	} // end if m_ireq.valid
1137	break;
1138	}
1139	/////////////////////
1140	case ICACHE_TLB_WAIT: // Waiting the itlb update by the DCACHE FSM after a tlb miss
1141	// the itlb is udated by the DCACHE FSM, as well as the
1142	// r_mmu_ietr and r_mmu_ibvar registers in case of error.
1143	// the itlb is not accessed by ICACHE FSM until DCACHE FSM
1144	// reset the r_icache_tlb_miss_req flip-flop
1145	// external coherence request are accepted in this state.
1146	{
1147	// DCACHE FSM signals response by reseting the request flip-flop
1148	if (not r_icache_tlb_miss_req.read()) {
1149	if (r_icache_tlb_rsp_error.read()) {
1150	// error reported : tlb not updated
1151	r_icache_tlb_rsp_error = false;
1152	m_irsp.error = true;
1153	m_irsp.valid = true;
1154	r_icache_fsm = ICACHE_IDLE;
1155	}
1156	else {
1157	// tlb updated : return to IDLE state
1158	r_icache_fsm = ICACHE_IDLE;
1159	}
1160	}
1161	break;
1162	}
1163	//////////////////////////
1164	case ICACHE_XTN_TLB_FLUSH: // invalidate in one cycle all non global TLB entries
1165	{
1166	r_itlb.flush();
1167	r_dcache_xtn_req = false;
1168	r_icache_fsm = ICACHE_IDLE;
1169	break;
1170	}
1171	////////////////////////////
1172	case ICACHE_XTN_CACHE_FLUSH: // Invalidate sequencially all cache lines, using
1173	// r_icache_flush_count as a slot counter,
1174	// looping in this state until all slots are visited.
1175	// It can require two cycles per slot:
1176	// We test here the slot state, and make the actual inval
1177	// (if line is valid) in ICACHE_XTN_CACHE_FLUSH_GO state.
1178	// A cleanup request is generated for each valid line
1179	{
1180	int state;
1181	paddr_t tag;
1182	size_t way = r_icache_flush_count.read() / m_icache_sets;
1183	size_t set = r_icache_flush_count.read() % m_icache_sets;
1184
1185	r_icache.read_dir(way,
1186	set,
1187	&tag,
1188	&state);
1189
1190	if (state == CACHE_SLOT_STATE_VALID) {
1191	// goes to ICACHE_XTN_CACHE_FLUSH_GO to make inval
1192	r_icache_miss_way = way;
1193	r_icache_miss_set = set;
1194	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH_GO;
1195	}
1196	else if (r_icache_flush_count.read() == (m_icache_sets * m_icache_ways - 1)) {
1197	// last slot
1198	r_dcache_xtn_req = false;
1199	m_drsp.valid = true;
1200	r_icache_fsm = ICACHE_IDLE;
1201	}
1202
1203	// saturation counter, to have the same last slot condition
1204	// in ICACHE_XTN_CACHE_FLUSH and ICACHE_XTN_CACHE_FLUSH_GO states
1205	if (r_icache_flush_count.read() < (m_icache_sets * m_icache_ways - 1)) {
1206	r_icache_flush_count = r_icache_flush_count.read() + 1;
1207	}
1208	break;
1209	}
1210	///////////////////////////////
1211	case ICACHE_XTN_CACHE_FLUSH_GO: // Switch slot state to ZOMBI for an XTN flush
1212	{
1213	size_t way = r_icache_miss_way.read();
1214	size_t set = r_icache_miss_set.read();
1215
1216	r_icache.write_dir(way,
1217	set,
1218	CACHE_SLOT_STATE_INVALID);
1219
1220	if (r_icache_flush_count.read() == (m_icache_sets * m_icache_ways - 1)) {
1221	// last slot
1222	r_dcache_xtn_req = false;
1223	m_drsp.valid = true;
1224	r_icache_fsm = ICACHE_IDLE;
1225	}
1226	else {
1227	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH;
1228	}
1229	break;
1230	}
1231
1232	//////////////////////////
1233	case ICACHE_XTN_TLB_INVAL: // invalidate one TLB entry selected by the virtual address
1234	// stored in the r_dcache_save_wdata register
1235	{
1236	r_itlb.inval(r_dcache_save_wdata.read());
1237	r_dcache_xtn_req = false;
1238	r_icache_fsm = ICACHE_IDLE;
1239	break;
1240	}
1241	///////////////////////////////
1242	case ICACHE_XTN_CACHE_INVAL_VA: // Selective cache line invalidate with virtual address
1243	// requires 3 cycles (in case of hit on itlb and icache).
1244	// In this state, access TLB to translate virtual address
1245	// stored in the r_dcache_save_wdata register.
1246	{
1247	paddr_t paddr;
1248	bool hit;
1249
1250	// read physical address in TLB when MMU activated
1251	if (r_mmu_mode.read() & INS_TLB_MASK) {
1252	// itlb activated
1253	hit = r_itlb.translate(r_dcache_save_wdata.read(), &paddr);
1254	}
1255	else {
1256	// itlb not activated
1257	paddr = (paddr_t) r_dcache_save_wdata.read();
1258	hit = true;
1259	}
1260
1261	if (hit) {
1262	// continue the selective inval process
1263	r_icache_vci_paddr = paddr;
1264	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA;
1265	}
1266	else {
1267	// miss : send a request to DCACHE FSM
1268	r_icache_tlb_miss_req = true;
1269	r_icache_vaddr_save = r_dcache_save_wdata.read();
1270	r_icache_fsm = ICACHE_TLB_WAIT;
1271	}
1272	break;
1273	}
1274	///////////////////////////////
1275	case ICACHE_XTN_CACHE_INVAL_PA: // selective invalidate cache line with physical address
1276	// require 2 cycles. In this state, we read directory
1277	// with address stored in r_icache_vci_paddr register.
1278	{
1279	int state;
1280	size_t way;
1281	size_t set;
1282	size_t word;
1283
1284	r_icache.read_dir(r_icache_vci_paddr.read(),
1285	&state,
1286	&way,
1287	&set,
1288	&word);
1289
1290	if (state == CACHE_SLOT_STATE_VALID) {
1291	// inval to be done
1292	r_icache_miss_way = way;
1293	r_icache_miss_set = set;
1294	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_GO;
1295	}
1296	else {
1297	// miss : acknowlege the XTN request and return
1298	r_dcache_xtn_req = false;
1299	r_icache_fsm = ICACHE_IDLE;
1300	}
1301	break;
1302	}
1303	///////////////////////////////
1304	case ICACHE_XTN_CACHE_INVAL_GO: // Switch slot to ZOMBI state for an XTN inval
1305	{
1306	r_icache.write_dir(r_icache_miss_way.read(),
1307	r_icache_miss_set.read(),
1308	CACHE_SLOT_STATE_INVALID);
1309
1310	// acknowledge the XTN request and return
1311	r_dcache_xtn_req = false;
1312	r_icache_fsm = ICACHE_IDLE;
1313	break;
1314	}
1315	////////////////////////
1316	case ICACHE_MISS_SELECT: // Try to select a slot in associative set,
1317	// Waiting in this state if no slot available.
1318	// If a victim slot has been chosen and the r_icache_cc_send_req is false,
1319	// we send the cleanup request in this state.
1320	// If not, a r_icache_cleanup_victim_req flip-flop is
1321	// utilized for saving this cleanup request, and it will be sent later
1322	// in state ICACHE_MISS_WAIT or ICACHE_MISS_UPDT_DIR.
1323	// The r_icache_miss_clack flip-flop is set
1324	// when a cleanup is required
1325	{
1326	bool found;
1327	bool cleanup;
1328	size_t way;
1329	size_t set;
1330	paddr_t victim;
1331
1332	r_icache.read_select(r_icache_vci_paddr.read(),
1333	&victim,
1334	&way,
1335	&set,
1336	&found,
1337	&cleanup);
1338	if (not found)
1339	{
1340	break;
1341	}
1342	else {
1343	r_icache_miss_way = way;
1344	r_icache_miss_set = set;
1345
1346	r_icache_fsm = ICACHE_MISS_WAIT;
1347
1348	#if DEBUG_ICACHE
1349	if (m_debug_icache_fsm) {
1350	std::cout << " <PROC " << name()
1351	<< " ICACHE_MISS_SELECT> Select a slot:" << std::dec
1352	<< " / WAY = " << way
1353	<< " / SET = " << set << std::endl;
1354	}
1355	#endif
1356	}
1357	break;
1358	}
1359	///////////////////////
1360	case ICACHE_MISS_CLEAN: // switch the slot to zombi state
1361	{
1362	r_icache.write_dir(r_icache_miss_way.read(),
1363	r_icache_miss_set.read(),
1364	CACHE_SLOT_STATE_INVALID);
1365	#if DEBUG_ICACHE
1366	if (m_debug_icache_fsm) {
1367	std::cout << " <PROC " << name()
1368	<< " ICACHE_MISS_CLEAN> Switch to EMPTY state" << std::dec
1369	<< " / WAY = " << r_icache_miss_way.read()
1370	<< " / SET = " << r_icache_miss_set.read() << std::endl;
1371	}
1372	#endif
1373
1374	r_icache_fsm = ICACHE_MISS_WAIT;
1375	break;
1376	}
1377	//////////////////////
1378	case ICACHE_MISS_WAIT: // waiting response from VCI_RSP FSM
1379	{
1380	if (r_vci_rsp_ins_error.read()) {
1381	// bus error
1382	r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS;
1383	r_mmu_ibvar = r_icache_vaddr_save.read();
1384	m_irsp.valid = true;
1385	m_irsp.error = true;
1386	r_vci_rsp_ins_error = false;
1387	r_icache_fsm = ICACHE_IDLE;
1388	}
1389	else if (r_vci_rsp_fifo_icache.rok()) {
1390	// response available
1391	r_icache_miss_word = 0;
1392	r_icache_fsm = ICACHE_MISS_DATA_UPDT;
1393	}
1394	break;
1395	}
1396	///////////////////////////
1397	case ICACHE_MISS_DATA_UPDT: // update the cache (one word per cycle)
1398	{
1399	if (r_vci_rsp_fifo_icache.rok()) {
1400	// response available
1401	r_icache.write(r_icache_miss_way.read(),
1402	r_icache_miss_set.read(),
1403	r_icache_miss_word.read(),
1404	r_vci_rsp_fifo_icache.read());
1405	#if DEBUG_ICACHE
1406	if (m_debug_icache_fsm) {
1407	std::cout << " <PROC " << name()
1408	<< " ICACHE_MISS_DATA_UPDT> Write one word:"
1409	<< " WDATA = " << std::hex << r_vci_rsp_fifo_icache.read()
1410	<< " WAY = " << r_icache_miss_way.read()
1411	<< " SET = " << r_icache_miss_set.read()
1412	<< " WORD = " << r_icache_miss_word.read() << std::endl;
1413	}
1414	#endif
1415	vci_rsp_fifo_icache_get = true;
1416	r_icache_miss_word = r_icache_miss_word.read() + 1;
1417
1418	if (r_icache_miss_word.read() == m_icache_words - 1) {
1419	// last word
1420	r_icache_fsm = ICACHE_MISS_DIR_UPDT;
1421	}
1422	}
1423	break;
1424	}
1425	//////////////////////////
1426	case ICACHE_MISS_DIR_UPDT: // Stalled if a victim line has been evicted,
1427	// and the cleanup ack has not been received,
1428	// as indicated by r_icache_miss_clack.
1429	// - If no matching coherence request (r_icache_miss_inval)
1430	// switch directory slot to VALID state.
1431	// - If matching coherence request, switch directory slot
1432	// to ZOMBI state, and send a cleanup request.
1433	{
1434	// Switch slot to VALID state
1435	r_icache.write_dir(r_icache_vci_paddr.read(),
1436	r_icache_miss_way.read(),
1437	r_icache_miss_set.read(),
1438	CACHE_SLOT_STATE_VALID);
1439	#if DEBUG_ICACHE
1440	if (m_debug_icache_fsm) {
1441	std::cout << " <PROC " << name()
1442	<< " ICACHE_MISS_DIR_UPDT> Switch cache slot to VALID state"
1443	<< " PADDR = " << std::hex << r_icache_vci_paddr.read()
1444	<< " WAY = " << std::dec << r_icache_miss_way.read()
1445	<< " SET = " << r_icache_miss_set.read() << std::endl;
1446	}
1447	#endif
1448
1449	// Immediate coherence test:
1450	// If we have received one or several updates on the line during the miss, we have stored them
1451	// and we update the values now
1452	for (std::list<VcacheUpdate>::iterator it = m_ipending_updates.begin(); it != m_ipending_updates.end(); it++)
1453	{
1454	bool cache_hit;
1455	size_t cache_way = 0;
1456	size_t cache_set = 0;
1457	size_t cache_word = 0;
1458	uint32_t cache_rdata = 0;
1459
1460	// Test if hit in dcache
1461	cache_hit = r_icache.read_neutral(it->m_addr,
1462	&cache_rdata,
1463	&cache_way,
1464	&cache_set,
1465	&cache_word);
1466
1467	assert(cache_hit);
1468	assert(cache_way == r_icache_miss_way.read());
1469	assert(cache_set == r_icache_miss_set.read());
1470
1471	r_icache.write(cache_way, cache_set, cache_word, it->m_value, it->m_be);
1472	#if DEBUG_DCACHE
1473	if (m_debug_icache_fsm) {
1474	std::cout << " <Cache " << name()
1475	<< " CACHE_MISS_DIR_UPDT> Updating pending update:"
1476	<< " ADDR = " << std::hex << it->m_addr
1477	<< " / WAY = " << std::dec << cache_way
1478	<< " / SET = " << cache_set
1479	<< " / VALUE = " << std::hex << it->m_value
1480	<< " / BE = " << it->m_be << std::endl;
1481	}
1482	#endif
1483	}
1484	m_ipending_updates.clear();
1485
1486	r_icache_fsm = ICACHE_IDLE;
1487	break;
1488	}
1489	////////////////////
1490	case ICACHE_UNC_WAIT: // waiting a response to an uncacheable read from VCI_RSP FSM
1491	{
1492	if (r_vci_rsp_ins_error.read()) {
1493	// bus error
1494	r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS;
1495	r_mmu_ibvar = m_ireq.addr;
1496	r_vci_rsp_ins_error = false;
1497	m_irsp.valid = true;
1498	m_irsp.error = true;
1499	r_icache_fsm = ICACHE_IDLE;
1500	}
1501	else if (r_vci_rsp_fifo_icache.rok()) {
1502	// instruction available
1503	vci_rsp_fifo_icache_get = true;
1504	r_icache_fsm = ICACHE_IDLE;
1505	if (m_ireq.valid and (m_ireq.addr == r_icache_vaddr_save.read())) {
1506	// request unmodified
1507	m_irsp.valid = true;
1508	m_irsp.instruction = r_vci_rsp_fifo_icache.read();
1509	}
1510	}
1511	break;
1512	}
1513
1514	} // end switch r_icache_fsm
1515
1516	////////////////////////////////////////////////////////////////////////////////////
1517	// DCACHE FSM
1518	//
1519	// 1/ Coherence operations
1520	// They are handled as interrupts generated by the CC_RECEIVE FSM.
1521	// - There is a coherence request when r_tgt_dcache_req is set.
1522	// They are taken in IDLE, MISS_WAIT, MISS_DIR_UPDT, UNC_WAIT, LL_WAIT
1523	// and SC_WAIT states.
1524	// - There is a cleanup acknowledge request when r_cleanup_dcache_req is set.
1525	// They are taken in IDLE, MISS_SELECT, MISS_CLEAN, MISS_WAIT, MISS_DATA_UPDT,
1526	// MISS_DIR_UPDT, UNC_WAIT, LL_WAIT, SC_WAIT states.
1527	// - For both types of requests, actions associated to the pre-empted state
1528	// are not executed. The DCACHE FSM goes to the proper sub-FSM (CC_CHECK
1529	// or CC_CLACK) to execute the requested coherence operation, and returns
1530	// to the pre-empted state.
1531	//
1532	// 2/ TLB miss
1533	// The page tables are generally cacheable.
1534	// In case of miss in itlb or dtlb, the tlb miss is handled by a dedicated
1535	// sub-fsm (DCACHE_TLB_MISS state), that handle possible miss in DCACHE,
1536	// this sub-fsm implement the table-walk...
1537	//
1538	// 3/ processor requests
1539	// Processor requests are taken in IDLE state only.
1540	// The IDLE state implements a two stages pipe-line to handle write bursts:
1541	// - Both DTLB and DCACHE are accessed in stage P0 (if processor request valid).
1542	// - The registration in wbuf and the dcache update is done in stage P1
1543	// (if the processor request is a write).
1544	// The two r_dcache_wbuf_req and r_dcache_updt_req flip-flops define
1545	// the operations that must be done in P1 stage, and the access type
1546	// (read or write) to the DATA part of DCACHE depends on r_dcache_updt_req.
1547	// READ requests are delayed if a cache update is requested.
1548	// WRITE or SC requests can require a PTE Dirty bit update (in memory),
1549	// that is done (before handling the processor request) by a dedicated sub-fsm.
1550	// If a PTE is modified, both the itlb and dtlb are selectively, but sequencially
1551	// cleared by a dedicated sub_fsm (DCACHE_INVAL_TLB_SCAN state).
1552	//
1553	// 4/ Atomic instructions LL/SC
1554	// The LL/SC address are non cacheable (systematic access to memory).
1555	// The llsc buffer contains a registration for an active LL/SC operation
1556	// (with an address, a registration key, an aging counter and a valid bit).
1557	// - LL requests from the processor are transmitted as a one flit VCI command
1558	// (CMD_LOCKED_READ as CMD, and TYPE_LL as PKTID value). PLEN must
1559	// be 8 as the response is 2 flits long (data and registration key)
1560	// - SC requests from the processor are systematically transmitted to the
1561	// memory cache as 2 flits VCI command (CMD_STORE_COND as CMD, and TYPE_SC
1562	// as PKTID value). The first flit contains the registration key, the second
1563	// flit contains the data to write in case of success.
1564	// The cache is not updated, as this is done in case of success by the
1565	// coherence transaction.
1566	//
1567	// 5/ Non cacheable access:
1568	// This component implement a strong order between non cacheable access
1569	// (read or write) : A new non cacheable VCI transaction starts only when
1570	// the previous non cacheable transaction is completed. After send the VCI
1571	// transaction, the DCACHE FSM wait for the respone in the DCACHE_UNC_WAIT state.
1572	// So the processor is blocked until the respone arrives in CACHE L1.
1573	//
1574	// 6/ Error handling:
1575	// When the MMU is not activated, Read Bus Errors are synchronous events,
1576	// Some Write Bus Errors are synchronous events when the request is a non cacheable access
1577	// but some Write Bus Errors are asynchronous events when the request is cacheable access
1578	// (processor is not frozen).
1579	// - If a Read Bus Error or a Non Cacheable Write Bus Error is detected, the VCI_RSP FSM sets the
1580	// r_vci_rsp_data_error flip-flop, without writing any data in the
1581	// r_vci_rsp_fifo_dcache FIFO, and the synchronous error is signaled
1582	// by the DCACHE FSM.
1583	// - If a Cacheable Write Bus Error is detected, the VCI_RSP_FSM signals
1584	// the asynchronous error using the setWriteBerr() method.
1585	// When the MMU is activated bus error are rare events, as the MMU
1586	// checks the physical address before the VCI transaction starts.
1587	////////////////////////////////////////////////////////////////////////////////////////
1588
1589	// default value for m_drsp
1590	m_drsp.valid = false;
1591	m_drsp.error = false;
1592	m_drsp.rdata = 0;
1593
1594	switch (r_dcache_fsm.read()) {
1595	case DCACHE_IDLE: // There are 10 conditions to exit the IDLE state :
1596	// 1) ITLB/DTLB inval request (update) => DCACHE_INVAL_TLB_SCAN
1597	// 3) ITLB miss request (ICACHE FSM) => DCACHE_TLB_MISS
1598	// 4) XTN request (processor) => DCACHE_XTN_*
1599	// 5) DTLB miss (processor) => DCACHE_TLB_MISS
1600	// 6) Dirty bit update (processor) => DCACHE_DIRTY_GET_PTE
1601	// 7) Cacheable read miss (processor) => DCACHE_MISS_SELECT
1602	// 8) Uncacheable read (processor) => DCACHE_UNC_WAIT
1603	// 9) LL access (processor) => DCACHE_LL_WAIT
1604	// 10) SC access (processor) => DCACHE_SC_WAIT
1605	//
1606	// There is a fixed priority to handle requests to DCACHE:
1607	// 1/ the ITLB/DTLB invalidate requests
1608	// 2/ the coherence requests,
1609	// 3/ the processor requests (including DTLB miss),
1610	// 4/ the ITLB miss requests,
1611	// The address space processor request are handled as follows:
1612	// - WRITE request is blocked if the Dirty bit mus be set.
1613	// If DTLB hit, the P1 stage is activated (writes WBUF, and
1614	// updates DCACHE if DCACHE hit) & processor request acknowledged.
1615	// - READ request generate a simultaneouss access to DCACHE.DATA
1616	// and DCACHE.DIR, but is delayed if DCACHE update required.
1617	//
1618	// There is 4 configurations defining the access type to
1619	// DTLB, DCACHE.DATA, and DCACHE.DIR, depending on the
1620	// dreq.valid (dreq) and r_dcache_updt_req (updt) signals:
1621	// dreq / updt / DTLB / DCACHE.DIR / DCACHE.DATA /
1622	// 0 / 0 / NOP / NOP / NOP /
1623	// 0 / 1 / NOP / NOP / WRITE /
1624	// 1 / 0 / READ / READ / NOP /
1625	// 1 / 1 / READ / READ / WRITE /
1626	// Those two registers are set at each cycle from the 3 signals
1627	// updt_request, wbuf_request, wbuf_write_miss.
1628	{
1629	paddr_t paddr;
1630	pte_info_t tlb_flags;
1631	size_t tlb_way;
1632	size_t tlb_set;
1633	paddr_t tlb_nline = 0;
1634	size_t cache_way;
1635	size_t cache_set;
1636	size_t cache_word;
1637	uint32_t cache_rdata = 0;
1638	bool tlb_hit = false;
1639	int cache_state = CACHE_SLOT_STATE_INVALID;
1640
1641	bool tlb_inval_required = false; // request TLB inval after cache update
1642	bool wbuf_write_miss = false; // miss a WBUF write request
1643	bool updt_request = false; // request DCACHE update in P1 stage
1644	bool wbuf_request = false; // request WBUF write in P1 stage
1645
1646	// physical address computation : systematic DTLB access if activated
1647	paddr = (paddr_t) m_dreq.addr;
1648	if (m_dreq.valid) {
1649	#if 1
1650	// DO NOT COMMIT: QM ONLY, SCRIPT PURPOSE
1651	if (m_dreq.addr == 0x0 && m_dreq.wdata == 0xDEADDEAD) {
1652	std::cout << "Ecriture Ã l'adresse 0 pour fin de simu" << std::endl;
1653	raise(SIGINT);
1654	}
1655	#endif
1656
1657	if (r_mmu_mode.read() & DATA_TLB_MASK) {
1658	// DTLB activated
1659	tlb_hit = r_dtlb.translate(m_dreq.addr,
1660	&paddr,
1661	&tlb_flags,
1662	&tlb_nline,
1663	&tlb_way,
1664	&tlb_set);
1665	}
1666	else {
1667	// identity mapping
1668	// we take into account the paddr extension
1669	if (vci_param::N > 32) {
1670	paddr = paddr \| ((paddr_t) (r_dcache_paddr_ext.read()) << 32);
1671	}
1672	}
1673	} // end physical address computation
1674
1675	// systematic DCACHE access depending on r_dcache_updt_req (if activated)
1676	if (r_mmu_mode.read() & DATA_CACHE_MASK) {
1677
1678	if (m_dreq.valid and r_dcache_updt_req.read()) {
1679	// read DIR and write DATA
1680	r_dcache.read_dir(paddr,
1681	&cache_state,
1682	&cache_way,
1683	&cache_set,
1684	&cache_word);
1685
1686	r_dcache.write(r_dcache_save_cache_way.read(),
1687	r_dcache_save_cache_set.read(),
1688	r_dcache_save_cache_word.read(),
1689	r_dcache_save_wdata.read(),
1690	r_dcache_save_be.read());
1691	}
1692	else if (m_dreq.valid and not r_dcache_updt_req.read()) {
1693	// read DIR and DATA
1694	r_dcache.read(paddr,
1695	&cache_rdata,
1696	&cache_way,
1697	&cache_set,
1698	&cache_word,
1699	&cache_state);
1700	}
1701	else if (not m_dreq.valid and r_dcache_updt_req.read()) {
1702	// write DATA
1703	r_dcache.write(r_dcache_save_cache_way.read(),
1704	r_dcache_save_cache_set.read(),
1705	r_dcache_save_cache_word.read(),
1706	r_dcache_save_wdata.read(),
1707	r_dcache_save_be.read());
1708	}
1709	} // end dcache access
1710
1711	// DCACHE update in P1 stage can require ITLB / DTLB inval or flush
1712	if (r_dcache_updt_req.read()) {
1713	size_t way = r_dcache_save_cache_way.read();
1714	size_t set = r_dcache_save_cache_set.read();
1715
1716	if (r_dcache_in_tlb[way * m_dcache_sets + set]) {
1717	tlb_inval_required = true;
1718	r_dcache_tlb_inval_set = 0;
1719	r_dcache_tlb_inval_line = r_dcache_save_paddr.read() >>
1720	(uint32_log2(m_dcache_words << 2));
1721	r_dcache_in_tlb[way * m_dcache_sets + set] = false;
1722	}
1723	else if (r_dcache_contains_ptd[way * m_dcache_sets + set]) {
1724	r_itlb.reset();
1725	r_dtlb.reset();
1726	r_dcache_contains_ptd[way * m_dcache_sets + set] = false;
1727	}
1728
1729	#if DEBUG_DCACHE
1730	if (m_debug_dcache_fsm) {
1731	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
1732	<< " Cache update in P1 stage" << std::dec
1733	<< " / WAY = " << r_dcache_save_cache_way.read()
1734	<< " / SET = " << r_dcache_save_cache_set.read()
1735	<< " / WORD = " << r_dcache_save_cache_word.read() << std::hex
1736	<< " / WDATA = " << r_dcache_save_wdata.read()
1737	<< " / BE = " << r_dcache_save_be.read() << std::endl;
1738	}
1739	#endif
1740	} // end test TLB inval
1741
1742	// Try WBUF update in P1 stage
1743	// Miss if the write request is non cacheable, and there is a pending
1744	// non cacheable write, or if the write buffer is full.
1745	if (r_dcache_wbuf_req.read()) {
1746	bool wok = r_wbuf.write(r_dcache_save_paddr.read(),
1747	r_dcache_save_be.read(),
1748	r_dcache_save_wdata.read(),
1749	true);
1750	if (not wok) {
1751	// miss if write buffer full
1752	wbuf_write_miss = true;
1753	}
1754	} // end WBUF update
1755
1756	// Computing the response to processor,
1757	// and the next value for r_dcache_fsm
1758
1759	// itlb/dtlb invalidation self-request
1760	if (tlb_inval_required) {
1761	r_dcache_fsm_scan_save = r_dcache_fsm.read();
1762	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
1763	}
1764
1765	// processor request (READ, WRITE, LL, SC, XTN_READ, XTN_WRITE)
1766	// we don't take the processor request, and registers
1767	// are frozen in case of wbuf_write_miss
1768	else if (m_dreq.valid and not wbuf_write_miss) {
1769	// register processor request and DCACHE response
1770	r_dcache_save_vaddr = m_dreq.addr;
1771	r_dcache_save_be = m_dreq.be;
1772	r_dcache_save_wdata = m_dreq.wdata;
1773
1774	// QM debug
1775	if (m_debug_dcache_fsm) {
1776	std::cout << "(1) In DCACHE_IDLE, r_dcache_save_paddr <- " << std::hex << paddr << std::endl;
1777	}
1778	r_dcache_save_paddr = paddr;
1779	r_dcache_save_cache_way = cache_way;
1780	r_dcache_save_cache_set = cache_set;
1781	r_dcache_save_cache_word = cache_word;
1782
1783	// READ XTN requests from processor
1784	// They are executed in this DCACHE_IDLE state.
1785	// The processor must not be in user mode
1786	if (m_dreq.type == iss_t::XTN_READ) {
1787	int xtn_opcode = (int) m_dreq.addr / 4;
1788
1789	// checking processor mode:
1790	if (m_dreq.mode == iss_t::MODE_USER) {
1791	r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION;
1792	r_mmu_dbvar = m_dreq.addr;
1793	m_drsp.valid = true;
1794	m_drsp.error = true;
1795	m_drsp.rdata = 0;
1796	r_dcache_fsm = DCACHE_IDLE;
1797	}
1798	else {
1799	switch (xtn_opcode) {
1800	case iss_t::XTN_INS_ERROR_TYPE:
1801	m_drsp.rdata = r_mmu_ietr.read();
1802	m_drsp.valid = true;
1803	m_drsp.error = false;
1804	break;
1805
1806	case iss_t::XTN_DATA_ERROR_TYPE:
1807	m_drsp.rdata = r_mmu_detr.read();
1808	m_drsp.valid = true;
1809	m_drsp.error = false;
1810	break;
1811
1812	case iss_t::XTN_INS_BAD_VADDR:
1813	m_drsp.rdata = r_mmu_ibvar.read();
1814	m_drsp.valid = true;
1815	m_drsp.error = false;
1816	break;
1817
1818	case iss_t::XTN_DATA_BAD_VADDR:
1819	m_drsp.rdata = r_mmu_dbvar.read();
1820	m_drsp.valid = true;
1821	m_drsp.error = false;
1822	break;
1823
1824	case iss_t::XTN_PTPR:
1825	m_drsp.rdata = r_mmu_ptpr.read();
1826	m_drsp.valid = true;
1827	m_drsp.error = false;
1828	break;
1829
1830	case iss_t::XTN_TLB_MODE:
1831	m_drsp.rdata = r_mmu_mode.read();
1832	m_drsp.valid = true;
1833	m_drsp.error = false;
1834	break;
1835
1836	case iss_t::XTN_MMU_PARAMS:
1837	m_drsp.rdata = r_mmu_params;
1838	m_drsp.valid = true;
1839	m_drsp.error = false;
1840	break;
1841
1842	case iss_t::XTN_MMU_RELEASE:
1843	m_drsp.rdata = r_mmu_release;
1844	m_drsp.valid = true;
1845	m_drsp.error = false;
1846	break;
1847
1848	case iss_t::XTN_MMU_WORD_LO:
1849	m_drsp.rdata = r_mmu_word_lo.read();
1850	m_drsp.valid = true;
1851	m_drsp.error = false;
1852	break;
1853
1854	case iss_t::XTN_MMU_WORD_HI:
1855	m_drsp.rdata = r_mmu_word_hi.read();
1856	m_drsp.valid = true;
1857	m_drsp.error = false;
1858	break;
1859
1860	case iss_t::XTN_DATA_PADDR_EXT:
1861	m_drsp.rdata = r_dcache_paddr_ext.read();
1862	m_drsp.valid = true;
1863	m_drsp.error = false;
1864	break;
1865
1866	case iss_t::XTN_INST_PADDR_EXT:
1867	m_drsp.rdata = r_icache_paddr_ext.read();
1868	m_drsp.valid = true;
1869	m_drsp.error = false;
1870	break;
1871
1872	default:
1873	r_mmu_detr = MMU_READ_UNDEFINED_XTN;
1874	r_mmu_dbvar = m_dreq.addr;
1875	m_drsp.valid = true;
1876	m_drsp.error = true;
1877	m_drsp.rdata = 0;
1878	break;
1879	} // end switch xtn_opcode
1880	} // end else
1881	} // end if XTN_READ
1882
1883	// Handling WRITE XTN requests from processor.
1884	// They are not executed in this DCACHE_IDLE state
1885	// if they require access to the caches or the TLBs
1886	// that are already accessed.
1887	// Caches can be invalidated or flushed in user mode,
1888	// and the sync instruction can be executed in user mode
1889	else if (m_dreq.type == iss_t::XTN_WRITE) {
1890	int xtn_opcode = (int) m_dreq.addr / 4;
1891	r_dcache_xtn_opcode = xtn_opcode;
1892
1893	// checking processor mode:
1894	if ((m_dreq.mode == iss_t::MODE_USER) &&
1895	(xtn_opcode != iss_t::XTN_SYNC) &&
1896	(xtn_opcode != iss_t::XTN_DCACHE_INVAL) &&
1897	(xtn_opcode != iss_t::XTN_DCACHE_FLUSH) &&
1898	(xtn_opcode != iss_t::XTN_ICACHE_INVAL) &&
1899	(xtn_opcode != iss_t::XTN_ICACHE_FLUSH)) {
1900	r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION;
1901	r_mmu_dbvar = m_dreq.addr;
1902	m_drsp.valid = true;
1903	m_drsp.error = true;
1904	m_drsp.rdata = 0;
1905	r_dcache_fsm = DCACHE_IDLE;
1906	}
1907	else {
1908	switch (xtn_opcode) {
1909	case iss_t::XTN_PTPR: // itlb & dtlb must be flushed
1910	r_dcache_xtn_req = true;
1911	r_dcache_fsm = DCACHE_XTN_SWITCH;
1912	break;
1913
1914	case iss_t::XTN_TLB_MODE: // no cache or tlb access
1915	r_mmu_mode = m_dreq.wdata;
1916	m_drsp.valid = true;
1917	r_dcache_fsm = DCACHE_IDLE;
1918	break;
1919
1920	case iss_t::XTN_DTLB_INVAL: // dtlb access
1921	r_dcache_fsm = DCACHE_XTN_DT_INVAL;
1922	break;
1923
1924	case iss_t::XTN_ITLB_INVAL: // itlb access
1925	r_dcache_xtn_req = true;
1926	r_dcache_fsm = DCACHE_XTN_IT_INVAL;
1927	break;
1928
1929	case iss_t::XTN_DCACHE_INVAL: // dcache, dtlb & itlb access
1930	r_dcache_fsm = DCACHE_XTN_DC_INVAL_VA;
1931	break;
1932
1933	case iss_t::XTN_MMU_DCACHE_PA_INV: // dcache, dtlb & itlb access
1934	r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA;
1935	if (sizeof(paddr_t) <= 32) {
1936	assert(r_mmu_word_hi.read() == 0 &&
1937	"high bits should be 0 for 32bit paddr");
1938
1939	// QM debug
1940	if (m_debug_dcache_fsm) {
1941	std::cout << "(2) In DCACHE_IDLE, r_dcache_save_paddr <- " << std::hex << (paddr_t) r_mmu_word_lo.read() << std::endl;
1942	}
1943	r_dcache_save_paddr = (paddr_t) r_mmu_word_lo.read();
1944	}
1945	else {
1946	r_dcache_save_paddr = (paddr_t) r_mmu_word_hi.read() << 32 \|
1947	(paddr_t) r_mmu_word_lo.read();
1948	}
1949	break;
1950
1951	case iss_t::XTN_DCACHE_FLUSH: // itlb and dtlb must be reset
1952	r_dcache_flush_count = 0;
1953	r_dcache_fsm = DCACHE_XTN_DC_FLUSH;
1954	break;
1955
1956	case iss_t::XTN_ICACHE_INVAL: // icache and itlb access
1957	r_dcache_xtn_req = true;
1958	r_dcache_fsm = DCACHE_XTN_IC_INVAL_VA;
1959	break;
1960
1961	case iss_t::XTN_MMU_ICACHE_PA_INV: // icache access
1962	r_dcache_xtn_req = true;
1963	r_dcache_fsm = DCACHE_XTN_IC_INVAL_PA;
1964	break;
1965
1966	case iss_t::XTN_ICACHE_FLUSH: // icache access
1967	r_dcache_xtn_req = true;
1968	r_dcache_fsm = DCACHE_XTN_IC_FLUSH;
1969	break;
1970
1971	case iss_t::XTN_SYNC: // wait until write buffer empty
1972	r_dcache_fsm = DCACHE_XTN_SYNC;
1973	break;
1974
1975	case iss_t::XTN_MMU_WORD_LO: // no cache or tlb access
1976	r_mmu_word_lo = m_dreq.wdata;
1977	m_drsp.valid = true;
1978	r_dcache_fsm = DCACHE_IDLE;
1979	break;
1980
1981	case iss_t::XTN_MMU_WORD_HI: // no cache or tlb access
1982	r_mmu_word_hi = m_dreq.wdata;
1983	m_drsp.valid = true;
1984	r_dcache_fsm = DCACHE_IDLE;
1985	break;
1986
1987	case iss_t::XTN_MMU_LL_RESET: // no cache or tlb access
1988	r_dcache_llsc_valid = false;
1989	m_drsp.valid = true;
1990	r_dcache_fsm = DCACHE_IDLE;
1991	break;
1992
1993	case iss_t::XTN_DATA_PADDR_EXT: // no cache or tlb access
1994	r_dcache_paddr_ext = m_dreq.wdata;
1995	m_drsp.valid = true;
1996	r_dcache_fsm = DCACHE_IDLE;
1997	break;
1998
1999	case iss_t::XTN_INST_PADDR_EXT: // no cache or tlb access
2000	r_dcache_xtn_req = true;
2001	r_dcache_fsm = DCACHE_XTN_IC_PADDR_EXT;
2002	break;
2003
2004	case iss_t::XTN_ICACHE_PREFETCH: // not implemented : no action
2005	case iss_t::XTN_DCACHE_PREFETCH: // not implemented : no action
2006	m_drsp.valid = true;
2007	r_dcache_fsm = DCACHE_IDLE;
2008	break;
2009
2010	case iss_t::XTN_DEBUG_MASK: // debug mask
2011	m_debug_dcache_fsm = ((m_dreq.wdata & 0x1) != 0);
2012	m_debug_icache_fsm = ((m_dreq.wdata & 0x2) != 0);
2013	m_debug_cmd_fsm = ((m_dreq.wdata & 0x4) != 0);
2014	m_drsp.valid = true;
2015	r_dcache_fsm = DCACHE_IDLE;
2016	break;
2017
2018	default:
2019	r_mmu_detr = MMU_WRITE_UNDEFINED_XTN;
2020	r_mmu_dbvar = m_dreq.addr;
2021	m_drsp.valid = true;
2022	m_drsp.error = true;
2023	r_dcache_fsm = DCACHE_IDLE;
2024	break;
2025	} // end switch xtn_opcode
2026	} // end else
2027	} // end if XTN_WRITE
2028
2029	// Handling processor requests to address space (READ/WRITE/LL/SC)
2030	// The dtlb and dcache can be activated or not.
2031	// We compute the cacheability, and check processor request validity:
2032	// - If DTLB not activated : cacheability is defined by the segment table,
2033	// and there is no access rights checking.
2034	// - If DTLB activated : cacheability is defined by the C bit in the PTE,
2035	// and the U & W bits of the PTE are checked, as well as the DTLB hit.
2036	// Jumps to the TLB_MISS sub-fsm in case of dtlb miss.
2037	else {
2038	bool valid_req;
2039	bool cacheable;
2040
2041	if (not (r_mmu_mode.read() & DATA_TLB_MASK)) {
2042	// dtlb not activated
2043	valid_req = true;
2044
2045	if (not (r_mmu_mode.read() & DATA_CACHE_MASK)) {
2046	cacheable = false;
2047	}
2048	else {
2049	cacheable = m_cacheability_table[(uint64_t) m_dreq.addr];
2050	}
2051	}
2052	else {
2053	// dtlb activated
2054	if (tlb_hit) {
2055	// cacheability
2056	if (not (r_mmu_mode.read() & DATA_CACHE_MASK)) {
2057	cacheable = false;
2058	}
2059	else {
2060	cacheable = tlb_flags.c;
2061	}
2062
2063	// access rights checking
2064	if (not tlb_flags.u and (m_dreq.mode == iss_t::MODE_USER)) {
2065	if ((m_dreq.type == iss_t::DATA_READ) or
2066	(m_dreq.type == iss_t::DATA_LL)) {
2067	r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION;
2068	}
2069	else {
2070	r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION;
2071	}
2072	valid_req = false;
2073	r_mmu_dbvar = m_dreq.addr;
2074	m_drsp.valid = true;
2075	m_drsp.error = true;
2076	m_drsp.rdata = 0;
2077	#if DEBUG_DCACHE
2078	if (m_debug_dcache_fsm) {
2079	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
2080	<< " HIT in dtlb, but privilege violation" << std::endl;
2081	}
2082	#endif
2083	}
2084	else if (not tlb_flags.w and
2085	((m_dreq.type == iss_t::DATA_WRITE) or
2086	(m_dreq.type == iss_t::DATA_SC))) {
2087	r_mmu_detr = MMU_WRITE_ACCES_VIOLATION;
2088	valid_req = false;
2089	r_mmu_dbvar = m_dreq.addr;
2090	m_drsp.valid = true;
2091	m_drsp.error = true;
2092	m_drsp.rdata = 0;
2093	#if DEBUG_DCACHE
2094	if (m_debug_dcache_fsm) {
2095	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
2096	<< " HIT in dtlb, but writable violation" << std::endl;
2097	}
2098	#endif
2099	}
2100	else {
2101	valid_req = true;
2102	}
2103	}
2104	else {
2105	// tlb miss
2106	valid_req = false;
2107	r_dcache_tlb_vaddr = m_dreq.addr;
2108	r_dcache_tlb_ins = false;
2109	r_dcache_fsm = DCACHE_TLB_MISS;
2110	}
2111	} // end DTLB activated
2112
2113	if (valid_req) {
2114	// processor request is valid (after MMU check)
2115	// READ request
2116	// The read requests are taken only if there is no cache update.
2117	// We request a VCI transaction to CMD FSM if miss or uncachable
2118
2119	if (((m_dreq.type == iss_t::DATA_READ))
2120	and not r_dcache_updt_req.read()) {
2121	if (cacheable) {
2122	// cacheable read
2123	if (cache_state == CACHE_SLOT_STATE_INVALID) {
2124	// cache miss
2125	// request a VCI DMISS transaction
2126	r_dcache_vci_paddr = paddr;
2127	r_dcache_vci_miss_req = true;
2128	r_dcache_miss_type = PROC_MISS;
2129	r_dcache_fsm = DCACHE_MISS_SELECT;
2130	#if DEBUG_DCACHE
2131	if (m_debug_dcache_fsm) {
2132	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
2133	<< " READ MISS in dcache"
2134	<< " / PADDR = " << std::hex << paddr << std::endl;
2135	}
2136	#endif
2137	}
2138	else {
2139	// cache hit
2140	// returns data to processor
2141	m_drsp.valid = true;
2142	m_drsp.error = false;
2143	m_drsp.rdata = cache_rdata;
2144	#if DEBUG_DCACHE
2145	if (m_debug_dcache_fsm)
2146	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
2147	<< " READ HIT in dcache"
2148	<< " : PADDR = " << std::hex << paddr
2149	<< " / DATA = " << std::hex << cache_rdata << std::endl;
2150	#endif
2151	}
2152	}
2153	else {
2154	// uncacheable read
2155	r_dcache_vci_paddr = paddr;
2156	r_dcache_vci_unc_be = m_dreq.be;
2157	r_dcache_vci_unc_write = false;
2158	r_dcache_vci_unc_req = true;
2159	r_dcache_fsm = DCACHE_UNC_WAIT;
2160	#if DEBUG_DCACHE
2161	if (m_debug_dcache_fsm) {
2162	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
2163	<< " READ UNCACHEABLE in dcache"
2164	<< " / PADDR = " << std::hex << paddr << std::endl;
2165	}
2166	#endif
2167	}
2168	} // end READ
2169
2170	// LL request (non cachable)
2171	// We request a VCI LL transaction to CMD FSM and register
2172	// the LL/SC operation in llsc buffer.
2173	else if (m_dreq.type == iss_t::DATA_LL) {
2174	// register paddr in LLSC buffer
2175	r_dcache_llsc_paddr = paddr;
2176	r_dcache_llsc_count = LLSC_TIMEOUT;
2177	r_dcache_llsc_valid = true;
2178
2179	// request an LL VCI transaction and go to DCACHE_LL_WAIT state
2180	r_dcache_vci_ll_req = true;
2181	r_dcache_vci_paddr = paddr;
2182	r_dcache_ll_rsp_count = 0;
2183	r_dcache_fsm = DCACHE_LL_WAIT;
2184
2185	} // end LL
2186
2187	// WRITE request:
2188	// If the TLB is activated and the PTE Dirty bit is not set, we stall
2189	// the processor and set the Dirty bit before handling the write request,
2190	// going to the DCACHE_DIRTY_GT_PTE state.
2191	// If we don't need to set the Dirty bit, we can acknowledge
2192	// the processor request, as the write arguments (including the
2193	// physical address) are registered in r_dcache_save registers,
2194	// and the write will be done in the P1 pipeline stage.
2195	else if (m_dreq.type == iss_t::DATA_WRITE) {
2196	if ((r_mmu_mode.read() & DATA_TLB_MASK) and not tlb_flags.d) {
2197	// Dirty bit must be set
2198	// The PTE physical address is obtained from the nline value (dtlb),
2199	// and from the virtual address (word index)
2200	if (tlb_flags.b) {
2201	// PTE1
2202	r_dcache_dirty_paddr = (paddr_t) (tlb_nline * (m_dcache_words << 2)) \|
2203	(paddr_t) ((m_dreq.addr >> 19) & 0x3c);
2204	}
2205	else {
2206	// PTE2
2207	r_dcache_dirty_paddr = (paddr_t) (tlb_nline * (m_dcache_words << 2)) \|
2208	(paddr_t) ((m_dreq.addr >> 9) & 0x38);
2209	}
2210	r_dcache_fsm = DCACHE_DIRTY_GET_PTE;
2211	}
2212	else {
2213	// Write request accepted
2214	// cleaning llsc buffer if address matching
2215	if (paddr == r_dcache_llsc_paddr.read()) {
2216	r_dcache_llsc_valid = false;
2217	}
2218
2219	if (not cacheable) {
2220	r_dcache_vci_paddr = paddr;
2221	r_dcache_vci_wdata = m_dreq.wdata;
2222	r_dcache_vci_unc_write = true;
2223	r_dcache_vci_unc_be = m_dreq.be;
2224	r_dcache_vci_unc_req = true;
2225	r_dcache_fsm = DCACHE_UNC_WAIT;
2226	}
2227	else {
2228	// response to processor
2229	m_drsp.valid = true;
2230	// activating P1 stage
2231	wbuf_request = true;
2232	updt_request = (cache_state == CACHE_SLOT_STATE_VALID);
2233	}
2234	}
2235	} // end WRITE
2236
2237	// SC request:
2238	// If the TLB is activated and the PTE Dirty bit is not set, we stall
2239	// the processor and set the Dirty bit before handling the write request,
2240	// going to the DCACHE_DIRTY_GT_PTE state.
2241	// If we don't need to set the Dirty bit, we test the llsc buffer:
2242	// If failure, we send a negative response to processor.
2243	// If success, we request a SC transaction to CMD FSM and go
2244	// to DCACHE_SC_WAIT state.
2245	// We don't check a possible write hit in dcache, as the cache update
2246	// is done by the coherence transaction induced by the SC...
2247	else if (m_dreq.type == iss_t::DATA_SC) {
2248	if ((r_mmu_mode.read() & DATA_TLB_MASK) and not tlb_flags.d) {
2249	// Dirty bit must be set
2250	// The PTE physical address is obtained from the nline value (dtlb),
2251	// and the word index (virtual address)
2252	if (tlb_flags.b) {
2253	// PTE1
2254	r_dcache_dirty_paddr = (paddr_t) (tlb_nline * (m_dcache_words << 2)) \|
2255	(paddr_t) ((m_dreq.addr >> 19) & 0x3c);
2256	}
2257	else {
2258	// PTE2
2259	r_dcache_dirty_paddr = (paddr_t) (tlb_nline * (m_dcache_words << 2)) \|
2260	(paddr_t) ((m_dreq.addr >> 9) & 0x38);
2261	}
2262	r_dcache_fsm = DCACHE_DIRTY_GET_PTE;
2263	m_drsp.valid = false;
2264	m_drsp.error = false;
2265	m_drsp.rdata = 0;
2266	}
2267	else {
2268	// SC request accepted
2269	// checking local success
2270	if (r_dcache_llsc_valid.read() and
2271	(r_dcache_llsc_paddr.read() == paddr)) {
2272	// local success
2273	// request an SC CMD and go to DCACHE_SC_WAIT state
2274	r_dcache_vci_paddr = paddr;
2275	r_dcache_vci_sc_req = true;
2276	r_dcache_vci_sc_data = m_dreq.wdata;
2277	r_dcache_fsm = DCACHE_SC_WAIT;
2278	}
2279	else {
2280	// local fail
2281	m_drsp.valid = true;
2282	m_drsp.error = false;
2283	m_drsp.rdata = 0x1;
2284	}
2285	}
2286	} // end SC
2287	} // end valid_req
2288	} // end if read/write/ll/sc request
2289	} // end processor request
2290
2291	// itlb miss request
2292	else if (r_icache_tlb_miss_req.read() and not wbuf_write_miss) {
2293	r_dcache_tlb_ins = true;
2294	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
2295	r_dcache_fsm = DCACHE_TLB_MISS;
2296	}
2297
2298	// Computing requests for P1 stage : r_dcache_wbuf_req & r_dcache_updt_req
2299	r_dcache_updt_req = updt_request;
2300	r_dcache_wbuf_req = wbuf_request or (r_dcache_wbuf_req.read() and wbuf_write_miss);
2301	break;
2302	}
2303	/////////////////////
2304	case DCACHE_TLB_MISS: // This is the entry point for the sub-fsm handling all tlb miss.
2305	// Input arguments are:
2306	// - r_dcache_tlb_vaddr
2307	// - r_dcache_tlb_ins (true when itlb miss)
2308	// The sub-fsm access the dcache to find the missing TLB entry,
2309	// and activates the cache miss procedure in case of miss.
2310	// It bypass the first level page table access if possible.
2311	// It uses atomic access to update the R/L access bits
2312	// in the page table if required.
2313	// It directly updates the itlb or dtlb, and writes into the
2314	// r_mmu_ins_* or r_mmu_data* error reporting registers.
2315	{
2316	uint32_t ptba = 0;
2317	bool bypass;
2318	paddr_t pte_paddr;
2319
2320	// evaluate bypass in order to skip first level page table access
2321	if (r_dcache_tlb_ins.read()) {
2322	// itlb miss
2323	bypass = r_itlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba);
2324	}
2325	else {
2326	// dtlb miss
2327	bypass = r_dtlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba);
2328	}
2329
2330	if (not bypass) {
2331	// Try to read PTE1/PTD1 in dcache
2332	pte_paddr = (((paddr_t) r_mmu_ptpr.read()) << (INDEX1_NBITS + 2)) \|
2333	((((paddr_t) r_dcache_tlb_vaddr.read()) >> PAGE_M_NBITS) << 2);
2334	r_dcache_tlb_paddr = pte_paddr;
2335	r_dcache_fsm = DCACHE_TLB_PTE1_GET;
2336	}
2337	else {
2338	// Try to read PTE2 in dcache
2339	pte_paddr = (paddr_t) ptba << PAGE_K_NBITS \|
2340	(paddr_t) (r_dcache_tlb_vaddr.read() & PTD_ID2_MASK) >> (PAGE_K_NBITS - 3);
2341	r_dcache_tlb_paddr = pte_paddr;
2342	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
2343	}
2344
2345	#if DEBUG_DCACHE
2346	if (m_debug_dcache_fsm) {
2347	if (r_dcache_tlb_ins.read()) {
2348	std::cout << " <PROC " << name() << " DCACHE_TLB_MISS> ITLB miss";
2349	}
2350	else {
2351	std::cout << " <PROC " << name() << " DCACHE_TLB_MISS> DTLB miss";
2352	std::cout << " / VADDR = " << std::hex << r_dcache_tlb_vaddr.read()
2353	<< " / ptpr = " << (((paddr_t)r_mmu_ptpr.read()) << (INDEX1_NBITS+2))
2354	<< " / BYPASS = " << bypass
2355	<< " / PTE_ADR = " << pte_paddr << std::endl;
2356	}
2357	}
2358	#endif
2359
2360	break;
2361	}
2362	/////////////////////////
2363	case DCACHE_TLB_PTE1_GET: // try to read a PT1 entry in dcache
2364	{
2365	uint32_t entry;
2366	size_t way;
2367	size_t set;
2368	size_t word;
2369	int cache_state;
2370
2371	r_dcache.read(r_dcache_tlb_paddr.read(),
2372	&entry,
2373	&way,
2374	&set,
2375	&word,
2376	&cache_state);
2377
2378	if (cache_state == CACHE_SLOT_STATE_VALID) {
2379	// hit in dcache
2380	if (not (entry & PTE_V_MASK)) {
2381	// unmapped
2382	if (r_dcache_tlb_ins.read()) {
2383	r_mmu_ietr = MMU_READ_PT1_UNMAPPED;
2384	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
2385	r_icache_tlb_miss_req = false;
2386	r_icache_tlb_rsp_error = true;
2387	}
2388	else {
2389	r_mmu_detr = MMU_READ_PT1_UNMAPPED;
2390	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
2391	m_drsp.valid = true;
2392	m_drsp.error = true;
2393	}
2394	r_dcache_fsm = DCACHE_IDLE;
2395
2396	#if DEBUG_DCACHE
2397	if (m_debug_dcache_fsm) {
2398	std::cout << " <PROC " << name()
2399	<< " DCACHE_TLB_PTE1_GET> HIT in dcache, but unmapped"
2400	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
2401	<< std::dec << " / way = " << way
2402	<< std::dec << " / set = " << set
2403	<< std::dec << " / word = " << word
2404	<< std::hex << " / PTE1 = " << entry << std::endl;
2405	}
2406	#endif
2407	}
2408	else if (entry & PTE_T_MASK) {
2409	// PTD : me must access PT2
2410	// mark the cache line ac containing a PTD
2411	r_dcache_contains_ptd[m_dcache_sets * way + set] = true;
2412
2413	// register bypass
2414	if (r_dcache_tlb_ins.read()) {
2415	// itlb
2416	r_itlb.set_bypass(r_dcache_tlb_vaddr.read(),
2417	entry & ((1 << (m_paddr_nbits - PAGE_K_NBITS)) - 1),
2418	r_dcache_tlb_paddr.read() / (m_icache_words << 2));
2419	}
2420	else {
2421	// dtlb
2422	r_dtlb.set_bypass(r_dcache_tlb_vaddr.read(),
2423	entry & ((1 << (m_paddr_nbits - PAGE_K_NBITS)) - 1),
2424	r_dcache_tlb_paddr.read() / (m_dcache_words << 2));
2425	}
2426	r_dcache_tlb_paddr =
2427	(paddr_t) (entry & ((1 << (m_paddr_nbits - PAGE_K_NBITS)) - 1)) << PAGE_K_NBITS \|
2428	(paddr_t) (((r_dcache_tlb_vaddr.read() & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3);
2429	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
2430
2431	#if DEBUG_DCACHE
2432	if (m_debug_dcache_fsm) {
2433	std::cout << " <PROC " << name()
2434	<< " DCACHE_TLB_PTE1_GET> HIT in dcache"
2435	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
2436	<< std::dec << " / way = " << way
2437	<< std::dec << " / set = " << set
2438	<< std::dec << " / word = " << word
2439	<< std::hex << " / PTD = " << entry << std::endl;
2440	}
2441	#endif
2442	}
2443	else {
2444	// PTE1 : we must update the TLB
2445	r_dcache_in_tlb[m_icache_sets * way + set] = true;
2446	r_dcache_tlb_pte_flags = entry;
2447	r_dcache_tlb_cache_way = way;
2448	r_dcache_tlb_cache_set = set;
2449	r_dcache_tlb_cache_word = word;
2450	r_dcache_fsm = DCACHE_TLB_PTE1_SELECT;
2451
2452	#if DEBUG_DCACHE
2453	if (m_debug_dcache_fsm) {
2454	std::cout << " <PROC " << name()
2455	<< " DCACHE_TLB_PTE1_GET> HIT in dcache"
2456	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
2457	<< std::dec << " / way = " << way
2458	<< std::dec << " / set = " << set
2459	<< std::dec << " / word = " << word
2460	<< std::hex << " / PTE1 = " << entry << std::endl;
2461	}
2462	#endif
2463	}
2464	}
2465	else {
2466	// we must load the missing cache line in dcache
2467	r_dcache_vci_miss_req = true;
2468	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
2469
2470	// QM debug
2471	if (m_debug_dcache_fsm) {
2472	std::cout << "(3) In DCACHE_TLB_PTE1_GET, r_dcache_save_paddr <- " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
2473	}
2474
2475	r_dcache_save_paddr = r_dcache_tlb_paddr.read();
2476	r_dcache_miss_type = PTE1_MISS;
2477	r_dcache_fsm = DCACHE_MISS_SELECT;
2478
2479	#if DEBUG_DCACHE
2480	if (m_debug_dcache_fsm) {
2481	std::cout << " <PROC " << name()
2482	<< " DCACHE_TLB_PTE1_GET> MISS in dcache:"
2483	<< " PTE1 address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
2484	}
2485	#endif
2486	}
2487	break;
2488	}
2489	////////////////////////////
2490	case DCACHE_TLB_PTE1_SELECT: // select a slot for PTE1
2491	{
2492	size_t way;
2493	size_t set;
2494
2495	if (r_dcache_tlb_ins.read()) {
2496	r_itlb.select(r_dcache_tlb_vaddr.read(),
2497	true, // PTE1
2498	&way,
2499	&set);
2500	}
2501	else {
2502	r_dtlb.select(r_dcache_tlb_vaddr.read(),
2503	true, // PTE1
2504	&way,
2505	&set);
2506	}
2507	r_dcache_tlb_way = way;
2508	r_dcache_tlb_set = set;
2509	r_dcache_fsm = DCACHE_TLB_PTE1_UPDT;
2510
2511	#if DEBUG_DCACHE
2512	if (m_debug_dcache_fsm) {
2513	if (r_dcache_tlb_ins.read()) {
2514	std::cout << " <PROC " << name() << " DCACHE_TLB_PTE1_SELECT> Select a slot in ITLB:";
2515	}
2516	else {
2517	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_SELECT> Select a slot in DTLB:";
2518	}
2519	std::cout << " way = " << std::dec << way << " / set = " << set << std::endl;
2520	}
2521	#endif
2522	break;
2523	}
2524	//////////////////////////
2525	case DCACHE_TLB_PTE1_UPDT: // write a new PTE1 in tlb after testing the L/R bit
2526	// - if L/R bit already set, exit the sub-fsm.
2527	// - if not, we update the page table but we dont write
2528	// neither in DCACHE, nor in TLB, as this will be done by
2529	// the coherence mechanism.
2530	{
2531	paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words) + 2);
2532	uint32_t pte = r_dcache_tlb_pte_flags.read();
2533	bool pt_updt = false;
2534	bool local = true;
2535
2536	// We should compute the access locality:
2537	// The PPN MSB bits define the destination cluster index.
2538	// The m_srcid MSB bits define the source cluster index.
2539	// The number of bits to compare depends on the number of clusters,
2540	// and can be obtained in the mapping table.
2541	// As long as this computation is not done, all access are local.
2542
2543	if (local) {
2544	// local access
2545	if (not ((pte & PTE_L_MASK) == PTE_L_MASK)) {
2546	// we must set the L bit
2547	pt_updt = true;
2548	r_dcache_vci_cas_old = pte;
2549	r_dcache_vci_cas_new = pte \| PTE_L_MASK;
2550	pte = pte \| PTE_L_MASK;
2551	r_dcache_tlb_pte_flags = pte;
2552	}
2553	}
2554	else {
2555	// remote access
2556	if (not ((pte & PTE_R_MASK) == PTE_R_MASK)) {
2557	// we must set the R bit
2558	pt_updt = true;
2559	r_dcache_vci_cas_old = pte;
2560	r_dcache_vci_cas_new = pte \| PTE_R_MASK;
2561	pte = pte \| PTE_R_MASK;
2562	r_dcache_tlb_pte_flags = pte;
2563	}
2564	}
2565
2566	if (not pt_updt) {
2567	// update TLB and return
2568	if (r_dcache_tlb_ins.read()) {
2569	r_itlb.write(true, // 2M page
2570	pte,
2571	0, // argument unused for a PTE1
2572	r_dcache_tlb_vaddr.read(),
2573	r_dcache_tlb_way.read(),
2574	r_dcache_tlb_set.read(),
2575	nline);
2576
2577	#if DEBUG_DCACHE
2578	if (m_debug_dcache_fsm) {
2579	std::cout << " <PROC " << name()
2580	<< " DCACHE_TLB_PTE1_UPDT> write PTE1 in ITLB"
2581	<< " / set = " << std::dec << r_dcache_tlb_set.read()
2582	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
2583	r_itlb.printTrace();
2584	}
2585	#endif
2586	}
2587	else {
2588	r_dtlb.write(true, // 2M page
2589	pte,
2590	0, // argument unused for a PTE1
2591	r_dcache_tlb_vaddr.read(),
2592	r_dcache_tlb_way.read(),
2593	r_dcache_tlb_set.read(),
2594	nline);
2595	#if DEBUG_DCACHE
2596	if (m_debug_dcache_fsm) {
2597	std::cout << " <PROC " << name()
2598	<< " DCACHE_TLB_PTE1_UPDT> write PTE1 in DTLB"
2599	<< " / set = " << std::dec << r_dcache_tlb_set.read()
2600	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
2601	r_dtlb.printTrace();
2602	}
2603	#endif
2604	}
2605	r_dcache_fsm = DCACHE_TLB_RETURN;
2606	}
2607	else {
2608	// update page table but not TLB
2609	r_dcache_fsm = DCACHE_TLB_LR_UPDT;
2610
2611	#if DEBUG_DCACHE
2612	if (m_debug_dcache_fsm) {
2613	std::cout << " <PROC " << name()
2614	<< " DCACHE_TLB_PTE1_UPDT> L/R bit update required"
2615	<< std::endl;
2616	}
2617	#endif
2618	}
2619	break;
2620	}
2621	/////////////////////////
2622	case DCACHE_TLB_PTE2_GET: // Try to get a PTE2 (64 bits) in the dcache
2623	{
2624	uint32_t pte_flags;
2625	uint32_t pte_ppn;
2626	size_t way;
2627	size_t set;
2628	size_t word;
2629	int cache_state;
2630
2631	r_dcache.read(r_dcache_tlb_paddr.read(),
2632	&pte_flags,
2633	&pte_ppn,
2634	&way,
2635	&set,
2636	&word,
2637	&cache_state);
2638
2639	if (cache_state == CACHE_SLOT_STATE_VALID) {
2640	// hit in dcache
2641	if (not (pte_flags & PTE_V_MASK)) {
2642	// unmapped
2643	if (r_dcache_tlb_ins.read()) {
2644	r_mmu_ietr = MMU_READ_PT2_UNMAPPED;
2645	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
2646	r_icache_tlb_miss_req = false;
2647	r_icache_tlb_rsp_error = true;
2648	}
2649	else {
2650	r_mmu_detr = MMU_READ_PT2_UNMAPPED;
2651	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
2652	m_drsp.valid = true;
2653	m_drsp.error = true;
2654	}
2655	r_dcache_fsm = DCACHE_IDLE;
2656
2657	#if DEBUG_DCACHE
2658	if (m_debug_dcache_fsm) {
2659	std::cout << " <PROC " << name()
2660	<< " DCACHE_TLB_PTE2_GET> HIT in dcache, but PTE unmapped"
2661	<< " PTE_FLAGS = " << std::hex << pte_flags
2662	<< " PTE_PPN = " << std::hex << pte_ppn << std::endl;
2663	}
2664	#endif
2665	}
2666	else {
2667	// mapped : we must update the TLB
2668	r_dcache_in_tlb[m_dcache_sets * way + set] = true;
2669	r_dcache_tlb_pte_flags = pte_flags;
2670	r_dcache_tlb_pte_ppn = pte_ppn;
2671	r_dcache_tlb_cache_way = way;
2672	r_dcache_tlb_cache_set = set;
2673	r_dcache_tlb_cache_word = word;
2674	r_dcache_fsm = DCACHE_TLB_PTE2_SELECT;
2675
2676	#if DEBUG_DCACHE
2677	if (m_debug_dcache_fsm) {
2678	std::cout << " <PROC " << name()
2679	<< " DCACHE_TLB_PTE2_GET> HIT in dcache:"
2680	<< " PTE_FLAGS = " << std::hex << pte_flags
2681	<< " PTE_PPN = " << std::hex << pte_ppn << std::endl;
2682	}
2683	#endif
2684	}
2685	}
2686	else {
2687	// we must load the missing cache line in dcache
2688	r_dcache_fsm = DCACHE_MISS_SELECT;
2689	r_dcache_vci_miss_req = true;
2690	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
2691
2692	// QM debug
2693	if (m_debug_dcache_fsm) {
2694	std::cout << "(4) In DCACHE_TLB_PTE2_GET, r_dcache_save_paddr <- " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
2695	}
2696	r_dcache_save_paddr = r_dcache_tlb_paddr.read();
2697	r_dcache_miss_type = PTE2_MISS;
2698
2699	#if DEBUG_DCACHE
2700	if (m_debug_dcache_fsm) {
2701	std::cout << " <PROC " << name()
2702	<< " DCACHE_TLB_PTE2_GET> MISS in dcache:"
2703	<< " PTE address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
2704	}
2705	#endif
2706	}
2707	break;
2708	}
2709	////////////////////////////
2710	case DCACHE_TLB_PTE2_SELECT: // select a slot for PTE2
2711	{
2712	size_t way;
2713	size_t set;
2714
2715	if (r_dcache_tlb_ins.read()) {
2716	r_itlb.select(r_dcache_tlb_vaddr.read(),
2717	false, // PTE2
2718	&way,
2719	&set);
2720	}
2721	else {
2722	r_dtlb.select(r_dcache_tlb_vaddr.read(),
2723	false, // PTE2
2724	&way,
2725	&set);
2726	}
2727
2728	#if DEBUG_DCACHE
2729	if (m_debug_dcache_fsm) {
2730	if (r_dcache_tlb_ins.read()) {
2731	std::cout << " <PROC " << name()
2732	<< " DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB:";
2733	}
2734	else {
2735	std::cout << " <PROC " << name()
2736	<< " DCACHE_TLB_PTE2_SELECT> Select a slot in DTLB:";
2737	}
2738	std::cout << " way = " << std::dec << way
2739	<< " / set = " << set << std::endl;
2740	}
2741	#endif
2742	r_dcache_tlb_way = way;
2743	r_dcache_tlb_set = set;
2744	r_dcache_fsm = DCACHE_TLB_PTE2_UPDT;
2745	break;
2746	}
2747	//////////////////////////
2748	case DCACHE_TLB_PTE2_UPDT: // write a new PTE2 in tlb after testing the L/R bit
2749	// - if L/R bit already set, exit the sub-fsm.
2750	// - if not, we update the page table but we dont write
2751	// neither in DCACHE, nor in TLB, as this will be done by
2752	// the coherence mechanism.
2753	{
2754	paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words) + 2);
2755	uint32_t pte_flags = r_dcache_tlb_pte_flags.read();
2756	uint32_t pte_ppn = r_dcache_tlb_pte_ppn.read();
2757	bool pt_updt = false;
2758	bool local = true;
2759
2760	// We should compute the access locality:
2761	// The PPN MSB bits define the destination cluster index.
2762	// The m_srcid MSB bits define the source cluster index.
2763	// The number of bits to compare depends on the number of clusters,
2764	// and can be obtained in the mapping table.
2765	// As long as this computation is not done, all access are local.
2766
2767	if (local) {
2768	// local access
2769	if (not ((pte_flags & PTE_L_MASK) == PTE_L_MASK)) {
2770	// we must set the L bit
2771	pt_updt = true;
2772	r_dcache_vci_cas_old = pte_flags;
2773	r_dcache_vci_cas_new = pte_flags \| PTE_L_MASK;
2774	pte_flags = pte_flags \| PTE_L_MASK;
2775	r_dcache_tlb_pte_flags = pte_flags;
2776	}
2777	}
2778	else {
2779	// remote access
2780	if (not ((pte_flags & PTE_R_MASK) == PTE_R_MASK)) {
2781	// we must set the R bit
2782	pt_updt = true;
2783	r_dcache_vci_cas_old = pte_flags;
2784	r_dcache_vci_cas_new = pte_flags \| PTE_R_MASK;
2785	pte_flags = pte_flags \| PTE_R_MASK;
2786	r_dcache_tlb_pte_flags = pte_flags;
2787	}
2788	}
2789
2790	if (not pt_updt) {
2791	// update TLB
2792	if (r_dcache_tlb_ins.read()) {
2793	r_itlb.write(false, // 4K page
2794	pte_flags,
2795	pte_ppn,
2796	r_dcache_tlb_vaddr.read(),
2797	r_dcache_tlb_way.read(),
2798	r_dcache_tlb_set.read(),
2799	nline);
2800
2801	#if DEBUG_DCACHE
2802	if (m_debug_dcache_fsm) {
2803	std::cout << " <PROC " << name()
2804	<< " DCACHE_TLB_PTE2_UPDT> write PTE2 in ITLB"
2805	<< " / set = " << std::dec << r_dcache_tlb_set.read()
2806	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
2807	r_itlb.printTrace();
2808	}
2809	#endif
2810	}
2811	else {
2812	r_dtlb.write(false, // 4K page
2813	pte_flags,
2814	pte_ppn,
2815	r_dcache_tlb_vaddr.read(),
2816	r_dcache_tlb_way.read(),
2817	r_dcache_tlb_set.read(),
2818	nline);
2819
2820	#if DEBUG_DCACHE
2821	if (m_debug_dcache_fsm) {
2822	std::cout << " <PROC " << name()
2823	<< " DCACHE_TLB_PTE2_UPDT> write PTE2 in DTLB"
2824	<< " / set = " << std::dec << r_dcache_tlb_set.read()
2825	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
2826	r_dtlb.printTrace();
2827	}
2828	#endif
2829
2830	}
2831	r_dcache_fsm = DCACHE_TLB_RETURN;
2832	}
2833	else {
2834	// update page table but not TLB
2835	r_dcache_fsm = DCACHE_TLB_LR_UPDT; // dcache and page table update
2836
2837	#if DEBUG_DCACHE
2838	if (m_debug_dcache_fsm) {
2839	std::cout << " <PROC " << name()
2840	<< " DCACHE_TLB_PTE2_UPDT> L/R bit update required" << std::endl;
2841	}
2842	#endif
2843	}
2844	break;
2845	}
2846	////////////////////////
2847	case DCACHE_TLB_LR_UPDT: // request a CAS transaction to update L/R bit
2848	{
2849	#if DEBUG_DCACHE
2850	if (m_debug_dcache_fsm) {
2851	std::cout << " <PROC " << name()
2852	<< " DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit" << std::endl;
2853	}
2854	#endif
2855	// r_dcache_vci_cas_old & r_dcache_vci_cas_new registers are already set
2856	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
2857
2858	// checking llsc reservation buffer
2859	if (r_dcache_llsc_paddr.read() == r_dcache_tlb_paddr.read()) {
2860	r_dcache_llsc_valid = false;
2861	}
2862
2863	// request a CAS CMD and go to DCACHE_TLB_LR_WAIT state
2864	r_dcache_vci_cas_req = true;
2865	r_dcache_fsm = DCACHE_TLB_LR_WAIT;
2866	break;
2867	}
2868	////////////////////////
2869	case DCACHE_TLB_LR_WAIT: // Waiting the response to SC transaction for DIRTY bit.
2870	// We consume the response in rsp FIFO,
2871	// and exit the sub-fsm, but we don't
2872	// analyse the response, because we don't
2873	// care if the L/R bit update is not done.
2874	// We must take the coherence requests because
2875	// there is a risk of dead-lock
2876
2877	{
2878	if (r_vci_rsp_data_error.read()) {
2879	std::cout << "BUS ERROR in DCACHE_TLB_LR_WAIT state" << std::endl;
2880	std::cout << "This should not happen in this state" << std::endl;
2881	exit(0);
2882	}
2883	else if (r_vci_rsp_fifo_dcache.rok()) {
2884	// response available
2885	#if DEBUG_DCACHE
2886	if (m_debug_dcache_fsm) {
2887	std::cout << " <PROC " << name() << " DCACHE_TLB_LR_WAIT> SC response received" << std::endl;
2888	}
2889	#endif
2890	vci_rsp_fifo_dcache_get = true;
2891	r_dcache_fsm = DCACHE_TLB_RETURN;
2892	}
2893	break;
2894	}
2895	///////////////////////
2896	case DCACHE_TLB_RETURN: // return to caller depending on tlb miss type
2897	{
2898	#if DEBUG_DCACHE
2899	if (m_debug_dcache_fsm) {
2900	std::cout << " <PROC " << name()
2901	<< " DCACHE_TLB_RETURN> TLB MISS completed" << std::endl;
2902	}
2903	#endif
2904	if (r_dcache_tlb_ins.read()) {
2905	r_icache_tlb_miss_req = false;
2906	}
2907	r_dcache_fsm = DCACHE_IDLE;
2908	break;
2909	}
2910	///////////////////////
2911	case DCACHE_XTN_SWITCH: // The r_ptpr registers must be written,
2912	// and both itlb and dtlb must be flushed.
2913	// Caution : the itlb miss requests must be taken
2914	// to avoid dead-lock in case of simultaneous ITLB miss
2915	// Caution : the clack and cc requests must be taken
2916	// to avoid dead-lock
2917	{
2918	// itlb miss request
2919	if (r_icache_tlb_miss_req.read()) {
2920	r_dcache_tlb_ins = true;
2921	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
2922	r_dcache_fsm = DCACHE_TLB_MISS;
2923	break;
2924	}
2925
2926	if (not r_dcache_xtn_req.read()) {
2927	r_dtlb.flush();
2928	r_mmu_ptpr = m_dreq.wdata;
2929	r_dcache_fsm = DCACHE_IDLE;
2930	m_drsp.valid = true;
2931	}
2932	break;
2933	}
2934	/////////////////////
2935	case DCACHE_XTN_SYNC: // waiting until write buffer empty
2936	// The coherence request must be taken
2937	// as there is a risk of dead-lock
2938	{
2939	if (r_wbuf.empty()) {
2940	m_drsp.valid = true;
2941	r_dcache_fsm = DCACHE_IDLE;
2942	}
2943	break;
2944	}
2945	////////////////////////
2946	case DCACHE_XTN_IC_FLUSH: // Waiting completion of an XTN request to the ICACHE FSM
2947	case DCACHE_XTN_IC_INVAL_VA: // Caution : the itlb miss requests must be taken
2948	case DCACHE_XTN_IC_INVAL_PA: // because the XTN_ICACHE_INVAL request to icache
2949	case DCACHE_XTN_IC_PADDR_EXT: // can generate an itlb miss,
2950	case DCACHE_XTN_IT_INVAL: // and because it can exist a simultaneous ITLB miss
2951
2952	{
2953	// itlb miss request
2954	if (r_icache_tlb_miss_req.read()) {
2955	r_dcache_tlb_ins = true;
2956	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
2957	r_dcache_fsm = DCACHE_TLB_MISS;
2958	break;
2959	}
2960
2961	// test if XTN request to icache completed
2962	if (not r_dcache_xtn_req.read()) {
2963	r_dcache_fsm = DCACHE_IDLE;
2964	m_drsp.valid = true;
2965	}
2966	break;
2967	}
2968	/////////////////////////
2969	case DCACHE_XTN_DC_FLUSH: // Invalidate sequentially all cache lines, using
2970	// r_dcache_flush_count as a slot counter,
2971	// looping in this state until all slots have been visited.
2972	// It can require two cycles per slot:
2973	// We test here the slot state, and make the actual inval
2974	// (if line is valid) in DCACHE_XTN_DC_FLUSH_GO state.
2975	// A cleanup request is generated for each valid line.
2976	// returns to IDLE and flush TLBs when last slot
2977	{
2978	int state;
2979	paddr_t tag;
2980	size_t way = r_dcache_flush_count.read() / m_dcache_sets;
2981	size_t set = r_dcache_flush_count.read() % m_dcache_sets;
2982
2983	r_dcache.read_dir(way,
2984	set,
2985	&tag,
2986	&state);
2987
2988	if (state == CACHE_SLOT_STATE_VALID) {
2989	// goes to DCACHE_XTN_DC_FLUSH_GO to inval directory
2990	r_dcache_miss_way = way;
2991	r_dcache_miss_set = set;
2992	r_dcache_fsm = DCACHE_XTN_DC_FLUSH_GO;
2993	}
2994	else if (r_dcache_flush_count.read() == (m_dcache_sets * m_dcache_ways - 1)) {
2995	// last slot
2996	r_dtlb.reset();
2997	r_itlb.reset();
2998	r_dcache_fsm = DCACHE_IDLE;
2999	m_drsp.valid = true;
3000	}
3001
3002	// saturation counter
3003	if (r_dcache_flush_count.read() < (m_dcache_sets * m_dcache_ways - 1)) {
3004	r_dcache_flush_count = r_dcache_flush_count.read() + 1;
3005	}
3006	break;
3007	}
3008	////////////////////////////
3009	case DCACHE_XTN_DC_FLUSH_GO: // Switch the cache slot to ZOMBI state
3010	// and reset directory extension.
3011	// returns to IDLE and flush TLBs when last slot
3012	{
3013	size_t way = r_dcache_miss_way.read();
3014	size_t set = r_dcache_miss_set.read();
3015
3016	r_dcache_in_tlb[m_dcache_sets * way + set] = false;
3017	r_dcache_contains_ptd[m_dcache_sets * way + set] = false;
3018
3019	r_dcache.write_dir(way,
3020	set,
3021	CACHE_SLOT_STATE_INVALID);
3022
3023	if (r_dcache_flush_count.read() == (m_dcache_sets * m_dcache_ways - 1)) {
3024	// last slot
3025	r_dtlb.reset();
3026	r_itlb.reset();
3027	r_dcache_fsm = DCACHE_IDLE;
3028	m_drsp.valid = true;
3029	}
3030	else {
3031	r_dcache_fsm = DCACHE_XTN_DC_FLUSH;
3032	}
3033	break;
3034	}
3035	/////////////////////////
3036	case DCACHE_XTN_DT_INVAL: // handling processor XTN_DTLB_INVAL request
3037	{
3038	r_dtlb.inval(r_dcache_save_wdata.read());
3039	r_dcache_fsm = DCACHE_IDLE;
3040	m_drsp.valid = true;
3041	break;
3042	}
3043	////////////////////////////
3044	case DCACHE_XTN_DC_INVAL_VA: // selective cache line invalidate with virtual address
3045	// requires 3 cycles: access tlb, read cache, inval cache
3046	// we compute the physical address in this state
3047	{
3048	paddr_t paddr;
3049	bool hit;
3050
3051	if (r_mmu_mode.read() & DATA_TLB_MASK) {
3052	// dtlb activated
3053	hit = r_dtlb.translate(r_dcache_save_wdata.read(), &paddr);
3054	}
3055	else {
3056	// dtlb not activated
3057	paddr = (paddr_t) r_dcache_save_wdata.read();
3058	if (vci_param::N > 32) {
3059	paddr = paddr \| ((paddr_t) (r_dcache_paddr_ext.read()) << 32);
3060	}
3061	hit = true;
3062	}
3063
3064	if (hit) {
3065	// tlb hit
3066
3067	// QM debug
3068	if (m_debug_dcache_fsm) {
3069	std::cout << "(5) In DCACHE_XTN_DC_INVAL_VA, r_dcache_save_paddr <- " << std::hex << paddr << std::endl;
3070	}
3071	r_dcache_save_paddr = paddr;
3072	r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA;
3073	}
3074	else {
3075	// tlb miss
3076	r_dcache_tlb_ins = false; // dtlb
3077	r_dcache_tlb_vaddr = r_dcache_save_wdata.read();
3078	r_dcache_fsm = DCACHE_TLB_MISS;
3079	}
3080
3081	#if DEBUG_DCACHE
3082	if (m_debug_dcache_fsm) {
3083	std::cout << " <PROC " << name()
3084	<< " DCACHE_XTN_DC_INVAL_VA> Compute physical address" << std::hex
3085	<< " / VADDR = " << r_dcache_save_wdata.read()
3086	<< " / PADDR = " << paddr << std::endl;
3087	}
3088	#endif
3089
3090	break;
3091	}
3092	////////////////////////////
3093	case DCACHE_XTN_DC_INVAL_PA: // selective cache line invalidate with physical address
3094	// requires 2 cycles: read cache / inval cache
3095	// In this state we read dcache.
3096	{
3097	size_t way;
3098	size_t set;
3099	size_t word;
3100	int state;
3101
3102	r_dcache.read_dir(r_dcache_save_paddr.read(),
3103	&state,
3104	&way,
3105	&set,
3106	&word);
3107
3108	if (state == CACHE_SLOT_STATE_VALID) {
3109	// inval to be done
3110	r_dcache_xtn_way = way;
3111	r_dcache_xtn_set = set;
3112	r_dcache_fsm = DCACHE_XTN_DC_INVAL_GO;
3113	}
3114	else {
3115	// miss : nothing to do
3116	r_dcache_fsm = DCACHE_IDLE;
3117	m_drsp.valid = true;
3118	}
3119
3120	#if DEBUG_DCACHE
3121	if (m_debug_dcache_fsm) {
3122	std::cout << " <PROC " << name()
3123	<< " DCACHE_XTN_DC_INVAL_PA> Test hit in dcache" << std::hex
3124	<< " / PADDR = " << r_dcache_save_paddr.read() << std::dec
3125	<< " / HIT = " << (state == CACHE_SLOT_STATE_VALID)
3126	<< " / SET = " << set
3127	<< " / WAY = " << way << std::endl;
3128	}
3129	#endif
3130	break;
3131	}
3132	////////////////////////////
3133	case DCACHE_XTN_DC_INVAL_GO: // In this state, we invalidate the cache line
3134	// Blocked if previous cleanup not completed
3135	// Test if itlb or dtlb inval is required
3136	{
3137	size_t way = r_dcache_xtn_way.read();
3138	size_t set = r_dcache_xtn_set.read();
3139	paddr_t nline = r_dcache_save_paddr.read() / (m_dcache_words << 2);
3140
3141	r_dcache.write_dir(way,
3142	set,
3143	CACHE_SLOT_STATE_INVALID);
3144
3145	// possible itlb & dtlb invalidate
3146	if (r_dcache_in_tlb[way * m_dcache_sets + set]) {
3147	r_dcache_tlb_inval_line = nline;
3148	r_dcache_tlb_inval_set = 0;
3149	r_dcache_fsm_scan_save = DCACHE_XTN_DC_INVAL_END;
3150	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
3151	r_dcache_in_tlb[way * m_dcache_sets + set] = false;
3152	}
3153	else if (r_dcache_contains_ptd[way * m_dcache_sets + set]) {
3154	r_itlb.reset();
3155	r_dtlb.reset();
3156	r_dcache_contains_ptd[way * m_dcache_sets + set] = false;
3157	r_dcache_fsm = DCACHE_IDLE;
3158	m_drsp.valid = true;
3159	}
3160	else {
3161	r_dcache_fsm = DCACHE_IDLE;
3162	m_drsp.valid = true;
3163	}
3164
3165	#if DEBUG_DCACHE
3166	if (m_debug_dcache_fsm) {
3167	std::cout << " <PROC " << name()
3168	<< " DCACHE_XTN_DC_INVAL_GO> Actual dcache inval" << std::hex
3169	<< " / PADDR = " << r_dcache_save_paddr.read() << std::endl;
3170	}
3171	#endif
3172	break;
3173	}
3174	//////////////////////////////
3175	case DCACHE_XTN_DC_INVAL_END: // send response to processor XTN request
3176	{
3177	r_dcache_fsm = DCACHE_IDLE;
3178	m_drsp.valid = true;
3179	break;
3180	}
3181	////////////////////////
3182	case DCACHE_MISS_SELECT: // Try to select a slot in associative set,
3183	// Waiting in this state if no slot available.
3184	// If a victim slot has been choosen and the r_icache_cc_send_req is false,
3185	// we send the cleanup request in this state.
3186	// If not, a r_icache_cleanup_victim_req flip-flop is
3187	// utilized for saving this cleanup request, and it will be sent later
3188	// in state ICACHE_MISS_WAIT or ICACHE_MISS_UPDT_DIR.
3189	// The r_icache_miss_clack flip-flop is set
3190	// when a cleanup is required
3191	{
3192	bool found = false;
3193	bool cleanup = false;
3194	size_t way = 0;
3195	size_t set = 0;
3196	paddr_t victim = 0;
3197
3198	r_dcache.read_select(r_dcache_save_paddr.read(),
3199	&victim,
3200	&way,
3201	&set,
3202	&found,
3203	&cleanup);
3204
3205	if (not found) {
3206	break;
3207	}
3208	else {
3209	r_dcache_miss_way = way;
3210	r_dcache_miss_set = set;
3211	r_dcache_miss_victim = victim;
3212
3213	r_dcache_fsm = DCACHE_MISS_VICTIM_CHECK;
3214
3215	#if DEBUG_DCACHE
3216	if (m_debug_dcache_fsm) {
3217	std::cout << " <PROC " << name()
3218	<< " DCACHE_MISS_SELECT> Select a slot:" << std::dec
3219	<< " / WAY = " << way
3220	<< " / SET = " << set
3221	<< " / PADDR = " << std::hex << r_dcache_save_paddr.read();
3222	if (cleanup) std::cout << " / VICTIM = " << (victim * m_dcache_words * 4) << std::endl;
3223	else std::cout << std::endl;
3224	}
3225	#endif
3226	} // end found
3227	break;
3228	}
3229	///////////////////////
3230	case DCACHE_MISS_VICTIM_CHECK: // possibly request itlb or dtlb invalidate
3231	{
3232	// Invalidation of the line to avoid the "famous" bug
3233	// of a direct update matching the previous line while
3234	// the missed line is being written
3235	size_t way = r_dcache_miss_way.read();
3236	size_t set = r_dcache_miss_set.read();
3237
3238	r_dcache.write_dir(r_dcache_save_paddr.read(),
3239	way,
3240	set,
3241	CACHE_SLOT_STATE_INVALID);
3242
3243	// if an itlb or dtlb invalidation is required
3244	// the miss response is not handled before the invalidatation is complete
3245	if (r_dcache_in_tlb[way * m_dcache_sets + set]) {
3246	r_dcache_in_tlb[way * m_dcache_sets + set] = false;
3247
3248	r_dcache_tlb_inval_line = r_dcache_miss_victim.read();
3249	r_dcache_tlb_inval_set = 0;
3250	r_dcache_fsm_scan_save = DCACHE_MISS_WAIT;
3251	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
3252	#if DEBUG_DCACHE
3253	if (m_debug_dcache_fsm) {
3254	std::cout << " <PROC " << name()
3255	<< " DCACHE_MISS_VICTIM_CHECK> Line in TLB" << std::dec
3256	<< " / way = " << way
3257	<< " / set = " << set
3258	<< std::hex <<
3259	" / victim = " << r_dcache_miss_victim.read()
3260	<< std::dec << std::endl;
3261	}
3262	#endif
3263	}
3264	else if (r_dcache_contains_ptd[way * m_dcache_sets + set]) {
3265	r_itlb.reset();
3266	r_dtlb.reset();
3267	r_dcache_contains_ptd[way * m_dcache_sets + set] = false;
3268	r_dcache_fsm = DCACHE_MISS_WAIT;
3269	#if DEBUG_DCACHE
3270	if (m_debug_dcache_fsm) {
3271	std::cout << " <PROC " << name()
3272	<< " DCACHE_MISS_VICTIM_CHECK> Reset ITLB and DTLB"
3273	<< std::dec << std::endl;
3274	}
3275	#endif
3276	}
3277	else {
3278	r_dcache_fsm = DCACHE_MISS_WAIT;
3279	}
3280	break;
3281	}
3282	//////////////////////
3283	case DCACHE_MISS_WAIT: // waiting the response to a miss request from VCI_RSP FSM
3284	// This state is in charge of error signaling
3285	// There is 5 types of error depending on the requester
3286	{
3287	if (r_vci_rsp_data_error.read()) {
3288	// bus error
3289	switch (r_dcache_miss_type.read()) {
3290	case PROC_MISS:
3291	{
3292	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
3293	r_mmu_dbvar = r_dcache_save_vaddr.read();
3294	m_drsp.valid = true;
3295	m_drsp.error = true;
3296	r_dcache_fsm = DCACHE_IDLE;
3297	break;
3298	}
3299	case PTE1_MISS:
3300	{
3301	if (r_dcache_tlb_ins.read()) {
3302	r_mmu_ietr = MMU_READ_PT1_ILLEGAL_ACCESS;
3303	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3304	r_icache_tlb_miss_req = false;
3305	r_icache_tlb_rsp_error = true;
3306	}
3307	else {
3308	r_mmu_detr = MMU_READ_PT1_ILLEGAL_ACCESS;
3309	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3310	m_drsp.valid = true;
3311	m_drsp.error = true;
3312	}
3313	r_dcache_fsm = DCACHE_IDLE;
3314	break;
3315	}
3316	case PTE2_MISS:
3317	{
3318	if (r_dcache_tlb_ins.read()) {
3319	r_mmu_ietr = MMU_READ_PT2_ILLEGAL_ACCESS;
3320	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3321	r_icache_tlb_miss_req = false;
3322	r_icache_tlb_rsp_error = true;
3323	}
3324	else {
3325	r_mmu_detr = MMU_READ_PT2_ILLEGAL_ACCESS;
3326	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3327	m_drsp.valid = true;
3328	m_drsp.error = true;
3329	}
3330	r_dcache_fsm = DCACHE_IDLE;
3331	break;
3332	}
3333	} // end switch type
3334	r_vci_rsp_data_error = false;
3335	}
3336	else if (r_vci_rsp_fifo_dcache.rok()) {
3337	// valid response available
3338	r_dcache_miss_word = 0;
3339	r_dcache_fsm = DCACHE_MISS_DATA_UPDT;
3340	}
3341	break;
3342	}
3343	//////////////////////////
3344	case DCACHE_MISS_DATA_UPDT: // update the dcache (one word per cycle)
3345	{
3346	if (r_vci_rsp_fifo_dcache.rok()) {
3347	// one word available
3348	r_dcache.write(r_dcache_miss_way.read(),
3349	r_dcache_miss_set.read(),
3350	r_dcache_miss_word.read(),
3351	r_vci_rsp_fifo_dcache.read());
3352	#if DEBUG_DCACHE
3353	if (m_debug_dcache_fsm) {
3354	std::cout << " <PROC " << name()
3355	<< " DCACHE_MISS_DATA_UPDT> Write one word:"
3356	<< " / DATA = " << std::hex << r_vci_rsp_fifo_dcache.read()
3357	<< " / WAY = " << std::dec << r_dcache_miss_way.read()
3358	<< " / SET = " << r_dcache_miss_set.read()
3359	<< " / WORD = " << r_dcache_miss_word.read() << std::endl;
3360	}
3361	#endif
3362	vci_rsp_fifo_dcache_get = true;
3363	r_dcache_miss_word = r_dcache_miss_word.read() + 1;
3364
3365	if (r_dcache_miss_word.read() == (m_dcache_words - 1)) {
3366	// last word
3367	r_dcache_fsm = DCACHE_MISS_DIR_UPDT;
3368	}
3369	}
3370	break;
3371	}
3372	//////////////////////////
3373	case DCACHE_MISS_DIR_UPDT: // Stalled if a victim line has been evicted
3374	// and the cleanup ack has not been received,
3375	// as indicated by the r_dcache_miss clack.
3376	// - If no matching coherence request (r_dcache_inval_miss)
3377	// switch directory slot to VALID state.
3378	// - If matching coherence request, switch directory slot
3379	// to ZOMBI state, and send a cleanup request.
3380	{
3381	// switch slot to VALID state
3382	r_dcache.write_dir(r_dcache_save_paddr.read(),
3383	r_dcache_miss_way.read(),
3384	r_dcache_miss_set.read(),
3385	CACHE_SLOT_STATE_VALID);
3386
3387	#if DEBUG_DCACHE
3388	if (m_debug_dcache_fsm) {
3389	std::cout << " <PROC " << name()
3390	<< " DCACHE_MISS_DIR_UPDT> Switch slot to VALID state"
3391	<< " PADDR = " << std::hex << r_dcache_save_paddr.read()
3392	<< " / WAY = " << std::dec << r_dcache_miss_way.read()
3393	<< " / SET = " << r_dcache_miss_set.read() << std::endl;
3394	}
3395	#endif
3396
3397	// Immediate coherence test:
3398	// If we have received one or several updates on the line during the miss, we have stored them
3399	// and we update the values now
3400	for (std::list<VcacheUpdate>::iterator it = m_dpending_updates.begin(); it != m_dpending_updates.end(); it++)
3401	{
3402	bool cache_hit;
3403	size_t cache_way = 0;
3404	size_t cache_set = 0;
3405	size_t cache_word = 0;
3406	uint32_t cache_rdata = 0;
3407
3408	// Test if hit in dcache
3409	cache_hit = r_dcache.read_neutral(it->m_addr,
3410	&cache_rdata,
3411	&cache_way,
3412	&cache_set,
3413	&cache_word);
3414
3415	assert(cache_hit);
3416	paddr_t mask = ~((m_dcache_words << 2) - 1);
3417	if ((it->m_addr & mask) != (mask & r_dcache_save_paddr.read())) {
3418	std::cerr << " <PROC " << name() << " (" << std::hex << m_srcid << ")"
3419	<< " cycle " << std::dec << m_cpt_total_cycles << " ERROR: it->m_addr = " << std::hex << it->m_addr
3420	<< " != r_dcache_save_paddr = " << r_dcache_save_paddr.read() << ">"
3421	<< std::endl;
3422	}
3423	if (cache_way != r_dcache_miss_way.read()) {
3424	std::cerr << " <PROC " << name() << " (" << std::hex << m_srcid << ")"
3425	<< " cycle " << std::dec << m_cpt_total_cycles << " ERROR: cache_way = " << std::dec << cache_way
3426	<< " != r_dcache_miss_way = " << r_dcache_miss_way.read() << ">"
3427	<< std::endl;
3428	}
3429	if (cache_set != r_dcache_miss_set.read()) {
3430	std::cerr << " <PROC " << name() << " (" << std::hex << m_srcid << ")"
3431	<< " cycle " << std::dec << m_cpt_total_cycles << " ERROR: cache_set = " << std::dec << cache_set
3432	<< " != r_dcache_miss_set = " << r_dcache_miss_set.read() << ">"
3433	<< std::endl;
3434	}
3435	//assert(it->m_addr == r_dcache_save_paddr.read());
3436	assert(cache_way == r_dcache_miss_way.read());
3437	assert(cache_set == r_dcache_miss_set.read());
3438
3439	r_dcache.write(cache_way, cache_set, cache_word, it->m_value, it->m_be);
3440	#if DEBUG_DCACHE
3441	if (m_debug_dcache_fsm) {
3442	std::cout << " <Cache " << name()
3443	<< " CACHE_MISS_DIR_UPDT> Updating pending update:"
3444	<< " ADDR = " << std::hex << it->m_addr
3445	<< " / WAY = " << std::dec << cache_way
3446	<< " / SET = " << cache_set
3447	<< " / VALUE = " << std::hex << it->m_value
3448	<< " / BE = " << it->m_be << std::endl;
3449	}
3450	#endif
3451	}
3452	m_dpending_updates.clear();
3453
3454	// reset directory extension
3455	size_t way = r_dcache_miss_way.read();
3456	size_t set = r_dcache_miss_set.read();
3457	r_dcache_in_tlb[way * m_dcache_sets + set] = false;
3458	r_dcache_contains_ptd[way * m_dcache_sets + set] = false;
3459	if (r_dcache_miss_type.read() == PTE1_MISS) r_dcache_fsm = DCACHE_TLB_PTE1_GET;
3460	else if (r_dcache_miss_type.read() == PTE2_MISS) r_dcache_fsm = DCACHE_TLB_PTE2_GET;
3461	else r_dcache_fsm = DCACHE_IDLE;
3462
3463	break;
3464	}
3465	/////////////////////
3466	case DCACHE_UNC_WAIT: // waiting a response to an uncacheable read
3467	{
3468	if (r_vci_rsp_data_error.read()) {
3469	// bus error
3470	if (r_dcache_vci_unc_write.read()) {
3471	r_mmu_detr = MMU_WRITE_DATA_ILLEGAL_ACCESS;
3472	}
3473	else {
3474	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
3475	}
3476
3477	r_mmu_dbvar = m_dreq.addr;
3478	r_vci_rsp_data_error = false;
3479	m_drsp.error = true;
3480	m_drsp.valid = true;
3481	r_dcache_fsm = DCACHE_IDLE;
3482	break;
3483	}
3484	else if (r_vci_rsp_fifo_dcache.rok()) {
3485	// data available
3486	// consume data
3487	vci_rsp_fifo_dcache_get = true;
3488	r_dcache_fsm = DCACHE_IDLE;
3489
3490	// acknowledge the processor request if it has not been modified
3491	if (m_dreq.valid and (m_dreq.addr == r_dcache_save_vaddr.read())) {
3492	m_drsp.valid = true;
3493	m_drsp.error = false;
3494	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
3495	}
3496	}
3497	break;
3498	}
3499	/////////////////////
3500	case DCACHE_LL_WAIT: // waiting VCI response to a LL transaction
3501	{
3502	if (r_vci_rsp_data_error.read()) {
3503	// bus error
3504	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
3505	r_mmu_dbvar = m_dreq.addr;
3506	r_vci_rsp_data_error = false;
3507	m_drsp.error = true;
3508	m_drsp.valid = true;
3509	r_dcache_fsm = DCACHE_IDLE;
3510	break;
3511	}
3512	else if (r_vci_rsp_fifo_dcache.rok()) {
3513	// data available
3514	// consume data
3515	vci_rsp_fifo_dcache_get = true;
3516
3517	if (r_dcache_ll_rsp_count.read() == 0) {
3518	// first flit
3519	// set key value in llsc reservation buffer
3520	r_dcache_llsc_key = r_vci_rsp_fifo_dcache.read();
3521	r_dcache_ll_rsp_count = r_dcache_ll_rsp_count.read() + 1;
3522	}
3523	else {
3524	// last flit
3525	// acknowledge the processor request if it has not been modified
3526	if (m_dreq.valid and (m_dreq.addr == r_dcache_save_vaddr.read())) {
3527	m_drsp.valid = true;
3528	m_drsp.error = false;
3529	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
3530	}
3531	r_dcache_fsm = DCACHE_IDLE;
3532	}
3533	}
3534	break;
3535	}
3536	////////////////////
3537	case DCACHE_SC_WAIT: // waiting VCI response to a SC transaction
3538	{
3539	if (r_vci_rsp_data_error.read()) {
3540	// bus error
3541	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
3542	r_mmu_dbvar = m_dreq.addr;
3543	r_vci_rsp_data_error = false;
3544	m_drsp.error = true;
3545	m_drsp.valid = true;
3546	r_dcache_fsm = DCACHE_IDLE;
3547	break;
3548	}
3549	else if (r_vci_rsp_fifo_dcache.rok()) {
3550	// response available
3551	// consume response
3552	vci_rsp_fifo_dcache_get = true;
3553	m_drsp.valid = true;
3554	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
3555	r_dcache_fsm = DCACHE_IDLE;
3556	}
3557	break;
3558	}
3559	//////////////////////////
3560	case DCACHE_DIRTY_GET_PTE: // This sub_fsm sets the PTE Dirty bit in memory
3561	// before handling a processor WRITE or SC request
3562	// Input argument is r_dcache_dirty_paddr
3563	// In this first state, we get PTE value in dcache
3564	// and post a CAS request to CMD FSM
3565	{
3566	// get PTE in dcache
3567	uint32_t pte;
3568	size_t way;
3569	size_t set;
3570	size_t word; // unused
3571	int state;
3572
3573	r_dcache.read(r_dcache_dirty_paddr.read(),
3574	&pte,
3575	&way,
3576	&set,
3577	&word,
3578	&state);
3579
3580	assert((state == CACHE_SLOT_STATE_VALID) and
3581	"error in DCACHE_DIRTY_TLB_SET: the PTE should be in dcache");
3582
3583	// request CAS transaction to CMD_FSM
3584	r_dcache_dirty_way = way;
3585	r_dcache_dirty_set = set;
3586
3587	// check llsc reservation buffer
3588	if (r_dcache_llsc_paddr.read() == r_dcache_dirty_paddr.read()) {
3589	r_dcache_llsc_valid = false;
3590	}
3591
3592	// request a CAS CMD and go to DCACHE_DIRTY_WAIT state
3593	r_dcache_vci_cas_req = true;
3594	r_dcache_vci_paddr = r_dcache_dirty_paddr.read();
3595	r_dcache_vci_cas_old = pte;
3596	r_dcache_vci_cas_new = pte \| PTE_D_MASK;
3597	r_dcache_fsm = DCACHE_DIRTY_WAIT;
3598
3599	#if DEBUG_DCACHE
3600	if (m_debug_dcache_fsm) {
3601	std::cout << " <PROC " << name()
3602	<< " DCACHE_DIRTY_GET_PTE> CAS request" << std::hex
3603	<< " / PTE_PADDR = " << r_dcache_dirty_paddr.read()
3604	<< " / PTE_VALUE = " << pte << std::dec
3605	<< " / SET = " << set
3606	<< " / WAY = " << way << std::endl;
3607	}
3608	#endif
3609	break;
3610	}
3611	///////////////////////
3612	case DCACHE_DIRTY_WAIT: // wait completion of CAS for PTE Dirty bit,
3613	// and return to IDLE state when response is received.
3614	// we don't care if the CAS is a failure:
3615	// - if the CAS is a success, the coherence mechanism
3616	// updates the local copy.
3617	// - if the CAS is a failure, we just retry the write.
3618	{
3619	if (r_vci_rsp_data_error.read()) {
3620	std::cout << "BUS ERROR in DCACHE_DIRTY_WAIT state" << std::endl;
3621	std::cout << "This should not happen in this state" << std::endl;
3622	exit(0);
3623	}
3624	else if (r_vci_rsp_fifo_dcache.rok()) {
3625	// response available
3626	vci_rsp_fifo_dcache_get = true;
3627	r_dcache_fsm = DCACHE_IDLE;
3628
3629	#if DEBUG_DCACHE
3630	if (m_debug_dcache_fsm) {
3631	std::cout << " <PROC " << name()
3632	<< " DCACHE_DIRTY_WAIT> CAS completed" << std::endl;
3633	}
3634	#endif
3635	}
3636	break;
3637	}
3638
3639
3640	///////////////////////////
3641	case DCACHE_INVAL_TLB_SCAN: // Scan sequentially all sets for both ITLB & DTLB
3642	// It makes assumption: m_itlb_sets == m_dtlb_sets
3643	// All ways are handled in parallel.
3644	// We enter this state when a DCACHE line is modified,
3645	// and there is a copy in itlb or dtlb.
3646	// It can be caused by:
3647	// - a coherence inval or updt transaction,
3648	// - a line inval caused by a cache miss
3649	// - a processor XTN inval request,
3650	// - a WRITE hit,
3651	// - a Dirty bit update
3652	// Input arguments are:
3653	// - r_dcache_tlb_inval_line
3654	// - r_dcache_tlb_inval_set
3655	// - r_dcache_fsm_scan_save
3656	{
3657	paddr_t line = r_dcache_tlb_inval_line.read();
3658	size_t set = r_dcache_tlb_inval_set.read();
3659	size_t way;
3660	bool ok;
3661
3662	for (way = 0; way < m_itlb_ways; way++) {
3663	ok = r_itlb.inval(line, way, set);
3664	#if DEBUG_DCACHE
3665	if (m_debug_dcache_fsm and ok) {
3666	std::cout << " <PROC " << name()
3667	<< ".DCACHE_INVAL_TLB_SCAN> Invalidate ITLB entry:" << std::hex
3668	<< " line = " << line << std::dec
3669	<< " / set = " << set
3670	<< " / way = " << way << std::endl;
3671	}
3672	#endif
3673	}
3674
3675	for (way = 0; way < m_dtlb_ways; way++) {
3676	ok = r_dtlb.inval(line, way, set);
3677	#if DEBUG_DCACHE
3678	if (m_debug_dcache_fsm and ok)
3679	std::cout << " <PROC " << name() << " DCACHE_INVAL_TLB_SCAN>"
3680	<< " Invalidate DTLB entry" << std::hex
3681	<< " / line = " << line << std::dec
3682	<< " / set = " << set
3683	<< " / way = " << way << std::endl;
3684	#endif
3685	}
3686
3687	// return to the calling state when TLB inval completed
3688	if (r_dcache_tlb_inval_set.read() == (m_dtlb_sets - 1)) {
3689	r_dcache_fsm = r_dcache_fsm_scan_save.read();
3690	}
3691	r_dcache_tlb_inval_set = r_dcache_tlb_inval_set.read() + 1;
3692	break;
3693	}
3694	} // end switch r_dcache_fsm
3695
3696	///////////////// wbuf update ///////////////////////////////////////////////////////
3697	r_wbuf.update();
3698
3699	///////////////// llsc update ///////////////////////////////////////////////////////
3700	if (r_dcache_llsc_valid.read()) r_dcache_llsc_count = r_dcache_llsc_count.read() - 1;
3701	if (r_dcache_llsc_count.read() == 1) r_dcache_llsc_valid = false;
3702
3703	//////////////// test processor frozen //////////////////////////////////////////////
3704	// The simulation exit if the number of consecutive frozen cycles
3705	// is larger than the m_max_frozen_cycles (constructor parameter)
3706	if ((m_ireq.valid and not m_irsp.valid) or (m_dreq.valid and not m_drsp.valid)) {
3707	m_cpt_frz_cycles++; // used for instrumentation
3708	m_cpt_stop_simulation++; // used for debug
3709	if (m_cpt_stop_simulation > m_max_frozen_cycles) {
3710	std::cout << std::dec << "ERROR in CC_VCACHE_WRAPPER " << name() << std::endl
3711	<< " stop at cycle " << m_cpt_total_cycles << std::endl
3712	<< " frozen since cycle " << m_cpt_total_cycles - m_max_frozen_cycles
3713	<< std::endl;
3714	r_iss.dump();
3715	exit(1);
3716	}
3717	}
3718	else {
3719	m_cpt_stop_simulation = 0;
3720	}
3721
3722	/////////// execute one iss cycle /////////////////////////////////
3723	{
3724	uint32_t it = 0;
3725	for (size_t i = 0; i < (size_t) iss_t::n_irq; i++) {
3726	if (p_irq[i].read()) {
3727	it \|= (1 << i);
3728	}
3729	}
3730	r_iss.executeNCycles(1, m_irsp, m_drsp, it);
3731	}
3732
3733	////////////////////////////////////////////////////////////////////////////
3734	// The VCI_CMD FSM controls the following ressources:
3735	// - r_vci_cmd_fsm
3736	// - r_vci_cmd_min
3737	// - r_vci_cmd_max
3738	// - r_vci_cmd_cpt
3739	// - r_vci_cmd_imiss_prio
3740	// - wbuf (reset)
3741	// - r_icache_miss_req (reset)
3742	// - r_icache_unc_req (reset)
3743	// - r_dcache_vci_miss_req (reset)
3744	// - r_dcache_vci_unc_req (reset)
3745	// - r_dcache_vci_ll_req (reset)
3746	// - r_dcache_vci_sc_req (reset in case of local sc fail)
3747	// - r_dcache_vci_cas_req (reset)
3748	//
3749	// This FSM handles requests from both the DCACHE FSM & the ICACHE FSM.
3750	// There are 8 request types, with the following priorities :
3751	// 1 - Data Read Miss : r_dcache_vci_miss_req and miss in the write buffer
3752	// 2 - Data Read Uncachable : r_dcache_vci_unc_req
3753	// 3 - Instruction Miss : r_icache_miss_req and miss in the write buffer
3754	// 4 - Instruction Uncachable : r_icache_unc_req
3755	// 5 - Data Write : r_wbuf.rok()
3756	// 6 - Data Linked Load : r_dcache_vci_ll_req
3757	// 7 - Data Store Conditionnal: r_dcache_vci_sc_req
3758	// 8 - Compare And Swap : r_dcache_vci_cas_req
3759	//
3760	// As we want to support several simultaneous VCI transactions, the VCI_CMD_FSM
3761	// and the VCI_RSP_FSM are fully desynchronized.
3762	//
3763	// VCI formats:
3764	// According to the VCI advanced specification, all read requests packets
3765	// (data Uncached, Miss data, instruction Uncached, Miss instruction)
3766	// are one word packets.
3767	// For write burst packets, all words are in the same cache line,
3768	// and addresses must be contiguous (the BE field is 0 in case of "holes").
3769	// The sc command packet implements actually a compare-and-swap mechanism
3770	// and the packet contains two flits.
3771	////////////////////////////////////////////////////////////////////////////////////
3772
3773
3774	switch (r_vci_cmd_fsm.read()) {
3775	//////////////
3776	case CMD_IDLE:
3777	{
3778	// DCACHE read requests (r_dcache_vci_miss_req or r_dcache_vci_ll_req), and
3779	// ICACHE read requests (r_icache_miss_req) require both a write_buffer access
3780	// to check a possible pending write on the same cache line.
3781	// As there is only one possible access per cycle to write buffer, we implement
3782	// a round-robin priority between DCACHE and ICACHE for this access,
3783	// using the r_vci_cmd_imiss_prio flip-flop.
3784
3785	size_t wbuf_min;
3786	size_t wbuf_max;
3787
3788	bool dcache_miss_req = r_dcache_vci_miss_req.read() and
3789	(not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read());
3790
3791	bool dcache_ll_req = r_dcache_vci_ll_req.read() and
3792	(not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read());
3793
3794	bool dcache_sc_req = r_dcache_vci_sc_req.read() and
3795	(not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read());
3796
3797	bool dcache_cas_req = r_dcache_vci_cas_req.read() and
3798	(not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read());
3799
3800	bool icache_miss_req = r_icache_miss_req.read() and
3801	(not (r_dcache_vci_miss_req.read() or
3802	r_dcache_vci_ll_req.read() or
3803	r_dcache_vci_cas_req.read() or
3804	r_dcache_vci_sc_req.read()) or
3805	r_vci_cmd_imiss_prio.read());
3806
3807	// 1 - Data unc write
3808	if (r_dcache_vci_unc_req.read() and r_dcache_vci_unc_write.read()) {
3809	r_vci_cmd_fsm = CMD_DATA_UNC_WRITE;
3810	r_dcache_vci_unc_req = false;
3811	}
3812	// 2 data read miss
3813	else if (dcache_miss_req and r_wbuf.miss(r_dcache_vci_paddr.read())) {
3814	r_vci_cmd_fsm = CMD_DATA_MISS;
3815	r_dcache_vci_miss_req = false;
3816	r_vci_cmd_imiss_prio = true;
3817	}
3818	// 3 - Data Read Uncachable
3819	else if (r_dcache_vci_unc_req.read() and not r_dcache_vci_unc_write.read()) {
3820	r_vci_cmd_fsm = CMD_DATA_UNC_READ;
3821	r_dcache_vci_unc_req = false;
3822	}
3823	// 4 - Data Linked Load
3824	else if (dcache_ll_req and r_wbuf.miss(r_dcache_vci_paddr.read())) {
3825	r_vci_cmd_fsm = CMD_DATA_LL;
3826	r_dcache_vci_ll_req = false;
3827	r_vci_cmd_imiss_prio = true;
3828	}
3829	// 5 - Instruction Miss
3830	else if (icache_miss_req and r_wbuf.miss(r_icache_vci_paddr.read())) {
3831	r_vci_cmd_fsm = CMD_INS_MISS;
3832	r_icache_miss_req = false;
3833	r_vci_cmd_imiss_prio = false;
3834	}
3835	// 6 - Instruction Uncachable
3836	else if (r_icache_unc_req.read()) {
3837	r_vci_cmd_fsm = CMD_INS_UNC;
3838	r_icache_unc_req = false;
3839	}
3840	// 7 - Data Write
3841	else if (r_wbuf.rok(&wbuf_min, &wbuf_max)) {
3842	r_vci_cmd_fsm = CMD_DATA_WRITE;
3843	r_vci_cmd_cpt = wbuf_min;
3844	r_vci_cmd_min = wbuf_min;
3845	r_vci_cmd_max = wbuf_max;
3846	}
3847	// 8 - Data Store Conditionnal
3848	else if (dcache_sc_req and r_wbuf.miss(r_dcache_vci_paddr.read())) {
3849	r_vci_cmd_fsm = CMD_DATA_SC;
3850	r_dcache_vci_sc_req = false;
3851	r_vci_cmd_imiss_prio = true;
3852	r_vci_cmd_cpt = 0;
3853	}
3854	// 9 - Compare And Swap
3855	else if (dcache_cas_req and r_wbuf.miss(r_dcache_vci_paddr.read())) {
3856	r_vci_cmd_fsm = CMD_DATA_CAS;
3857	r_dcache_vci_cas_req = false;
3858	r_vci_cmd_imiss_prio = true;
3859	r_vci_cmd_cpt = 0;
3860	}
3861
3862	#if DEBUG_CMD
3863	if (m_debug_cmd_fsm) {
3864	std::cout << " <PROC " << name() << " CMD_IDLE>"
3865	<< " / dmiss_req = " << dcache_miss_req
3866	<< " / imiss_req = " << icache_miss_req
3867	<< std::endl;
3868	}
3869	#endif
3870	break;
3871	}
3872	////////////////////
3873	case CMD_DATA_WRITE:
3874	{
3875	if (p_vci.cmdack.read()) {
3876	r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
3877	if (r_vci_cmd_cpt == r_vci_cmd_max) {
3878	// last flit sent
3879	r_vci_cmd_fsm = CMD_IDLE;
3880	r_wbuf.sent();
3881	}
3882	}
3883	break;
3884	}
3885	/////////////////
3886	case CMD_DATA_SC:
3887	case CMD_DATA_CAS:
3888	{
3889	// The CAS and SC VCI commands contain two flits
3890	if (p_vci.cmdack.read()) {
3891	r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
3892	if (r_vci_cmd_cpt == 1) r_vci_cmd_fsm = CMD_IDLE ;
3893	}
3894	break;
3895	}
3896	//////////////////
3897	case CMD_INS_MISS:
3898	case CMD_INS_UNC:
3899	case CMD_DATA_MISS:
3900	case CMD_DATA_UNC_READ:
3901	case CMD_DATA_UNC_WRITE:
3902	case CMD_DATA_LL:
3903	{
3904	// all read VCI commands contain one single flit
3905	if (p_vci.cmdack.read()) {
3906	r_vci_cmd_fsm = CMD_IDLE;
3907	}
3908	break;
3909	}
3910
3911	} // end switch r_vci_cmd_fsm
3912
3913	//////////////////////////////////////////////////////////////////////////
3914	// The VCI_RSP FSM controls the following ressources:
3915	// - r_vci_rsp_fsm:
3916	// - r_vci_rsp_fifo_icache (push)
3917	// - r_vci_rsp_fifo_dcache (push)
3918	// - r_vci_rsp_data_error (set)
3919	// - r_vci_rsp_ins_error (set)
3920	// - r_vci_rsp_cpt
3921	// - r_dcache_vci_sc_req (reset when SC response recieved)
3922	//
3923	// As the VCI_RSP and VCI_CMD are fully desynchronized to support several
3924	// simultaneous VCI transactions, this FSM uses the VCI RPKTID field
3925	// to identify the transactions.
3926	//
3927	// VCI vormat:
3928	// This component checks the response packet length and accepts only
3929	// single word packets for write response packets.
3930	//
3931	// Error handling:
3932	// This FSM analyzes the VCI error code and signals directly the Write Bus Error.
3933	// In case of Read Data Error, the VCI_RSP FSM sets the r_vci_rsp_data_error
3934	// flip_flop and the error is signaled by the DCACHE FSM.
3935	// In case of Instruction Error, the VCI_RSP FSM sets the r_vci_rsp_ins_error
3936	// flip_flop and the error is signaled by the ICACHE FSM.
3937	// In case of Cleanup Error, the simulation stops with an error message...
3938	//////////////////////////////////////////////////////////////////////////
3939
3940	switch (r_vci_rsp_fsm.read()) {
3941	//////////////
3942	case RSP_IDLE:
3943	{
3944	if (p_vci.rspval.read()) {
3945	r_vci_rsp_cpt = 0;
3946
3947	if ((p_vci.rpktid.read() & 0x7) == TYPE_DATA_UNC) {
3948	r_vci_rsp_fsm = RSP_DATA_UNC;
3949	}
3950	else if ((p_vci.rpktid.read() & 0x7) == TYPE_READ_DATA_MISS) {
3951	r_vci_rsp_fsm = RSP_DATA_MISS;
3952	}
3953	else if ((p_vci.rpktid.read() & 0x7) == TYPE_READ_INS_UNC) {
3954	r_vci_rsp_fsm = RSP_INS_UNC;
3955	}
3956	else if ((p_vci.rpktid.read() & 0x7) == TYPE_READ_INS_MISS) {
3957	r_vci_rsp_fsm = RSP_INS_MISS;
3958	}
3959	else if ((p_vci.rpktid.read() & 0x7) == TYPE_WRITE) {
3960	r_vci_rsp_fsm = RSP_DATA_WRITE;
3961	}
3962	else if ((p_vci.rpktid.read() & 0x7) == TYPE_CAS) {
3963	r_vci_rsp_fsm = RSP_DATA_UNC;
3964	}
3965	else if ((p_vci.rpktid.read() & 0x7) == TYPE_LL) {
3966	r_vci_rsp_fsm = RSP_DATA_LL;
3967	}
3968	else if ((p_vci.rpktid.read() & 0x7) == TYPE_SC) {
3969	r_vci_rsp_fsm = RSP_DATA_UNC;
3970	}
3971	else {
3972	assert(false and "Unexpected VCI response");
3973	}
3974	}
3975	break;
3976	}
3977	//////////////////
3978	case RSP_INS_MISS:
3979	{
3980	if (p_vci.rspval.read()) {
3981	if ((p_vci.rerror.read() & 0x1) != 0) {
3982	r_vci_rsp_ins_error = true;
3983	if (p_vci.reop.read()) {
3984	r_vci_rsp_fsm = RSP_IDLE;
3985	}
3986	}
3987	else {
3988	if (r_vci_rsp_fifo_icache.wok()) {
3989	if (r_vci_rsp_cpt.read() >= m_icache_words) {
3990	std::cout << "ERROR in VCI_CC_VCACHE " << name()
3991	<< " VCI response packet too long "
3992	<< " for instruction miss" << std::endl;
3993	exit(0);
3994	}
3995	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
3996	vci_rsp_fifo_icache_put = true,
3997	vci_rsp_fifo_icache_data = p_vci.rdata.read();
3998	if (p_vci.reop.read()) {
3999	if (r_vci_rsp_cpt.read() != (m_icache_words - 1)) {
4000	std::cout << "ERROR in VCI_CC_VCACHE " << name()
4001	<< " VCI response packet too short"
4002	<< " for instruction miss" << std::endl;
4003	exit(0);
4004	}
4005	r_vci_rsp_fsm = RSP_IDLE;
4006	}
4007	}
4008	}
4009	}
4010	break;
4011	}
4012	/////////////////
4013	case RSP_INS_UNC:
4014	{
4015	if (p_vci.rspval.read()) {
4016	assert(p_vci.reop.read() and
4017	"illegal VCI response packet for uncachable instruction");
4018
4019	if ((p_vci.rerror.read() & 0x1) != 0) {
4020	r_vci_rsp_ins_error = true;
4021	r_vci_rsp_fsm = RSP_IDLE;
4022	}
4023	else {
4024	if (r_vci_rsp_fifo_icache.wok()) {
4025	vci_rsp_fifo_icache_put = true;
4026	vci_rsp_fifo_icache_data = p_vci.rdata.read();
4027	r_vci_rsp_fsm = RSP_IDLE;
4028	}
4029	}
4030	}
4031	break;
4032	}
4033	///////////////////
4034	case RSP_DATA_MISS:
4035	{
4036	if (p_vci.rspval.read()) {
4037	if ((p_vci.rerror.read() & 0x1) != 0) {
4038	r_vci_rsp_data_error = true;
4039	if (p_vci.reop.read()) r_vci_rsp_fsm = RSP_IDLE;
4040	}
4041	else {
4042	if (r_vci_rsp_fifo_dcache.wok()) {
4043	assert((r_vci_rsp_cpt.read() < m_dcache_words) and
4044	"The VCI response packet for data miss is too long");
4045
4046	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
4047	vci_rsp_fifo_dcache_put = true,
4048	vci_rsp_fifo_dcache_data = p_vci.rdata.read();
4049	if (p_vci.reop.read()) {
4050	assert((r_vci_rsp_cpt.read() == m_dcache_words - 1) and
4051	"The VCI response packet for data miss is too short");
4052
4053	r_vci_rsp_fsm = RSP_IDLE;
4054	}
4055	}
4056	}
4057	}
4058	break;
4059	}
4060	//////////////////
4061	case RSP_DATA_UNC:
4062	{
4063	if (p_vci.rspval.read()) {
4064	assert(p_vci.reop.read() and
4065	"illegal VCI response packet for uncachable read data");
4066
4067	if ((p_vci.rerror.read() & 0x1) != 0) {
4068	r_vci_rsp_data_error = true;
4069	r_vci_rsp_fsm = RSP_IDLE;
4070	}
4071	else {
4072	if (r_vci_rsp_fifo_dcache.wok()) {
4073	vci_rsp_fifo_dcache_put = true;
4074	vci_rsp_fifo_dcache_data = p_vci.rdata.read();
4075	r_vci_rsp_fsm = RSP_IDLE;
4076	}
4077	}
4078	}
4079	break;
4080	}
4081	/////////////////
4082	case RSP_DATA_LL:
4083	{
4084	if (p_vci.rspval.read()) {
4085	if ((p_vci.rerror.read() & 0x1) != 0) {
4086	r_vci_rsp_data_error = true;
4087	r_vci_rsp_fsm = RSP_IDLE;
4088	break;
4089	}
4090	if (r_vci_rsp_cpt.read() == 0) {
4091	if (r_vci_rsp_fifo_dcache.wok()) {
4092	assert(!p_vci.reop.read() && "illegal VCI response packet for LL");
4093	vci_rsp_fifo_dcache_put = true;
4094	vci_rsp_fifo_dcache_data = p_vci.rdata.read();
4095	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
4096	}
4097	break;
4098	}
4099	else {
4100	// last flit
4101	if (r_vci_rsp_fifo_dcache.wok()) {
4102	assert(p_vci.reop.read() &&
4103	"illegal VCI response packet for LL");
4104	vci_rsp_fifo_dcache_put = true;
4105	vci_rsp_fifo_dcache_data = p_vci.rdata.read();
4106	r_vci_rsp_fsm = RSP_IDLE;
4107	}
4108	break;
4109	}
4110	}
4111	break;
4112	}
4113	////////////////////
4114	case RSP_DATA_WRITE:
4115	{
4116	if (p_vci.rspval.read()) {
4117	assert(p_vci.reop.read() and
4118	"a VCI response packet must contain one flit for a write transaction");
4119
4120	r_vci_rsp_fsm = RSP_IDLE;
4121	uint32_t wbuf_index = p_vci.rtrdid.read();
4122	r_wbuf.completed(wbuf_index);
4123	if ((p_vci.rerror.read() & 0x1) != 0) {
4124	r_iss.setWriteBerr();
4125	}
4126	}
4127	break;
4128	}
4129	} // end switch r_vci_rsp_fsm
4130
4131
4132	///////////////// Response FIFOs update //////////////////////
4133	r_vci_rsp_fifo_icache.update(vci_rsp_fifo_icache_get,
4134	vci_rsp_fifo_icache_put,
4135	vci_rsp_fifo_icache_data);
4136
4137	r_vci_rsp_fifo_dcache.update(vci_rsp_fifo_dcache_get,
4138	vci_rsp_fifo_dcache_put,
4139	vci_rsp_fifo_dcache_data);
4140
4141
4142	} // end transition()
4143
4144
4145
4146	///////////////////////
4147	tmpl(void)::genMoore()
4148	///////////////////////
4149	{
4150	// VCI initiator command on the direct network
4151	// it depends on the CMD FSM state
4152
4153	bool is_sc_or_cas = (r_vci_cmd_fsm.read() == CMD_DATA_CAS) or
4154	(r_vci_cmd_fsm.read() == CMD_DATA_SC);
4155
4156	p_vci.pktid = 0;
4157	p_vci.srcid = m_srcid;
4158	p_vci.cons = is_sc_or_cas;
4159	p_vci.contig = not is_sc_or_cas;
4160	p_vci.wrap = false;
4161	p_vci.clen = 0;
4162	p_vci.cfixed = false;
4163
4164	if (m_monitor_ok) {
4165	if (p_vci.cmdack.read() == true and p_vci.cmdval == true) {
4166	if (((p_vci.address.read()) >= m_monitor_base) and
4167	((p_vci.address.read()) < m_monitor_base + m_monitor_length)) {
4168	std::cout << "CC_VCACHE Monitor " << name() << std::hex
4169	<< " Access type = " << vci_cmd_type_str[p_vci.cmd.read()]
4170	<< " Pktid type = " << vci_pktid_type_str[p_vci.pktid.read()]
4171	<< " : address = " << p_vci.address.read()
4172	<< " / be = " << p_vci.be.read();
4173	if (p_vci.cmd.read() == vci_param::CMD_WRITE) {
4174	std::cout << " / data = " << p_vci.wdata.read();
4175	}
4176	std::cout << std::dec << std::endl;
4177	}
4178	}
4179	}
4180
4181	switch (r_vci_cmd_fsm.read()) {
4182
4183	case CMD_IDLE:
4184	p_vci.cmdval = false;
4185	p_vci.address = 0;
4186	p_vci.wdata = 0;
4187	p_vci.be = 0;
4188	p_vci.trdid = 0;
4189	p_vci.pktid = 0;
4190	p_vci.plen = 0;
4191	p_vci.cmd = vci_param::CMD_NOP;
4192	p_vci.eop = false;
4193	break;
4194
4195	case CMD_INS_MISS:
4196	p_vci.cmdval = true;
4197	p_vci.address = r_icache_vci_paddr.read() & m_icache_yzmask;
4198	p_vci.wdata = 0;
4199	p_vci.be = 0xF;
4200	p_vci.trdid = 0;
4201	p_vci.pktid = TYPE_READ_INS_MISS;
4202	p_vci.plen = m_icache_words << 2;
4203	p_vci.cmd = vci_param::CMD_READ;
4204	p_vci.eop = true;
4205	break;
4206
4207	case CMD_INS_UNC:
4208	p_vci.cmdval = true;
4209	p_vci.address = r_icache_vci_paddr.read() & ~0x3;
4210	p_vci.wdata = 0;
4211	p_vci.be = 0xF;
4212	p_vci.trdid = 0;
4213	p_vci.pktid = TYPE_READ_INS_UNC;
4214	p_vci.plen = 4;
4215	p_vci.cmd = vci_param::CMD_READ;
4216	p_vci.eop = true;
4217	break;
4218
4219	case CMD_DATA_MISS:
4220	p_vci.cmdval = true;
4221	p_vci.address = r_dcache_vci_paddr.read() & m_dcache_yzmask;
4222	p_vci.wdata = 0;
4223	p_vci.be = 0xF;
4224	p_vci.trdid = 0;
4225	p_vci.pktid = TYPE_READ_DATA_MISS;
4226	p_vci.plen = m_dcache_words << 2;
4227	p_vci.cmd = vci_param::CMD_READ;
4228	p_vci.eop = true;
4229	break;
4230
4231	case CMD_DATA_UNC_READ:
4232	p_vci.cmdval = true;
4233	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
4234	p_vci.wdata = 0;
4235	p_vci.be = r_dcache_vci_unc_be.read();
4236	p_vci.trdid = 0;
4237	p_vci.pktid = TYPE_DATA_UNC;
4238	p_vci.plen = 4;
4239	p_vci.cmd = vci_param::CMD_READ;
4240	p_vci.eop = true;
4241	break;
4242
4243	case CMD_DATA_UNC_WRITE:
4244	p_vci.cmdval = true;
4245	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
4246	p_vci.wdata = r_dcache_vci_wdata.read();
4247	p_vci.be = r_dcache_vci_unc_be.read();
4248	p_vci.trdid = 0;
4249	p_vci.pktid = TYPE_DATA_UNC;
4250	p_vci.plen = 4;
4251	p_vci.cmd = vci_param::CMD_WRITE;
4252	p_vci.eop = true;
4253	break;
4254
4255	case CMD_DATA_WRITE:
4256	p_vci.cmdval = true;
4257	p_vci.address = r_wbuf.getAddress(r_vci_cmd_cpt.read()) & ~0x3;
4258	p_vci.wdata = r_wbuf.getData(r_vci_cmd_cpt.read());
4259	p_vci.be = r_wbuf.getBe(r_vci_cmd_cpt.read());
4260	p_vci.trdid = r_wbuf.getIndex();
4261	p_vci.pktid = TYPE_WRITE;
4262	p_vci.plen = (r_vci_cmd_max.read() - r_vci_cmd_min.read() + 1) << 2;
4263	p_vci.cmd = vci_param::CMD_WRITE;
4264	p_vci.eop = (r_vci_cmd_cpt.read() == r_vci_cmd_max.read());
4265	break;
4266
4267	case CMD_DATA_LL:
4268	p_vci.cmdval = true;
4269	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
4270	p_vci.wdata = 0;
4271	p_vci.be = 0xF;
4272	p_vci.trdid = 0;
4273	p_vci.pktid = TYPE_LL;
4274	p_vci.plen = 8;
4275	p_vci.cmd = vci_param::CMD_LOCKED_READ;
4276	p_vci.eop = true;
4277	break;
4278
4279	case CMD_DATA_SC:
4280	p_vci.cmdval = true;
4281	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
4282	if (r_vci_cmd_cpt.read() == 0) p_vci.wdata = r_dcache_llsc_key.read();
4283	else p_vci.wdata = r_dcache_vci_sc_data.read();
4284	p_vci.be = 0xF;
4285	p_vci.trdid = 0;
4286	p_vci.pktid = TYPE_SC;
4287	p_vci.plen = 8;
4288	p_vci.cmd = vci_param::CMD_NOP;
4289	p_vci.eop = (r_vci_cmd_cpt.read() == 1);
4290	break;
4291
4292	case CMD_DATA_CAS:
4293	p_vci.cmdval = true;
4294	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
4295	if (r_vci_cmd_cpt.read() == 0) {
4296	p_vci.wdata = r_dcache_vci_cas_old.read();
4297	}
4298	else {
4299	p_vci.wdata = r_dcache_vci_cas_new.read();
4300	}
4301	p_vci.be = 0xF;
4302	p_vci.trdid = 0;
4303	p_vci.pktid = TYPE_CAS;
4304	p_vci.plen = 8;
4305	p_vci.cmd = vci_param::CMD_NOP;
4306	p_vci.eop = (r_vci_cmd_cpt.read() == 1);
4307	break;
4308	} // end switch r_vci_cmd_fsm
4309
4310	// VCI initiator response on the direct network
4311	// it depends on the VCI_RSP FSM
4312
4313	switch (r_vci_rsp_fsm.read()) {
4314	case RSP_DATA_WRITE : p_vci.rspack = true; break;
4315	case RSP_INS_MISS : p_vci.rspack = r_vci_rsp_fifo_icache.wok(); break;
4316	case RSP_INS_UNC : p_vci.rspack = r_vci_rsp_fifo_icache.wok(); break;
4317	case RSP_DATA_MISS : p_vci.rspack = r_vci_rsp_fifo_dcache.wok(); break;
4318	case RSP_DATA_UNC : p_vci.rspack = r_vci_rsp_fifo_dcache.wok(); break;
4319	case RSP_DATA_LL : p_vci.rspack = r_vci_rsp_fifo_dcache.wok(); break;
4320	case RSP_IDLE : p_vci.rspack = false; break;
4321	} // end switch r_vci_rsp_fsm
4322
4323
4324	// No coherence
4325	p_dspin_p2m.write = false;
4326	p_dspin_p2m.eop = false;
4327	p_dspin_p2m.data = 0;
4328
4329	p_dspin_m2p.read = false;
4330	p_dspin_clack.read = false;
4331
4332	} // end genMoore
4333
4334	tmpl(void)::start_monitor(paddr_t base, paddr_t length)
4335	// This version of monitor print both Read and Write request
4336	{
4337	m_monitor_ok = true;
4338	m_monitor_base = base;
4339	m_monitor_length = length;
4340	}
4341
4342	tmpl(void)::stop_monitor() {
4343	m_monitor_ok = false;
4344	}
4345
4346	}}
4347
4348	// Local Variables:
4349	// tab-width: 4
4350	// c-basic-offset: 4
4351	// c-file-offsets:((innamespace . 0)(inline-open . 0))
4352	// indent-tabs-mode: nil
4353	// End:
4354
4355	// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4

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