source: trunk/modules/vci_block_device_tsar/caba/source/include/vci_block_device_tsar.h @ 733

Last change on this file since 733 was 733, checked in by alain, 10 years ago

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1
2/* -*- c++ -*-
3 *
4 * SOCLIB_LGPL_HEADER_BEGIN
5 *
6 * This file is part of SoCLib, GNU LGPLv2.1.
7 *
8 * SoCLib is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU Lesser General Public License as published
10 * by the Free Software Foundation; version 2.1 of the License.
11 *
12 * SoCLib is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with SoCLib; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 * SOCLIB_LGPL_HEADER_END
23 *
24 * Copyright (c) UPMC, Lip6, Asim
25 *         alain.greiner@lip6.fr april 2011
26 *
27 * Maintainers: alain
28 */
29
30//////////////////////////////////////////////////////////////////////////////////////
31// This component is a simplified disk controller with a VCI interface.
32// It supports only 32 or 64 bits VCI DATA width, but all addressable registers
33// contain 32 bits words. It supports VCI addresss lartger than 32 bits.
34//
35// This component can perform data transfers between one single file (belonging
36// to the host system) and a buffer in the memory of the virtual prototype.
37// The name of the file containing the disk image is a constructor argument.
38// This component has a DMA capability, and is both a target and an initiator.
39// The block size (bytes), and the burst size (bytes) must be power of 2.
40// The burst size is typically a cache line.
41// The memory buffer is not constrained to be aligned on a burst boundary,
42// but must be aligned on a 32 bits word boundary.
43// Both read and write transfers are supported. An IRQ is optionally
44// asserted when the transfer is completed.
45//
46// As a target this block device controler contains 9 32 bits memory mapped registers,
47// taking 36 bytes in the address space.
48// - BLOCK_DEVICE_BUFFER        0x00 (read/write)  Memory buffer base address (LSB bits)
49// - BLOCK_DEVICE_COUNT         0x04 (read/write)  Number of blocks to be transfered.
50// - BLOCK_DEVICE_LBA           0x08 (read/write)  Index of first block in the file.
51// - BLOCK_DEVICE_OP            0x0C (write-only)  Writing here starts the operation.
52// - BLOCK_DEVICE_STATUS        0x10 (read-only)   Block Device status.
53// - BLOCK_DEVICE_IRQ_ENABLE    0x14 (read/write)  IRQ enabled if non zero.
54// - BLOCK_DEVICE_SIZE          0x18 (read-only)   Number of addressable blocks.
55// - BLOCK_DEVICE_BLOCK_SIZE    0x1C (read_only)   Block size in bytes.
56// - BLOCK_DEVICE_BUFFER_EXT    0x20 (read/write)  Memory buffer base address (MSB bits)
57//
58// The following operations codes are supported:
59// - BLOCK_DEVICE_NOOP          No operation
60// - BLOCK_DEVICE_READ          From block device to memory
61// - BLOCK_DEVICE_WRITE         From memory to block device
62//
63// The BLOCK_DEVICE_STATUS is actually defined by the initiator FSM state.
64// The following values are defined for device status:
65// -BLOCK_DEVICE_IDLE           0
66// -BLOCK_DEVICE_BUSY           1
67// -BLOCK_DEVICE_READ_SUCCESS   2
68// -BLOCK_DEVICE_WRITE_SUCCESS  3
69// -BLOCK_DEVICE_READ_ERROR     4
70// -BLOCK_DEVICE_WRITE_ERROR    5
71//
72// In the 4 states READ_ERROR, READ_SUCCESS, WRITE_ERROR, WRITE_SUCCESS,
73// the IRQ is asserted (if it is enabled).
74// A read access to the BLOCK_DEVICE_STATUS in these 4 states reset
75// the initiator FSM state to IDLE, and acknowledge the IRQ.
76// Any write access to registers BUFFER, COUNT, LBA, OP is ignored
77// if the device is not IDLE.
78///////////////////////////////////////////////////////////////////////////
79
80#ifndef SOCLIB_VCI_BLOCK_DEVICE_TSAR_H
81#define SOCLIB_VCI_BLOCK_DEVICE_TSAR_H
82
83#include <stdint.h>
84#include <systemc>
85#include <unistd.h>
86#include "caba_base_module.h"
87#include "mapping_table.h"
88#include "vci_initiator.h"
89#include "vci_target.h"
90
91namespace soclib {
92namespace caba {
93
94using namespace sc_core;
95
96template<typename vci_param>
97class VciBlockDeviceTsar
98        : public caba::BaseModule
99{
100private:
101
102    // Registers
103    sc_signal<int>                     r_target_fsm;       // target fsm state register
104    sc_signal<int>                     r_initiator_fsm;    // initiator fsm state register
105    sc_signal<bool>                    r_irq_enable;       // default value is true
106    sc_signal<uint32_t>                r_nblocks;          // number of blocks in transfer
107    sc_signal<uint64_t>                r_buf_address;      // memory buffer address
108    sc_signal<uint32_t>                r_lba;              // first block index
109    sc_signal<bool>                    r_read;             // requested operation
110    sc_signal<uint32_t>                r_index;            // word index in local buffer
111    sc_signal<uint32_t>                r_latency_count;    // latency counter
112    sc_signal<uint32_t>                r_words_count;      // word counter (in a burst)
113    sc_signal<uint32_t>                r_burst_count;      // burst counter (in a block)
114    sc_signal<uint32_t>                r_block_count;      // block counter (in a transfer)
115    sc_signal<uint32_t>                r_burst_offset;     // number of non aligned words
116    sc_signal<uint32_t>                r_burst_nwords;     // number of words in a burst
117    sc_signal<bool>                    r_go;               // command from T_FSM to M_FSM
118
119    sc_signal<typename vci_param::srcid_t >     r_srcid;   // save srcid
120    sc_signal<typename vci_param::trdid_t >     r_trdid;   // save trdid
121    sc_signal<typename vci_param::pktid_t >     r_pktid;   // save pktid
122    sc_signal<typename vci_param::data_t >      r_tdata;   // save wdata
123
124    uint32_t*                          r_local_buffer;     // capacity is one block
125
126    // structural parameters
127    std::list<soclib::common::Segment> m_seglist;
128    uint32_t                           m_srcid;            // initiator index
129    int                                m_fd;               // File descriptor
130    uint64_t                           m_device_size;      // Total number of blocks
131    const uint32_t                     m_words_per_block;  // number of words in a block
132    const uint32_t                     m_words_per_burst;  // number of words in a burst
133    const uint32_t                     m_bursts_per_block; // number of bursts in a block
134    const uint32_t                     m_latency;          // device latency
135
136    // methods
137    void transition();
138    void genMoore();
139
140    //  Master FSM states
141    enum {
142    M_IDLE              = 0,
143
144    M_READ_BLOCK        = 1,
145    M_READ_BURST        = 2,
146    M_READ_CMD          = 3,
147    M_READ_RSP          = 4,
148    M_READ_SUCCESS      = 5,
149    M_READ_ERROR        = 6,
150
151    M_WRITE_BURST       = 7,
152    M_WRITE_CMD         = 8,
153    M_WRITE_RSP         = 9,
154    M_WRITE_BLOCK       = 10,
155    M_WRITE_SUCCESS     = 11,
156    M_WRITE_ERROR       = 12,
157    };
158
159    // Target FSM states
160    enum {
161    T_IDLE              = 0,
162    T_WRITE_BUFFER      = 1,
163    T_READ_BUFFER       = 2,
164    T_WRITE_BUFFER_EXT  = 3,
165    T_READ_BUFFER_EXT   = 4,
166    T_WRITE_COUNT       = 5,
167    T_READ_COUNT        = 6,
168    T_WRITE_LBA         = 7,
169    T_READ_LBA          = 8,
170    T_WRITE_OP          = 9,
171    T_READ_STATUS       = 10,
172    T_WRITE_IRQEN       = 11,
173    T_READ_IRQEN        = 12,
174    T_READ_SIZE         = 13,
175    T_READ_BLOCK        = 14,
176    T_READ_ERROR        = 15,
177    T_WRITE_ERROR       = 16,
178    };
179
180    // Error codes values
181    enum {
182    VCI_READ_OK         = 0,
183    VCI_READ_ERROR      = 1,
184    VCI_WRITE_OK        = 2,
185    VCI_WRITE_ERROR     = 3,
186    };
187
188    /* transaction type, pktid field */
189    enum transaction_type_e
190    {
191      // b3 unused
192      // b2 READ / NOT READ
193      // Si READ
194      //  b1 DATA / INS
195      //  b0 UNC / MISS
196      // Si NOT READ
197      //  b1 accÚs table llsc type SW / other
198      //  b2 WRITE/CAS/LL/SC
199      TYPE_READ_DATA_UNC          = 0x0,
200      TYPE_READ_DATA_MISS         = 0x1,
201      TYPE_READ_INS_UNC           = 0x2,
202      TYPE_READ_INS_MISS          = 0x3,
203      TYPE_WRITE                  = 0x4,
204      TYPE_CAS                    = 0x5,
205      TYPE_LL                     = 0x6,
206      TYPE_SC                     = 0x7
207    };
208
209protected:
210
211    SC_HAS_PROCESS(VciBlockDeviceTsar);
212
213public:
214
215    // ports
216    sc_in<bool>                                               p_clk;
217    sc_in<bool>                                               p_resetn;
218    soclib::caba::VciInitiator<vci_param> p_vci_initiator;
219    soclib::caba::VciTarget<vci_param>    p_vci_target;
220    sc_out<bool>                                              p_irq;
221
222    void print_trace();
223
224    // Constructor   
225    VciBlockDeviceTsar(
226                sc_module_name                      name,
227                const soclib::common::MappingTable      &mt,
228                const soclib::common::IntTab            &srcid,
229                const soclib::common::IntTab            &tgtid,
230        const std::string                   &filename,
231        const uint32_t                      block_size = 512,
232        const uint32_t                      burst_size = 64,
233        const uint32_t                      latency = 0);
234
235    ~VciBlockDeviceTsar();
236
237};
238
239}}
240
241#endif /* SOCLIB_VCI_BLOCK_DEVICE_TSAR_H */
242
243// Local Variables:
244// tab-width: 4
245// c-basic-offset: 4
246// c-file-offsets:((innamespace . 0)(inline-open . 0))
247// indent-tabs-mode: nil
248// End:
249
250// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
251
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