source: trunk/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h @ 513

Last change on this file since 513 was 487, checked in by haoliu, 11 years ago

Bug fixed in vci_cc_vcache_wrapper component:
1) The r_dcache_paddr_ext is utiliszed in the state DCACHE_XTN_DC_INVAL_VA(DCACHE FSM)
for constructing the physical address when the tlb is not activated.

2) In the ICACHE FSM and DCACHE FSM, the state MISS_SELECT will not be blocked by the
r_icache_cc_send_req (r_dcache_cc_send_req for DCACHE FSM) when a victim solt is found,
because we should assure that the cache L1 can consume the response of the miss read
request when the response has arrived.
(The reason of this condtion comes from a deadlock detected in the above version)

A new filp-flop is utilized in the ICACHE FSM (same in DCACHE FSM) for saving the cleanup victim
request when the r_icache_cc_send_req is true. This saving request will be sent later
in the states MISS_WAIT or MISS_UPDT_DIR when r_icache_cc_send_req is false.

File size: 34.3 KB
Line 
1/* -*- c++ -*-
2 *
3 * File : vci_cc_vcache_wrapper.h
4 * Copyright (c) UPMC, Lip6, SoC
5 * Authors : Alain GREINER, Yang GAO
6 * Date : 27/11/2011
7 *
8 * SOCLIB_LGPL_HEADER_BEGIN
9 *
10 * This file is part of SoCLib, GNU LGPLv2.1.
11 *
12 * SoCLib is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU Lesser General Public License as published
14 * by the Free Software Foundation; version 2.1 of the License.
15 *
16 * SoCLib is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
19 * Lesser General Public License for more details.
20 *
21 * You should have received a copy of the GNU Lesser General Public
22 * License along with SoCLib; if not, write to the Free Software
23 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
24 * 02110-1301 USA
25 *
26 * SOCLIB_LGPL_HEADER_END
27 *
28 * Maintainers: cesar.fuguet-tortolero@lip6.fr
29 *              alexandre.joannou@lip6.fr
30 */
31
32#ifndef SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER_H
33#define SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER_H
34
35#include <inttypes.h>
36#include <systemc>
37#include "caba_base_module.h"
38#include "multi_write_buffer.h"
39#include "generic_fifo.h"
40#include "generic_tlb.h"
41#include "generic_cache.h"
42#include "vci_initiator.h"
43#include "dspin_interface.h"
44#include "dspin_dhccp_param.h"
45#include "mapping_table.h"
46#include "static_assert.h"
47#include "iss2.h"
48
49#define LLSC_TIMEOUT    10000
50
51namespace soclib {
52namespace caba {
53
54using namespace sc_core;
55
56////////////////////////////////////////////
57template<typename vci_param, 
58         size_t   dspin_in_width,
59         size_t   dspin_out_width,
60         typename iss_t>
61class VciCcVCacheWrapper
62////////////////////////////////////////////
63    : public soclib::caba::BaseModule
64{
65
66    typedef typename vci_param::fast_addr_t  paddr_t;
67
68    enum icache_fsm_state_e
69    {
70        ICACHE_IDLE,
71        // handling XTN processor requests
72        ICACHE_XTN_TLB_FLUSH,
73        ICACHE_XTN_CACHE_FLUSH,
74        ICACHE_XTN_CACHE_FLUSH_GO,
75        ICACHE_XTN_TLB_INVAL,
76        ICACHE_XTN_CACHE_INVAL_VA,
77        ICACHE_XTN_CACHE_INVAL_PA,
78        ICACHE_XTN_CACHE_INVAL_GO,
79        // handling tlb miss
80        ICACHE_TLB_WAIT,
81        // handling cache miss
82        ICACHE_MISS_SELECT,
83        ICACHE_MISS_CLEAN,
84        ICACHE_MISS_WAIT,
85        ICACHE_MISS_DATA_UPDT,
86        ICACHE_MISS_DIR_UPDT,
87        // handling unc read
88        ICACHE_UNC_WAIT,
89        // handling coherence requests
90        ICACHE_CC_CHECK,
91        ICACHE_CC_UPDT,
92        ICACHE_CC_INVAL,
93    };
94
95    enum dcache_fsm_state_e
96    {
97        DCACHE_IDLE,
98        // handling itlb & dtlb miss
99        DCACHE_TLB_MISS,
100        DCACHE_TLB_PTE1_GET,
101        DCACHE_TLB_PTE1_SELECT,
102        DCACHE_TLB_PTE1_UPDT,
103        DCACHE_TLB_PTE2_GET,
104        DCACHE_TLB_PTE2_SELECT,
105        DCACHE_TLB_PTE2_UPDT,
106        DCACHE_TLB_LR_UPDT,
107        DCACHE_TLB_LR_WAIT,
108        DCACHE_TLB_RETURN,
109            // handling processor XTN requests
110        DCACHE_XTN_SWITCH,
111        DCACHE_XTN_SYNC,
112        DCACHE_XTN_IC_INVAL_VA,
113        DCACHE_XTN_IC_FLUSH,
114        DCACHE_XTN_IC_INVAL_PA,
115        DCACHE_XTN_IT_INVAL,
116        DCACHE_XTN_DC_FLUSH,
117        DCACHE_XTN_DC_FLUSH_GO,
118        DCACHE_XTN_DC_INVAL_VA,
119        DCACHE_XTN_DC_INVAL_PA,
120        DCACHE_XTN_DC_INVAL_END,
121        DCACHE_XTN_DC_INVAL_GO,
122        DCACHE_XTN_DT_INVAL,
123        //handling dirty bit update
124        DCACHE_DIRTY_GET_PTE,
125        DCACHE_DIRTY_WAIT,
126            // handling processor miss requests
127        DCACHE_MISS_SELECT,
128        DCACHE_MISS_CLEAN,
129        DCACHE_MISS_WAIT,
130        DCACHE_MISS_DATA_UPDT,
131        DCACHE_MISS_DIR_UPDT,
132        // handling processor unc, ll and sc requests
133        DCACHE_UNC_WAIT,
134        DCACHE_LL_WAIT,
135        DCACHE_SC_WAIT,
136        // handling coherence requests
137        DCACHE_CC_CHECK,
138        DCACHE_CC_UPDT,
139        DCACHE_CC_INVAL,
140        // handling TLB inval (after a coherence or XTN request)
141        DCACHE_INVAL_TLB_SCAN,
142    };
143
144    enum cmd_fsm_state_e
145    {
146        CMD_IDLE,
147        CMD_INS_MISS,
148        CMD_INS_UNC,
149        CMD_DATA_MISS,
150        CMD_DATA_UNC,
151        CMD_DATA_WRITE,
152        CMD_DATA_LL,
153        CMD_DATA_SC,
154        CMD_DATA_CAS,
155    };
156
157    enum rsp_fsm_state_e
158    {
159        RSP_IDLE,
160        RSP_INS_MISS,
161        RSP_INS_UNC,
162        RSP_DATA_MISS,
163        RSP_DATA_UNC,
164        RSP_DATA_LL,
165        RSP_DATA_WRITE,
166    };
167
168    enum cc_receive_fsm_state_e
169    {
170        CC_RECEIVE_IDLE,
171        CC_RECEIVE_BRDCAST_HEADER,
172        CC_RECEIVE_BRDCAST_NLINE,
173        CC_RECEIVE_INS_INVAL_HEADER,
174        CC_RECEIVE_INS_INVAL_NLINE,
175        CC_RECEIVE_INS_UPDT_HEADER,
176        CC_RECEIVE_INS_UPDT_NLINE,
177        CC_RECEIVE_DATA_INVAL_HEADER,
178        CC_RECEIVE_DATA_INVAL_NLINE,
179        CC_RECEIVE_DATA_UPDT_HEADER,
180        CC_RECEIVE_DATA_UPDT_NLINE,
181        CC_RECEIVE_INS_UPDT_DATA,
182        CC_RECEIVE_DATA_UPDT_DATA,
183    };
184
185    enum cc_send_fsm_state_e
186    {
187        CC_SEND_IDLE,
188        CC_SEND_CLEANUP_1,
189        CC_SEND_CLEANUP_2,
190        CC_SEND_MULTI_ACK,
191    };
192
193    /* transaction type, pktid field */
194    enum transaction_type_e
195    {
196        // b3 unused
197        // b2 READ / NOT READ
198        // if READ
199        //  b1 DATA / INS
200        //  b0 UNC / MISS
201        // else
202        //  b1 accÚs table llsc type SW / other
203        //  b2 WRITE/CAS/LL/SC
204        TYPE_READ_DATA_UNC          = 0x0,
205        TYPE_READ_DATA_MISS         = 0x1,
206        TYPE_READ_INS_UNC           = 0x2,
207        TYPE_READ_INS_MISS          = 0x3,
208        TYPE_WRITE                  = 0x4,
209        TYPE_CAS                    = 0x5,
210        TYPE_LL                     = 0x6,
211        TYPE_SC                     = 0x7
212    };
213
214    /* SC return values */
215    enum sc_status_type_e
216    {
217        SC_SUCCESS  =   0x00000000,
218        SC_FAIL     =   0x00000001
219    };
220
221    // cc_send_type
222    typedef enum 
223    {
224        CC_TYPE_CLEANUP,
225        CC_TYPE_MULTI_ACK,
226    } cc_send_t;
227
228    // cc_receive_type
229    typedef enum 
230    {
231        CC_TYPE_CLACK,
232        CC_TYPE_BRDCAST,
233        CC_TYPE_INVAL,
234        CC_TYPE_UPDT,
235    } cc_receive_t;
236
237    // TLB Mode : ITLB / DTLB / ICACHE / DCACHE
238    enum 
239    {
240        INS_TLB_MASK    = 0x8,
241        DATA_TLB_MASK   = 0x4,
242        INS_CACHE_MASK  = 0x2,
243        DATA_CACHE_MASK = 0x1,
244    };
245
246    // Error Type
247    enum mmu_error_type_e
248    {
249        MMU_NONE                      = 0x0000, // None
250        MMU_WRITE_PT1_UNMAPPED        = 0x0001, // Write & Page fault on PT1
251        MMU_WRITE_PT2_UNMAPPED        = 0x0002, // Write & Page fault on PT2
252        MMU_WRITE_PRIVILEGE_VIOLATION = 0x0004, // Write & Protected access in user mode
253        MMU_WRITE_ACCES_VIOLATION     = 0x0008, // Write to non writable page
254        MMU_WRITE_UNDEFINED_XTN       = 0x0020, // Write & undefined external access
255        MMU_WRITE_PT1_ILLEGAL_ACCESS  = 0x0040, // Write & Bus Error accessing PT1
256        MMU_WRITE_PT2_ILLEGAL_ACCESS  = 0x0080, // Write & Bus Error accessing PT2
257        MMU_WRITE_DATA_ILLEGAL_ACCESS = 0x0100, // Write & Bus Error in cache access
258        MMU_READ_PT1_UNMAPPED         = 0x1001, // Read & Page fault on PT1
259        MMU_READ_PT2_UNMAPPED         = 0x1002, // Read & Page fault on PT2
260        MMU_READ_PRIVILEGE_VIOLATION  = 0x1004, // Read & Protected access in user mode
261        MMU_READ_EXEC_VIOLATION       = 0x1010, // Read & Exec access to a non exec page
262        MMU_READ_UNDEFINED_XTN        = 0x1020, // Read & Undefined external access
263        MMU_READ_PT1_ILLEGAL_ACCESS   = 0x1040, // Read & Bus Error accessing PT1
264        MMU_READ_PT2_ILLEGAL_ACCESS   = 0x1080, // Read & Bus Error accessing PT2
265        MMU_READ_DATA_ILLEGAL_ACCESS  = 0x1100, // Read & Bus Error in cache access
266    };
267
268    // miss types for data cache
269    enum dcache_miss_type_e
270    {
271        PTE1_MISS,
272        PTE2_MISS,
273        PROC_MISS,
274    };
275
276    enum transaction_type_d_e
277    {
278        // b0 : 1 if cached
279        // b1 : 1 if instruction
280        TYPE_DATA_UNC     = 0x0,
281        TYPE_DATA_MISS    = 0x1,
282        TYPE_INS_UNC      = 0x2,
283        TYPE_INS_MISS     = 0x3,
284    };
285
286public:
287    sc_in<bool>                                p_clk;
288    sc_in<bool>                                p_resetn;
289    sc_in<bool>                                p_irq[iss_t::n_irq];
290    soclib::caba::VciInitiator<vci_param>      p_vci;
291    soclib::caba::DspinInput<dspin_in_width>   p_dspin_m2p;
292    soclib::caba::DspinOutput<dspin_out_width> p_dspin_p2m;
293    soclib::caba::DspinInput<dspin_in_width>   p_dspin_clack;
294
295private:
296
297    // STRUCTURAL PARAMETERS
298    soclib::common::AddressDecodingTable<uint32_t, bool> m_cacheability_table;
299
300    const size_t                        m_srcid;
301    const size_t                        m_cc_global_id;
302    const size_t                        m_nline_width;
303    const size_t                                                m_itlb_ways;
304    const size_t                                                m_itlb_sets;
305    const size_t                                                m_dtlb_ways;
306    const size_t                                                m_dtlb_sets;
307    const size_t                                                m_icache_ways;
308    const size_t                                                m_icache_sets;
309    const paddr_t                                               m_icache_yzmask;
310    const size_t                                                m_icache_words;
311    const size_t                                                m_dcache_ways;
312    const size_t                                                m_dcache_sets;
313    const paddr_t                                               m_dcache_yzmask;
314    const size_t                                                m_dcache_words;
315    const size_t                        m_x_width;
316    const size_t                        m_y_width;
317    const size_t                        m_proc_id;
318    const uint32_t                                              m_max_frozen_cycles;
319    const size_t                                                m_paddr_nbits;
320    uint32_t                            m_debug_start_cycle;
321    bool                                m_debug_ok;
322
323    ////////////////////////////////////////
324    // Communication with processor ISS
325    ////////////////////////////////////////
326    typename iss_t::InstructionRequest  m_ireq;
327    typename iss_t::InstructionResponse m_irsp;
328    typename iss_t::DataRequest         m_dreq;
329    typename iss_t::DataResponse        m_drsp;
330
331    /////////////////////////////////////////////
332    // debug variables
333    /////////////////////////////////////////////
334    bool                                m_debug_previous_i_hit;
335    bool                                m_debug_previous_d_hit;
336    bool                                m_debug_activated;
337
338    ///////////////////////////////
339    // Software visible REGISTERS
340    ///////////////////////////////
341    sc_signal<uint32_t>     r_mmu_ptpr;                 // page table pointer register
342    sc_signal<uint32_t>     r_mmu_mode;                 // mmu mode register
343    sc_signal<uint32_t>     r_mmu_word_lo;              // mmu misc data low
344    sc_signal<uint32_t>     r_mmu_word_hi;              // mmu misc data hight
345    sc_signal<uint32_t>     r_mmu_ibvar;                // mmu bad instruction address
346    sc_signal<uint32_t>     r_mmu_dbvar;                // mmu bad data address
347    sc_signal<uint32_t>     r_mmu_ietr;                 // mmu instruction error type
348    sc_signal<uint32_t>     r_mmu_detr;                 // mmu data error type
349    uint32_t                r_mmu_params;                       // read-only
350    uint32_t                r_mmu_release;                      // read_only
351
352
353    //////////////////////////////
354    // ICACHE FSM REGISTERS
355    //////////////////////////////
356    sc_signal<int>          r_icache_fsm;               // state register
357    sc_signal<int>          r_icache_fsm_save;          // return state for coherence op
358    sc_signal<paddr_t>      r_icache_vci_paddr;         // physical address
359    sc_signal<uint32_t>     r_icache_vaddr_save;        // virtual address from processor
360
361    // icache miss handling
362    sc_signal<size_t>       r_icache_miss_way;              // selected way for cache update
363    sc_signal<size_t>       r_icache_miss_set;              // selected set for cache update
364    sc_signal<size_t>       r_icache_miss_word;             // word index ( cache update)
365    sc_signal<bool>         r_icache_miss_inval;        // coherence request matching a miss
366    sc_signal<bool>         r_icache_miss_clack;        // waiting for a cleanup acknowledge
367
368    // coherence request handling
369    sc_signal<size_t>       r_icache_cc_way;                // selected way for cc update/inval
370    sc_signal<size_t>       r_icache_cc_set;                // selected set for cc update/inval
371    sc_signal<size_t>       r_icache_cc_word;               // word counter for cc update
372    sc_signal<bool>         r_icache_cc_need_write;     // activate the cache for writing
373
374    // coherence clack handling
375    sc_signal<bool>         r_icache_clack_req;         // clack request
376    sc_signal<size_t>       r_icache_clack_way;             // clack way
377    sc_signal<size_t>       r_icache_clack_set;             // clack set
378
379    // icache flush handling
380    sc_signal<size_t>       r_icache_flush_count;           // slot counter used for cache flush
381
382    // communication between ICACHE FSM and VCI_CMD FSM
383    sc_signal<bool>         r_icache_miss_req;           // cached read miss
384    sc_signal<bool>         r_icache_unc_req;            // uncached read miss
385
386    // communication between ICACHE FSM and DCACHE FSM
387    sc_signal<bool>             r_icache_tlb_miss_req;       // (set icache/reset dcache)
388    sc_signal<bool>         r_icache_tlb_rsp_error;      // tlb miss response error
389
390    // Filp-Flop in ICACHE FSM for saving the cleanup victim request
391    sc_signal<bool>         r_icache_cleanup_victim_req; 
392    sc_signal<paddr_t>      r_icache_cleanup_victim_nline;
393
394    // communication between ICACHE FSM and CC_SEND FSM
395    sc_signal<bool>         r_icache_cc_send_req;           // ICACHE cc_send request
396    sc_signal<cc_send_t>    r_icache_cc_send_type;          // ICACHE cc_send request type
397    sc_signal<paddr_t>      r_icache_cc_send_nline;         // ICACHE cc_send nline
398    sc_signal<size_t>       r_icache_cc_send_way;           // ICACHE cc_send way
399    sc_signal<size_t>       r_icache_cc_send_updt_tab_idx;  // ICACHE cc_send update table index
400
401    ///////////////////////////////
402    // DCACHE FSM REGISTERS
403    ///////////////////////////////
404    sc_signal<int>          r_dcache_fsm;               // state register
405    sc_signal<int>          r_dcache_fsm_cc_save;       // return state for coherence op
406    sc_signal<int>          r_dcache_fsm_scan_save;     // return state for tlb scan op
407    // registers written in P0 stage (used in P1 stage)
408    sc_signal<bool>         r_dcache_wbuf_req;          // WBUF must be written in P1 stage
409    sc_signal<bool>         r_dcache_updt_req;          // DCACHE must be updated in P1 stage
410    sc_signal<uint32_t>     r_dcache_save_vaddr;        // virtual address (from proc)
411    sc_signal<uint32_t>     r_dcache_save_wdata;        // write data (from proc)
412    sc_signal<uint32_t>     r_dcache_save_be;           // byte enable (from proc)
413    sc_signal<paddr_t>      r_dcache_save_paddr;        // physical address
414    sc_signal<bool>         r_dcache_save_cacheable;    // address cacheable
415    sc_signal<size_t>       r_dcache_save_cache_way;    // selected way (from dcache)
416    sc_signal<size_t>       r_dcache_save_cache_set;    // selected set (from dcache)
417    sc_signal<size_t>       r_dcache_save_cache_word;   // selected word (from dcache)
418    // registers used by the Dirty bit sub-fsm
419    sc_signal<paddr_t>      r_dcache_dirty_paddr;       // PTE physical address
420    sc_signal<size_t>       r_dcache_dirty_way;         // way to invalidate in dcache
421    sc_signal<size_t>       r_dcache_dirty_set;         // set to invalidate in dcache
422
423    // communication between DCACHE FSM and VCI_CMD FSM
424    sc_signal<paddr_t>      r_dcache_vci_paddr;             // physical address for VCI command
425    sc_signal<bool>         r_dcache_vci_miss_req;      // read miss request
426    sc_signal<bool>         r_dcache_vci_unc_req;       // uncacheable read request
427    sc_signal<uint32_t>     r_dcache_vci_unc_be;        // uncacheable read byte enable
428    sc_signal<bool>         r_dcache_vci_cas_req;       // atomic write request CAS
429    sc_signal<uint32_t>     r_dcache_vci_cas_old;       // previous data value for a CAS
430    sc_signal<uint32_t>     r_dcache_vci_cas_new;       // new data value for a CAS
431    sc_signal<bool>         r_dcache_vci_ll_req;        // atomic read request LL
432    sc_signal<bool>         r_dcache_vci_sc_req;        // atomic write request SC
433    sc_signal<uint32_t>     r_dcache_vci_sc_data;       // SC data (command)
434
435    // register used for XTN inval
436    sc_signal<size_t>       r_dcache_xtn_way;               // selected way (from dcache)
437    sc_signal<size_t>       r_dcache_xtn_set;               // selected set (from dcache)
438
439    // write buffer state extension
440    sc_signal<bool>         r_dcache_pending_unc_write; // pending uncacheable write in WBUF
441
442    // handling dcache miss
443    sc_signal<int>              r_dcache_miss_type;                 // depending on the requester
444    sc_signal<size_t>       r_dcache_miss_word;             // word index for cache update
445    sc_signal<size_t>       r_dcache_miss_way;              // selected way for cache update
446    sc_signal<size_t>       r_dcache_miss_set;              // selected set for cache update
447    sc_signal<bool>         r_dcache_miss_inval;        // coherence request matching a miss
448    sc_signal<bool>         r_dcache_miss_clack;        // waiting for a cleanup acknowledge
449
450    // handling coherence requests
451    sc_signal<size_t>       r_dcache_cc_way;                // selected way for cc update/inval
452    sc_signal<size_t>       r_dcache_cc_set;                // selected set for cc update/inval
453    sc_signal<size_t>       r_dcache_cc_word;               // word counter for cc update
454    sc_signal<bool>         r_dcache_cc_need_write;     // activate the cache for writing
455
456    // coherence clack handling
457    sc_signal<bool>         r_dcache_clack_req;         // clack request
458    sc_signal<size_t>       r_dcache_clack_way;             // clack way
459    sc_signal<size_t>       r_dcache_clack_set;             // clack set
460
461    // dcache flush handling
462    sc_signal<size_t>       r_dcache_flush_count;           // slot counter used for cache flush
463
464    // ll response handling
465    sc_signal<size_t>       r_dcache_ll_rsp_count;          // flit counter used for ll rsp
466
467    // used by the TLB miss sub-fsm
468    sc_signal<uint32_t>     r_dcache_tlb_vaddr;             // virtual address for a tlb miss
469    sc_signal<bool>         r_dcache_tlb_ins;               // target tlb (itlb if true)
470    sc_signal<paddr_t>      r_dcache_tlb_paddr;             // physical address of pte
471    sc_signal<uint32_t>     r_dcache_tlb_pte_flags;         // pte1 or first word of pte2
472    sc_signal<uint32_t>     r_dcache_tlb_pte_ppn;           // second word of pte2
473    sc_signal<size_t>       r_dcache_tlb_cache_way;         // selected way in dcache
474    sc_signal<size_t>       r_dcache_tlb_cache_set;         // selected set in dcache
475    sc_signal<size_t>       r_dcache_tlb_cache_word;    // selected word in dcache
476    sc_signal<size_t>       r_dcache_tlb_way;               // selected way in tlb
477    sc_signal<size_t>       r_dcache_tlb_set;               // selected set in tlb
478
479    // ITLB and DTLB invalidation
480    sc_signal<paddr_t>      r_dcache_tlb_inval_line;    // line index
481    sc_signal<size_t>       r_dcache_tlb_inval_set;     // tlb set counter
482
483    // communication between DCACHE FSM and ICACHE FSM
484    sc_signal<bool>         r_dcache_xtn_req;           // xtn request (caused by processor)
485    sc_signal<int>          r_dcache_xtn_opcode;        // xtn request type
486
487    // Filp-Flop in DCACHE FSM for saving the cleanup victim request
488    sc_signal<bool>         r_dcache_cleanup_victim_req; 
489    sc_signal<paddr_t>      r_dcache_cleanup_victim_nline;
490
491    // communication between DCACHE FSM and CC_SEND FSM
492    sc_signal<bool>         r_dcache_cc_send_req;           // DCACHE cc_send request
493    sc_signal<cc_send_t>    r_dcache_cc_send_type;          // DCACHE cc_send request type
494    sc_signal<paddr_t>      r_dcache_cc_send_nline;         // DCACHE cc_send nline
495    sc_signal<size_t>       r_dcache_cc_send_way;           // DCACHE cc_send way
496    sc_signal<size_t>       r_dcache_cc_send_updt_tab_idx;  // DCACHE cc_send update table index
497
498    // dcache directory extension
499    bool                    *r_dcache_in_tlb;               // copy exist in dtlb or itlb
500    bool                    *r_dcache_contains_ptd;         // cache line contains a PTD
501
502    // Physical address extension for data access
503    sc_signal<uint32_t>     r_dcache_paddr_ext;             // CP2 register (if vci_address > 32)
504
505    ///////////////////////////////////
506    // VCI_CMD FSM REGISTERS
507    ///////////////////////////////////
508    sc_signal<int>          r_vci_cmd_fsm;
509    sc_signal<size_t>       r_vci_cmd_min;                      // used for write bursts
510    sc_signal<size_t>       r_vci_cmd_max;                      // used for write bursts
511    sc_signal<size_t>       r_vci_cmd_cpt;                      // used for write bursts
512    sc_signal<bool>         r_vci_cmd_imiss_prio;               // round-robin between imiss & dmiss
513
514    ///////////////////////////////////
515    // VCI_RSP FSM REGISTERS
516    ///////////////////////////////////
517    sc_signal<int>          r_vci_rsp_fsm;
518    sc_signal<size_t>       r_vci_rsp_cpt;
519    sc_signal<bool>         r_vci_rsp_ins_error;
520    sc_signal<bool>         r_vci_rsp_data_error;
521    GenericFifo<uint32_t>   r_vci_rsp_fifo_icache;              // response FIFO to ICACHE FSM
522    GenericFifo<uint32_t>   r_vci_rsp_fifo_dcache;              // response FIFO to DCACHE FSM
523
524    ///////////////////////////////////
525    //  CC_SEND FSM REGISTER
526    ///////////////////////////////////
527    sc_signal<int>          r_cc_send_fsm;                  // state register
528    sc_signal<bool>         r_cc_send_last_client;          // 0 dcache / 1 icache
529
530    ///////////////////////////////////
531    //  CC_RECEIVE FSM REGISTER
532    ///////////////////////////////////
533    sc_signal<int>          r_cc_receive_fsm;               // state register
534    sc_signal<bool>         r_cc_receive_data_ins;          // request to : 0 dcache / 1 icache
535
536    // communication between CC_RECEIVE FSM and ICACHE/DCACHE FSM
537    sc_signal<size_t>       r_cc_receive_word_idx;          // word index
538    GenericFifo<uint32_t>   r_cc_receive_updt_fifo_be;
539    GenericFifo<uint32_t>   r_cc_receive_updt_fifo_data;
540    GenericFifo<bool>       r_cc_receive_updt_fifo_eop;
541
542    // communication between CC_RECEIVE FSM and ICACHE FSM
543    sc_signal<bool>         r_cc_receive_icache_req;        // cc_receive to icache request
544    sc_signal<cc_receive_t> r_cc_receive_icache_type;       // cc_receive type of request
545    sc_signal<size_t>       r_cc_receive_icache_way;        // cc_receive to icache way
546    sc_signal<size_t>       r_cc_receive_icache_set;        // cc_receive to icache set
547    sc_signal<size_t>       r_cc_receive_icache_updt_tab_idx;  // cc_receive update table index
548    sc_signal<paddr_t>      r_cc_receive_icache_nline;      // cache line physical address
549
550    // communication between CC_RECEIVE FSM and DCACHE FSM
551    sc_signal<bool>         r_cc_receive_dcache_req;        // cc_receive to dcache request
552    sc_signal<cc_receive_t> r_cc_receive_dcache_type;       // cc_receive type of request
553    sc_signal<size_t>       r_cc_receive_dcache_way;        // cc_receive to dcache way
554    sc_signal<size_t>       r_cc_receive_dcache_set;        // cc_receive to dcache set
555    sc_signal<size_t>       r_cc_receive_dcache_updt_tab_idx;  // cc_receive update table index
556    sc_signal<paddr_t>      r_cc_receive_dcache_nline;      // cache line physical address
557
558    ///////////////////////////////////
559    //  DSPIN CLACK INTERFACE REGISTER
560    ///////////////////////////////////
561    sc_signal<bool>         r_dspin_clack_req;
562    sc_signal<uint64_t>     r_dspin_clack_flit;
563   
564    //////////////////////////////////////////////////////////////////
565    // processor, write buffer, caches , TLBs
566    //////////////////////////////////////////////////////////////////
567
568    iss_t                       r_iss;
569    MultiWriteBuffer<paddr_t>   r_wbuf;
570    GenericCache<paddr_t>       r_icache;
571    GenericCache<paddr_t>       r_dcache;
572    GenericTlb<paddr_t>         r_itlb;
573    GenericTlb<paddr_t>         r_dtlb;
574
575    //////////////////////////////////////////////////////////////////
576    // llsc registration buffer
577    //////////////////////////////////////////////////////////////////
578
579    sc_signal<paddr_t>                     r_dcache_llsc_paddr;
580    sc_signal<uint32_t>                    r_dcache_llsc_key;
581    sc_signal<uint32_t>                    r_dcache_llsc_count;
582    sc_signal<bool>                        r_dcache_llsc_valid;
583
584    ////////////////////////////////
585    // Activity counters
586    ////////////////////////////////
587    uint32_t m_cpt_dcache_data_read;        // DCACHE DATA READ
588    uint32_t m_cpt_dcache_data_write;       // DCACHE DATA WRITE
589    uint32_t m_cpt_dcache_dir_read;         // DCACHE DIR READ
590    uint32_t m_cpt_dcache_dir_write;        // DCACHE DIR WRITE
591
592    uint32_t m_cpt_icache_data_read;        // ICACHE DATA READ
593    uint32_t m_cpt_icache_data_write;       // ICACHE DATA WRITE
594    uint32_t m_cpt_icache_dir_read;         // ICACHE DIR READ
595    uint32_t m_cpt_icache_dir_write;        // ICACHE DIR WRITE
596
597    uint32_t m_cpt_frz_cycles;              // number of cycles where the cpu is frozen
598    uint32_t m_cpt_total_cycles;                // total number of cycles
599
600    // Cache activity counters
601    uint32_t m_cpt_data_read;               // total number of read data
602    uint32_t m_cpt_data_write;              // total number of write data
603    uint32_t m_cpt_data_miss;               // number of read miss
604    uint32_t m_cpt_ins_miss;                // number of instruction miss
605    uint32_t m_cpt_unc_read;                // number of read uncached
606    uint32_t m_cpt_write_cached;            // number of cached write
607    uint32_t m_cpt_ins_read;                // number of instruction read
608    uint32_t m_cpt_ins_spc_miss;            // number of speculative instruction miss
609
610    uint32_t m_cost_write_frz;              // number of frozen cycles related to write buffer
611    uint32_t m_cost_data_miss_frz;          // number of frozen cycles related to data miss
612    uint32_t m_cost_unc_read_frz;           // number of frozen cycles related to uncached read
613    uint32_t m_cost_ins_miss_frz;           // number of frozen cycles related to ins miss
614
615    uint32_t m_cpt_imiss_transaction;       // number of VCI instruction miss transactions
616    uint32_t m_cpt_dmiss_transaction;       // number of VCI data miss transactions
617    uint32_t m_cpt_unc_transaction;         // number of VCI uncached read transactions
618    uint32_t m_cpt_write_transaction;       // number of VCI write transactions
619    uint32_t m_cpt_icache_unc_transaction;
620
621    uint32_t m_cost_imiss_transaction;      // cumulated duration for VCI IMISS transactions
622    uint32_t m_cost_dmiss_transaction;      // cumulated duration for VCI DMISS transactions
623    uint32_t m_cost_unc_transaction;        // cumulated duration for VCI UNC transactions
624    uint32_t m_cost_write_transaction;      // cumulated duration for VCI WRITE transactions
625    uint32_t m_cost_icache_unc_transaction; // cumulated duration for VCI IUNC transactions
626    uint32_t m_length_write_transaction;    // cumulated length for VCI WRITE transactions
627
628    // TLB activity counters
629    uint32_t m_cpt_ins_tlb_read;            // number of instruction tlb read
630    uint32_t m_cpt_ins_tlb_miss;            // number of instruction tlb miss
631    uint32_t m_cpt_ins_tlb_update_acc;      // number of instruction tlb update
632    uint32_t m_cpt_ins_tlb_occup_cache;     // number of instruction tlb occupy data cache line
633    uint32_t m_cpt_ins_tlb_hit_dcache;      // number of instruction tlb hit in data cache
634
635    uint32_t m_cpt_data_tlb_read;           // number of data tlb read
636    uint32_t m_cpt_data_tlb_miss;           // number of data tlb miss
637    uint32_t m_cpt_data_tlb_update_acc;     // number of data tlb update
638    uint32_t m_cpt_data_tlb_update_dirty;   // number of data tlb update dirty
639    uint32_t m_cpt_data_tlb_hit_dcache;     // number of data tlb hit in data cache
640    uint32_t m_cpt_data_tlb_occup_cache;    // number of data tlb occupy data cache line
641    uint32_t m_cpt_tlb_occup_dcache;
642
643    uint32_t m_cost_ins_tlb_miss_frz;       // number of frozen cycles related to instruction tlb miss
644    uint32_t m_cost_data_tlb_miss_frz;      // number of frozen cycles related to data tlb miss
645    uint32_t m_cost_ins_tlb_update_acc_frz;    // number of frozen cycles related to instruction tlb update acc
646    uint32_t m_cost_data_tlb_update_acc_frz;   // number of frozen cycles related to data tlb update acc
647    uint32_t m_cost_data_tlb_update_dirty_frz; // number of frozen cycles related to data tlb update dirty
648    uint32_t m_cost_ins_tlb_occup_cache_frz;   // number of frozen cycles related to instruction tlb miss operate in dcache
649    uint32_t m_cost_data_tlb_occup_cache_frz;  // number of frozen cycles related to data tlb miss operate in dcache
650
651    uint32_t m_cpt_itlbmiss_transaction;       // number of itlb miss transactions
652    uint32_t m_cpt_itlb_ll_transaction;        // number of itlb ll acc transactions
653    uint32_t m_cpt_itlb_sc_transaction;        // number of itlb sc acc transactions
654    uint32_t m_cpt_dtlbmiss_transaction;       // number of dtlb miss transactions
655    uint32_t m_cpt_dtlb_ll_transaction;        // number of dtlb ll acc transactions
656    uint32_t m_cpt_dtlb_sc_transaction;        // number of dtlb sc acc transactions
657    uint32_t m_cpt_dtlb_ll_dirty_transaction;  // number of dtlb ll dirty transactions
658    uint32_t m_cpt_dtlb_sc_dirty_transaction;  // number of dtlb sc dirty transactions
659
660    uint32_t m_cost_itlbmiss_transaction;       // cumulated duration for VCI instruction TLB miss transactions
661    uint32_t m_cost_itlb_ll_transaction;        // cumulated duration for VCI instruction TLB ll acc transactions
662    uint32_t m_cost_itlb_sc_transaction;        // cumulated duration for VCI instruction TLB sc acc transactions
663    uint32_t m_cost_dtlbmiss_transaction;       // cumulated duration for VCI data TLB miss transactions
664    uint32_t m_cost_dtlb_ll_transaction;        // cumulated duration for VCI data TLB ll acc transactions
665    uint32_t m_cost_dtlb_sc_transaction;        // cumulated duration for VCI data TLB sc acc transactions
666    uint32_t m_cost_dtlb_ll_dirty_transaction;  // cumulated duration for VCI data TLB ll dirty transactions
667    uint32_t m_cost_dtlb_sc_dirty_transaction;  // cumulated duration for VCI data TLB sc dirty transactions
668
669    // coherence activity counters
670    uint32_t m_cpt_cc_update_icache;            // number of coherence update instruction commands
671    uint32_t m_cpt_cc_update_dcache;            // number of coherence update data commands
672    uint32_t m_cpt_cc_inval_icache;             // number of coherence inval instruction commands
673    uint32_t m_cpt_cc_inval_dcache;             // number of coherence inval data commands
674    uint32_t m_cpt_cc_broadcast;                // number of coherence broadcast commands
675
676    uint32_t m_cost_updt_data_frz;              // number of frozen cycles related to coherence update data packets
677    uint32_t m_cost_inval_ins_frz;              // number of frozen cycles related to coherence inval instruction packets
678    uint32_t m_cost_inval_data_frz;             // number of frozen cycles related to coherence inval data packets
679    uint32_t m_cost_broadcast_frz;              // number of frozen cycles related to coherence broadcast packets
680
681    uint32_t m_cpt_cc_cleanup_ins;              // number of coherence cleanup packets
682    uint32_t m_cpt_cc_cleanup_data;             // number of coherence cleanup packets
683
684    uint32_t m_cpt_icleanup_transaction;        // number of instruction cleanup transactions
685    uint32_t m_cpt_dcleanup_transaction;        // number of instructinumber of data cleanup transactions
686    uint32_t m_cost_icleanup_transaction;       // cumulated duration for VCI instruction cleanup transactions
687    uint32_t m_cost_dcleanup_transaction;       // cumulated duration for VCI data cleanup transactions
688
689    uint32_t m_cost_ins_tlb_inval_frz;      // number of frozen cycles related to checking ins tlb invalidate
690    uint32_t m_cpt_ins_tlb_inval;           // number of ins tlb invalidate
691
692    uint32_t m_cost_data_tlb_inval_frz;     // number of frozen cycles related to checking data tlb invalidate
693    uint32_t m_cpt_data_tlb_inval;          // number of data tlb invalidate
694
695    // FSM activity counters
696    uint32_t m_cpt_fsm_icache     [64];
697    uint32_t m_cpt_fsm_dcache     [64];
698    uint32_t m_cpt_fsm_cmd        [64];
699    uint32_t m_cpt_fsm_rsp        [64];
700    uint32_t m_cpt_fsm_cc_receive [64];
701    uint32_t m_cpt_fsm_cc_send    [64];
702
703    uint32_t m_cpt_stop_simulation;             // used to stop simulation if frozen
704    bool     m_monitor_ok;                      // used to debug cache output 
705    uint32_t m_monitor_base;               
706    uint32_t m_monitor_length;             
707
708protected:
709    SC_HAS_PROCESS(VciCcVCacheWrapper);
710
711public:
712    VciCcVCacheWrapper(
713        sc_module_name                      name,
714        const int                           proc_id,
715        const soclib::common::MappingTable  &mtd,
716        const soclib::common::IntTab        &srcid,
717        const size_t                        cc_global_id,
718        const size_t                        itlb_ways,
719        const size_t                        itlb_sets,
720        const size_t                        dtlb_ways,
721        const size_t                        dtlb_sets,
722        const size_t                        icache_ways,
723        const size_t                        icache_sets,
724        const size_t                        icache_words,
725        const size_t                        dcache_ways,
726        const size_t                        dcache_sets,
727        const size_t                        dcache_words,
728        const size_t                        wbuf_nlines,
729        const size_t                        wbuf_nwords,
730        const size_t                        x_width,
731        const size_t                        y_width,
732        const uint32_t                      max_frozen_cycles,
733        const uint32_t                      debug_start_cycle,
734        const bool                          debug_ok );
735
736    ~VciCcVCacheWrapper();
737
738    void print_cpi();
739    void print_stats();
740    void clear_stats();
741    void print_trace(size_t mode = 0);
742    void cache_monitor(paddr_t addr);
743    void start_monitor(paddr_t,paddr_t);
744    void stop_monitor();
745    inline void iss_set_debug_mask(uint v) 
746    {
747            r_iss.set_debug_mask(v);
748    }
749
750private:
751    void transition();
752    void genMoore();
753
754    soclib_static_assert((int)iss_t::SC_ATOMIC == (int)vci_param::STORE_COND_ATOMIC);
755    soclib_static_assert((int)iss_t::SC_NOT_ATOMIC == (int)vci_param::STORE_COND_NOT_ATOMIC);
756};
757
758}}
759
760#endif /* SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER_H */
761
762// Local Variables:
763// tab-width: 4
764// c-basic-offset: 4
765// c-file-offsets:((innamespace . 0)(inline-open . 0))
766// indent-tabs-mode: nil
767// End:
768
769// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
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