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source: trunk/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp @ 386

Last change on this file since 386 was 386, checked in by alain, 11 years ago
New release supporting the tsar_generic_xbar platform with 64 bits interface between MEMC & XCACHE, and preparing support for the tsar_generic_iob platform.
File size: 231.0 KB

Line
1	/* -- c++ --
2	* File : vci_cc_vcache_wrapper.cpp
3	* Copyright (c) UPMC, Lip6, SoC
4	* Authors : Alain GREINER, Yang GAO
5	*
6	* SOCLIB_LGPL_HEADER_BEGIN
7	*
8	* This file is part of SoCLib, GNU LGPLv2.1.
9	*
10	* SoCLib is free software; you can redistribute it and/or modify it
11	* under the terms of the GNU Lesser General Public License as published
12	* by the Free Software Foundation; version 2.1 of the License.
13	*
14	* SoCLib is distributed in the hope that it will be useful, but
15	* WITHOUT ANY WARRANTY; without even the implied warranty of
16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17	* Lesser General Public License for more details.
18	*
19	* You should have received a copy of the GNU Lesser General Public
20	* License along with SoCLib; if not, write to the Free Software
21	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
22	* 02110-1301 USA
23	*
24	* SOCLIB_LGPL_HEADER_END
25	*
26	* Maintainers: cesar.fuguet-tortolero@lip6.fr
27	* alexandre.joannou@lip6.fr
28	*/
29
30	#include <cassert>
31	#include "arithmetics.h"
32	#include "../include/vci_cc_vcache_wrapper.h"
33
34	#define DEBUG_DCACHE 1
35	#define DEBUG_ICACHE 1
36	#define DEBUG_CLEANUP 1
37
38	namespace soclib {
39	namespace caba {
40
41	namespace {
42	const char *icache_fsm_state_str[] = {
43	"ICACHE_IDLE",
44
45	"ICACHE_XTN_TLB_FLUSH",
46	"ICACHE_XTN_CACHE_FLUSH",
47	"ICACHE_XTN_CACHE_FLUSH_GO",
48	"ICACHE_XTN_TLB_INVAL",
49	"ICACHE_XTN_CACHE_INVAL_VA",
50	"ICACHE_XTN_CACHE_INVAL_PA",
51	"ICACHE_XTN_CACHE_INVAL_GO",
52
53	"ICACHE_TLB_WAIT",
54
55	"ICACHE_MISS_SELECT",
56	"ICACHE_MISS_CLEAN",
57	"ICACHE_MISS_WAIT",
58	"ICACHE_MISS_DATA_UPDT",
59	"ICACHE_MISS_DIR_UPDT",
60
61	"ICACHE_UNC_WAIT",
62
63	"ICACHE_CC_CHECK",
64	"ICACHE_CC_INVAL",
65	"ICACHE_CC_UPDT",
66	"ICACHE_CC_BROADCAST",
67	"ICACHE_CC_SEND_WAIT",
68	};
69
70	const char *dcache_fsm_state_str[] = {
71	"DCACHE_IDLE",
72
73	"DCACHE_TLB_MISS",
74	"DCACHE_TLB_PTE1_GET",
75	"DCACHE_TLB_PTE1_SELECT",
76	"DCACHE_TLB_PTE1_UPDT",
77	"DCACHE_TLB_PTE2_GET",
78	"DCACHE_TLB_PTE2_SELECT",
79	"DCACHE_TLB_PTE2_UPDT",
80	"DCACHE_TLB_LR_UPDT",
81	"DCACHE_TLB_LR_WAIT",
82	"DCACHE_TLB_RETURN",
83
84	"DCACHE_XTN_SWITCH",
85	"DCACHE_XTN_SYNC",
86	"DCACHE_XTN_IC_INVAL_VA",
87	"DCACHE_XTN_IC_FLUSH",
88	"DCACHE_XTN_IC_INVAL_PA",
89	"DCACHE_XTN_IT_INVAL",
90	"DCACHE_XTN_DC_FLUSH",
91	"DCACHE_XTN_DC_FLUSH_GO",
92	"DCACHE_XTN_DC_INVAL_VA",
93	"DCACHE_XTN_DC_INVAL_PA",
94	"DCACHE_XTN_DC_INVAL_END",
95	"DCACHE_XTN_DC_INVAL_GO",
96	"DCACHE_XTN_DT_INVAL",
97
98	"DCACHE_DIRTY_GET_PTE",
99	"DCACHE_DIRTY_WAIT",
100
101	"DCACHE_MISS_SELECT",
102	"DCACHE_MISS_CLEAN",
103	"DCACHE_MISS_WAIT",
104	"DCACHE_MISS_DATA_UPDT",
105	"DCACHE_MISS_DIR_UPDT",
106
107	"DCACHE_UNC_WAIT",
108	"DCACHE_LL_WAIT",
109	"DCACHE_SC_WAIT",
110
111	"DCACHE_CC_CHECK",
112	"DCACHE_CC_INVAL",
113	"DCACHE_CC_UPDT",
114	"DCACHE_CC_BROADCAST",
115	"DCACHE_CC_SEND_WAIT",
116
117	"DCACHE_INVAL_TLB_SCAN",
118	};
119
120	const char *cmd_fsm_state_str[] = {
121	"CMD_IDLE",
122	"CMD_INS_MISS",
123	"CMD_INS_UNC",
124	"CMD_DATA_MISS",
125	"CMD_DATA_UNC",
126	"CMD_DATA_WRITE",
127	"CMD_DATA_LL",
128	"CMD_DATA_SC",
129	"CMD_DATA_CAS",
130	};
131
132	const char *rsp_fsm_state_str[] = {
133	"RSP_IDLE",
134	"RSP_INS_MISS",
135	"RSP_INS_UNC",
136	"RSP_DATA_MISS",
137	"RSP_DATA_UNC",
138	"RSP_DATA_LL",
139	"RSP_DATA_WRITE",
140	};
141
142	const char *cc_receive_fsm_state_str[] = {
143	"CC_RECEIVE_IDLE",
144	"CC_RECEIVE_CLACK",
145	"CC_RECEIVE_BRDCAST_HEADER",
146	"CC_RECEIVE_BRDCAST_NLINE",
147	"CC_RECEIVE_INVAL_HEADER",
148	"CC_RECEIVE_INVAL_NLINE",
149	"CC_RECEIVE_UPDT_HEADER",
150	"CC_RECEIVE_UPDT_NLINE",
151	"CC_RECEIVE_UPDT_DATA",
152	};
153
154	const char *cc_send_fsm_state_str[] = {
155	"CC_SEND_IDLE",
156	"CC_SEND_CLEANUP_1",
157	"CC_SEND_CLEANUP_2",
158	"CC_SEND_MULTI_ACK",
159	};
160	}
161
162	#define tmpl(...) \
163	template<typename vci_param, \
164	size_t dspin_in_width, \
165	size_t dspin_out_width, \
166	typename iss_t> __VA_ARGS__ \
167	VciCcVCacheWrapper<vci_param, dspin_in_width, dspin_out_width, iss_t>
168
169	using namespace soclib::common;
170
171	/////////////////////////////////
172	tmpl(/**/)::VciCcVCacheWrapper(
173	sc_module_name name,
174	const int proc_id,
175	const MappingTable &mtd,
176	const IntTab &srcid,
177	const size_t cc_global_id,
178	const size_t itlb_ways,
179	const size_t itlb_sets,
180	const size_t dtlb_ways,
181	const size_t dtlb_sets,
182	const size_t icache_ways,
183	const size_t icache_sets,
184	const size_t icache_words,
185	const size_t dcache_ways,
186	const size_t dcache_sets,
187	const size_t dcache_words,
188	const size_t wbuf_nlines,
189	const size_t wbuf_nwords,
190	const size_t x_width,
191	const size_t y_width,
192	const uint32_t max_frozen_cycles,
193	const uint32_t debug_start_cycle,
194	const bool debug_ok )
195	: soclib::caba::BaseModule(name),
196
197	p_clk("p_clk"),
198	p_resetn("p_resetn"),
199	p_vci("p_vci"),
200	p_dspin_in("p_dspin_in"),
201	p_dspin_out("p_dspin_out"),
202
203	m_cacheability_table( mtd.getCacheabilityTable() ),
204	m_srcid( mtd.indexForId(srcid) ),
205	m_cc_global_id( cc_global_id ),
206	m_nline_width( vci_param::N - (uint32_log2(dcache_words)) - 2 ),
207	m_itlb_ways( itlb_ways ),
208	m_itlb_sets( itlb_sets ),
209	m_dtlb_ways( dtlb_ways ),
210	m_dtlb_sets( dtlb_sets ),
211	m_icache_ways( icache_ways ),
212	m_icache_sets( icache_sets ),
213	m_icache_yzmask( (~0)<<(uint32_log2(icache_words) + 2) ),
214	m_icache_words( icache_words ),
215	m_dcache_ways( dcache_ways ),
216	m_dcache_sets( dcache_sets ),
217	m_dcache_yzmask( (~0)<<(uint32_log2(dcache_words) + 2) ),
218	m_dcache_words( dcache_words ),
219	m_x_width( x_width ),
220	m_y_width( y_width ),
221	m_proc_id( proc_id ),
222	m_max_frozen_cycles( max_frozen_cycles ),
223	m_paddr_nbits( vci_param::N ),
224	m_debug_start_cycle( debug_start_cycle ),
225	m_debug_ok( debug_ok ),
226
227	r_mmu_ptpr("r_mmu_ptpr"),
228	r_mmu_mode("r_mmu_mode"),
229	r_mmu_word_lo("r_mmu_word_lo"),
230	r_mmu_word_hi("r_mmu_word_hi"),
231	r_mmu_ibvar("r_mmu_ibvar"),
232	r_mmu_dbvar("r_mmu_dbvar"),
233	r_mmu_ietr("r_mmu_ietr"),
234	r_mmu_detr("r_mmu_detr"),
235
236	r_icache_fsm("r_icache_fsm"),
237	r_icache_fsm_save("r_icache_fsm_save"),
238	r_icache_vci_paddr("r_icache_vci_paddr"),
239	r_icache_vaddr_save("r_icache_vaddr_save"),
240
241	r_icache_miss_way("r_icache_miss_way"),
242	r_icache_miss_set("r_icache_miss_set"),
243	r_icache_miss_word("r_icache_miss_word"),
244	r_icache_miss_inval("r_icache_miss_inval"),
245	r_icache_miss_clack("r_icache_miss_clack"),
246
247	r_icache_cc_way("r_icache_cc_way"),
248	r_icache_cc_set("r_icache_cc_set"),
249	r_icache_cc_word("r_icache_cc_word"),
250	r_icache_cc_need_write("r_icache_cc_need_write"),
251
252	r_icache_flush_count("r_icache_flush_count"),
253
254	r_icache_miss_req("r_icache_miss_req"),
255	r_icache_unc_req("r_icache_unc_req"),
256
257	r_icache_tlb_miss_req("r_icache_tlb_read_req"),
258	r_icache_tlb_rsp_error("r_icache_tlb_rsp_error"),
259
260	r_icache_cc_send_req("r_icache_cc_send_req"),
261	r_icache_cc_send_type("r_icache_cc_send_type"),
262	r_icache_cc_send_nline("r_icache_cc_send_nline"),
263	r_icache_cc_send_way("r_icache_cc_send_way"),
264	r_icache_cc_send_updt_tab_idx("r_icache_cc_send_updt_tab_idx"),
265
266	r_dcache_fsm("r_dcache_fsm"),
267	r_dcache_fsm_cc_save("r_dcache_fsm_cc_save"),
268	r_dcache_fsm_scan_save("r_dcache_fsm_scan_save"),
269
270	r_dcache_wbuf_req("r_dcache_wbuf_req"),
271	r_dcache_updt_req("r_dcache_updt_req"),
272	r_dcache_save_vaddr("r_dcache_save_vaddr"),
273	r_dcache_save_wdata("r_dcache_save_wdata"),
274	r_dcache_save_be("r_dcache_save_be"),
275	r_dcache_save_paddr("r_dcache_save_paddr"),
276	r_dcache_save_cacheable("r_dcache_save_cacheable"),
277	r_dcache_save_cache_way("r_dcache_save_cache_way"),
278	r_dcache_save_cache_set("r_dcache_save_cache_set"),
279	r_dcache_save_cache_word("r_dcache_save_cache_word"),
280
281	r_dcache_dirty_paddr("r_dcache_dirty_paddr"),
282	r_dcache_dirty_way("r_dcache_dirty_way"),
283	r_dcache_dirty_set("r_dcache_dirty_set"),
284
285	r_dcache_vci_paddr("r_dcache_vci_paddr"),
286	r_dcache_vci_miss_req("r_dcache_vci_miss_req"),
287	r_dcache_vci_unc_req("r_dcache_vci_unc_req"),
288	r_dcache_vci_unc_be("r_dcache_vci_unc_be"),
289	r_dcache_vci_cas_req("r_dcache_vci_cas_req"),
290	r_dcache_vci_cas_old("r_dcache_vci_cas_old"),
291	r_dcache_vci_cas_new("r_dcache_vci_cas_new"),
292	r_dcache_vci_ll_req("r_dcache_vci_ll_req"),
293	r_dcache_vci_sc_req("r_dcache_vci_sc_req"),
294	r_dcache_vci_sc_data("r_dcache_vci_sc_data"),
295
296	r_dcache_xtn_way("r_dcache_xtn_way"),
297	r_dcache_xtn_set("r_dcache_xtn_set"),
298
299	r_dcache_pending_unc_write("r_dcache_pending_unc_write"),
300
301	r_dcache_miss_type("r_dcache_miss_type"),
302	r_dcache_miss_word("r_dcache_miss_word"),
303	r_dcache_miss_way("r_dcache_miss_way"),
304	r_dcache_miss_set("r_dcache_miss_set"),
305	r_dcache_miss_inval("r_dcache_miss_inval"),
306
307	r_dcache_cc_way("r_dcache_cc_way"),
308	r_dcache_cc_set("r_dcache_cc_set"),
309	r_dcache_cc_word("r_dcache_cc_word"),
310	r_dcache_cc_need_write("r_dcache_cc_need_write"),
311
312	r_dcache_flush_count("r_dcache_flush_count"),
313
314	r_dcache_ll_rsp_count("r_dcache_ll_rsp_count"),
315
316	r_dcache_tlb_vaddr("r_dcache_tlb_vaddr"),
317	r_dcache_tlb_ins("r_dcache_tlb_ins"),
318	r_dcache_tlb_pte_flags("r_dcache_tlb_pte_flags"),
319	r_dcache_tlb_pte_ppn("r_dcache_tlb_pte_ppn"),
320	r_dcache_tlb_cache_way("r_dcache_tlb_cache_way"),
321	r_dcache_tlb_cache_set("r_dcache_tlb_cache_set"),
322	r_dcache_tlb_cache_word("r_dcache_tlb_cache_word"),
323	r_dcache_tlb_way("r_dcache_tlb_way"),
324	r_dcache_tlb_set("r_dcache_tlb_set"),
325
326	r_dcache_tlb_inval_line("r_dcache_tlb_inval_line"),
327	r_dcache_tlb_inval_set("r_dcache_tlb_inval_set"),
328
329	r_dcache_xtn_req("r_dcache_xtn_req"),
330	r_dcache_xtn_opcode("r_dcache_xtn_opcode"),
331
332	r_dcache_cc_send_req("r_dcache_cc_send_req"),
333	r_dcache_cc_send_type("r_dcache_cc_send_type"),
334	r_dcache_cc_send_nline("r_dcache_cc_send_nline"),
335	r_dcache_cc_send_way("r_dcache_cc_send_way"),
336	r_dcache_cc_send_updt_tab_idx("r_dcache_cc_send_updt_tab_idx"),
337
338	r_vci_cmd_fsm("r_vci_cmd_fsm"),
339	r_vci_cmd_min("r_vci_cmd_min"),
340	r_vci_cmd_max("r_vci_cmd_max"),
341	r_vci_cmd_cpt("r_vci_cmd_cpt"),
342	r_vci_cmd_imiss_prio("r_vci_cmd_imiss_prio"),
343
344	r_vci_rsp_fsm("r_vci_rsp_fsm"),
345	r_vci_rsp_cpt("r_vci_rsp_cpt"),
346	r_vci_rsp_ins_error("r_vci_rsp_ins_error"),
347	r_vci_rsp_data_error("r_vci_rsp_data_error"),
348	r_vci_rsp_fifo_icache("r_vci_rsp_fifo_icache", 2), // 2 words depth
349	r_vci_rsp_fifo_dcache("r_vci_rsp_fifo_dcache", 2), // 2 words depth
350
351	r_cc_send_fsm("r_cc_send_fsm"),
352	r_cc_send_last_client("r_cc_send_last_client"),
353
354	r_cc_receive_fsm("r_cc_receive_fsm"),
355	r_cc_receive_data_ins("r_cc_receive_data_ins"),
356	r_cc_receive_word_idx("r_cc_receive_word_idx"),
357	r_cc_receive_updt_fifo_be("r_cc_receive_updt_fifo_be", 2), // 2 words depth
358	r_cc_receive_updt_fifo_data("r_cc_receive_updt_fifo_data", 2), // 2 words depth
359	r_cc_receive_updt_fifo_eop("r_cc_receive_updt_fifo_eop", 2), // 2 words depth
360
361	r_cc_receive_icache_req("r_cc_receive_icache_req"),
362	r_cc_receive_icache_type("r_cc_receive_icache_type"),
363	r_cc_receive_icache_way("r_cc_receive_icache_way"),
364	r_cc_receive_icache_set("r_cc_receive_icache_set"),
365	r_cc_receive_icache_updt_tab_idx("r_cc_receive_icache_updt_tab_idx"),
366	r_cc_receive_icache_nline("r_cc_receive_icache_nline"),
367
368	r_cc_receive_dcache_req("r_cc_receive_dcache_req"),
369	r_cc_receive_dcache_type("r_cc_receive_dcache_type"),
370	r_cc_receive_dcache_way("r_cc_receive_dcache_way"),
371	r_cc_receive_dcache_set("r_cc_receive_dcache_set"),
372	r_cc_receive_dcache_updt_tab_idx("r_cc_receive_dcache_updt_tab_idx"),
373	r_cc_receive_dcache_nline("r_cc_receive_dcache_nline"),
374
375	r_iss(this->name(), proc_id),
376	r_wbuf("wbuf", wbuf_nwords, wbuf_nlines, dcache_words ),
377	r_icache("icache", icache_ways, icache_sets, icache_words),
378	r_dcache("dcache", dcache_ways, dcache_sets, dcache_words),
379	r_itlb("itlb", proc_id, itlb_ways,itlb_sets,vci_param::N),
380	r_dtlb("dtlb", proc_id, dtlb_ways,dtlb_sets,vci_param::N)
381	{
382	assert( ((icache_words*vci_param::B) < (1<<vci_param::K)) and
383	"Need more PLEN bits.");
384
385	assert( (vci_param::T > 2) and ((1<<(vci_param::T-1)) >= (wbuf_nlines)) and
386	"Need more TRDID bits.");
387
388	assert( (icache_words == dcache_words) and
389	"icache_words and dcache_words parameters must be equal");
390
391	assert( (itlb_sets == dtlb_sets) and
392	"itlb_sets and dtlb_sets parameters must be etqual");
393
394	assert( (itlb_ways == dtlb_ways) and
395	"itlb_ways and dtlb_ways parameters must be etqual");
396
397	r_mmu_params = (uint32_log2(m_dtlb_ways) << 29) \| (uint32_log2(m_dtlb_sets) << 25) \|
398	(uint32_log2(m_dcache_ways) << 22) \| (uint32_log2(m_dcache_sets) << 18) \|
399	(uint32_log2(m_itlb_ways) << 15) \| (uint32_log2(m_itlb_sets) << 11) \|
400	(uint32_log2(m_icache_ways) << 8) \| (uint32_log2(m_icache_sets) << 4) \|
401	(uint32_log2(m_icache_words<<2));
402
403	r_mmu_release = (uint32_t)(1 << 16) \| 0x1;
404
405	r_dcache_in_tlb = new bool[dcache_ways*dcache_sets];
406	r_dcache_contains_ptd = new bool[dcache_ways*dcache_sets];
407
408	SC_METHOD(transition);
409	dont_initialize();
410	sensitive << p_clk.pos();
411
412	SC_METHOD(genMoore);
413	dont_initialize();
414	sensitive << p_clk.neg();
415
416	typename iss_t::CacheInfo cache_info;
417	cache_info.has_mmu = true;
418	cache_info.icache_line_size = icache_words*sizeof(uint32_t);
419	cache_info.icache_assoc = icache_ways;
420	cache_info.icache_n_lines = icache_sets;
421	cache_info.dcache_line_size = dcache_words*sizeof(uint32_t);
422	cache_info.dcache_assoc = dcache_ways;
423	cache_info.dcache_n_lines = dcache_sets;
424	r_iss.setCacheInfo(cache_info);
425	}
426
427	/////////////////////////////////////
428	tmpl(/**/)::~VciCcVCacheWrapper()
429	/////////////////////////////////////
430	{
431	delete [] r_dcache_in_tlb;
432	delete [] r_dcache_contains_ptd;
433	}
434
435	////////////////////////
436	tmpl(void)::print_cpi()
437	////////////////////////
438	{
439	std::cout << name() << " CPI = "
440	<< (float)m_cpt_total_cycles/(m_cpt_total_cycles - m_cpt_frz_cycles) << std::endl ;
441	}
442
443	////////////////////////////////////
444	tmpl(void)::print_trace(size_t mode)
445	////////////////////////////////////
446	{
447	// b0 : write buffer trace
448	// b1 : write buffer verbose
449	// b2 : dcache trace
450	// b3 : icache trace
451	// b4 : dtlb trace
452	// b5 : itlb trace
453
454	std::cout << std::dec << "PROC " << name() << std::endl;
455
456	std::cout << " " << m_ireq << std::endl;
457	std::cout << " " << m_irsp << std::endl;
458	std::cout << " " << m_dreq << std::endl;
459	std::cout << " " << m_drsp << std::endl;
460
461	std::cout << " " << icache_fsm_state_str[r_icache_fsm.read()]
462	<< " \| " << dcache_fsm_state_str[r_dcache_fsm.read()]
463	<< " \| " << cmd_fsm_state_str[r_vci_cmd_fsm.read()]
464	<< " \| " << rsp_fsm_state_str[r_vci_rsp_fsm.read()]
465	<< " \| " << cc_receive_fsm_state_str[r_cc_receive_fsm.read()]
466	<< " \| " << cc_send_fsm_state_str[r_cc_send_fsm.read()];
467	if (r_dcache_updt_req.read() ) std::cout << " \| P1_UPDT";
468	if (r_dcache_wbuf_req.read() ) std::cout << " \| P1_WBUF";
469	std::cout << std::endl;
470
471	if(mode & 0x01)
472	{
473	r_wbuf.printTrace((mode>>1)&1);
474	}
475	if(mode & 0x04)
476	{
477	std::cout << " Data Cache" << std::endl;
478	r_dcache.printTrace();
479	}
480	if(mode & 0x08)
481	{
482	std::cout << " Instruction Cache" << std::endl;
483	r_icache.printTrace();
484	}
485	if(mode & 0x10)
486	{
487	std::cout << " Data TLB" << std::endl;
488	r_dtlb.printTrace();
489	}
490	if(mode & 0x20)
491	{
492	std::cout << " Instruction TLB" << std::endl;
493	r_itlb.printTrace();
494	}
495	}
496
497	//////////////////////////////////////////
498	tmpl(void)::cache_monitor( paddr_t addr )
499	//////////////////////////////////////////
500	{
501	size_t cache_way;
502	size_t cache_set;
503	size_t cache_word;
504	uint32_t cache_rdata;
505	bool cache_hit = r_dcache.read_neutral( addr,
506	&cache_rdata,
507	&cache_way,
508	&cache_set,
509	&cache_word );
510	bool icache_hit = r_icache.read_neutral( addr,
511	&cache_rdata,
512	&cache_way,
513	&cache_set,
514	&cache_word );
515	if ( cache_hit != m_debug_previous_hit )
516	{
517	std::cout << "PROC " << name()
518	<< " dcache change at cycle " << std::dec << m_cpt_total_cycles
519	<< " for adresse " << std::hex << addr
520	<< " / HIT = " << std::dec << cache_hit << std::endl;
521	m_debug_previous_hit = cache_hit;
522	}
523	if ( icache_hit != m_idebug_previous_hit )
524	{
525	std::cout << "PROC " << name()
526	<< " icache change at cycle " << std::dec << m_cpt_total_cycles
527	<< " for adresse " << std::hex << addr
528	<< " / HIT = " << icache_hit << std::endl;
529	m_idebug_previous_hit = icache_hit;
530	}
531	}
532
533	/*
534	////////////////////////
535	tmpl(void)::print_stats()
536	////////////////////////
537	{
538	float run_cycles = (float)(m_cpt_total_cycles - m_cpt_frz_cycles);
539	std::cout << name() << std::endl
540	<< "- CPI = " << (float)m_cpt_total_cycles/run_cycles << std::endl
541	<< "- READ RATE = " << (float)m_cpt_read/run_cycles << std::endl
542	<< "- WRITE RATE = " << (float)m_cpt_write/run_cycles << std::endl
543	<< "- IMISS_RATE = " << (float)m_cpt_ins_miss/m_cpt_ins_read << std::endl
544	<< "- DMISS RATE = " << (float)m_cpt_data_miss/(m_cpt_read-m_cpt_unc_read) << std::endl
545	<< "- INS MISS COST = " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl
546	<< "- DATA MISS COST = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl
547	<< "- WRITE COST = " << (float)m_cost_write_frz/m_cpt_write << std::endl
548	<< "- UNC COST = " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl
549	<< "- UNCACHED READ RATE = " << (float)m_cpt_unc_read/m_cpt_read << std::endl
550	<< "- CACHED WRITE RATE = " << (float)m_cpt_write_cached/m_cpt_write << std::endl
551	<< "- INS TLB MISS RATE = " << (float)m_cpt_ins_tlb_miss/m_cpt_ins_tlb_read << std::endl
552	<< "- DATA TLB MISS RATE = " << (float)m_cpt_data_tlb_miss/m_cpt_data_tlb_read << std::endl
553	<< "- ITLB MISS COST = " << (float)m_cost_ins_tlb_miss_frz/m_cpt_ins_tlb_miss << std::endl
554	<< "- DTLB MISS COST = " << (float)m_cost_data_tlb_miss_frz/m_cpt_data_tlb_miss << std::endl
555	<< "- ITLB UPDATE ACC COST = " << (float)m_cost_ins_tlb_update_acc_frz/m_cpt_ins_tlb_update_acc << std::endl
556	<< "- DTLB UPDATE ACC COST = " << (float)m_cost_data_tlb_update_acc_frz/m_cpt_data_tlb_update_acc << std::endl
557	<< "- DTLB UPDATE DIRTY COST = " << (float)m_cost_data_tlb_update_dirty_frz/m_cpt_data_tlb_update_dirty << std::endl
558	<< "- ITLB HIT IN DCACHE RATE= " << (float)m_cpt_ins_tlb_hit_dcache/m_cpt_ins_tlb_miss << std::endl
559	<< "- DTLB HIT IN DCACHE RATE= " << (float)m_cpt_data_tlb_hit_dcache/m_cpt_data_tlb_miss << std::endl
560	<< "- DCACHE FROZEN BY ITLB = " << (float)m_cost_ins_tlb_occup_cache_frz/m_cpt_dcache_frz_cycles << std::endl
561	<< "- DCACHE FOR TLB % = " << (float)m_cpt_tlb_occup_dcache/(m_dcache_ways*m_dcache_sets) << std::endl
562	<< "- NB CC BROADCAST = " << m_cpt_cc_broadcast << std::endl
563	<< "- NB CC UPDATE DATA = " << m_cpt_cc_update_data << std::endl
564	<< "- NB CC INVAL DATA = " << m_cpt_cc_inval_data << std::endl
565	<< "- NB CC INVAL INS = " << m_cpt_cc_inval_ins << std::endl
566	<< "- CC BROADCAST COST = " << (float)m_cost_broadcast_frz/m_cpt_cc_broadcast << std::endl
567	<< "- CC UPDATE DATA COST = " << (float)m_cost_updt_data_frz/m_cpt_cc_update_data << std::endl
568	<< "- CC INVAL DATA COST = " << (float)m_cost_inval_data_frz/m_cpt_cc_inval_data << std::endl
569	<< "- CC INVAL INS COST = " << (float)m_cost_inval_ins_frz/m_cpt_cc_inval_ins << std::endl
570	<< "- NB CC CLEANUP DATA = " << m_cpt_cc_cleanup_data << std::endl
571	<< "- NB CC CLEANUP INS = " << m_cpt_cc_cleanup_ins << std::endl
572	<< "- IMISS TRANSACTION = " << (float)m_cost_imiss_transaction/m_cpt_imiss_transaction << std::endl
573	<< "- DMISS TRANSACTION = " << (float)m_cost_dmiss_transaction/m_cpt_dmiss_transaction << std::endl
574	<< "- UNC TRANSACTION = " << (float)m_cost_unc_transaction/m_cpt_unc_transaction << std::endl
575	<< "- WRITE TRANSACTION = " << (float)m_cost_write_transaction/m_cpt_write_transaction << std::endl
576	<< "- WRITE LENGTH = " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl
577	<< "- ITLB MISS TRANSACTION = " << (float)m_cost_itlbmiss_transaction/m_cpt_itlbmiss_transaction << std::endl
578	<< "- DTLB MISS TRANSACTION = " << (float)m_cost_dtlbmiss_transaction/m_cpt_dtlbmiss_transaction << std::endl;
579	}
580
581	////////////////////////
582	tmpl(void)::clear_stats()
583	////////////////////////
584	{
585	m_cpt_dcache_data_read = 0;
586	m_cpt_dcache_data_write = 0;
587	m_cpt_dcache_dir_read = 0;
588	m_cpt_dcache_dir_write = 0;
589	m_cpt_icache_data_read = 0;
590	m_cpt_icache_data_write = 0;
591	m_cpt_icache_dir_read = 0;
592	m_cpt_icache_dir_write = 0;
593
594	m_cpt_frz_cycles = 0;
595	m_cpt_dcache_frz_cycles = 0;
596	m_cpt_total_cycles = 0;
597
598	m_cpt_read = 0;
599	m_cpt_write = 0;
600	m_cpt_data_miss = 0;
601	m_cpt_ins_miss = 0;
602	m_cpt_unc_read = 0;
603	m_cpt_write_cached = 0;
604	m_cpt_ins_read = 0;
605
606	m_cost_write_frz = 0;
607	m_cost_data_miss_frz = 0;
608	m_cost_unc_read_frz = 0;
609	m_cost_ins_miss_frz = 0;
610
611	m_cpt_imiss_transaction = 0;
612	m_cpt_dmiss_transaction = 0;
613	m_cpt_unc_transaction = 0;
614	m_cpt_write_transaction = 0;
615	m_cpt_icache_unc_transaction = 0;
616
617	m_cost_imiss_transaction = 0;
618	m_cost_dmiss_transaction = 0;
619	m_cost_unc_transaction = 0;
620	m_cost_write_transaction = 0;
621	m_cost_icache_unc_transaction = 0;
622	m_length_write_transaction = 0;
623
624	m_cpt_ins_tlb_read = 0;
625	m_cpt_ins_tlb_miss = 0;
626	m_cpt_ins_tlb_update_acc = 0;
627
628	m_cpt_data_tlb_read = 0;
629	m_cpt_data_tlb_miss = 0;
630	m_cpt_data_tlb_update_acc = 0;
631	m_cpt_data_tlb_update_dirty = 0;
632	m_cpt_ins_tlb_hit_dcache = 0;
633	m_cpt_data_tlb_hit_dcache = 0;
634	m_cpt_ins_tlb_occup_cache = 0;
635	m_cpt_data_tlb_occup_cache = 0;
636
637	m_cost_ins_tlb_miss_frz = 0;
638	m_cost_data_tlb_miss_frz = 0;
639	m_cost_ins_tlb_update_acc_frz = 0;
640	m_cost_data_tlb_update_acc_frz = 0;
641	m_cost_data_tlb_update_dirty_frz = 0;
642	m_cost_ins_tlb_occup_cache_frz = 0;
643	m_cost_data_tlb_occup_cache_frz = 0;
644
645	m_cpt_itlbmiss_transaction = 0;
646	m_cpt_itlb_ll_transaction = 0;
647	m_cpt_itlb_sc_transaction = 0;
648	m_cpt_dtlbmiss_transaction = 0;
649	m_cpt_dtlb_ll_transaction = 0;
650	m_cpt_dtlb_sc_transaction = 0;
651	m_cpt_dtlb_ll_dirty_transaction = 0;
652	m_cpt_dtlb_sc_dirty_transaction = 0;
653
654	m_cost_itlbmiss_transaction = 0;
655	m_cost_itlb_ll_transaction = 0;
656	m_cost_itlb_sc_transaction = 0;
657	m_cost_dtlbmiss_transaction = 0;
658	m_cost_dtlb_ll_transaction = 0;
659	m_cost_dtlb_sc_transaction = 0;
660	m_cost_dtlb_ll_dirty_transaction = 0;
661	m_cost_dtlb_sc_dirty_transaction = 0;
662
663	m_cpt_cc_update_data = 0;
664	m_cpt_cc_inval_ins = 0;
665	m_cpt_cc_inval_data = 0;
666	m_cpt_cc_broadcast = 0;
667
668	m_cost_updt_data_frz = 0;
669	m_cost_inval_ins_frz = 0;
670	m_cost_inval_data_frz = 0;
671	m_cost_broadcast_frz = 0;
672
673	m_cpt_cc_cleanup_data = 0;
674	m_cpt_cc_cleanup_ins = 0;
675	}
676
677	*/
678
679	/////////////////////////
680	tmpl(void)::transition()
681	/////////////////////////
682	{
683	#define LLSCLocalTable GenericLLSCLocalTable<8000, 1, paddr_t, vci_trdid_t, vci_data_t>
684	if ( not p_resetn.read() )
685	{
686	r_iss.reset();
687	r_wbuf.reset();
688	r_icache.reset();
689	r_dcache.reset();
690	r_itlb.reset();
691	r_dtlb.reset();
692
693	r_dcache_fsm = DCACHE_IDLE;
694	r_icache_fsm = ICACHE_IDLE;
695	r_vci_cmd_fsm = CMD_IDLE;
696	r_vci_rsp_fsm = RSP_IDLE;
697	r_cc_receive_fsm = CC_RECEIVE_IDLE;
698	r_cc_send_fsm = CC_SEND_IDLE;
699
700	// reset dcache directory extension
701	for (size_t i=0 ; i< m_dcache_ways*m_dcache_sets ; i++)
702	{
703	r_dcache_in_tlb[i] = false;
704	r_dcache_contains_ptd[i] = false;
705	}
706
707	// Response FIFOs and cleanup buffer
708	r_vci_rsp_fifo_icache.init();
709	r_vci_rsp_fifo_dcache.init();
710
711	// ICACHE & DCACHE activated
712	r_mmu_mode = 0x3;
713
714	// No request from ICACHE FSM to CMD FSM
715	r_icache_miss_req = false;
716	r_icache_unc_req = false;
717
718	// No request from ICACHE_FSM to DCACHE FSM
719	r_icache_tlb_miss_req = false;
720
721	// No request from ICACHE_FSM to CC_SEND FSM
722	r_icache_cc_send_req = false;
723
724	// No pending write in pipeline
725	r_dcache_wbuf_req = false;
726	r_dcache_updt_req = false;
727
728	// No request from DCACHE_FSM to CMD_FSM
729	r_dcache_vci_miss_req = false;
730	r_dcache_vci_unc_req = false;
731	r_dcache_vci_cas_req = false;
732	r_dcache_vci_ll_req = false;
733	r_dcache_vci_sc_req = false;
734
735	// No uncacheable write pending
736	r_dcache_pending_unc_write = false;
737
738	// No processor XTN request pending
739	r_dcache_xtn_req = false;
740
741	// No request from DCACHE FSM to CC_SEND FSM
742	r_dcache_cc_send_req = false;
743
744	// No request from CC_RECEIVE FSM to ICACHE/DCACHE FSMs
745	r_cc_receive_icache_req = false;
746	r_cc_receive_dcache_req = false;
747
748	// last cc_send client was dcache
749	r_cc_send_last_client = false;
750
751	// No pending cleanup after a replacement
752	r_icache_miss_clack = false;
753	r_dcache_miss_clack = false;
754
755	// No signalisation of a coherence request matching a pending miss
756	r_icache_miss_inval = false;
757	r_dcache_miss_inval = false;
758
759	// No signalisation of errors
760	r_vci_rsp_ins_error = false;
761	r_vci_rsp_data_error = false;
762
763	// Debug variables
764	m_debug_previous_hit = false;
765	m_idebug_previous_hit = false;
766	m_debug_dcache_fsm = false;
767	m_debug_icache_fsm = false;
768
769	// activity counters
770	m_cpt_dcache_data_read = 0;
771	m_cpt_dcache_data_write = 0;
772	m_cpt_dcache_dir_read = 0;
773	m_cpt_dcache_dir_write = 0;
774	m_cpt_icache_data_read = 0;
775	m_cpt_icache_data_write = 0;
776	m_cpt_icache_dir_read = 0;
777	m_cpt_icache_dir_write = 0;
778
779	m_cpt_frz_cycles = 0;
780	m_cpt_total_cycles = 0;
781	m_cpt_stop_simulation = 0;
782
783	m_cpt_data_miss = 0;
784	m_cpt_ins_miss = 0;
785	m_cpt_unc_read = 0;
786	m_cpt_write_cached = 0;
787	m_cpt_ins_read = 0;
788
789	m_cost_write_frz = 0;
790	m_cost_data_miss_frz = 0;
791	m_cost_unc_read_frz = 0;
792	m_cost_ins_miss_frz = 0;
793
794	m_cpt_imiss_transaction = 0;
795	m_cpt_dmiss_transaction = 0;
796	m_cpt_unc_transaction = 0;
797	m_cpt_write_transaction = 0;
798	m_cpt_icache_unc_transaction = 0;
799
800	m_cost_imiss_transaction = 0;
801	m_cost_dmiss_transaction = 0;
802	m_cost_unc_transaction = 0;
803	m_cost_write_transaction = 0;
804	m_cost_icache_unc_transaction = 0;
805	m_length_write_transaction = 0;
806
807	m_cpt_ins_tlb_read = 0;
808	m_cpt_ins_tlb_miss = 0;
809	m_cpt_ins_tlb_update_acc = 0;
810
811	m_cpt_data_tlb_read = 0;
812	m_cpt_data_tlb_miss = 0;
813	m_cpt_data_tlb_update_acc = 0;
814	m_cpt_data_tlb_update_dirty = 0;
815	m_cpt_ins_tlb_hit_dcache = 0;
816	m_cpt_data_tlb_hit_dcache = 0;
817	m_cpt_ins_tlb_occup_cache = 0;
818	m_cpt_data_tlb_occup_cache = 0;
819
820	m_cost_ins_tlb_miss_frz = 0;
821	m_cost_data_tlb_miss_frz = 0;
822	m_cost_ins_tlb_update_acc_frz = 0;
823	m_cost_data_tlb_update_acc_frz = 0;
824	m_cost_data_tlb_update_dirty_frz = 0;
825	m_cost_ins_tlb_occup_cache_frz = 0;
826	m_cost_data_tlb_occup_cache_frz = 0;
827
828	m_cpt_ins_tlb_inval = 0;
829	m_cpt_data_tlb_inval = 0;
830	m_cost_ins_tlb_inval_frz = 0;
831	m_cost_data_tlb_inval_frz = 0;
832
833	m_cpt_cc_broadcast = 0;
834
835	m_cost_updt_data_frz = 0;
836	m_cost_inval_ins_frz = 0;
837	m_cost_inval_data_frz = 0;
838	m_cost_broadcast_frz = 0;
839
840	m_cpt_cc_cleanup_data = 0;
841	m_cpt_cc_cleanup_ins = 0;
842
843	m_cpt_itlbmiss_transaction = 0;
844	m_cpt_itlb_ll_transaction = 0;
845	m_cpt_itlb_sc_transaction = 0;
846	m_cpt_dtlbmiss_transaction = 0;
847	m_cpt_dtlb_ll_transaction = 0;
848	m_cpt_dtlb_sc_transaction = 0;
849	m_cpt_dtlb_ll_dirty_transaction = 0;
850	m_cpt_dtlb_sc_dirty_transaction = 0;
851
852	m_cost_itlbmiss_transaction = 0;
853	m_cost_itlb_ll_transaction = 0;
854	m_cost_itlb_sc_transaction = 0;
855	m_cost_dtlbmiss_transaction = 0;
856	m_cost_dtlb_ll_transaction = 0;
857	m_cost_dtlb_sc_transaction = 0;
858	m_cost_dtlb_ll_dirty_transaction = 0;
859	m_cost_dtlb_sc_dirty_transaction = 0;
860	/*
861	m_cpt_dcache_frz_cycles = 0;
862	m_cpt_read = 0;
863	m_cpt_write = 0;
864	m_cpt_cc_update_data = 0;
865	m_cpt_cc_inval_ins = 0;
866	m_cpt_cc_inval_data = 0;
867	*/
868
869	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_icache [i] = 0;
870	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_dcache [i] = 0;
871	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_cmd [i] = 0;
872	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_rsp [i] = 0;
873
874	// init the llsc reservation buffer
875	r_dcache_llsc_valid = false;
876
877	return;
878	}
879
880	// Response FIFOs default values
881	bool vci_rsp_fifo_icache_get = false;
882	bool vci_rsp_fifo_icache_put = false;
883	uint32_t vci_rsp_fifo_icache_data = 0;
884
885	bool vci_rsp_fifo_dcache_get = false;
886	bool vci_rsp_fifo_dcache_put = false;
887	uint32_t vci_rsp_fifo_dcache_data = 0;
888
889	// updt fifo
890	bool cc_receive_updt_fifo_get = false;
891	bool cc_receive_updt_fifo_put = false;
892	uint32_t cc_receive_updt_fifo_be = 0;
893	uint32_t cc_receive_updt_fifo_data = 0;
894	bool cc_receive_updt_fifo_eop = false;
895
896	#ifdef INSTRUMENTATION
897	m_cpt_fsm_dcache [r_dcache_fsm.read() ] ++;
898	m_cpt_fsm_icache [r_icache_fsm.read() ] ++;
899	m_cpt_fsm_cmd [r_vci_cmd_fsm.read()] ++;
900	m_cpt_fsm_rsp [r_vci_rsp_fsm.read()] ++;
901	m_cpt_fsm_tgt [r_tgt_fsm.read() ] ++;
902	m_cpt_fsm_cleanup [r_cleanup_cmd_fsm.read()] ++;
903	#endif
904
905	m_cpt_total_cycles++;
906
907	m_debug_icache_fsm = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok;
908	m_debug_dcache_fsm = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok;
909
910	/////////////////////////////////////////////////////////////////////
911	// Get data and instruction requests from processor
912	///////////////////////////////////////////////////////////////////////
913
914	r_iss.getRequests(m_ireq, m_dreq);
915
916	////////////////////////////////////////////////////////////////////////////////////
917	// ICACHE_FSM
918	//
919	// 1/ Coherence operations
920	// They are handled as interrupts generated by the CC_RECEIVE FSM.
921	// - There is a coherence request when r_tgt_icache_req is set.
922	// They are taken in IDLE, MISS_WAIT, MISS_DIR_UPDT, UNC_WAIT, states.
923	// - There is a cleanup ack request when r_cleanup_icache_req is set.
924	// They are taken in IDLE, MISS_SELECT, MISS_CLEAN, MISS_WAIT,
925	// MISS_DATA_UPDT, MISS_DIR_UPDT and UNC_WAIT states.
926	// - For both types of requests, actions associated to the pre-empted state
927	// are not executed. The DCACHE FSM goes to the proper sub-FSM (CC_CHECK
928	// or CC_CLACK) to execute the requested coherence operation, and returns
929	// to the pre-empted state.
930	//
931	// 2/ Processor requests
932	// They are taken in IDLE state only. In case of cache miss, or uncacheable
933	// instruction, the ICACHE FSM request a VCI transaction to CMD FSM,
934	// using the r_icache_miss_req or r_icache_unc_req flip-flops. These
935	// flip-flops are reset when the transaction starts.
936	// - In case of miss the ICACHE FSM goes to the ICACHE_MISS_SELECT state
937	// to select a slot and possibly request a cleanup transaction to the CC_SEND FSM.
938	// It goes next to the ICACHE_MISS_WAIT state waiting a response from RSP FSM,
939	// The availability of the missing cache line is signaled by the response fifo,
940	// and the cache update is done (one word per cycle) in the ICACHE_MISS_DATA_UPDT
941	// and ICACHE_MISS_DIR_UPDT states.
942	// - In case of uncacheable instruction, the ICACHE FSM goes to ICACHE_UNC_WAIT
943	// to wait the response from the RSP FSM, through the response fifo.
944	// The missing instruction is directly returned to processor in this state.
945	//
946	// 3/ TLB miss
947	// In case of tlb miss, the ICACHE FSM request to the DCACHE FSM to update the
948	// ITLB using the r_icache_tlb_miss_req flip-flop and the r_icache_tlb_miss_vaddr
949	// register, and goes to the ICACHE_TLB_WAIT state.
950	// The tlb update is entirely done by the DCACHE FSM (who becomes the owner
951	// of ITLB until the update is completed, and reset r_icache_tlb_miss_req
952	// to signal the completion.
953	//
954	// 4/ XTN requests
955	// The DCACHE FSM signals XTN processor requests to ICACHE_FSM
956	// using the r_dcache_xtn_req flip-flop.
957	// The request opcode and the address to be invalidated are transmitted
958	// in the r_dcache_xtn_opcode and r_dcache_save_wdata registers respectively.
959	// The r_dcache_xtn_req flip-flop is reset by the ICACHE_FSM when the operation
960	// is completed.
961	//
962	// 5/ Error Handling
963	// The r_vci_rsp_ins_error flip-flop is set by the RSP FSM in case of bus error
964	// in a cache miss or uncacheable read VCI transaction. Nothing is written
965	// in the response fifo. This flip-flop is reset by the ICACHE-FSM.
966	////////////////////////////////////////////////////////////////////////////////////////
967
968	// default value for m_irsp
969	m_irsp.valid = false;
970	m_irsp.error = false;
971	m_irsp.instruction = 0;
972
973	switch( r_icache_fsm.read() )
974	{
975	/////////////////
976	case ICACHE_IDLE: // In this state, we handle processor requests, XTN requests,
977	// and coherence requests with a fixed priority:
978	// 1/ Coherence requests => ICACHE_CC_CHECK
979	// 2/ XTN processor requests (from DCACHE FSM) => ICACHE_XTN_*
980	// 3/ tlb miss => ICACHE_TLB_WAIT
981	// 4/ cacheable read miss => ICACHE_MISS_SELECT
982	// 5/ uncacheable read miss => ICACHE_UNC_REQ
983	{
984	// coherence interrupt
985	if ( r_cc_receive_icache_req.read() )
986	{
987	r_icache_fsm = ICACHE_CC_CHECK;
988	r_icache_fsm_save = r_icache_fsm.read();
989	break;
990	}
991
992	// XTN requests sent by DCACHE FSM
993	// These request are not executed in this IDLE state, because
994	// they require access to icache or itlb, that are already accessed
995	if ( r_dcache_xtn_req.read() )
996	{
997	if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_PTPR )
998	{
999	r_icache_fsm = ICACHE_XTN_TLB_FLUSH;
1000	}
1001	else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ICACHE_FLUSH)
1002	{
1003	r_icache_flush_count = 0;
1004	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH;
1005	}
1006	else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ITLB_INVAL)
1007	{
1008	r_icache_fsm = ICACHE_XTN_TLB_INVAL;
1009	}
1010	else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ICACHE_INVAL)
1011	{
1012	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_VA;
1013	}
1014	else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_MMU_ICACHE_PA_INV)
1015	{
1016	if (sizeof(paddr_t) <= 32)
1017	{
1018	assert(r_mmu_word_hi.read() == 0 &&
1019	"illegal XTN request in ICACHE: high bits should be 0 for 32bit paddr");
1020	r_icache_vci_paddr = (paddr_t)r_mmu_word_lo.read();
1021	}
1022	else
1023	{
1024	r_icache_vci_paddr = (paddr_t)r_mmu_word_hi.read() << 32 \|
1025	(paddr_t)r_mmu_word_lo.read();
1026	}
1027	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA;
1028	}
1029	else
1030	{
1031	assert( false and
1032	"undefined XTN request received by ICACHE FSM");
1033	}
1034	break;
1035	} // end if xtn_req
1036
1037	// processor request
1038	if ( m_ireq.valid )
1039	{
1040	bool cacheable;
1041	paddr_t paddr;
1042	bool tlb_hit = false;
1043	pte_info_t tlb_flags;
1044	size_t tlb_way;
1045	size_t tlb_set;
1046	paddr_t tlb_nline;
1047	uint32_t cache_inst = 0;
1048	size_t cache_way;
1049	size_t cache_set;
1050	size_t cache_word;
1051	int cache_state = CACHE_SLOT_STATE_EMPTY;
1052
1053	// We register processor request
1054	r_icache_vaddr_save = m_ireq.addr;
1055
1056	// sytematic itlb access (if activated)
1057	if ( r_mmu_mode.read() & INS_TLB_MASK )
1058	{
1059
1060	#ifdef INSTRUMENTATION
1061	m_cpt_itlb_read++;
1062	#endif
1063	tlb_hit = r_itlb.translate( m_ireq.addr,
1064	&paddr,
1065	&tlb_flags,
1066	&tlb_nline, // unused
1067	&tlb_way, // unused
1068	&tlb_set ); // unused
1069	}
1070	else
1071	{
1072	paddr = (paddr_t)m_ireq.addr;
1073	}
1074
1075	// systematic icache access (if activated)
1076	if ( r_mmu_mode.read() & INS_CACHE_MASK )
1077	{
1078
1079
1080	#ifdef INSTRUMENTATION
1081	m_cpt_icache_data_read++;
1082	m_cpt_icache_dir_read++;
1083	#endif
1084	r_icache.read( paddr,
1085	&cache_inst,
1086	&cache_way,
1087	&cache_set,
1088	&cache_word,
1089	&cache_state );
1090	}
1091
1092	// We compute cacheability and check access rights:
1093	// - If MMU activated : cacheability is defined by the C bit in the PTE,
1094	// and the access rights are defined by the U and X bits in the PTE.
1095	// - If MMU not activated : cacheability is defined by the segment table,
1096	// and there is no access rights checking
1097
1098	if ( not (r_mmu_mode.read() & INS_TLB_MASK) ) // tlb not activated:
1099	{
1100	// cacheability
1101	if ( not (r_mmu_mode.read() & INS_CACHE_MASK) ) cacheable = false;
1102	else cacheable = m_cacheability_table[m_ireq.addr];
1103	}
1104	else // itlb activated
1105	{
1106	if ( tlb_hit ) // ITLB hit
1107	{
1108	// cacheability
1109	if ( not (r_mmu_mode.read() & INS_CACHE_MASK) ) cacheable = false;
1110	else cacheable = tlb_flags.c;
1111
1112	// access rights checking
1113	if ( not tlb_flags.u && (m_ireq.mode == iss_t::MODE_USER) )
1114	{
1115	r_mmu_ietr = MMU_READ_PRIVILEGE_VIOLATION;
1116	r_mmu_ibvar = m_ireq.addr;
1117	m_irsp.valid = true;
1118	m_irsp.error = true;
1119	m_irsp.instruction = 0;
1120	break;
1121	}
1122	else if ( not tlb_flags.x )
1123	{
1124	r_mmu_ietr = MMU_READ_EXEC_VIOLATION;
1125	r_mmu_ibvar = m_ireq.addr;
1126	m_irsp.valid = true;
1127	m_irsp.error = true;
1128	m_irsp.instruction = 0;
1129	break;
1130	}
1131	}
1132	else // ITLB miss
1133	{
1134
1135	#ifdef INSTRUMENTATION
1136	m_cpt_itlb_miss++;
1137	#endif
1138	r_icache_fsm = ICACHE_TLB_WAIT;
1139	r_icache_tlb_miss_req = true;
1140	break;
1141	}
1142	} // end if itlb activated
1143
1144	// physical address registration
1145	r_icache_vci_paddr = paddr;
1146
1147	// Finally, we send the response to processor, and compute next state
1148	if ( cacheable )
1149	{
1150	if (cache_state == CACHE_SLOT_STATE_EMPTY) // cache miss
1151	{
1152
1153	#ifdef INSTRUMENTATION
1154	m_cpt_icache_miss++;
1155	#endif
1156	// we request a VCI transaction
1157	r_icache_fsm = ICACHE_MISS_SELECT;
1158	#if DEBUG_ICACHE
1159	if ( m_debug_icache_fsm )
1160	{
1161	std::cout << " <PROC " << name()
1162	<< " ICACHE_IDLE> READ MISS in icache"
1163	<< " : PADDR = " << std::hex << paddr << std::endl;
1164	}
1165	#endif
1166	r_icache_miss_req = true;
1167	}
1168	else if (cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup
1169	{
1170	// stalled until cleanup is acknowledged
1171	r_icache_fsm = ICACHE_IDLE;
1172	}
1173	else // cache hit
1174	{
1175
1176	#ifdef INSTRUMENTATION
1177	m_cpt_ins_read++;
1178	#endif
1179	// return instruction to processor
1180	m_irsp.valid = true;
1181	m_irsp.instruction = cache_inst;
1182	r_icache_fsm = ICACHE_IDLE;
1183	#if DEBUG_ICACHE
1184	if ( m_debug_icache_fsm )
1185	{
1186	std::cout << " <PROC " << name()
1187	<< " ICACHE_IDLE> READ HIT in icache"
1188	<< " : PADDR = " << std::hex << paddr << std::endl;
1189	}
1190	#endif
1191	}
1192	}
1193	else // non cacheable read
1194	{
1195	r_icache_unc_req = true;
1196	r_icache_fsm = ICACHE_UNC_WAIT;
1197
1198	#if DEBUG_ICACHE
1199	if ( m_debug_icache_fsm )
1200	{
1201	std::cout << " <PROC " << name()
1202	<< " ICACHE_IDLE> READ UNCACHEABLE in icache"
1203	<< " : PADDR = " << std::hex << paddr << std::endl;
1204	}
1205	#endif
1206	}
1207	} // end if m_ireq.valid
1208	break;
1209	}
1210	/////////////////////
1211	case ICACHE_TLB_WAIT: // Waiting the itlb update by the DCACHE FSM after a tlb miss
1212	// the itlb is udated by the DCACHE FSM, as well as the
1213	// r_mmu_ietr and r_mmu_ibvar registers in case of error.
1214	// the itlb is not accessed by ICACHE FSM until DCACHE FSM
1215	// reset the r_icache_tlb_miss_req flip-flop
1216	// external coherence request are accepted in this state.
1217	{
1218	// coherence interrupt
1219	if ( r_cc_receive_icache_req.read() )
1220	{
1221	r_icache_fsm = ICACHE_CC_CHECK;
1222	r_icache_fsm_save = r_icache_fsm.read();
1223	break;
1224	}
1225
1226	if ( m_ireq.valid ) m_cost_ins_tlb_miss_frz++;
1227
1228	// DCACHE FSM signals response by reseting the request flip-flop
1229	if ( not r_icache_tlb_miss_req.read() )
1230	{
1231	if ( r_icache_tlb_rsp_error.read() ) // error reported : tlb not updated
1232	{
1233	r_icache_tlb_rsp_error = false;
1234	m_irsp.error = true;
1235	m_irsp.valid = true;
1236	r_icache_fsm = ICACHE_IDLE;
1237	}
1238	else // tlb updated : return to IDLE state
1239	{
1240	r_icache_fsm = ICACHE_IDLE;
1241	}
1242	}
1243	break;
1244	}
1245	//////////////////////////
1246	case ICACHE_XTN_TLB_FLUSH: // invalidate in one cycle all non global TLB entries
1247	{
1248	r_itlb.flush();
1249	r_dcache_xtn_req = false;
1250	r_icache_fsm = ICACHE_IDLE;
1251	break;
1252	}
1253	////////////////////////////
1254	case ICACHE_XTN_CACHE_FLUSH: // Invalidate sequencially all cache lines, using
1255	// r_icache_flush_count as a slot counter,
1256	// looping in this state until all slots are visited.
1257	// It can require two cycles per slot:
1258	// We test here the slot state, and make the actual inval
1259	// (if line is valid) in ICACHE_XTN_CACHE_FLUSH_GO state.
1260	// A cleanup request is generated for each valid line
1261	{
1262	// coherence request (from CC_RECEIVE FSM)
1263	if ( r_cc_receive_icache_req.read() )
1264	{
1265	r_icache_fsm = ICACHE_CC_CHECK;
1266	r_icache_fsm_save = r_icache_fsm.read();
1267	break;
1268	}
1269
1270	if ( not r_icache_cc_send_req.read() ) // blocked until previous cc_send request is sent
1271	{
1272	int state;
1273	uint32_t tag;
1274	size_t way = r_icache_flush_count.read()/m_icache_sets;
1275	size_t set = r_icache_flush_count.read()%m_icache_sets;
1276
1277	#ifdef INSTRUMENTATION
1278	m_cpt_icache_dir_read++;
1279	#endif
1280	r_icache.read_dir( way,
1281	set,
1282	&tag,
1283	&state );
1284
1285	if ( state == CACHE_SLOT_STATE_VALID ) // inval required
1286	{
1287	// request cleanup
1288	r_icache_cc_send_req = true;
1289	r_icache_cc_send_nline = tag * m_icache_sets + set;
1290	r_icache_cc_send_way = way;
1291	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1292
1293	// goes to ICACHE_XTN_CACHE_FLUSH_GO to make inval
1294	r_icache_miss_way = way;
1295	r_icache_miss_set = set;
1296	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH_GO;
1297	}
1298	else if ( r_icache_flush_count.read() ==
1299	(m_icache_sets*m_icache_ways - 1) ) // last slot
1300	{
1301	r_dcache_xtn_req = false;
1302	m_drsp.valid = true;
1303	r_icache_fsm = ICACHE_IDLE;
1304	}
1305
1306	// saturation counter, to have the same last slot condition
1307	// in ICACHE_XTN_CACHE_FLUSH and ICACHE_XTN_CACHE_FLUSH_GO states
1308	if ( r_icache_flush_count.read() < (m_icache_sets*m_icache_ways - 1) )
1309	{
1310	r_icache_flush_count = r_icache_flush_count.read() + 1;
1311	}
1312	}
1313	break;
1314	}
1315	///////////////////////////////
1316	case ICACHE_XTN_CACHE_FLUSH_GO: // Switch slot state to ZOMBI for an XTN flush
1317	{
1318	size_t way = r_icache_miss_way.read();
1319	size_t set = r_icache_miss_set.read();
1320
1321	#ifdef INSTRUMENTATION
1322	m_cpt_icache_dir_write++;
1323	#endif
1324
1325	r_icache.write_dir( way,
1326	set,
1327	CACHE_SLOT_STATE_ZOMBI );
1328
1329	if ( r_icache_flush_count.read() ==
1330	(m_icache_sets*m_icache_ways - 1) ) // last slot
1331	{
1332	r_dcache_xtn_req = false;
1333	m_drsp.valid = true;
1334	r_icache_fsm = ICACHE_IDLE;
1335	}
1336	else
1337	{
1338	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH;
1339	}
1340	break;
1341	}
1342
1343	//////////////////////////
1344	case ICACHE_XTN_TLB_INVAL: // invalidate one TLB entry selected by the virtual address
1345	// stored in the r_dcache_save_wdata register
1346	{
1347	r_itlb.inval(r_dcache_save_wdata.read());
1348	r_dcache_xtn_req = false;
1349	r_icache_fsm = ICACHE_IDLE;
1350	break;
1351	}
1352	///////////////////////////////
1353	case ICACHE_XTN_CACHE_INVAL_VA: // Selective cache line invalidate with virtual address
1354	// requires 3 cycles (in case of hit on itlb and icache).
1355	// In this state, access TLB to translate virtual address
1356	// stored in the r_dcache_save_wdata register.
1357	{
1358	paddr_t paddr;
1359	bool hit;
1360
1361	// read physical address in TLB when MMU activated
1362	if ( r_mmu_mode.read() & INS_TLB_MASK ) // itlb activated
1363	{
1364
1365	#ifdef INSTRUMENTATION
1366	m_cpt_itlb_read++;
1367	#endif
1368	hit = r_itlb.translate(r_dcache_save_wdata.read(),
1369	&paddr);
1370	}
1371	else // itlb not activated
1372	{
1373	paddr = (paddr_t)r_dcache_save_wdata.read();
1374	hit = true;
1375	}
1376
1377	if ( hit ) // continue the selective inval process
1378	{
1379	r_icache_vci_paddr = paddr;
1380	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA;
1381	}
1382	else // miss : send a request to DCACHE FSM
1383	{
1384
1385	#ifdef INSTRUMENTATION
1386	m_cpt_itlb_miss++;
1387	#endif
1388	r_icache_tlb_miss_req = true;
1389	r_icache_vaddr_save = r_dcache_save_wdata.read();
1390	r_icache_fsm = ICACHE_TLB_WAIT;
1391	}
1392	break;
1393	}
1394	///////////////////////////////
1395	case ICACHE_XTN_CACHE_INVAL_PA: // selective invalidate cache line with physical address
1396	// require 2 cycles. In this state, we read directory
1397	// with address stored in r_icache_vci_paddr register.
1398	{
1399	int state;
1400	size_t way;
1401	size_t set;
1402	size_t word;
1403
1404	#ifdef INSTRUMENTATION
1405	m_cpt_icache_dir_read++;
1406	#endif
1407	r_icache.read_dir(r_icache_vci_paddr.read(),
1408	&state,
1409	&way,
1410	&set,
1411	&word);
1412
1413	if ( state == CACHE_SLOT_STATE_VALID ) // inval to be done
1414	{
1415	r_icache_miss_way = way;
1416	r_icache_miss_set = set;
1417	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_GO;
1418	}
1419	else // miss : acknowlege the XTN request and return
1420	{
1421	r_dcache_xtn_req = false;
1422	r_icache_fsm = ICACHE_IDLE;
1423	}
1424	break;
1425	}
1426	///////////////////////////////
1427	case ICACHE_XTN_CACHE_INVAL_GO: // Switch slot to ZOMBI state for an XTN inval
1428	{
1429	if ( not r_icache_cc_send_req.read() ) // blocked until previous cc_send request not sent
1430	{
1431
1432	#ifdef INSTRUMENTATION
1433	m_cpt_icache_dir_write++;
1434	#endif
1435	r_icache.write_dir( r_icache_miss_way.read(),
1436	r_icache_miss_set.read(),
1437	CACHE_SLOT_STATE_ZOMBI );
1438
1439	// request cleanup
1440	r_icache_cc_send_req = true;
1441	r_icache_cc_send_nline = r_icache_vci_paddr.read() / (m_icache_words<<2);
1442	r_icache_cc_send_way = r_icache_miss_way.read();
1443	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1444
1445	// acknowledge the XTN request and return
1446	r_dcache_xtn_req = false;
1447	r_icache_fsm = ICACHE_IDLE;
1448	}
1449	break;
1450	}
1451	////////////////////////
1452	case ICACHE_MISS_SELECT: // Try to select a slot in associative set,
1453	// if previous cleanup has been sent.
1454	// Waiting in this state if no slot available.
1455	// Set the r_icache_cleanup_req flip-flop
1456	// and the r_icache_miss_clack flip-flop,
1457	// when a cleanup is required
1458	{
1459	if (m_ireq.valid) m_cost_ins_miss_frz++;
1460
1461	// coherence interrupt
1462	if ( r_cc_receive_icache_req.read() )
1463	{
1464	r_icache_fsm = ICACHE_CC_CHECK;
1465	r_icache_fsm_save = r_icache_fsm.read();
1466	break;
1467	}
1468
1469	if ( not r_icache_cc_send_req.read() ) // wait for previous cc_send request to be sent
1470	{
1471	bool found;
1472	bool cleanup;
1473	size_t way;
1474	size_t set;
1475	paddr_t victim;
1476
1477	#ifdef INSTRUMENTATION
1478	m_cpt_icache_dir_read++;
1479	#endif
1480	r_icache.read_select(r_icache_vci_paddr.read(),
1481	&victim,
1482	&way,
1483	&set,
1484	&found,
1485	&cleanup );
1486	if ( found )
1487	{
1488	r_icache_miss_way = way;
1489	r_icache_miss_set = set;
1490
1491	if ( cleanup )
1492	{
1493	r_icache_fsm = ICACHE_MISS_CLEAN;
1494	r_icache_miss_clack = true;
1495	// request cleanup
1496	r_icache_cc_send_req = true;
1497	r_icache_cc_send_nline = victim;
1498	r_icache_cc_send_way = way;
1499	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1500	}
1501	else
1502	{
1503	r_icache_fsm = ICACHE_MISS_WAIT;
1504	}
1505
1506	#if DEBUG_ICACHE
1507	if ( m_debug_dcache_fsm )
1508	{
1509	std::cout << " <PROC " << name()
1510	<< " ICACHE_MISS_SELECT> Select a slot:" << std::dec
1511	<< " / WAY = " << way
1512	<< " / SET = " << set;
1513	if (cleanup) std::cout << " / VICTIM = " << std::hex << victim << std::endl;
1514	else std::cout << std::endl;
1515	}
1516	#endif
1517	}
1518	}
1519	break;
1520	}
1521	///////////////////////
1522	case ICACHE_MISS_CLEAN: // switch the slot to zombi state
1523	{
1524	if (m_ireq.valid) m_cost_ins_miss_frz++;
1525
1526	#ifdef INSTRUMENTATION
1527	m_cpt_icache_dir_write++;
1528	#endif
1529	r_icache.write_dir( r_icache_miss_way.read(),
1530	r_icache_miss_set.read(),
1531	CACHE_SLOT_STATE_ZOMBI);
1532	#if DEBUG_ICACHE
1533	if ( m_debug_dcache_fsm )
1534	{
1535	std::cout << " <PROC " << name()
1536	<< " ICACHE_MISS_CLEAN> Switch to ZOMBI state" << std::dec
1537	<< " / WAY = " << r_icache_miss_way.read()
1538	<< " / SET = " << r_icache_miss_set.read() << std::endl;
1539	}
1540	#endif
1541
1542	r_icache_fsm = ICACHE_MISS_WAIT;
1543	break;
1544	}
1545	//////////////////////
1546	case ICACHE_MISS_WAIT: // waiting response from VCI_RSP FSM
1547	{
1548	if (m_ireq.valid) m_cost_ins_miss_frz++;
1549
1550	// coherence interrupt
1551	if ( r_cc_receive_icache_req.read() )
1552	{
1553	r_icache_fsm = ICACHE_CC_CHECK;
1554	r_icache_fsm_save = r_icache_fsm.read();
1555	break;
1556	}
1557
1558	if ( r_vci_rsp_ins_error.read() ) // bus error
1559	{
1560	r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS;
1561	r_mmu_ibvar = r_icache_vaddr_save.read();
1562	m_irsp.valid = true;
1563	m_irsp.error = true;
1564	r_vci_rsp_ins_error = false;
1565	r_icache_fsm = ICACHE_IDLE;
1566	}
1567	else if ( r_vci_rsp_fifo_icache.rok() ) // response available
1568	{
1569	r_icache_miss_word = 0;
1570	r_icache_fsm = ICACHE_MISS_DATA_UPDT;
1571	}
1572	break;
1573	}
1574	///////////////////////////
1575	case ICACHE_MISS_DATA_UPDT: // update the cache (one word per cycle)
1576	{
1577	if ( m_ireq.valid ) m_cost_ins_miss_frz++;
1578
1579	if ( r_vci_rsp_fifo_icache.rok() ) // response available
1580	{
1581
1582	#ifdef INSTRUMENTATION
1583	m_cpt_icache_data_write++;
1584	#endif
1585	r_icache.write( r_icache_miss_way.read(),
1586	r_icache_miss_set.read(),
1587	r_icache_miss_word.read(),
1588	r_vci_rsp_fifo_icache.read() );
1589	#if DEBUG_ICACHE
1590	if ( m_debug_icache_fsm )
1591	{
1592	std::cout << " <PROC " << name()
1593	<< " ICACHE_MISS_DATA_UPDT> Write one word:"
1594	<< " WDATA = " << r_vci_rsp_fifo_icache.read()
1595	<< " WAY = " << r_icache_miss_way.read()
1596	<< " SET = " << r_icache_miss_set.read()
1597	<< " WORD = " << r_icache_miss_word.read() << std::endl;
1598	}
1599	#endif
1600	vci_rsp_fifo_icache_get = true;
1601	r_icache_miss_word = r_icache_miss_word.read() + 1;
1602
1603	if ( r_icache_miss_word.read() == m_icache_words-1 ) // last word
1604	{
1605	r_icache_fsm = ICACHE_MISS_DIR_UPDT;
1606	}
1607	}
1608	break;
1609	}
1610	//////////////////////////
1611	case ICACHE_MISS_DIR_UPDT: // Stalled if a victim line has been evicted,
1612	// and the cleanup ack has not been received,
1613	// as indicated by r_icache_miss_clack.
1614	// - If no matching coherence request (r_icache_miss_inval)
1615	// switch directory slot to VALID state.
1616	// - If matching coherence request, switch directory slot
1617	// to ZOMBI state, and send a cleanup request.
1618	{
1619	if ( m_ireq.valid ) m_cost_ins_miss_frz++;
1620
1621	// coherence interrupt
1622	if ( r_cc_receive_icache_req.read() )
1623	{
1624	r_icache_fsm = ICACHE_CC_CHECK;
1625	r_icache_fsm_save = r_icache_fsm.read();
1626	break;
1627	}
1628
1629	if ( not r_icache_miss_clack.read() ) // waiting cleanup acknowledge for victim line
1630	{
1631	if ( r_icache_miss_inval ) // Switch slot to ZOMBI state, and new cleanup
1632	{
1633	if ( not r_icache_cc_send_req.read() )
1634	{
1635	r_icache_miss_inval = false;
1636	// request cleanup
1637	r_icache_cc_send_req = true;
1638	r_icache_cc_send_nline = r_icache_vci_paddr.read() / (m_icache_words<<2);
1639	r_icache_cc_send_way = r_icache_miss_way.read();
1640	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1641
1642	#ifdef INSTRUMENTATION
1643	m_cpt_icache_dir_write++;
1644	#endif
1645	r_icache.write_dir( r_icache_vci_paddr.read(),
1646	r_icache_miss_way.read(),
1647	r_icache_miss_set.read(),
1648	CACHE_SLOT_STATE_ZOMBI );
1649	#if DEBUG_ICACHE
1650	if ( m_debug_icache_fsm )
1651	{
1652	std::cout << " <PROC " << name()
1653	<< " ICACHE_MISS_DIR_UPDT> Switch cache slot to ZOMBI state"
1654	<< " PADDR = " << std::hex << r_icache_vci_paddr.read()
1655	<< " WAY = " << std::dec << r_icache_miss_way.read()
1656	<< " SET = " << r_icache_miss_set.read() << std::endl;
1657	}
1658	#endif
1659	}
1660	else
1661	break;
1662	}
1663	else // Switch slot to VALID state
1664	{
1665
1666	#ifdef INSTRUMENTATION
1667	m_cpt_icache_dir_write++;
1668	#endif
1669	r_icache.write_dir( r_icache_vci_paddr.read(),
1670	r_icache_miss_way.read(),
1671	r_icache_miss_set.read(),
1672	CACHE_SLOT_STATE_VALID );
1673	#if DEBUG_ICACHE
1674	if ( m_debug_icache_fsm )
1675	{
1676	std::cout << " <PROC " << name()
1677	<< " ICACHE_MISS_DIR_UPDT> Switch cache slot to VALID state"
1678	<< " PADDR = " << std::hex << r_icache_vci_paddr.read()
1679	<< " WAY = " << std::dec << r_icache_miss_way.read()
1680	<< " SET = " << r_icache_miss_set.read() << std::endl;
1681	}
1682	#endif
1683	}
1684
1685	r_icache_fsm = ICACHE_IDLE;
1686	}
1687	break;
1688	}
1689	////////////////////
1690	case ICACHE_UNC_WAIT: // waiting a response to an uncacheable read from VCI_RSP FSM
1691	{
1692	// coherence interrupt
1693	if ( r_cc_receive_icache_req.read() )
1694	{
1695	r_icache_fsm = ICACHE_CC_CHECK;
1696	r_icache_fsm_save = r_icache_fsm.read();
1697	break;
1698	}
1699
1700	if ( r_vci_rsp_ins_error.read() ) // bus error
1701	{
1702	r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS;
1703	r_mmu_ibvar = m_ireq.addr;
1704	r_vci_rsp_ins_error = false;
1705	m_irsp.valid = true;
1706	m_irsp.error = true;
1707	r_icache_fsm = ICACHE_IDLE;
1708	}
1709	else if (r_vci_rsp_fifo_icache.rok() ) // instruction available
1710	{
1711	vci_rsp_fifo_icache_get = true;
1712	r_icache_fsm = ICACHE_IDLE;
1713	if ( m_ireq.valid and
1714	(m_ireq.addr == r_icache_vaddr_save.read()) ) // request unmodified
1715	{
1716	m_irsp.valid = true;
1717	m_irsp.instruction = r_vci_rsp_fifo_icache.read();
1718	}
1719	}
1720	break;
1721	}
1722	/////////////////////
1723	case ICACHE_CC_CHECK: // This state is the entry point of a sub-fsm
1724	// handling coherence requests.
1725	// if there is a matching pending miss, it is
1726	// signaled in the r_icache_miss_inval flip-flop.
1727	// The return state is defined in r_icache_fsm_save.
1728	{
1729	paddr_t paddr = r_cc_receive_icache_nline.read() * m_icache_words * 4;
1730	paddr_t mask = ~((m_icache_words<<2)-1);
1731
1732	if (r_cc_receive_icache_type.read() == CC_TYPE_CLACK)
1733	// We switch the directory slot to EMPTY state
1734	// and reset r_icache_miss_clack if the cleanup ack
1735	// is matching a pending miss
1736	{
1737
1738	if ( m_ireq.valid ) m_cost_ins_miss_frz++;
1739
1740	#ifdef INSTRUMENTATION
1741	m_cpt_icache_dir_write++;
1742	#endif
1743	r_icache.write_dir( 0,
1744	r_cc_receive_icache_way.read(),
1745	r_cc_receive_icache_set.read(),
1746	CACHE_SLOT_STATE_EMPTY);
1747
1748	if ( (r_icache_miss_set.read() == r_cc_receive_icache_set.read()) and
1749	(r_icache_miss_way.read() == r_cc_receive_icache_way.read()) )
1750	r_icache_miss_clack = false;
1751
1752	r_icache_fsm = r_icache_fsm_save.read() ;
1753	r_cc_receive_icache_req = false;
1754
1755	#if DEBUG_ICACHE
1756	if ( m_debug_icache_fsm )
1757	{
1758	std::cout << " <PROC " << name()
1759	<< " ICACHE_CC_CHECK> CC_TYPE_CLACK slot returns to empty state"
1760	<< " set = " << r_cc_receive_icache_set.read()
1761	<< " / way = " << r_cc_receive_icache_way.read() << std::endl;
1762	}
1763	#endif
1764	}
1765	else if( ((r_icache_fsm_save.read() == ICACHE_MISS_SELECT) or
1766	(r_icache_fsm_save.read() == ICACHE_MISS_WAIT) or
1767	(r_icache_fsm_save.read() == ICACHE_MISS_DIR_UPDT)) and
1768	((r_icache_vci_paddr.read() & mask) == (paddr & mask)) ) // matching
1769	{
1770	// signaling the matching
1771	r_icache_miss_inval = true;
1772
1773	// in case of update, go to CC_UPDT
1774	// JUST TO POP THE FIFO
1775	if (r_cc_receive_icache_type.read() == CC_TYPE_UPDT)
1776	{
1777	r_icache_fsm = ICACHE_CC_UPDT;
1778	r_icache_cc_word = r_cc_receive_word_idx.read();
1779	// just pop the fifo , don't write in icache
1780	r_icache_cc_need_write = false;
1781	}
1782	// the request is dealt with
1783	else
1784	{
1785	r_cc_receive_icache_req = false;
1786	r_icache_fsm = r_icache_fsm_save.read();
1787	}
1788	#if DEBUG_ICACHE
1789	if ( m_debug_icache_fsm )
1790	{
1791	std::cout << " <PROC " << name()
1792	<< " ICACHE_CC_CHECK> Coherence request matching a pending miss:"
1793	<< " PADDR = " << std::hex << paddr << std::endl;
1794	}
1795	#endif
1796	}
1797	else // no match
1798	{
1799	int state;
1800	size_t way;
1801	size_t set;
1802	size_t word;
1803
1804	#ifdef INSTRUMENTATION
1805	m_cpt_icache_dir_read++;
1806	#endif
1807	r_icache.read_dir(paddr,
1808	&state,
1809	&way,
1810	&set,
1811	&word);
1812
1813	r_icache_cc_way = way;
1814	r_icache_cc_set = set;
1815
1816	if ( state == CACHE_SLOT_STATE_VALID) // hit
1817	{
1818	// need to update the cache state
1819	r_icache_cc_need_write = true;
1820	if (r_cc_receive_icache_type.read() == CC_TYPE_UPDT) // hit update
1821	{
1822	r_icache_fsm = ICACHE_CC_UPDT;
1823	r_icache_cc_word = r_cc_receive_word_idx.read();
1824	}
1825	else if (r_cc_receive_icache_type.read() == CC_TYPE_INVAL) // hit inval
1826	{
1827	r_icache_fsm = ICACHE_CC_INVAL;
1828	}
1829	else if (r_cc_receive_icache_type.read() == CC_TYPE_BRDCAST) // hit broadcast
1830	{
1831	r_icache_fsm = ICACHE_CC_BROADCAST;
1832	}
1833	}
1834	else // miss
1835	{
1836	// multicast acknowledgement required in case of update
1837	if(r_cc_receive_icache_type.read() == CC_TYPE_UPDT)
1838	{
1839	r_icache_fsm = ICACHE_CC_UPDT;
1840	r_icache_cc_word = r_cc_receive_word_idx.read();
1841	// just pop the fifo , don't write in icache
1842	r_icache_cc_need_write = false;
1843	}
1844	else // No response needed
1845	{
1846	r_cc_receive_icache_req = false;
1847	r_icache_fsm = r_icache_fsm_save.read();
1848	}
1849	}
1850	}
1851	break;
1852	}
1853	/////////////////////
1854	case ICACHE_CC_INVAL: // hit inval : switch slot to EMPTY state
1855	{
1856
1857	#if DEBUG_ICACHE
1858	if ( m_debug_icache_fsm )
1859	{
1860	std::cout << " <PROC " << name()
1861	<< " ICACHE_CC_INVAL> slot returns to empty state"
1862	<< " set = " << r_icache_cc_set.read()
1863	<< " / way = " << r_icache_cc_way.read() << std::endl;
1864	}
1865	#endif
1866
1867	#ifdef INSTRUMENTATION
1868	m_cpt_icache_dir_read++;
1869	#endif
1870	if (r_icache_cc_need_write.read())
1871	{
1872	r_icache.write_dir( 0,
1873	r_icache_cc_way.read(),
1874	r_icache_cc_set.read(),
1875	CACHE_SLOT_STATE_EMPTY );
1876	// no need to write in the cache anymore
1877	r_icache_cc_need_write = false;
1878	}
1879
1880	// multicast acknowledgement
1881	// send a request to cc_send_fsm
1882	if(not r_icache_cc_send_req.read()) // cc_send is available
1883	{
1884	// coherence request completed
1885	r_cc_receive_icache_req = false;
1886	// request multicast acknowledgement
1887	r_icache_cc_send_req = true;
1888	r_icache_cc_send_nline = r_cc_receive_icache_nline.read();
1889	r_icache_cc_send_updt_tab_idx = r_cc_receive_icache_updt_tab_idx.read();
1890	r_icache_cc_send_type = CC_TYPE_MULTI_ACK;
1891
1892	r_icache_fsm = r_icache_fsm_save.read();
1893	}
1894	//else wait for previous cc_send request to be sent
1895	break;
1896	}
1897	////////////////////
1898	case ICACHE_CC_UPDT: // hit update : write one word per cycle
1899	{
1900
1901	#if DEBUG_ICACHE
1902	if ( m_debug_icache_fsm )
1903	{
1904	std::cout << " <PROC " << name()
1905	<< " ICACHE_CC_UPDT> Write one word "
1906	<< " set = " << r_icache_cc_set.read()
1907	<< " / way = " << r_icache_cc_way.read()
1908	<< " / word = " << r_icache_cc_word.read() << std::endl;
1909	}
1910	#endif
1911
1912	#ifdef INSTRUMENTATION
1913	m_cpt_icache_data_write++;
1914	#endif
1915	size_t word = r_icache_cc_word.read();
1916	size_t way = r_icache_cc_way.read();
1917	size_t set = r_icache_cc_set.read();
1918
1919	if (r_cc_receive_updt_fifo_be.rok())
1920	{
1921	if (r_icache_cc_need_write.read())
1922	{
1923	r_icache.write( way,
1924	set,
1925	word,
1926	r_cc_receive_updt_fifo_data.read(),
1927	r_cc_receive_updt_fifo_be.read() );
1928
1929	r_icache_cc_word = word+1;
1930	}
1931	if ( r_cc_receive_updt_fifo_eop.read() ) // last word
1932	{
1933	// no need to write in the cache anymore
1934	r_icache_cc_need_write = false;
1935	// wait to send a request to cc_send_fsm
1936	if(not r_icache_cc_send_req.read()) // cc_send is available
1937	{
1938	//consume last flit
1939	cc_receive_updt_fifo_get = true;
1940	// coherence request completed
1941	r_cc_receive_icache_req = false;
1942	// request multicast acknowledgement
1943	r_icache_cc_send_req = true;
1944	r_icache_cc_send_nline = r_cc_receive_icache_nline.read();
1945	r_icache_cc_send_updt_tab_idx = r_cc_receive_icache_updt_tab_idx.read();
1946	r_icache_cc_send_type = CC_TYPE_MULTI_ACK;
1947
1948	r_icache_fsm = r_icache_fsm_save.read();
1949	}
1950	}
1951	else
1952	{
1953	//consume fifo if not eop
1954	cc_receive_updt_fifo_get = true;
1955	}
1956	}
1957	break;
1958	}
1959	/////////////////////////
1960	case ICACHE_CC_BROADCAST: // hit broadcast : switch slot to ZOMBI state
1961	// and request a cleanup
1962	{
1963
1964	#if DEBUG_ICACHE
1965	if ( m_debug_icache_fsm )
1966	{
1967	std::cout << " <PROC " << name()
1968	<< " ICACHE_CC_BROADCAST > Slot goes to zombi state "
1969	<< " set = " << r_icache_cc_set.read()
1970	<< " / way = " << r_icache_cc_way.read() << std::endl;
1971	}
1972	#endif
1973
1974	#ifdef INSTRUMENTATION
1975	m_cpt_icache_dir_write++;
1976	#endif
1977	if (r_icache_cc_need_write.read())
1978	{
1979	r_icache.write_dir( r_icache_cc_way.read(),
1980	r_icache_cc_set.read(),
1981	CACHE_SLOT_STATE_ZOMBI );
1982	// no need to write in the cache anymore
1983	r_icache_cc_need_write = false;
1984	}
1985
1986	// cleanup
1987	// send a request to cc_send_fsm
1988	if(not r_icache_cc_send_req.read()) // cc_send is available
1989	{
1990	// coherence request completed
1991	r_cc_receive_icache_req = false;
1992	// request cleanup
1993	r_icache_cc_send_req = true;
1994	r_icache_cc_send_nline = r_cc_receive_icache_nline.read();
1995	r_icache_cc_send_way = r_icache_cc_way.read();
1996	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1997
1998	r_icache_fsm = r_icache_fsm_save.read();
1999	}
2000	//else wait for previous cc_send request to be sent
2001	break;
2002	}
2003	} // end switch r_icache_fsm
2004
2005	////////////////////////////////////////////////////////////////////////////////////
2006	// DCACHE FSM
2007	//
2008	// 1/ Coherence operations
2009	// They are handled as interrupts generated by the CC_RECEIVE FSM.
2010	// - There is a coherence request when r_tgt_dcache_req is set.
2011	// They are taken in IDLE, MISS_WAIT, MISS_DIR_UPDT, UNC_WAIT, LL_WAIT
2012	// and SC_WAIT states.
2013	// - There is a cleanup acknowledge request when r_cleanup_dcache_req is set.
2014	// They are taken in IDLE, MISS_SELECT, MISS_CLEAN, MISS_WAIT, MISS_DATA_UPDT,
2015	// MISS_DIR_UPDT, UNC_WAIT, LL_WAIT, SC_WAIT states.
2016	// - For both types of requests, actions associated to the pre-empted state
2017	// are not executed. The DCACHE FSM goes to the proper sub-FSM (CC_CHECK
2018	// or CC_CLACK) to execute the requested coherence operation, and returns
2019	// to the pre-empted state.
2020	//
2021	// 2/ TLB miss
2022	// The page tables are generally cacheable.
2023	// In case of miss in itlb or dtlb, the tlb miss is handled by a dedicated
2024	// sub-fsm (DCACHE_TLB_MISS state), that handle possible miss in DCACHE,
2025	// this sub-fsm implement the table-walk...
2026	//
2027	// 3/ processor requests
2028	// Processor requests are taken in IDLE state only.
2029	// The IDLE state implements a two stages pipe-line to handle write bursts:
2030	// - Both DTLB and DCACHE are accessed in stage P0 (if processor request valid).
2031	// - The registration in wbuf and the dcache update is done in stage P1
2032	// (if the processor request is a write).
2033	// The two r_dcache_wbuf_req and r_dcache_updt_req flip-flops define
2034	// the operations that must be done in P1 stage, and the access type
2035	// (read or write) to the DATA part of DCACHE depends on r_dcache_updt_req.
2036	// READ requests are delayed if a cache update is requested.
2037	// WRITE or SC requests can require a PTE Dirty bit update (in memory),
2038	// that is done (before handling the processor request) by a dedicated sub-fsm.
2039	// If a PTE is modified, both the itlb and dtlb are selectively, but sequencially
2040	// cleared by a dedicated sub_fsm (DCACHE_INVAL_TLB_SCAN state).
2041	//
2042	// 4/ Atomic instructions LL/SC
2043	// The LL/SC address are non cacheable (systematic access to memory).
2044	// The llsc buffer contains a registration for an active LL/SC operation
2045	// (with an address, a registration key, an aging counter and a valid bit).
2046	// - LL requests from the processor are transmitted as a one flit VCI command
2047	// (CMD_LOCKED_READ as CMD, and TYPE_LL as PKTID value). PLEN must
2048	// be 8 as the response is 2 flits long (data and registration key)
2049	// - SC requests from the processor are systematically transmitted to the
2050	// memory cache as 2 flits VCI command (CMD_STORE_COND as CMD, and TYPE_SC
2051	// as PKTID value). The first flit contains the registration key, the second
2052	// flit contains the data to write in case of success.
2053	// The cache is not updated, as this is done in case of success by the
2054	// coherence transaction.
2055	//
2056	// 5/ Non cacheable access:
2057	// This component implement a strong order between non cacheable access
2058	// (read or write) : A new non cacheable VCI transaction starts only when
2059	// the previous non cacheable transaction is completed. Both cacheable and
2060	// non cacheable transactions use the write buffer, but the DCACHE FSM registers
2061	// a non cacheable write transaction posted in the write buffer by setting the
2062	// r_dcache_pending_unc_write flip_flop. All other non cacheable requests
2063	// are stalled until this flip-flop is reset by the VCI_RSP_FSM (when the
2064	// pending non cacheable write transaction completes).
2065	//
2066	// 6/ Error handling:
2067	// When the MMU is not activated, Read Bus Errors are synchronous events,
2068	// but Write Bus Errors are asynchronous events (processor is not frozen).
2069	// - If a Read Bus Error is detected, the VCI_RSP FSM sets the
2070	// r_vci_rsp_data_error flip-flop, without writing any data in the
2071	// r_vci_rsp_fifo_dcache FIFO, and the synchronous error is signaled
2072	// by the DCACHE FSM.
2073	// - If a Write Bus Error is detected, the VCI_RSP FSM signals
2074	// the asynchronous error using the setWriteBerr() method.
2075	// When the MMU is activated bus error are rare events, as the MMU
2076	// checks the physical address before the VCI transaction starts.
2077	////////////////////////////////////////////////////////////////////////////////////////
2078
2079	// default value for m_drsp
2080	m_drsp.valid = false;
2081	m_drsp.error = false;
2082	m_drsp.rdata = 0;
2083
2084	switch ( r_dcache_fsm.read() )
2085	{
2086	case DCACHE_IDLE: // There are 10 conditions to exit the IDLE state :
2087	// 1) ITLB/DTLB inval request (update) => DCACHE_INVAL_TLB_SCAN
2088	// 2) Coherence request (TGT FSM) => DCACHE_CC_CHECK
2089	// 3) ITLB miss request (ICACHE FSM) => DCACHE_TLB_MISS
2090	// 4) XTN request (processor) => DCACHE_XTN_*
2091	// 5) DTLB miss (processor) => DCACHE_TLB_MISS
2092	// 6) Dirty bit update (processor) => DCACHE_DIRTY_GET_PTE
2093	// 7) Cacheable read miss (processor) => DCACHE_MISS_SELECT
2094	// 8) Uncacheable read (processor) => DCACHE_UNC_WAIT
2095	// 9) LL access (processor) => DCACHE_LL_WAIT
2096	// 10) SC access (processor) => DCACHE_SC_WAIT
2097	//
2098	// There is a fixed priority to handle requests to DCACHE:
2099	// 1/ the ITLB/DTLB invalidate requests
2100	// 2/ the coherence requests,
2101	// 3/ the processor requests (including DTLB miss),
2102	// 4/ the ITLB miss requests,
2103	// The address space processor request are handled as follows:
2104	// - WRITE request is blocked if the Dirty bit mus be set.
2105	// If DTLB hit, the P1 stage is activated (writes WBUF, and
2106	// updates DCACHE if DCACHE hit) & processor request acknowledged.
2107	// - READ request generate a simultaneouss access to DCACHE.DATA
2108	// and DCACHE.DIR, but is delayed if DCACHE update required.
2109	//
2110	// There is 4 configurations defining the access type to
2111	// DTLB, DCACHE.DATA, and DCACHE.DIR, depending on the
2112	// dreq.valid (dreq) and r_dcache_updt_req (updt) signals:
2113	// dreq / updt / DTLB / DCACHE.DIR / DCACHE.DATA /
2114	// 0 / 0 / NOP / NOP / NOP /
2115	// 0 / 1 / NOP / NOP / WRITE /
2116	// 1 / 0 / READ / READ / NOP /
2117	// 1 / 1 / READ / READ / WRITE /
2118	// Those two registers are set at each cycle from the 3 signals
2119	// updt_request, wbuf_request, wbuf_write_miss.
2120	{
2121	paddr_t paddr; // physical address
2122	pte_info_t tlb_flags;
2123	size_t tlb_way;
2124	size_t tlb_set;
2125	paddr_t tlb_nline;
2126	size_t cache_way;
2127	size_t cache_set;
2128	size_t cache_word;
2129	uint32_t cache_rdata = 0;
2130	bool tlb_hit = false;
2131	int cache_state = CACHE_SLOT_STATE_EMPTY;
2132
2133	bool tlb_inval_required = false; // request TLB inval after cache update
2134	bool wbuf_write_miss = false; // miss a WBUF write request
2135	bool updt_request = false; // request DCACHE update in P1 stage
2136	bool wbuf_request = false; // request WBUF write in P1 stage
2137
2138	// physical address computation : systematic DTLB access if activated)
2139	if ( m_dreq.valid )
2140	{
2141	if ( r_mmu_mode.read() & DATA_TLB_MASK ) // DTLB activated
2142	{
2143	tlb_hit = r_dtlb.translate( m_dreq.addr,
2144	&paddr,
2145	&tlb_flags,
2146	&tlb_nline,
2147	&tlb_way,
2148	&tlb_set );
2149	#ifdef INSTRUMENTATION
2150	m_cpt_dtlb_read++;
2151	#endif
2152	}
2153	else // identity mapping
2154	{
2155	paddr = (paddr_t)m_dreq.addr;
2156	}
2157	} // end physical address computation
2158
2159	// systematic DCACHE access depending on r_dcache_updt_req (if activated)
2160	if ( r_mmu_mode.read() & DATA_CACHE_MASK)
2161	{
2162	if ( m_dreq.valid and r_dcache_updt_req.read() ) // read DIR and write DATA
2163	{
2164	r_dcache.read_dir( paddr,
2165	&cache_state,
2166	&cache_way,
2167	&cache_set,
2168	&cache_word );
2169
2170	r_dcache.write( r_dcache_save_cache_way.read(),
2171	r_dcache_save_cache_set.read(),
2172	r_dcache_save_cache_word.read(),
2173	r_dcache_save_wdata.read(),
2174	r_dcache_save_be.read() );
2175	#ifdef INSTRUMENTATION
2176	m_cpt_dcache_dir_read++;
2177	m_cpt_dcache_data_write++;
2178	#endif
2179	}
2180	else if ( m_dreq.valid and not r_dcache_updt_req.read() ) // read DIR and DATA
2181	{
2182	r_dcache.read( paddr,
2183	&cache_rdata,
2184	&cache_way,
2185	&cache_set,
2186	&cache_word,
2187	&cache_state );
2188
2189	#ifdef INSTRUMENTATION
2190	m_cpt_dcache_dir_read++;
2191	m_cpt_dcache_data_read++;
2192	#endif
2193	}
2194	else if ( not m_dreq.valid and r_dcache_updt_req.read() ) // write DATA
2195	{
2196	r_dcache.write( r_dcache_save_cache_way.read(),
2197	r_dcache_save_cache_set.read(),
2198	r_dcache_save_cache_word.read(),
2199	r_dcache_save_wdata.read(),
2200	r_dcache_save_be.read() );
2201	#ifdef INSTRUMENTATION
2202	m_cpt_dcache_data_write++;
2203	#endif
2204	}
2205	} // end dcache access
2206
2207	// DCACHE update in P1 stage can require ITLB / DTLB inval or flush
2208	if ( r_dcache_updt_req.read() )
2209	{
2210	size_t way = r_dcache_save_cache_way.read();
2211	size_t set = r_dcache_save_cache_set.read();
2212
2213	if ( r_dcache_in_tlb[way*m_dcache_sets+set] )
2214	{
2215	tlb_inval_required = true;
2216	r_dcache_tlb_inval_set = 0;
2217	r_dcache_tlb_inval_line = r_dcache_save_paddr.read()>>
2218	(uint32_log2(m_dcache_words<<2));
2219	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
2220	}
2221	else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] )
2222	{
2223	r_itlb.reset();
2224	r_dtlb.reset();
2225	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
2226	}
2227
2228	#if DEBUG_DCACHE
2229	if ( m_debug_dcache_fsm )
2230	{
2231	std::cout << " <PROC " << name()
2232	<< " DCACHE_IDLE> Cache update in P1 stage" << std::dec
2233	<< " / WAY = " << r_dcache_save_cache_way.read()
2234	<< " / SET = " << r_dcache_save_cache_set.read()
2235	<< " / WORD = " << r_dcache_save_cache_word.read() << std::hex
2236	<< " / DATA = " << r_dcache_save_wdata.read()
2237	<< " / BE = " << r_dcache_save_be.read() << std::endl;
2238	}
2239	#endif
2240	} // end test TLB inval
2241
2242	// Try WBUF update in P1 stage
2243	// Miss if the write request is non cacheable, and there is a pending
2244	// non cacheable write, or if the write buffer is full.
2245	if ( r_dcache_wbuf_req.read() )
2246	{
2247	// miss if write not cacheable, and previous non cacheable write registered
2248	if ( not r_dcache_save_cacheable.read() and r_dcache_pending_unc_write.read() )
2249	{
2250	wbuf_write_miss = true;
2251	}
2252	else // try a registration into write buffer
2253	{
2254	bool wok = r_wbuf.write( r_dcache_save_paddr.read(),
2255	r_dcache_save_be.read(),
2256	r_dcache_save_wdata.read(),
2257	r_dcache_save_cacheable.read() );
2258	#ifdef INSTRUMENTATION
2259	m_cpt_wbuf_write++;
2260	#endif
2261	if ( not wok ) // miss if write buffer full
2262	{
2263	wbuf_write_miss = true;
2264	}
2265	else // update the write_buffer state extension
2266	{
2267	if(not r_dcache_pending_unc_write.read())
2268	r_dcache_pending_unc_write = not r_dcache_save_cacheable.read();
2269	}
2270	}
2271	} // end WBUF update
2272
2273	// Computing the response to processor,
2274	// and the next value for r_dcache_fsm
2275
2276	// itlb/dtlb invalidation self-request
2277	if ( tlb_inval_required )
2278	{
2279	r_dcache_fsm_scan_save = r_dcache_fsm.read();
2280	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
2281	}
2282
2283	// coherence request (from CC_RECEIVE FSM)
2284	else if ( r_cc_receive_dcache_req.read() )
2285	{
2286	r_dcache_fsm = DCACHE_CC_CHECK;
2287	r_dcache_fsm_cc_save = r_dcache_fsm.read();
2288	}
2289
2290	// processor request (READ, WRITE, LL, SC, XTN_READ, XTN_WRITE)
2291	// we don't take the processor request, and registers
2292	// are frozen in case of wbuf_write_miss
2293	else if ( m_dreq.valid and not wbuf_write_miss )
2294	{
2295	// register processor request and DCACHE response
2296	r_dcache_save_vaddr = m_dreq.addr;
2297	r_dcache_save_be = m_dreq.be;
2298	r_dcache_save_wdata = m_dreq.wdata;
2299	r_dcache_save_paddr = paddr;
2300	r_dcache_save_cache_way = cache_way;
2301	r_dcache_save_cache_set = cache_set;
2302	r_dcache_save_cache_word = cache_word;
2303
2304	// READ XTN requests from processor
2305	// They are executed in this DCACHE_IDLE state.
2306	// The processor must not be in user mode
2307	if (m_dreq.type == iss_t::XTN_READ)
2308	{
2309	int xtn_opcode = (int)m_dreq.addr/4;
2310
2311	// checking processor mode:
2312	if (m_dreq.mode == iss_t::MODE_USER)
2313	{
2314	r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION;
2315	r_mmu_dbvar = m_dreq.addr;
2316	m_drsp.valid = true;
2317	m_drsp.error = true;
2318	m_drsp.rdata = 0;
2319	r_dcache_fsm = DCACHE_IDLE;
2320	}
2321	else
2322	{
2323	switch( xtn_opcode )
2324	{
2325	case iss_t::XTN_INS_ERROR_TYPE:
2326	m_drsp.rdata = r_mmu_ietr.read();
2327	m_drsp.valid = true;
2328	m_drsp.error = false;
2329	break;
2330
2331	case iss_t::XTN_DATA_ERROR_TYPE:
2332	m_drsp.rdata = r_mmu_detr.read();
2333	m_drsp.valid = true;
2334	m_drsp.error = false;
2335	break;
2336
2337	case iss_t::XTN_INS_BAD_VADDR:
2338	m_drsp.rdata = r_mmu_ibvar.read();
2339	m_drsp.valid = true;
2340	m_drsp.error = false;
2341	break;
2342
2343	case iss_t::XTN_DATA_BAD_VADDR:
2344	m_drsp.rdata = r_mmu_dbvar.read();
2345	m_drsp.valid = true;
2346	m_drsp.error = false;
2347	break;
2348
2349	case iss_t::XTN_PTPR:
2350	m_drsp.rdata = r_mmu_ptpr.read();
2351	m_drsp.valid = true;
2352	m_drsp.error = false;
2353	break;
2354
2355	case iss_t::XTN_TLB_MODE:
2356	m_drsp.rdata = r_mmu_mode.read();
2357	m_drsp.valid = true;
2358	m_drsp.error = false;
2359	break;
2360
2361	case iss_t::XTN_MMU_PARAMS:
2362	m_drsp.rdata = r_mmu_params;
2363	m_drsp.valid = true;
2364	m_drsp.error = false;
2365	break;
2366
2367	case iss_t::XTN_MMU_RELEASE:
2368	m_drsp.rdata = r_mmu_release;
2369	m_drsp.valid = true;
2370	m_drsp.error = false;
2371	break;
2372
2373	case iss_t::XTN_MMU_WORD_LO:
2374	m_drsp.rdata = r_mmu_word_lo.read();
2375	m_drsp.valid = true;
2376	m_drsp.error = false;
2377	break;
2378
2379	case iss_t::XTN_MMU_WORD_HI:
2380	m_drsp.rdata = r_mmu_word_hi.read();
2381	m_drsp.valid = true;
2382	m_drsp.error = false;
2383	break;
2384
2385	default:
2386	r_mmu_detr = MMU_READ_UNDEFINED_XTN;
2387	r_mmu_dbvar = m_dreq.addr;
2388	m_drsp.valid = true;
2389	m_drsp.error = true;
2390	m_drsp.rdata = 0;
2391	break;
2392	} // end switch xtn_opcode
2393	} // end else
2394	} // end if XTN_READ
2395
2396	// Handling WRITE XTN requests from processor.
2397	// They are not executed in this DCACHE_IDLE state
2398	// if they require access to the caches or the TLBs
2399	// that are already accessed.
2400	// Caches can be invalidated or flushed in user mode,
2401	// and the sync instruction can be executed in user mode
2402	else if (m_dreq.type == iss_t::XTN_WRITE)
2403	{
2404	int xtn_opcode = (int)m_dreq.addr/4;
2405	r_dcache_xtn_opcode = xtn_opcode;
2406
2407	// checking processor mode:
2408	if ( (m_dreq.mode == iss_t::MODE_USER) &&
2409	(xtn_opcode != iss_t::XTN_SYNC) &&
2410	(xtn_opcode != iss_t::XTN_DCACHE_INVAL) &&
2411	(xtn_opcode != iss_t::XTN_DCACHE_FLUSH) &&
2412	(xtn_opcode != iss_t::XTN_ICACHE_INVAL) &&
2413	(xtn_opcode != iss_t::XTN_ICACHE_FLUSH) )
2414	{
2415	r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION;
2416	r_mmu_dbvar = m_dreq.addr;
2417	m_drsp.valid = true;
2418	m_drsp.error = true;
2419	m_drsp.rdata = 0;
2420	r_dcache_fsm = DCACHE_IDLE;
2421	}
2422	else
2423	{
2424	switch( xtn_opcode )
2425	{
2426	case iss_t::XTN_PTPR: // itlb & dtlb must be flushed
2427	r_dcache_xtn_req = true;
2428	r_dcache_fsm = DCACHE_XTN_SWITCH;
2429	break;
2430
2431	case iss_t::XTN_TLB_MODE: // no cache or tlb access
2432	r_mmu_mode = m_dreq.wdata;
2433	m_drsp.valid = true;
2434	r_dcache_fsm = DCACHE_IDLE;
2435	break;
2436
2437	case iss_t::XTN_DTLB_INVAL: // dtlb access
2438	r_dcache_fsm = DCACHE_XTN_DT_INVAL;
2439	break;
2440
2441	case iss_t::XTN_ITLB_INVAL: // itlb access
2442	r_dcache_xtn_req = true;
2443	r_dcache_fsm = DCACHE_XTN_IT_INVAL;
2444	break;
2445
2446	case iss_t::XTN_DCACHE_INVAL: // dcache, dtlb & itlb access
2447	r_dcache_fsm = DCACHE_XTN_DC_INVAL_VA;
2448	break;
2449
2450	case iss_t::XTN_MMU_DCACHE_PA_INV: // dcache, dtlb & itlb access
2451	r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA;
2452	if (sizeof(paddr_t) <= 32)
2453	{
2454	assert(r_mmu_word_hi.read() == 0 &&
2455	"high bits should be 0 for 32bit paddr");
2456	r_dcache_save_paddr = (paddr_t)r_mmu_word_lo.read();
2457	}
2458	else
2459	{
2460	r_dcache_save_paddr = (paddr_t)r_mmu_word_hi.read() << 32 \|
2461	(paddr_t)r_mmu_word_lo.read();
2462	}
2463	break;
2464
2465	case iss_t::XTN_DCACHE_FLUSH: // itlb and dtlb must be reset
2466	r_dcache_flush_count = 0;
2467	r_dcache_fsm = DCACHE_XTN_DC_FLUSH;
2468	break;
2469
2470	case iss_t::XTN_ICACHE_INVAL: // icache and itlb access
2471	r_dcache_xtn_req = true;
2472	r_dcache_fsm = DCACHE_XTN_IC_INVAL_VA;
2473	break;
2474
2475	case iss_t::XTN_MMU_ICACHE_PA_INV: // icache access
2476	r_dcache_xtn_req = true;
2477	r_dcache_fsm = DCACHE_XTN_IC_INVAL_PA;
2478	break;
2479
2480	case iss_t::XTN_ICACHE_FLUSH: // icache access
2481	r_dcache_xtn_req = true;
2482	r_dcache_fsm = DCACHE_XTN_IC_FLUSH;
2483	break;
2484
2485	case iss_t::XTN_SYNC: // wait until write buffer empty
2486	r_dcache_fsm = DCACHE_XTN_SYNC;
2487	break;
2488
2489	case iss_t::XTN_MMU_WORD_LO: // no cache or tlb access
2490	r_mmu_word_lo = m_dreq.wdata;
2491	m_drsp.valid = true;
2492	r_dcache_fsm = DCACHE_IDLE;
2493	break;
2494
2495	case iss_t::XTN_MMU_WORD_HI: // no cache or tlb access
2496	r_mmu_word_hi = m_dreq.wdata;
2497	m_drsp.valid = true;
2498	r_dcache_fsm = DCACHE_IDLE;
2499	break;
2500
2501	case iss_t::XTN_MMU_LL_RESET: // no cache or tlb access
2502	r_dcache_llsc_valid = false;
2503	m_drsp.valid = true;
2504	r_dcache_fsm = DCACHE_IDLE;
2505	break;
2506
2507	case iss_t::XTN_ICACHE_PREFETCH: // not implemented : no action
2508	case iss_t::XTN_DCACHE_PREFETCH: // not implemented : no action
2509	m_drsp.valid = true;
2510	r_dcache_fsm = DCACHE_IDLE;
2511	break;
2512
2513	default:
2514	r_mmu_detr = MMU_WRITE_UNDEFINED_XTN;
2515	r_mmu_dbvar = m_dreq.addr;
2516	m_drsp.valid = true;
2517	m_drsp.error = true;
2518	r_dcache_fsm = DCACHE_IDLE;
2519	break;
2520	} // end switch xtn_opcode
2521	} // end else
2522	} // end if XTN_WRITE
2523
2524	// Handling processor requests to address space (READ/WRITE/LL/SC)
2525	// The dtlb and dcache can be activated or not.
2526	// We compute the cacheability, and check processor request validity:
2527	// - If DTLB not activated : cacheability is defined by the segment table,
2528	// and there is no access rights checking.
2529	// - If DTLB activated : cacheability is defined by the C bit in the PTE,
2530	// and the U & W bits of the PTE are checked, as well as the DTLB hit.
2531	// Jumps to the TLB_MISS sub-fsm in case of dtlb miss.
2532	else
2533	{
2534	bool valid_req;
2535	bool cacheable;
2536
2537	if ( not (r_mmu_mode.read() & DATA_TLB_MASK) ) // dtlb not activated
2538	{
2539	valid_req = true;
2540
2541	if ( not (r_mmu_mode.read() & DATA_CACHE_MASK) ) cacheable = false;
2542	else cacheable = m_cacheability_table[m_dreq.addr];
2543	}
2544	else // dtlb activated
2545	{
2546	if ( tlb_hit ) // tlb hit
2547	{
2548	// cacheability
2549	if ( not (r_mmu_mode.read() & DATA_CACHE_MASK) ) cacheable = false;
2550	else cacheable = tlb_flags.c;
2551
2552	// access rights checking
2553	if ( not tlb_flags.u and (m_dreq.mode == iss_t::MODE_USER))
2554	{
2555	if ( (m_dreq.type == iss_t::DATA_READ) or
2556	(m_dreq.type == iss_t::DATA_LL) )
2557	{
2558	r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION;
2559	}
2560	else
2561	{
2562	r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION;
2563	}
2564	valid_req = false;
2565	r_mmu_dbvar = m_dreq.addr;
2566	m_drsp.valid = true;
2567	m_drsp.error = true;
2568	m_drsp.rdata = 0;
2569	#if DEBUG_DCACHE
2570	if ( m_debug_dcache_fsm )
2571	{
2572	std::cout << " <PROC " << name()
2573	<< ".DCACHE_IDLE> HIT in dtlb, but privilege violation" << std::endl;
2574	}
2575	#endif
2576	}
2577	else if ( not tlb_flags.w and
2578	((m_dreq.type == iss_t::DATA_WRITE) or
2579	(m_dreq.type == iss_t::DATA_SC)) )
2580	{
2581	r_mmu_detr = MMU_WRITE_ACCES_VIOLATION;
2582	valid_req = false;
2583	r_mmu_dbvar = m_dreq.addr;
2584	m_drsp.valid = true;
2585	m_drsp.error = true;
2586	m_drsp.rdata = 0;
2587	#if DEBUG_DCACHE
2588	if ( m_debug_dcache_fsm )
2589	{
2590	std::cout << " <PROC " << name()
2591	<< ".DCACHE_IDLE> HIT in dtlb, but writable violation" << std::endl;
2592	}
2593	#endif
2594	}
2595	else
2596	{
2597	valid_req = true;
2598	}
2599	}
2600	else // tlb miss
2601	{
2602	valid_req = false;
2603	r_dcache_tlb_vaddr = m_dreq.addr;
2604	r_dcache_tlb_ins = false;
2605	r_dcache_fsm = DCACHE_TLB_MISS;
2606	}
2607	} // end DTLB activated
2608
2609	if ( valid_req ) // processor request is valid after TLB check
2610	{
2611	r_dcache_save_cacheable = cacheable;
2612
2613	// READ request
2614	// The read requests are taken only if there is no cache update.
2615	// We request a VCI transaction to CMD FSM if miss or uncachable
2616
2617	if ( ((m_dreq.type == iss_t::DATA_READ))
2618	and not r_dcache_updt_req.read() )
2619	{
2620	if ( cacheable ) // cacheable read
2621	{
2622	if ( cache_state == CACHE_SLOT_STATE_EMPTY ) // cache miss
2623	{
2624	#ifdef INSTRUMENTATION
2625	m_cpt_dcache_miss++;
2626	#endif
2627	// request a VCI DMISS transaction
2628	r_dcache_vci_paddr = paddr;
2629	r_dcache_vci_miss_req = true;
2630	r_dcache_miss_type = PROC_MISS;
2631	r_dcache_fsm = DCACHE_MISS_SELECT;
2632	#if DEBUG_DCACHE
2633	if ( m_debug_dcache_fsm )
2634	{
2635	std::cout << " <PROC " << name()
2636	<< " DCACHE_IDLE> READ MISS in dcache"
2637	<< " : PADDR = " << std::hex << paddr << std::endl;
2638	}
2639	#endif
2640	}
2641	else if (cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup
2642	{
2643	// stalled until cleanup is acknowledged
2644	r_dcache_fsm = DCACHE_IDLE;
2645	}
2646	else // cache hit
2647	{
2648	#ifdef INSTRUMENTATION
2649	m_cpt_data_read++;
2650	#endif
2651	// returns data to processor
2652	m_drsp.valid = true;
2653	m_drsp.error = false;
2654	m_drsp.rdata = cache_rdata;
2655	#if DEBUG_DCACHE
2656	if ( m_debug_dcache_fsm )
2657	{
2658	std::cout << " <PROC " << name()
2659	<< " DCACHE_IDLE> READ HIT in dcache"
2660	<< " : PADDR = " << std::hex << paddr << std::endl;
2661	}
2662	#endif
2663	}
2664	}
2665	else // uncacheable read
2666	{
2667	r_dcache_vci_paddr = paddr;
2668	r_dcache_vci_unc_be = m_dreq.be;
2669	r_dcache_vci_unc_req = true;
2670	r_dcache_fsm = DCACHE_UNC_WAIT;
2671	#if DEBUG_DCACHE
2672	if ( m_debug_dcache_fsm )
2673	{
2674	std::cout << " <PROC " << name()
2675	<< " DCACHE_IDLE> READ UNCACHEABLE in dcache"
2676	<< " : PADDR = " << std::hex << paddr << std::endl;
2677	}
2678	#endif
2679	}
2680	} // end READ
2681
2682	// LL request (non cachable)
2683	// We request a VCI LL transaction to CMD FSM and register
2684	// the LL/SC operation in llsc buffer.
2685	else if (m_dreq.type == iss_t::DATA_LL)
2686	{
2687	// register paddr in LLSC buffer
2688	r_dcache_llsc_paddr = paddr;
2689	r_dcache_llsc_count = LLSC_TIMEOUT;
2690	r_dcache_llsc_valid = true;
2691
2692	// request an LL VCI transaction and go to DCACHE_LL_WAIT state
2693	r_dcache_vci_ll_req = true;
2694	r_dcache_vci_paddr = paddr;
2695	r_dcache_ll_rsp_count = 0;
2696	r_dcache_fsm = DCACHE_LL_WAIT;
2697
2698	}// end LL
2699
2700	// WRITE request:
2701	// If the TLB is activated and the PTE Dirty bit is not set, we stall
2702	// the processor and set the Dirty bit before handling the write request,
2703	// going to the DCACHE_DIRTY_GT_PTE state.
2704	// If we don't need to set the Dirty bit, we can acknowledge
2705	// the processor request, as the write arguments (including the
2706	// physical address) are registered in r_dcache_save registers,
2707	// and the write will be done in the P1 pipeline stage.
2708	else if ( m_dreq.type == iss_t::DATA_WRITE )
2709	{
2710	if ( (r_mmu_mode.read() & DATA_TLB_MASK )
2711	and not tlb_flags.d ) // Dirty bit must be set
2712	{
2713	// The PTE physical address is obtained from the nline value (dtlb),
2714	// and from the virtual address (word index)
2715	if ( tlb_flags.b ) // PTE1
2716	{
2717	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2718	(paddr_t)((m_dreq.addr>>19) & 0x3c);
2719	}
2720	else // PTE2
2721	{
2722	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2723	(paddr_t)((m_dreq.addr>>9) & 0x38);
2724	}
2725	r_dcache_fsm = DCACHE_DIRTY_GET_PTE;
2726	}
2727	else // Write request accepted
2728	{
2729	#ifdef INSTRUMENTATION
2730	m_cpt_data_write++;
2731	#endif
2732	// cleaning llsc buffer if address matching
2733	if ( paddr == r_dcache_llsc_paddr.read() )
2734	r_dcache_llsc_valid = false;
2735
2736	// response to processor
2737	m_drsp.valid = true;
2738
2739	// activating P1 stage
2740	wbuf_request = true;
2741	updt_request = (cache_state == CACHE_SLOT_STATE_VALID);
2742	}
2743	} // end WRITE
2744
2745	// SC request:
2746	// If the TLB is activated and the PTE Dirty bit is not set, we stall
2747	// the processor and set the Dirty bit before handling the write request,
2748	// going to the DCACHE_DIRTY_GT_PTE state.
2749	// If we don't need to set the Dirty bit, we test the llsc buffer:
2750	// If failure, we send a negative response to processor.
2751	// If success, we request a SC transaction to CMD FSM and go
2752	// to DCACHE_SC_WAIT state.
2753	// We don't check a possible write hit in dcache, as the cache update
2754	// is done by the coherence transaction induced by the SC...
2755	else if ( m_dreq.type == iss_t::DATA_SC )
2756	{
2757	if ( (r_mmu_mode.read() & DATA_TLB_MASK )
2758	and not tlb_flags.d ) // Dirty bit must be set
2759	{
2760	// The PTE physical address is obtained from the nline value (dtlb),
2761	// and the word index (virtual address)
2762	if ( tlb_flags.b ) // PTE1
2763	{
2764	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2765	(paddr_t)((m_dreq.addr>>19) & 0x3c);
2766	}
2767	else // PTE2
2768	{
2769	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2770	(paddr_t)((m_dreq.addr>>9) & 0x38);
2771	}
2772	r_dcache_fsm = DCACHE_DIRTY_GET_PTE;
2773	m_drsp.valid = false;
2774	m_drsp.error = false;
2775	m_drsp.rdata = 0;
2776	}
2777	else // SC request accepted
2778	{
2779	#ifdef INSTRUMENTATION
2780	m_cpt_data_sc++;
2781	#endif
2782	// checking local success
2783	if( r_dcache_llsc_valid.read() and
2784	(r_dcache_llsc_paddr.read() == paddr) ) // local success
2785	{
2786	// request an SC CMD and go to DCACHE_SC_WAIT state
2787	r_dcache_vci_paddr = paddr;
2788	r_dcache_vci_sc_req = true;
2789	r_dcache_vci_sc_data = m_dreq.wdata;
2790	r_dcache_fsm = DCACHE_SC_WAIT;
2791	}
2792	else // local fail
2793	{
2794	m_drsp.valid = true;
2795	m_drsp.error = false;
2796	m_drsp.rdata = 0x1;
2797	}
2798	}
2799	} // end SC
2800	} // end valid_req
2801	} // end if read/write/ll/sc request
2802	} // end processor request
2803
2804	// itlb miss request
2805	else if ( r_icache_tlb_miss_req.read() and not wbuf_write_miss )
2806	{
2807	r_dcache_tlb_ins = true;
2808	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
2809	r_dcache_fsm = DCACHE_TLB_MISS;
2810	}
2811
2812	// Computing requests for P1 stage : r_dcache_wbuf_req & r_dcache_updt_req
2813	r_dcache_updt_req = updt_request;
2814	r_dcache_wbuf_req = wbuf_request or
2815	(r_dcache_wbuf_req.read() and wbuf_write_miss);
2816	break;
2817	}
2818	/////////////////////
2819	case DCACHE_TLB_MISS: // This is the entry point for the sub-fsm handling all tlb miss.
2820	// Input arguments are:
2821	// - r_dcache_tlb_vaddr
2822	// - r_dcache_tlb_ins (true when itlb miss)
2823	// The sub-fsm access the dcache to find the missing TLB entry,
2824	// and activates the cache miss procedure in case of miss.
2825	// It bypass the first level page table access if possible.
2826	// It uses atomic access to update the R/L access bits
2827	// in the page table if required.
2828	// It directly updates the itlb or dtlb, and writes into the
2829	// r_mmu_ins_* or r_mmu_data* error reporting registers.
2830	{
2831	uint32_t ptba = 0;
2832	bool bypass;
2833	paddr_t pte_paddr;
2834
2835	// evaluate bypass in order to skip first level page table access
2836	if ( r_dcache_tlb_ins.read() ) // itlb miss
2837	{
2838	bypass = r_itlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba);
2839	}
2840	else // dtlb miss
2841	{
2842	bypass = r_dtlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba);
2843	}
2844
2845	if ( not bypass ) // Try to read PTE1/PTD1 in dcache
2846	{
2847	pte_paddr = (paddr_t)r_mmu_ptpr.read() << (INDEX1_NBITS+2) \|
2848	(paddr_t)((r_dcache_tlb_vaddr.read() >> PAGE_M_NBITS) << 2);
2849	r_dcache_tlb_paddr = pte_paddr;
2850	r_dcache_fsm = DCACHE_TLB_PTE1_GET;
2851	}
2852	else // Try to read PTE2 in dcache
2853	{
2854	pte_paddr = (paddr_t)ptba << PAGE_K_NBITS \|
2855	(paddr_t)(r_dcache_tlb_vaddr.read()&PTD_ID2_MASK)>>(PAGE_K_NBITS-3);
2856	r_dcache_tlb_paddr = pte_paddr;
2857	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
2858	}
2859
2860	#if DEBUG_DCACHE
2861	if ( m_debug_dcache_fsm )
2862	{
2863	if ( r_dcache_tlb_ins.read() )
2864	{
2865	std::cout << " <PROC " << name() << ".DCACHE_TLB_MISS> ITLB miss";
2866	}
2867	else
2868	{
2869	std::cout << " <PROC " << name() << ".DCACHE_TLB_MISS> DTLB miss";
2870	}
2871	std::cout << " / VADDR = " << std::hex << r_dcache_tlb_vaddr.read()
2872	<< " / BYPASS = " << bypass
2873	<< " / PTE_ADR = " << pte_paddr << std::endl;
2874	}
2875	#endif
2876
2877	break;
2878	}
2879	/////////////////////////
2880	case DCACHE_TLB_PTE1_GET: // try to read a PT1 entry in dcache
2881	{
2882	// coherence request (from CC_RECEIVE FSM)
2883	if ( r_cc_receive_dcache_req.read() )
2884	{
2885	r_dcache_fsm = DCACHE_CC_CHECK;
2886	r_dcache_fsm_cc_save = r_dcache_fsm.read();
2887	break;
2888	}
2889
2890	uint32_t entry;
2891	size_t way;
2892	size_t set;
2893	size_t word;
2894	int cache_state;
2895	r_dcache.read( r_dcache_tlb_paddr.read(),
2896	&entry,
2897	&way,
2898	&set,
2899	&word,
2900	&cache_state );
2901	#ifdef INSTRUMENTATION
2902	m_cpt_dcache_data_read++;
2903	m_cpt_dcache_dir_read++;
2904	#endif
2905	if ( cache_state == CACHE_SLOT_STATE_VALID ) // hit in dcache
2906	{
2907	if ( not (entry & PTE_V_MASK) ) // unmapped
2908	{
2909	if ( r_dcache_tlb_ins.read() )
2910	{
2911	r_mmu_ietr = MMU_READ_PT1_UNMAPPED;
2912	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
2913	r_icache_tlb_miss_req = false;
2914	r_icache_tlb_rsp_error = true;
2915	}
2916	else
2917	{
2918	r_mmu_detr = MMU_READ_PT1_UNMAPPED;
2919	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
2920	m_drsp.valid = true;
2921	m_drsp.error = true;
2922	}
2923	r_dcache_fsm = DCACHE_IDLE;
2924
2925	#if DEBUG_DCACHE
2926	if ( m_debug_dcache_fsm )
2927	{
2928	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_GET> HIT in dcache, but unmapped"
2929	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
2930	<< std::dec << " / way = " << way
2931	<< std::dec << " / set = " << set
2932	<< std::dec << " / word = " << word
2933	<< std::hex << " / PTE1 = " << entry << std::endl;
2934	}
2935	#endif
2936
2937	}
2938	else if( entry & PTE_T_MASK ) // PTD : me must access PT2
2939	{
2940	// mark the cache line ac containing a PTD
2941	r_dcache_contains_ptd[m_dcache_sets*way+set] = true;
2942
2943	// register bypass
2944	if ( r_dcache_tlb_ins.read() ) // itlb
2945	{
2946	r_itlb.set_bypass(r_dcache_tlb_vaddr.read(),
2947	entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1),
2948	r_dcache_tlb_paddr.read() / (m_icache_words<<2) );
2949	}
2950	else // dtlb
2951	{
2952	r_dtlb.set_bypass(r_dcache_tlb_vaddr.read(),
2953	entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1),
2954	r_dcache_tlb_paddr.read() / (m_dcache_words<<2) );
2955	}
2956	r_dcache_tlb_paddr =
2957	(paddr_t)(entry & ((1<<(m_paddr_nbits-PAGE_K_NBITS))-1)) << PAGE_K_NBITS \|
2958	(paddr_t)(((r_dcache_tlb_vaddr.read() & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3);
2959	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
2960
2961	#if DEBUG_DCACHE
2962	if ( m_debug_dcache_fsm )
2963	{
2964	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_GET> HIT in dcache"
2965	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
2966	<< std::dec << " / way = " << way
2967	<< std::dec << " / set = " << set
2968	<< std::dec << " / word = " << word
2969	<< std::hex << " / PTD = " << entry << std::endl;
2970	}
2971	#endif
2972	}
2973	else // PTE1 : we must update the TLB
2974	{
2975	r_dcache_in_tlb[m_icache_sets*way+set] = true;
2976	r_dcache_tlb_pte_flags = entry;
2977	r_dcache_tlb_cache_way = way;
2978	r_dcache_tlb_cache_set = set;
2979	r_dcache_tlb_cache_word = word;
2980	r_dcache_fsm = DCACHE_TLB_PTE1_SELECT;
2981
2982	#if DEBUG_DCACHE
2983	if ( m_debug_dcache_fsm )
2984	{
2985	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_GET> HIT in dcache"
2986	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
2987	<< std::dec << " / way = " << way
2988	<< std::dec << " / set = " << set
2989	<< std::dec << " / word = " << word
2990	<< std::hex << " / PTE1 = " << entry << std::endl;
2991	}
2992	#endif
2993	}
2994	}
2995	else if ( cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup
2996	{
2997	// stalled until cleanup is acknowledged
2998	r_dcache_fsm = DCACHE_TLB_PTE1_GET;
2999	}
3000	else // we must load the missing cache line in dcache
3001	{
3002	r_dcache_vci_miss_req = true;
3003	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
3004	r_dcache_save_paddr = r_dcache_tlb_paddr.read();
3005	r_dcache_miss_type = PTE1_MISS;
3006	r_dcache_fsm = DCACHE_MISS_SELECT;
3007
3008	#if DEBUG_DCACHE
3009	if ( m_debug_dcache_fsm )
3010	{
3011	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_GET> MISS in dcache:"
3012	<< " PTE1 address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
3013	}
3014	#endif
3015	}
3016	break;
3017	}
3018	////////////////////////////
3019	case DCACHE_TLB_PTE1_SELECT: // select a slot for PTE1
3020	{
3021	size_t way;
3022	size_t set;
3023
3024	if ( r_dcache_tlb_ins.read() )
3025	{
3026	r_itlb.select( r_dcache_tlb_vaddr.read(),
3027	true, // PTE1
3028	&way,
3029	&set );
3030	#ifdef INSTRUMENTATION
3031	m_cpt_itlb_read++;
3032	#endif
3033	}
3034	else
3035	{
3036	r_dtlb.select( r_dcache_tlb_vaddr.read(),
3037	true, // PTE1
3038	&way,
3039	&set );
3040	#ifdef INSTRUMENTATION
3041	m_cpt_dtlb_read++;
3042	#endif
3043	}
3044	r_dcache_tlb_way = way;
3045	r_dcache_tlb_set = set;
3046	r_dcache_fsm = DCACHE_TLB_PTE1_UPDT;
3047
3048	#if DEBUG_DCACHE
3049	if ( m_debug_dcache_fsm )
3050	{
3051	if ( r_dcache_tlb_ins.read() )
3052	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_SELECT> Select a slot in ITLB:";
3053	else
3054	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_SELECT> Select a slot in DTLB:";
3055	std::cout << " way = " << std::dec << way
3056	<< " / set = " << set << std::endl;
3057	}
3058	#endif
3059	break;
3060	}
3061	//////////////////////////
3062	case DCACHE_TLB_PTE1_UPDT: // write a new PTE1 in tlb after testing the L/R bit
3063	// - if L/R bit already set, exit the sub-fsm.
3064	// - if not, we update the page table but we dont write
3065	// neither in DCACHE, nor in TLB, as this will be done by
3066	// the coherence mechanism.
3067	{
3068	paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2);
3069	uint32_t pte = r_dcache_tlb_pte_flags.read();
3070	bool pt_updt = false;
3071	bool local = true;
3072
3073	// We should compute the access locality:
3074	// The PPN MSB bits define the destination cluster index.
3075	// The m_srcid MSB bits define the source cluster index.
3076	// The number of bits to compare depends on the number of clusters,
3077	// and can be obtained in the mapping table.
3078	// As long as this computation is not done, all access are local.
3079
3080	if ( local ) // local access
3081	{
3082	if ( not ((pte & PTE_L_MASK) == PTE_L_MASK) ) // we must set the L bit
3083	{
3084	pt_updt = true;
3085	r_dcache_vci_cas_old = pte;
3086	r_dcache_vci_cas_new = pte \| PTE_L_MASK;
3087	pte = pte \| PTE_L_MASK;
3088	r_dcache_tlb_pte_flags = pte;
3089	}
3090	}
3091	else // remote access
3092	{
3093	if ( not ((pte & PTE_R_MASK) == PTE_R_MASK) ) // we must set the R bit
3094	{
3095	pt_updt = true;
3096	r_dcache_vci_cas_old = pte;
3097	r_dcache_vci_cas_new = pte \| PTE_R_MASK;
3098	pte = pte \| PTE_R_MASK;
3099	r_dcache_tlb_pte_flags = pte;
3100	}
3101	}
3102
3103	if ( not pt_updt ) // update TLB and return
3104	{
3105	if ( r_dcache_tlb_ins.read() )
3106	{
3107	r_itlb.write( true, // 2M page
3108	pte,
3109	0, // argument unused for a PTE1
3110	r_dcache_tlb_vaddr.read(),
3111	r_dcache_tlb_way.read(),
3112	r_dcache_tlb_set.read(),
3113	nline );
3114	#ifdef INSTRUMENTATION
3115	m_cpt_itlb_write++;
3116	#endif
3117
3118	#if DEBUG_DCACHE
3119	if ( m_debug_dcache_fsm )
3120	{
3121	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_UPDT> write PTE1 in ITLB";
3122	std::cout << " / set = " << std::dec << r_dcache_tlb_set.read()
3123	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3124	r_itlb.printTrace();
3125	}
3126	#endif
3127	}
3128	else
3129	{
3130	r_dtlb.write( true, // 2M page
3131	pte,
3132	0, // argument unused for a PTE1
3133	r_dcache_tlb_vaddr.read(),
3134	r_dcache_tlb_way.read(),
3135	r_dcache_tlb_set.read(),
3136	nline );
3137	#ifdef INSTRUMENTATION
3138	m_cpt_dtlb_write++;
3139	#endif
3140
3141	#if DEBUG_DCACHE
3142	if ( m_debug_dcache_fsm )
3143	{
3144	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_UPDT> write PTE1 in DTLB";
3145	std::cout << " / set = " << std::dec << r_dcache_tlb_set.read()
3146	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3147	r_dtlb.printTrace();
3148	}
3149	#endif
3150	}
3151	r_dcache_fsm = DCACHE_TLB_RETURN;
3152	}
3153	else // update page table but not TLB
3154	{
3155	r_dcache_fsm = DCACHE_TLB_LR_UPDT;
3156
3157	#if DEBUG_DCACHE
3158	if ( m_debug_dcache_fsm )
3159	{
3160	std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_UPDT> L/R bit update required"
3161	<< std::endl;
3162	}
3163	#endif
3164	}
3165	break;
3166	}
3167	/////////////////////////
3168	case DCACHE_TLB_PTE2_GET: // Try to get a PTE2 (64 bits) in the dcache
3169	{
3170	// coherence request (from CC_RECEIVE FSM)
3171	if ( r_cc_receive_dcache_req.read() )
3172	{
3173	r_dcache_fsm = DCACHE_CC_CHECK;
3174	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3175	break;
3176	}
3177
3178	uint32_t pte_flags;
3179	uint32_t pte_ppn;
3180	size_t way;
3181	size_t set;
3182	size_t word;
3183	int cache_state;
3184
3185	r_dcache.read( r_dcache_tlb_paddr.read(),
3186	&pte_flags,
3187	&pte_ppn,
3188	&way,
3189	&set,
3190	&word,
3191	&cache_state );
3192	#ifdef INSTRUMENTATION
3193	m_cpt_dcache_data_read++;
3194	m_cpt_dcache_dir_read++;
3195	#endif
3196	if ( cache_state == CACHE_SLOT_STATE_VALID ) // hit in dcache
3197	{
3198	if ( not (pte_flags & PTE_V_MASK) ) // unmapped
3199	{
3200	if ( r_dcache_tlb_ins.read() )
3201	{
3202	r_mmu_ietr = MMU_READ_PT2_UNMAPPED;
3203	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3204	r_icache_tlb_miss_req = false;
3205	r_icache_tlb_rsp_error = true;
3206	}
3207	else
3208	{
3209	r_mmu_detr = MMU_READ_PT2_UNMAPPED;
3210	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3211	m_drsp.valid = true;
3212	m_drsp.error = true;
3213	}
3214	r_dcache_fsm = DCACHE_IDLE;
3215
3216	#if DEBUG_DCACHE
3217	if ( m_debug_dcache_fsm )
3218	{
3219	std::cout << " <PROC " << name()
3220	<< " DCACHE_TLB_PTE2_GET> HIT in dcache, but PTE unmapped"
3221	<< " PTE_FLAGS = " << std::hex << pte_flags
3222	<< " PTE_PPN = " << std::hex << pte_ppn << std::endl;
3223	}
3224	#endif
3225	}
3226	else // mapped : we must update the TLB
3227	{
3228	r_dcache_in_tlb[m_dcache_sets*way+set] = true;
3229	r_dcache_tlb_pte_flags = pte_flags;
3230	r_dcache_tlb_pte_ppn = pte_ppn;
3231	r_dcache_tlb_cache_way = way;
3232	r_dcache_tlb_cache_set = set;
3233	r_dcache_tlb_cache_word = word;
3234	r_dcache_fsm = DCACHE_TLB_PTE2_SELECT;
3235
3236	#if DEBUG_DCACHE
3237	if ( m_debug_dcache_fsm )
3238	{
3239	std::cout << " <PROC " << name()
3240	<< " DCACHE_TLB_PTE2_GET> HIT in dcache:"
3241	<< " PTE_FLAGS = " << std::hex << pte_flags
3242	<< " PTE_PPN = " << std::hex << pte_ppn << std::endl;
3243	}
3244	#endif
3245	}
3246	}
3247	else if ( cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup
3248	{
3249	// stalled until cleanup is acknowledged
3250	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
3251
3252	#if DEBUG_DCACHE
3253	if ( m_debug_dcache_fsm )
3254	{
3255	std::cout << " <PROC " << name()
3256	<< " DCACHE_TLB_PTE2_GET> ZOMBI in dcache: waiting cleanup ack"
3257	<< std::endl;
3258	}
3259	#endif
3260	}
3261	else // we must load the missing cache line in dcache
3262	{
3263	r_dcache_fsm = DCACHE_MISS_SELECT;
3264	r_dcache_vci_miss_req = true;
3265	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
3266	r_dcache_save_paddr = r_dcache_tlb_paddr.read();
3267	r_dcache_miss_type = PTE2_MISS;
3268
3269	#if DEBUG_DCACHE
3270	if ( m_debug_dcache_fsm )
3271	{
3272	std::cout << " <PROC " << name()
3273	<< " DCACHE_TLB_PTE2_GET> MISS in dcache:"
3274	<< " PTE address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
3275	}
3276	#endif
3277	}
3278	break;
3279	}
3280	////////////////////////////
3281	case DCACHE_TLB_PTE2_SELECT: // select a slot for PTE2
3282	{
3283	size_t way;
3284	size_t set;
3285
3286	if ( r_dcache_tlb_ins.read() )
3287	{
3288	r_itlb.select( r_dcache_tlb_vaddr.read(),
3289	false, // PTE2
3290	&way,
3291	&set );
3292	#ifdef INSTRUMENTATION
3293	m_cpt_itlb_read++;
3294	#endif
3295	}
3296	else
3297	{
3298	r_dtlb.select( r_dcache_tlb_vaddr.read(),
3299	false, // PTE2
3300	&way,
3301	&set );
3302	#ifdef INSTRUMENTATION
3303	m_cpt_dtlb_read++;
3304	#endif
3305	}
3306
3307	#if DEBUG_DCACHE
3308	if ( m_debug_dcache_fsm )
3309	{
3310	if ( r_dcache_tlb_ins.read() )
3311	std::cout << " <PROC " << name()
3312	<< " DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB:";
3313	else
3314	std::cout << " <PROC " << name()
3315	<< " DCACHE_TLB_PTE2_SELECT> Select a slot in DTLB:";
3316	std::cout << " way = " << std::dec << way
3317	<< " / set = " << set << std::endl;
3318	}
3319	#endif
3320	r_dcache_tlb_way = way;
3321	r_dcache_tlb_set = set;
3322	r_dcache_fsm = DCACHE_TLB_PTE2_UPDT;
3323	break;
3324	}
3325	//////////////////////////
3326	case DCACHE_TLB_PTE2_UPDT: // write a new PTE2 in tlb after testing the L/R bit
3327	// - if L/R bit already set, exit the sub-fsm.
3328	// - if not, we update the page table but we dont write
3329	// neither in DCACHE, nor in TLB, as this will be done by
3330	// the coherence mechanism.
3331	{
3332	paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2);
3333	uint32_t pte_flags = r_dcache_tlb_pte_flags.read();
3334	uint32_t pte_ppn = r_dcache_tlb_pte_ppn.read();
3335	bool pt_updt = false;
3336	bool local = true;
3337
3338	// We should compute the access locality:
3339	// The PPN MSB bits define the destination cluster index.
3340	// The m_srcid MSB bits define the source cluster index.
3341	// The number of bits to compare depends on the number of clusters,
3342	// and can be obtained in the mapping table.
3343	// As long as this computation is not done, all access are local.
3344
3345	if ( local ) // local access
3346	{
3347	if ( not ((pte_flags & PTE_L_MASK) == PTE_L_MASK) ) // we must set the L bit
3348	{
3349	pt_updt = true;
3350	r_dcache_vci_cas_old = pte_flags;
3351	r_dcache_vci_cas_new = pte_flags \| PTE_L_MASK;
3352	pte_flags = pte_flags \| PTE_L_MASK;
3353	r_dcache_tlb_pte_flags = pte_flags;
3354	}
3355	}
3356	else // remote access
3357	{
3358	if ( not ((pte_flags & PTE_R_MASK) == PTE_R_MASK) ) // we must set the R bit
3359	{
3360	pt_updt = true;
3361	r_dcache_vci_cas_old = pte_flags;
3362	r_dcache_vci_cas_new = pte_flags \| PTE_R_MASK;
3363	pte_flags = pte_flags \| PTE_R_MASK;
3364	r_dcache_tlb_pte_flags = pte_flags;
3365	}
3366	}
3367
3368	if ( not pt_updt ) // update TLB
3369	{
3370	if ( r_dcache_tlb_ins.read() )
3371	{
3372	r_itlb.write( false, // 4K page
3373	pte_flags,
3374	pte_ppn,
3375	r_dcache_tlb_vaddr.read(),
3376	r_dcache_tlb_way.read(),
3377	r_dcache_tlb_set.read(),
3378	nline );
3379	#ifdef INSTRUMENTATION
3380	m_cpt_itlb_write++;
3381	#endif
3382
3383	#if DEBUG_DCACHE
3384	if ( m_debug_dcache_fsm )
3385	{
3386	std::cout << " <PROC " << name()
3387	<< " DCACHE_TLB_PTE2_UPDT> write PTE2 in ITLB"
3388	<< " / set = " << std::dec << r_dcache_tlb_set.read()
3389	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3390	r_itlb.printTrace();
3391	}
3392	#endif
3393	}
3394	else
3395	{
3396	r_dtlb.write( false, // 4K page
3397	pte_flags,
3398	pte_ppn,
3399	r_dcache_tlb_vaddr.read(),
3400	r_dcache_tlb_way.read(),
3401	r_dcache_tlb_set.read(),
3402	nline );
3403	#ifdef INSTRUMENTATION
3404	m_cpt_dtlb_write++;
3405	#endif
3406
3407	#if DEBUG_DCACHE
3408	if ( m_debug_dcache_fsm )
3409	{
3410	std::cout << " <PROC " << name()
3411	<< " DCACHE_TLB_PTE2_UPDT> write PTE2 in DTLB"
3412	<< " / set = " << std::dec << r_dcache_tlb_set.read()
3413	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3414	r_dtlb.printTrace();
3415	}
3416	#endif
3417
3418	}
3419	r_dcache_fsm = DCACHE_TLB_RETURN;
3420	}
3421	else // update page table but not TLB
3422	{
3423	r_dcache_fsm = DCACHE_TLB_LR_UPDT; // dcache and page table update
3424
3425	#if DEBUG_DCACHE
3426	if ( m_debug_dcache_fsm )
3427	{
3428	std::cout << " <PROC " << name()
3429	<< " DCACHE_TLB_PTE2_UPDT> L/R bit update required" << std::endl;
3430	}
3431	#endif
3432	}
3433	break;
3434	}
3435	////////////////////////
3436	case DCACHE_TLB_LR_UPDT: // request a CAS transaction to update L/R bit
3437	{
3438	#if DEBUG_DCACHE
3439	if ( m_debug_dcache_fsm )
3440	{
3441	std::cout << " <PROC " << name()
3442	<< " DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit" << std::endl;
3443	}
3444	#endif
3445	// r_dcache_vci_cas_old & r_dcache_vci_cas_new registers are already set
3446	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
3447
3448	// checking llsc reservation buffer
3449	if ( r_dcache_llsc_paddr.read() == r_dcache_tlb_paddr.read() )
3450	r_dcache_llsc_valid = false;
3451
3452	// request a CAS CMD and go to DCACHE_TLB_LR_WAIT state
3453	r_dcache_vci_cas_req = true;
3454	r_dcache_fsm = DCACHE_TLB_LR_WAIT;
3455	break;
3456	}
3457	////////////////////////
3458	case DCACHE_TLB_LR_WAIT: // Waiting the response to SC transaction for DIRTY bit.
3459	// We consume the response in rsp FIFO,
3460	// and exit the sub-fsm, but we don't
3461	// analyse the response, because we don't
3462	// care if the L/R bit update is not done.
3463	// We must take the coherence requests because
3464	// there is a risk of dead-lock
3465
3466	{
3467	// coherence request (from CC_RECEIVE FSM)
3468	if ( r_cc_receive_dcache_req.read() )
3469	{
3470	r_dcache_fsm = DCACHE_CC_CHECK;
3471	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3472	break;
3473	}
3474
3475	if ( r_vci_rsp_data_error.read() ) // bus error
3476	{
3477	std::cout << "BUS ERROR in DCACHE_TLB_LR_WAIT state" << std::endl;
3478	std::cout << "This should not happen in this state" << std::endl;
3479	exit(0);
3480	}
3481	else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
3482	{
3483	#if DEBUG_DCACHE
3484	if ( m_debug_dcache_fsm )
3485	{
3486	std::cout << " <PROC " << name()
3487	<< " DCACHE_TLB_LR_WAIT> SC response received" << std::endl;
3488	}
3489	#endif
3490	vci_rsp_fifo_dcache_get = true;
3491	r_dcache_fsm = DCACHE_TLB_RETURN;
3492	}
3493	break;
3494	}
3495	///////////////////////
3496	case DCACHE_TLB_RETURN: // return to caller depending on tlb miss type
3497	{
3498	#if DEBUG_DCACHE
3499	if ( m_debug_dcache_fsm )
3500	{
3501	std::cout << " <PROC " << name()
3502	<< " DCACHE_TLB_RETURN> TLB MISS completed" << std::endl;
3503	}
3504	#endif
3505	if ( r_dcache_tlb_ins.read() ) r_icache_tlb_miss_req = false;
3506	r_dcache_fsm = DCACHE_IDLE;
3507	break;
3508	}
3509	///////////////////////
3510	case DCACHE_XTN_SWITCH: // The r_ptpr registers must be written,
3511	// and both itlb and dtlb must be flushed.
3512	// Caution : the itlb miss requests must be taken
3513	// to avoid dead-lock in case of simultaneous ITLB miss
3514	{
3515	// itlb miss request
3516	if ( r_icache_tlb_miss_req.read() )
3517	{
3518	r_dcache_tlb_ins = true;
3519	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
3520	r_dcache_fsm = DCACHE_TLB_MISS;
3521	break;
3522	}
3523
3524	if ( not r_dcache_xtn_req.read() )
3525	{
3526	r_dtlb.flush();
3527	r_mmu_ptpr = m_dreq.wdata;
3528	r_dcache_fsm = DCACHE_IDLE;
3529	m_drsp.valid = true;
3530	}
3531	break;
3532	}
3533	/////////////////////
3534	case DCACHE_XTN_SYNC: // waiting until write buffer empty
3535	// The coherence request must be taken
3536	// as there is a risk of dead-lock
3537	{
3538	// coherence request (from CC_RECEIVE FSM)
3539	if ( r_cc_receive_dcache_req.read() )
3540	{
3541	r_dcache_fsm = DCACHE_CC_CHECK;
3542	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3543	}
3544
3545	if ( r_wbuf.empty() )
3546	{
3547	m_drsp.valid = true;
3548	r_dcache_fsm = DCACHE_IDLE;
3549	}
3550	break;
3551	}
3552	////////////////////////
3553	case DCACHE_XTN_IC_FLUSH: // Waiting completion of an XTN request to the ICACHE FSM
3554	case DCACHE_XTN_IC_INVAL_VA: // Caution : the itlb miss requests must be taken
3555	case DCACHE_XTN_IC_INVAL_PA: // because the XTN_ICACHE_INVAL request to icache
3556	case DCACHE_XTN_IT_INVAL: // can generate an itlb miss,
3557	// and because it can exist a simultaneous ITLB miss
3558	{
3559	// coherence request (from CC_RECEIVE FSM)
3560	if ( r_cc_receive_dcache_req.read() )
3561	{
3562	r_dcache_fsm = DCACHE_CC_CHECK;
3563	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3564	break;
3565	}
3566
3567	// itlb miss request
3568	if ( r_icache_tlb_miss_req.read() )
3569	{
3570	r_dcache_tlb_ins = true;
3571	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
3572	r_dcache_fsm = DCACHE_TLB_MISS;
3573	break;
3574	}
3575
3576	// test if XTN request to icache completed
3577	if ( not r_dcache_xtn_req.read() )
3578	{
3579	r_dcache_fsm = DCACHE_IDLE;
3580	m_drsp.valid = true;
3581	}
3582	break;
3583	}
3584	/////////////////////////
3585	case DCACHE_XTN_DC_FLUSH: // Invalidate sequencially all cache lines, using
3586	// r_dcache_flush_count as a slot counter,
3587	// looping in this state until all slots have been visited.
3588	// It can require two cycles per slot:
3589	// We test here the slot state, and make the actual inval
3590	// (if line is valid) in DCACHE_XTN_DC_FLUSH_GO state.
3591	// A cleanup request is generated for each valid line.
3592	// returns to IDLE and flush TLBs when last slot
3593	{
3594	// coherence request (from CC_RECEIVE FSM)
3595	if ( r_cc_receive_dcache_req.read() )
3596	{
3597	r_dcache_fsm = DCACHE_CC_CHECK;
3598	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3599	break;
3600	}
3601
3602	if ( not r_dcache_cc_send_req.read() ) // blocked until previous cc_send request is sent
3603	{
3604	int state;
3605	uint32_t tag;
3606	size_t way = r_dcache_flush_count.read()/m_dcache_sets;
3607	size_t set = r_dcache_flush_count.read()%m_dcache_sets;
3608
3609	#ifdef INSTRUMENTATION
3610	m_cpt_dcache_dir_read++;
3611	#endif
3612	r_dcache.read_dir( way,
3613	set,
3614	&tag,
3615	&state );
3616
3617	if ( state == CACHE_SLOT_STATE_VALID ) // inval required
3618	{
3619	// request cleanup
3620	r_dcache_cc_send_req = true;
3621	r_dcache_cc_send_nline = tag * m_dcache_sets + set;
3622	r_dcache_cc_send_way = way;
3623	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
3624
3625	// goes to DCACHE_XTN_DC_FLUSH_GO to inval directory
3626	r_dcache_miss_way = way;
3627	r_dcache_miss_set = set;
3628	r_dcache_fsm = DCACHE_XTN_DC_FLUSH_GO;
3629	}
3630	else if ( r_dcache_flush_count.read() ==
3631	(m_dcache_sets*m_dcache_ways - 1) ) // last slot
3632	{
3633	r_dtlb.reset();
3634	r_itlb.reset();
3635	r_dcache_fsm = DCACHE_IDLE;
3636	m_drsp.valid = true;
3637	}
3638
3639	// saturation counter
3640	if ( r_dcache_flush_count.read() < (m_dcache_sets*m_dcache_ways - 1) )
3641	r_dcache_flush_count = r_dcache_flush_count.read() + 1;
3642	}
3643	break;
3644	}
3645	////////////////////////////
3646	case DCACHE_XTN_DC_FLUSH_GO: // Switch the cache slot to ZOMBI state
3647	// and reset directory extension.
3648	// returns to IDLE and flush TLBs when last slot
3649	{
3650	size_t way = r_dcache_miss_way.read();
3651	size_t set = r_dcache_miss_set.read();
3652
3653	r_dcache_in_tlb[m_dcache_sets*way+set] = false;
3654	r_dcache_contains_ptd[m_dcache_sets*way+set] = false;
3655
3656	#ifdef INSTRUMENTATION
3657	m_cpt_dcache_dir_write++;
3658	#endif
3659	r_dcache.write_dir( way,
3660	set,
3661	CACHE_SLOT_STATE_ZOMBI );
3662
3663	if ( r_dcache_flush_count.read() ==
3664	(m_dcache_sets*m_dcache_ways - 1) ) // last slot
3665	{
3666	r_dtlb.reset();
3667	r_itlb.reset();
3668	r_dcache_fsm = DCACHE_IDLE;
3669	m_drsp.valid = true;
3670	}
3671	else
3672	{
3673	r_dcache_fsm = DCACHE_XTN_DC_FLUSH;
3674	}
3675	break;
3676	}
3677	/////////////////////////
3678	case DCACHE_XTN_DT_INVAL: // handling processor XTN_DTLB_INVAL request
3679	{
3680	r_dtlb.inval(r_dcache_save_wdata.read());
3681	r_dcache_fsm = DCACHE_IDLE;
3682	m_drsp.valid = true;
3683	break;
3684	}
3685	////////////////////////////
3686	case DCACHE_XTN_DC_INVAL_VA: // selective cache line invalidate with virtual address
3687	// requires 3 cycles: access tlb, read cache, inval cache
3688	// we compute the physical address in this state
3689	{
3690	paddr_t paddr;
3691	bool hit;
3692
3693	if ( r_mmu_mode.read() & DATA_TLB_MASK ) // dtlb activated
3694	{
3695
3696	#ifdef INSTRUMENTATION
3697	m_cpt_dtlb_read++;
3698	#endif
3699	hit = r_dtlb.translate( r_dcache_save_wdata.read(),
3700	&paddr );
3701	}
3702	else // dtlb not activated
3703	{
3704	paddr = (paddr_t)r_dcache_save_wdata.read();
3705	hit = true;
3706	}
3707
3708	if ( hit ) // tlb hit
3709	{
3710	r_dcache_save_paddr = paddr;
3711	r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA;
3712	}
3713	else // tlb miss
3714	{
3715
3716	#ifdef INSTRUMENTATION
3717	m_cpt_dtlb_miss++;
3718	#endif
3719	r_dcache_tlb_ins = false; // dtlb
3720	r_dcache_tlb_vaddr = r_dcache_save_wdata.read();
3721	r_dcache_fsm = DCACHE_TLB_MISS;
3722	}
3723
3724	#if DEBUG_DCACHE
3725	if ( m_debug_dcache_fsm )
3726	{
3727	std::cout << " <PROC " << name()
3728	<< " DCACHE_XTN_DC_INVAL_VA> Compute physical address" << std::hex
3729	<< " / VADDR = " << r_dcache_save_wdata.read()
3730	<< " / PADDR = " << paddr << std::endl;
3731	}
3732	#endif
3733
3734	break;
3735	}
3736	////////////////////////////
3737	case DCACHE_XTN_DC_INVAL_PA: // selective cache line invalidate with physical address
3738	// requires 2 cycles: read cache / inval cache
3739	// In this state we read dcache.
3740	{
3741	size_t way;
3742	size_t set;
3743	size_t word;
3744	int state;
3745
3746	#ifdef INSTRUMENTATION
3747	m_cpt_dcache_dir_read++;
3748	#endif
3749	r_dcache.read_dir( r_dcache_save_paddr.read(),
3750	&state,
3751	&way,
3752	&set,
3753	&word );
3754
3755	if ( state == CACHE_SLOT_STATE_VALID ) // inval to be done
3756	{
3757	r_dcache_xtn_way = way;
3758	r_dcache_xtn_set = set;
3759	r_dcache_fsm = DCACHE_XTN_DC_INVAL_GO;
3760	}
3761	else // miss : nothing to do
3762	{
3763	r_dcache_fsm = DCACHE_IDLE;
3764	m_drsp.valid = true;
3765	}
3766
3767	#if DEBUG_DCACHE
3768	if ( m_debug_dcache_fsm )
3769	{
3770	std::cout << " <PROC " << name()
3771	<< " DCACHE_XTN_DC_INVAL_PA> Test hit in dcache" << std::hex
3772	<< " / PADDR = " << r_dcache_save_paddr.read() << std::dec
3773	<< " / HIT = " << (state == CACHE_SLOT_STATE_VALID)
3774	<< " / SET = " << set
3775	<< " / WAY = " << way << std::endl;
3776	}
3777	#endif
3778	break;
3779	}
3780	////////////////////////////
3781	case DCACHE_XTN_DC_INVAL_GO: // In this state, we invalidate the cache line
3782	// Blocked if previous cleanup not completed
3783	// Test if itlb or dtlb inval is required
3784	{
3785	if ( not r_dcache_cc_send_req.read() ) // blocked until previous cc_send request is sent
3786	{
3787	size_t way = r_dcache_xtn_way.read();
3788	size_t set = r_dcache_xtn_set.read();
3789	paddr_t nline = r_dcache_save_paddr.read() / (m_dcache_words<<2);
3790
3791	#ifdef INSTRUMENTATION
3792	m_cpt_dcache_dir_write++;
3793	#endif
3794	r_dcache.write_dir( way,
3795	set,
3796	CACHE_SLOT_STATE_ZOMBI );
3797
3798	// request cleanup
3799	r_dcache_cc_send_req = true;
3800	r_dcache_cc_send_nline = nline;
3801	r_dcache_cc_send_way = way;
3802	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
3803
3804	// possible itlb & dtlb invalidate
3805	if ( r_dcache_in_tlb[way*m_dcache_sets+set] )
3806	{
3807	r_dcache_tlb_inval_line = nline;
3808	r_dcache_tlb_inval_set = 0;
3809	r_dcache_fsm_scan_save = DCACHE_XTN_DC_INVAL_END;
3810	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
3811	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
3812	}
3813	else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] )
3814	{
3815	r_itlb.reset();
3816	r_dtlb.reset();
3817	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
3818	r_dcache_fsm = DCACHE_IDLE;
3819	m_drsp.valid = true;
3820	}
3821	else
3822	{
3823	r_dcache_fsm = DCACHE_IDLE;
3824	m_drsp.valid = true;
3825	}
3826
3827	#if DEBUG_DCACHE
3828	if ( m_debug_dcache_fsm )
3829	{
3830	std::cout << " <PROC " << name()
3831	<< " DCACHE_XTN_DC_INVAL_GO> Actual dcache inval" << std::hex
3832	<< " / PADDR = " << r_dcache_save_paddr.read() << std::endl;
3833	}
3834	#endif
3835	}
3836	break;
3837	}
3838	//////////////////////////////
3839	case DCACHE_XTN_DC_INVAL_END: // send response to processor XTN request
3840	{
3841	r_dcache_fsm = DCACHE_IDLE;
3842	m_drsp.valid = true;
3843	break;
3844	}
3845	////////////////////////
3846	case DCACHE_MISS_SELECT: // Try to select a slot in associative set
3847	// if previous cleanup has been sent.
3848	// Waiting in this state if no slot available
3849	// Set the r_dcache_cleanup_req flip-flop
3850	// and the r_dcache_miss_clack flip-flop
3851	// when a cleanup is required
3852	{
3853	if ( m_dreq.valid) m_cost_data_miss_frz++;
3854
3855	// coherence request (from CC_RECEIVE FSM)
3856	if ( r_cc_receive_dcache_req.read() )
3857	{
3858	r_dcache_fsm = DCACHE_CC_CHECK;
3859	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3860	break;
3861	}
3862
3863	if ( not r_dcache_cc_send_req.read() ) // blocked until previous cc_send request is sent
3864	{
3865	bool found;
3866	bool cleanup;
3867	size_t way;
3868	size_t set;
3869	paddr_t victim;
3870
3871	#ifdef INSTRUMENTATION
3872	m_cpt_dcache_dir_read++;
3873	#endif
3874	r_dcache.read_select( r_dcache_save_paddr.read(),
3875	&victim,
3876	&way,
3877	&set,
3878	&found,
3879	&cleanup );
3880
3881	if ( found )
3882	{
3883	r_dcache_miss_way = way;
3884	r_dcache_miss_set = set;
3885
3886	if ( cleanup )
3887	{
3888	r_dcache_miss_clack = true;
3889	r_dcache_fsm = DCACHE_MISS_CLEAN;
3890	// request cleanup
3891	r_dcache_cc_send_req = true;
3892	r_dcache_cc_send_nline = victim;
3893	r_dcache_cc_send_way = way;
3894	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
3895	}
3896	else
3897	{
3898	r_dcache_fsm = DCACHE_MISS_WAIT;
3899	}
3900
3901	#if DEBUG_DCACHE
3902	if ( m_debug_dcache_fsm )
3903	{
3904	std::cout << " <PROC " << name()
3905	<< " DCACHE_MISS_SELECT> Select a slot:" << std::dec
3906	<< " / WAY = " << way
3907	<< " / SET = " << set
3908	<< " / PADDR = " << std::hex << r_dcache_save_paddr.read();
3909	if(cleanup) std::cout << " / VICTIM = " << std::hex << victim << std::endl;
3910	else std::cout << std::endl;
3911	}
3912	#endif
3913	} // end found
3914	}
3915	break;
3916	}
3917	///////////////////////
3918	case DCACHE_MISS_CLEAN: // switch the slot to ZOMBI state
3919	// and possibly request itlb or dtlb invalidate
3920	{
3921	if ( m_dreq.valid) m_cost_data_miss_frz++;
3922
3923	size_t way = r_dcache_miss_way.read();
3924	size_t set = r_dcache_miss_set.read();
3925	paddr_t nline = r_dcache_save_paddr.read() / (m_dcache_words<<2);
3926
3927	#ifdef INSTRUMENTATION
3928	m_cpt_dcache_dir_read++;
3929	#endif
3930	r_dcache.write_dir( way,
3931	set,
3932	CACHE_SLOT_STATE_ZOMBI );
3933	#if DEBUG_DCACHE
3934	if ( m_debug_dcache_fsm )
3935	{
3936	std::cout << " <PROC " << name()
3937	<< " DCACHE_MISS_CLEAN> Switch to ZOMBI state" << std::dec
3938	<< " / way = " << way
3939	<< " / set = " << set << std::endl;
3940	}
3941	#endif
3942	// if selective itlb & dtlb invalidate are required
3943	// the miss response is not handled before invalidate completed
3944	if ( r_dcache_in_tlb[way*m_dcache_sets+set] )
3945	{
3946	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
3947	r_dcache_tlb_inval_line = r_dcache_cc_send_nline;
3948	r_dcache_tlb_inval_set = 0;
3949	r_dcache_fsm_scan_save = DCACHE_MISS_WAIT;
3950	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
3951	}
3952	else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] )
3953	{
3954	r_itlb.reset();
3955	r_dtlb.reset();
3956	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
3957	r_dcache_fsm = DCACHE_MISS_WAIT;
3958	}
3959	else
3960	{
3961	r_dcache_fsm = DCACHE_MISS_WAIT;
3962	}
3963	break;
3964	}
3965	//////////////////////
3966	case DCACHE_MISS_WAIT: // waiting the response to a miss request from VCI_RSP FSM
3967	// This state is in charge of error signaling
3968	// There is 5 types of error depending on the requester
3969	{
3970	if ( m_dreq.valid) m_cost_data_miss_frz++;
3971
3972	// coherence request (from CC_RECEIVE FSM)
3973	if ( r_cc_receive_dcache_req.read() )
3974	{
3975	r_dcache_fsm = DCACHE_CC_CHECK;
3976	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3977	break;
3978	}
3979
3980	if ( r_vci_rsp_data_error.read() ) // bus error
3981	{
3982	switch ( r_dcache_miss_type.read() )
3983	{
3984	case PROC_MISS:
3985	{
3986	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
3987	r_mmu_dbvar = r_dcache_save_vaddr.read();
3988	m_drsp.valid = true;
3989	m_drsp.error = true;
3990	r_dcache_fsm = DCACHE_IDLE;
3991	break;
3992	}
3993	case PTE1_MISS:
3994	{
3995	if ( r_dcache_tlb_ins.read() )
3996	{
3997	r_mmu_ietr = MMU_READ_PT1_ILLEGAL_ACCESS;
3998	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3999	r_icache_tlb_miss_req = false;
4000	r_icache_tlb_rsp_error = true;
4001	}
4002	else
4003	{
4004	r_mmu_detr = MMU_READ_PT1_ILLEGAL_ACCESS;
4005	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
4006	m_drsp.valid = true;
4007	m_drsp.error = true;
4008	}
4009	r_dcache_fsm = DCACHE_IDLE;
4010	break;
4011	}
4012	case PTE2_MISS:
4013	{
4014	if ( r_dcache_tlb_ins.read() )
4015	{
4016	r_mmu_ietr = MMU_READ_PT2_ILLEGAL_ACCESS;
4017	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
4018	r_icache_tlb_miss_req = false;
4019	r_icache_tlb_rsp_error = true;
4020	}
4021	else
4022	{
4023	r_mmu_detr = MMU_READ_PT2_ILLEGAL_ACCESS;
4024	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
4025	m_drsp.valid = true;
4026	m_drsp.error = true;
4027	}
4028	r_dcache_fsm = DCACHE_IDLE;
4029	break;
4030	}
4031	} // end switch type
4032	r_vci_rsp_data_error = false;
4033	}
4034	else if ( r_vci_rsp_fifo_dcache.rok() ) // valid response available
4035	{
4036	r_dcache_miss_word = 0;
4037	r_dcache_fsm = DCACHE_MISS_DATA_UPDT;
4038	}
4039	break;
4040	}
4041	//////////////////////////
4042	case DCACHE_MISS_DATA_UPDT: // update the dcache (one word per cycle)
4043	{
4044	if ( m_dreq.valid) m_cost_data_miss_frz++;
4045
4046	if ( r_vci_rsp_fifo_dcache.rok() ) // one word available
4047	{
4048	#ifdef INSTRUMENTATION
4049	m_cpt_dcache_data_write++;
4050	#endif
4051	r_dcache.write( r_dcache_miss_way.read(),
4052	r_dcache_miss_set.read(),
4053	r_dcache_miss_word.read(),
4054	r_vci_rsp_fifo_dcache.read() );
4055	#if DEBUG_DCACHE
4056	if ( m_debug_dcache_fsm )
4057	{
4058	std::cout << " <PROC " << name()
4059	<< " DCACHE_MISS_DATA_UPDT> Write one word:"
4060	<< " / DATA = " << std::hex << r_vci_rsp_fifo_dcache.read()
4061	<< " / WAY = " << std::dec << r_dcache_miss_way.read()
4062	<< " / SET = " << r_dcache_miss_set.read()
4063	<< " / WORD = " << r_dcache_miss_word.read() << std::endl;
4064	}
4065	#endif
4066	vci_rsp_fifo_dcache_get = true;
4067	r_dcache_miss_word = r_dcache_miss_word.read() + 1;
4068
4069	if ( r_dcache_miss_word.read() == (m_dcache_words-1) ) // last word
4070	{
4071	r_dcache_fsm = DCACHE_MISS_DIR_UPDT;
4072	}
4073	}
4074	break;
4075	}
4076	//////////////////////////
4077	case DCACHE_MISS_DIR_UPDT: // Stalled if a victim line has been evicted
4078	// and the cleanup ack has not been received,
4079	// as indicated by the r_dcache_miss clack.
4080	// - If no matching coherence request (r_dcache_inval_miss)
4081	// switch directory slot to VALID state.
4082	// - If matching coherence request, switch directory slot
4083	// to ZOMBI state, and send a cleanup request.
4084	{
4085	if ( m_dreq.valid) m_cost_data_miss_frz++;
4086
4087	// coherence request (from CC_RECEIVE FSM)
4088	if ( r_cc_receive_dcache_req.read() )
4089	{
4090	r_dcache_fsm = DCACHE_CC_CHECK;
4091	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4092	break;
4093	}
4094
4095	if ( not r_dcache_miss_clack.read() ) // waiting cleanup acknowledge
4096	{
4097	if ( r_dcache_miss_inval.read() ) // switch slot to ZOMBI state, and new cleanup
4098	{
4099	if ( not r_dcache_cc_send_req.read() ) // blocked until previous cc_send request is sent
4100	{
4101	r_dcache_miss_inval = false;
4102	// request cleanup
4103	r_dcache_cc_send_req = true;
4104	r_dcache_cc_send_nline = r_dcache_save_paddr.read()/(m_dcache_words<<2);
4105	r_dcache_cc_send_way = r_dcache_miss_way.read();
4106	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
4107
4108	#ifdef INSTRUMENTATION
4109	m_cpt_dcache_dir_write++;
4110	#endif
4111	r_dcache.write_dir( r_dcache_save_paddr.read(),
4112	r_dcache_miss_way.read(),
4113	r_dcache_miss_set.read(),
4114	CACHE_SLOT_STATE_ZOMBI );
4115	#if DEBUG_DCACHE
4116	if ( m_debug_dcache_fsm )
4117	{
4118	std::cout << " <PROC " << name()
4119	<< " DCACHE_MISS_DIR_UPDT> Switch slot to ZOMBI state"
4120	<< " PADDR = " << std::hex << r_dcache_save_paddr.read()
4121	<< " / WAY = " << std::dec << r_dcache_miss_way.read()
4122	<< " / SET = " << r_dcache_miss_set.read() << std::endl;
4123	}
4124	#endif
4125	}
4126	else
4127	break;
4128	}
4129	else // switch slot to VALID state
4130	{
4131
4132	#ifdef INSTRUMENTATION
4133	m_cpt_dcache_dir_write++;
4134	#endif
4135	r_dcache.write_dir( r_dcache_save_paddr.read(),
4136	r_dcache_miss_way.read(),
4137	r_dcache_miss_set.read(),
4138	CACHE_SLOT_STATE_VALID );
4139
4140	#if DEBUG_DCACHE
4141	if ( m_debug_dcache_fsm )
4142	{
4143	std::cout << " <PROC " << name()
4144	<< " DCACHE_MISS_DIR_UPDT> Switch slot to VALID state"
4145	<< " PADDR = " << std::hex << r_dcache_save_paddr.read()
4146	<< " / WAY = " << std::dec << r_dcache_miss_way.read()
4147	<< " / SET = " << r_dcache_miss_set.read() << std::endl;
4148
4149	// r_dcache.printTrace();
4150
4151
4152	}
4153	#endif
4154	// reset directory extension
4155	size_t way = r_dcache_miss_way.read();
4156	size_t set = r_dcache_miss_set.read();
4157	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
4158	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
4159	}
4160	if (r_dcache_miss_type.read()==PTE1_MISS) r_dcache_fsm = DCACHE_TLB_PTE1_GET;
4161	else if (r_dcache_miss_type.read()==PTE2_MISS) r_dcache_fsm = DCACHE_TLB_PTE2_GET;
4162	else r_dcache_fsm = DCACHE_IDLE;
4163	}
4164	break;
4165	}
4166	/////////////////////
4167	case DCACHE_UNC_WAIT: // waiting a response to an uncacheable read
4168	{
4169	// coherence request (from CC_RECEIVE FSM)
4170	if ( r_cc_receive_dcache_req.read() )
4171	{
4172	r_dcache_fsm = DCACHE_CC_CHECK;
4173	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4174	break;
4175	}
4176
4177	if ( r_vci_rsp_data_error.read() ) // bus error
4178	{
4179	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
4180	r_mmu_dbvar = m_dreq.addr;
4181	r_vci_rsp_data_error = false;
4182	m_drsp.error = true;
4183	m_drsp.valid = true;
4184	r_dcache_fsm = DCACHE_IDLE;
4185	break;
4186	}
4187	else if ( r_vci_rsp_fifo_dcache.rok() ) // data available
4188	{
4189	// consume data
4190	vci_rsp_fifo_dcache_get = true;
4191	r_dcache_fsm = DCACHE_IDLE;
4192
4193	// acknowledge the processor request if it has not been modified
4194	if ( m_dreq.valid and (m_dreq.addr == r_dcache_save_vaddr.read()) )
4195	{
4196	m_drsp.valid = true;
4197	m_drsp.error = false;
4198	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
4199	}
4200	}
4201	break;
4202	}
4203	/////////////////////
4204	case DCACHE_LL_WAIT: // waiting VCI response to a LL transaction
4205	{
4206	// coherence request (from CC_RECEIVE FSM)
4207	if ( r_cc_receive_dcache_req.read() )
4208	{
4209	r_dcache_fsm = DCACHE_CC_CHECK;
4210	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4211	break;
4212	}
4213
4214	if ( r_vci_rsp_data_error.read() ) // bus error
4215	{
4216	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
4217	r_mmu_dbvar = m_dreq.addr;
4218	r_vci_rsp_data_error = false;
4219	m_drsp.error = true;
4220	m_drsp.valid = true;
4221	r_dcache_fsm = DCACHE_IDLE;
4222	break;
4223	}
4224	else if ( r_vci_rsp_fifo_dcache.rok() ) // data available
4225	{
4226	// consume data
4227	vci_rsp_fifo_dcache_get = true;
4228
4229	if(r_dcache_ll_rsp_count.read() == 0) // first flit
4230	{
4231	// set key value in llsc reservation buffer
4232	r_dcache_llsc_key = r_vci_rsp_fifo_dcache.read();
4233	r_dcache_ll_rsp_count = r_dcache_ll_rsp_count.read() + 1 ;
4234	}
4235	else // last flit
4236	{
4237	// acknowledge the processor request if it has not been modified
4238	if ( m_dreq.valid and (m_dreq.addr == r_dcache_save_vaddr.read()) )
4239	{
4240	m_drsp.valid = true;
4241	m_drsp.error = false;
4242	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
4243	}
4244	r_dcache_fsm = DCACHE_IDLE;
4245	}
4246	}
4247	break;
4248	}
4249	////////////////////
4250	case DCACHE_SC_WAIT: // waiting VCI response to a SC transaction
4251	{
4252	// coherence request (from CC_RECEIVE FSM)
4253	if ( r_cc_receive_dcache_req.read() )
4254	{
4255	r_dcache_fsm = DCACHE_CC_CHECK;
4256	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4257	break;
4258	}
4259
4260	if ( r_vci_rsp_data_error.read() ) // bus error
4261	{
4262	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
4263	r_mmu_dbvar = m_dreq.addr;
4264	r_vci_rsp_data_error = false;
4265	m_drsp.error = true;
4266	m_drsp.valid = true;
4267	r_dcache_fsm = DCACHE_IDLE;
4268	break;
4269	}
4270	else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
4271	{
4272	// consume response
4273	vci_rsp_fifo_dcache_get = true;
4274	m_drsp.valid = true;
4275	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
4276	r_dcache_fsm = DCACHE_IDLE;
4277	}
4278	break;
4279	}
4280	//////////////////////////
4281	case DCACHE_DIRTY_GET_PTE: // This sub_fsm set the PTE Dirty bit in memory
4282	// before handling a processor WRITE or SC request
4283	// Input argument is r_dcache_dirty_paddr
4284	// In this first state, we get PTE value in dcache
4285	// and post a CAS request to CMD FSM
4286	{
4287	// get PTE in dcache
4288	uint32_t pte;
4289	size_t way;
4290	size_t set;
4291	size_t word; // unused
4292	int state;
4293
4294	#ifdef INSTRUMENTATION
4295	m_cpt_dcache_data_read++;
4296	m_cpt_dcache_dir_read++;
4297	#endif
4298	r_dcache.read( r_dcache_dirty_paddr.read(),
4299	&pte,
4300	&way,
4301	&set,
4302	&word,
4303	&state );
4304
4305	assert( (state == CACHE_SLOT_STATE_VALID) and
4306	"error in DCACHE_DIRTY_TLB_SET: the PTE should be in dcache" );
4307
4308	// request CAS transaction to CMD_FSM
4309	r_dcache_dirty_way = way;
4310	r_dcache_dirty_set = set;
4311
4312	// check llsc reservation buffer
4313	if (r_dcache_llsc_paddr.read() == r_dcache_dirty_paddr.read() )
4314	r_dcache_llsc_valid = false;
4315
4316	// request a CAS CMD and go to DCACHE_DIRTY_WAIT state
4317	r_dcache_vci_cas_req = true;
4318	r_dcache_vci_paddr = r_dcache_dirty_paddr.read();
4319	r_dcache_vci_cas_old = pte;
4320	r_dcache_vci_cas_new = pte \| PTE_D_MASK;
4321	r_dcache_fsm = DCACHE_DIRTY_WAIT;
4322
4323	#if DEBUG_DCACHE
4324	if ( m_debug_dcache_fsm )
4325	{
4326	std::cout << " <PROC " << name()
4327	<< " DCACHE_DIRTY_GET_PTE> CAS request" << std::hex
4328	<< " / PTE_PADDR = " << r_dcache_dirty_paddr.read()
4329	<< " / PTE_VALUE = " << pte << std::dec
4330	<< " / SET = " << set
4331	<< " / WAY = " << way << std::endl;
4332	}
4333	#endif
4334	break;
4335	}
4336	///////////////////////
4337	case DCACHE_DIRTY_WAIT: // wait completion of CAS for PTE Dirty bit,
4338	// and return to IDLE state when response is received.
4339	// we don't care if the CAS is a failure:
4340	// - if the CAS is a success, the coherence mechanism
4341	// updates the local copy.
4342	// - if the CAS is a failure, we just retry the write.
4343	{
4344	// coherence request (from CC_RECEIVE FSM)
4345	if ( r_cc_receive_dcache_req.read() )
4346	{
4347	r_dcache_fsm = DCACHE_CC_CHECK;
4348	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4349	break;
4350	}
4351
4352	if ( r_vci_rsp_data_error.read() ) // bus error
4353	{
4354	std::cout << "BUS ERROR in DCACHE_DIRTY_WAIT state" << std::endl;
4355	std::cout << "This should not happen in this state" << std::endl;
4356	exit(0);
4357	}
4358	else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
4359	{
4360	vci_rsp_fifo_dcache_get = true;
4361	r_dcache_fsm = DCACHE_IDLE;
4362
4363	#if DEBUG_DCACHE
4364	if ( m_debug_dcache_fsm )
4365	{
4366	std::cout << " <PROC " << name()
4367	<< " DCACHE_DIRTY_WAIT> CAS completed" << std::endl;
4368	}
4369	#endif
4370	}
4371	break;
4372	}
4373	/////////////////////
4374	case DCACHE_CC_CHECK: // This state is the entry point for the sub-FSM
4375	// handling coherence requests for DCACHE.
4376	// If there is a matching pending miss on the modified cache
4377	// line this is signaled in the r_dcache_miss inval flip-flop.
4378	// If the updated (or invalidated) cache line has copies in TLBs
4379	// these TLB copies are invalidated.
4380	// The return state is defined in r_dcache_fsm_cc_save
4381	{
4382	paddr_t paddr = r_cc_receive_dcache_nline.read() * m_dcache_words * 4;
4383	paddr_t mask = ~((m_dcache_words<<2)-1);
4384
4385	#if DEBUG_DCACHE
4386	if ( m_debug_dcache_fsm )
4387	{
4388	std::cout << " <PROC " << name()
4389	<< " DCACHE_CC_CHECK> paddr = " << paddr
4390	<< " r_dcache_vci_paddr = " << r_dcache_vci_paddr.read()
4391	<< " mask = " << mask
4392	<< " (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) = " << (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT)
4393	<< " (r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT) = " << (r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT)
4394	<< " ((r_dcache_vci_paddr.read() & mask) == (paddr & mask)) = " << ((r_dcache_vci_paddr.read() & mask) == (paddr & mask))
4395	<<std::endl;
4396	}
4397	#endif
4398
4399	if (r_cc_receive_dcache_type.read() == CC_TYPE_CLACK)
4400	// We switch the directory slot to EMPTY state
4401	// and reset r_icache_miss_clack if the cleanup ack
4402	// is matching a pending miss.
4403	{
4404
4405	if ( m_dreq.valid ) m_cost_data_miss_frz++;
4406
4407	#ifdef INSTRUMENTATION
4408	m_cpt_dcache_dir_write++;
4409	#endif
4410	r_dcache.write_dir( 0,
4411	r_cc_receive_dcache_way.read(),
4412	r_cc_receive_dcache_set.read(),
4413	CACHE_SLOT_STATE_EMPTY);
4414
4415	if ( (r_dcache_miss_set.read() == r_cc_receive_dcache_set.read()) and
4416	(r_dcache_miss_way.read() == r_cc_receive_dcache_way.read()) )
4417	r_dcache_miss_clack = false;
4418
4419	r_dcache_fsm = r_dcache_fsm_cc_save.read() ;
4420	r_cc_receive_dcache_req = false;
4421	#if DEBUG_DCACHE
4422	if ( m_debug_dcache_fsm )
4423	{
4424	std::cout << " <PROC " << name()
4425	<< " DCACHE_CC_CHECK> CC_TYPE_CLACK Switch slot to EMPTY state"
4426	<< " set = " << r_cc_receive_dcache_set.read()
4427	<< " / way = " << r_cc_receive_dcache_way.read() << std::endl;
4428	}
4429	#endif
4430	}
4431	else if( ((r_dcache_fsm_cc_save == DCACHE_MISS_SELECT) or
4432	(r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) or
4433	(r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT)) and
4434	((r_dcache_vci_paddr.read() & mask) == (paddr & mask)) ) // matching
4435	{
4436	// signaling matching
4437	r_dcache_miss_inval = true;
4438
4439	// in case of update, go to CC_UPDT
4440	// JUST TO POP THE FIFO
4441	if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT)
4442	{
4443	r_dcache_fsm = DCACHE_CC_UPDT;
4444	r_dcache_cc_word = r_cc_receive_word_idx.read();
4445	// just pop the fifo , don't write in icache
4446	r_dcache_cc_need_write = false;
4447	}
4448	// the request is dealt with
4449	else
4450	{
4451	r_cc_receive_dcache_req = false;
4452	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4453	}
4454
4455	#if DEBUG_DCACHE
4456	if ( m_debug_dcache_fsm )
4457	{
4458	std::cout << " <PROC " << name()
4459	<< " DCACHE_CC_CHECK> Coherence request matching a pending miss:"
4460	<< " PADDR = " << std::hex << paddr << std::endl;
4461	}
4462	#endif
4463
4464	}
4465	else // no match
4466	{
4467	int state;
4468	size_t way;
4469	size_t set;
4470	size_t word;
4471
4472	#ifdef INSTRUMENTATION
4473	m_cpt_dcache_dir_read++;
4474	#endif
4475	r_dcache.read_dir( paddr,
4476	&state,
4477	&way,
4478	&set,
4479	&word ); // unused
4480
4481	r_dcache_cc_way = way;
4482	r_dcache_cc_set = set;
4483
4484	if ( state == CACHE_SLOT_STATE_VALID) // hit
4485	{
4486	// need to update the cache state
4487	r_dcache_cc_need_write = true;
4488	if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT) // hit update
4489	{
4490	r_dcache_fsm = DCACHE_CC_UPDT;
4491	r_dcache_cc_word = r_cc_receive_word_idx.read();
4492	}
4493	else if (r_cc_receive_dcache_type.read() == CC_TYPE_INVAL) // hit inval
4494	{
4495	r_dcache_fsm = DCACHE_CC_INVAL;
4496	}
4497	else if ( r_cc_receive_dcache_type.read() == CC_TYPE_BRDCAST) // hit broadcast
4498	{
4499	r_dcache_fsm = DCACHE_CC_BROADCAST;
4500	}
4501	}
4502	else // miss
4503	{
4504	// multicast acknowledgement required in case of update
4505	if(r_cc_receive_dcache_type.read() == CC_TYPE_UPDT)
4506	{
4507	r_dcache_fsm = DCACHE_CC_UPDT;
4508	r_dcache_cc_word = r_cc_receive_word_idx.read();
4509	// just pop the fifo , don't write in icache
4510	r_dcache_cc_need_write = false;
4511	}
4512	else // No response needed
4513	{
4514	r_cc_receive_dcache_req = false;
4515	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4516	}
4517	}
4518
4519	#if DEBUG_DCACHE
4520	if ( m_debug_dcache_fsm )
4521	{
4522	std::cout << " <PROC " << name()
4523	<< " DCACHE_CC_CHECK> Coherence request received:"
4524	<< " PADDR = " << std::hex << paddr
4525	<< " / TYPE = " << std::dec << r_cc_receive_dcache_type.read()
4526	<< " / HIT = " << (state == CACHE_SLOT_STATE_VALID) << std::endl;
4527	}
4528	#endif
4529	}
4530	break;
4531	}
4532	/////////////////////
4533	case DCACHE_CC_INVAL: // hit inval: switch slot to EMPTY state,
4534	// after possible invalidation of copies in TLBs
4535	{
4536	size_t way = r_dcache_cc_way.read();
4537	size_t set = r_dcache_cc_set.read();
4538
4539	if (r_dcache_cc_need_write.read())
4540	{
4541	if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // selective TLB inval
4542	{
4543	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
4544	r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read();
4545	r_dcache_tlb_inval_set = 0;
4546	r_dcache_fsm_scan_save = r_dcache_fsm.read();
4547	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4548	break;
4549	}
4550	else
4551	{
4552	if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // TLB flush
4553	{
4554	r_itlb.reset();
4555	r_dtlb.reset();
4556	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
4557
4558	#if DEBUG_DCACHE
4559	if ( m_debug_dcache_fsm )
4560	{
4561	std::cout << " <PROC " << name()
4562	<< " DCACHE_CC_INVAL> Flush DTLB & ITLB" << std::endl;
4563	}
4564	#endif
4565	}
4566
4567	r_dcache.write_dir( 0,
4568	way,
4569	set,
4570	CACHE_SLOT_STATE_EMPTY );
4571
4572	r_dcache_cc_need_write = false;
4573
4574	#if DEBUG_DCACHE
4575	if ( m_debug_dcache_fsm )
4576	{
4577	std::cout << " <PROC " << name()
4578	<< " DCACHE_CC_INVAL> Switch slot to EMPTY state:" << std::dec
4579	<< " / WAY = " << way
4580	<< " / SET = " << set << std::endl;
4581	}
4582	#endif
4583	}
4584	}
4585	// multicast acknowledgement
4586	// send a request to cc_send_fsm
4587	if(not r_dcache_cc_send_req.read()) // cc_send is available
4588	{
4589	// coherence request completed
4590	r_cc_receive_dcache_req = false;
4591	// request multicast acknowledgement
4592	r_dcache_cc_send_req = true;
4593	r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read();
4594	r_dcache_cc_send_updt_tab_idx = r_cc_receive_dcache_updt_tab_idx.read();
4595	r_dcache_cc_send_type = CC_TYPE_MULTI_ACK;
4596
4597	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4598	}
4599	//else wait for previous cc_send request to be sent
4600	break;
4601	}
4602	///////////////////
4603	case DCACHE_CC_UPDT: // hit update: write one word per cycle,
4604	// after possible invalidation of copies in TLBs
4605	{
4606	size_t word = r_dcache_cc_word.read();
4607	size_t way = r_dcache_cc_way.read();
4608	size_t set = r_dcache_cc_set.read();
4609
4610	if (r_cc_receive_updt_fifo_be.rok())
4611	{
4612	if (r_dcache_cc_need_write.read())
4613	{
4614	if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // selective TLB inval
4615	{
4616	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
4617	r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read();
4618	r_dcache_tlb_inval_set = 0;
4619	r_dcache_fsm_scan_save = r_dcache_fsm.read();
4620	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4621	break;
4622	}
4623
4624	if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // TLB flush
4625	{
4626	r_itlb.reset();
4627	r_dtlb.reset();
4628	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
4629
4630	#if DEBUG_DCACHE
4631	if ( m_debug_dcache_fsm )
4632	{
4633	std::cout << " <PROC " << name()
4634	<< " DCACHE_CC_UPDT> Flush DTLB & ITLB" << std::endl;
4635	}
4636	#endif
4637	}
4638
4639	#ifdef INSTRUMENTATION
4640	m_cpt_dcache_data_write++;
4641	#endif
4642	r_dcache.write( way,
4643	set,
4644	word,
4645	r_cc_receive_updt_fifo_data.read(),
4646	r_cc_receive_updt_fifo_be.read() );
4647
4648	r_dcache_cc_word = word + 1;
4649
4650	#if DEBUG_DCACHE
4651	if ( m_debug_dcache_fsm )
4652	{
4653	std::cout << " <PROC " << name()
4654	<< " DCACHE_CC_UPDT> Write one word" << std::dec
4655	<< " / WAY = " << way
4656	<< " / SET = " << set
4657	<< " / WORD = " << word
4658	<< " / VALUE = " << std::hex << r_cc_receive_updt_fifo_data.read() << std::endl;
4659	}
4660	#endif
4661	}
4662
4663	if ( r_cc_receive_updt_fifo_eop.read() ) // last word
4664	{
4665	// no need to write in the cache anymore
4666	r_dcache_cc_need_write = false;
4667
4668	// wait to send a request to cc_send_fsm
4669	if(not r_icache_cc_send_req.read())
4670	// cc_send is available
4671	{
4672	//consume last fifo flit if eop and request to cc_send possible
4673	cc_receive_updt_fifo_get = true;
4674
4675	// coherence request completed
4676	r_cc_receive_dcache_req = false;
4677
4678	// request multicast acknowledgement
4679	r_dcache_cc_send_req = true;
4680	r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read();
4681	r_dcache_cc_send_updt_tab_idx = r_cc_receive_dcache_updt_tab_idx.read();
4682	r_dcache_cc_send_type = CC_TYPE_MULTI_ACK;
4683
4684	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4685	}
4686	}
4687	else
4688	{
4689	//consume fifo if not eop
4690	cc_receive_updt_fifo_get = true;
4691	}
4692	}
4693	break;
4694	}
4695	/////////////////////////
4696	case DCACHE_CC_BROADCAST: // hit broadcast : switch state to ZOMBI state
4697	// and request a cleanup, after possible
4698	// invalidation of copies in TLBs
4699	{
4700	size_t way = r_dcache_cc_way.read();
4701	size_t set = r_dcache_cc_set.read();
4702	paddr_t nline = r_cc_receive_dcache_nline.read();
4703
4704	if (r_dcache_cc_need_write.read())
4705	{
4706	if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // selective TLB inval
4707	{
4708	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
4709	r_dcache_tlb_inval_line = nline;
4710	r_dcache_tlb_inval_set = 0;
4711	r_dcache_fsm_scan_save = r_dcache_fsm.read();
4712	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4713	break;
4714	}
4715	else
4716	{
4717	if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // TLB flush
4718	{
4719	r_itlb.reset();
4720	r_dtlb.reset();
4721	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
4722
4723	#if DEBUG_DCACHE
4724	if ( m_debug_dcache_fsm )
4725	{
4726	std::cout << " <PROC " << name()
4727	<< " DCACHE_CC_BROADCAST> Flush DTLB & ITLB" << std::endl;
4728	}
4729	#endif
4730	}
4731
4732	#ifdef INSTRUMENTATION
4733	m_cpt_dcache_dir_write++;
4734	#endif
4735	r_dcache.write_dir( way,
4736	set,
4737	CACHE_SLOT_STATE_ZOMBI );
4738
4739	r_dcache_cc_need_write = false;
4740	#if DEBUG_DCACHE
4741	if ( m_debug_dcache_fsm )
4742	{
4743	std::cout << " <PROC " << name()
4744	<< " DCACHE_CC_BROADCAST > Slot goes to ZOMBI state "
4745	<< " SET = " << set
4746	<< " / WAY = " << way << std::endl;
4747	}
4748	#endif
4749	}
4750	}
4751	// cleanup
4752	// send a request to cc_send_fsm
4753	if(not r_dcache_cc_send_req.read()) // cc_send is available
4754	{
4755	// coherence request completed
4756	r_cc_receive_dcache_req = false;
4757	// request cleanup
4758	r_dcache_cc_send_req = true;
4759	r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read();
4760	r_dcache_cc_send_way = r_dcache_cc_way.read();
4761	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
4762
4763	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4764	}
4765	//else wait for previous cc_send request to be sent
4766	break;
4767	}
4768	///////////////////////////
4769	case DCACHE_INVAL_TLB_SCAN: // Scan sequencially all sets for both ITLB & DTLB
4770	// It makes assumption: m_itlb_sets == m_dtlb_sets
4771	// All ways are handled in parallel.
4772	// We enter this state when a DCACHE line is modified,
4773	// and there is a copy in itlb or dtlb.
4774	// It can be caused by:
4775	// - a coherence inval or updt transaction,
4776	// - a line inval caused by a cache miss
4777	// - a processor XTN inval request,
4778	// - a WRITE hit,
4779	// - a Dirty bit update
4780	// Input arguments are:
4781	// - r_dcache_tlb_inval_line
4782	// - r_dcache_tlb_inval_set
4783	// - r_dcache_fsm_scan_save
4784	{
4785	paddr_t line = r_dcache_tlb_inval_line.read();
4786	size_t set = r_dcache_tlb_inval_set.read();
4787	size_t way;
4788	bool ok;
4789
4790	for ( way = 0 ; way < m_itlb_ways ; way++ )
4791	{
4792	ok = r_itlb.inval( line, way, set );
4793
4794	#if DEBUG_DCACHE
4795	if ( m_debug_dcache_fsm and ok )
4796	{
4797	std::cout << " <PROC " << name()
4798	<< ".DCACHE_INVAL_TLB_SCAN> Invalidate ITLB entry:" << std::hex
4799	<< " line = " << line << std::dec
4800	<< " / set = " << set
4801	<< " / way = " << way << std::endl;
4802	}
4803	#endif
4804	}
4805
4806	for ( way = 0 ; way < m_dtlb_ways ; way++ )
4807	{
4808	ok = r_dtlb.inval( line, way, set );
4809
4810	#if DEBUG_DCACHE
4811	if ( m_debug_dcache_fsm and ok )
4812	{
4813	std::cout << " <PROC " << name()
4814	<< ".DCACHE_INVAL_TLB_SCAN> Invalidate DTLB entry:" << std::hex
4815	<< " line = " << line << std::dec
4816	<< " / set = " << set
4817	<< " / way = " << way << std::endl;
4818	}
4819	#endif
4820	}
4821
4822	// return to the calling state when TLB inval completed
4823	if ( r_dcache_tlb_inval_set.read() == (m_dtlb_sets-1) )
4824	{
4825	r_dcache_fsm = r_dcache_fsm_scan_save.read();
4826	}
4827	r_dcache_tlb_inval_set = r_dcache_tlb_inval_set.read() + 1;
4828	break;
4829	}
4830	} // end switch r_dcache_fsm
4831
4832	///////////////// wbuf update ///////////////////////////////////////////////////////
4833	r_wbuf.update();
4834
4835	///////////////// llsc update ///////////////////////////////////////////////////////
4836	if (r_dcache_llsc_valid.read()) r_dcache_llsc_count = r_dcache_llsc_count.read() - 1;
4837	if (r_dcache_llsc_count.read() == 1) r_dcache_llsc_valid = false;
4838
4839	//////////////// test processor frozen //////////////////////////////////////////////
4840	// The simulation exit if the number of consecutive frozen cycles
4841	// is larger than the m_max_frozen_cycles (constructor parameter)
4842	if ( (m_ireq.valid and not m_irsp.valid) or (m_dreq.valid and not m_drsp.valid) )
4843	{
4844	m_cpt_frz_cycles++; // used for instrumentation
4845	m_cpt_stop_simulation++; // used for debug
4846	if ( m_cpt_stop_simulation > m_max_frozen_cycles )
4847	{
4848	std::cout << std::dec << "ERROR in CC_VCACHE_WRAPPER " << name() << std::endl
4849	<< " stop at cycle " << m_cpt_total_cycles << std::endl
4850	<< " frozen since cycle " << m_cpt_total_cycles - m_max_frozen_cycles
4851	<< std::endl;
4852	r_iss.dump();
4853	exit(1);
4854	}
4855	}
4856	else
4857	{
4858	m_cpt_stop_simulation = 0;
4859	}
4860
4861	/////////// execute one iss cycle /////////////////////////////////
4862	{
4863	uint32_t it = 0;
4864	for (size_t i=0; i<(size_t)iss_t::n_irq; i++) if(p_irq[i].read()) it \|= (1<<i);
4865	r_iss.executeNCycles(1, m_irsp, m_drsp, it);
4866	}
4867
4868	////////////////////////////////////////////////////////////////////////////
4869	// The VCI_CMD FSM controls the following ressources:
4870	// - r_vci_cmd_fsm
4871	// - r_vci_cmd_min
4872	// - r_vci_cmd_max
4873	// - r_vci_cmd_cpt
4874	// - r_vci_cmd_imiss_prio
4875	// - wbuf (reset)
4876	// - r_icache_miss_req (reset)
4877	// - r_icache_unc_req (reset)
4878	// - r_dcache_vci_miss_req (reset)
4879	// - r_dcache_vci_unc_req (reset)
4880	// - r_dcache_vci_ll_req (reset)
4881	// - r_dcache_vci_sc_req (reset in case of local sc fail)
4882	// - r_dcache_vci_cas_req (reset)
4883	//
4884	// This FSM handles requests from both the DCACHE FSM & the ICACHE FSM.
4885	// There are 8 request types, with the following priorities :
4886	// 1 - Data Read Miss : r_dcache_vci_miss_req and miss in the write buffer
4887	// 2 - Data Read Uncachable : r_dcache_vci_unc_req
4888	// 3 - Instruction Miss : r_icache_miss_req and miss in the write buffer
4889	// 4 - Instruction Uncachable : r_icache_unc_req
4890	// 5 - Data Write : r_wbuf.rok()
4891	// 6 - Data Linked Load : r_dcache_vci_ll_req
4892	// 7 - Data Store Conditionnal: r_dcache_vci_sc_req
4893	// 8 - Compare And Swap : r_dcache_vci_cas_req
4894	//
4895	// As we want to support several simultaneous VCI transactions, the VCI_CMD_FSM
4896	// and the VCI_RSP_FSM are fully desynchronized.
4897	//
4898	// VCI formats:
4899	// According to the VCI advanced specification, all read requests packets
4900	// (data Uncached, Miss data, instruction Uncached, Miss instruction)
4901	// are one word packets.
4902	// For write burst packets, all words are in the same cache line,
4903	// and addresses must be contiguous (the BE field is 0 in case of "holes").
4904	// The sc command packet implements actually a compare-and-swap mechanism
4905	// and the packet contains two flits.
4906	////////////////////////////////////////////////////////////////////////////////////
4907
4908	switch ( r_vci_cmd_fsm.read() )
4909	{
4910	//////////////
4911	case CMD_IDLE:
4912	{
4913	// DDACHE read requests (r_dcache_vci_miss_req or r_dcache_vci_ll_req), and
4914	// ICACHE read requests (r_icache_miss_req) require both a write_buffer access
4915	// to check a possible pending write on the same cache line.
4916	// As there is only one possible access per cycle to write buffer, we implement
4917	// a round-robin priority between DCACHE and ICACHE for this access,
4918	// using the r_vci_cmd_imiss_prio flip-flop.
4919
4920	size_t wbuf_min;
4921	size_t wbuf_max;
4922
4923	bool dcache_unc_req = r_dcache_vci_unc_req.read() and
4924	( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() );
4925
4926	bool dcache_miss_req = r_dcache_vci_miss_req.read() and
4927	( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() );
4928
4929	bool dcache_ll_req = r_dcache_vci_ll_req.read() and
4930	( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() );
4931
4932	bool icache_miss_req = r_icache_miss_req.read() and
4933	( not (r_dcache_vci_miss_req.read() or
4934	r_dcache_vci_ll_req.read() or
4935	r_dcache_vci_unc_req.read())
4936	or r_vci_cmd_imiss_prio.read() );
4937
4938
4939	// 1 - Data Read Miss
4940	if ( dcache_miss_req and r_wbuf.miss(r_dcache_vci_paddr.read()) )
4941	{
4942	r_vci_cmd_fsm = CMD_DATA_MISS;
4943	r_dcache_vci_miss_req = false;
4944	r_vci_cmd_imiss_prio = true;
4945	// m_cpt_dmiss_transaction++;
4946	}
4947	// 2 - Data Read Uncachable
4948	else if ( dcache_unc_req and r_wbuf.miss(r_dcache_vci_paddr.read()))
4949	{
4950	r_vci_cmd_fsm = CMD_DATA_UNC;
4951	r_dcache_vci_unc_req = false;
4952	// m_cpt_dunc_transaction++;
4953	}
4954	// 3 - Data Linked Load
4955	else if ( dcache_ll_req and r_wbuf.miss(r_dcache_vci_paddr.read()))
4956	{
4957	r_dcache_vci_ll_req = false;
4958	r_vci_cmd_fsm = CMD_DATA_LL;
4959	// m_cpt_ll_transaction++;
4960	}
4961	// 4 - Instruction Miss
4962	else if ( icache_miss_req and r_wbuf.miss(r_icache_vci_paddr.read()) )
4963	{
4964	r_vci_cmd_fsm = CMD_INS_MISS;
4965	r_icache_miss_req = false;
4966	r_vci_cmd_imiss_prio = false;
4967	// m_cpt_imiss_transaction++;
4968	}
4969	// 5 - Instruction Uncachable
4970	else if ( r_icache_unc_req.read() )
4971	{
4972	r_vci_cmd_fsm = CMD_INS_UNC;
4973	r_icache_unc_req = false;
4974	// m_cpt_iunc_transaction++;
4975	}
4976	// 6 - Data Write
4977	else if ( r_wbuf.rok(&wbuf_min, &wbuf_max) )
4978	{
4979	r_vci_cmd_fsm = CMD_DATA_WRITE;
4980	r_vci_cmd_cpt = wbuf_min;
4981	r_vci_cmd_min = wbuf_min;
4982	r_vci_cmd_max = wbuf_max;
4983	// m_cpt_write_transaction++;
4984	// m_length_write_transaction += (wbuf_max-wbuf_min+1);
4985	}
4986	// 7 - Data Store Conditionnal
4987	else if ( r_dcache_vci_sc_req.read() )
4988	{
4989	r_dcache_vci_sc_req = false;
4990	r_vci_cmd_cpt = 0;
4991	r_vci_cmd_fsm = CMD_DATA_SC;
4992	// m_cpt_sc_transaction++;
4993	}
4994	// 8 - Compare And Swap
4995	else if ( r_dcache_vci_cas_req.read() )
4996	{
4997	r_vci_cmd_fsm = CMD_DATA_CAS;
4998	r_dcache_vci_cas_req = false;
4999	r_vci_cmd_cpt = 0;
5000	// m_cpt_cas_transaction++;
5001	}
5002	break;
5003	}
5004	////////////////////
5005	case CMD_DATA_WRITE:
5006	{
5007	if ( p_vci.cmdack.read() )
5008	{
5009	r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
5010	if (r_vci_cmd_cpt == r_vci_cmd_max) // last flit sent
5011	{
5012	r_vci_cmd_fsm = CMD_IDLE ;
5013	r_wbuf.sent() ;
5014	}
5015	}
5016	break;
5017	}
5018	/////////////////
5019	case CMD_DATA_SC:
5020	case CMD_DATA_CAS:
5021	{
5022	// The CAS and SC VCI commands contain two flits
5023	if ( p_vci.cmdack.read() )
5024	{
5025	r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
5026	if (r_vci_cmd_cpt == 1) r_vci_cmd_fsm = CMD_IDLE ;
5027	}
5028	break;
5029	}
5030	//////////////////
5031	case CMD_INS_MISS:
5032	case CMD_INS_UNC:
5033	case CMD_DATA_MISS:
5034	case CMD_DATA_UNC:
5035	case CMD_DATA_LL:
5036	{
5037	// all read VCI commands contain one single flit
5038	if ( p_vci.cmdack.read() ) r_vci_cmd_fsm = CMD_IDLE;
5039	break;
5040	}
5041
5042	} // end switch r_vci_cmd_fsm
5043
5044	//////////////////////////////////////////////////////////////////////////
5045	// The VCI_RSP FSM controls the following ressources:
5046	// - r_vci_rsp_fsm:
5047	// - r_vci_rsp_fifo_icache (push)
5048	// - r_vci_rsp_fifo_dcache (push)
5049	// - r_vci_rsp_data_error (set)
5050	// - r_vci_rsp_ins_error (set)
5051	// - r_vci_rsp_cpt
5052	// - r_dcache_vci_sc_req (reset when SC response recieved)
5053	//
5054	// As the VCI_RSP and VCI_CMD are fully desynchronized to support several
5055	// simultaneous VCI transactions, this FSM uses the VCI RPKTID field
5056	// to identify the transactions.
5057	//
5058	// VCI vormat:
5059	// This component checks the response packet length and accepts only
5060	// single word packets for write response packets.
5061	//
5062	// Error handling:
5063	// This FSM analyzes the VCI error code and signals directly the Write Bus Error.
5064	// In case of Read Data Error, the VCI_RSP FSM sets the r_vci_rsp_data_error
5065	// flip_flop and the error is signaled by the DCACHE FSM.
5066	// In case of Instruction Error, the VCI_RSP FSM sets the r_vci_rsp_ins_error
5067	// flip_flop and the error is signaled by the ICACHE FSM.
5068	// In case of Cleanup Error, the simulation stops with an error message...
5069	//////////////////////////////////////////////////////////////////////////
5070
5071	switch ( r_vci_rsp_fsm.read() )
5072	{
5073	//////////////
5074	case RSP_IDLE:
5075	{
5076	if ( p_vci.rspval.read() )
5077	{
5078	r_vci_rsp_cpt = 0;
5079
5080	if ( (p_vci.rpktid.read() & 0x7) == TYPE_READ_DATA_UNC )
5081	{
5082	r_vci_rsp_fsm = RSP_DATA_UNC;
5083	}
5084	else if ( (p_vci.rpktid.read() & 0x7) == TYPE_READ_DATA_MISS )
5085	{
5086	r_vci_rsp_fsm = RSP_DATA_MISS;
5087	}
5088	else if ( (p_vci.rpktid.read() & 0x7) == TYPE_READ_INS_UNC )
5089	{
5090	r_vci_rsp_fsm = RSP_INS_UNC;
5091	}
5092	else if ( (p_vci.rpktid.read() & 0x7) == TYPE_READ_INS_MISS )
5093	{
5094	r_vci_rsp_fsm = RSP_INS_MISS;
5095	}
5096	else if ( (p_vci.rpktid.read() & 0x7) == TYPE_WRITE )
5097	{
5098	r_vci_rsp_fsm = RSP_DATA_WRITE;
5099	}
5100	else if ( (p_vci.rpktid.read() & 0x7) == TYPE_CAS )
5101	{
5102	r_vci_rsp_fsm = RSP_DATA_UNC;
5103	}
5104	else if ( (p_vci.rpktid.read() & 0x7) == TYPE_LL )
5105	{
5106	r_vci_rsp_fsm = RSP_DATA_LL;
5107	}
5108	else if ( (p_vci.rpktid.read() & 0x7) == TYPE_SC )
5109	{
5110	r_vci_rsp_fsm = RSP_DATA_UNC;
5111	}
5112	else
5113	{
5114	assert(false and "Unexpected VCI response");
5115	}
5116	}
5117	break;
5118	}
5119	//////////////////
5120	case RSP_INS_MISS:
5121	{
5122	if ( p_vci.rspval.read() )
5123	{
5124	if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported
5125	{
5126	r_vci_rsp_ins_error = true;
5127	if ( p_vci.reop.read() ) r_vci_rsp_fsm = RSP_IDLE;
5128	}
5129	else // no error reported
5130	{
5131	if ( r_vci_rsp_fifo_icache.wok() )
5132	{
5133	assert( (r_vci_rsp_cpt.read() < m_icache_words) and
5134	"The VCI response packet for instruction miss is too long" );
5135
5136	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
5137	vci_rsp_fifo_icache_put = true,
5138	vci_rsp_fifo_icache_data = p_vci.rdata.read();
5139	if ( p_vci.reop.read() )
5140	{
5141	assert( (r_vci_rsp_cpt.read() == m_icache_words - 1) and
5142	"The VCI response packet for instruction miss is too short");
5143
5144	r_vci_rsp_fsm = RSP_IDLE;
5145	}
5146	}
5147	}
5148	}
5149	break;
5150	}
5151	/////////////////
5152	case RSP_INS_UNC:
5153	{
5154	if (p_vci.rspval.read() )
5155	{
5156	assert( p_vci.reop.read() and
5157	"illegal VCI response packet for uncachable instruction");
5158
5159	if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported
5160	{
5161	r_vci_rsp_ins_error = true;
5162	r_vci_rsp_fsm = RSP_IDLE;
5163	}
5164	else // no error reported
5165	{
5166	if ( r_vci_rsp_fifo_icache.wok())
5167	{
5168	vci_rsp_fifo_icache_put = true;
5169	vci_rsp_fifo_icache_data = p_vci.rdata.read();
5170	r_vci_rsp_fsm = RSP_IDLE;
5171	}
5172	}
5173	}
5174	break;
5175	}
5176	///////////////////
5177	case RSP_DATA_MISS:
5178	{
5179	if ( p_vci.rspval.read() )
5180	{
5181	if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported
5182	{
5183	r_vci_rsp_data_error = true;
5184	if ( p_vci.reop.read() ) r_vci_rsp_fsm = RSP_IDLE;
5185	}
5186	else // no error reported
5187	{
5188	if ( r_vci_rsp_fifo_dcache.wok() )
5189	{
5190	assert( (r_vci_rsp_cpt.read() < m_dcache_words) and
5191	"The VCI response packet for data miss is too long");
5192
5193	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
5194	vci_rsp_fifo_dcache_put = true,
5195	vci_rsp_fifo_dcache_data = p_vci.rdata.read();
5196	if ( p_vci.reop.read() )
5197	{
5198	assert( (r_vci_rsp_cpt.read() == m_dcache_words - 1) and
5199	"The VCI response packet for data miss is too short");
5200
5201	r_vci_rsp_fsm = RSP_IDLE;
5202	}
5203	}
5204	}
5205	}
5206	break;
5207	}
5208	//////////////////
5209	case RSP_DATA_UNC:
5210	{
5211	if (p_vci.rspval.read() )
5212	{
5213	assert( p_vci.reop.read() and
5214	"illegal VCI response packet for uncachable read data");
5215
5216	if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported
5217	{
5218	r_vci_rsp_data_error = true;
5219	r_vci_rsp_fsm = RSP_IDLE;
5220	}
5221	else // no error reported
5222	{
5223	if ( r_vci_rsp_fifo_dcache.wok())
5224	{
5225	vci_rsp_fifo_dcache_put = true;
5226	vci_rsp_fifo_dcache_data = p_vci.rdata.read();
5227	r_vci_rsp_fsm = RSP_IDLE;
5228	}
5229	}
5230	}
5231	break;
5232	}
5233	////////////////////
5234	case RSP_DATA_LL:
5235	{
5236	if ( p_vci.rspval.read() )
5237	{
5238	if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported
5239	{
5240	r_vci_rsp_data_error = true;
5241	r_vci_rsp_fsm = RSP_IDLE;
5242	}
5243	if (r_vci_rsp_cpt.read() == 0) //first flit
5244	{
5245	if(r_vci_rsp_fifo_dcache.wok())
5246	{
5247	assert(!p_vci.reop.read() &&
5248	"illegal VCI response packet for LL");
5249	vci_rsp_fifo_dcache_put = true;
5250	vci_rsp_fifo_dcache_data = p_vci.rdata.read();
5251	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
5252	}
5253	break;
5254	}
5255	else // last flit
5256	{
5257	if(r_vci_rsp_fifo_dcache.wok())
5258	{
5259	assert(p_vci.reop.read() &&
5260	"illegal VCI response packet for LL");
5261	vci_rsp_fifo_dcache_put = true;
5262	vci_rsp_fifo_dcache_data = p_vci.rdata.read();
5263	r_vci_rsp_fsm = RSP_IDLE;
5264	}
5265	break;
5266	}
5267	}
5268	break;
5269	}
5270	////////////////////
5271	case RSP_DATA_WRITE:
5272	{
5273	if (p_vci.rspval.read())
5274	{
5275	assert( p_vci.reop.read() and
5276	"a VCI response packet must contain one flit for a write transaction");
5277
5278	r_vci_rsp_fsm = RSP_IDLE;
5279	uint32_t wbuf_index = p_vci.rtrdid.read();
5280	bool cacheable = r_wbuf.completed(wbuf_index);
5281	if ( not cacheable ) r_dcache_pending_unc_write = false;
5282	if ( (p_vci.rerror.read()&0x1) != 0 ) r_iss.setWriteBerr();
5283	}
5284	break;
5285	}
5286	} // end switch r_vci_rsp_fsm
5287
5288	/////////////////////////////////////////////////////////////////////////////////////
5289	// The CC_SEND FSM is in charge of sending cleanups and the multicast
5290	// acknowledgements on the coherence network. It has two clients (DCACHE FSM
5291	// and ICACHE FSM) that are served with a round-robin priority.
5292	// The CC_SEND FSM resets the r_*cache_cc_send_req request flip-flops as
5293	// soon as the request has been sent.
5294	/////////////////////////////////////////////////////////////////////////////////////
5295	switch ( r_cc_send_fsm.read() )
5296	{
5297	///////////////////////////
5298	case CC_SEND_IDLE:
5299	{
5300	///////////////////////////////////////////////////////
5301	// handling round robin between icache and dcache : //
5302	// we first check for the last client and listen for //
5303	// a request of the other, then update the client //
5304	// r_cc_send_last_client : 0 dcache / 1 icache
5305	///////////////////////////////////////////////////////
5306	bool update_last_client = r_cc_send_last_client.read();
5307	if ( r_cc_send_last_client.read() == 0 ) // last client was dcache
5308	{
5309	if (r_icache_cc_send_req.read()) // request from icache
5310	update_last_client = 1; // update last client to icache
5311	}
5312	else // last client was icache
5313	{
5314	if (r_dcache_cc_send_req.read()) // request from dcache
5315	update_last_client = 0; // update last client to dcache
5316	}
5317	r_cc_send_last_client = update_last_client;
5318
5319	// if there is an actual request
5320	if (r_dcache_cc_send_req.read() or r_icache_cc_send_req.read())
5321	{
5322	// the new client is dcache and has a cleanup request
5323	if ( (update_last_client == 0) and
5324	(r_dcache_cc_send_type.read() == CC_TYPE_CLEANUP))
5325	r_cc_send_fsm = CC_SEND_CLEANUP_1;
5326	// the new client is dcache and has a multi acknowledgement request
5327	else if ( (update_last_client == 0) and
5328	(r_dcache_cc_send_type.read() == CC_TYPE_MULTI_ACK))
5329	r_cc_send_fsm = CC_SEND_MULTI_ACK;
5330	// the new client is icache and has a cleanup request
5331	else if ( (update_last_client == 1) and
5332	(r_icache_cc_send_type.read() == CC_TYPE_CLEANUP))
5333	r_cc_send_fsm = CC_SEND_CLEANUP_1;
5334	// the new client is icache and has a multi acknowledgement request
5335	else if ( (update_last_client == 1) and
5336	(r_icache_cc_send_type.read() == CC_TYPE_MULTI_ACK))
5337	r_cc_send_fsm = CC_SEND_MULTI_ACK;
5338	}
5339	break;
5340	}
5341	///////////////////////////
5342	case CC_SEND_CLEANUP_1:
5343	{
5344	// wait for the first flit to be consumed
5345	if (p_dspin_out.read.read())
5346	r_cc_send_fsm = CC_SEND_CLEANUP_2;
5347
5348	break;
5349	}
5350	///////////////////////////
5351	case CC_SEND_CLEANUP_2:
5352	{
5353	// wait for the second flit to be consumed
5354	if (p_dspin_out.read.read())
5355	{
5356	if (r_cc_send_last_client.read() == 0) // dcache active request
5357	r_dcache_cc_send_req = false; // reset dcache request
5358	else // icache active request
5359	r_icache_cc_send_req = false; // reset icache request
5360
5361	// go back to idle state
5362	r_cc_send_fsm = CC_SEND_IDLE;
5363	}
5364	break;
5365	}
5366	///////////////////////////
5367	case CC_SEND_MULTI_ACK:
5368	{
5369	// wait for the flit to be consumed
5370	if(p_dspin_out.read.read())
5371	{
5372	if(r_cc_send_last_client.read() == 0) // dcache active request
5373	r_dcache_cc_send_req = false; // reset dcache request
5374	else // icache active request
5375	r_icache_cc_send_req = false; // reset icache request
5376	// go back to idle state
5377	r_cc_send_fsm = CC_SEND_IDLE;
5378	}
5379	break;
5380	}
5381	} // end switch CC_SEND FSM
5382
5383	///////////////////////////////////////////////////////////////////////////////
5384	// C_RECEIVE FSM
5385	// This FSM receive all coherence packets on a DSPIN40 port.
5386	// There is 4 packet types:
5387	// - CC_DATA_INVAL : DCACHE invalidate request
5388	// - CC_DATA_UPDT : DCACHE update request (multi-words)
5389	// - CC_INST_INVAL : ICACHE invalidate request
5390	// - CC_INST_UPDT : ICACHE update request (multi-words)
5391	// - CC_BROADCAST : Broadcast invalidate request (both DCACHE & ICACHE)
5392	// - CC_DATA_CLACK : DCACHE cleanup acknowledge
5393	// - CC_INST_CLACK : ICACHE cleanup acknowledge
5394	//////////////////////////////////////////////////////////////////////////////
5395	switch( r_cc_receive_fsm.read() )
5396	{
5397	/////////////////////
5398	case CC_RECEIVE_IDLE:
5399	{
5400	// a coherence request has arrived
5401	if (p_dspin_in.write.read())
5402	{
5403	// initialize dspin received data
5404	uint64_t receive_data = p_dspin_in.data.read();
5405	// initialize coherence packet type
5406	uint64_t receive_type = DspinDhccpParam::dspin_get(receive_data,
5407	DspinDhccpParam::FROM_MC_TYPE);
5408	// initialize data/ins flip_flop (0 data / 1 ins)
5409	r_cc_receive_data_ins = (bool)(receive_type & 0x1);
5410	// test for a broadcast
5411	if (DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::FROM_MC_BC))
5412	{
5413	r_cc_receive_fsm = CC_RECEIVE_BRDCAST_HEADER;
5414	}
5415	// test for a CLACK
5416	else if ((receive_type == DspinDhccpParam::TYPE_CLEANUP_ACK_DATA) or
5417	(receive_type == DspinDhccpParam::TYPE_CLEANUP_ACK_INST))
5418	{
5419	r_cc_receive_fsm = CC_RECEIVE_CLACK;
5420	}
5421	// test for a multi updt
5422	else if ((receive_type == DspinDhccpParam::TYPE_MULTI_UPDT_DATA) or
5423	(receive_type == DspinDhccpParam::TYPE_MULTI_UPDT_INST))
5424	{
5425	r_cc_receive_fsm = CC_RECEIVE_UPDT_HEADER;
5426	}
5427	// test for a multi inval
5428	else
5429	{
5430	r_cc_receive_fsm = CC_RECEIVE_INVAL_HEADER;
5431	}
5432	}
5433	break;
5434	}
5435	//////////////////////
5436	case CC_RECEIVE_CLACK:
5437	{
5438	// initialize dspin received data
5439	uint64_t receive_data = p_dspin_in.data.read();
5440
5441	// for data CLACK, wait for dcache to take the request
5442	if ((r_cc_receive_data_ins.read() == 0) and
5443	not (r_cc_receive_dcache_req.read()))
5444	{
5445	// request dcache to handle the CLACK
5446	r_cc_receive_dcache_req = true;
5447	r_cc_receive_dcache_set = DspinDhccpParam::dspin_get(receive_data,
5448	DspinDhccpParam::CLEANUP_ACK_SET) &
5449	((1ULL<<(uint32_log2(m_dcache_sets)))-1);
5450	r_cc_receive_dcache_way = DspinDhccpParam::dspin_get(receive_data,
5451	DspinDhccpParam::CLEANUP_ACK_WAY) &
5452	((1ULL<<(uint32_log2(m_dcache_ways)))-1);
5453	r_cc_receive_dcache_type = CC_TYPE_CLACK;
5454	// get back to idle state
5455	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5456	break;
5457	}
5458	// for ins CLACK, wait for icache to take the request
5459	if ((r_cc_receive_data_ins.read() == 1) and
5460	not (r_cc_receive_icache_req.read()))
5461	{
5462	// request icache to handle the CLACK
5463	r_cc_receive_icache_req = true;
5464	r_cc_receive_icache_set = DspinDhccpParam::dspin_get(receive_data,
5465	DspinDhccpParam::CLEANUP_ACK_SET) &
5466	((1ULL<<(uint32_log2(m_icache_sets)))-1);
5467	r_cc_receive_icache_way = DspinDhccpParam::dspin_get(receive_data,
5468	DspinDhccpParam::CLEANUP_ACK_WAY) &
5469	((1ULL<<(uint32_log2(m_icache_ways)))-1);
5470	r_cc_receive_icache_type = CC_TYPE_CLACK;
5471	// get back to idle state
5472	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5473	break;
5474	}
5475	// keep waiting for the correct cache to accept the request
5476	break;
5477	}
5478	///////////////////////////////
5479	case CC_RECEIVE_BRDCAST_HEADER:
5480	{
5481	// no actual data in the HEADER, just skip to second flit
5482	r_cc_receive_fsm = CC_RECEIVE_BRDCAST_NLINE;
5483	break;
5484	}
5485	//////////////////////////////
5486	case CC_RECEIVE_BRDCAST_NLINE:
5487	{
5488	// initialize dspin received data
5489	uint64_t receive_data = p_dspin_in.data.read();
5490	// wait for both dcache and icache to take the request
5491	// TODO maybe we need to wait for both only to leave the state, but
5492	// not to actually post a request to an available cache => need a
5493	// flip_flop to check that ?
5494	if (not (r_cc_receive_icache_req.read()) and
5495	not (r_cc_receive_dcache_req.read()) and
5496	(p_dspin_in.write.read()))
5497	{
5498	// request dcache to handle the BROADCAST
5499	r_cc_receive_dcache_req = true;
5500	r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,
5501	DspinDhccpParam::BROADCAST_NLINE);
5502	r_cc_receive_dcache_type = CC_TYPE_BRDCAST;
5503	// request icache to handle the BROADCAST
5504	r_cc_receive_icache_req = true;
5505	r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,
5506	DspinDhccpParam::BROADCAST_NLINE);
5507	r_cc_receive_icache_type = CC_TYPE_BRDCAST;
5508	// get back to idle state
5509	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5510	break;
5511	}
5512	// keep waiting for the caches to accept the request
5513	break;
5514	}
5515	/////////////////////////////
5516	case CC_RECEIVE_INVAL_HEADER:
5517	{
5518	// sample updt tab index in the HEADER, then skip to second flit
5519	uint64_t receive_data = p_dspin_in.data.read();
5520	// for data INVAL, wait for dcache to take the request
5521	if ((r_cc_receive_data_ins.read() == 0) and
5522	not (r_cc_receive_dcache_req.read()))
5523	{
5524	r_cc_receive_dcache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,
5525	DspinDhccpParam::MULTI_INVAL_UPDT_INDEX);
5526	r_cc_receive_fsm = CC_RECEIVE_INVAL_NLINE;
5527	break;
5528	}
5529	// for ins INVAL, wait for icache to take the request
5530	if ((r_cc_receive_data_ins.read() == 1) and
5531	not (r_cc_receive_icache_req.read()))
5532	{
5533	r_cc_receive_icache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,
5534	DspinDhccpParam::MULTI_INVAL_UPDT_INDEX);
5535	r_cc_receive_fsm = CC_RECEIVE_INVAL_NLINE;
5536	break;
5537	}
5538	// keep waiting for the correct cache to accept the request
5539	break;
5540	}
5541	////////////////////////////
5542	case CC_RECEIVE_INVAL_NLINE:
5543	{
5544	// sample nline in the second flit
5545	uint64_t receive_data = p_dspin_in.data.read();
5546	// for data INVAL, wait for dcache to take the request
5547	if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()) and (p_dspin_in.write.read()))
5548	{
5549	// request dcache to handle the INVAL
5550	r_cc_receive_dcache_req = true;
5551	r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_NLINE);
5552	r_cc_receive_dcache_type = CC_TYPE_INVAL;
5553	// get back to idle state
5554	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5555	break;
5556	}
5557	// for ins INVAL, wait for icache to take the request
5558	if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()) and (p_dspin_in.write.read()))
5559	{
5560	// request icache to handle the INVAL
5561	r_cc_receive_icache_req = true;
5562	r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_NLINE);
5563	r_cc_receive_icache_type = CC_TYPE_INVAL;
5564	// get back to idle state
5565	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5566	break;
5567	}
5568	// we should never get there
5569	assert ( false && "CC_RECEIVE_INVAL_NLINE : incoherent handling of either r_cc_receive_data_ins or r_cc_receive_*cache_req\n");
5570	}
5571	////////////////////////////
5572	case CC_RECEIVE_UPDT_HEADER:
5573	{
5574	// sample updt tab index in the HEADER, than skip to second flit
5575	uint64_t receive_data = p_dspin_in.data.read();
5576	// for data INVAL, wait for dcache to take the request and fifo to
5577	// be empty
5578	if ((r_cc_receive_data_ins.read() == 0) and not r_cc_receive_dcache_req.read() and r_cc_receive_updt_fifo_be.empty())
5579	{
5580	r_cc_receive_dcache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_UPDT_INDEX);
5581	r_cc_receive_fsm = CC_RECEIVE_UPDT_NLINE;
5582	break;
5583	}
5584	// for ins INVAL, wait for icache to take the request and fifo to be
5585	// empty
5586	if ((r_cc_receive_data_ins.read() == 1) and not r_cc_receive_icache_req.read() and r_cc_receive_updt_fifo_be.empty())
5587	{
5588	r_cc_receive_icache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_UPDT_INDEX);
5589	r_cc_receive_fsm = CC_RECEIVE_UPDT_NLINE;
5590	break;
5591	}
5592	// keep waiting for the correct cache to accept the request
5593	break;
5594	}
5595	///////////////////////////
5596	case CC_RECEIVE_UPDT_NLINE:
5597	{
5598	// sample nline and word index in the second flit
5599	uint64_t receive_data = p_dspin_in.data.read();
5600	// for data INVAL, wait for dcache to take the request and fifo to
5601	// be empty
5602	if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()) and r_cc_receive_updt_fifo_be.empty() and (p_dspin_in.write.read()))
5603	{
5604	r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_NLINE);
5605	r_cc_receive_word_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_WORD_INDEX);
5606	r_cc_receive_dcache_type = CC_TYPE_UPDT;
5607	// get back to idle state
5608	r_cc_receive_fsm = CC_RECEIVE_UPDT_DATA;
5609	break;
5610	}
5611	// for ins INVAL, wait for icache to take the request and fifo to be
5612	// empty
5613	if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()) and r_cc_receive_updt_fifo_be.empty() and (p_dspin_in.write.read()))
5614	{
5615	r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_NLINE);
5616	r_cc_receive_word_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_WORD_INDEX);
5617	r_cc_receive_icache_type = CC_TYPE_UPDT;
5618	// get back to idle state
5619	r_cc_receive_fsm = CC_RECEIVE_UPDT_DATA;
5620	break;
5621	}
5622	// we should never get there
5623	assert ( false && "CC_RECEIVE_UPDT_NLINE : incoherent handling of either r_cc_receive_data_ins or r_cc_receive_*cache_req or r_cc_receive_fifo\n");
5624	break;
5625	}
5626	//////////////////////////
5627	case CC_RECEIVE_UPDT_DATA:
5628	{
5629	if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()) and (p_dspin_in.write.read()))
5630	r_cc_receive_dcache_req = true;
5631	if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()) and (p_dspin_in.write.read()))
5632	r_cc_receive_icache_req = true;
5633
5634	// sample data, be and eop
5635	uint64_t receive_data = p_dspin_in.data.read();
5636	// wait for the fifo
5637	if (r_cc_receive_updt_fifo_be.wok() and (p_dspin_in.write.read()))
5638	{
5639	cc_receive_updt_fifo_be = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_BE);
5640	cc_receive_updt_fifo_data = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_DATA);
5641	// sample eop to test for state exit
5642	bool flit_eop = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::FROM_MC_EOP);
5643	cc_receive_updt_fifo_eop = flit_eop;
5644	cc_receive_updt_fifo_put = true;
5645	if(flit_eop)
5646	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5647	}
5648	break;
5649	}
5650	} // end switch CC_RECEIVE FSM
5651
5652	///////////////// Response FIFOs update //////////////////////
5653	r_vci_rsp_fifo_icache.update(vci_rsp_fifo_icache_get,
5654	vci_rsp_fifo_icache_put,
5655	vci_rsp_fifo_icache_data);
5656
5657	r_vci_rsp_fifo_dcache.update(vci_rsp_fifo_dcache_get,
5658	vci_rsp_fifo_dcache_put,
5659	vci_rsp_fifo_dcache_data);
5660
5661	///////////////// updt FIFO update //////////////////////
5662	//TODO check this
5663	r_cc_receive_updt_fifo_be.update(cc_receive_updt_fifo_get,
5664	cc_receive_updt_fifo_put,
5665	cc_receive_updt_fifo_be);
5666	r_cc_receive_updt_fifo_data.update(cc_receive_updt_fifo_get,
5667	cc_receive_updt_fifo_put,
5668	cc_receive_updt_fifo_data);
5669	r_cc_receive_updt_fifo_eop.update(cc_receive_updt_fifo_get,
5670	cc_receive_updt_fifo_put,
5671	cc_receive_updt_fifo_eop);
5672
5673	} // end transition()
5674
5675	///////////////////////
5676	tmpl(void)::genMoore()
5677	///////////////////////
5678	{
5679
5680	// VCI initiator command on the direct network
5681	// it depends on the CMD FSM state
5682
5683	bool is_sc_or_cas = (r_vci_cmd_fsm.read() == CMD_DATA_CAS) or
5684	(r_vci_cmd_fsm.read() == CMD_DATA_SC );
5685
5686	p_vci.pktid = 0;
5687	p_vci.srcid = m_srcid;
5688	p_vci.cons = is_sc_or_cas;
5689	p_vci.contig = not is_sc_or_cas;
5690	p_vci.wrap = false;
5691	p_vci.clen = 0;
5692	p_vci.cfixed = false;
5693
5694	switch ( r_vci_cmd_fsm.read() ) {
5695
5696	case CMD_IDLE:
5697	p_vci.cmdval = false;
5698	p_vci.address = 0;
5699	p_vci.wdata = 0;
5700	p_vci.be = 0;
5701	p_vci.trdid = 0;
5702	p_vci.pktid = 0;
5703	p_vci.plen = 0;
5704	p_vci.cmd = vci_param::CMD_NOP;
5705	p_vci.eop = false;
5706	break;
5707
5708	case CMD_INS_MISS:
5709	p_vci.cmdval = true;
5710	p_vci.address = r_icache_vci_paddr.read() & m_icache_yzmask;
5711	p_vci.wdata = 0;
5712	p_vci.be = 0xF;
5713	p_vci.trdid = 0;
5714	p_vci.pktid = TYPE_READ_INS_MISS;
5715	p_vci.plen = m_icache_words<<2;
5716	p_vci.cmd = vci_param::CMD_READ;
5717	p_vci.eop = true;
5718	break;
5719
5720	case CMD_INS_UNC:
5721	p_vci.cmdval = true;
5722	p_vci.address = r_icache_vci_paddr.read() & ~0x3;
5723	p_vci.wdata = 0;
5724	p_vci.be = 0xF;
5725	p_vci.trdid = 0;
5726	p_vci.pktid = TYPE_READ_INS_UNC;
5727	p_vci.plen = 4;
5728	p_vci.cmd = vci_param::CMD_READ;
5729	p_vci.eop = true;
5730	break;
5731
5732	case CMD_DATA_MISS:
5733	p_vci.cmdval = true;
5734	p_vci.address = r_dcache_vci_paddr.read() & m_dcache_yzmask;
5735	p_vci.wdata = 0;
5736	p_vci.be = 0xF;
5737	p_vci.trdid = 0;
5738	p_vci.pktid = TYPE_READ_DATA_MISS;
5739	p_vci.plen = m_dcache_words << 2;
5740	p_vci.cmd = vci_param::CMD_READ;
5741	p_vci.eop = true;
5742	break;
5743
5744	case CMD_DATA_UNC:
5745	p_vci.cmdval = true;
5746	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
5747	p_vci.wdata = 0;
5748	p_vci.be = r_dcache_vci_unc_be.read();
5749	p_vci.trdid = 0;
5750	p_vci.pktid = TYPE_READ_DATA_UNC;
5751	p_vci.plen = 4;
5752	p_vci.cmd = vci_param::CMD_READ;
5753	p_vci.eop = true;
5754	break;
5755
5756	case CMD_DATA_WRITE:
5757	p_vci.cmdval = true;
5758	p_vci.address = r_wbuf.getAddress(r_vci_cmd_cpt.read()) & ~0x3;
5759	p_vci.wdata = r_wbuf.getData(r_vci_cmd_cpt.read());
5760	p_vci.be = r_wbuf.getBe(r_vci_cmd_cpt.read());
5761	p_vci.trdid = r_wbuf.getIndex();
5762	p_vci.pktid = TYPE_WRITE;
5763	p_vci.plen = (r_vci_cmd_max.read() - r_vci_cmd_min.read() + 1) << 2;
5764	p_vci.cmd = vci_param::CMD_WRITE;
5765	p_vci.eop = (r_vci_cmd_cpt.read() == r_vci_cmd_max.read());
5766	break;
5767
5768	case CMD_DATA_LL:
5769	p_vci.cmdval = true;
5770	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
5771	p_vci.wdata = 0;
5772	p_vci.be = 0xF;
5773	p_vci.trdid = 0;
5774	p_vci.pktid = TYPE_LL;
5775	p_vci.plen = 8;
5776	p_vci.cmd = vci_param::CMD_LOCKED_READ;
5777	p_vci.eop = true;
5778	break;
5779
5780	case CMD_DATA_SC:
5781	p_vci.cmdval = true;
5782	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
5783	if ( r_vci_cmd_cpt.read() == 0 ) p_vci.wdata = r_dcache_llsc_key.read();
5784	else p_vci.wdata = r_dcache_vci_sc_data.read();
5785	p_vci.be = 0xF;
5786	p_vci.trdid = 0;
5787	p_vci.pktid = TYPE_SC;
5788	p_vci.plen = 8;
5789	p_vci.cmd = vci_param::CMD_NOP;
5790	p_vci.eop = (r_vci_cmd_cpt.read() == 1);
5791	break;
5792
5793	case CMD_DATA_CAS:
5794	p_vci.cmdval = true;
5795	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
5796	if ( r_vci_cmd_cpt.read() == 0 ) p_vci.wdata = r_dcache_vci_cas_old.read();
5797	else p_vci.wdata = r_dcache_vci_cas_new.read();
5798	p_vci.be = 0xF;
5799	p_vci.trdid = 0;
5800	p_vci.pktid = TYPE_CAS;
5801	p_vci.plen = 8;
5802	p_vci.cmd = vci_param::CMD_NOP;
5803	p_vci.eop = (r_vci_cmd_cpt.read() == 1);
5804	break;
5805	} // end switch r_vci_cmd_fsm
5806
5807	// VCI initiator response on the direct network
5808	// it depends on the VCI_RSP FSM
5809
5810	switch (r_vci_rsp_fsm.read() )
5811	{
5812	case RSP_DATA_WRITE : p_vci.rspack = true; break;
5813	case RSP_INS_MISS : p_vci.rspack = r_vci_rsp_fifo_icache.wok(); break;
5814	case RSP_INS_UNC : p_vci.rspack = r_vci_rsp_fifo_icache.wok(); break;
5815	case RSP_DATA_MISS : p_vci.rspack = r_vci_rsp_fifo_dcache.wok(); break;
5816	case RSP_DATA_UNC : p_vci.rspack = r_vci_rsp_fifo_dcache.wok(); break;
5817	case RSP_DATA_LL : p_vci.rspack = r_vci_rsp_fifo_dcache.wok(); break;
5818	case RSP_IDLE : p_vci.rspack = false; break;
5819	} // end switch r_vci_rsp_fsm
5820
5821
5822	// Send coherence packets on DSPIN L2M
5823	// it depends on the CC_SEND FSM
5824
5825	uint64_t dspin_send_data = 0;
5826	switch ( r_cc_send_fsm.read() )
5827	{
5828	//////////////////
5829	case CC_SEND_IDLE:
5830	{
5831	p_dspin_out.write = false;
5832	break;
5833	}
5834	///////////////////////
5835	case CC_SEND_CLEANUP_1:
5836	{
5837	// initialize dspin send data
5838	DspinDhccpParam::dspin_set(dspin_send_data,
5839	0,
5840	DspinDhccpParam::FROM_L1_EOP);
5841	DspinDhccpParam::dspin_set(dspin_send_data,
5842	m_cc_global_id,
5843	DspinDhccpParam::CLEANUP_SRCID);
5844	DspinDhccpParam::dspin_set(dspin_send_data,
5845	0,
5846	DspinDhccpParam::FROM_L1_BC);
5847
5848	if(r_cc_send_last_client.read() == 0) // dcache active request
5849	{
5850	uint64_t dest = (uint64_t) r_dcache_cc_send_nline.read()
5851	>> (m_nline_width - m_x_width - m_y_width)
5852	<< (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
5853
5854	DspinDhccpParam::dspin_set(dspin_send_data,
5855	dest,
5856	DspinDhccpParam::CLEANUP_DEST);
5857
5858	DspinDhccpParam::dspin_set(dspin_send_data,
5859	r_dcache_cc_send_nline.read() & 0x300000000ULL,
5860	DspinDhccpParam::CLEANUP_NLINE_MSB);
5861
5862	DspinDhccpParam::dspin_set(dspin_send_data,
5863	r_dcache_cc_send_way.read(),
5864	DspinDhccpParam::CLEANUP_WAY_INDEX);
5865
5866	DspinDhccpParam::dspin_set(dspin_send_data,
5867	DspinDhccpParam::TYPE_CLEANUP_DATA,
5868	DspinDhccpParam::FROM_L1_TYPE);
5869	}
5870	else // icache active request
5871	{
5872	uint64_t dest = (uint64_t) r_icache_cc_send_nline.read()
5873	>> (m_nline_width - m_x_width - m_y_width)
5874	<< (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
5875
5876	DspinDhccpParam::dspin_set(dspin_send_data,
5877	dest,
5878	DspinDhccpParam::CLEANUP_DEST);
5879
5880	DspinDhccpParam::dspin_set(dspin_send_data,
5881	r_icache_cc_send_nline.read() & 0x300000000ULL,
5882	DspinDhccpParam::CLEANUP_NLINE_MSB);
5883
5884	DspinDhccpParam::dspin_set(dspin_send_data,
5885	r_icache_cc_send_way.read(),
5886	DspinDhccpParam::CLEANUP_WAY_INDEX);
5887
5888	DspinDhccpParam::dspin_set(dspin_send_data,
5889	DspinDhccpParam::TYPE_CLEANUP_INST,
5890	DspinDhccpParam::FROM_L1_TYPE);
5891	}
5892	// send flit
5893	p_dspin_out.data = dspin_send_data;
5894	p_dspin_out.write = true;
5895	break;
5896	}
5897	///////////////////////
5898	case CC_SEND_CLEANUP_2:
5899	{
5900	// initialize dspin send data
5901	DspinDhccpParam::dspin_set(dspin_send_data,
5902	1,
5903	DspinDhccpParam::FROM_L1_EOP);
5904
5905	if(r_cc_send_last_client.read() == 0) // dcache active request
5906	{
5907	DspinDhccpParam::dspin_set(dspin_send_data,
5908	r_dcache_cc_send_nline.read() & 0xFFFFFFFFULL,
5909	DspinDhccpParam::CLEANUP_NLINE_LSB);
5910	}
5911	else // icache active request
5912	{
5913	DspinDhccpParam::dspin_set(dspin_send_data,
5914	r_icache_cc_send_nline.read() & 0xFFFFFFFFULL,
5915	DspinDhccpParam::CLEANUP_NLINE_LSB);
5916	}
5917	// send flit
5918	p_dspin_out.data = dspin_send_data;
5919	p_dspin_out.write = true;
5920	break;
5921	}
5922	///////////////////////
5923	case CC_SEND_MULTI_ACK:
5924	{
5925	// initialize dspin send data
5926	DspinDhccpParam::dspin_set(dspin_send_data,
5927	1,
5928	DspinDhccpParam::FROM_L1_EOP);
5929	DspinDhccpParam::dspin_set(dspin_send_data,
5930	0,
5931	DspinDhccpParam::FROM_L1_BC);
5932	DspinDhccpParam::dspin_set(dspin_send_data,
5933	DspinDhccpParam::TYPE_MULTI_ACK,
5934	DspinDhccpParam::FROM_L1_TYPE);
5935
5936	if(r_cc_send_last_client.read() == 0) // dcache active request
5937	{
5938	uint64_t dest = (uint64_t) r_dcache_cc_send_nline.read()
5939	>> (m_nline_width - m_x_width - m_y_width)
5940	<< (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
5941
5942	DspinDhccpParam::dspin_set(dspin_send_data,
5943	dest,
5944	DspinDhccpParam::MULTI_ACK_DEST);
5945
5946	DspinDhccpParam::dspin_set(dspin_send_data,
5947	r_dcache_cc_send_updt_tab_idx.read(),
5948	DspinDhccpParam::MULTI_ACK_UPDT_INDEX);
5949	}
5950	else // icache active request
5951	{
5952	uint64_t dest = (uint64_t) r_icache_cc_send_nline.read()
5953	>> (m_nline_width - m_x_width - m_y_width)
5954	<< (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
5955
5956
5957	DspinDhccpParam::dspin_set(dspin_send_data,
5958	dest,
5959	DspinDhccpParam::MULTI_ACK_DEST);
5960
5961	DspinDhccpParam::dspin_set(dspin_send_data,
5962	r_icache_cc_send_updt_tab_idx.read(),
5963	DspinDhccpParam::MULTI_ACK_UPDT_INDEX);
5964	}
5965	// send flit
5966	p_dspin_out.data = dspin_send_data;
5967	p_dspin_out.write = true;
5968
5969	break;
5970	}
5971	} // end switch CC_SEND FSM
5972
5973	// Receive coherence packets
5974	// It depends on the CC_RECEIVE FSM
5975
5976	switch( r_cc_receive_fsm.read() )
5977	{
5978	/////////////////////
5979	case CC_RECEIVE_IDLE:
5980	{
5981	p_dspin_in.read = false;
5982	break;
5983	}
5984	//////////////////////
5985	case CC_RECEIVE_CLACK:
5986	{
5987	if (((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read())) or
5988	((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read())))
5989	p_dspin_in.read = true;
5990	else
5991	p_dspin_in.read = false;
5992	break;
5993	}
5994	///////////////////////////////
5995	case CC_RECEIVE_BRDCAST_HEADER:
5996	{
5997	p_dspin_in.read = true;
5998	break;
5999	}
6000	//////////////////////////////
6001	case CC_RECEIVE_BRDCAST_NLINE:
6002	{
6003	// TODO maybe we need to wait for both only to leave the state, but
6004	// not to actually post a request to an available cache => need a
6005	// flip_flop to check that ?
6006	if (not (r_cc_receive_icache_req.read()) and not (r_cc_receive_dcache_req.read()))
6007	p_dspin_in.read = true;
6008	else
6009	p_dspin_in.read = false;
6010	break;
6011	}
6012	/////////////////////////////
6013	case CC_RECEIVE_INVAL_HEADER:
6014	{
6015	if (((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read())) or
6016	((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read())))
6017	p_dspin_in.read = true;
6018	else
6019	p_dspin_in.read = false;
6020	break;
6021	}
6022	////////////////////////////
6023	case CC_RECEIVE_INVAL_NLINE:
6024	{
6025	p_dspin_in.read = true;
6026	break;
6027	}
6028	////////////////////////////
6029	case CC_RECEIVE_UPDT_HEADER:
6030	{
6031	if (((r_cc_receive_data_ins.read() == 0) and
6032	not r_cc_receive_dcache_req.read() and
6033	r_cc_receive_updt_fifo_be.empty())
6034	or
6035	((r_cc_receive_data_ins.read() == 1) and
6036	not r_cc_receive_icache_req.read()) and
6037	r_cc_receive_updt_fifo_be.empty())
6038	p_dspin_in.read = true;
6039	else
6040	p_dspin_in.read = false;
6041	break;
6042	}
6043	///////////////////////////
6044	case CC_RECEIVE_UPDT_NLINE:
6045	{
6046	if (((r_cc_receive_data_ins.read() == 0) and
6047	not (r_cc_receive_dcache_req.read()) and
6048	r_cc_receive_updt_fifo_be.empty())
6049	or
6050	((r_cc_receive_data_ins.read() == 1) and
6051	not (r_cc_receive_icache_req.read()) and
6052	r_cc_receive_updt_fifo_be.empty()))
6053	p_dspin_in.read = true;
6054	else
6055	p_dspin_in.read = false;
6056	break;
6057	}
6058	//////////////////////////
6059	case CC_RECEIVE_UPDT_DATA:
6060	{
6061	if (r_cc_receive_updt_fifo_be.wok())
6062	p_dspin_in.read = true;
6063	else
6064	p_dspin_in.read = false;
6065	break;
6066	}
6067	} // end switch CC_RECEIVE FSM
6068
6069	} // end genMoore
6070
6071	}}
6072
6073	// Local Variables:
6074	// tab-width: 4
6075	// c-basic-offset: 4
6076	// c-file-offsets:((innamespace . 0)(inline-open . 0))
6077	// indent-tabs-mode: nil
6078	// End:
6079
6080	// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4

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