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source: trunk/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp @ 421

Last change on this file since 421 was 421, checked in by alain, 11 years ago
Bug fix: the r_dcache_vci_unc_be register was declared as bool. Changed to uint32_t
File size: 232.2 KB

Line
1	/* -- c++ --
2	* File : vci_cc_vcache_wrapper.cpp
3	* Copyright (c) UPMC, Lip6, SoC
4	* Authors : Alain GREINER, Yang GAO
5	*
6	* SOCLIB_LGPL_HEADER_BEGIN
7	*
8	* This file is part of SoCLib, GNU LGPLv2.1.
9	*
10	* SoCLib is free software; you can redistribute it and/or modify it
11	* under the terms of the GNU Lesser General Public License as published
12	* by the Free Software Foundation; version 2.1 of the License.
13	*
14	* SoCLib is distributed in the hope that it will be useful, but
15	* WITHOUT ANY WARRANTY; without even the implied warranty of
16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17	* Lesser General Public License for more details.
18	*
19	* You should have received a copy of the GNU Lesser General Public
20	* License along with SoCLib; if not, write to the Free Software
21	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
22	* 02110-1301 USA
23	*
24	* SOCLIB_LGPL_HEADER_END
25	*
26	* Maintainers: cesar.fuguet-tortolero@lip6.fr
27	* alexandre.joannou@lip6.fr
28	*/
29
30	#include <cassert>
31	#include "arithmetics.h"
32	#include "../include/vci_cc_vcache_wrapper.h"
33
34	#define DEBUG_DCACHE 1
35	#define DEBUG_ICACHE 1
36	#define DEBUG_CMD 0
37
38	namespace soclib {
39	namespace caba {
40
41	namespace {
42	const char *icache_fsm_state_str[] = {
43	"ICACHE_IDLE",
44
45	"ICACHE_XTN_TLB_FLUSH",
46	"ICACHE_XTN_CACHE_FLUSH",
47	"ICACHE_XTN_CACHE_FLUSH_GO",
48	"ICACHE_XTN_TLB_INVAL",
49	"ICACHE_XTN_CACHE_INVAL_VA",
50	"ICACHE_XTN_CACHE_INVAL_PA",
51	"ICACHE_XTN_CACHE_INVAL_GO",
52
53	"ICACHE_TLB_WAIT",
54
55	"ICACHE_MISS_SELECT",
56	"ICACHE_MISS_CLEAN",
57	"ICACHE_MISS_WAIT",
58	"ICACHE_MISS_DATA_UPDT",
59	"ICACHE_MISS_DIR_UPDT",
60
61	"ICACHE_UNC_WAIT",
62
63	"ICACHE_CC_CHECK",
64	"ICACHE_CC_INVAL",
65	"ICACHE_CC_UPDT",
66	"ICACHE_CC_BROADCAST",
67	"ICACHE_CC_SEND_WAIT",
68	};
69
70	const char *dcache_fsm_state_str[] = {
71	"DCACHE_IDLE",
72
73	"DCACHE_TLB_MISS",
74	"DCACHE_TLB_PTE1_GET",
75	"DCACHE_TLB_PTE1_SELECT",
76	"DCACHE_TLB_PTE1_UPDT",
77	"DCACHE_TLB_PTE2_GET",
78	"DCACHE_TLB_PTE2_SELECT",
79	"DCACHE_TLB_PTE2_UPDT",
80	"DCACHE_TLB_LR_UPDT",
81	"DCACHE_TLB_LR_WAIT",
82	"DCACHE_TLB_RETURN",
83
84	"DCACHE_XTN_SWITCH",
85	"DCACHE_XTN_SYNC",
86	"DCACHE_XTN_IC_INVAL_VA",
87	"DCACHE_XTN_IC_FLUSH",
88	"DCACHE_XTN_IC_INVAL_PA",
89	"DCACHE_XTN_IT_INVAL",
90	"DCACHE_XTN_DC_FLUSH",
91	"DCACHE_XTN_DC_FLUSH_GO",
92	"DCACHE_XTN_DC_INVAL_VA",
93	"DCACHE_XTN_DC_INVAL_PA",
94	"DCACHE_XTN_DC_INVAL_END",
95	"DCACHE_XTN_DC_INVAL_GO",
96	"DCACHE_XTN_DT_INVAL",
97
98	"DCACHE_DIRTY_GET_PTE",
99	"DCACHE_DIRTY_WAIT",
100
101	"DCACHE_MISS_SELECT",
102	"DCACHE_MISS_CLEAN",
103	"DCACHE_MISS_WAIT",
104	"DCACHE_MISS_DATA_UPDT",
105	"DCACHE_MISS_DIR_UPDT",
106
107	"DCACHE_UNC_WAIT",
108	"DCACHE_LL_WAIT",
109	"DCACHE_SC_WAIT",
110
111	"DCACHE_CC_CHECK",
112	"DCACHE_CC_INVAL",
113	"DCACHE_CC_UPDT",
114	"DCACHE_CC_BROADCAST",
115	"DCACHE_CC_SEND_WAIT",
116
117	"DCACHE_INVAL_TLB_SCAN",
118	};
119
120	const char *cmd_fsm_state_str[] = {
121	"CMD_IDLE",
122	"CMD_INS_MISS",
123	"CMD_INS_UNC",
124	"CMD_DATA_MISS",
125	"CMD_DATA_UNC",
126	"CMD_DATA_WRITE",
127	"CMD_DATA_LL",
128	"CMD_DATA_SC",
129	"CMD_DATA_CAS",
130	};
131
132	const char *rsp_fsm_state_str[] = {
133	"RSP_IDLE",
134	"RSP_INS_MISS",
135	"RSP_INS_UNC",
136	"RSP_DATA_MISS",
137	"RSP_DATA_UNC",
138	"RSP_DATA_LL",
139	"RSP_DATA_WRITE",
140	};
141
142	const char *cc_receive_fsm_state_str[] = {
143	"CC_RECEIVE_IDLE",
144	"CC_RECEIVE_CLACK",
145	"CC_RECEIVE_BRDCAST_HEADER",
146	"CC_RECEIVE_BRDCAST_NLINE",
147	"CC_RECEIVE_INVAL_HEADER",
148	"CC_RECEIVE_INVAL_NLINE",
149	"CC_RECEIVE_UPDT_HEADER",
150	"CC_RECEIVE_UPDT_NLINE",
151	"CC_RECEIVE_UPDT_DATA",
152	};
153
154	const char *cc_send_fsm_state_str[] = {
155	"CC_SEND_IDLE",
156	"CC_SEND_CLEANUP_1",
157	"CC_SEND_CLEANUP_2",
158	"CC_SEND_MULTI_ACK",
159	};
160	}
161
162	#define tmpl(...) \
163	template<typename vci_param, \
164	size_t dspin_in_width, \
165	size_t dspin_out_width, \
166	typename iss_t> __VA_ARGS__ \
167	VciCcVCacheWrapper<vci_param, dspin_in_width, dspin_out_width, iss_t>
168
169	using namespace soclib::common;
170
171	/////////////////////////////////
172	tmpl(/**/)::VciCcVCacheWrapper(
173	sc_module_name name,
174	const int proc_id,
175	const MappingTable &mtd,
176	const IntTab &srcid,
177	const size_t cc_global_id,
178	const size_t itlb_ways,
179	const size_t itlb_sets,
180	const size_t dtlb_ways,
181	const size_t dtlb_sets,
182	const size_t icache_ways,
183	const size_t icache_sets,
184	const size_t icache_words,
185	const size_t dcache_ways,
186	const size_t dcache_sets,
187	const size_t dcache_words,
188	const size_t wbuf_nlines,
189	const size_t wbuf_nwords,
190	const size_t x_width,
191	const size_t y_width,
192	const uint32_t max_frozen_cycles,
193	const uint32_t debug_start_cycle,
194	const bool debug_ok )
195	: soclib::caba::BaseModule(name),
196
197	p_clk("p_clk"),
198	p_resetn("p_resetn"),
199	p_vci("p_vci"),
200	p_dspin_in("p_dspin_in"),
201	p_dspin_out("p_dspin_out"),
202
203	m_cacheability_table( mtd.getCacheabilityTable() ),
204	m_srcid( mtd.indexForId(srcid) ),
205	m_cc_global_id( cc_global_id ),
206	m_nline_width( vci_param::N - (uint32_log2(dcache_words)) - 2 ),
207	m_itlb_ways( itlb_ways ),
208	m_itlb_sets( itlb_sets ),
209	m_dtlb_ways( dtlb_ways ),
210	m_dtlb_sets( dtlb_sets ),
211	m_icache_ways( icache_ways ),
212	m_icache_sets( icache_sets ),
213	m_icache_yzmask( (~0)<<(uint32_log2(icache_words) + 2) ),
214	m_icache_words( icache_words ),
215	m_dcache_ways( dcache_ways ),
216	m_dcache_sets( dcache_sets ),
217	m_dcache_yzmask( (~0)<<(uint32_log2(dcache_words) + 2) ),
218	m_dcache_words( dcache_words ),
219	m_x_width( x_width ),
220	m_y_width( y_width ),
221	m_proc_id( proc_id ),
222	m_max_frozen_cycles( max_frozen_cycles ),
223	m_paddr_nbits( vci_param::N ),
224	m_debug_start_cycle( debug_start_cycle ),
225	m_debug_ok( debug_ok ),
226
227	r_mmu_ptpr("r_mmu_ptpr"),
228	r_mmu_mode("r_mmu_mode"),
229	r_mmu_word_lo("r_mmu_word_lo"),
230	r_mmu_word_hi("r_mmu_word_hi"),
231	r_mmu_ibvar("r_mmu_ibvar"),
232	r_mmu_dbvar("r_mmu_dbvar"),
233	r_mmu_ietr("r_mmu_ietr"),
234	r_mmu_detr("r_mmu_detr"),
235
236	r_icache_fsm("r_icache_fsm"),
237	r_icache_fsm_save("r_icache_fsm_save"),
238	r_icache_vci_paddr("r_icache_vci_paddr"),
239	r_icache_vaddr_save("r_icache_vaddr_save"),
240
241	r_icache_miss_way("r_icache_miss_way"),
242	r_icache_miss_set("r_icache_miss_set"),
243	r_icache_miss_word("r_icache_miss_word"),
244	r_icache_miss_inval("r_icache_miss_inval"),
245	r_icache_miss_clack("r_icache_miss_clack"),
246
247	r_icache_cc_way("r_icache_cc_way"),
248	r_icache_cc_set("r_icache_cc_set"),
249	r_icache_cc_word("r_icache_cc_word"),
250	r_icache_cc_need_write("r_icache_cc_need_write"),
251
252	r_icache_flush_count("r_icache_flush_count"),
253
254	r_icache_miss_req("r_icache_miss_req"),
255	r_icache_unc_req("r_icache_unc_req"),
256
257	r_icache_tlb_miss_req("r_icache_tlb_read_req"),
258	r_icache_tlb_rsp_error("r_icache_tlb_rsp_error"),
259
260	r_icache_cc_send_req("r_icache_cc_send_req"),
261	r_icache_cc_send_type("r_icache_cc_send_type"),
262	r_icache_cc_send_nline("r_icache_cc_send_nline"),
263	r_icache_cc_send_way("r_icache_cc_send_way"),
264	r_icache_cc_send_updt_tab_idx("r_icache_cc_send_updt_tab_idx"),
265
266	r_dcache_fsm("r_dcache_fsm"),
267	r_dcache_fsm_cc_save("r_dcache_fsm_cc_save"),
268	r_dcache_fsm_scan_save("r_dcache_fsm_scan_save"),
269
270	r_dcache_wbuf_req("r_dcache_wbuf_req"),
271	r_dcache_updt_req("r_dcache_updt_req"),
272	r_dcache_save_vaddr("r_dcache_save_vaddr"),
273	r_dcache_save_wdata("r_dcache_save_wdata"),
274	r_dcache_save_be("r_dcache_save_be"),
275	r_dcache_save_paddr("r_dcache_save_paddr"),
276	r_dcache_save_cacheable("r_dcache_save_cacheable"),
277	r_dcache_save_cache_way("r_dcache_save_cache_way"),
278	r_dcache_save_cache_set("r_dcache_save_cache_set"),
279	r_dcache_save_cache_word("r_dcache_save_cache_word"),
280
281	r_dcache_dirty_paddr("r_dcache_dirty_paddr"),
282	r_dcache_dirty_way("r_dcache_dirty_way"),
283	r_dcache_dirty_set("r_dcache_dirty_set"),
284
285	r_dcache_vci_paddr("r_dcache_vci_paddr"),
286	r_dcache_vci_miss_req("r_dcache_vci_miss_req"),
287	r_dcache_vci_unc_req("r_dcache_vci_unc_req"),
288	r_dcache_vci_unc_be("r_dcache_vci_unc_be"),
289	r_dcache_vci_cas_req("r_dcache_vci_cas_req"),
290	r_dcache_vci_cas_old("r_dcache_vci_cas_old"),
291	r_dcache_vci_cas_new("r_dcache_vci_cas_new"),
292	r_dcache_vci_ll_req("r_dcache_vci_ll_req"),
293	r_dcache_vci_sc_req("r_dcache_vci_sc_req"),
294	r_dcache_vci_sc_data("r_dcache_vci_sc_data"),
295
296	r_dcache_xtn_way("r_dcache_xtn_way"),
297	r_dcache_xtn_set("r_dcache_xtn_set"),
298
299	r_dcache_pending_unc_write("r_dcache_pending_unc_write"),
300
301	r_dcache_miss_type("r_dcache_miss_type"),
302	r_dcache_miss_word("r_dcache_miss_word"),
303	r_dcache_miss_way("r_dcache_miss_way"),
304	r_dcache_miss_set("r_dcache_miss_set"),
305	r_dcache_miss_inval("r_dcache_miss_inval"),
306
307	r_dcache_cc_way("r_dcache_cc_way"),
308	r_dcache_cc_set("r_dcache_cc_set"),
309	r_dcache_cc_word("r_dcache_cc_word"),
310	r_dcache_cc_need_write("r_dcache_cc_need_write"),
311
312	r_dcache_flush_count("r_dcache_flush_count"),
313
314	r_dcache_ll_rsp_count("r_dcache_ll_rsp_count"),
315
316	r_dcache_tlb_vaddr("r_dcache_tlb_vaddr"),
317	r_dcache_tlb_ins("r_dcache_tlb_ins"),
318	r_dcache_tlb_pte_flags("r_dcache_tlb_pte_flags"),
319	r_dcache_tlb_pte_ppn("r_dcache_tlb_pte_ppn"),
320	r_dcache_tlb_cache_way("r_dcache_tlb_cache_way"),
321	r_dcache_tlb_cache_set("r_dcache_tlb_cache_set"),
322	r_dcache_tlb_cache_word("r_dcache_tlb_cache_word"),
323	r_dcache_tlb_way("r_dcache_tlb_way"),
324	r_dcache_tlb_set("r_dcache_tlb_set"),
325
326	r_dcache_tlb_inval_line("r_dcache_tlb_inval_line"),
327	r_dcache_tlb_inval_set("r_dcache_tlb_inval_set"),
328
329	r_dcache_xtn_req("r_dcache_xtn_req"),
330	r_dcache_xtn_opcode("r_dcache_xtn_opcode"),
331
332	r_dcache_cc_send_req("r_dcache_cc_send_req"),
333	r_dcache_cc_send_type("r_dcache_cc_send_type"),
334	r_dcache_cc_send_nline("r_dcache_cc_send_nline"),
335	r_dcache_cc_send_way("r_dcache_cc_send_way"),
336	r_dcache_cc_send_updt_tab_idx("r_dcache_cc_send_updt_tab_idx"),
337
338	r_vci_cmd_fsm("r_vci_cmd_fsm"),
339	r_vci_cmd_min("r_vci_cmd_min"),
340	r_vci_cmd_max("r_vci_cmd_max"),
341	r_vci_cmd_cpt("r_vci_cmd_cpt"),
342	r_vci_cmd_imiss_prio("r_vci_cmd_imiss_prio"),
343
344	r_vci_rsp_fsm("r_vci_rsp_fsm"),
345	r_vci_rsp_cpt("r_vci_rsp_cpt"),
346	r_vci_rsp_ins_error("r_vci_rsp_ins_error"),
347	r_vci_rsp_data_error("r_vci_rsp_data_error"),
348	r_vci_rsp_fifo_icache("r_vci_rsp_fifo_icache", 2), // 2 words depth
349	r_vci_rsp_fifo_dcache("r_vci_rsp_fifo_dcache", 2), // 2 words depth
350
351	r_cc_send_fsm("r_cc_send_fsm"),
352	r_cc_send_last_client("r_cc_send_last_client"),
353
354	r_cc_receive_fsm("r_cc_receive_fsm"),
355	r_cc_receive_data_ins("r_cc_receive_data_ins"),
356	r_cc_receive_word_idx("r_cc_receive_word_idx"),
357	r_cc_receive_updt_fifo_be("r_cc_receive_updt_fifo_be", 2), // 2 words depth
358	r_cc_receive_updt_fifo_data("r_cc_receive_updt_fifo_data", 2), // 2 words depth
359	r_cc_receive_updt_fifo_eop("r_cc_receive_updt_fifo_eop", 2), // 2 words depth
360
361	r_cc_receive_icache_req("r_cc_receive_icache_req"),
362	r_cc_receive_icache_type("r_cc_receive_icache_type"),
363	r_cc_receive_icache_way("r_cc_receive_icache_way"),
364	r_cc_receive_icache_set("r_cc_receive_icache_set"),
365	r_cc_receive_icache_updt_tab_idx("r_cc_receive_icache_updt_tab_idx"),
366	r_cc_receive_icache_nline("r_cc_receive_icache_nline"),
367
368	r_cc_receive_dcache_req("r_cc_receive_dcache_req"),
369	r_cc_receive_dcache_type("r_cc_receive_dcache_type"),
370	r_cc_receive_dcache_way("r_cc_receive_dcache_way"),
371	r_cc_receive_dcache_set("r_cc_receive_dcache_set"),
372	r_cc_receive_dcache_updt_tab_idx("r_cc_receive_dcache_updt_tab_idx"),
373	r_cc_receive_dcache_nline("r_cc_receive_dcache_nline"),
374
375	r_iss(this->name(), proc_id),
376	r_wbuf("wbuf", wbuf_nwords, wbuf_nlines, dcache_words ),
377	r_icache("icache", icache_ways, icache_sets, icache_words),
378	r_dcache("dcache", dcache_ways, dcache_sets, dcache_words),
379	r_itlb("itlb", proc_id, itlb_ways,itlb_sets,vci_param::N),
380	r_dtlb("dtlb", proc_id, dtlb_ways,dtlb_sets,vci_param::N)
381	{
382	std::cout << " - Building VciCcVcacheWrapper : " << name << std::endl;
383
384	assert( ((icache_words*vci_param::B) < (1<<vci_param::K)) and
385	"Need more PLEN bits.");
386
387	assert( (vci_param::T > 2) and ((1<<(vci_param::T-1)) >= (wbuf_nlines)) and
388	"Need more TRDID bits.");
389
390	assert( (icache_words == dcache_words) and
391	"icache_words and dcache_words parameters must be equal");
392
393	assert( (itlb_sets == dtlb_sets) and
394	"itlb_sets and dtlb_sets parameters must be etqual");
395
396	assert( (itlb_ways == dtlb_ways) and
397	"itlb_ways and dtlb_ways parameters must be etqual");
398
399	r_mmu_params = (uint32_log2(m_dtlb_ways) << 29) \| (uint32_log2(m_dtlb_sets) << 25) \|
400	(uint32_log2(m_dcache_ways) << 22) \| (uint32_log2(m_dcache_sets) << 18) \|
401	(uint32_log2(m_itlb_ways) << 15) \| (uint32_log2(m_itlb_sets) << 11) \|
402	(uint32_log2(m_icache_ways) << 8) \| (uint32_log2(m_icache_sets) << 4) \|
403	(uint32_log2(m_icache_words<<2));
404
405	r_mmu_release = (uint32_t)(1 << 16) \| 0x1;
406
407	r_dcache_in_tlb = new bool[dcache_ways*dcache_sets];
408	r_dcache_contains_ptd = new bool[dcache_ways*dcache_sets];
409
410	SC_METHOD(transition);
411	dont_initialize();
412	sensitive << p_clk.pos();
413
414	SC_METHOD(genMoore);
415	dont_initialize();
416	sensitive << p_clk.neg();
417
418	typename iss_t::CacheInfo cache_info;
419	cache_info.has_mmu = true;
420	cache_info.icache_line_size = icache_words*sizeof(uint32_t);
421	cache_info.icache_assoc = icache_ways;
422	cache_info.icache_n_lines = icache_sets;
423	cache_info.dcache_line_size = dcache_words*sizeof(uint32_t);
424	cache_info.dcache_assoc = dcache_ways;
425	cache_info.dcache_n_lines = dcache_sets;
426	r_iss.setCacheInfo(cache_info);
427	}
428
429	/////////////////////////////////////
430	tmpl(/**/)::~VciCcVCacheWrapper()
431	/////////////////////////////////////
432	{
433	delete [] r_dcache_in_tlb;
434	delete [] r_dcache_contains_ptd;
435	}
436
437	////////////////////////
438	tmpl(void)::print_cpi()
439	////////////////////////
440	{
441	std::cout << name() << " CPI = "
442	<< (float)m_cpt_total_cycles/(m_cpt_total_cycles - m_cpt_frz_cycles) << std::endl ;
443	}
444
445	////////////////////////////////////
446	tmpl(void)::print_trace(size_t mode)
447	////////////////////////////////////
448	{
449	// b0 : write buffer trace
450	// b1 : write buffer verbose
451	// b2 : dcache trace
452	// b3 : icache trace
453	// b4 : dtlb trace
454	// b5 : itlb trace
455
456	std::cout << std::dec << "PROC " << name() << std::endl;
457
458	std::cout << " " << m_ireq << std::endl;
459	std::cout << " " << m_irsp << std::endl;
460	std::cout << " " << m_dreq << std::endl;
461	std::cout << " " << m_drsp << std::endl;
462
463	std::cout << " " << icache_fsm_state_str[r_icache_fsm.read()]
464	<< " \| " << dcache_fsm_state_str[r_dcache_fsm.read()]
465	<< " \| " << cmd_fsm_state_str[r_vci_cmd_fsm.read()]
466	<< " \| " << rsp_fsm_state_str[r_vci_rsp_fsm.read()]
467	<< " \| " << cc_receive_fsm_state_str[r_cc_receive_fsm.read()]
468	<< " \| " << cc_send_fsm_state_str[r_cc_send_fsm.read()]
469	<< " \| MMU = " << r_mmu_mode.read();
470	if (r_dcache_updt_req.read() ) std::cout << " \| P1_UPDT";
471	if (r_dcache_wbuf_req.read() ) std::cout << " \| P1_WBUF";
472	std::cout << std::endl;
473
474	if(mode & 0x01)
475	{
476	r_wbuf.printTrace((mode>>1)&1);
477	}
478	if(mode & 0x04)
479	{
480	std::cout << " Data Cache" << std::endl;
481	r_dcache.printTrace();
482	}
483	if(mode & 0x08)
484	{
485	std::cout << " Instruction Cache" << std::endl;
486	r_icache.printTrace();
487	}
488	if(mode & 0x10)
489	{
490	std::cout << " Data TLB" << std::endl;
491	r_dtlb.printTrace();
492	}
493	if(mode & 0x20)
494	{
495	std::cout << " Instruction TLB" << std::endl;
496	r_itlb.printTrace();
497	}
498	}
499
500	//////////////////////////////////////////
501	tmpl(void)::cache_monitor( paddr_t addr )
502	//////////////////////////////////////////
503	{
504	bool cache_hit;
505	size_t cache_way = 0;
506	size_t cache_set = 0;
507	size_t cache_word = 0;
508	uint32_t cache_rdata = 0;
509
510	cache_hit = r_dcache.read_neutral( addr,
511	&cache_rdata,
512	&cache_way,
513	&cache_set,
514	&cache_word );
515
516	if ( cache_hit != m_debug_previous_d_hit )
517	{
518	std::cout << "Monitor PROC " << name()
519	<< " DCACHE at cycle " << std::dec << m_cpt_total_cycles
520	<< " / HIT = " << cache_hit
521	<< " / PADDR = " << std::hex << addr
522	<< " / DATA = " << cache_rdata
523	<< " / WAY = " << cache_way << std::endl;
524	m_debug_previous_d_hit = cache_hit;
525	}
526
527	cache_hit = r_icache.read_neutral( addr,
528	&cache_rdata,
529	&cache_way,
530	&cache_set,
531	&cache_word );
532
533	if ( cache_hit != m_debug_previous_i_hit )
534	{
535	std::cout << "Monitor PROC " << name()
536	<< " ICACHE at cycle " << std::dec << m_cpt_total_cycles
537	<< " / HIT = " << cache_hit
538	<< " / PADDR = " << std::hex << addr
539	<< " / DATA = " << cache_rdata
540	<< " / WAY = " << cache_way << std::endl;
541	m_debug_previous_i_hit = cache_hit;
542	}
543	}
544
545	/*
546	////////////////////////
547	tmpl(void)::print_stats()
548	////////////////////////
549	{
550	float run_cycles = (float)(m_cpt_total_cycles - m_cpt_frz_cycles);
551	std::cout << name() << std::endl
552	<< "- CPI = " << (float)m_cpt_total_cycles/run_cycles << std::endl
553	<< "- READ RATE = " << (float)m_cpt_read/run_cycles << std::endl
554	<< "- WRITE RATE = " << (float)m_cpt_write/run_cycles << std::endl
555	<< "- IMISS_RATE = " << (float)m_cpt_ins_miss/m_cpt_ins_read << std::endl
556	<< "- DMISS RATE = " << (float)m_cpt_data_miss/(m_cpt_read-m_cpt_unc_read) << std::endl
557	<< "- INS MISS COST = " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl
558	<< "- DATA MISS COST = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl
559	<< "- WRITE COST = " << (float)m_cost_write_frz/m_cpt_write << std::endl
560	<< "- UNC COST = " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl
561	<< "- UNCACHED READ RATE = " << (float)m_cpt_unc_read/m_cpt_read << std::endl
562	<< "- CACHED WRITE RATE = " << (float)m_cpt_write_cached/m_cpt_write << std::endl
563	<< "- INS TLB MISS RATE = " << (float)m_cpt_ins_tlb_miss/m_cpt_ins_tlb_read << std::endl
564	<< "- DATA TLB MISS RATE = " << (float)m_cpt_data_tlb_miss/m_cpt_data_tlb_read << std::endl
565	<< "- ITLB MISS COST = " << (float)m_cost_ins_tlb_miss_frz/m_cpt_ins_tlb_miss << std::endl
566	<< "- DTLB MISS COST = " << (float)m_cost_data_tlb_miss_frz/m_cpt_data_tlb_miss << std::endl
567	<< "- ITLB UPDATE ACC COST = " << (float)m_cost_ins_tlb_update_acc_frz/m_cpt_ins_tlb_update_acc << std::endl
568	<< "- DTLB UPDATE ACC COST = " << (float)m_cost_data_tlb_update_acc_frz/m_cpt_data_tlb_update_acc << std::endl
569	<< "- DTLB UPDATE DIRTY COST = " << (float)m_cost_data_tlb_update_dirty_frz/m_cpt_data_tlb_update_dirty << std::endl
570	<< "- ITLB HIT IN DCACHE RATE= " << (float)m_cpt_ins_tlb_hit_dcache/m_cpt_ins_tlb_miss << std::endl
571	<< "- DTLB HIT IN DCACHE RATE= " << (float)m_cpt_data_tlb_hit_dcache/m_cpt_data_tlb_miss << std::endl
572	<< "- DCACHE FROZEN BY ITLB = " << (float)m_cost_ins_tlb_occup_cache_frz/m_cpt_dcache_frz_cycles << std::endl
573	<< "- DCACHE FOR TLB % = " << (float)m_cpt_tlb_occup_dcache/(m_dcache_ways*m_dcache_sets) << std::endl
574	<< "- NB CC BROADCAST = " << m_cpt_cc_broadcast << std::endl
575	<< "- NB CC UPDATE DATA = " << m_cpt_cc_update_data << std::endl
576	<< "- NB CC INVAL DATA = " << m_cpt_cc_inval_data << std::endl
577	<< "- NB CC INVAL INS = " << m_cpt_cc_inval_ins << std::endl
578	<< "- CC BROADCAST COST = " << (float)m_cost_broadcast_frz/m_cpt_cc_broadcast << std::endl
579	<< "- CC UPDATE DATA COST = " << (float)m_cost_updt_data_frz/m_cpt_cc_update_data << std::endl
580	<< "- CC INVAL DATA COST = " << (float)m_cost_inval_data_frz/m_cpt_cc_inval_data << std::endl
581	<< "- CC INVAL INS COST = " << (float)m_cost_inval_ins_frz/m_cpt_cc_inval_ins << std::endl
582	<< "- NB CC CLEANUP DATA = " << m_cpt_cc_cleanup_data << std::endl
583	<< "- NB CC CLEANUP INS = " << m_cpt_cc_cleanup_ins << std::endl
584	<< "- IMISS TRANSACTION = " << (float)m_cost_imiss_transaction/m_cpt_imiss_transaction << std::endl
585	<< "- DMISS TRANSACTION = " << (float)m_cost_dmiss_transaction/m_cpt_dmiss_transaction << std::endl
586	<< "- UNC TRANSACTION = " << (float)m_cost_unc_transaction/m_cpt_unc_transaction << std::endl
587	<< "- WRITE TRANSACTION = " << (float)m_cost_write_transaction/m_cpt_write_transaction << std::endl
588	<< "- WRITE LENGTH = " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl
589	<< "- ITLB MISS TRANSACTION = " << (float)m_cost_itlbmiss_transaction/m_cpt_itlbmiss_transaction << std::endl
590	<< "- DTLB MISS TRANSACTION = " << (float)m_cost_dtlbmiss_transaction/m_cpt_dtlbmiss_transaction << std::endl;
591	}
592
593	////////////////////////
594	tmpl(void)::clear_stats()
595	////////////////////////
596	{
597	m_cpt_dcache_data_read = 0;
598	m_cpt_dcache_data_write = 0;
599	m_cpt_dcache_dir_read = 0;
600	m_cpt_dcache_dir_write = 0;
601	m_cpt_icache_data_read = 0;
602	m_cpt_icache_data_write = 0;
603	m_cpt_icache_dir_read = 0;
604	m_cpt_icache_dir_write = 0;
605
606	m_cpt_frz_cycles = 0;
607	m_cpt_dcache_frz_cycles = 0;
608	m_cpt_total_cycles = 0;
609
610	m_cpt_read = 0;
611	m_cpt_write = 0;
612	m_cpt_data_miss = 0;
613	m_cpt_ins_miss = 0;
614	m_cpt_unc_read = 0;
615	m_cpt_write_cached = 0;
616	m_cpt_ins_read = 0;
617
618	m_cost_write_frz = 0;
619	m_cost_data_miss_frz = 0;
620	m_cost_unc_read_frz = 0;
621	m_cost_ins_miss_frz = 0;
622
623	m_cpt_imiss_transaction = 0;
624	m_cpt_dmiss_transaction = 0;
625	m_cpt_unc_transaction = 0;
626	m_cpt_write_transaction = 0;
627	m_cpt_icache_unc_transaction = 0;
628
629	m_cost_imiss_transaction = 0;
630	m_cost_dmiss_transaction = 0;
631	m_cost_unc_transaction = 0;
632	m_cost_write_transaction = 0;
633	m_cost_icache_unc_transaction = 0;
634	m_length_write_transaction = 0;
635
636	m_cpt_ins_tlb_read = 0;
637	m_cpt_ins_tlb_miss = 0;
638	m_cpt_ins_tlb_update_acc = 0;
639
640	m_cpt_data_tlb_read = 0;
641	m_cpt_data_tlb_miss = 0;
642	m_cpt_data_tlb_update_acc = 0;
643	m_cpt_data_tlb_update_dirty = 0;
644	m_cpt_ins_tlb_hit_dcache = 0;
645	m_cpt_data_tlb_hit_dcache = 0;
646	m_cpt_ins_tlb_occup_cache = 0;
647	m_cpt_data_tlb_occup_cache = 0;
648
649	m_cost_ins_tlb_miss_frz = 0;
650	m_cost_data_tlb_miss_frz = 0;
651	m_cost_ins_tlb_update_acc_frz = 0;
652	m_cost_data_tlb_update_acc_frz = 0;
653	m_cost_data_tlb_update_dirty_frz = 0;
654	m_cost_ins_tlb_occup_cache_frz = 0;
655	m_cost_data_tlb_occup_cache_frz = 0;
656
657	m_cpt_itlbmiss_transaction = 0;
658	m_cpt_itlb_ll_transaction = 0;
659	m_cpt_itlb_sc_transaction = 0;
660	m_cpt_dtlbmiss_transaction = 0;
661	m_cpt_dtlb_ll_transaction = 0;
662	m_cpt_dtlb_sc_transaction = 0;
663	m_cpt_dtlb_ll_dirty_transaction = 0;
664	m_cpt_dtlb_sc_dirty_transaction = 0;
665
666	m_cost_itlbmiss_transaction = 0;
667	m_cost_itlb_ll_transaction = 0;
668	m_cost_itlb_sc_transaction = 0;
669	m_cost_dtlbmiss_transaction = 0;
670	m_cost_dtlb_ll_transaction = 0;
671	m_cost_dtlb_sc_transaction = 0;
672	m_cost_dtlb_ll_dirty_transaction = 0;
673	m_cost_dtlb_sc_dirty_transaction = 0;
674
675	m_cpt_cc_update_data = 0;
676	m_cpt_cc_inval_ins = 0;
677	m_cpt_cc_inval_data = 0;
678	m_cpt_cc_broadcast = 0;
679
680	m_cost_updt_data_frz = 0;
681	m_cost_inval_ins_frz = 0;
682	m_cost_inval_data_frz = 0;
683	m_cost_broadcast_frz = 0;
684
685	m_cpt_cc_cleanup_data = 0;
686	m_cpt_cc_cleanup_ins = 0;
687	}
688
689	*/
690
691	/////////////////////////
692	tmpl(void)::transition()
693	/////////////////////////
694	{
695	if ( not p_resetn.read() )
696	{
697	r_iss.reset();
698	r_wbuf.reset();
699	r_icache.reset();
700	r_dcache.reset();
701	r_itlb.reset();
702	r_dtlb.reset();
703
704	r_dcache_fsm = DCACHE_IDLE;
705	r_icache_fsm = ICACHE_IDLE;
706	r_vci_cmd_fsm = CMD_IDLE;
707	r_vci_rsp_fsm = RSP_IDLE;
708	r_cc_receive_fsm = CC_RECEIVE_IDLE;
709	r_cc_send_fsm = CC_SEND_IDLE;
710
711	// reset data physical address extension
712	r_dcache_paddr_ext = 0;
713
714	// reset dcache directory extension
715	for (size_t i=0 ; i< m_dcache_ways*m_dcache_sets ; i++)
716	{
717	r_dcache_in_tlb[i] = false;
718	r_dcache_contains_ptd[i] = false;
719	}
720
721	// Response FIFOs and cleanup buffer
722	r_vci_rsp_fifo_icache.init();
723	r_vci_rsp_fifo_dcache.init();
724
725	// ICACHE & DCACHE activated
726	// ITLB & DTLB desactivated
727	r_mmu_mode = 0x3;
728
729	// No request from ICACHE FSM to CMD FSM
730	r_icache_miss_req = false;
731	r_icache_unc_req = false;
732
733	// No request from ICACHE_FSM to DCACHE FSM
734	r_icache_tlb_miss_req = false;
735
736	// No request from ICACHE_FSM to CC_SEND FSM
737	r_icache_cc_send_req = false;
738
739	// No pending write in pipeline
740	r_dcache_wbuf_req = false;
741	r_dcache_updt_req = false;
742
743	// No request from DCACHE_FSM to CMD_FSM
744	r_dcache_vci_miss_req = false;
745	r_dcache_vci_unc_req = false;
746	r_dcache_vci_cas_req = false;
747	r_dcache_vci_ll_req = false;
748	r_dcache_vci_sc_req = false;
749
750	// No uncacheable write pending
751	r_dcache_pending_unc_write = false;
752
753	// No processor XTN request pending
754	r_dcache_xtn_req = false;
755
756	// No request from DCACHE FSM to CC_SEND FSM
757	r_dcache_cc_send_req = false;
758
759	// No request from CC_RECEIVE FSM to ICACHE/DCACHE FSMs
760	r_cc_receive_icache_req = false;
761	r_cc_receive_dcache_req = false;
762
763	// last cc_send client was dcache
764	r_cc_send_last_client = false;
765
766	// No pending cleanup after a replacement
767	r_icache_miss_clack = false;
768	r_dcache_miss_clack = false;
769
770	// No signalisation of a coherence request matching a pending miss
771	r_icache_miss_inval = false;
772	r_dcache_miss_inval = false;
773
774	// No signalisation of errors
775	r_vci_rsp_ins_error = false;
776	r_vci_rsp_data_error = false;
777
778	// Debug variables
779	m_debug_previous_i_hit = false;
780	m_debug_previous_d_hit = false;
781	m_debug_activated = false;
782
783	// activity counters
784	m_cpt_dcache_data_read = 0;
785	m_cpt_dcache_data_write = 0;
786	m_cpt_dcache_dir_read = 0;
787	m_cpt_dcache_dir_write = 0;
788	m_cpt_icache_data_read = 0;
789	m_cpt_icache_data_write = 0;
790	m_cpt_icache_dir_read = 0;
791	m_cpt_icache_dir_write = 0;
792
793	m_cpt_frz_cycles = 0;
794	m_cpt_total_cycles = 0;
795	m_cpt_stop_simulation = 0;
796
797	m_cpt_data_miss = 0;
798	m_cpt_ins_miss = 0;
799	m_cpt_unc_read = 0;
800	m_cpt_write_cached = 0;
801	m_cpt_ins_read = 0;
802
803	m_cost_write_frz = 0;
804	m_cost_data_miss_frz = 0;
805	m_cost_unc_read_frz = 0;
806	m_cost_ins_miss_frz = 0;
807
808	m_cpt_imiss_transaction = 0;
809	m_cpt_dmiss_transaction = 0;
810	m_cpt_unc_transaction = 0;
811	m_cpt_write_transaction = 0;
812	m_cpt_icache_unc_transaction = 0;
813
814	m_cost_imiss_transaction = 0;
815	m_cost_dmiss_transaction = 0;
816	m_cost_unc_transaction = 0;
817	m_cost_write_transaction = 0;
818	m_cost_icache_unc_transaction = 0;
819	m_length_write_transaction = 0;
820
821	m_cpt_ins_tlb_read = 0;
822	m_cpt_ins_tlb_miss = 0;
823	m_cpt_ins_tlb_update_acc = 0;
824
825	m_cpt_data_tlb_read = 0;
826	m_cpt_data_tlb_miss = 0;
827	m_cpt_data_tlb_update_acc = 0;
828	m_cpt_data_tlb_update_dirty = 0;
829	m_cpt_ins_tlb_hit_dcache = 0;
830	m_cpt_data_tlb_hit_dcache = 0;
831	m_cpt_ins_tlb_occup_cache = 0;
832	m_cpt_data_tlb_occup_cache = 0;
833
834	m_cost_ins_tlb_miss_frz = 0;
835	m_cost_data_tlb_miss_frz = 0;
836	m_cost_ins_tlb_update_acc_frz = 0;
837	m_cost_data_tlb_update_acc_frz = 0;
838	m_cost_data_tlb_update_dirty_frz = 0;
839	m_cost_ins_tlb_occup_cache_frz = 0;
840	m_cost_data_tlb_occup_cache_frz = 0;
841
842	m_cpt_ins_tlb_inval = 0;
843	m_cpt_data_tlb_inval = 0;
844	m_cost_ins_tlb_inval_frz = 0;
845	m_cost_data_tlb_inval_frz = 0;
846
847	m_cpt_cc_broadcast = 0;
848
849	m_cost_updt_data_frz = 0;
850	m_cost_inval_ins_frz = 0;
851	m_cost_inval_data_frz = 0;
852	m_cost_broadcast_frz = 0;
853
854	m_cpt_cc_cleanup_data = 0;
855	m_cpt_cc_cleanup_ins = 0;
856
857	m_cpt_itlbmiss_transaction = 0;
858	m_cpt_itlb_ll_transaction = 0;
859	m_cpt_itlb_sc_transaction = 0;
860	m_cpt_dtlbmiss_transaction = 0;
861	m_cpt_dtlb_ll_transaction = 0;
862	m_cpt_dtlb_sc_transaction = 0;
863	m_cpt_dtlb_ll_dirty_transaction = 0;
864	m_cpt_dtlb_sc_dirty_transaction = 0;
865
866	m_cost_itlbmiss_transaction = 0;
867	m_cost_itlb_ll_transaction = 0;
868	m_cost_itlb_sc_transaction = 0;
869	m_cost_dtlbmiss_transaction = 0;
870	m_cost_dtlb_ll_transaction = 0;
871	m_cost_dtlb_sc_transaction = 0;
872	m_cost_dtlb_ll_dirty_transaction = 0;
873	m_cost_dtlb_sc_dirty_transaction = 0;
874	/*
875	m_cpt_dcache_frz_cycles = 0;
876	m_cpt_read = 0;
877	m_cpt_write = 0;
878	m_cpt_cc_update_data = 0;
879	m_cpt_cc_inval_ins = 0;
880	m_cpt_cc_inval_data = 0;
881	*/
882
883	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_icache [i] = 0;
884	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_dcache [i] = 0;
885	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_cmd [i] = 0;
886	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_rsp [i] = 0;
887
888	// init the llsc reservation buffer
889	r_dcache_llsc_valid = false;
890
891	return;
892	}
893
894	// Response FIFOs default values
895	bool vci_rsp_fifo_icache_get = false;
896	bool vci_rsp_fifo_icache_put = false;
897	uint32_t vci_rsp_fifo_icache_data = 0;
898
899	bool vci_rsp_fifo_dcache_get = false;
900	bool vci_rsp_fifo_dcache_put = false;
901	uint32_t vci_rsp_fifo_dcache_data = 0;
902
903	// updt fifo
904	bool cc_receive_updt_fifo_get = false;
905	bool cc_receive_updt_fifo_put = false;
906	uint32_t cc_receive_updt_fifo_be = 0;
907	uint32_t cc_receive_updt_fifo_data = 0;
908	bool cc_receive_updt_fifo_eop = false;
909
910	#ifdef INSTRUMENTATION
911	m_cpt_fsm_dcache [r_dcache_fsm.read() ] ++;
912	m_cpt_fsm_icache [r_icache_fsm.read() ] ++;
913	m_cpt_fsm_cmd [r_vci_cmd_fsm.read()] ++;
914	m_cpt_fsm_rsp [r_vci_rsp_fsm.read()] ++;
915	m_cpt_fsm_tgt [r_tgt_fsm.read() ] ++;
916	m_cpt_fsm_cleanup [r_cleanup_cmd_fsm.read()] ++;
917	#endif
918
919	m_cpt_total_cycles++;
920
921	m_debug_activated = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok;
922
923	/////////////////////////////////////////////////////////////////////
924	// Get data and instruction requests from processor
925	///////////////////////////////////////////////////////////////////////
926
927	r_iss.getRequests(m_ireq, m_dreq);
928
929	////////////////////////////////////////////////////////////////////////////////////
930	// ICACHE_FSM
931	//
932	// 1/ Coherence operations
933	// They are handled as interrupts generated by the CC_RECEIVE FSM.
934	// - There is a coherence request when r_tgt_icache_req is set.
935	// They are taken in IDLE, MISS_WAIT, MISS_DIR_UPDT, UNC_WAIT, states.
936	// - There is a cleanup ack request when r_cleanup_icache_req is set.
937	// They are taken in IDLE, MISS_SELECT, MISS_CLEAN, MISS_WAIT,
938	// MISS_DATA_UPDT, MISS_DIR_UPDT and UNC_WAIT states.
939	// - For both types of requests, actions associated to the pre-empted state
940	// are not executed. The DCACHE FSM goes to the proper sub-FSM (CC_CHECK
941	// or CC_CLACK) to execute the requested coherence operation, and returns
942	// to the pre-empted state.
943	//
944	// 2/ Processor requests
945	// They are taken in IDLE state only. In case of cache miss, or uncacheable
946	// instruction, the ICACHE FSM request a VCI transaction to CMD FSM,
947	// using the r_icache_miss_req or r_icache_unc_req flip-flops. These
948	// flip-flops are reset when the transaction starts.
949	// - In case of miss the ICACHE FSM goes to the ICACHE_MISS_SELECT state
950	// to select a slot and possibly request a cleanup transaction to the CC_SEND FSM.
951	// It goes next to the ICACHE_MISS_WAIT state waiting a response from RSP FSM,
952	// The availability of the missing cache line is signaled by the response fifo,
953	// and the cache update is done (one word per cycle) in the ICACHE_MISS_DATA_UPDT
954	// and ICACHE_MISS_DIR_UPDT states.
955	// - In case of uncacheable instruction, the ICACHE FSM goes to ICACHE_UNC_WAIT
956	// to wait the response from the RSP FSM, through the response fifo.
957	// The missing instruction is directly returned to processor in this state.
958	//
959	// 3/ TLB miss
960	// In case of tlb miss, the ICACHE FSM request to the DCACHE FSM to update the
961	// ITLB using the r_icache_tlb_miss_req flip-flop and the r_icache_tlb_miss_vaddr
962	// register, and goes to the ICACHE_TLB_WAIT state.
963	// The tlb update is entirely done by the DCACHE FSM (who becomes the owner
964	// of ITLB until the update is completed, and reset r_icache_tlb_miss_req
965	// to signal the completion.
966	//
967	// 4/ XTN requests
968	// The DCACHE FSM signals XTN processor requests to ICACHE_FSM
969	// using the r_dcache_xtn_req flip-flop.
970	// The request opcode and the address to be invalidated are transmitted
971	// in the r_dcache_xtn_opcode and r_dcache_save_wdata registers respectively.
972	// The r_dcache_xtn_req flip-flop is reset by the ICACHE_FSM when the operation
973	// is completed.
974	//
975	// 5/ Error Handling
976	// The r_vci_rsp_ins_error flip-flop is set by the RSP FSM in case of bus error
977	// in a cache miss or uncacheable read VCI transaction. Nothing is written
978	// in the response fifo. This flip-flop is reset by the ICACHE-FSM.
979	////////////////////////////////////////////////////////////////////////////////////////
980
981	// default value for m_irsp
982	m_irsp.valid = false;
983	m_irsp.error = false;
984	m_irsp.instruction = 0;
985
986	switch( r_icache_fsm.read() )
987	{
988	/////////////////
989	case ICACHE_IDLE: // In this state, we handle processor requests, XTN requests,
990	// and coherence requests with a fixed priority:
991	// 1/ Coherence requests => ICACHE_CC_CHECK
992	// 2/ XTN processor requests (from DCACHE FSM) => ICACHE_XTN_*
993	// 3/ tlb miss => ICACHE_TLB_WAIT
994	// 4/ cacheable read miss => ICACHE_MISS_SELECT
995	// 5/ uncacheable read miss => ICACHE_UNC_REQ
996	{
997	// coherence interrupt
998	if ( r_cc_receive_icache_req.read() )
999	{
1000	r_icache_fsm = ICACHE_CC_CHECK;
1001	r_icache_fsm_save = r_icache_fsm.read();
1002	break;
1003	}
1004
1005	// XTN requests sent by DCACHE FSM
1006	// These request are not executed in this IDLE state, because
1007	// they require access to icache or itlb, that are already accessed
1008	if ( r_dcache_xtn_req.read() )
1009	{
1010	if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_PTPR )
1011	{
1012	r_icache_fsm = ICACHE_XTN_TLB_FLUSH;
1013	}
1014	else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ICACHE_FLUSH)
1015	{
1016	r_icache_flush_count = 0;
1017	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH;
1018	}
1019	else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ITLB_INVAL)
1020	{
1021	r_icache_fsm = ICACHE_XTN_TLB_INVAL;
1022	}
1023	else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ICACHE_INVAL)
1024	{
1025	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_VA;
1026	}
1027	else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_MMU_ICACHE_PA_INV)
1028	{
1029	if (sizeof(paddr_t) <= 32)
1030	{
1031	assert(r_mmu_word_hi.read() == 0 &&
1032	"illegal XTN request in ICACHE: high bits should be 0 for 32bit paddr");
1033	r_icache_vci_paddr = (paddr_t)r_mmu_word_lo.read();
1034	}
1035	else
1036	{
1037	r_icache_vci_paddr = (paddr_t)r_mmu_word_hi.read() << 32 \|
1038	(paddr_t)r_mmu_word_lo.read();
1039	}
1040	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA;
1041	}
1042	else
1043	{
1044	assert( false and
1045	"undefined XTN request received by ICACHE FSM");
1046	}
1047	break;
1048	} // end if xtn_req
1049
1050	// processor request
1051	if ( m_ireq.valid )
1052	{
1053	bool cacheable;
1054	paddr_t paddr;
1055	bool tlb_hit = false;
1056	pte_info_t tlb_flags;
1057	size_t tlb_way;
1058	size_t tlb_set;
1059	paddr_t tlb_nline;
1060	uint32_t cache_inst = 0;
1061	size_t cache_way;
1062	size_t cache_set;
1063	size_t cache_word;
1064	int cache_state = CACHE_SLOT_STATE_EMPTY;
1065
1066	// We register processor request
1067	r_icache_vaddr_save = m_ireq.addr;
1068
1069	// sytematic itlb access (if activated)
1070	if ( r_mmu_mode.read() & INS_TLB_MASK )
1071	{
1072
1073	#ifdef INSTRUMENTATION
1074	m_cpt_itlb_read++;
1075	#endif
1076	tlb_hit = r_itlb.translate( m_ireq.addr,
1077	&paddr,
1078	&tlb_flags,
1079	&tlb_nline, // unused
1080	&tlb_way, // unused
1081	&tlb_set ); // unused
1082	}
1083	else
1084	{
1085	paddr = (paddr_t)m_ireq.addr;
1086	}
1087
1088	// systematic icache access (if activated)
1089	if ( r_mmu_mode.read() & INS_CACHE_MASK )
1090	{
1091
1092
1093	#ifdef INSTRUMENTATION
1094	m_cpt_icache_data_read++;
1095	m_cpt_icache_dir_read++;
1096	#endif
1097	r_icache.read( paddr,
1098	&cache_inst,
1099	&cache_way,
1100	&cache_set,
1101	&cache_word,
1102	&cache_state );
1103	}
1104
1105	// We compute cacheability and check access rights:
1106	// - If MMU activated : cacheability is defined by the C bit in the PTE,
1107	// and the access rights are defined by the U and X bits in the PTE.
1108	// - If MMU not activated : cacheability is defined by the segment table,
1109	// and there is no access rights checking
1110
1111	if ( not (r_mmu_mode.read() & INS_TLB_MASK) ) // tlb not activated:
1112	{
1113	// cacheability
1114	if ( not (r_mmu_mode.read() & INS_CACHE_MASK) ) cacheable = false;
1115	else cacheable = m_cacheability_table[m_ireq.addr];
1116	}
1117	else // itlb activated
1118	{
1119	if ( tlb_hit ) // ITLB hit
1120	{
1121	// cacheability
1122	if ( not (r_mmu_mode.read() & INS_CACHE_MASK) ) cacheable = false;
1123	else cacheable = tlb_flags.c;
1124
1125	// access rights checking
1126	if ( not tlb_flags.u && (m_ireq.mode == iss_t::MODE_USER) )
1127	{
1128	r_mmu_ietr = MMU_READ_PRIVILEGE_VIOLATION;
1129	r_mmu_ibvar = m_ireq.addr;
1130	m_irsp.valid = true;
1131	m_irsp.error = true;
1132	m_irsp.instruction = 0;
1133	break;
1134	}
1135	else if ( not tlb_flags.x )
1136	{
1137	r_mmu_ietr = MMU_READ_EXEC_VIOLATION;
1138	r_mmu_ibvar = m_ireq.addr;
1139	m_irsp.valid = true;
1140	m_irsp.error = true;
1141	m_irsp.instruction = 0;
1142	break;
1143	}
1144	}
1145	else // ITLB miss
1146	{
1147
1148	#ifdef INSTRUMENTATION
1149	m_cpt_itlb_miss++;
1150	#endif
1151	r_icache_fsm = ICACHE_TLB_WAIT;
1152	r_icache_tlb_miss_req = true;
1153	break;
1154	}
1155	} // end if itlb activated
1156
1157	// physical address registration
1158	r_icache_vci_paddr = paddr;
1159
1160	// Finally, we send the response to processor, and compute next state
1161	if ( cacheable )
1162	{
1163	if (cache_state == CACHE_SLOT_STATE_EMPTY) // cache miss
1164	{
1165
1166	#ifdef INSTRUMENTATION
1167	m_cpt_icache_miss++;
1168	#endif
1169	// we request a VCI transaction
1170	r_icache_fsm = ICACHE_MISS_SELECT;
1171	#if DEBUG_ICACHE
1172	if ( m_debug_activated )
1173	std::cout << " <PROC " << name() << " ICACHE_IDLE> READ MISS in icache"
1174	<< " : PADDR = " << std::hex << paddr << std::endl;
1175	#endif
1176	r_icache_miss_req = true;
1177	}
1178	else if (cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup
1179	{
1180	// stalled until cleanup is acknowledged
1181	r_icache_fsm = ICACHE_IDLE;
1182	}
1183	else // cache hit
1184	{
1185
1186	#ifdef INSTRUMENTATION
1187	m_cpt_ins_read++;
1188	#endif
1189	// return instruction to processor
1190	m_irsp.valid = true;
1191	m_irsp.instruction = cache_inst;
1192	r_icache_fsm = ICACHE_IDLE;
1193	#if DEBUG_ICACHE
1194	if ( m_debug_activated )
1195	std::cout << " <PROC " << name() << " ICACHE_IDLE> READ HIT in icache"
1196	<< " : PADDR = " << std::hex << paddr << std::endl;
1197	#endif
1198	}
1199	}
1200	else // non cacheable read
1201	{
1202	r_icache_unc_req = true;
1203	r_icache_fsm = ICACHE_UNC_WAIT;
1204
1205	#if DEBUG_ICACHE
1206	if ( m_debug_activated )
1207	{
1208	std::cout << " <PROC " << name()
1209	<< " ICACHE_IDLE> READ UNCACHEABLE in icache"
1210	<< " : PADDR = " << std::hex << paddr << std::endl;
1211	}
1212	#endif
1213	}
1214	} // end if m_ireq.valid
1215	break;
1216	}
1217	/////////////////////
1218	case ICACHE_TLB_WAIT: // Waiting the itlb update by the DCACHE FSM after a tlb miss
1219	// the itlb is udated by the DCACHE FSM, as well as the
1220	// r_mmu_ietr and r_mmu_ibvar registers in case of error.
1221	// the itlb is not accessed by ICACHE FSM until DCACHE FSM
1222	// reset the r_icache_tlb_miss_req flip-flop
1223	// external coherence request are accepted in this state.
1224	{
1225	// coherence interrupt
1226	if ( r_cc_receive_icache_req.read() )
1227	{
1228	r_icache_fsm = ICACHE_CC_CHECK;
1229	r_icache_fsm_save = r_icache_fsm.read();
1230	break;
1231	}
1232
1233	if ( m_ireq.valid ) m_cost_ins_tlb_miss_frz++;
1234
1235	// DCACHE FSM signals response by reseting the request flip-flop
1236	if ( not r_icache_tlb_miss_req.read() )
1237	{
1238	if ( r_icache_tlb_rsp_error.read() ) // error reported : tlb not updated
1239	{
1240	r_icache_tlb_rsp_error = false;
1241	m_irsp.error = true;
1242	m_irsp.valid = true;
1243	r_icache_fsm = ICACHE_IDLE;
1244	}
1245	else // tlb updated : return to IDLE state
1246	{
1247	r_icache_fsm = ICACHE_IDLE;
1248	}
1249	}
1250	break;
1251	}
1252	//////////////////////////
1253	case ICACHE_XTN_TLB_FLUSH: // invalidate in one cycle all non global TLB entries
1254	{
1255	r_itlb.flush();
1256	r_dcache_xtn_req = false;
1257	r_icache_fsm = ICACHE_IDLE;
1258	break;
1259	}
1260	////////////////////////////
1261	case ICACHE_XTN_CACHE_FLUSH: // Invalidate sequencially all cache lines, using
1262	// r_icache_flush_count as a slot counter,
1263	// looping in this state until all slots are visited.
1264	// It can require two cycles per slot:
1265	// We test here the slot state, and make the actual inval
1266	// (if line is valid) in ICACHE_XTN_CACHE_FLUSH_GO state.
1267	// A cleanup request is generated for each valid line
1268	{
1269	// coherence request (from CC_RECEIVE FSM)
1270	if ( r_cc_receive_icache_req.read() )
1271	{
1272	r_icache_fsm = ICACHE_CC_CHECK;
1273	r_icache_fsm_save = r_icache_fsm.read();
1274	break;
1275	}
1276
1277	if ( not r_icache_cc_send_req.read() ) // blocked until previous cc_send request is sent
1278	{
1279	int state;
1280	paddr_t tag;
1281	size_t way = r_icache_flush_count.read()/m_icache_sets;
1282	size_t set = r_icache_flush_count.read()%m_icache_sets;
1283
1284	#ifdef INSTRUMENTATION
1285	m_cpt_icache_dir_read++;
1286	#endif
1287	r_icache.read_dir( way,
1288	set,
1289	&tag,
1290	&state );
1291
1292	if ( state == CACHE_SLOT_STATE_VALID ) // inval required
1293	{
1294	// request cleanup
1295	r_icache_cc_send_req = true;
1296	r_icache_cc_send_nline = tag * m_icache_sets + set;
1297	r_icache_cc_send_way = way;
1298	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1299
1300	// goes to ICACHE_XTN_CACHE_FLUSH_GO to make inval
1301	r_icache_miss_way = way;
1302	r_icache_miss_set = set;
1303	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH_GO;
1304	}
1305	else if ( r_icache_flush_count.read() ==
1306	(m_icache_sets*m_icache_ways - 1) ) // last slot
1307	{
1308	r_dcache_xtn_req = false;
1309	m_drsp.valid = true;
1310	r_icache_fsm = ICACHE_IDLE;
1311	}
1312
1313	// saturation counter, to have the same last slot condition
1314	// in ICACHE_XTN_CACHE_FLUSH and ICACHE_XTN_CACHE_FLUSH_GO states
1315	if ( r_icache_flush_count.read() < (m_icache_sets*m_icache_ways - 1) )
1316	{
1317	r_icache_flush_count = r_icache_flush_count.read() + 1;
1318	}
1319	}
1320	break;
1321	}
1322	///////////////////////////////
1323	case ICACHE_XTN_CACHE_FLUSH_GO: // Switch slot state to ZOMBI for an XTN flush
1324	{
1325	size_t way = r_icache_miss_way.read();
1326	size_t set = r_icache_miss_set.read();
1327
1328	#ifdef INSTRUMENTATION
1329	m_cpt_icache_dir_write++;
1330	#endif
1331
1332	r_icache.write_dir( way,
1333	set,
1334	CACHE_SLOT_STATE_ZOMBI );
1335
1336	if ( r_icache_flush_count.read() ==
1337	(m_icache_sets*m_icache_ways - 1) ) // last slot
1338	{
1339	r_dcache_xtn_req = false;
1340	m_drsp.valid = true;
1341	r_icache_fsm = ICACHE_IDLE;
1342	}
1343	else
1344	{
1345	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH;
1346	}
1347	break;
1348	}
1349
1350	//////////////////////////
1351	case ICACHE_XTN_TLB_INVAL: // invalidate one TLB entry selected by the virtual address
1352	// stored in the r_dcache_save_wdata register
1353	{
1354	r_itlb.inval(r_dcache_save_wdata.read());
1355	r_dcache_xtn_req = false;
1356	r_icache_fsm = ICACHE_IDLE;
1357	break;
1358	}
1359	///////////////////////////////
1360	case ICACHE_XTN_CACHE_INVAL_VA: // Selective cache line invalidate with virtual address
1361	// requires 3 cycles (in case of hit on itlb and icache).
1362	// In this state, access TLB to translate virtual address
1363	// stored in the r_dcache_save_wdata register.
1364	{
1365	paddr_t paddr;
1366	bool hit;
1367
1368	// read physical address in TLB when MMU activated
1369	if ( r_mmu_mode.read() & INS_TLB_MASK ) // itlb activated
1370	{
1371
1372	#ifdef INSTRUMENTATION
1373	m_cpt_itlb_read++;
1374	#endif
1375	hit = r_itlb.translate(r_dcache_save_wdata.read(),
1376	&paddr);
1377	}
1378	else // itlb not activated
1379	{
1380	paddr = (paddr_t)r_dcache_save_wdata.read();
1381	hit = true;
1382	}
1383
1384	if ( hit ) // continue the selective inval process
1385	{
1386	r_icache_vci_paddr = paddr;
1387	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA;
1388	}
1389	else // miss : send a request to DCACHE FSM
1390	{
1391
1392	#ifdef INSTRUMENTATION
1393	m_cpt_itlb_miss++;
1394	#endif
1395	r_icache_tlb_miss_req = true;
1396	r_icache_vaddr_save = r_dcache_save_wdata.read();
1397	r_icache_fsm = ICACHE_TLB_WAIT;
1398	}
1399	break;
1400	}
1401	///////////////////////////////
1402	case ICACHE_XTN_CACHE_INVAL_PA: // selective invalidate cache line with physical address
1403	// require 2 cycles. In this state, we read directory
1404	// with address stored in r_icache_vci_paddr register.
1405	{
1406	int state;
1407	size_t way;
1408	size_t set;
1409	size_t word;
1410
1411	#ifdef INSTRUMENTATION
1412	m_cpt_icache_dir_read++;
1413	#endif
1414	r_icache.read_dir(r_icache_vci_paddr.read(),
1415	&state,
1416	&way,
1417	&set,
1418	&word);
1419
1420	if ( state == CACHE_SLOT_STATE_VALID ) // inval to be done
1421	{
1422	r_icache_miss_way = way;
1423	r_icache_miss_set = set;
1424	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_GO;
1425	}
1426	else // miss : acknowlege the XTN request and return
1427	{
1428	r_dcache_xtn_req = false;
1429	r_icache_fsm = ICACHE_IDLE;
1430	}
1431	break;
1432	}
1433	///////////////////////////////
1434	case ICACHE_XTN_CACHE_INVAL_GO: // Switch slot to ZOMBI state for an XTN inval
1435	{
1436	if ( not r_icache_cc_send_req.read() ) // blocked until previous cc_send request not sent
1437	{
1438
1439	#ifdef INSTRUMENTATION
1440	m_cpt_icache_dir_write++;
1441	#endif
1442	r_icache.write_dir( r_icache_miss_way.read(),
1443	r_icache_miss_set.read(),
1444	CACHE_SLOT_STATE_ZOMBI );
1445
1446	// request cleanup
1447	r_icache_cc_send_req = true;
1448	r_icache_cc_send_nline = r_icache_vci_paddr.read() / (m_icache_words<<2);
1449	r_icache_cc_send_way = r_icache_miss_way.read();
1450	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1451
1452	// acknowledge the XTN request and return
1453	r_dcache_xtn_req = false;
1454	r_icache_fsm = ICACHE_IDLE;
1455	}
1456	break;
1457	}
1458	////////////////////////
1459	case ICACHE_MISS_SELECT: // Try to select a slot in associative set,
1460	// if previous cleanup has been sent.
1461	// Waiting in this state if no slot available.
1462	// Set the r_icache_cleanup_req flip-flop
1463	// and the r_icache_miss_clack flip-flop,
1464	// when a cleanup is required
1465	{
1466	if (m_ireq.valid) m_cost_ins_miss_frz++;
1467
1468	// coherence interrupt
1469	if ( r_cc_receive_icache_req.read() )
1470	{
1471	r_icache_fsm = ICACHE_CC_CHECK;
1472	r_icache_fsm_save = r_icache_fsm.read();
1473	break;
1474	}
1475
1476	if ( not r_icache_cc_send_req.read() ) // wait for previous cc_send request to be sent
1477	{
1478	bool found;
1479	bool cleanup;
1480	size_t way;
1481	size_t set;
1482	paddr_t victim;
1483
1484	#ifdef INSTRUMENTATION
1485	m_cpt_icache_dir_read++;
1486	#endif
1487	r_icache.read_select(r_icache_vci_paddr.read(),
1488	&victim,
1489	&way,
1490	&set,
1491	&found,
1492	&cleanup );
1493	if ( found )
1494	{
1495	r_icache_miss_way = way;
1496	r_icache_miss_set = set;
1497
1498	if ( cleanup )
1499	{
1500	r_icache_fsm = ICACHE_MISS_CLEAN;
1501	r_icache_miss_clack = true;
1502	// request cleanup
1503	r_icache_cc_send_req = true;
1504	r_icache_cc_send_nline = victim;
1505	r_icache_cc_send_way = way;
1506	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1507	}
1508	else
1509	{
1510	r_icache_fsm = ICACHE_MISS_WAIT;
1511	}
1512
1513	#if DEBUG_ICACHE
1514	if ( m_debug_activated )
1515	{
1516	std::cout << " <PROC " << name()
1517	<< " ICACHE_MISS_SELECT> Select a slot:" << std::dec
1518	<< " / WAY = " << way
1519	<< " / SET = " << set;
1520	if (cleanup) std::cout << " / VICTIM = " << std::hex << victim << std::endl;
1521	else std::cout << std::endl;
1522	}
1523	#endif
1524	}
1525	}
1526	break;
1527	}
1528	///////////////////////
1529	case ICACHE_MISS_CLEAN: // switch the slot to zombi state
1530	{
1531	if (m_ireq.valid) m_cost_ins_miss_frz++;
1532
1533	#ifdef INSTRUMENTATION
1534	m_cpt_icache_dir_write++;
1535	#endif
1536	r_icache.write_dir( r_icache_miss_way.read(),
1537	r_icache_miss_set.read(),
1538	CACHE_SLOT_STATE_ZOMBI);
1539	#if DEBUG_ICACHE
1540	if ( m_debug_activated )
1541	{
1542	std::cout << " <PROC " << name()
1543	<< " ICACHE_MISS_CLEAN> Switch to ZOMBI state" << std::dec
1544	<< " / WAY = " << r_icache_miss_way.read()
1545	<< " / SET = " << r_icache_miss_set.read() << std::endl;
1546	}
1547	#endif
1548
1549	r_icache_fsm = ICACHE_MISS_WAIT;
1550	break;
1551	}
1552	//////////////////////
1553	case ICACHE_MISS_WAIT: // waiting response from VCI_RSP FSM
1554	{
1555	if (m_ireq.valid) m_cost_ins_miss_frz++;
1556
1557	// coherence interrupt
1558	if ( r_cc_receive_icache_req.read() )
1559	{
1560	r_icache_fsm = ICACHE_CC_CHECK;
1561	r_icache_fsm_save = r_icache_fsm.read();
1562	break;
1563	}
1564
1565	if ( r_vci_rsp_ins_error.read() ) // bus error
1566	{
1567	r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS;
1568	r_mmu_ibvar = r_icache_vaddr_save.read();
1569	m_irsp.valid = true;
1570	m_irsp.error = true;
1571	r_vci_rsp_ins_error = false;
1572	r_icache_fsm = ICACHE_IDLE;
1573	}
1574	else if ( r_vci_rsp_fifo_icache.rok() ) // response available
1575	{
1576	r_icache_miss_word = 0;
1577	r_icache_fsm = ICACHE_MISS_DATA_UPDT;
1578	}
1579	break;
1580	}
1581	///////////////////////////
1582	case ICACHE_MISS_DATA_UPDT: // update the cache (one word per cycle)
1583	{
1584	if ( m_ireq.valid ) m_cost_ins_miss_frz++;
1585
1586	if ( r_vci_rsp_fifo_icache.rok() ) // response available
1587	{
1588
1589	#ifdef INSTRUMENTATION
1590	m_cpt_icache_data_write++;
1591	#endif
1592	r_icache.write( r_icache_miss_way.read(),
1593	r_icache_miss_set.read(),
1594	r_icache_miss_word.read(),
1595	r_vci_rsp_fifo_icache.read() );
1596	#if DEBUG_ICACHE
1597	if ( m_debug_activated )
1598	{
1599	std::cout << " <PROC " << name()
1600	<< " ICACHE_MISS_DATA_UPDT> Write one word:"
1601	<< " WDATA = " << r_vci_rsp_fifo_icache.read()
1602	<< " WAY = " << r_icache_miss_way.read()
1603	<< " SET = " << r_icache_miss_set.read()
1604	<< " WORD = " << r_icache_miss_word.read() << std::endl;
1605	}
1606	#endif
1607	vci_rsp_fifo_icache_get = true;
1608	r_icache_miss_word = r_icache_miss_word.read() + 1;
1609
1610	if ( r_icache_miss_word.read() == m_icache_words-1 ) // last word
1611	{
1612	r_icache_fsm = ICACHE_MISS_DIR_UPDT;
1613	}
1614	}
1615	break;
1616	}
1617	//////////////////////////
1618	case ICACHE_MISS_DIR_UPDT: // Stalled if a victim line has been evicted,
1619	// and the cleanup ack has not been received,
1620	// as indicated by r_icache_miss_clack.
1621	// - If no matching coherence request (r_icache_miss_inval)
1622	// switch directory slot to VALID state.
1623	// - If matching coherence request, switch directory slot
1624	// to ZOMBI state, and send a cleanup request.
1625	{
1626	if ( m_ireq.valid ) m_cost_ins_miss_frz++;
1627
1628	// coherence interrupt
1629	if ( r_cc_receive_icache_req.read() )
1630	{
1631	r_icache_fsm = ICACHE_CC_CHECK;
1632	r_icache_fsm_save = r_icache_fsm.read();
1633	break;
1634	}
1635
1636	if ( not r_icache_miss_clack.read() ) // waiting cleanup acknowledge for victim line
1637	{
1638	if ( r_icache_miss_inval ) // Switch slot to ZOMBI state, and new cleanup
1639	{
1640	if ( not r_icache_cc_send_req.read() )
1641	{
1642	r_icache_miss_inval = false;
1643	// request cleanup
1644	r_icache_cc_send_req = true;
1645	r_icache_cc_send_nline = r_icache_vci_paddr.read() / (m_icache_words<<2);
1646	r_icache_cc_send_way = r_icache_miss_way.read();
1647	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1648
1649	#ifdef INSTRUMENTATION
1650	m_cpt_icache_dir_write++;
1651	#endif
1652	r_icache.write_dir( r_icache_vci_paddr.read(),
1653	r_icache_miss_way.read(),
1654	r_icache_miss_set.read(),
1655	CACHE_SLOT_STATE_ZOMBI );
1656	#if DEBUG_ICACHE
1657	if ( m_debug_activated )
1658	{
1659	std::cout << " <PROC " << name()
1660	<< " ICACHE_MISS_DIR_UPDT> Switch cache slot to ZOMBI state"
1661	<< " PADDR = " << std::hex << r_icache_vci_paddr.read()
1662	<< " WAY = " << std::dec << r_icache_miss_way.read()
1663	<< " SET = " << r_icache_miss_set.read() << std::endl;
1664	}
1665	#endif
1666	}
1667	else
1668	break;
1669	}
1670	else // Switch slot to VALID state
1671	{
1672
1673	#ifdef INSTRUMENTATION
1674	m_cpt_icache_dir_write++;
1675	#endif
1676	r_icache.write_dir( r_icache_vci_paddr.read(),
1677	r_icache_miss_way.read(),
1678	r_icache_miss_set.read(),
1679	CACHE_SLOT_STATE_VALID );
1680	#if DEBUG_ICACHE
1681	if ( m_debug_activated )
1682	{
1683	std::cout << " <PROC " << name()
1684	<< " ICACHE_MISS_DIR_UPDT> Switch cache slot to VALID state"
1685	<< " PADDR = " << std::hex << r_icache_vci_paddr.read()
1686	<< " WAY = " << std::dec << r_icache_miss_way.read()
1687	<< " SET = " << r_icache_miss_set.read() << std::endl;
1688	}
1689	#endif
1690	}
1691
1692	r_icache_fsm = ICACHE_IDLE;
1693	}
1694	break;
1695	}
1696	////////////////////
1697	case ICACHE_UNC_WAIT: // waiting a response to an uncacheable read from VCI_RSP FSM
1698	{
1699	// coherence interrupt
1700	if ( r_cc_receive_icache_req.read() )
1701	{
1702	r_icache_fsm = ICACHE_CC_CHECK;
1703	r_icache_fsm_save = r_icache_fsm.read();
1704	break;
1705	}
1706
1707	if ( r_vci_rsp_ins_error.read() ) // bus error
1708	{
1709	r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS;
1710	r_mmu_ibvar = m_ireq.addr;
1711	r_vci_rsp_ins_error = false;
1712	m_irsp.valid = true;
1713	m_irsp.error = true;
1714	r_icache_fsm = ICACHE_IDLE;
1715	}
1716	else if (r_vci_rsp_fifo_icache.rok() ) // instruction available
1717	{
1718	vci_rsp_fifo_icache_get = true;
1719	r_icache_fsm = ICACHE_IDLE;
1720	if ( m_ireq.valid and
1721	(m_ireq.addr == r_icache_vaddr_save.read()) ) // request unmodified
1722	{
1723	m_irsp.valid = true;
1724	m_irsp.instruction = r_vci_rsp_fifo_icache.read();
1725	}
1726	}
1727	break;
1728	}
1729	/////////////////////
1730	case ICACHE_CC_CHECK: // This state is the entry point of a sub-fsm
1731	// handling coherence requests.
1732	// if there is a matching pending miss, it is
1733	// signaled in the r_icache_miss_inval flip-flop.
1734	// The return state is defined in r_icache_fsm_save.
1735	{
1736	paddr_t paddr = r_cc_receive_icache_nline.read() * m_icache_words * 4;
1737	paddr_t mask = ~((m_icache_words<<2)-1);
1738
1739	if (r_cc_receive_icache_type.read() == CC_TYPE_CLACK)
1740	// We switch the directory slot to EMPTY state
1741	// and reset r_icache_miss_clack if the cleanup ack
1742	// is matching a pending miss
1743	{
1744
1745	if ( m_ireq.valid ) m_cost_ins_miss_frz++;
1746
1747	#ifdef INSTRUMENTATION
1748	m_cpt_icache_dir_write++;
1749	#endif
1750	r_icache.write_dir( 0,
1751	r_cc_receive_icache_way.read(),
1752	r_cc_receive_icache_set.read(),
1753	CACHE_SLOT_STATE_EMPTY);
1754
1755	if ( (r_icache_miss_set.read() == r_cc_receive_icache_set.read()) and
1756	(r_icache_miss_way.read() == r_cc_receive_icache_way.read()) )
1757	r_icache_miss_clack = false;
1758
1759	r_icache_fsm = r_icache_fsm_save.read() ;
1760	r_cc_receive_icache_req = false;
1761
1762	#if DEBUG_ICACHE
1763	if ( m_debug_activated )
1764	{
1765	std::cout << " <PROC " << name()
1766	<< " ICACHE_CC_CHECK> CC_TYPE_CLACK slot returns to empty state"
1767	<< " set = " << r_cc_receive_icache_set.read()
1768	<< " / way = " << r_cc_receive_icache_way.read() << std::endl;
1769	}
1770	#endif
1771	}
1772	else if( ((r_icache_fsm_save.read() == ICACHE_MISS_SELECT) or
1773	(r_icache_fsm_save.read() == ICACHE_MISS_WAIT) or
1774	(r_icache_fsm_save.read() == ICACHE_MISS_DIR_UPDT)) and
1775	((r_icache_vci_paddr.read() & mask) == (paddr & mask)) ) // matching
1776	{
1777	// signaling the matching
1778	r_icache_miss_inval = true;
1779
1780	// in case of update, go to CC_UPDT
1781	// JUST TO POP THE FIFO
1782	if (r_cc_receive_icache_type.read() == CC_TYPE_UPDT)
1783	{
1784	r_icache_fsm = ICACHE_CC_UPDT;
1785	r_icache_cc_word = r_cc_receive_word_idx.read();
1786	// just pop the fifo , don't write in icache
1787	r_icache_cc_need_write = false;
1788	}
1789	// the request is dealt with
1790	else
1791	{
1792	r_cc_receive_icache_req = false;
1793	r_icache_fsm = r_icache_fsm_save.read();
1794	}
1795	#if DEBUG_ICACHE
1796	if ( m_debug_activated )
1797	{
1798	std::cout << " <PROC " << name()
1799	<< " ICACHE_CC_CHECK> Coherence request matching a pending miss:"
1800	<< " PADDR = " << std::hex << paddr << std::endl;
1801	}
1802	#endif
1803	}
1804	else // no match
1805	{
1806	int state;
1807	size_t way;
1808	size_t set;
1809	size_t word;
1810
1811	#ifdef INSTRUMENTATION
1812	m_cpt_icache_dir_read++;
1813	#endif
1814	r_icache.read_dir(paddr,
1815	&state,
1816	&way,
1817	&set,
1818	&word);
1819
1820	r_icache_cc_way = way;
1821	r_icache_cc_set = set;
1822
1823	if ( state == CACHE_SLOT_STATE_VALID) // hit
1824	{
1825	// need to update the cache state
1826	r_icache_cc_need_write = true;
1827	if (r_cc_receive_icache_type.read() == CC_TYPE_UPDT) // hit update
1828	{
1829	r_icache_fsm = ICACHE_CC_UPDT;
1830	r_icache_cc_word = r_cc_receive_word_idx.read();
1831	}
1832	else if (r_cc_receive_icache_type.read() == CC_TYPE_INVAL) // hit inval
1833	{
1834	r_icache_fsm = ICACHE_CC_INVAL;
1835	}
1836	else if (r_cc_receive_icache_type.read() == CC_TYPE_BRDCAST) // hit broadcast
1837	{
1838	r_icache_fsm = ICACHE_CC_BROADCAST;
1839	}
1840	}
1841	else // miss
1842	{
1843	// multicast acknowledgement required in case of update
1844	if(r_cc_receive_icache_type.read() == CC_TYPE_UPDT)
1845	{
1846	r_icache_fsm = ICACHE_CC_UPDT;
1847	r_icache_cc_word = r_cc_receive_word_idx.read();
1848	// just pop the fifo , don't write in icache
1849	r_icache_cc_need_write = false;
1850	}
1851	else // No response needed
1852	{
1853	r_cc_receive_icache_req = false;
1854	r_icache_fsm = r_icache_fsm_save.read();
1855	}
1856	}
1857	}
1858	break;
1859	}
1860	/////////////////////
1861	case ICACHE_CC_INVAL: // hit inval : switch slot to EMPTY state
1862	{
1863
1864	#if DEBUG_ICACHE
1865	if ( m_debug_activated )
1866	{
1867	std::cout << " <PROC " << name()
1868	<< " ICACHE_CC_INVAL> slot returns to empty state"
1869	<< " set = " << r_icache_cc_set.read()
1870	<< " / way = " << r_icache_cc_way.read() << std::endl;
1871	}
1872	#endif
1873
1874	#ifdef INSTRUMENTATION
1875	m_cpt_icache_dir_read++;
1876	#endif
1877	if (r_icache_cc_need_write.read())
1878	{
1879	r_icache.write_dir( 0,
1880	r_icache_cc_way.read(),
1881	r_icache_cc_set.read(),
1882	CACHE_SLOT_STATE_EMPTY );
1883	// no need to write in the cache anymore
1884	r_icache_cc_need_write = false;
1885	}
1886
1887	// multicast acknowledgement
1888	// send a request to cc_send_fsm
1889	if(not r_icache_cc_send_req.read()) // cc_send is available
1890	{
1891	// coherence request completed
1892	r_cc_receive_icache_req = false;
1893	// request multicast acknowledgement
1894	r_icache_cc_send_req = true;
1895	r_icache_cc_send_nline = r_cc_receive_icache_nline.read();
1896	r_icache_cc_send_updt_tab_idx = r_cc_receive_icache_updt_tab_idx.read();
1897	r_icache_cc_send_type = CC_TYPE_MULTI_ACK;
1898
1899	r_icache_fsm = r_icache_fsm_save.read();
1900	}
1901	//else wait for previous cc_send request to be sent
1902	break;
1903	}
1904	////////////////////
1905	case ICACHE_CC_UPDT: // hit update : write one word per cycle
1906	{
1907
1908	#if DEBUG_ICACHE
1909	if ( m_debug_activated )
1910	{
1911	std::cout << " <PROC " << name()
1912	<< " ICACHE_CC_UPDT> Write one word "
1913	<< " set = " << r_icache_cc_set.read()
1914	<< " / way = " << r_icache_cc_way.read()
1915	<< " / word = " << r_icache_cc_word.read() << std::endl;
1916	}
1917	#endif
1918
1919	#ifdef INSTRUMENTATION
1920	m_cpt_icache_data_write++;
1921	#endif
1922	size_t word = r_icache_cc_word.read();
1923	size_t way = r_icache_cc_way.read();
1924	size_t set = r_icache_cc_set.read();
1925
1926	if (r_cc_receive_updt_fifo_be.rok())
1927	{
1928	if (r_icache_cc_need_write.read())
1929	{
1930	r_icache.write( way,
1931	set,
1932	word,
1933	r_cc_receive_updt_fifo_data.read(),
1934	r_cc_receive_updt_fifo_be.read() );
1935
1936	r_icache_cc_word = word+1;
1937	}
1938	if ( r_cc_receive_updt_fifo_eop.read() ) // last word
1939	{
1940	// no need to write in the cache anymore
1941	r_icache_cc_need_write = false;
1942	// wait to send a request to cc_send_fsm
1943	if(not r_icache_cc_send_req.read()) // cc_send is available
1944	{
1945	//consume last flit
1946	cc_receive_updt_fifo_get = true;
1947	// coherence request completed
1948	r_cc_receive_icache_req = false;
1949	// request multicast acknowledgement
1950	r_icache_cc_send_req = true;
1951	r_icache_cc_send_nline = r_cc_receive_icache_nline.read();
1952	r_icache_cc_send_updt_tab_idx = r_cc_receive_icache_updt_tab_idx.read();
1953	r_icache_cc_send_type = CC_TYPE_MULTI_ACK;
1954
1955	r_icache_fsm = r_icache_fsm_save.read();
1956	}
1957	}
1958	else
1959	{
1960	//consume fifo if not eop
1961	cc_receive_updt_fifo_get = true;
1962	}
1963	}
1964	break;
1965	}
1966	/////////////////////////
1967	case ICACHE_CC_BROADCAST: // hit broadcast : switch slot to ZOMBI state
1968	// and request a cleanup
1969	{
1970
1971	#if DEBUG_ICACHE
1972	if ( m_debug_activated )
1973	{
1974	std::cout << " <PROC " << name()
1975	<< " ICACHE_CC_BROADCAST > Slot goes to zombi state "
1976	<< " set = " << r_icache_cc_set.read()
1977	<< " / way = " << r_icache_cc_way.read() << std::endl;
1978	}
1979	#endif
1980
1981	#ifdef INSTRUMENTATION
1982	m_cpt_icache_dir_write++;
1983	#endif
1984	if (r_icache_cc_need_write.read())
1985	{
1986	r_icache.write_dir( r_icache_cc_way.read(),
1987	r_icache_cc_set.read(),
1988	CACHE_SLOT_STATE_ZOMBI );
1989	// no need to write in the cache anymore
1990	r_icache_cc_need_write = false;
1991	}
1992
1993	// cleanup
1994	// send a request to cc_send_fsm
1995	if(not r_icache_cc_send_req.read()) // cc_send is available
1996	{
1997	// coherence request completed
1998	r_cc_receive_icache_req = false;
1999	// request cleanup
2000	r_icache_cc_send_req = true;
2001	r_icache_cc_send_nline = r_cc_receive_icache_nline.read();
2002	r_icache_cc_send_way = r_icache_cc_way.read();
2003	r_icache_cc_send_type = CC_TYPE_CLEANUP;
2004
2005	r_icache_fsm = r_icache_fsm_save.read();
2006	}
2007	//else wait for previous cc_send request to be sent
2008	break;
2009	}
2010	} // end switch r_icache_fsm
2011
2012	////////////////////////////////////////////////////////////////////////////////////
2013	// DCACHE FSM
2014	//
2015	// 1/ Coherence operations
2016	// They are handled as interrupts generated by the CC_RECEIVE FSM.
2017	// - There is a coherence request when r_tgt_dcache_req is set.
2018	// They are taken in IDLE, MISS_WAIT, MISS_DIR_UPDT, UNC_WAIT, LL_WAIT
2019	// and SC_WAIT states.
2020	// - There is a cleanup acknowledge request when r_cleanup_dcache_req is set.
2021	// They are taken in IDLE, MISS_SELECT, MISS_CLEAN, MISS_WAIT, MISS_DATA_UPDT,
2022	// MISS_DIR_UPDT, UNC_WAIT, LL_WAIT, SC_WAIT states.
2023	// - For both types of requests, actions associated to the pre-empted state
2024	// are not executed. The DCACHE FSM goes to the proper sub-FSM (CC_CHECK
2025	// or CC_CLACK) to execute the requested coherence operation, and returns
2026	// to the pre-empted state.
2027	//
2028	// 2/ TLB miss
2029	// The page tables are generally cacheable.
2030	// In case of miss in itlb or dtlb, the tlb miss is handled by a dedicated
2031	// sub-fsm (DCACHE_TLB_MISS state), that handle possible miss in DCACHE,
2032	// this sub-fsm implement the table-walk...
2033	//
2034	// 3/ processor requests
2035	// Processor requests are taken in IDLE state only.
2036	// The IDLE state implements a two stages pipe-line to handle write bursts:
2037	// - Both DTLB and DCACHE are accessed in stage P0 (if processor request valid).
2038	// - The registration in wbuf and the dcache update is done in stage P1
2039	// (if the processor request is a write).
2040	// The two r_dcache_wbuf_req and r_dcache_updt_req flip-flops define
2041	// the operations that must be done in P1 stage, and the access type
2042	// (read or write) to the DATA part of DCACHE depends on r_dcache_updt_req.
2043	// READ requests are delayed if a cache update is requested.
2044	// WRITE or SC requests can require a PTE Dirty bit update (in memory),
2045	// that is done (before handling the processor request) by a dedicated sub-fsm.
2046	// If a PTE is modified, both the itlb and dtlb are selectively, but sequencially
2047	// cleared by a dedicated sub_fsm (DCACHE_INVAL_TLB_SCAN state).
2048	//
2049	// 4/ Atomic instructions LL/SC
2050	// The LL/SC address are non cacheable (systematic access to memory).
2051	// The llsc buffer contains a registration for an active LL/SC operation
2052	// (with an address, a registration key, an aging counter and a valid bit).
2053	// - LL requests from the processor are transmitted as a one flit VCI command
2054	// (CMD_LOCKED_READ as CMD, and TYPE_LL as PKTID value). PLEN must
2055	// be 8 as the response is 2 flits long (data and registration key)
2056	// - SC requests from the processor are systematically transmitted to the
2057	// memory cache as 2 flits VCI command (CMD_STORE_COND as CMD, and TYPE_SC
2058	// as PKTID value). The first flit contains the registration key, the second
2059	// flit contains the data to write in case of success.
2060	// The cache is not updated, as this is done in case of success by the
2061	// coherence transaction.
2062	//
2063	// 5/ Non cacheable access:
2064	// This component implement a strong order between non cacheable access
2065	// (read or write) : A new non cacheable VCI transaction starts only when
2066	// the previous non cacheable transaction is completed. Both cacheable and
2067	// non cacheable transactions use the write buffer, but the DCACHE FSM registers
2068	// a non cacheable write transaction posted in the write buffer by setting the
2069	// r_dcache_pending_unc_write flip_flop. All other non cacheable requests
2070	// are stalled until this flip-flop is reset by the VCI_RSP_FSM (when the
2071	// pending non cacheable write transaction completes).
2072	//
2073	// 6/ Error handling:
2074	// When the MMU is not activated, Read Bus Errors are synchronous events,
2075	// but Write Bus Errors are asynchronous events (processor is not frozen).
2076	// - If a Read Bus Error is detected, the VCI_RSP FSM sets the
2077	// r_vci_rsp_data_error flip-flop, without writing any data in the
2078	// r_vci_rsp_fifo_dcache FIFO, and the synchronous error is signaled
2079	// by the DCACHE FSM.
2080	// - If a Write Bus Error is detected, the VCI_RSP FSM signals
2081	// the asynchronous error using the setWriteBerr() method.
2082	// When the MMU is activated bus error are rare events, as the MMU
2083	// checks the physical address before the VCI transaction starts.
2084	////////////////////////////////////////////////////////////////////////////////////////
2085
2086	// default value for m_drsp
2087	m_drsp.valid = false;
2088	m_drsp.error = false;
2089	m_drsp.rdata = 0;
2090
2091	switch ( r_dcache_fsm.read() )
2092	{
2093	case DCACHE_IDLE: // There are 10 conditions to exit the IDLE state :
2094	// 1) ITLB/DTLB inval request (update) => DCACHE_INVAL_TLB_SCAN
2095	// 2) Coherence request (TGT FSM) => DCACHE_CC_CHECK
2096	// 3) ITLB miss request (ICACHE FSM) => DCACHE_TLB_MISS
2097	// 4) XTN request (processor) => DCACHE_XTN_*
2098	// 5) DTLB miss (processor) => DCACHE_TLB_MISS
2099	// 6) Dirty bit update (processor) => DCACHE_DIRTY_GET_PTE
2100	// 7) Cacheable read miss (processor) => DCACHE_MISS_SELECT
2101	// 8) Uncacheable read (processor) => DCACHE_UNC_WAIT
2102	// 9) LL access (processor) => DCACHE_LL_WAIT
2103	// 10) SC access (processor) => DCACHE_SC_WAIT
2104	//
2105	// There is a fixed priority to handle requests to DCACHE:
2106	// 1/ the ITLB/DTLB invalidate requests
2107	// 2/ the coherence requests,
2108	// 3/ the processor requests (including DTLB miss),
2109	// 4/ the ITLB miss requests,
2110	// The address space processor request are handled as follows:
2111	// - WRITE request is blocked if the Dirty bit mus be set.
2112	// If DTLB hit, the P1 stage is activated (writes WBUF, and
2113	// updates DCACHE if DCACHE hit) & processor request acknowledged.
2114	// - READ request generate a simultaneouss access to DCACHE.DATA
2115	// and DCACHE.DIR, but is delayed if DCACHE update required.
2116	//
2117	// There is 4 configurations defining the access type to
2118	// DTLB, DCACHE.DATA, and DCACHE.DIR, depending on the
2119	// dreq.valid (dreq) and r_dcache_updt_req (updt) signals:
2120	// dreq / updt / DTLB / DCACHE.DIR / DCACHE.DATA /
2121	// 0 / 0 / NOP / NOP / NOP /
2122	// 0 / 1 / NOP / NOP / WRITE /
2123	// 1 / 0 / READ / READ / NOP /
2124	// 1 / 1 / READ / READ / WRITE /
2125	// Those two registers are set at each cycle from the 3 signals
2126	// updt_request, wbuf_request, wbuf_write_miss.
2127	{
2128	paddr_t paddr; // physical address
2129	pte_info_t tlb_flags;
2130	size_t tlb_way;
2131	size_t tlb_set;
2132	paddr_t tlb_nline = 0;
2133	size_t cache_way;
2134	size_t cache_set;
2135	size_t cache_word;
2136	uint32_t cache_rdata = 0;
2137	bool tlb_hit = false;
2138	int cache_state = CACHE_SLOT_STATE_EMPTY;
2139
2140	bool tlb_inval_required = false; // request TLB inval after cache update
2141	bool wbuf_write_miss = false; // miss a WBUF write request
2142	bool updt_request = false; // request DCACHE update in P1 stage
2143	bool wbuf_request = false; // request WBUF write in P1 stage
2144
2145	// physical address computation : systematic DTLB access if activated)
2146	if ( m_dreq.valid )
2147	{
2148	if ( r_mmu_mode.read() & DATA_TLB_MASK ) // DTLB activated
2149	{
2150	tlb_hit = r_dtlb.translate( m_dreq.addr,
2151	&paddr,
2152	&tlb_flags,
2153	&tlb_nline,
2154	&tlb_way,
2155	&tlb_set );
2156	#ifdef INSTRUMENTATION
2157	m_cpt_dtlb_read++;
2158	#endif
2159	}
2160	else // identity mapping
2161	{
2162	paddr = (paddr_t)m_dreq.addr;
2163	// we take into account the paddr extension
2164	if (vci_param::N > 32)
2165	paddr = paddr \| ((paddr_t)(r_dcache_paddr_ext.read()) << 32);
2166	}
2167	} // end physical address computation
2168
2169	// systematic DCACHE access depending on r_dcache_updt_req (if activated)
2170	if ( r_mmu_mode.read() & DATA_CACHE_MASK)
2171	{
2172	if ( m_dreq.valid and r_dcache_updt_req.read() ) // read DIR and write DATA
2173	{
2174	r_dcache.read_dir( paddr,
2175	&cache_state,
2176	&cache_way,
2177	&cache_set,
2178	&cache_word );
2179
2180	r_dcache.write( r_dcache_save_cache_way.read(),
2181	r_dcache_save_cache_set.read(),
2182	r_dcache_save_cache_word.read(),
2183	r_dcache_save_wdata.read(),
2184	r_dcache_save_be.read() );
2185	#ifdef INSTRUMENTATION
2186	m_cpt_dcache_dir_read++;
2187	m_cpt_dcache_data_write++;
2188	#endif
2189	}
2190	else if ( m_dreq.valid and not r_dcache_updt_req.read() ) // read DIR and DATA
2191	{
2192	r_dcache.read( paddr,
2193	&cache_rdata,
2194	&cache_way,
2195	&cache_set,
2196	&cache_word,
2197	&cache_state );
2198
2199	#ifdef INSTRUMENTATION
2200	m_cpt_dcache_dir_read++;
2201	m_cpt_dcache_data_read++;
2202	#endif
2203	}
2204	else if ( not m_dreq.valid and r_dcache_updt_req.read() ) // write DATA
2205	{
2206	r_dcache.write( r_dcache_save_cache_way.read(),
2207	r_dcache_save_cache_set.read(),
2208	r_dcache_save_cache_word.read(),
2209	r_dcache_save_wdata.read(),
2210	r_dcache_save_be.read() );
2211	#ifdef INSTRUMENTATION
2212	m_cpt_dcache_data_write++;
2213	#endif
2214	}
2215	} // end dcache access
2216
2217	// DCACHE update in P1 stage can require ITLB / DTLB inval or flush
2218	if ( r_dcache_updt_req.read() )
2219	{
2220	size_t way = r_dcache_save_cache_way.read();
2221	size_t set = r_dcache_save_cache_set.read();
2222
2223	if ( r_dcache_in_tlb[way*m_dcache_sets+set] )
2224	{
2225	tlb_inval_required = true;
2226	r_dcache_tlb_inval_set = 0;
2227	r_dcache_tlb_inval_line = r_dcache_save_paddr.read()>>
2228	(uint32_log2(m_dcache_words<<2));
2229	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
2230	}
2231	else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] )
2232	{
2233	r_itlb.reset();
2234	r_dtlb.reset();
2235	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
2236	}
2237
2238	#if DEBUG_DCACHE
2239	if ( m_debug_activated )
2240	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
2241	<< " Cache update in P1 stage" << std::dec
2242	<< " / WAY = " << r_dcache_save_cache_way.read()
2243	<< " / SET = " << r_dcache_save_cache_set.read()
2244	<< " / WORD = " << r_dcache_save_cache_word.read() << std::hex
2245	<< " / WDATA = " << r_dcache_save_wdata.read()
2246	<< " / BE = " << r_dcache_save_be.read() << std::endl;
2247	#endif
2248	} // end test TLB inval
2249
2250	// Try WBUF update in P1 stage
2251	// Miss if the write request is non cacheable, and there is a pending
2252	// non cacheable write, or if the write buffer is full.
2253	if ( r_dcache_wbuf_req.read() )
2254	{
2255	// miss if write not cacheable, and previous non cacheable write registered
2256	if ( not r_dcache_save_cacheable.read() and r_dcache_pending_unc_write.read() )
2257	{
2258	wbuf_write_miss = true;
2259	}
2260	else // try a registration into write buffer
2261	{
2262	bool wok = r_wbuf.write( r_dcache_save_paddr.read(),
2263	r_dcache_save_be.read(),
2264	r_dcache_save_wdata.read(),
2265	r_dcache_save_cacheable.read() );
2266	#ifdef INSTRUMENTATION
2267	m_cpt_wbuf_write++;
2268	#endif
2269	if ( not wok ) // miss if write buffer full
2270	{
2271	wbuf_write_miss = true;
2272	}
2273	else // update the write_buffer state extension
2274	{
2275	if(not r_dcache_pending_unc_write.read())
2276	r_dcache_pending_unc_write = not r_dcache_save_cacheable.read();
2277	}
2278	}
2279	} // end WBUF update
2280
2281	// Computing the response to processor,
2282	// and the next value for r_dcache_fsm
2283
2284	// itlb/dtlb invalidation self-request
2285	if ( tlb_inval_required )
2286	{
2287	r_dcache_fsm_scan_save = r_dcache_fsm.read();
2288	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
2289	}
2290
2291	// coherence request (from CC_RECEIVE FSM)
2292	else if ( r_cc_receive_dcache_req.read() )
2293	{
2294	r_dcache_fsm = DCACHE_CC_CHECK;
2295	r_dcache_fsm_cc_save = r_dcache_fsm.read();
2296	}
2297
2298	// processor request (READ, WRITE, LL, SC, XTN_READ, XTN_WRITE)
2299	// we don't take the processor request, and registers
2300	// are frozen in case of wbuf_write_miss
2301	else if ( m_dreq.valid and not wbuf_write_miss )
2302	{
2303	// register processor request and DCACHE response
2304	r_dcache_save_vaddr = m_dreq.addr;
2305	r_dcache_save_be = m_dreq.be;
2306	r_dcache_save_wdata = m_dreq.wdata;
2307	r_dcache_save_paddr = paddr;
2308	r_dcache_save_cache_way = cache_way;
2309	r_dcache_save_cache_set = cache_set;
2310	r_dcache_save_cache_word = cache_word;
2311
2312	// READ XTN requests from processor
2313	// They are executed in this DCACHE_IDLE state.
2314	// The processor must not be in user mode
2315	if (m_dreq.type == iss_t::XTN_READ)
2316	{
2317	int xtn_opcode = (int)m_dreq.addr/4;
2318
2319	// checking processor mode:
2320	if (m_dreq.mode == iss_t::MODE_USER)
2321	{
2322	r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION;
2323	r_mmu_dbvar = m_dreq.addr;
2324	m_drsp.valid = true;
2325	m_drsp.error = true;
2326	m_drsp.rdata = 0;
2327	r_dcache_fsm = DCACHE_IDLE;
2328	}
2329	else
2330	{
2331	switch( xtn_opcode )
2332	{
2333	case iss_t::XTN_INS_ERROR_TYPE:
2334	m_drsp.rdata = r_mmu_ietr.read();
2335	m_drsp.valid = true;
2336	m_drsp.error = false;
2337	break;
2338
2339	case iss_t::XTN_DATA_ERROR_TYPE:
2340	m_drsp.rdata = r_mmu_detr.read();
2341	m_drsp.valid = true;
2342	m_drsp.error = false;
2343	break;
2344
2345	case iss_t::XTN_INS_BAD_VADDR:
2346	m_drsp.rdata = r_mmu_ibvar.read();
2347	m_drsp.valid = true;
2348	m_drsp.error = false;
2349	break;
2350
2351	case iss_t::XTN_DATA_BAD_VADDR:
2352	m_drsp.rdata = r_mmu_dbvar.read();
2353	m_drsp.valid = true;
2354	m_drsp.error = false;
2355	break;
2356
2357	case iss_t::XTN_PTPR:
2358	m_drsp.rdata = r_mmu_ptpr.read();
2359	m_drsp.valid = true;
2360	m_drsp.error = false;
2361	break;
2362
2363	case iss_t::XTN_TLB_MODE:
2364	m_drsp.rdata = r_mmu_mode.read();
2365	m_drsp.valid = true;
2366	m_drsp.error = false;
2367	break;
2368
2369	case iss_t::XTN_MMU_PARAMS:
2370	m_drsp.rdata = r_mmu_params;
2371	m_drsp.valid = true;
2372	m_drsp.error = false;
2373	break;
2374
2375	case iss_t::XTN_MMU_RELEASE:
2376	m_drsp.rdata = r_mmu_release;
2377	m_drsp.valid = true;
2378	m_drsp.error = false;
2379	break;
2380
2381	case iss_t::XTN_MMU_WORD_LO:
2382	m_drsp.rdata = r_mmu_word_lo.read();
2383	m_drsp.valid = true;
2384	m_drsp.error = false;
2385	break;
2386
2387	case iss_t::XTN_MMU_WORD_HI:
2388	m_drsp.rdata = r_mmu_word_hi.read();
2389	m_drsp.valid = true;
2390	m_drsp.error = false;
2391	break;
2392
2393	case iss_t::XTN_DATA_PADDR_EXT:
2394	m_drsp.rdata = r_dcache_paddr_ext.read();
2395	m_drsp.valid = true;
2396	m_drsp.error = false;
2397	break;
2398
2399	default:
2400	r_mmu_detr = MMU_READ_UNDEFINED_XTN;
2401	r_mmu_dbvar = m_dreq.addr;
2402	m_drsp.valid = true;
2403	m_drsp.error = true;
2404	m_drsp.rdata = 0;
2405	break;
2406	} // end switch xtn_opcode
2407	} // end else
2408	} // end if XTN_READ
2409
2410	// Handling WRITE XTN requests from processor.
2411	// They are not executed in this DCACHE_IDLE state
2412	// if they require access to the caches or the TLBs
2413	// that are already accessed.
2414	// Caches can be invalidated or flushed in user mode,
2415	// and the sync instruction can be executed in user mode
2416	else if (m_dreq.type == iss_t::XTN_WRITE)
2417	{
2418	int xtn_opcode = (int)m_dreq.addr/4;
2419	r_dcache_xtn_opcode = xtn_opcode;
2420
2421	// checking processor mode:
2422	if ( (m_dreq.mode == iss_t::MODE_USER) &&
2423	(xtn_opcode != iss_t::XTN_SYNC) &&
2424	(xtn_opcode != iss_t::XTN_DCACHE_INVAL) &&
2425	(xtn_opcode != iss_t::XTN_DCACHE_FLUSH) &&
2426	(xtn_opcode != iss_t::XTN_ICACHE_INVAL) &&
2427	(xtn_opcode != iss_t::XTN_ICACHE_FLUSH) )
2428	{
2429	r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION;
2430	r_mmu_dbvar = m_dreq.addr;
2431	m_drsp.valid = true;
2432	m_drsp.error = true;
2433	m_drsp.rdata = 0;
2434	r_dcache_fsm = DCACHE_IDLE;
2435	}
2436	else
2437	{
2438	switch( xtn_opcode )
2439	{
2440	case iss_t::XTN_PTPR: // itlb & dtlb must be flushed
2441	r_dcache_xtn_req = true;
2442	r_dcache_fsm = DCACHE_XTN_SWITCH;
2443	break;
2444
2445	case iss_t::XTN_TLB_MODE: // no cache or tlb access
2446	r_mmu_mode = m_dreq.wdata;
2447	m_drsp.valid = true;
2448	r_dcache_fsm = DCACHE_IDLE;
2449	break;
2450
2451	case iss_t::XTN_DTLB_INVAL: // dtlb access
2452	r_dcache_fsm = DCACHE_XTN_DT_INVAL;
2453	break;
2454
2455	case iss_t::XTN_ITLB_INVAL: // itlb access
2456	r_dcache_xtn_req = true;
2457	r_dcache_fsm = DCACHE_XTN_IT_INVAL;
2458	break;
2459
2460	case iss_t::XTN_DCACHE_INVAL: // dcache, dtlb & itlb access
2461	r_dcache_fsm = DCACHE_XTN_DC_INVAL_VA;
2462	break;
2463
2464	case iss_t::XTN_MMU_DCACHE_PA_INV: // dcache, dtlb & itlb access
2465	r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA;
2466	if (sizeof(paddr_t) <= 32)
2467	{
2468	assert(r_mmu_word_hi.read() == 0 &&
2469	"high bits should be 0 for 32bit paddr");
2470	r_dcache_save_paddr = (paddr_t)r_mmu_word_lo.read();
2471	}
2472	else
2473	{
2474	r_dcache_save_paddr = (paddr_t)r_mmu_word_hi.read() << 32 \|
2475	(paddr_t)r_mmu_word_lo.read();
2476	}
2477	break;
2478
2479	case iss_t::XTN_DCACHE_FLUSH: // itlb and dtlb must be reset
2480	r_dcache_flush_count = 0;
2481	r_dcache_fsm = DCACHE_XTN_DC_FLUSH;
2482	break;
2483
2484	case iss_t::XTN_ICACHE_INVAL: // icache and itlb access
2485	r_dcache_xtn_req = true;
2486	r_dcache_fsm = DCACHE_XTN_IC_INVAL_VA;
2487	break;
2488
2489	case iss_t::XTN_MMU_ICACHE_PA_INV: // icache access
2490	r_dcache_xtn_req = true;
2491	r_dcache_fsm = DCACHE_XTN_IC_INVAL_PA;
2492	break;
2493
2494	case iss_t::XTN_ICACHE_FLUSH: // icache access
2495	r_dcache_xtn_req = true;
2496	r_dcache_fsm = DCACHE_XTN_IC_FLUSH;
2497	break;
2498
2499	case iss_t::XTN_SYNC: // wait until write buffer empty
2500	r_dcache_fsm = DCACHE_XTN_SYNC;
2501	break;
2502
2503	case iss_t::XTN_MMU_WORD_LO: // no cache or tlb access
2504	r_mmu_word_lo = m_dreq.wdata;
2505	m_drsp.valid = true;
2506	r_dcache_fsm = DCACHE_IDLE;
2507	break;
2508
2509	case iss_t::XTN_MMU_WORD_HI: // no cache or tlb access
2510	r_mmu_word_hi = m_dreq.wdata;
2511	m_drsp.valid = true;
2512	r_dcache_fsm = DCACHE_IDLE;
2513	break;
2514
2515	case iss_t::XTN_MMU_LL_RESET: // no cache or tlb access
2516	r_dcache_llsc_valid = false;
2517	m_drsp.valid = true;
2518	r_dcache_fsm = DCACHE_IDLE;
2519	break;
2520
2521	case iss_t::XTN_DATA_PADDR_EXT: // no cache or tlb access
2522	r_dcache_paddr_ext = m_dreq.wdata;
2523	m_drsp.valid = true;
2524	r_dcache_fsm = DCACHE_IDLE;
2525	break;
2526
2527	case iss_t::XTN_ICACHE_PREFETCH: // not implemented : no action
2528	case iss_t::XTN_DCACHE_PREFETCH: // not implemented : no action
2529	m_drsp.valid = true;
2530	r_dcache_fsm = DCACHE_IDLE;
2531	break;
2532
2533	default:
2534	r_mmu_detr = MMU_WRITE_UNDEFINED_XTN;
2535	r_mmu_dbvar = m_dreq.addr;
2536	m_drsp.valid = true;
2537	m_drsp.error = true;
2538	r_dcache_fsm = DCACHE_IDLE;
2539	break;
2540	} // end switch xtn_opcode
2541	} // end else
2542	} // end if XTN_WRITE
2543
2544	// Handling processor requests to address space (READ/WRITE/LL/SC)
2545	// The dtlb and dcache can be activated or not.
2546	// We compute the cacheability, and check processor request validity:
2547	// - If DTLB not activated : cacheability is defined by the segment table,
2548	// and there is no access rights checking.
2549	// - If DTLB activated : cacheability is defined by the C bit in the PTE,
2550	// and the U & W bits of the PTE are checked, as well as the DTLB hit.
2551	// Jumps to the TLB_MISS sub-fsm in case of dtlb miss.
2552	else
2553	{
2554	bool valid_req;
2555	bool cacheable;
2556
2557	if ( not (r_mmu_mode.read() & DATA_TLB_MASK) ) // dtlb not activated
2558	{
2559	valid_req = true;
2560
2561	if ( not (r_mmu_mode.read() & DATA_CACHE_MASK) ) cacheable = false;
2562	else cacheable = m_cacheability_table[m_dreq.addr];
2563	}
2564	else // dtlb activated
2565	{
2566	if ( tlb_hit ) // tlb hit
2567	{
2568	// cacheability
2569	if ( not (r_mmu_mode.read() & DATA_CACHE_MASK) ) cacheable = false;
2570	else cacheable = tlb_flags.c;
2571
2572	// access rights checking
2573	if ( not tlb_flags.u and (m_dreq.mode == iss_t::MODE_USER))
2574	{
2575	if ( (m_dreq.type == iss_t::DATA_READ) or
2576	(m_dreq.type == iss_t::DATA_LL) )
2577	{
2578	r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION;
2579	}
2580	else
2581	{
2582	r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION;
2583	}
2584	valid_req = false;
2585	r_mmu_dbvar = m_dreq.addr;
2586	m_drsp.valid = true;
2587	m_drsp.error = true;
2588	m_drsp.rdata = 0;
2589	#if DEBUG_DCACHE
2590	if ( m_debug_activated )
2591	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
2592	<< " HIT in dtlb, but privilege violation" << std::endl;
2593	#endif
2594	}
2595	else if ( not tlb_flags.w and
2596	((m_dreq.type == iss_t::DATA_WRITE) or
2597	(m_dreq.type == iss_t::DATA_SC)) )
2598	{
2599	r_mmu_detr = MMU_WRITE_ACCES_VIOLATION;
2600	valid_req = false;
2601	r_mmu_dbvar = m_dreq.addr;
2602	m_drsp.valid = true;
2603	m_drsp.error = true;
2604	m_drsp.rdata = 0;
2605	#if DEBUG_DCACHE
2606	if ( m_debug_activated )
2607	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
2608	<< " HIT in dtlb, but writable violation" << std::endl;
2609	#endif
2610	}
2611	else
2612	{
2613	valid_req = true;
2614	}
2615	}
2616	else // tlb miss
2617	{
2618	valid_req = false;
2619	r_dcache_tlb_vaddr = m_dreq.addr;
2620	r_dcache_tlb_ins = false;
2621	r_dcache_fsm = DCACHE_TLB_MISS;
2622	}
2623	} // end DTLB activated
2624
2625	if ( valid_req ) // processor request is valid (after MMU check)
2626	{
2627	r_dcache_save_cacheable = cacheable;
2628
2629	// READ request
2630	// The read requests are taken only if there is no cache update.
2631	// We request a VCI transaction to CMD FSM if miss or uncachable
2632
2633	if ( ((m_dreq.type == iss_t::DATA_READ))
2634	and not r_dcache_updt_req.read() )
2635	{
2636	if ( cacheable ) // cacheable read
2637	{
2638	if ( cache_state == CACHE_SLOT_STATE_EMPTY ) // cache miss
2639	{
2640	#ifdef INSTRUMENTATION
2641	m_cpt_dcache_miss++;
2642	#endif
2643	// request a VCI DMISS transaction
2644	r_dcache_vci_paddr = paddr;
2645	r_dcache_vci_miss_req = true;
2646	r_dcache_miss_type = PROC_MISS;
2647	r_dcache_fsm = DCACHE_MISS_SELECT;
2648	#if DEBUG_DCACHE
2649	if ( m_debug_activated )
2650	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
2651	<< " READ MISS in dcache"
2652	<< " / PADDR = " << std::hex << paddr << std::endl;
2653	#endif
2654	}
2655	else if (cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup
2656	{
2657	// stalled until cleanup is acknowledged
2658	r_dcache_fsm = DCACHE_IDLE;
2659	#if DEBUG_DCACHE
2660	if ( m_debug_activated )
2661	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
2662	<< " Pending cleanup, stalled until cleanup acknowledge"
2663	<< " / PADDR = " << std::hex << paddr << std::endl;
2664	#endif
2665	}
2666	else // cache hit
2667	{
2668	#ifdef INSTRUMENTATION
2669	m_cpt_data_read++;
2670	#endif
2671	// returns data to processor
2672	m_drsp.valid = true;
2673	m_drsp.error = false;
2674	m_drsp.rdata = cache_rdata;
2675	#if DEBUG_DCACHE
2676	if ( m_debug_activated )
2677	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
2678	<< " READ HIT in dcache"
2679	<< " / PADDR = " << std::hex << paddr << std::endl;
2680	#endif
2681	}
2682	}
2683	else // uncacheable read
2684	{
2685	r_dcache_vci_paddr = paddr;
2686	r_dcache_vci_unc_be = m_dreq.be;
2687	r_dcache_vci_unc_req = true;
2688	r_dcache_fsm = DCACHE_UNC_WAIT;
2689	#if DEBUG_DCACHE
2690	if ( m_debug_activated )
2691	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
2692	<< " READ UNCACHEABLE in dcache"
2693	<< " / PADDR = " << std::hex << paddr << std::endl;
2694	#endif
2695	}
2696	} // end READ
2697
2698	// LL request (non cachable)
2699	// We request a VCI LL transaction to CMD FSM and register
2700	// the LL/SC operation in llsc buffer.
2701	else if (m_dreq.type == iss_t::DATA_LL)
2702	{
2703	// register paddr in LLSC buffer
2704	r_dcache_llsc_paddr = paddr;
2705	r_dcache_llsc_count = LLSC_TIMEOUT;
2706	r_dcache_llsc_valid = true;
2707
2708	// request an LL VCI transaction and go to DCACHE_LL_WAIT state
2709	r_dcache_vci_ll_req = true;
2710	r_dcache_vci_paddr = paddr;
2711	r_dcache_ll_rsp_count = 0;
2712	r_dcache_fsm = DCACHE_LL_WAIT;
2713
2714	}// end LL
2715
2716	// WRITE request:
2717	// If the TLB is activated and the PTE Dirty bit is not set, we stall
2718	// the processor and set the Dirty bit before handling the write request,
2719	// going to the DCACHE_DIRTY_GT_PTE state.
2720	// If we don't need to set the Dirty bit, we can acknowledge
2721	// the processor request, as the write arguments (including the
2722	// physical address) are registered in r_dcache_save registers,
2723	// and the write will be done in the P1 pipeline stage.
2724	else if ( m_dreq.type == iss_t::DATA_WRITE )
2725	{
2726	if ( (r_mmu_mode.read() & DATA_TLB_MASK )
2727	and not tlb_flags.d ) // Dirty bit must be set
2728	{
2729	// The PTE physical address is obtained from the nline value (dtlb),
2730	// and from the virtual address (word index)
2731	if ( tlb_flags.b ) // PTE1
2732	{
2733	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2734	(paddr_t)((m_dreq.addr>>19) & 0x3c);
2735	}
2736	else // PTE2
2737	{
2738	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2739	(paddr_t)((m_dreq.addr>>9) & 0x38);
2740	}
2741	r_dcache_fsm = DCACHE_DIRTY_GET_PTE;
2742	}
2743	else // Write request accepted
2744	{
2745	#ifdef INSTRUMENTATION
2746	m_cpt_data_write++;
2747	#endif
2748	// cleaning llsc buffer if address matching
2749	if ( paddr == r_dcache_llsc_paddr.read() )
2750	r_dcache_llsc_valid = false;
2751
2752	// response to processor
2753	m_drsp.valid = true;
2754
2755	// activating P1 stage
2756	wbuf_request = true;
2757	updt_request = (cache_state == CACHE_SLOT_STATE_VALID);
2758	}
2759	} // end WRITE
2760
2761	// SC request:
2762	// If the TLB is activated and the PTE Dirty bit is not set, we stall
2763	// the processor and set the Dirty bit before handling the write request,
2764	// going to the DCACHE_DIRTY_GT_PTE state.
2765	// If we don't need to set the Dirty bit, we test the llsc buffer:
2766	// If failure, we send a negative response to processor.
2767	// If success, we request a SC transaction to CMD FSM and go
2768	// to DCACHE_SC_WAIT state.
2769	// We don't check a possible write hit in dcache, as the cache update
2770	// is done by the coherence transaction induced by the SC...
2771	else if ( m_dreq.type == iss_t::DATA_SC )
2772	{
2773	if ( (r_mmu_mode.read() & DATA_TLB_MASK )
2774	and not tlb_flags.d ) // Dirty bit must be set
2775	{
2776	// The PTE physical address is obtained from the nline value (dtlb),
2777	// and the word index (virtual address)
2778	if ( tlb_flags.b ) // PTE1
2779	{
2780	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2781	(paddr_t)((m_dreq.addr>>19) & 0x3c);
2782	}
2783	else // PTE2
2784	{
2785	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2786	(paddr_t)((m_dreq.addr>>9) & 0x38);
2787	}
2788	r_dcache_fsm = DCACHE_DIRTY_GET_PTE;
2789	m_drsp.valid = false;
2790	m_drsp.error = false;
2791	m_drsp.rdata = 0;
2792	}
2793	else // SC request accepted
2794	{
2795	#ifdef INSTRUMENTATION
2796	m_cpt_data_sc++;
2797	#endif
2798	// checking local success
2799	if( r_dcache_llsc_valid.read() and
2800	(r_dcache_llsc_paddr.read() == paddr) ) // local success
2801	{
2802	// request an SC CMD and go to DCACHE_SC_WAIT state
2803	r_dcache_vci_paddr = paddr;
2804	r_dcache_vci_sc_req = true;
2805	r_dcache_vci_sc_data = m_dreq.wdata;
2806	r_dcache_fsm = DCACHE_SC_WAIT;
2807	}
2808	else // local fail
2809	{
2810	m_drsp.valid = true;
2811	m_drsp.error = false;
2812	m_drsp.rdata = 0x1;
2813	}
2814	}
2815	} // end SC
2816	} // end valid_req
2817	} // end if read/write/ll/sc request
2818	} // end processor request
2819
2820	// itlb miss request
2821	else if ( r_icache_tlb_miss_req.read() and not wbuf_write_miss )
2822	{
2823	r_dcache_tlb_ins = true;
2824	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
2825	r_dcache_fsm = DCACHE_TLB_MISS;
2826	}
2827
2828	// Computing requests for P1 stage : r_dcache_wbuf_req & r_dcache_updt_req
2829	r_dcache_updt_req = updt_request;
2830	r_dcache_wbuf_req = wbuf_request or
2831	(r_dcache_wbuf_req.read() and wbuf_write_miss);
2832	break;
2833	}
2834	/////////////////////
2835	case DCACHE_TLB_MISS: // This is the entry point for the sub-fsm handling all tlb miss.
2836	// Input arguments are:
2837	// - r_dcache_tlb_vaddr
2838	// - r_dcache_tlb_ins (true when itlb miss)
2839	// The sub-fsm access the dcache to find the missing TLB entry,
2840	// and activates the cache miss procedure in case of miss.
2841	// It bypass the first level page table access if possible.
2842	// It uses atomic access to update the R/L access bits
2843	// in the page table if required.
2844	// It directly updates the itlb or dtlb, and writes into the
2845	// r_mmu_ins_* or r_mmu_data* error reporting registers.
2846	{
2847	uint32_t ptba = 0;
2848	bool bypass;
2849	paddr_t pte_paddr;
2850
2851	// evaluate bypass in order to skip first level page table access
2852	if ( r_dcache_tlb_ins.read() ) // itlb miss
2853	{
2854	bypass = r_itlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba);
2855	}
2856	else // dtlb miss
2857	{
2858	bypass = r_dtlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba);
2859	}
2860
2861	if ( not bypass ) // Try to read PTE1/PTD1 in dcache
2862	{
2863	pte_paddr = (((paddr_t)r_mmu_ptpr.read()) << (INDEX1_NBITS+2)) \|
2864	((((paddr_t)r_dcache_tlb_vaddr.read()) >> PAGE_M_NBITS) << 2);
2865	r_dcache_tlb_paddr = pte_paddr;
2866	r_dcache_fsm = DCACHE_TLB_PTE1_GET;
2867	}
2868	else // Try to read PTE2 in dcache
2869	{
2870	pte_paddr = (paddr_t)ptba << PAGE_K_NBITS \|
2871	(paddr_t)(r_dcache_tlb_vaddr.read()&PTD_ID2_MASK)>>(PAGE_K_NBITS-3);
2872	r_dcache_tlb_paddr = pte_paddr;
2873	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
2874	}
2875
2876	#if DEBUG_DCACHE
2877	if ( m_debug_activated )
2878	{
2879	if ( r_dcache_tlb_ins.read() )
2880	std::cout << " <PROC " << name() << " DCACHE_TLB_MISS> ITLB miss";
2881	else
2882	std::cout << " <PROC " << name() << " DCACHE_TLB_MISS> DTLB miss";
2883	std::cout << " / VADDR = " << std::hex << r_dcache_tlb_vaddr.read()
2884	<< " / ptpr = " << (((paddr_t)r_mmu_ptpr.read()) << (INDEX1_NBITS+2))
2885	<< " / BYPASS = " << bypass
2886	<< " / PTE_ADR = " << pte_paddr << std::endl;
2887	}
2888	#endif
2889
2890	break;
2891	}
2892	/////////////////////////
2893	case DCACHE_TLB_PTE1_GET: // try to read a PT1 entry in dcache
2894	{
2895	// coherence request (from CC_RECEIVE FSM)
2896	if ( r_cc_receive_dcache_req.read() )
2897	{
2898	r_dcache_fsm = DCACHE_CC_CHECK;
2899	r_dcache_fsm_cc_save = r_dcache_fsm.read();
2900	break;
2901	}
2902
2903	uint32_t entry;
2904	size_t way;
2905	size_t set;
2906	size_t word;
2907	int cache_state;
2908	r_dcache.read( r_dcache_tlb_paddr.read(),
2909	&entry,
2910	&way,
2911	&set,
2912	&word,
2913	&cache_state );
2914	#ifdef INSTRUMENTATION
2915	m_cpt_dcache_data_read++;
2916	m_cpt_dcache_dir_read++;
2917	#endif
2918	if ( cache_state == CACHE_SLOT_STATE_VALID ) // hit in dcache
2919	{
2920	if ( not (entry & PTE_V_MASK) ) // unmapped
2921	{
2922	if ( r_dcache_tlb_ins.read() )
2923	{
2924	r_mmu_ietr = MMU_READ_PT1_UNMAPPED;
2925	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
2926	r_icache_tlb_miss_req = false;
2927	r_icache_tlb_rsp_error = true;
2928	}
2929	else
2930	{
2931	r_mmu_detr = MMU_READ_PT1_UNMAPPED;
2932	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
2933	m_drsp.valid = true;
2934	m_drsp.error = true;
2935	}
2936	r_dcache_fsm = DCACHE_IDLE;
2937
2938	#if DEBUG_DCACHE
2939	if ( m_debug_activated )
2940	{
2941	std::cout << " <PROC " << name()
2942	<< " DCACHE_TLB_PTE1_GET> HIT in dcache, but unmapped"
2943	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
2944	<< std::dec << " / way = " << way
2945	<< std::dec << " / set = " << set
2946	<< std::dec << " / word = " << word
2947	<< std::hex << " / PTE1 = " << entry << std::endl;
2948	}
2949	#endif
2950
2951	}
2952	else if( entry & PTE_T_MASK ) // PTD : me must access PT2
2953	{
2954	// mark the cache line ac containing a PTD
2955	r_dcache_contains_ptd[m_dcache_sets*way+set] = true;
2956
2957	// register bypass
2958	if ( r_dcache_tlb_ins.read() ) // itlb
2959	{
2960	r_itlb.set_bypass(r_dcache_tlb_vaddr.read(),
2961	entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1),
2962	r_dcache_tlb_paddr.read() / (m_icache_words<<2) );
2963	}
2964	else // dtlb
2965	{
2966	r_dtlb.set_bypass(r_dcache_tlb_vaddr.read(),
2967	entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1),
2968	r_dcache_tlb_paddr.read() / (m_dcache_words<<2) );
2969	}
2970	r_dcache_tlb_paddr =
2971	(paddr_t)(entry & ((1<<(m_paddr_nbits-PAGE_K_NBITS))-1)) << PAGE_K_NBITS \|
2972	(paddr_t)(((r_dcache_tlb_vaddr.read() & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3);
2973	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
2974
2975	#if DEBUG_DCACHE
2976	if ( m_debug_activated )
2977	{
2978	std::cout << " <PROC " << name()
2979	<< " DCACHE_TLB_PTE1_GET> HIT in dcache"
2980	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
2981	<< std::dec << " / way = " << way
2982	<< std::dec << " / set = " << set
2983	<< std::dec << " / word = " << word
2984	<< std::hex << " / PTD = " << entry << std::endl;
2985	}
2986	#endif
2987	}
2988	else // PTE1 : we must update the TLB
2989	{
2990	r_dcache_in_tlb[m_icache_sets*way+set] = true;
2991	r_dcache_tlb_pte_flags = entry;
2992	r_dcache_tlb_cache_way = way;
2993	r_dcache_tlb_cache_set = set;
2994	r_dcache_tlb_cache_word = word;
2995	r_dcache_fsm = DCACHE_TLB_PTE1_SELECT;
2996
2997	#if DEBUG_DCACHE
2998	if ( m_debug_activated )
2999	{
3000	std::cout << " <PROC " << name()
3001	<< " DCACHE_TLB_PTE1_GET> HIT in dcache"
3002	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
3003	<< std::dec << " / way = " << way
3004	<< std::dec << " / set = " << set
3005	<< std::dec << " / word = " << word
3006	<< std::hex << " / PTE1 = " << entry << std::endl;
3007	}
3008	#endif
3009	}
3010	}
3011	else if ( cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup
3012	{
3013	// stalled until cleanup is acknowledged
3014	r_dcache_fsm = DCACHE_TLB_PTE1_GET;
3015	}
3016	else // we must load the missing cache line in dcache
3017	{
3018	r_dcache_vci_miss_req = true;
3019	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
3020	r_dcache_save_paddr = r_dcache_tlb_paddr.read();
3021	r_dcache_miss_type = PTE1_MISS;
3022	r_dcache_fsm = DCACHE_MISS_SELECT;
3023
3024	#if DEBUG_DCACHE
3025	if ( m_debug_activated )
3026	{
3027	std::cout << " <PROC " << name()
3028	<< " DCACHE_TLB_PTE1_GET> MISS in dcache:"
3029	<< " PTE1 address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
3030	}
3031	#endif
3032	}
3033	break;
3034	}
3035	////////////////////////////
3036	case DCACHE_TLB_PTE1_SELECT: // select a slot for PTE1
3037	{
3038	size_t way;
3039	size_t set;
3040
3041	if ( r_dcache_tlb_ins.read() )
3042	{
3043	r_itlb.select( r_dcache_tlb_vaddr.read(),
3044	true, // PTE1
3045	&way,
3046	&set );
3047	#ifdef INSTRUMENTATION
3048	m_cpt_itlb_read++;
3049	#endif
3050	}
3051	else
3052	{
3053	r_dtlb.select( r_dcache_tlb_vaddr.read(),
3054	true, // PTE1
3055	&way,
3056	&set );
3057	#ifdef INSTRUMENTATION
3058	m_cpt_dtlb_read++;
3059	#endif
3060	}
3061	r_dcache_tlb_way = way;
3062	r_dcache_tlb_set = set;
3063	r_dcache_fsm = DCACHE_TLB_PTE1_UPDT;
3064
3065	#if DEBUG_DCACHE
3066	if ( m_debug_activated )
3067	{
3068	if ( r_dcache_tlb_ins.read() )
3069	std::cout << " <PROC " << name()
3070	<< " DCACHE_TLB_PTE1_SELECT> Select a slot in ITLB:";
3071	else
3072	std::cout << " <PROC " << name()
3073	<< ".DCACHE_TLB_PTE1_SELECT> Select a slot in DTLB:";
3074	std::cout << " way = " << std::dec << way
3075	<< " / set = " << set << std::endl;
3076	}
3077	#endif
3078	break;
3079	}
3080	//////////////////////////
3081	case DCACHE_TLB_PTE1_UPDT: // write a new PTE1 in tlb after testing the L/R bit
3082	// - if L/R bit already set, exit the sub-fsm.
3083	// - if not, we update the page table but we dont write
3084	// neither in DCACHE, nor in TLB, as this will be done by
3085	// the coherence mechanism.
3086	{
3087	paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2);
3088	uint32_t pte = r_dcache_tlb_pte_flags.read();
3089	bool pt_updt = false;
3090	bool local = true;
3091
3092	// We should compute the access locality:
3093	// The PPN MSB bits define the destination cluster index.
3094	// The m_srcid MSB bits define the source cluster index.
3095	// The number of bits to compare depends on the number of clusters,
3096	// and can be obtained in the mapping table.
3097	// As long as this computation is not done, all access are local.
3098
3099	if ( local ) // local access
3100	{
3101	if ( not ((pte & PTE_L_MASK) == PTE_L_MASK) ) // we must set the L bit
3102	{
3103	pt_updt = true;
3104	r_dcache_vci_cas_old = pte;
3105	r_dcache_vci_cas_new = pte \| PTE_L_MASK;
3106	pte = pte \| PTE_L_MASK;
3107	r_dcache_tlb_pte_flags = pte;
3108	}
3109	}
3110	else // remote access
3111	{
3112	if ( not ((pte & PTE_R_MASK) == PTE_R_MASK) ) // we must set the R bit
3113	{
3114	pt_updt = true;
3115	r_dcache_vci_cas_old = pte;
3116	r_dcache_vci_cas_new = pte \| PTE_R_MASK;
3117	pte = pte \| PTE_R_MASK;
3118	r_dcache_tlb_pte_flags = pte;
3119	}
3120	}
3121
3122	if ( not pt_updt ) // update TLB and return
3123	{
3124	if ( r_dcache_tlb_ins.read() )
3125	{
3126	r_itlb.write( true, // 2M page
3127	pte,
3128	0, // argument unused for a PTE1
3129	r_dcache_tlb_vaddr.read(),
3130	r_dcache_tlb_way.read(),
3131	r_dcache_tlb_set.read(),
3132	nline );
3133	#ifdef INSTRUMENTATION
3134	m_cpt_itlb_write++;
3135	#endif
3136
3137	#if DEBUG_DCACHE
3138	if ( m_debug_activated )
3139	{
3140	std::cout << " <PROC " << name()
3141	<< " DCACHE_TLB_PTE1_UPDT> write PTE1 in ITLB"
3142	<< " / set = " << std::dec << r_dcache_tlb_set.read()
3143	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3144	r_itlb.printTrace();
3145	}
3146	#endif
3147	}
3148	else
3149	{
3150	r_dtlb.write( true, // 2M page
3151	pte,
3152	0, // argument unused for a PTE1
3153	r_dcache_tlb_vaddr.read(),
3154	r_dcache_tlb_way.read(),
3155	r_dcache_tlb_set.read(),
3156	nline );
3157	#ifdef INSTRUMENTATION
3158	m_cpt_dtlb_write++;
3159	#endif
3160
3161	#if DEBUG_DCACHE
3162	if ( m_debug_activated )
3163	{
3164	std::cout << " <PROC " << name()
3165	<< " DCACHE_TLB_PTE1_UPDT> write PTE1 in DTLB"
3166	<< " / set = " << std::dec << r_dcache_tlb_set.read()
3167	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3168	r_dtlb.printTrace();
3169	}
3170	#endif
3171	}
3172	r_dcache_fsm = DCACHE_TLB_RETURN;
3173	}
3174	else // update page table but not TLB
3175	{
3176	r_dcache_fsm = DCACHE_TLB_LR_UPDT;
3177
3178	#if DEBUG_DCACHE
3179	if ( m_debug_activated )
3180	{
3181	std::cout << " <PROC " << name()
3182	<< " DCACHE_TLB_PTE1_UPDT> L/R bit update required"
3183	<< std::endl;
3184	}
3185	#endif
3186	}
3187	break;
3188	}
3189	/////////////////////////
3190	case DCACHE_TLB_PTE2_GET: // Try to get a PTE2 (64 bits) in the dcache
3191	{
3192	// coherence request (from CC_RECEIVE FSM)
3193	if ( r_cc_receive_dcache_req.read() )
3194	{
3195	r_dcache_fsm = DCACHE_CC_CHECK;
3196	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3197	break;
3198	}
3199
3200	uint32_t pte_flags;
3201	uint32_t pte_ppn;
3202	size_t way;
3203	size_t set;
3204	size_t word;
3205	int cache_state;
3206
3207	r_dcache.read( r_dcache_tlb_paddr.read(),
3208	&pte_flags,
3209	&pte_ppn,
3210	&way,
3211	&set,
3212	&word,
3213	&cache_state );
3214	#ifdef INSTRUMENTATION
3215	m_cpt_dcache_data_read++;
3216	m_cpt_dcache_dir_read++;
3217	#endif
3218	if ( cache_state == CACHE_SLOT_STATE_VALID ) // hit in dcache
3219	{
3220	if ( not (pte_flags & PTE_V_MASK) ) // unmapped
3221	{
3222	if ( r_dcache_tlb_ins.read() )
3223	{
3224	r_mmu_ietr = MMU_READ_PT2_UNMAPPED;
3225	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3226	r_icache_tlb_miss_req = false;
3227	r_icache_tlb_rsp_error = true;
3228	}
3229	else
3230	{
3231	r_mmu_detr = MMU_READ_PT2_UNMAPPED;
3232	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3233	m_drsp.valid = true;
3234	m_drsp.error = true;
3235	}
3236	r_dcache_fsm = DCACHE_IDLE;
3237
3238	#if DEBUG_DCACHE
3239	if ( m_debug_activated )
3240	{
3241	std::cout << " <PROC " << name()
3242	<< " DCACHE_TLB_PTE2_GET> HIT in dcache, but PTE unmapped"
3243	<< " PTE_FLAGS = " << std::hex << pte_flags
3244	<< " PTE_PPN = " << std::hex << pte_ppn << std::endl;
3245	}
3246	#endif
3247	}
3248	else // mapped : we must update the TLB
3249	{
3250	r_dcache_in_tlb[m_dcache_sets*way+set] = true;
3251	r_dcache_tlb_pte_flags = pte_flags;
3252	r_dcache_tlb_pte_ppn = pte_ppn;
3253	r_dcache_tlb_cache_way = way;
3254	r_dcache_tlb_cache_set = set;
3255	r_dcache_tlb_cache_word = word;
3256	r_dcache_fsm = DCACHE_TLB_PTE2_SELECT;
3257
3258	#if DEBUG_DCACHE
3259	if ( m_debug_activated )
3260	{
3261	std::cout << " <PROC " << name()
3262	<< " DCACHE_TLB_PTE2_GET> HIT in dcache:"
3263	<< " PTE_FLAGS = " << std::hex << pte_flags
3264	<< " PTE_PPN = " << std::hex << pte_ppn << std::endl;
3265	}
3266	#endif
3267	}
3268	}
3269	else if ( cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup
3270	{
3271	// stalled until cleanup is acknowledged
3272	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
3273
3274	#if DEBUG_DCACHE
3275	if ( m_debug_activated )
3276	{
3277	std::cout << " <PROC " << name()
3278	<< " DCACHE_TLB_PTE2_GET> ZOMBI in dcache: waiting cleanup ack"
3279	<< std::endl;
3280	}
3281	#endif
3282	}
3283	else // we must load the missing cache line in dcache
3284	{
3285	r_dcache_fsm = DCACHE_MISS_SELECT;
3286	r_dcache_vci_miss_req = true;
3287	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
3288	r_dcache_save_paddr = r_dcache_tlb_paddr.read();
3289	r_dcache_miss_type = PTE2_MISS;
3290
3291	#if DEBUG_DCACHE
3292	if ( m_debug_activated )
3293	{
3294	std::cout << " <PROC " << name()
3295	<< " DCACHE_TLB_PTE2_GET> MISS in dcache:"
3296	<< " PTE address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
3297	}
3298	#endif
3299	}
3300	break;
3301	}
3302	////////////////////////////
3303	case DCACHE_TLB_PTE2_SELECT: // select a slot for PTE2
3304	{
3305	size_t way;
3306	size_t set;
3307
3308	if ( r_dcache_tlb_ins.read() )
3309	{
3310	r_itlb.select( r_dcache_tlb_vaddr.read(),
3311	false, // PTE2
3312	&way,
3313	&set );
3314	#ifdef INSTRUMENTATION
3315	m_cpt_itlb_read++;
3316	#endif
3317	}
3318	else
3319	{
3320	r_dtlb.select( r_dcache_tlb_vaddr.read(),
3321	false, // PTE2
3322	&way,
3323	&set );
3324	#ifdef INSTRUMENTATION
3325	m_cpt_dtlb_read++;
3326	#endif
3327	}
3328
3329	#if DEBUG_DCACHE
3330	if ( m_debug_activated )
3331	{
3332	if ( r_dcache_tlb_ins.read() )
3333	std::cout << " <PROC " << name()
3334	<< " DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB:";
3335	else
3336	std::cout << " <PROC " << name()
3337	<< " DCACHE_TLB_PTE2_SELECT> Select a slot in DTLB:";
3338	std::cout << " way = " << std::dec << way
3339	<< " / set = " << set << std::endl;
3340	}
3341	#endif
3342	r_dcache_tlb_way = way;
3343	r_dcache_tlb_set = set;
3344	r_dcache_fsm = DCACHE_TLB_PTE2_UPDT;
3345	break;
3346	}
3347	//////////////////////////
3348	case DCACHE_TLB_PTE2_UPDT: // write a new PTE2 in tlb after testing the L/R bit
3349	// - if L/R bit already set, exit the sub-fsm.
3350	// - if not, we update the page table but we dont write
3351	// neither in DCACHE, nor in TLB, as this will be done by
3352	// the coherence mechanism.
3353	{
3354	paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2);
3355	uint32_t pte_flags = r_dcache_tlb_pte_flags.read();
3356	uint32_t pte_ppn = r_dcache_tlb_pte_ppn.read();
3357	bool pt_updt = false;
3358	bool local = true;
3359
3360	// We should compute the access locality:
3361	// The PPN MSB bits define the destination cluster index.
3362	// The m_srcid MSB bits define the source cluster index.
3363	// The number of bits to compare depends on the number of clusters,
3364	// and can be obtained in the mapping table.
3365	// As long as this computation is not done, all access are local.
3366
3367	if ( local ) // local access
3368	{
3369	if ( not ((pte_flags & PTE_L_MASK) == PTE_L_MASK) ) // we must set the L bit
3370	{
3371	pt_updt = true;
3372	r_dcache_vci_cas_old = pte_flags;
3373	r_dcache_vci_cas_new = pte_flags \| PTE_L_MASK;
3374	pte_flags = pte_flags \| PTE_L_MASK;
3375	r_dcache_tlb_pte_flags = pte_flags;
3376	}
3377	}
3378	else // remote access
3379	{
3380	if ( not ((pte_flags & PTE_R_MASK) == PTE_R_MASK) ) // we must set the R bit
3381	{
3382	pt_updt = true;
3383	r_dcache_vci_cas_old = pte_flags;
3384	r_dcache_vci_cas_new = pte_flags \| PTE_R_MASK;
3385	pte_flags = pte_flags \| PTE_R_MASK;
3386	r_dcache_tlb_pte_flags = pte_flags;
3387	}
3388	}
3389
3390	if ( not pt_updt ) // update TLB
3391	{
3392	if ( r_dcache_tlb_ins.read() )
3393	{
3394	r_itlb.write( false, // 4K page
3395	pte_flags,
3396	pte_ppn,
3397	r_dcache_tlb_vaddr.read(),
3398	r_dcache_tlb_way.read(),
3399	r_dcache_tlb_set.read(),
3400	nline );
3401	#ifdef INSTRUMENTATION
3402	m_cpt_itlb_write++;
3403	#endif
3404
3405	#if DEBUG_DCACHE
3406	if ( m_debug_activated )
3407	{
3408	std::cout << " <PROC " << name()
3409	<< " DCACHE_TLB_PTE2_UPDT> write PTE2 in ITLB"
3410	<< " / set = " << std::dec << r_dcache_tlb_set.read()
3411	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3412	r_itlb.printTrace();
3413	}
3414	#endif
3415	}
3416	else
3417	{
3418	r_dtlb.write( false, // 4K page
3419	pte_flags,
3420	pte_ppn,
3421	r_dcache_tlb_vaddr.read(),
3422	r_dcache_tlb_way.read(),
3423	r_dcache_tlb_set.read(),
3424	nline );
3425	#ifdef INSTRUMENTATION
3426	m_cpt_dtlb_write++;
3427	#endif
3428
3429	#if DEBUG_DCACHE
3430	if ( m_debug_activated )
3431	{
3432	std::cout << " <PROC " << name()
3433	<< " DCACHE_TLB_PTE2_UPDT> write PTE2 in DTLB"
3434	<< " / set = " << std::dec << r_dcache_tlb_set.read()
3435	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3436	r_dtlb.printTrace();
3437	}
3438	#endif
3439
3440	}
3441	r_dcache_fsm = DCACHE_TLB_RETURN;
3442	}
3443	else // update page table but not TLB
3444	{
3445	r_dcache_fsm = DCACHE_TLB_LR_UPDT; // dcache and page table update
3446
3447	#if DEBUG_DCACHE
3448	if ( m_debug_activated )
3449	{
3450	std::cout << " <PROC " << name()
3451	<< " DCACHE_TLB_PTE2_UPDT> L/R bit update required" << std::endl;
3452	}
3453	#endif
3454	}
3455	break;
3456	}
3457	////////////////////////
3458	case DCACHE_TLB_LR_UPDT: // request a CAS transaction to update L/R bit
3459	{
3460	#if DEBUG_DCACHE
3461	if ( m_debug_activated )
3462	{
3463	std::cout << " <PROC " << name()
3464	<< " DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit" << std::endl;
3465	}
3466	#endif
3467	// r_dcache_vci_cas_old & r_dcache_vci_cas_new registers are already set
3468	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
3469
3470	// checking llsc reservation buffer
3471	if ( r_dcache_llsc_paddr.read() == r_dcache_tlb_paddr.read() )
3472	r_dcache_llsc_valid = false;
3473
3474	// request a CAS CMD and go to DCACHE_TLB_LR_WAIT state
3475	r_dcache_vci_cas_req = true;
3476	r_dcache_fsm = DCACHE_TLB_LR_WAIT;
3477	break;
3478	}
3479	////////////////////////
3480	case DCACHE_TLB_LR_WAIT: // Waiting the response to SC transaction for DIRTY bit.
3481	// We consume the response in rsp FIFO,
3482	// and exit the sub-fsm, but we don't
3483	// analyse the response, because we don't
3484	// care if the L/R bit update is not done.
3485	// We must take the coherence requests because
3486	// there is a risk of dead-lock
3487
3488	{
3489	// coherence request (from CC_RECEIVE FSM)
3490	if ( r_cc_receive_dcache_req.read() )
3491	{
3492	r_dcache_fsm = DCACHE_CC_CHECK;
3493	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3494	break;
3495	}
3496
3497	if ( r_vci_rsp_data_error.read() ) // bus error
3498	{
3499	std::cout << "BUS ERROR in DCACHE_TLB_LR_WAIT state" << std::endl;
3500	std::cout << "This should not happen in this state" << std::endl;
3501	exit(0);
3502	}
3503	else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
3504	{
3505	#if DEBUG_DCACHE
3506	if ( m_debug_activated )
3507	{
3508	std::cout << " <PROC " << name()
3509	<< " DCACHE_TLB_LR_WAIT> SC response received" << std::endl;
3510	}
3511	#endif
3512	vci_rsp_fifo_dcache_get = true;
3513	r_dcache_fsm = DCACHE_TLB_RETURN;
3514	}
3515	break;
3516	}
3517	///////////////////////
3518	case DCACHE_TLB_RETURN: // return to caller depending on tlb miss type
3519	{
3520	#if DEBUG_DCACHE
3521	if ( m_debug_activated )
3522	{
3523	std::cout << " <PROC " << name()
3524	<< " DCACHE_TLB_RETURN> TLB MISS completed" << std::endl;
3525	}
3526	#endif
3527	if ( r_dcache_tlb_ins.read() ) r_icache_tlb_miss_req = false;
3528	r_dcache_fsm = DCACHE_IDLE;
3529	break;
3530	}
3531	///////////////////////
3532	case DCACHE_XTN_SWITCH: // The r_ptpr registers must be written,
3533	// and both itlb and dtlb must be flushed.
3534	// Caution : the itlb miss requests must be taken
3535	// to avoid dead-lock in case of simultaneous ITLB miss
3536	{
3537	// itlb miss request
3538	if ( r_icache_tlb_miss_req.read() )
3539	{
3540	r_dcache_tlb_ins = true;
3541	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
3542	r_dcache_fsm = DCACHE_TLB_MISS;
3543	break;
3544	}
3545
3546	if ( not r_dcache_xtn_req.read() )
3547	{
3548	r_dtlb.flush();
3549	r_mmu_ptpr = m_dreq.wdata;
3550	r_dcache_fsm = DCACHE_IDLE;
3551	m_drsp.valid = true;
3552	}
3553	break;
3554	}
3555	/////////////////////
3556	case DCACHE_XTN_SYNC: // waiting until write buffer empty
3557	// The coherence request must be taken
3558	// as there is a risk of dead-lock
3559	{
3560	// coherence request (from CC_RECEIVE FSM)
3561	if ( r_cc_receive_dcache_req.read() )
3562	{
3563	r_dcache_fsm = DCACHE_CC_CHECK;
3564	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3565	}
3566
3567	if ( r_wbuf.empty() )
3568	{
3569	m_drsp.valid = true;
3570	r_dcache_fsm = DCACHE_IDLE;
3571	}
3572	break;
3573	}
3574	////////////////////////
3575	case DCACHE_XTN_IC_FLUSH: // Waiting completion of an XTN request to the ICACHE FSM
3576	case DCACHE_XTN_IC_INVAL_VA: // Caution : the itlb miss requests must be taken
3577	case DCACHE_XTN_IC_INVAL_PA: // because the XTN_ICACHE_INVAL request to icache
3578	case DCACHE_XTN_IT_INVAL: // can generate an itlb miss,
3579	// and because it can exist a simultaneous ITLB miss
3580	{
3581	// coherence request (from CC_RECEIVE FSM)
3582	if ( r_cc_receive_dcache_req.read() )
3583	{
3584	r_dcache_fsm = DCACHE_CC_CHECK;
3585	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3586	break;
3587	}
3588
3589	// itlb miss request
3590	if ( r_icache_tlb_miss_req.read() )
3591	{
3592	r_dcache_tlb_ins = true;
3593	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
3594	r_dcache_fsm = DCACHE_TLB_MISS;
3595	break;
3596	}
3597
3598	// test if XTN request to icache completed
3599	if ( not r_dcache_xtn_req.read() )
3600	{
3601	r_dcache_fsm = DCACHE_IDLE;
3602	m_drsp.valid = true;
3603	}
3604	break;
3605	}
3606	/////////////////////////
3607	case DCACHE_XTN_DC_FLUSH: // Invalidate sequencially all cache lines, using
3608	// r_dcache_flush_count as a slot counter,
3609	// looping in this state until all slots have been visited.
3610	// It can require two cycles per slot:
3611	// We test here the slot state, and make the actual inval
3612	// (if line is valid) in DCACHE_XTN_DC_FLUSH_GO state.
3613	// A cleanup request is generated for each valid line.
3614	// returns to IDLE and flush TLBs when last slot
3615	{
3616	// coherence request (from CC_RECEIVE FSM)
3617	if ( r_cc_receive_dcache_req.read() )
3618	{
3619	r_dcache_fsm = DCACHE_CC_CHECK;
3620	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3621	break;
3622	}
3623
3624	if ( not r_dcache_cc_send_req.read() ) // blocked until previous cc_send request is sent
3625	{
3626	int state;
3627	paddr_t tag;
3628	size_t way = r_dcache_flush_count.read()/m_dcache_sets;
3629	size_t set = r_dcache_flush_count.read()%m_dcache_sets;
3630
3631	#ifdef INSTRUMENTATION
3632	m_cpt_dcache_dir_read++;
3633	#endif
3634	r_dcache.read_dir( way,
3635	set,
3636	&tag,
3637	&state );
3638
3639	if ( state == CACHE_SLOT_STATE_VALID ) // inval required
3640	{
3641	// request cleanup
3642	r_dcache_cc_send_req = true;
3643	r_dcache_cc_send_nline = tag * m_dcache_sets + set;
3644	r_dcache_cc_send_way = way;
3645	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
3646
3647	// goes to DCACHE_XTN_DC_FLUSH_GO to inval directory
3648	r_dcache_miss_way = way;
3649	r_dcache_miss_set = set;
3650	r_dcache_fsm = DCACHE_XTN_DC_FLUSH_GO;
3651	}
3652	else if ( r_dcache_flush_count.read() ==
3653	(m_dcache_sets*m_dcache_ways - 1) ) // last slot
3654	{
3655	r_dtlb.reset();
3656	r_itlb.reset();
3657	r_dcache_fsm = DCACHE_IDLE;
3658	m_drsp.valid = true;
3659	}
3660
3661	// saturation counter
3662	if ( r_dcache_flush_count.read() < (m_dcache_sets*m_dcache_ways - 1) )
3663	r_dcache_flush_count = r_dcache_flush_count.read() + 1;
3664	}
3665	break;
3666	}
3667	////////////////////////////
3668	case DCACHE_XTN_DC_FLUSH_GO: // Switch the cache slot to ZOMBI state
3669	// and reset directory extension.
3670	// returns to IDLE and flush TLBs when last slot
3671	{
3672	size_t way = r_dcache_miss_way.read();
3673	size_t set = r_dcache_miss_set.read();
3674
3675	r_dcache_in_tlb[m_dcache_sets*way+set] = false;
3676	r_dcache_contains_ptd[m_dcache_sets*way+set] = false;
3677
3678	#ifdef INSTRUMENTATION
3679	m_cpt_dcache_dir_write++;
3680	#endif
3681	r_dcache.write_dir( way,
3682	set,
3683	CACHE_SLOT_STATE_ZOMBI );
3684
3685	if ( r_dcache_flush_count.read() ==
3686	(m_dcache_sets*m_dcache_ways - 1) ) // last slot
3687	{
3688	r_dtlb.reset();
3689	r_itlb.reset();
3690	r_dcache_fsm = DCACHE_IDLE;
3691	m_drsp.valid = true;
3692	}
3693	else
3694	{
3695	r_dcache_fsm = DCACHE_XTN_DC_FLUSH;
3696	}
3697	break;
3698	}
3699	/////////////////////////
3700	case DCACHE_XTN_DT_INVAL: // handling processor XTN_DTLB_INVAL request
3701	{
3702	r_dtlb.inval(r_dcache_save_wdata.read());
3703	r_dcache_fsm = DCACHE_IDLE;
3704	m_drsp.valid = true;
3705	break;
3706	}
3707	////////////////////////////
3708	case DCACHE_XTN_DC_INVAL_VA: // selective cache line invalidate with virtual address
3709	// requires 3 cycles: access tlb, read cache, inval cache
3710	// we compute the physical address in this state
3711	{
3712	paddr_t paddr;
3713	bool hit;
3714
3715	if ( r_mmu_mode.read() & DATA_TLB_MASK ) // dtlb activated
3716	{
3717
3718	#ifdef INSTRUMENTATION
3719	m_cpt_dtlb_read++;
3720	#endif
3721	hit = r_dtlb.translate( r_dcache_save_wdata.read(),
3722	&paddr );
3723	}
3724	else // dtlb not activated
3725	{
3726	paddr = (paddr_t)r_dcache_save_wdata.read();
3727	hit = true;
3728	}
3729
3730	if ( hit ) // tlb hit
3731	{
3732	r_dcache_save_paddr = paddr;
3733	r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA;
3734	}
3735	else // tlb miss
3736	{
3737
3738	#ifdef INSTRUMENTATION
3739	m_cpt_dtlb_miss++;
3740	#endif
3741	r_dcache_tlb_ins = false; // dtlb
3742	r_dcache_tlb_vaddr = r_dcache_save_wdata.read();
3743	r_dcache_fsm = DCACHE_TLB_MISS;
3744	}
3745
3746	#if DEBUG_DCACHE
3747	if ( m_debug_activated )
3748	{
3749	std::cout << " <PROC " << name()
3750	<< " DCACHE_XTN_DC_INVAL_VA> Compute physical address" << std::hex
3751	<< " / VADDR = " << r_dcache_save_wdata.read()
3752	<< " / PADDR = " << paddr << std::endl;
3753	}
3754	#endif
3755
3756	break;
3757	}
3758	////////////////////////////
3759	case DCACHE_XTN_DC_INVAL_PA: // selective cache line invalidate with physical address
3760	// requires 2 cycles: read cache / inval cache
3761	// In this state we read dcache.
3762	{
3763	size_t way;
3764	size_t set;
3765	size_t word;
3766	int state;
3767
3768	#ifdef INSTRUMENTATION
3769	m_cpt_dcache_dir_read++;
3770	#endif
3771	r_dcache.read_dir( r_dcache_save_paddr.read(),
3772	&state,
3773	&way,
3774	&set,
3775	&word );
3776
3777	if ( state == CACHE_SLOT_STATE_VALID ) // inval to be done
3778	{
3779	r_dcache_xtn_way = way;
3780	r_dcache_xtn_set = set;
3781	r_dcache_fsm = DCACHE_XTN_DC_INVAL_GO;
3782	}
3783	else // miss : nothing to do
3784	{
3785	r_dcache_fsm = DCACHE_IDLE;
3786	m_drsp.valid = true;
3787	}
3788
3789	#if DEBUG_DCACHE
3790	if ( m_debug_activated )
3791	{
3792	std::cout << " <PROC " << name()
3793	<< " DCACHE_XTN_DC_INVAL_PA> Test hit in dcache" << std::hex
3794	<< " / PADDR = " << r_dcache_save_paddr.read() << std::dec
3795	<< " / HIT = " << (state == CACHE_SLOT_STATE_VALID)
3796	<< " / SET = " << set
3797	<< " / WAY = " << way << std::endl;
3798	}
3799	#endif
3800	break;
3801	}
3802	////////////////////////////
3803	case DCACHE_XTN_DC_INVAL_GO: // In this state, we invalidate the cache line
3804	// Blocked if previous cleanup not completed
3805	// Test if itlb or dtlb inval is required
3806	{
3807	if ( not r_dcache_cc_send_req.read() ) // blocked until previous cc_send request is sent
3808	{
3809	size_t way = r_dcache_xtn_way.read();
3810	size_t set = r_dcache_xtn_set.read();
3811	paddr_t nline = r_dcache_save_paddr.read() / (m_dcache_words<<2);
3812
3813	#ifdef INSTRUMENTATION
3814	m_cpt_dcache_dir_write++;
3815	#endif
3816	r_dcache.write_dir( way,
3817	set,
3818	CACHE_SLOT_STATE_ZOMBI );
3819
3820	// request cleanup
3821	r_dcache_cc_send_req = true;
3822	r_dcache_cc_send_nline = nline;
3823	r_dcache_cc_send_way = way;
3824	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
3825
3826	// possible itlb & dtlb invalidate
3827	if ( r_dcache_in_tlb[way*m_dcache_sets+set] )
3828	{
3829	r_dcache_tlb_inval_line = nline;
3830	r_dcache_tlb_inval_set = 0;
3831	r_dcache_fsm_scan_save = DCACHE_XTN_DC_INVAL_END;
3832	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
3833	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
3834	}
3835	else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] )
3836	{
3837	r_itlb.reset();
3838	r_dtlb.reset();
3839	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
3840	r_dcache_fsm = DCACHE_IDLE;
3841	m_drsp.valid = true;
3842	}
3843	else
3844	{
3845	r_dcache_fsm = DCACHE_IDLE;
3846	m_drsp.valid = true;
3847	}
3848
3849	#if DEBUG_DCACHE
3850	if ( m_debug_activated )
3851	{
3852	std::cout << " <PROC " << name()
3853	<< " DCACHE_XTN_DC_INVAL_GO> Actual dcache inval" << std::hex
3854	<< " / PADDR = " << r_dcache_save_paddr.read() << std::endl;
3855	}
3856	#endif
3857	}
3858	break;
3859	}
3860	//////////////////////////////
3861	case DCACHE_XTN_DC_INVAL_END: // send response to processor XTN request
3862	{
3863	r_dcache_fsm = DCACHE_IDLE;
3864	m_drsp.valid = true;
3865	break;
3866	}
3867	////////////////////////
3868	case DCACHE_MISS_SELECT: // Try to select a slot in associative set
3869	// if previous cleanup has been sent.
3870	// Waiting in this state if no slot available
3871	// Set the r_dcache_cleanup_req flip-flop
3872	// and the r_dcache_miss_clack flip-flop
3873	// when a cleanup is required
3874	{
3875	if ( m_dreq.valid) m_cost_data_miss_frz++;
3876
3877	// coherence request (from CC_RECEIVE FSM)
3878	if ( r_cc_receive_dcache_req.read() )
3879	{
3880	r_dcache_fsm = DCACHE_CC_CHECK;
3881	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3882	break;
3883	}
3884
3885	if ( not r_dcache_cc_send_req.read() ) // blocked until previous cc_send request is sent
3886	{
3887	bool found;
3888	bool cleanup;
3889	size_t way;
3890	size_t set;
3891	paddr_t victim;
3892
3893	#ifdef INSTRUMENTATION
3894	m_cpt_dcache_dir_read++;
3895	#endif
3896	r_dcache.read_select( r_dcache_save_paddr.read(),
3897	&victim,
3898	&way,
3899	&set,
3900	&found,
3901	&cleanup );
3902
3903	if ( found )
3904	{
3905	r_dcache_miss_way = way;
3906	r_dcache_miss_set = set;
3907
3908	if ( cleanup )
3909	{
3910	r_dcache_miss_clack = true;
3911	r_dcache_fsm = DCACHE_MISS_CLEAN;
3912	// request cleanup
3913	r_dcache_cc_send_req = true;
3914	r_dcache_cc_send_nline = victim;
3915	r_dcache_cc_send_way = way;
3916	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
3917	}
3918	else
3919	{
3920	r_dcache_fsm = DCACHE_MISS_WAIT;
3921	}
3922
3923	#if DEBUG_DCACHE
3924	if ( m_debug_activated )
3925	{
3926	std::cout << " <PROC " << name()
3927	<< " DCACHE_MISS_SELECT> Select a slot:" << std::dec
3928	<< " / WAY = " << way
3929	<< " / SET = " << set
3930	<< " / PADDR = " << std::hex << r_dcache_save_paddr.read();
3931	if(cleanup) std::cout << " / VICTIM = " << (victimm_dcache_words4) << std::endl;
3932	else std::cout << std::endl;
3933	}
3934	#endif
3935	} // end found
3936	}
3937	break;
3938	}
3939	///////////////////////
3940	case DCACHE_MISS_CLEAN: // switch the slot to ZOMBI state
3941	// and possibly request itlb or dtlb invalidate
3942	{
3943	if ( m_dreq.valid) m_cost_data_miss_frz++;
3944
3945	size_t way = r_dcache_miss_way.read();
3946	size_t set = r_dcache_miss_set.read();
3947
3948	#ifdef INSTRUMENTATION
3949	m_cpt_dcache_dir_read++;
3950	#endif
3951	r_dcache.write_dir( way,
3952	set,
3953	CACHE_SLOT_STATE_ZOMBI );
3954	#if DEBUG_DCACHE
3955	if ( m_debug_activated )
3956	{
3957	std::cout << " <PROC " << name()
3958	<< " DCACHE_MISS_CLEAN> Switch to ZOMBI state" << std::dec
3959	<< " / way = " << way
3960	<< " / set = " << set << std::endl;
3961	}
3962	#endif
3963	// if selective itlb & dtlb invalidate are required
3964	// the miss response is not handled before invalidate completed
3965	if ( r_dcache_in_tlb[way*m_dcache_sets+set] )
3966	{
3967	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
3968	r_dcache_tlb_inval_line = r_dcache_cc_send_nline;
3969	r_dcache_tlb_inval_set = 0;
3970	r_dcache_fsm_scan_save = DCACHE_MISS_WAIT;
3971	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
3972	}
3973	else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] )
3974	{
3975	r_itlb.reset();
3976	r_dtlb.reset();
3977	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
3978	r_dcache_fsm = DCACHE_MISS_WAIT;
3979	}
3980	else
3981	{
3982	r_dcache_fsm = DCACHE_MISS_WAIT;
3983	}
3984	break;
3985	}
3986	//////////////////////
3987	case DCACHE_MISS_WAIT: // waiting the response to a miss request from VCI_RSP FSM
3988	// This state is in charge of error signaling
3989	// There is 5 types of error depending on the requester
3990	{
3991	if ( m_dreq.valid) m_cost_data_miss_frz++;
3992
3993	// coherence request (from CC_RECEIVE FSM)
3994	if ( r_cc_receive_dcache_req.read() )
3995	{
3996	r_dcache_fsm = DCACHE_CC_CHECK;
3997	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3998	break;
3999	}
4000
4001	if ( r_vci_rsp_data_error.read() ) // bus error
4002	{
4003	switch ( r_dcache_miss_type.read() )
4004	{
4005	case PROC_MISS:
4006	{
4007	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
4008	r_mmu_dbvar = r_dcache_save_vaddr.read();
4009	m_drsp.valid = true;
4010	m_drsp.error = true;
4011	r_dcache_fsm = DCACHE_IDLE;
4012	break;
4013	}
4014	case PTE1_MISS:
4015	{
4016	if ( r_dcache_tlb_ins.read() )
4017	{
4018	r_mmu_ietr = MMU_READ_PT1_ILLEGAL_ACCESS;
4019	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
4020	r_icache_tlb_miss_req = false;
4021	r_icache_tlb_rsp_error = true;
4022	}
4023	else
4024	{
4025	r_mmu_detr = MMU_READ_PT1_ILLEGAL_ACCESS;
4026	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
4027	m_drsp.valid = true;
4028	m_drsp.error = true;
4029	}
4030	r_dcache_fsm = DCACHE_IDLE;
4031	break;
4032	}
4033	case PTE2_MISS:
4034	{
4035	if ( r_dcache_tlb_ins.read() )
4036	{
4037	r_mmu_ietr = MMU_READ_PT2_ILLEGAL_ACCESS;
4038	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
4039	r_icache_tlb_miss_req = false;
4040	r_icache_tlb_rsp_error = true;
4041	}
4042	else
4043	{
4044	r_mmu_detr = MMU_READ_PT2_ILLEGAL_ACCESS;
4045	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
4046	m_drsp.valid = true;
4047	m_drsp.error = true;
4048	}
4049	r_dcache_fsm = DCACHE_IDLE;
4050	break;
4051	}
4052	} // end switch type
4053	r_vci_rsp_data_error = false;
4054	}
4055	else if ( r_vci_rsp_fifo_dcache.rok() ) // valid response available
4056	{
4057	r_dcache_miss_word = 0;
4058	r_dcache_fsm = DCACHE_MISS_DATA_UPDT;
4059	}
4060	break;
4061	}
4062	//////////////////////////
4063	case DCACHE_MISS_DATA_UPDT: // update the dcache (one word per cycle)
4064	{
4065	if ( m_dreq.valid) m_cost_data_miss_frz++;
4066
4067	if ( r_vci_rsp_fifo_dcache.rok() ) // one word available
4068	{
4069	#ifdef INSTRUMENTATION
4070	m_cpt_dcache_data_write++;
4071	#endif
4072	r_dcache.write( r_dcache_miss_way.read(),
4073	r_dcache_miss_set.read(),
4074	r_dcache_miss_word.read(),
4075	r_vci_rsp_fifo_dcache.read() );
4076	#if DEBUG_DCACHE
4077	if ( m_debug_activated )
4078	{
4079	std::cout << " <PROC " << name()
4080	<< " DCACHE_MISS_DATA_UPDT> Write one word:"
4081	<< " / DATA = " << std::hex << r_vci_rsp_fifo_dcache.read()
4082	<< " / WAY = " << std::dec << r_dcache_miss_way.read()
4083	<< " / SET = " << r_dcache_miss_set.read()
4084	<< " / WORD = " << r_dcache_miss_word.read() << std::endl;
4085	}
4086	#endif
4087	vci_rsp_fifo_dcache_get = true;
4088	r_dcache_miss_word = r_dcache_miss_word.read() + 1;
4089
4090	if ( r_dcache_miss_word.read() == (m_dcache_words-1) ) // last word
4091	{
4092	r_dcache_fsm = DCACHE_MISS_DIR_UPDT;
4093	}
4094	}
4095	break;
4096	}
4097	//////////////////////////
4098	case DCACHE_MISS_DIR_UPDT: // Stalled if a victim line has been evicted
4099	// and the cleanup ack has not been received,
4100	// as indicated by the r_dcache_miss clack.
4101	// - If no matching coherence request (r_dcache_inval_miss)
4102	// switch directory slot to VALID state.
4103	// - If matching coherence request, switch directory slot
4104	// to ZOMBI state, and send a cleanup request.
4105	{
4106	if ( m_dreq.valid) m_cost_data_miss_frz++;
4107
4108	// coherence request (from CC_RECEIVE FSM)
4109	if ( r_cc_receive_dcache_req.read() )
4110	{
4111	r_dcache_fsm = DCACHE_CC_CHECK;
4112	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4113	break;
4114	}
4115
4116	if ( not r_dcache_miss_clack.read() ) // waiting cleanup acknowledge
4117	{
4118	if ( r_dcache_miss_inval.read() ) // switch slot to ZOMBI state, and new cleanup
4119	{
4120	if ( not r_dcache_cc_send_req.read() ) // blocked until previous request sent
4121	{
4122	r_dcache_miss_inval = false;
4123	// request cleanup
4124	r_dcache_cc_send_req = true;
4125	r_dcache_cc_send_nline = r_dcache_save_paddr.read()/(m_dcache_words<<2);
4126	r_dcache_cc_send_way = r_dcache_miss_way.read();
4127	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
4128
4129	#ifdef INSTRUMENTATION
4130	m_cpt_dcache_dir_write++;
4131	#endif
4132	r_dcache.write_dir( r_dcache_save_paddr.read(),
4133	r_dcache_miss_way.read(),
4134	r_dcache_miss_set.read(),
4135	CACHE_SLOT_STATE_ZOMBI );
4136	#if DEBUG_DCACHE
4137	if ( m_debug_activated )
4138	std::cout << " <PROC " << name()
4139	<< " DCACHE_MISS_DIR_UPDT> Switch slot to ZOMBI state"
4140	<< " PADDR = " << std::hex << r_dcache_save_paddr.read()
4141	<< " / WAY = " << std::dec << r_dcache_miss_way.read()
4142	<< " / SET = " << r_dcache_miss_set.read() << std::endl;
4143	#endif
4144	}
4145	else
4146	break;
4147	}
4148	else // switch slot to VALID state
4149	{
4150
4151	#ifdef INSTRUMENTATION
4152	m_cpt_dcache_dir_write++;
4153	#endif
4154	r_dcache.write_dir( r_dcache_save_paddr.read(),
4155	r_dcache_miss_way.read(),
4156	r_dcache_miss_set.read(),
4157	CACHE_SLOT_STATE_VALID );
4158
4159	#if DEBUG_DCACHE
4160	if ( m_debug_activated )
4161	std::cout << " <PROC " << name()
4162	<< " DCACHE_MISS_DIR_UPDT> Switch slot to VALID state"
4163	<< " PADDR = " << std::hex << r_dcache_save_paddr.read()
4164	<< " / WAY = " << std::dec << r_dcache_miss_way.read()
4165	<< " / SET = " << r_dcache_miss_set.read() << std::endl;
4166	#endif
4167	// reset directory extension
4168	size_t way = r_dcache_miss_way.read();
4169	size_t set = r_dcache_miss_set.read();
4170	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
4171	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
4172	}
4173	if (r_dcache_miss_type.read()==PTE1_MISS) r_dcache_fsm = DCACHE_TLB_PTE1_GET;
4174	else if (r_dcache_miss_type.read()==PTE2_MISS) r_dcache_fsm = DCACHE_TLB_PTE2_GET;
4175	else r_dcache_fsm = DCACHE_IDLE;
4176	}
4177	break;
4178	}
4179	/////////////////////
4180	case DCACHE_UNC_WAIT: // waiting a response to an uncacheable read
4181	{
4182	// coherence request (from CC_RECEIVE FSM)
4183	if ( r_cc_receive_dcache_req.read() )
4184	{
4185	r_dcache_fsm = DCACHE_CC_CHECK;
4186	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4187	break;
4188	}
4189
4190	if ( r_vci_rsp_data_error.read() ) // bus error
4191	{
4192	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
4193	r_mmu_dbvar = m_dreq.addr;
4194	r_vci_rsp_data_error = false;
4195	m_drsp.error = true;
4196	m_drsp.valid = true;
4197	r_dcache_fsm = DCACHE_IDLE;
4198	break;
4199	}
4200	else if ( r_vci_rsp_fifo_dcache.rok() ) // data available
4201	{
4202	// consume data
4203	vci_rsp_fifo_dcache_get = true;
4204	r_dcache_fsm = DCACHE_IDLE;
4205
4206	// acknowledge the processor request if it has not been modified
4207	if ( m_dreq.valid and (m_dreq.addr == r_dcache_save_vaddr.read()) )
4208	{
4209	m_drsp.valid = true;
4210	m_drsp.error = false;
4211	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
4212	}
4213	}
4214	break;
4215	}
4216	/////////////////////
4217	case DCACHE_LL_WAIT: // waiting VCI response to a LL transaction
4218	{
4219	// coherence request (from CC_RECEIVE FSM)
4220	if ( r_cc_receive_dcache_req.read() )
4221	{
4222	r_dcache_fsm = DCACHE_CC_CHECK;
4223	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4224	break;
4225	}
4226
4227	if ( r_vci_rsp_data_error.read() ) // bus error
4228	{
4229	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
4230	r_mmu_dbvar = m_dreq.addr;
4231	r_vci_rsp_data_error = false;
4232	m_drsp.error = true;
4233	m_drsp.valid = true;
4234	r_dcache_fsm = DCACHE_IDLE;
4235	break;
4236	}
4237	else if ( r_vci_rsp_fifo_dcache.rok() ) // data available
4238	{
4239	// consume data
4240	vci_rsp_fifo_dcache_get = true;
4241
4242	if(r_dcache_ll_rsp_count.read() == 0) // first flit
4243	{
4244	// set key value in llsc reservation buffer
4245	r_dcache_llsc_key = r_vci_rsp_fifo_dcache.read();
4246	r_dcache_ll_rsp_count = r_dcache_ll_rsp_count.read() + 1 ;
4247	}
4248	else // last flit
4249	{
4250	// acknowledge the processor request if it has not been modified
4251	if ( m_dreq.valid and (m_dreq.addr == r_dcache_save_vaddr.read()) )
4252	{
4253	m_drsp.valid = true;
4254	m_drsp.error = false;
4255	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
4256	}
4257	r_dcache_fsm = DCACHE_IDLE;
4258	}
4259	}
4260	break;
4261	}
4262	////////////////////
4263	case DCACHE_SC_WAIT: // waiting VCI response to a SC transaction
4264	{
4265	// coherence request (from CC_RECEIVE FSM)
4266	if ( r_cc_receive_dcache_req.read() )
4267	{
4268	r_dcache_fsm = DCACHE_CC_CHECK;
4269	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4270	break;
4271	}
4272
4273	if ( r_vci_rsp_data_error.read() ) // bus error
4274	{
4275	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
4276	r_mmu_dbvar = m_dreq.addr;
4277	r_vci_rsp_data_error = false;
4278	m_drsp.error = true;
4279	m_drsp.valid = true;
4280	r_dcache_fsm = DCACHE_IDLE;
4281	break;
4282	}
4283	else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
4284	{
4285	// consume response
4286	vci_rsp_fifo_dcache_get = true;
4287	m_drsp.valid = true;
4288	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
4289	r_dcache_fsm = DCACHE_IDLE;
4290	}
4291	break;
4292	}
4293	//////////////////////////
4294	case DCACHE_DIRTY_GET_PTE: // This sub_fsm set the PTE Dirty bit in memory
4295	// before handling a processor WRITE or SC request
4296	// Input argument is r_dcache_dirty_paddr
4297	// In this first state, we get PTE value in dcache
4298	// and post a CAS request to CMD FSM
4299	{
4300	// get PTE in dcache
4301	uint32_t pte;
4302	size_t way;
4303	size_t set;
4304	size_t word; // unused
4305	int state;
4306
4307	#ifdef INSTRUMENTATION
4308	m_cpt_dcache_data_read++;
4309	m_cpt_dcache_dir_read++;
4310	#endif
4311	r_dcache.read( r_dcache_dirty_paddr.read(),
4312	&pte,
4313	&way,
4314	&set,
4315	&word,
4316	&state );
4317
4318	assert( (state == CACHE_SLOT_STATE_VALID) and
4319	"error in DCACHE_DIRTY_TLB_SET: the PTE should be in dcache" );
4320
4321	// request CAS transaction to CMD_FSM
4322	r_dcache_dirty_way = way;
4323	r_dcache_dirty_set = set;
4324
4325	// check llsc reservation buffer
4326	if (r_dcache_llsc_paddr.read() == r_dcache_dirty_paddr.read() )
4327	r_dcache_llsc_valid = false;
4328
4329	// request a CAS CMD and go to DCACHE_DIRTY_WAIT state
4330	r_dcache_vci_cas_req = true;
4331	r_dcache_vci_paddr = r_dcache_dirty_paddr.read();
4332	r_dcache_vci_cas_old = pte;
4333	r_dcache_vci_cas_new = pte \| PTE_D_MASK;
4334	r_dcache_fsm = DCACHE_DIRTY_WAIT;
4335
4336	#if DEBUG_DCACHE
4337	if ( m_debug_activated )
4338	{
4339	std::cout << " <PROC " << name()
4340	<< " DCACHE_DIRTY_GET_PTE> CAS request" << std::hex
4341	<< " / PTE_PADDR = " << r_dcache_dirty_paddr.read()
4342	<< " / PTE_VALUE = " << pte << std::dec
4343	<< " / SET = " << set
4344	<< " / WAY = " << way << std::endl;
4345	}
4346	#endif
4347	break;
4348	}
4349	///////////////////////
4350	case DCACHE_DIRTY_WAIT: // wait completion of CAS for PTE Dirty bit,
4351	// and return to IDLE state when response is received.
4352	// we don't care if the CAS is a failure:
4353	// - if the CAS is a success, the coherence mechanism
4354	// updates the local copy.
4355	// - if the CAS is a failure, we just retry the write.
4356	{
4357	// coherence request (from CC_RECEIVE FSM)
4358	if ( r_cc_receive_dcache_req.read() )
4359	{
4360	r_dcache_fsm = DCACHE_CC_CHECK;
4361	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4362	break;
4363	}
4364
4365	if ( r_vci_rsp_data_error.read() ) // bus error
4366	{
4367	std::cout << "BUS ERROR in DCACHE_DIRTY_WAIT state" << std::endl;
4368	std::cout << "This should not happen in this state" << std::endl;
4369	exit(0);
4370	}
4371	else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
4372	{
4373	vci_rsp_fifo_dcache_get = true;
4374	r_dcache_fsm = DCACHE_IDLE;
4375
4376	#if DEBUG_DCACHE
4377	if ( m_debug_activated )
4378	{
4379	std::cout << " <PROC " << name()
4380	<< " DCACHE_DIRTY_WAIT> CAS completed" << std::endl;
4381	}
4382	#endif
4383	}
4384	break;
4385	}
4386	/////////////////////
4387	case DCACHE_CC_CHECK: // This state is the entry point for the sub-FSM
4388	// handling coherence requests for DCACHE.
4389	// If there is a matching pending miss on the modified cache
4390	// line this is signaled in the r_dcache_miss inval flip-flop.
4391	// If the updated (or invalidated) cache line has copies in TLBs
4392	// these TLB copies are invalidated.
4393	// The return state is defined in r_dcache_fsm_cc_save
4394	{
4395	paddr_t paddr = r_cc_receive_dcache_nline.read() * m_dcache_words * 4;
4396	paddr_t mask = ~((m_dcache_words<<2)-1);
4397
4398	#if DEBUG_DCACHE
4399	if ( m_debug_activated )
4400	{
4401	std::cout << " <PROC " << name()
4402	<< " DCACHE_CC_CHECK> paddr = " << paddr
4403	<< " r_dcache_vci_paddr = " << r_dcache_vci_paddr.read()
4404	<< " mask = " << mask
4405	<< " (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) = "
4406	<< (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT)
4407	<< " (r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT) = "
4408	<< (r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT)
4409	<< " ((r_dcache_vci_paddr.read() & mask) == (paddr & mask)) = "
4410	<< ((r_dcache_vci_paddr.read() & mask) == (paddr & mask))
4411	<<std::endl;
4412	}
4413	#endif
4414
4415	if (r_cc_receive_dcache_type.read() == CC_TYPE_CLACK)
4416	// We switch the directory slot to EMPTY state
4417	// and reset r_icache_miss_clack if the cleanup ack
4418	// is matching a pending miss.
4419	{
4420
4421	if ( m_dreq.valid ) m_cost_data_miss_frz++;
4422
4423	#ifdef INSTRUMENTATION
4424	m_cpt_dcache_dir_write++;
4425	#endif
4426	r_dcache.write_dir( 0,
4427	r_cc_receive_dcache_way.read(),
4428	r_cc_receive_dcache_set.read(),
4429	CACHE_SLOT_STATE_EMPTY);
4430
4431	if ( (r_dcache_miss_set.read() == r_cc_receive_dcache_set.read()) and
4432	(r_dcache_miss_way.read() == r_cc_receive_dcache_way.read()) )
4433	r_dcache_miss_clack = false;
4434
4435	r_dcache_fsm = r_dcache_fsm_cc_save.read() ;
4436	r_cc_receive_dcache_req = false;
4437	#if DEBUG_DCACHE
4438	if ( m_debug_activated )
4439	{
4440	std::cout << " <PROC " << name()
4441	<< " DCACHE_CC_CHECK> CC_TYPE_CLACK Switch slot to EMPTY state"
4442	<< " set = " << r_cc_receive_dcache_set.read()
4443	<< " / way = " << r_cc_receive_dcache_way.read() << std::endl;
4444	}
4445	#endif
4446	}
4447	else if( ((r_dcache_fsm_cc_save == DCACHE_MISS_SELECT) or
4448	(r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) or
4449	(r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT)) and
4450	((r_dcache_vci_paddr.read() & mask) == (paddr & mask)) ) // matching
4451	{
4452	// signaling matching
4453	r_dcache_miss_inval = true;
4454
4455	// in case of update, go to CC_UPDT
4456	// JUST TO POP THE FIFO
4457	if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT)
4458	{
4459	r_dcache_fsm = DCACHE_CC_UPDT;
4460	r_dcache_cc_word = r_cc_receive_word_idx.read();
4461	// just pop the fifo , don't write in icache
4462	r_dcache_cc_need_write = false;
4463	}
4464	// the request is dealt with
4465	else
4466	{
4467	r_cc_receive_dcache_req = false;
4468	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4469	}
4470
4471	#if DEBUG_DCACHE
4472	if ( m_debug_activated )
4473	{
4474	std::cout << " <PROC " << name()
4475	<< " DCACHE_CC_CHECK> Coherence request matching a pending miss:"
4476	<< " PADDR = " << std::hex << paddr << std::endl;
4477	}
4478	#endif
4479
4480	}
4481	else // no match
4482	{
4483	int state;
4484	size_t way;
4485	size_t set;
4486	size_t word;
4487
4488	#ifdef INSTRUMENTATION
4489	m_cpt_dcache_dir_read++;
4490	#endif
4491	r_dcache.read_dir( paddr,
4492	&state,
4493	&way,
4494	&set,
4495	&word ); // unused
4496
4497	r_dcache_cc_way = way;
4498	r_dcache_cc_set = set;
4499
4500	if ( state == CACHE_SLOT_STATE_VALID) // hit
4501	{
4502	// need to update the cache state
4503	r_dcache_cc_need_write = true;
4504	if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT) // hit update
4505	{
4506	r_dcache_fsm = DCACHE_CC_UPDT;
4507	r_dcache_cc_word = r_cc_receive_word_idx.read();
4508	}
4509	else if (r_cc_receive_dcache_type.read() == CC_TYPE_INVAL) // hit inval
4510	{
4511	r_dcache_fsm = DCACHE_CC_INVAL;
4512	}
4513	else if ( r_cc_receive_dcache_type.read() == CC_TYPE_BRDCAST) // hit broadcast
4514	{
4515	r_dcache_fsm = DCACHE_CC_BROADCAST;
4516	}
4517	}
4518	else // miss
4519	{
4520	// multicast acknowledgement required in case of update
4521	if(r_cc_receive_dcache_type.read() == CC_TYPE_UPDT)
4522	{
4523	r_dcache_fsm = DCACHE_CC_UPDT;
4524	r_dcache_cc_word = r_cc_receive_word_idx.read();
4525	// just pop the fifo , don't write in icache
4526	r_dcache_cc_need_write = false;
4527	}
4528	else // No response needed
4529	{
4530	r_cc_receive_dcache_req = false;
4531	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4532	}
4533	}
4534
4535	#if DEBUG_DCACHE
4536	if ( m_debug_activated )
4537	{
4538	std::cout << " <PROC " << name()
4539	<< " DCACHE_CC_CHECK> Coherence request received:"
4540	<< " PADDR = " << std::hex << paddr
4541	<< " / TYPE = " << std::dec << r_cc_receive_dcache_type.read()
4542	<< " / HIT = " << (state == CACHE_SLOT_STATE_VALID) << std::endl;
4543	}
4544	#endif
4545	}
4546	break;
4547	}
4548	/////////////////////
4549	case DCACHE_CC_INVAL: // hit inval: switch slot to EMPTY state,
4550	// after possible invalidation of copies in TLBs
4551	{
4552	size_t way = r_dcache_cc_way.read();
4553	size_t set = r_dcache_cc_set.read();
4554
4555	if (r_dcache_cc_need_write.read())
4556	{
4557	if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // selective TLB inval
4558	{
4559	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
4560	r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read();
4561	r_dcache_tlb_inval_set = 0;
4562	r_dcache_fsm_scan_save = r_dcache_fsm.read();
4563	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4564	break;
4565	}
4566	else
4567	{
4568	if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // TLB flush
4569	{
4570	r_itlb.reset();
4571	r_dtlb.reset();
4572	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
4573
4574	#if DEBUG_DCACHE
4575	if ( m_debug_activated )
4576	{
4577	std::cout << " <PROC " << name()
4578	<< " DCACHE_CC_INVAL> Flush DTLB & ITLB" << std::endl;
4579	}
4580	#endif
4581	}
4582
4583	r_dcache.write_dir( 0,
4584	way,
4585	set,
4586	CACHE_SLOT_STATE_EMPTY );
4587
4588	r_dcache_cc_need_write = false;
4589
4590	#if DEBUG_DCACHE
4591	if ( m_debug_activated )
4592	{
4593	std::cout << " <PROC " << name()
4594	<< " DCACHE_CC_INVAL> Switch slot to EMPTY state:" << std::dec
4595	<< " / WAY = " << way
4596	<< " / SET = " << set << std::endl;
4597	}
4598	#endif
4599	}
4600	}
4601	// multicast acknowledgement
4602	// send a request to cc_send_fsm
4603	if(not r_dcache_cc_send_req.read()) // cc_send is available
4604	{
4605	// coherence request completed
4606	r_cc_receive_dcache_req = false;
4607	// request multicast acknowledgement
4608	r_dcache_cc_send_req = true;
4609	r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read();
4610	r_dcache_cc_send_updt_tab_idx = r_cc_receive_dcache_updt_tab_idx.read();
4611	r_dcache_cc_send_type = CC_TYPE_MULTI_ACK;
4612
4613	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4614	}
4615	//else wait for previous cc_send request to be sent
4616	break;
4617	}
4618	///////////////////
4619	case DCACHE_CC_UPDT: // hit update: write one word per cycle,
4620	// after possible invalidation of copies in TLBs
4621	{
4622	size_t word = r_dcache_cc_word.read();
4623	size_t way = r_dcache_cc_way.read();
4624	size_t set = r_dcache_cc_set.read();
4625
4626	if (r_cc_receive_updt_fifo_be.rok())
4627	{
4628	if (r_dcache_cc_need_write.read())
4629	{
4630	if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // selective TLB inval
4631	{
4632	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
4633	r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read();
4634	r_dcache_tlb_inval_set = 0;
4635	r_dcache_fsm_scan_save = r_dcache_fsm.read();
4636	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4637	break;
4638	}
4639
4640	if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // TLB flush
4641	{
4642	r_itlb.reset();
4643	r_dtlb.reset();
4644	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
4645
4646	#if DEBUG_DCACHE
4647	if ( m_debug_activated )
4648	{
4649	std::cout << " <PROC " << name()
4650	<< " DCACHE_CC_UPDT> Flush DTLB & ITLB" << std::endl;
4651	}
4652	#endif
4653	}
4654
4655	#ifdef INSTRUMENTATION
4656	m_cpt_dcache_data_write++;
4657	#endif
4658	r_dcache.write( way,
4659	set,
4660	word,
4661	r_cc_receive_updt_fifo_data.read(),
4662	r_cc_receive_updt_fifo_be.read() );
4663
4664	r_dcache_cc_word = word + 1;
4665
4666	#if DEBUG_DCACHE
4667	if ( m_debug_activated )
4668	{
4669	std::cout << " <PROC " << name()
4670	<< " DCACHE_CC_UPDT> Write one word" << std::dec
4671	<< " / WAY = " << way
4672	<< " / SET = " << set
4673	<< " / WORD = " << word
4674	<< " / VALUE = " << std::hex << r_cc_receive_updt_fifo_data.read() << std::endl;
4675	}
4676	#endif
4677	}
4678
4679	if ( r_cc_receive_updt_fifo_eop.read() ) // last word
4680	{
4681	// no need to write in the cache anymore
4682	r_dcache_cc_need_write = false;
4683
4684	// wait to send a request to cc_send_fsm
4685	if(not r_dcache_cc_send_req.read())
4686	// cc_send is available
4687	{
4688	//consume last fifo flit if eop and request to cc_send possible
4689	cc_receive_updt_fifo_get = true;
4690
4691	// coherence request completed
4692	r_cc_receive_dcache_req = false;
4693
4694	// request multicast acknowledgement
4695	r_dcache_cc_send_req = true;
4696	r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read();
4697	r_dcache_cc_send_updt_tab_idx = r_cc_receive_dcache_updt_tab_idx.read();
4698	r_dcache_cc_send_type = CC_TYPE_MULTI_ACK;
4699
4700	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4701	}
4702	}
4703	else
4704	{
4705	//consume fifo if not eop
4706	cc_receive_updt_fifo_get = true;
4707	}
4708	}
4709	break;
4710	}
4711	/////////////////////////
4712	case DCACHE_CC_BROADCAST: // hit broadcast : switch state to ZOMBI state
4713	// and request a cleanup, after possible
4714	// invalidation of copies in TLBs
4715	{
4716	size_t way = r_dcache_cc_way.read();
4717	size_t set = r_dcache_cc_set.read();
4718	paddr_t nline = r_cc_receive_dcache_nline.read();
4719
4720	if (r_dcache_cc_need_write.read())
4721	{
4722	if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // selective TLB inval
4723	{
4724	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
4725	r_dcache_tlb_inval_line = nline;
4726	r_dcache_tlb_inval_set = 0;
4727	r_dcache_fsm_scan_save = r_dcache_fsm.read();
4728	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4729	break;
4730	}
4731	else
4732	{
4733	if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // TLB flush
4734	{
4735	r_itlb.reset();
4736	r_dtlb.reset();
4737	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
4738
4739	#if DEBUG_DCACHE
4740	if ( m_debug_activated )
4741	{
4742	std::cout << " <PROC " << name()
4743	<< " DCACHE_CC_BROADCAST> Flush DTLB & ITLB" << std::endl;
4744	}
4745	#endif
4746	}
4747
4748	#ifdef INSTRUMENTATION
4749	m_cpt_dcache_dir_write++;
4750	#endif
4751	r_dcache.write_dir( way,
4752	set,
4753	CACHE_SLOT_STATE_ZOMBI );
4754
4755	r_dcache_cc_need_write = false;
4756	#if DEBUG_DCACHE
4757	if ( m_debug_activated )
4758	{
4759	std::cout << " <PROC " << name()
4760	<< " DCACHE_CC_BROADCAST > Slot goes to ZOMBI state "
4761	<< " SET = " << set
4762	<< " / WAY = " << way << std::endl;
4763	}
4764	#endif
4765	}
4766	}
4767	// cleanup
4768	// send a request to cc_send_fsm
4769	if(not r_dcache_cc_send_req.read()) // cc_send is available
4770	{
4771	// coherence request completed
4772	r_cc_receive_dcache_req = false;
4773	// request cleanup
4774	r_dcache_cc_send_req = true;
4775	r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read();
4776	r_dcache_cc_send_way = r_dcache_cc_way.read();
4777	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
4778
4779	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4780	}
4781	//else wait for previous cc_send request to be sent
4782	break;
4783	}
4784	///////////////////////////
4785	case DCACHE_INVAL_TLB_SCAN: // Scan sequencially all sets for both ITLB & DTLB
4786	// It makes assumption: m_itlb_sets == m_dtlb_sets
4787	// All ways are handled in parallel.
4788	// We enter this state when a DCACHE line is modified,
4789	// and there is a copy in itlb or dtlb.
4790	// It can be caused by:
4791	// - a coherence inval or updt transaction,
4792	// - a line inval caused by a cache miss
4793	// - a processor XTN inval request,
4794	// - a WRITE hit,
4795	// - a Dirty bit update
4796	// Input arguments are:
4797	// - r_dcache_tlb_inval_line
4798	// - r_dcache_tlb_inval_set
4799	// - r_dcache_fsm_scan_save
4800	{
4801	paddr_t line = r_dcache_tlb_inval_line.read();
4802	size_t set = r_dcache_tlb_inval_set.read();
4803	size_t way;
4804	bool ok;
4805
4806	for ( way = 0 ; way < m_itlb_ways ; way++ )
4807	{
4808	ok = r_itlb.inval( line, way, set );
4809
4810	#if DEBUG_DCACHE
4811	if ( m_debug_activated and ok )
4812	{
4813	std::cout << " <PROC " << name()
4814	<< ".DCACHE_INVAL_TLB_SCAN> Invalidate ITLB entry:" << std::hex
4815	<< " line = " << line << std::dec
4816	<< " / set = " << set
4817	<< " / way = " << way << std::endl;
4818	}
4819	#endif
4820	}
4821
4822	for ( way = 0 ; way < m_dtlb_ways ; way++ )
4823	{
4824	ok = r_dtlb.inval( line, way, set );
4825
4826	#if DEBUG_DCACHE
4827	if ( m_debug_activated and ok )
4828	std::cout << " <PROC " << name() << " DCACHE_INVAL_TLB_SCAN>"
4829	<< " Invalidate DTLB entry" << std::hex
4830	<< " / line = " << line << std::dec
4831	<< " / set = " << set
4832	<< " / way = " << way << std::endl;
4833	#endif
4834	}
4835
4836	// return to the calling state when TLB inval completed
4837	if ( r_dcache_tlb_inval_set.read() == (m_dtlb_sets-1) )
4838	{
4839	r_dcache_fsm = r_dcache_fsm_scan_save.read();
4840	}
4841	r_dcache_tlb_inval_set = r_dcache_tlb_inval_set.read() + 1;
4842	break;
4843	}
4844	} // end switch r_dcache_fsm
4845
4846	///////////////// wbuf update ///////////////////////////////////////////////////////
4847	r_wbuf.update();
4848
4849	///////////////// llsc update ///////////////////////////////////////////////////////
4850	if (r_dcache_llsc_valid.read()) r_dcache_llsc_count = r_dcache_llsc_count.read() - 1;
4851	if (r_dcache_llsc_count.read() == 1) r_dcache_llsc_valid = false;
4852
4853	//////////////// test processor frozen //////////////////////////////////////////////
4854	// The simulation exit if the number of consecutive frozen cycles
4855	// is larger than the m_max_frozen_cycles (constructor parameter)
4856	if ( (m_ireq.valid and not m_irsp.valid) or (m_dreq.valid and not m_drsp.valid) )
4857	{
4858	m_cpt_frz_cycles++; // used for instrumentation
4859	m_cpt_stop_simulation++; // used for debug
4860	if ( m_cpt_stop_simulation > m_max_frozen_cycles )
4861	{
4862	std::cout << std::dec << "ERROR in CC_VCACHE_WRAPPER " << name() << std::endl
4863	<< " stop at cycle " << m_cpt_total_cycles << std::endl
4864	<< " frozen since cycle " << m_cpt_total_cycles - m_max_frozen_cycles
4865	<< std::endl;
4866	r_iss.dump();
4867	exit(1);
4868	}
4869	}
4870	else
4871	{
4872	m_cpt_stop_simulation = 0;
4873	}
4874
4875	/////////// execute one iss cycle /////////////////////////////////
4876	{
4877	uint32_t it = 0;
4878	for (size_t i=0; i<(size_t)iss_t::n_irq; i++) if(p_irq[i].read()) it \|= (1<<i);
4879	r_iss.executeNCycles(1, m_irsp, m_drsp, it);
4880	}
4881
4882	////////////////////////////////////////////////////////////////////////////
4883	// The VCI_CMD FSM controls the following ressources:
4884	// - r_vci_cmd_fsm
4885	// - r_vci_cmd_min
4886	// - r_vci_cmd_max
4887	// - r_vci_cmd_cpt
4888	// - r_vci_cmd_imiss_prio
4889	// - wbuf (reset)
4890	// - r_icache_miss_req (reset)
4891	// - r_icache_unc_req (reset)
4892	// - r_dcache_vci_miss_req (reset)
4893	// - r_dcache_vci_unc_req (reset)
4894	// - r_dcache_vci_ll_req (reset)
4895	// - r_dcache_vci_sc_req (reset in case of local sc fail)
4896	// - r_dcache_vci_cas_req (reset)
4897	//
4898	// This FSM handles requests from both the DCACHE FSM & the ICACHE FSM.
4899	// There are 8 request types, with the following priorities :
4900	// 1 - Data Read Miss : r_dcache_vci_miss_req and miss in the write buffer
4901	// 2 - Data Read Uncachable : r_dcache_vci_unc_req
4902	// 3 - Instruction Miss : r_icache_miss_req and miss in the write buffer
4903	// 4 - Instruction Uncachable : r_icache_unc_req
4904	// 5 - Data Write : r_wbuf.rok()
4905	// 6 - Data Linked Load : r_dcache_vci_ll_req
4906	// 7 - Data Store Conditionnal: r_dcache_vci_sc_req
4907	// 8 - Compare And Swap : r_dcache_vci_cas_req
4908	//
4909	// As we want to support several simultaneous VCI transactions, the VCI_CMD_FSM
4910	// and the VCI_RSP_FSM are fully desynchronized.
4911	//
4912	// VCI formats:
4913	// According to the VCI advanced specification, all read requests packets
4914	// (data Uncached, Miss data, instruction Uncached, Miss instruction)
4915	// are one word packets.
4916	// For write burst packets, all words are in the same cache line,
4917	// and addresses must be contiguous (the BE field is 0 in case of "holes").
4918	// The sc command packet implements actually a compare-and-swap mechanism
4919	// and the packet contains two flits.
4920	////////////////////////////////////////////////////////////////////////////////////
4921
4922	switch ( r_vci_cmd_fsm.read() )
4923	{
4924	//////////////
4925	case CMD_IDLE:
4926	{
4927	// DCACHE read requests (r_dcache_vci_miss_req or r_dcache_vci_ll_req), and
4928	// ICACHE read requests (r_icache_miss_req) require both a write_buffer access
4929	// to check a possible pending write on the same cache line.
4930	// As there is only one possible access per cycle to write buffer, we implement
4931	// a round-robin priority between DCACHE and ICACHE for this access,
4932	// using the r_vci_cmd_imiss_prio flip-flop.
4933
4934	size_t wbuf_min;
4935	size_t wbuf_max;
4936
4937	bool dcache_unc_req = r_dcache_vci_unc_req.read() and
4938	( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() );
4939
4940	bool dcache_miss_req = r_dcache_vci_miss_req.read() and
4941	( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() );
4942
4943	bool dcache_ll_req = r_dcache_vci_ll_req.read() and
4944	( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() );
4945
4946	bool icache_miss_req = r_icache_miss_req.read() and
4947	( not (r_dcache_vci_miss_req.read() or
4948	r_dcache_vci_ll_req.read() or
4949	r_dcache_vci_unc_req.read())
4950	or r_vci_cmd_imiss_prio.read() );
4951
4952	// 1 - Data Read Miss
4953	if ( dcache_miss_req and r_wbuf.miss(r_dcache_vci_paddr.read()) )
4954	{
4955	r_vci_cmd_fsm = CMD_DATA_MISS;
4956	r_dcache_vci_miss_req = false;
4957	r_vci_cmd_imiss_prio = true;
4958	// m_cpt_dmiss_transaction++;
4959	}
4960	// 2 - Data Read Uncachable
4961	else if ( dcache_unc_req and r_wbuf.miss(r_dcache_vci_paddr.read()))
4962	{
4963	r_vci_cmd_fsm = CMD_DATA_UNC;
4964	r_dcache_vci_unc_req = false;
4965	// m_cpt_dunc_transaction++;
4966	}
4967	// 3 - Data Linked Load
4968	else if ( dcache_ll_req and r_wbuf.miss(r_dcache_vci_paddr.read()))
4969	{
4970	r_dcache_vci_ll_req = false;
4971	r_vci_cmd_fsm = CMD_DATA_LL;
4972	// m_cpt_ll_transaction++;
4973	}
4974	// 4 - Instruction Miss
4975	else if ( icache_miss_req and r_wbuf.miss(r_icache_vci_paddr.read()) )
4976	{
4977	r_vci_cmd_fsm = CMD_INS_MISS;
4978	r_icache_miss_req = false;
4979	r_vci_cmd_imiss_prio = false;
4980	// m_cpt_imiss_transaction++;
4981	}
4982	// 5 - Instruction Uncachable
4983	else if ( r_icache_unc_req.read() )
4984	{
4985	r_vci_cmd_fsm = CMD_INS_UNC;
4986	r_icache_unc_req = false;
4987	// m_cpt_iunc_transaction++;
4988	}
4989	// 6 - Data Write
4990	else if ( r_wbuf.rok(&wbuf_min, &wbuf_max) )
4991	{
4992	r_vci_cmd_fsm = CMD_DATA_WRITE;
4993	r_vci_cmd_cpt = wbuf_min;
4994	r_vci_cmd_min = wbuf_min;
4995	r_vci_cmd_max = wbuf_max;
4996	// m_cpt_write_transaction++;
4997	// m_length_write_transaction += (wbuf_max-wbuf_min+1);
4998	}
4999	// 7 - Data Store Conditionnal
5000	else if ( r_dcache_vci_sc_req.read() )
5001	{
5002	r_dcache_vci_sc_req = false;
5003	r_vci_cmd_cpt = 0;
5004	r_vci_cmd_fsm = CMD_DATA_SC;
5005	// m_cpt_sc_transaction++;
5006	}
5007	// 8 - Compare And Swap
5008	else if ( r_dcache_vci_cas_req.read() )
5009	{
5010	r_vci_cmd_fsm = CMD_DATA_CAS;
5011	r_dcache_vci_cas_req = false;
5012	r_vci_cmd_cpt = 0;
5013	// m_cpt_cas_transaction++;
5014	}
5015
5016	#if DEBUG_CMD
5017	if ( m_debug_activated )
5018	{
5019	std::cout << " <PROC " << name() << " CMD_IDLE>"
5020	<< " / dmiss_req = " << dcache_miss_req
5021	<< " / imiss_req = " << icache_miss_req
5022	<< std::endl;
5023	}
5024	#endif
5025	break;
5026	}
5027	////////////////////
5028	case CMD_DATA_WRITE:
5029	{
5030	if ( p_vci.cmdack.read() )
5031	{
5032	r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
5033	if (r_vci_cmd_cpt == r_vci_cmd_max) // last flit sent
5034	{
5035	r_vci_cmd_fsm = CMD_IDLE ;
5036	r_wbuf.sent() ;
5037	}
5038	}
5039	break;
5040	}
5041	/////////////////
5042	case CMD_DATA_SC:
5043	case CMD_DATA_CAS:
5044	{
5045	// The CAS and SC VCI commands contain two flits
5046	if ( p_vci.cmdack.read() )
5047	{
5048	r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
5049	if (r_vci_cmd_cpt == 1) r_vci_cmd_fsm = CMD_IDLE ;
5050	}
5051	break;
5052	}
5053	//////////////////
5054	case CMD_INS_MISS:
5055	case CMD_INS_UNC:
5056	case CMD_DATA_MISS:
5057	case CMD_DATA_UNC:
5058	case CMD_DATA_LL:
5059	{
5060	// all read VCI commands contain one single flit
5061	if ( p_vci.cmdack.read() ) r_vci_cmd_fsm = CMD_IDLE;
5062	break;
5063	}
5064
5065	} // end switch r_vci_cmd_fsm
5066
5067	//////////////////////////////////////////////////////////////////////////
5068	// The VCI_RSP FSM controls the following ressources:
5069	// - r_vci_rsp_fsm:
5070	// - r_vci_rsp_fifo_icache (push)
5071	// - r_vci_rsp_fifo_dcache (push)
5072	// - r_vci_rsp_data_error (set)
5073	// - r_vci_rsp_ins_error (set)
5074	// - r_vci_rsp_cpt
5075	// - r_dcache_vci_sc_req (reset when SC response recieved)
5076	//
5077	// As the VCI_RSP and VCI_CMD are fully desynchronized to support several
5078	// simultaneous VCI transactions, this FSM uses the VCI RPKTID field
5079	// to identify the transactions.
5080	//
5081	// VCI vormat:
5082	// This component checks the response packet length and accepts only
5083	// single word packets for write response packets.
5084	//
5085	// Error handling:
5086	// This FSM analyzes the VCI error code and signals directly the Write Bus Error.
5087	// In case of Read Data Error, the VCI_RSP FSM sets the r_vci_rsp_data_error
5088	// flip_flop and the error is signaled by the DCACHE FSM.
5089	// In case of Instruction Error, the VCI_RSP FSM sets the r_vci_rsp_ins_error
5090	// flip_flop and the error is signaled by the ICACHE FSM.
5091	// In case of Cleanup Error, the simulation stops with an error message...
5092	//////////////////////////////////////////////////////////////////////////
5093
5094	switch ( r_vci_rsp_fsm.read() )
5095	{
5096	//////////////
5097	case RSP_IDLE:
5098	{
5099	if ( p_vci.rspval.read() )
5100	{
5101	r_vci_rsp_cpt = 0;
5102
5103	if ( (p_vci.rpktid.read() & 0x7) == TYPE_READ_DATA_UNC )
5104	{
5105	r_vci_rsp_fsm = RSP_DATA_UNC;
5106	}
5107	else if ( (p_vci.rpktid.read() & 0x7) == TYPE_READ_DATA_MISS )
5108	{
5109	r_vci_rsp_fsm = RSP_DATA_MISS;
5110	}
5111	else if ( (p_vci.rpktid.read() & 0x7) == TYPE_READ_INS_UNC )
5112	{
5113	r_vci_rsp_fsm = RSP_INS_UNC;
5114	}
5115	else if ( (p_vci.rpktid.read() & 0x7) == TYPE_READ_INS_MISS )
5116	{
5117	r_vci_rsp_fsm = RSP_INS_MISS;
5118	}
5119	else if ( (p_vci.rpktid.read() & 0x7) == TYPE_WRITE )
5120	{
5121	r_vci_rsp_fsm = RSP_DATA_WRITE;
5122	}
5123	else if ( (p_vci.rpktid.read() & 0x7) == TYPE_CAS )
5124	{
5125	r_vci_rsp_fsm = RSP_DATA_UNC;
5126	}
5127	else if ( (p_vci.rpktid.read() & 0x7) == TYPE_LL )
5128	{
5129	r_vci_rsp_fsm = RSP_DATA_LL;
5130	}
5131	else if ( (p_vci.rpktid.read() & 0x7) == TYPE_SC )
5132	{
5133	r_vci_rsp_fsm = RSP_DATA_UNC;
5134	}
5135	else
5136	{
5137	assert(false and "Unexpected VCI response");
5138	}
5139	}
5140	break;
5141	}
5142	//////////////////
5143	case RSP_INS_MISS:
5144	{
5145	if ( p_vci.rspval.read() )
5146	{
5147	if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported
5148	{
5149	r_vci_rsp_ins_error = true;
5150	if ( p_vci.reop.read() ) r_vci_rsp_fsm = RSP_IDLE;
5151	}
5152	else // no error reported
5153	{
5154	if ( r_vci_rsp_fifo_icache.wok() )
5155	{
5156	assert( (r_vci_rsp_cpt.read() < m_icache_words) and
5157	"The VCI response packet for instruction miss is too long" );
5158
5159	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
5160	vci_rsp_fifo_icache_put = true,
5161	vci_rsp_fifo_icache_data = p_vci.rdata.read();
5162	if ( p_vci.reop.read() )
5163	{
5164	assert( (r_vci_rsp_cpt.read() == m_icache_words - 1) and
5165	"The VCI response packet for instruction miss is too short");
5166
5167	r_vci_rsp_fsm = RSP_IDLE;
5168	}
5169	}
5170	}
5171	}
5172	break;
5173	}
5174	/////////////////
5175	case RSP_INS_UNC:
5176	{
5177	if (p_vci.rspval.read() )
5178	{
5179	assert( p_vci.reop.read() and
5180	"illegal VCI response packet for uncachable instruction");
5181
5182	if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported
5183	{
5184	r_vci_rsp_ins_error = true;
5185	r_vci_rsp_fsm = RSP_IDLE;
5186	}
5187	else // no error reported
5188	{
5189	if ( r_vci_rsp_fifo_icache.wok())
5190	{
5191	vci_rsp_fifo_icache_put = true;
5192	vci_rsp_fifo_icache_data = p_vci.rdata.read();
5193	r_vci_rsp_fsm = RSP_IDLE;
5194	}
5195	}
5196	}
5197	break;
5198	}
5199	///////////////////
5200	case RSP_DATA_MISS:
5201	{
5202	if ( p_vci.rspval.read() )
5203	{
5204	if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported
5205	{
5206	r_vci_rsp_data_error = true;
5207	if ( p_vci.reop.read() ) r_vci_rsp_fsm = RSP_IDLE;
5208	}
5209	else // no error reported
5210	{
5211	if ( r_vci_rsp_fifo_dcache.wok() )
5212	{
5213	assert( (r_vci_rsp_cpt.read() < m_dcache_words) and
5214	"The VCI response packet for data miss is too long");
5215
5216	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
5217	vci_rsp_fifo_dcache_put = true,
5218	vci_rsp_fifo_dcache_data = p_vci.rdata.read();
5219	if ( p_vci.reop.read() )
5220	{
5221	assert( (r_vci_rsp_cpt.read() == m_dcache_words - 1) and
5222	"The VCI response packet for data miss is too short");
5223
5224	r_vci_rsp_fsm = RSP_IDLE;
5225	}
5226	}
5227	}
5228	}
5229	break;
5230	}
5231	//////////////////
5232	case RSP_DATA_UNC:
5233	{
5234	if (p_vci.rspval.read() )
5235	{
5236	assert( p_vci.reop.read() and
5237	"illegal VCI response packet for uncachable read data");
5238
5239	if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported
5240	{
5241	r_vci_rsp_data_error = true;
5242	r_vci_rsp_fsm = RSP_IDLE;
5243	}
5244	else // no error reported
5245	{
5246	if ( r_vci_rsp_fifo_dcache.wok())
5247	{
5248	vci_rsp_fifo_dcache_put = true;
5249	vci_rsp_fifo_dcache_data = p_vci.rdata.read();
5250	r_vci_rsp_fsm = RSP_IDLE;
5251	}
5252	}
5253	}
5254	break;
5255	}
5256	////////////////////
5257	case RSP_DATA_LL:
5258	{
5259	if ( p_vci.rspval.read() )
5260	{
5261	if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported
5262	{
5263	r_vci_rsp_data_error = true;
5264	r_vci_rsp_fsm = RSP_IDLE;
5265	}
5266	if (r_vci_rsp_cpt.read() == 0) //first flit
5267	{
5268	if(r_vci_rsp_fifo_dcache.wok())
5269	{
5270	assert(!p_vci.reop.read() &&
5271	"illegal VCI response packet for LL");
5272	vci_rsp_fifo_dcache_put = true;
5273	vci_rsp_fifo_dcache_data = p_vci.rdata.read();
5274	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
5275	}
5276	break;
5277	}
5278	else // last flit
5279	{
5280	if(r_vci_rsp_fifo_dcache.wok())
5281	{
5282	assert(p_vci.reop.read() &&
5283	"illegal VCI response packet for LL");
5284	vci_rsp_fifo_dcache_put = true;
5285	vci_rsp_fifo_dcache_data = p_vci.rdata.read();
5286	r_vci_rsp_fsm = RSP_IDLE;
5287	}
5288	break;
5289	}
5290	}
5291	break;
5292	}
5293	////////////////////
5294	case RSP_DATA_WRITE:
5295	{
5296	if (p_vci.rspval.read())
5297	{
5298	assert( p_vci.reop.read() and
5299	"a VCI response packet must contain one flit for a write transaction");
5300
5301	r_vci_rsp_fsm = RSP_IDLE;
5302	uint32_t wbuf_index = p_vci.rtrdid.read();
5303	bool cacheable = r_wbuf.completed(wbuf_index);
5304	if ( not cacheable ) r_dcache_pending_unc_write = false;
5305	if ( (p_vci.rerror.read()&0x1) != 0 ) r_iss.setWriteBerr();
5306	}
5307	break;
5308	}
5309	} // end switch r_vci_rsp_fsm
5310
5311	/////////////////////////////////////////////////////////////////////////////////////
5312	// The CC_SEND FSM is in charge of sending cleanups and the multicast
5313	// acknowledgements on the coherence network. It has two clients (DCACHE FSM
5314	// and ICACHE FSM) that are served with a round-robin priority.
5315	// The CC_SEND FSM resets the r_*cache_cc_send_req request flip-flops as
5316	// soon as the request has been sent.
5317	/////////////////////////////////////////////////////////////////////////////////////
5318	switch ( r_cc_send_fsm.read() )
5319	{
5320	///////////////////////////
5321	case CC_SEND_IDLE:
5322	{
5323	///////////////////////////////////////////////////////
5324	// handling round robin between icache and dcache : //
5325	// we first check for the last client and listen for //
5326	// a request of the other, then update the client //
5327	// r_cc_send_last_client : 0 dcache / 1 icache
5328	///////////////////////////////////////////////////////
5329	bool update_last_client = r_cc_send_last_client.read();
5330	if ( r_cc_send_last_client.read() == 0 ) // last client was dcache
5331	{
5332	if (r_icache_cc_send_req.read()) // request from icache
5333	update_last_client = 1; // update last client to icache
5334	}
5335	else // last client was icache
5336	{
5337	if (r_dcache_cc_send_req.read()) // request from dcache
5338	update_last_client = 0; // update last client to dcache
5339	}
5340	r_cc_send_last_client = update_last_client;
5341
5342	// if there is an actual request
5343	if (r_dcache_cc_send_req.read() or r_icache_cc_send_req.read())
5344	{
5345	// the new client is dcache and has a cleanup request
5346	if ( (update_last_client == 0) and
5347	(r_dcache_cc_send_type.read() == CC_TYPE_CLEANUP))
5348	r_cc_send_fsm = CC_SEND_CLEANUP_1;
5349	// the new client is dcache and has a multi acknowledgement request
5350	else if ( (update_last_client == 0) and
5351	(r_dcache_cc_send_type.read() == CC_TYPE_MULTI_ACK))
5352	r_cc_send_fsm = CC_SEND_MULTI_ACK;
5353	// the new client is icache and has a cleanup request
5354	else if ( (update_last_client == 1) and
5355	(r_icache_cc_send_type.read() == CC_TYPE_CLEANUP))
5356	r_cc_send_fsm = CC_SEND_CLEANUP_1;
5357	// the new client is icache and has a multi acknowledgement request
5358	else if ( (update_last_client == 1) and
5359	(r_icache_cc_send_type.read() == CC_TYPE_MULTI_ACK))
5360	r_cc_send_fsm = CC_SEND_MULTI_ACK;
5361	}
5362	break;
5363	}
5364	///////////////////////////
5365	case CC_SEND_CLEANUP_1:
5366	{
5367	// wait for the first flit to be consumed
5368	if (p_dspin_out.read.read())
5369	r_cc_send_fsm = CC_SEND_CLEANUP_2;
5370
5371	break;
5372	}
5373	///////////////////////////
5374	case CC_SEND_CLEANUP_2:
5375	{
5376	// wait for the second flit to be consumed
5377	if (p_dspin_out.read.read())
5378	{
5379	if (r_cc_send_last_client.read() == 0) // dcache active request
5380	r_dcache_cc_send_req = false; // reset dcache request
5381	else // icache active request
5382	r_icache_cc_send_req = false; // reset icache request
5383
5384	// go back to idle state
5385	r_cc_send_fsm = CC_SEND_IDLE;
5386	}
5387	break;
5388	}
5389	///////////////////////////
5390	case CC_SEND_MULTI_ACK:
5391	{
5392	// wait for the flit to be consumed
5393	if(p_dspin_out.read.read())
5394	{
5395	if(r_cc_send_last_client.read() == 0) // dcache active request
5396	r_dcache_cc_send_req = false; // reset dcache request
5397	else // icache active request
5398	r_icache_cc_send_req = false; // reset icache request
5399	// go back to idle state
5400	r_cc_send_fsm = CC_SEND_IDLE;
5401	}
5402	break;
5403	}
5404	} // end switch CC_SEND FSM
5405
5406	///////////////////////////////////////////////////////////////////////////////
5407	// C_RECEIVE FSM
5408	// This FSM receive all coherence packets on a DSPIN40 port.
5409	// There is 7 packet types:
5410	// - CC_DATA_INVAL : DCACHE invalidate request
5411	// - CC_DATA_UPDT : DCACHE update request (multi-words)
5412	// - CC_INST_INVAL : ICACHE invalidate request
5413	// - CC_INST_UPDT : ICACHE update request (multi-words)
5414	// - CC_BROADCAST : Broadcast invalidate request (both DCACHE & ICACHE)
5415	// - CC_DATA_CLACK : DCACHE cleanup acknowledge
5416	// - CC_INST_CLACK : ICACHE cleanup acknowledge
5417	//////////////////////////////////////////////////////////////////////////////
5418	switch( r_cc_receive_fsm.read() )
5419	{
5420	/////////////////////
5421	case CC_RECEIVE_IDLE:
5422	{
5423	// a coherence request has arrived
5424	if (p_dspin_in.write.read())
5425	{
5426	// initialize dspin received data
5427	uint64_t receive_data = p_dspin_in.data.read();
5428	// initialize coherence packet type
5429	uint64_t receive_type = DspinDhccpParam::dspin_get(receive_data,
5430	DspinDhccpParam::FROM_MC_TYPE);
5431	// initialize data/ins flip_flop (0 data / 1 ins)
5432	r_cc_receive_data_ins = (bool)(receive_type & 0x1);
5433	// test for a broadcast
5434	if (DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::FROM_MC_BC))
5435	{
5436	r_cc_receive_fsm = CC_RECEIVE_BRDCAST_HEADER;
5437	}
5438	// test for a CLACK
5439	else if ((receive_type == DspinDhccpParam::TYPE_CLEANUP_ACK_DATA) or
5440	(receive_type == DspinDhccpParam::TYPE_CLEANUP_ACK_INST))
5441	{
5442	r_cc_receive_fsm = CC_RECEIVE_CLACK;
5443	}
5444	// test for a multi updt
5445	else if ((receive_type == DspinDhccpParam::TYPE_MULTI_UPDT_DATA) or
5446	(receive_type == DspinDhccpParam::TYPE_MULTI_UPDT_INST))
5447	{
5448	r_cc_receive_fsm = CC_RECEIVE_UPDT_HEADER;
5449	}
5450	// test for a multi inval
5451	else
5452	{
5453	r_cc_receive_fsm = CC_RECEIVE_INVAL_HEADER;
5454	}
5455	}
5456	break;
5457	}
5458	//////////////////////
5459	case CC_RECEIVE_CLACK:
5460	{
5461	// initialize dspin received data
5462	uint64_t receive_data = p_dspin_in.data.read();
5463
5464	// for data CLACK, wait for dcache to take the request
5465	if ((r_cc_receive_data_ins.read() == 0) and
5466	not (r_cc_receive_dcache_req.read()))
5467	{
5468	// request dcache to handle the CLACK
5469	r_cc_receive_dcache_req = true;
5470	r_cc_receive_dcache_set = DspinDhccpParam::dspin_get(receive_data,
5471	DspinDhccpParam::CLEANUP_ACK_SET) &
5472	((1ULL<<(uint32_log2(m_dcache_sets)))-1);
5473	r_cc_receive_dcache_way = DspinDhccpParam::dspin_get(receive_data,
5474	DspinDhccpParam::CLEANUP_ACK_WAY) &
5475	((1ULL<<(uint32_log2(m_dcache_ways)))-1);
5476	r_cc_receive_dcache_type = CC_TYPE_CLACK;
5477	// get back to idle state
5478	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5479	break;
5480	}
5481	// for ins CLACK, wait for icache to take the request
5482	if ((r_cc_receive_data_ins.read() == 1) and
5483	not (r_cc_receive_icache_req.read()))
5484	{
5485	// request icache to handle the CLACK
5486	r_cc_receive_icache_req = true;
5487	r_cc_receive_icache_set = DspinDhccpParam::dspin_get(receive_data,
5488	DspinDhccpParam::CLEANUP_ACK_SET) &
5489	((1ULL<<(uint32_log2(m_icache_sets)))-1);
5490	r_cc_receive_icache_way = DspinDhccpParam::dspin_get(receive_data,
5491	DspinDhccpParam::CLEANUP_ACK_WAY) &
5492	((1ULL<<(uint32_log2(m_icache_ways)))-1);
5493	r_cc_receive_icache_type = CC_TYPE_CLACK;
5494	// get back to idle state
5495	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5496	break;
5497	}
5498	// keep waiting for the correct cache to accept the request
5499	break;
5500	}
5501	///////////////////////////////
5502	case CC_RECEIVE_BRDCAST_HEADER:
5503	{
5504	// no actual data in the HEADER, just skip to second flit
5505	r_cc_receive_fsm = CC_RECEIVE_BRDCAST_NLINE;
5506	break;
5507	}
5508	//////////////////////////////
5509	case CC_RECEIVE_BRDCAST_NLINE:
5510	{
5511	// initialize dspin received data
5512	uint64_t receive_data = p_dspin_in.data.read();
5513	// wait for both dcache and icache to take the request
5514	// TODO maybe we need to wait for both only to leave the state, but
5515	// not to actually post a request to an available cache => need a
5516	// flip_flop to check that ?
5517	if (not (r_cc_receive_icache_req.read()) and
5518	not (r_cc_receive_dcache_req.read()) and
5519	(p_dspin_in.write.read()))
5520	{
5521	// request dcache to handle the BROADCAST
5522	r_cc_receive_dcache_req = true;
5523	r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,
5524	DspinDhccpParam::BROADCAST_NLINE);
5525	r_cc_receive_dcache_type = CC_TYPE_BRDCAST;
5526	// request icache to handle the BROADCAST
5527	r_cc_receive_icache_req = true;
5528	r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,
5529	DspinDhccpParam::BROADCAST_NLINE);
5530	r_cc_receive_icache_type = CC_TYPE_BRDCAST;
5531	// get back to idle state
5532	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5533	break;
5534	}
5535	// keep waiting for the caches to accept the request
5536	break;
5537	}
5538	/////////////////////////////
5539	case CC_RECEIVE_INVAL_HEADER:
5540	{
5541	// sample updt tab index in the HEADER, then skip to second flit
5542	uint64_t receive_data = p_dspin_in.data.read();
5543	// for data INVAL, wait for dcache to take the request
5544	if ((r_cc_receive_data_ins.read() == 0) and
5545	not (r_cc_receive_dcache_req.read()))
5546	{
5547	r_cc_receive_dcache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,
5548	DspinDhccpParam::MULTI_INVAL_UPDT_INDEX);
5549	r_cc_receive_fsm = CC_RECEIVE_INVAL_NLINE;
5550	break;
5551	}
5552	// for ins INVAL, wait for icache to take the request
5553	if ((r_cc_receive_data_ins.read() == 1) and
5554	not (r_cc_receive_icache_req.read()))
5555	{
5556	r_cc_receive_icache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,
5557	DspinDhccpParam::MULTI_INVAL_UPDT_INDEX);
5558	r_cc_receive_fsm = CC_RECEIVE_INVAL_NLINE;
5559	break;
5560	}
5561	// keep waiting for the correct cache to accept the request
5562	break;
5563	}
5564	////////////////////////////
5565	case CC_RECEIVE_INVAL_NLINE:
5566	{
5567	// sample nline in the second flit
5568	uint64_t receive_data = p_dspin_in.data.read();
5569	// for data INVAL, wait for dcache to take the request
5570	if ( (r_cc_receive_data_ins.read() == 0) and
5571	not (r_cc_receive_dcache_req.read()) and
5572	(p_dspin_in.write.read()) )
5573	{
5574	// request dcache to handle the INVAL
5575	r_cc_receive_dcache_req = true;
5576	r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_NLINE);
5577	r_cc_receive_dcache_type = CC_TYPE_INVAL;
5578	// get back to idle state
5579	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5580	break;
5581	}
5582	// for ins INVAL, wait for icache to take the request
5583	if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()) and (p_dspin_in.write.read()))
5584	{
5585	// request icache to handle the INVAL
5586	r_cc_receive_icache_req = true;
5587	r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_NLINE);
5588	r_cc_receive_icache_type = CC_TYPE_INVAL;
5589	// get back to idle state
5590	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5591	break;
5592	}
5593	// we should never get there
5594	assert ( false && "ERROR in CC_VCACHE : CC_RECEIVE_INVAL_NLINE\n");
5595	}
5596	////////////////////////////
5597	case CC_RECEIVE_UPDT_HEADER:
5598	{
5599	// sample updt tab index in the HEADER, than skip to second flit
5600	uint64_t receive_data = p_dspin_in.data.read();
5601	// for data INVAL, wait for dcache to take the request and fifo to
5602	// be empty
5603	if ((r_cc_receive_data_ins.read() == 0) and not r_cc_receive_dcache_req.read() and r_cc_receive_updt_fifo_be.empty())
5604	{
5605	r_cc_receive_dcache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_UPDT_INDEX);
5606	r_cc_receive_fsm = CC_RECEIVE_UPDT_NLINE;
5607	break;
5608	}
5609	// for ins INVAL, wait for icache to take the request and fifo to be
5610	// empty
5611	if ((r_cc_receive_data_ins.read() == 1) and not r_cc_receive_icache_req.read() and r_cc_receive_updt_fifo_be.empty())
5612	{
5613	r_cc_receive_icache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_UPDT_INDEX);
5614	r_cc_receive_fsm = CC_RECEIVE_UPDT_NLINE;
5615	break;
5616	}
5617	// keep waiting for the correct cache to accept the request
5618	break;
5619	}
5620	///////////////////////////
5621	case CC_RECEIVE_UPDT_NLINE:
5622	{
5623	// sample nline and word index in the second flit
5624	uint64_t receive_data = p_dspin_in.data.read();
5625	// for data INVAL, wait for dcache to take the request and fifo to
5626	// be empty
5627	if ( (r_cc_receive_data_ins.read() == 0) and
5628	not (r_cc_receive_dcache_req.read()) and
5629	r_cc_receive_updt_fifo_be.empty() and
5630	(p_dspin_in.write.read()) )
5631	{
5632	r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_NLINE);
5633	r_cc_receive_word_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_WORD_INDEX);
5634	r_cc_receive_dcache_type = CC_TYPE_UPDT;
5635	// get back to idle state
5636	r_cc_receive_fsm = CC_RECEIVE_UPDT_DATA;
5637	break;
5638	}
5639	// for ins INVAL, wait for icache to take the request and fifo to be
5640	// empty
5641	if ( (r_cc_receive_data_ins.read() == 1) and
5642	not (r_cc_receive_icache_req.read()) and
5643	r_cc_receive_updt_fifo_be.empty() and
5644	(p_dspin_in.write.read()))
5645	{
5646	r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_NLINE);
5647	r_cc_receive_word_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_WORD_INDEX);
5648	r_cc_receive_icache_type = CC_TYPE_UPDT;
5649	// get back to idle state
5650	r_cc_receive_fsm = CC_RECEIVE_UPDT_DATA;
5651	break;
5652	}
5653	// we should never get there
5654	assert ( false && "ERROR in CC_VCACHE : CC_RECEIVE_UPDT_NLINE \n");
5655	break;
5656	}
5657	//////////////////////////
5658	case CC_RECEIVE_UPDT_DATA:
5659	{
5660	if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()) and (p_dspin_in.write.read()))
5661	r_cc_receive_dcache_req = true;
5662	if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()) and (p_dspin_in.write.read()))
5663	r_cc_receive_icache_req = true;
5664
5665	// wait for the fifo
5666	if (r_cc_receive_updt_fifo_be.wok() and (p_dspin_in.write.read()))
5667	{
5668	uint64_t receive_data = p_dspin_in.data.read();
5669	bool receive_eop = p_dspin_in.eop.read();
5670	cc_receive_updt_fifo_be = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_BE);
5671	cc_receive_updt_fifo_data = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_DATA);
5672	cc_receive_updt_fifo_eop = receive_eop;
5673	cc_receive_updt_fifo_put = true;
5674	if ( receive_eop ) r_cc_receive_fsm = CC_RECEIVE_IDLE;
5675	}
5676	break;
5677	}
5678	} // end switch CC_RECEIVE FSM
5679
5680	///////////////// Response FIFOs update //////////////////////
5681	r_vci_rsp_fifo_icache.update(vci_rsp_fifo_icache_get,
5682	vci_rsp_fifo_icache_put,
5683	vci_rsp_fifo_icache_data);
5684
5685	r_vci_rsp_fifo_dcache.update(vci_rsp_fifo_dcache_get,
5686	vci_rsp_fifo_dcache_put,
5687	vci_rsp_fifo_dcache_data);
5688
5689	///////////////// updt FIFO update //////////////////////
5690	//TODO check this
5691	r_cc_receive_updt_fifo_be.update(cc_receive_updt_fifo_get,
5692	cc_receive_updt_fifo_put,
5693	cc_receive_updt_fifo_be);
5694	r_cc_receive_updt_fifo_data.update(cc_receive_updt_fifo_get,
5695	cc_receive_updt_fifo_put,
5696	cc_receive_updt_fifo_data);
5697	r_cc_receive_updt_fifo_eop.update(cc_receive_updt_fifo_get,
5698	cc_receive_updt_fifo_put,
5699	cc_receive_updt_fifo_eop);
5700
5701	} // end transition()
5702
5703	///////////////////////
5704	tmpl(void)::genMoore()
5705	///////////////////////
5706	{
5707
5708	// VCI initiator command on the direct network
5709	// it depends on the CMD FSM state
5710
5711	bool is_sc_or_cas = (r_vci_cmd_fsm.read() == CMD_DATA_CAS) or
5712	(r_vci_cmd_fsm.read() == CMD_DATA_SC );
5713
5714	p_vci.pktid = 0;
5715	p_vci.srcid = m_srcid;
5716	p_vci.cons = is_sc_or_cas;
5717	p_vci.contig = not is_sc_or_cas;
5718	p_vci.wrap = false;
5719	p_vci.clen = 0;
5720	p_vci.cfixed = false;
5721
5722	switch ( r_vci_cmd_fsm.read() ) {
5723
5724	case CMD_IDLE:
5725	p_vci.cmdval = false;
5726	p_vci.address = 0;
5727	p_vci.wdata = 0;
5728	p_vci.be = 0;
5729	p_vci.trdid = 0;
5730	p_vci.pktid = 0;
5731	p_vci.plen = 0;
5732	p_vci.cmd = vci_param::CMD_NOP;
5733	p_vci.eop = false;
5734	break;
5735
5736	case CMD_INS_MISS:
5737	p_vci.cmdval = true;
5738	p_vci.address = r_icache_vci_paddr.read() & m_icache_yzmask;
5739	p_vci.wdata = 0;
5740	p_vci.be = 0xF;
5741	p_vci.trdid = 0;
5742	p_vci.pktid = TYPE_READ_INS_MISS;
5743	p_vci.plen = m_icache_words<<2;
5744	p_vci.cmd = vci_param::CMD_READ;
5745	p_vci.eop = true;
5746	break;
5747
5748	case CMD_INS_UNC:
5749	p_vci.cmdval = true;
5750	p_vci.address = r_icache_vci_paddr.read() & ~0x3;
5751	p_vci.wdata = 0;
5752	p_vci.be = 0xF;
5753	p_vci.trdid = 0;
5754	p_vci.pktid = TYPE_READ_INS_UNC;
5755	p_vci.plen = 4;
5756	p_vci.cmd = vci_param::CMD_READ;
5757	p_vci.eop = true;
5758	break;
5759
5760	case CMD_DATA_MISS:
5761	p_vci.cmdval = true;
5762	p_vci.address = r_dcache_vci_paddr.read() & m_dcache_yzmask;
5763	p_vci.wdata = 0;
5764	p_vci.be = 0xF;
5765	p_vci.trdid = 0;
5766	p_vci.pktid = TYPE_READ_DATA_MISS;
5767	p_vci.plen = m_dcache_words << 2;
5768	p_vci.cmd = vci_param::CMD_READ;
5769	p_vci.eop = true;
5770	break;
5771
5772	case CMD_DATA_UNC:
5773	p_vci.cmdval = true;
5774	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
5775	p_vci.wdata = 0;
5776	p_vci.be = r_dcache_vci_unc_be.read();
5777	p_vci.trdid = 0;
5778	p_vci.pktid = TYPE_READ_DATA_UNC;
5779	p_vci.plen = 4;
5780	p_vci.cmd = vci_param::CMD_READ;
5781	p_vci.eop = true;
5782	break;
5783
5784	case CMD_DATA_WRITE:
5785	p_vci.cmdval = true;
5786	p_vci.address = r_wbuf.getAddress(r_vci_cmd_cpt.read()) & ~0x3;
5787	p_vci.wdata = r_wbuf.getData(r_vci_cmd_cpt.read());
5788	p_vci.be = r_wbuf.getBe(r_vci_cmd_cpt.read());
5789	p_vci.trdid = r_wbuf.getIndex();
5790	p_vci.pktid = TYPE_WRITE;
5791	p_vci.plen = (r_vci_cmd_max.read() - r_vci_cmd_min.read() + 1) << 2;
5792	p_vci.cmd = vci_param::CMD_WRITE;
5793	p_vci.eop = (r_vci_cmd_cpt.read() == r_vci_cmd_max.read());
5794	break;
5795
5796	case CMD_DATA_LL:
5797	p_vci.cmdval = true;
5798	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
5799	p_vci.wdata = 0;
5800	p_vci.be = 0xF;
5801	p_vci.trdid = 0;
5802	p_vci.pktid = TYPE_LL;
5803	p_vci.plen = 8;
5804	p_vci.cmd = vci_param::CMD_LOCKED_READ;
5805	p_vci.eop = true;
5806	break;
5807
5808	case CMD_DATA_SC:
5809	p_vci.cmdval = true;
5810	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
5811	if ( r_vci_cmd_cpt.read() == 0 ) p_vci.wdata = r_dcache_llsc_key.read();
5812	else p_vci.wdata = r_dcache_vci_sc_data.read();
5813	p_vci.be = 0xF;
5814	p_vci.trdid = 0;
5815	p_vci.pktid = TYPE_SC;
5816	p_vci.plen = 8;
5817	p_vci.cmd = vci_param::CMD_NOP;
5818	p_vci.eop = (r_vci_cmd_cpt.read() == 1);
5819	break;
5820
5821	case CMD_DATA_CAS:
5822	p_vci.cmdval = true;
5823	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
5824	if ( r_vci_cmd_cpt.read() == 0 ) p_vci.wdata = r_dcache_vci_cas_old.read();
5825	else p_vci.wdata = r_dcache_vci_cas_new.read();
5826	p_vci.be = 0xF;
5827	p_vci.trdid = 0;
5828	p_vci.pktid = TYPE_CAS;
5829	p_vci.plen = 8;
5830	p_vci.cmd = vci_param::CMD_NOP;
5831	p_vci.eop = (r_vci_cmd_cpt.read() == 1);
5832	break;
5833	} // end switch r_vci_cmd_fsm
5834
5835	// VCI initiator response on the direct network
5836	// it depends on the VCI_RSP FSM
5837
5838	switch (r_vci_rsp_fsm.read() )
5839	{
5840	case RSP_DATA_WRITE : p_vci.rspack = true; break;
5841	case RSP_INS_MISS : p_vci.rspack = r_vci_rsp_fifo_icache.wok(); break;
5842	case RSP_INS_UNC : p_vci.rspack = r_vci_rsp_fifo_icache.wok(); break;
5843	case RSP_DATA_MISS : p_vci.rspack = r_vci_rsp_fifo_dcache.wok(); break;
5844	case RSP_DATA_UNC : p_vci.rspack = r_vci_rsp_fifo_dcache.wok(); break;
5845	case RSP_DATA_LL : p_vci.rspack = r_vci_rsp_fifo_dcache.wok(); break;
5846	case RSP_IDLE : p_vci.rspack = false; break;
5847	} // end switch r_vci_rsp_fsm
5848
5849
5850	// Send coherence packets on DSPIN P2M
5851	// it depends on the CC_SEND FSM
5852
5853	uint64_t dspin_send_data = 0;
5854	switch ( r_cc_send_fsm.read() )
5855	{
5856	//////////////////
5857	case CC_SEND_IDLE:
5858	{
5859	p_dspin_out.write = false;
5860	break;
5861	}
5862	///////////////////////
5863	case CC_SEND_CLEANUP_1:
5864	{
5865	// initialize dspin send data
5866	// DspinDhccpParam::dspin_set(dspin_send_data,
5867	// 0,
5868	// DspinDhccpParam::FROM_L1_EOP);
5869	DspinDhccpParam::dspin_set(dspin_send_data,
5870	m_cc_global_id,
5871	DspinDhccpParam::CLEANUP_SRCID);
5872	DspinDhccpParam::dspin_set(dspin_send_data,
5873	0,
5874	DspinDhccpParam::FROM_L1_BC);
5875
5876	if(r_cc_send_last_client.read() == 0) // dcache active request
5877	{
5878	uint64_t dest = (uint64_t) r_dcache_cc_send_nline.read()
5879	>> (m_nline_width - m_x_width - m_y_width)
5880	<< (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
5881
5882	DspinDhccpParam::dspin_set(dspin_send_data,
5883	dest,
5884	DspinDhccpParam::CLEANUP_DEST);
5885
5886	DspinDhccpParam::dspin_set(dspin_send_data,
5887	(r_dcache_cc_send_nline.read() & 0x300000000ULL)>>32,
5888	DspinDhccpParam::CLEANUP_NLINE_MSB);
5889
5890	DspinDhccpParam::dspin_set(dspin_send_data,
5891	r_dcache_cc_send_way.read(),
5892	DspinDhccpParam::CLEANUP_WAY_INDEX);
5893
5894	DspinDhccpParam::dspin_set(dspin_send_data,
5895	DspinDhccpParam::TYPE_CLEANUP_DATA,
5896	DspinDhccpParam::FROM_L1_TYPE);
5897	}
5898	else // icache active request
5899	{
5900	uint64_t dest = (uint64_t) r_icache_cc_send_nline.read()
5901	>> (m_nline_width - m_x_width - m_y_width)
5902	<< (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
5903
5904	DspinDhccpParam::dspin_set(dspin_send_data,
5905	dest,
5906	DspinDhccpParam::CLEANUP_DEST);
5907
5908	DspinDhccpParam::dspin_set(dspin_send_data,
5909	(r_icache_cc_send_nline.read() & 0x300000000ULL)>>32,
5910	DspinDhccpParam::CLEANUP_NLINE_MSB);
5911
5912	DspinDhccpParam::dspin_set(dspin_send_data,
5913	r_icache_cc_send_way.read(),
5914	DspinDhccpParam::CLEANUP_WAY_INDEX);
5915
5916	DspinDhccpParam::dspin_set(dspin_send_data,
5917	DspinDhccpParam::TYPE_CLEANUP_INST,
5918	DspinDhccpParam::FROM_L1_TYPE);
5919	}
5920	// send flit
5921	p_dspin_out.data = dspin_send_data;
5922	p_dspin_out.write = true;
5923	p_dspin_out.eop = false;
5924	break;
5925	}
5926	///////////////////////
5927	case CC_SEND_CLEANUP_2:
5928	{
5929	// initialize dspin send data
5930	// DspinDhccpParam::dspin_set(dspin_send_data,
5931	// 1,
5932	// DspinDhccpParam::FROM_L1_EOP);
5933
5934	if(r_cc_send_last_client.read() == 0) // dcache active request
5935	{
5936	DspinDhccpParam::dspin_set(dspin_send_data,
5937	r_dcache_cc_send_nline.read() & 0xFFFFFFFFULL,
5938	DspinDhccpParam::CLEANUP_NLINE_LSB);
5939	}
5940	else // icache active request
5941	{
5942	DspinDhccpParam::dspin_set(dspin_send_data,
5943	r_icache_cc_send_nline.read() & 0xFFFFFFFFULL,
5944	DspinDhccpParam::CLEANUP_NLINE_LSB);
5945	}
5946	// send flit
5947	p_dspin_out.data = dspin_send_data;
5948	p_dspin_out.write = true;
5949	p_dspin_out.eop = true;
5950	break;
5951	}
5952	///////////////////////
5953	case CC_SEND_MULTI_ACK:
5954	{
5955	// initialize dspin send data
5956	// DspinDhccpParam::dspin_set(dspin_send_data,
5957	// 1,
5958	// DspinDhccpParam::FROM_L1_EOP);
5959	DspinDhccpParam::dspin_set(dspin_send_data,
5960	0,
5961	DspinDhccpParam::FROM_L1_BC);
5962	DspinDhccpParam::dspin_set(dspin_send_data,
5963	DspinDhccpParam::TYPE_MULTI_ACK,
5964	DspinDhccpParam::FROM_L1_TYPE);
5965
5966	if(r_cc_send_last_client.read() == 0) // dcache active request
5967	{
5968	uint64_t dest = (uint64_t) r_dcache_cc_send_nline.read()
5969	>> (m_nline_width - m_x_width - m_y_width)
5970	<< (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
5971
5972	DspinDhccpParam::dspin_set(dspin_send_data,
5973	dest,
5974	DspinDhccpParam::MULTI_ACK_DEST);
5975
5976	DspinDhccpParam::dspin_set(dspin_send_data,
5977	r_dcache_cc_send_updt_tab_idx.read(),
5978	DspinDhccpParam::MULTI_ACK_UPDT_INDEX);
5979	}
5980	else // icache active request
5981	{
5982	uint64_t dest = (uint64_t) r_icache_cc_send_nline.read()
5983	>> (m_nline_width - m_x_width - m_y_width)
5984	<< (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
5985
5986
5987	DspinDhccpParam::dspin_set(dspin_send_data,
5988	dest,
5989	DspinDhccpParam::MULTI_ACK_DEST);
5990
5991	DspinDhccpParam::dspin_set(dspin_send_data,
5992	r_icache_cc_send_updt_tab_idx.read(),
5993	DspinDhccpParam::MULTI_ACK_UPDT_INDEX);
5994	}
5995	// send flit
5996	p_dspin_out.data = dspin_send_data;
5997	p_dspin_out.write = true;
5998	p_dspin_out.eop = true;
5999
6000	break;
6001	}
6002	} // end switch CC_SEND FSM
6003
6004	// Receive coherence packets
6005	// It depends on the CC_RECEIVE FSM
6006
6007	switch( r_cc_receive_fsm.read() )
6008	{
6009	/////////////////////
6010	case CC_RECEIVE_IDLE:
6011	{
6012	p_dspin_in.read = false;
6013	break;
6014	}
6015	//////////////////////
6016	case CC_RECEIVE_CLACK:
6017	{
6018	if (((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read())) or
6019	((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read())))
6020	p_dspin_in.read = true;
6021	else
6022	p_dspin_in.read = false;
6023	break;
6024	}
6025	///////////////////////////////
6026	case CC_RECEIVE_BRDCAST_HEADER:
6027	{
6028	p_dspin_in.read = true;
6029	break;
6030	}
6031	//////////////////////////////
6032	case CC_RECEIVE_BRDCAST_NLINE:
6033	{
6034	// TODO maybe we need to wait for both only to leave the state, but
6035	// not to actually post a request to an available cache => need a
6036	// flip_flop to check that ?
6037	if (not (r_cc_receive_icache_req.read()) and not (r_cc_receive_dcache_req.read()))
6038	p_dspin_in.read = true;
6039	else
6040	p_dspin_in.read = false;
6041	break;
6042	}
6043	/////////////////////////////
6044	case CC_RECEIVE_INVAL_HEADER:
6045	{
6046	if (((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read())) or
6047	((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read())))
6048	p_dspin_in.read = true;
6049	else
6050	p_dspin_in.read = false;
6051	break;
6052	}
6053	////////////////////////////
6054	case CC_RECEIVE_INVAL_NLINE:
6055	{
6056	p_dspin_in.read = true;
6057	break;
6058	}
6059	////////////////////////////
6060	case CC_RECEIVE_UPDT_HEADER:
6061	{
6062	if (((r_cc_receive_data_ins.read() == 0) and
6063	not r_cc_receive_dcache_req.read() and
6064	r_cc_receive_updt_fifo_be.empty())
6065	or
6066	((r_cc_receive_data_ins.read() == 1) and
6067	not r_cc_receive_icache_req.read()) and
6068	r_cc_receive_updt_fifo_be.empty())
6069	p_dspin_in.read = true;
6070	else
6071	p_dspin_in.read = false;
6072	break;
6073	}
6074	///////////////////////////
6075	case CC_RECEIVE_UPDT_NLINE:
6076	{
6077	if (((r_cc_receive_data_ins.read() == 0) and
6078	not (r_cc_receive_dcache_req.read()) and
6079	r_cc_receive_updt_fifo_be.empty())
6080	or
6081	((r_cc_receive_data_ins.read() == 1) and
6082	not (r_cc_receive_icache_req.read()) and
6083	r_cc_receive_updt_fifo_be.empty()))
6084	p_dspin_in.read = true;
6085	else
6086	p_dspin_in.read = false;
6087	break;
6088	}
6089	//////////////////////////
6090	case CC_RECEIVE_UPDT_DATA:
6091	{
6092	if (r_cc_receive_updt_fifo_be.wok())
6093	p_dspin_in.read = true;
6094	else
6095	p_dspin_in.read = false;
6096	break;
6097	}
6098	} // end switch CC_RECEIVE FSM
6099
6100	} // end genMoore
6101
6102	}}
6103
6104	// Local Variables:
6105	// tab-width: 4
6106	// c-basic-offset: 4
6107	// c-file-offsets:((innamespace . 0)(inline-open . 0))
6108	// indent-tabs-mode: nil
6109	// End:
6110
6111	// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4

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