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source: trunk/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp @ 711

Last change on this file since 711 was 711, checked in by alain, 10 years ago
Improving debug messages.
File size: 239.4 KB

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1	/* -- c++ --
2	* File : vci_cc_vcache_wrapper.cpp
3	* Copyright (c) UPMC, Lip6, SoC
4	* Authors : Alain GREINER, Yang GAO
5	*
6	* SOCLIB_LGPL_HEADER_BEGIN
7	*
8	* This file is part of SoCLib, GNU LGPLv2.1.
9	*
10	* SoCLib is free software; you can redistribute it and/or modify it
11	* under the terms of the GNU Lesser General Public License as published
12	* by the Free Software Foundation; version 2.1 of the License.
13	*
14	* SoCLib is distributed in the hope that it will be useful, but
15	* WITHOUT ANY WARRANTY; without even the implied warranty of
16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17	* Lesser General Public License for more details.
18	*
19	* You should have received a copy of the GNU Lesser General Public
20	* License along with SoCLib; if not, write to the Free Software
21	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
22	* 02110-1301 USA
23	*
24	* SOCLIB_LGPL_HEADER_END
25	*
26	* Maintainers: cesar.fuguet-tortolero@lip6.fr
27	* alexandre.joannou@lip6.fr
28	*/
29
30	#include <cassert>
31	#include "arithmetics.h"
32	#include "../include/vci_cc_vcache_wrapper.h"
33
34	#define DEBUG_DCACHE 1
35	#define DEBUG_ICACHE 1
36	#define DEBUG_CMD 0
37
38	namespace soclib {
39	namespace caba {
40
41	namespace {
42	const char *icache_fsm_state_str[] = {
43	"ICACHE_IDLE",
44
45	"ICACHE_XTN_TLB_FLUSH",
46	"ICACHE_XTN_CACHE_FLUSH",
47	"ICACHE_XTN_CACHE_FLUSH_GO",
48	"ICACHE_XTN_TLB_INVAL",
49	"ICACHE_XTN_CACHE_INVAL_VA",
50	"ICACHE_XTN_CACHE_INVAL_PA",
51	"ICACHE_XTN_CACHE_INVAL_GO",
52
53	"ICACHE_TLB_WAIT",
54
55	"ICACHE_MISS_SELECT",
56	"ICACHE_MISS_CLEAN",
57	"ICACHE_MISS_WAIT",
58	"ICACHE_MISS_DATA_UPDT",
59	"ICACHE_MISS_DIR_UPDT",
60
61	"ICACHE_UNC_WAIT",
62
63	"ICACHE_CC_CHECK",
64	"ICACHE_CC_UPDT",
65	"ICACHE_CC_INVAL",
66	};
67
68	const char *dcache_fsm_state_str[] = {
69	"DCACHE_IDLE",
70
71	"DCACHE_TLB_MISS",
72	"DCACHE_TLB_PTE1_GET",
73	"DCACHE_TLB_PTE1_SELECT",
74	"DCACHE_TLB_PTE1_UPDT",
75	"DCACHE_TLB_PTE2_GET",
76	"DCACHE_TLB_PTE2_SELECT",
77	"DCACHE_TLB_PTE2_UPDT",
78	"DCACHE_TLB_LR_UPDT",
79	"DCACHE_TLB_LR_WAIT",
80	"DCACHE_TLB_RETURN",
81
82	"DCACHE_XTN_SWITCH",
83	"DCACHE_XTN_SYNC",
84	"DCACHE_XTN_IC_INVAL_VA",
85	"DCACHE_XTN_IC_FLUSH",
86	"DCACHE_XTN_IC_INVAL_PA",
87	"DCACHE_XTN_IT_INVAL",
88	"DCACHE_XTN_DC_FLUSH",
89	"DCACHE_XTN_DC_FLUSH_GO",
90	"DCACHE_XTN_DC_INVAL_VA",
91	"DCACHE_XTN_DC_INVAL_PA",
92	"DCACHE_XTN_DC_INVAL_END",
93	"DCACHE_XTN_DC_INVAL_GO",
94	"DCACHE_XTN_DT_INVAL",
95
96	"DCACHE_DIRTY_GET_PTE",
97	"DCACHE_DIRTY_WAIT",
98
99	"DCACHE_MISS_SELECT",
100	"DCACHE_MISS_CLEAN",
101	"DCACHE_MISS_WAIT",
102	"DCACHE_MISS_DATA_UPDT",
103	"DCACHE_MISS_DIR_UPDT",
104
105	"DCACHE_UNC_WAIT",
106	"DCACHE_LL_WAIT",
107	"DCACHE_SC_WAIT",
108
109	"DCACHE_CC_CHECK",
110	"DCACHE_CC_UPDT",
111	"DCACHE_CC_INVAL",
112
113	"DCACHE_INVAL_TLB_SCAN",
114	};
115
116	const char *cmd_fsm_state_str[] = {
117	"CMD_IDLE",
118	"CMD_INS_MISS",
119	"CMD_INS_UNC",
120	"CMD_DATA_MISS",
121	"CMD_DATA_UNC_READ",
122	"CMD_DATA_UNC_WRITE",
123	"CMD_DATA_WRITE",
124	"CMD_DATA_LL",
125	"CMD_DATA_SC",
126	"CMD_DATA_CAS",
127	};
128
129	const char *vci_pktid_type_str[] = {
130	"TYPE_DATA_UNC",
131	"TYPE_READ_DATA_MISS",
132	"TYPE_READ_INS_UNC",
133	"TYPE_READ_INS_MISS",
134	"TYPE_WRITE",
135	"TYPE_CAS",
136	"TYPE_LL",
137	"TYPE_SC",
138	};
139
140	const char *vci_cmd_type_str[] = {
141	"NOP or STORE_COND",
142	"READ",
143	"WRITE",
144	"LOCKED_READ"
145	};
146
147	const char *rsp_fsm_state_str[] = {
148	"RSP_IDLE",
149	"RSP_INS_MISS",
150	"RSP_INS_UNC",
151	"RSP_DATA_MISS",
152	"RSP_DATA_UNC",
153	"RSP_DATA_LL",
154	"RSP_DATA_WRITE",
155	};
156
157	const char *cc_receive_fsm_state_str[] = {
158	"CC_RECEIVE_IDLE",
159	"CC_RECEIVE_BRDCAST_HEADER",
160	"CC_RECEIVE_BRDCAST_NLINE",
161	"CC_RECEIVE_INS_INVAL_HEADER",
162	"CC_RECEIVE_INS_INVAL_NLINE",
163	"CC_RECEIVE_INS_UPDT_HEADER",
164	"CC_RECEIVE_INS_UPDT_NLINE",
165	"CC_RECEIVE_INS_UPDT_DATA",
166	"CC_RECEIVE_DATA_INVAL_HEADER",
167	"CC_RECEIVE_DATA_INVAL_NLINE",
168	"CC_RECEIVE_DATA_UPDT_HEADER",
169	"CC_RECEIVE_DATA_UPDT_NLINE",
170	"CC_RECEIVE_DATA_UPDT_DATA",
171	};
172
173	const char *cc_send_fsm_state_str[] = {
174	"CC_SEND_IDLE",
175	"CC_SEND_CLEANUP_1",
176	"CC_SEND_CLEANUP_2",
177	"CC_SEND_MULTI_ACK",
178	};
179	}
180
181	#define tmpl(...) \
182	template<typename vci_param, \
183	size_t dspin_in_width, \
184	size_t dspin_out_width, \
185	typename iss_t> __VA_ARGS__ \
186	VciCcVCacheWrapper<vci_param, dspin_in_width, dspin_out_width, iss_t>
187
188	using namespace soclib::common;
189
190	/////////////////////////////////
191	tmpl(/**/)::VciCcVCacheWrapper(
192	sc_module_name name,
193	const int proc_id,
194	const MappingTable &mtd,
195	const IntTab &srcid,
196	const size_t cc_global_id,
197	const size_t itlb_ways,
198	const size_t itlb_sets,
199	const size_t dtlb_ways,
200	const size_t dtlb_sets,
201	const size_t icache_ways,
202	const size_t icache_sets,
203	const size_t icache_words,
204	const size_t dcache_ways,
205	const size_t dcache_sets,
206	const size_t dcache_words,
207	const size_t wbuf_nlines,
208	const size_t wbuf_nwords,
209	const size_t x_width,
210	const size_t y_width,
211	const uint32_t max_frozen_cycles,
212	const uint32_t debug_start_cycle,
213	const bool debug_ok )
214	: soclib::caba::BaseModule(name),
215
216	p_clk("p_clk"),
217	p_resetn("p_resetn"),
218	p_vci("p_vci"),
219	p_dspin_m2p("p_dspin_m2p"),
220	p_dspin_p2m("p_dspin_p2m"),
221	p_dspin_clack("p_dspin_clack"),
222
223	m_cacheability_table( mtd.getCacheabilityTable() ),
224	m_srcid( mtd.indexForId(srcid) ),
225	m_cc_global_id( cc_global_id ),
226	m_nline_width( vci_param::N - (uint32_log2(dcache_words)) - 2 ),
227	m_itlb_ways( itlb_ways ),
228	m_itlb_sets( itlb_sets ),
229	m_dtlb_ways( dtlb_ways ),
230	m_dtlb_sets( dtlb_sets ),
231	m_icache_ways( icache_ways ),
232	m_icache_sets( icache_sets ),
233	m_icache_yzmask( (~0)<<(uint32_log2(icache_words) + 2) ),
234	m_icache_words( icache_words ),
235	m_dcache_ways( dcache_ways ),
236	m_dcache_sets( dcache_sets ),
237	m_dcache_yzmask( (~0)<<(uint32_log2(dcache_words) + 2) ),
238	m_dcache_words( dcache_words ),
239	m_x_width( x_width ),
240	m_y_width( y_width ),
241	m_proc_id( proc_id ),
242	m_max_frozen_cycles( max_frozen_cycles ),
243	m_paddr_nbits( vci_param::N ),
244	m_debug_start_cycle( debug_start_cycle ),
245	m_debug_ok( debug_ok ),
246
247	r_mmu_ptpr("r_mmu_ptpr"),
248	r_mmu_mode("r_mmu_mode"),
249	r_mmu_word_lo("r_mmu_word_lo"),
250	r_mmu_word_hi("r_mmu_word_hi"),
251	r_mmu_ibvar("r_mmu_ibvar"),
252	r_mmu_dbvar("r_mmu_dbvar"),
253	r_mmu_ietr("r_mmu_ietr"),
254	r_mmu_detr("r_mmu_detr"),
255
256	r_icache_fsm("r_icache_fsm"),
257	r_icache_fsm_save("r_icache_fsm_save"),
258	r_icache_vci_paddr("r_icache_vci_paddr"),
259	r_icache_vaddr_save("r_icache_vaddr_save"),
260
261	r_icache_miss_way("r_icache_miss_way"),
262	r_icache_miss_set("r_icache_miss_set"),
263	r_icache_miss_word("r_icache_miss_word"),
264	r_icache_miss_inval("r_icache_miss_inval"),
265	r_icache_miss_clack("r_icache_miss_clack"),
266
267	r_icache_cc_way("r_icache_cc_way"),
268	r_icache_cc_set("r_icache_cc_set"),
269	r_icache_cc_word("r_icache_cc_word"),
270	r_icache_cc_need_write("r_icache_cc_need_write"),
271
272	r_icache_flush_count("r_icache_flush_count"),
273
274	r_icache_miss_req("r_icache_miss_req"),
275	r_icache_unc_req("r_icache_unc_req"),
276
277	r_icache_tlb_miss_req("r_icache_tlb_read_req"),
278	r_icache_tlb_rsp_error("r_icache_tlb_rsp_error"),
279
280	r_icache_cleanup_victim_req("r_icache_cleanup_victim_req"),
281	r_icache_cleanup_victim_nline("r_icache_cleanup_victim_nline"),
282
283	r_icache_cc_send_req("r_icache_cc_send_req"),
284	r_icache_cc_send_type("r_icache_cc_send_type"),
285	r_icache_cc_send_nline("r_icache_cc_send_nline"),
286	r_icache_cc_send_way("r_icache_cc_send_way"),
287	r_icache_cc_send_updt_tab_idx("r_icache_cc_send_updt_tab_idx"),
288
289	r_dcache_fsm("r_dcache_fsm"),
290	r_dcache_fsm_cc_save("r_dcache_fsm_cc_save"),
291	r_dcache_fsm_scan_save("r_dcache_fsm_scan_save"),
292
293	r_dcache_wbuf_req("r_dcache_wbuf_req"),
294	r_dcache_updt_req("r_dcache_updt_req"),
295	r_dcache_save_vaddr("r_dcache_save_vaddr"),
296	r_dcache_save_wdata("r_dcache_save_wdata"),
297	r_dcache_save_be("r_dcache_save_be"),
298	r_dcache_save_paddr("r_dcache_save_paddr"),
299	r_dcache_save_cache_way("r_dcache_save_cache_way"),
300	r_dcache_save_cache_set("r_dcache_save_cache_set"),
301	r_dcache_save_cache_word("r_dcache_save_cache_word"),
302
303	r_dcache_dirty_paddr("r_dcache_dirty_paddr"),
304	r_dcache_dirty_way("r_dcache_dirty_way"),
305	r_dcache_dirty_set("r_dcache_dirty_set"),
306
307	r_dcache_vci_paddr("r_dcache_vci_paddr"),
308	r_dcache_vci_wdata("r_dcache_vci_wdata"),
309	r_dcache_vci_miss_req("r_dcache_vci_miss_req"),
310	r_dcache_vci_unc_req("r_dcache_vci_unc_req"),
311	r_dcache_vci_unc_be("r_dcache_vci_unc_be"),
312	r_dcache_vci_unc_write("r_dcache_vci_unc_write"),
313	r_dcache_vci_cas_req("r_dcache_vci_cas_req"),
314	r_dcache_vci_cas_old("r_dcache_vci_cas_old"),
315	r_dcache_vci_cas_new("r_dcache_vci_cas_new"),
316	r_dcache_vci_ll_req("r_dcache_vci_ll_req"),
317	r_dcache_vci_sc_req("r_dcache_vci_sc_req"),
318	r_dcache_vci_sc_data("r_dcache_vci_sc_data"),
319
320	r_dcache_xtn_way("r_dcache_xtn_way"),
321	r_dcache_xtn_set("r_dcache_xtn_set"),
322
323	r_dcache_miss_type("r_dcache_miss_type"),
324	r_dcache_miss_word("r_dcache_miss_word"),
325	r_dcache_miss_way("r_dcache_miss_way"),
326	r_dcache_miss_set("r_dcache_miss_set"),
327	r_dcache_miss_inval("r_dcache_miss_inval"),
328
329	r_dcache_cc_way("r_dcache_cc_way"),
330	r_dcache_cc_set("r_dcache_cc_set"),
331	r_dcache_cc_word("r_dcache_cc_word"),
332	r_dcache_cc_need_write("r_dcache_cc_need_write"),
333
334	r_dcache_flush_count("r_dcache_flush_count"),
335
336	r_dcache_ll_rsp_count("r_dcache_ll_rsp_count"),
337
338	r_dcache_tlb_vaddr("r_dcache_tlb_vaddr"),
339	r_dcache_tlb_ins("r_dcache_tlb_ins"),
340	r_dcache_tlb_pte_flags("r_dcache_tlb_pte_flags"),
341	r_dcache_tlb_pte_ppn("r_dcache_tlb_pte_ppn"),
342	r_dcache_tlb_cache_way("r_dcache_tlb_cache_way"),
343	r_dcache_tlb_cache_set("r_dcache_tlb_cache_set"),
344	r_dcache_tlb_cache_word("r_dcache_tlb_cache_word"),
345	r_dcache_tlb_way("r_dcache_tlb_way"),
346	r_dcache_tlb_set("r_dcache_tlb_set"),
347
348	r_dcache_tlb_inval_line("r_dcache_tlb_inval_line"),
349	r_dcache_tlb_inval_set("r_dcache_tlb_inval_set"),
350
351	r_dcache_xtn_req("r_dcache_xtn_req"),
352	r_dcache_xtn_opcode("r_dcache_xtn_opcode"),
353
354	r_dcache_cleanup_victim_req("r_dcache_cleanup_victim_req"),
355	r_dcache_cleanup_victim_nline("r_dcache_cleanup_victim_nline"),
356
357	r_dcache_cc_send_req("r_dcache_cc_send_req"),
358	r_dcache_cc_send_type("r_dcache_cc_send_type"),
359	r_dcache_cc_send_nline("r_dcache_cc_send_nline"),
360	r_dcache_cc_send_way("r_dcache_cc_send_way"),
361	r_dcache_cc_send_updt_tab_idx("r_dcache_cc_send_updt_tab_idx"),
362
363	r_vci_cmd_fsm("r_vci_cmd_fsm"),
364	r_vci_cmd_min("r_vci_cmd_min"),
365	r_vci_cmd_max("r_vci_cmd_max"),
366	r_vci_cmd_cpt("r_vci_cmd_cpt"),
367	r_vci_cmd_imiss_prio("r_vci_cmd_imiss_prio"),
368
369	r_vci_rsp_fsm("r_vci_rsp_fsm"),
370	r_vci_rsp_cpt("r_vci_rsp_cpt"),
371	r_vci_rsp_ins_error("r_vci_rsp_ins_error"),
372	r_vci_rsp_data_error("r_vci_rsp_data_error"),
373	r_vci_rsp_fifo_icache("r_vci_rsp_fifo_icache", 2), // 2 words depth
374	r_vci_rsp_fifo_dcache("r_vci_rsp_fifo_dcache", 2), // 2 words depth
375
376	r_cc_send_fsm("r_cc_send_fsm"),
377	r_cc_send_last_client("r_cc_send_last_client"),
378
379	r_cc_receive_fsm("r_cc_receive_fsm"),
380	r_cc_receive_data_ins("r_cc_receive_data_ins"),
381	r_cc_receive_word_idx("r_cc_receive_word_idx"),
382	r_cc_receive_updt_fifo_be("r_cc_receive_updt_fifo_be", 2), // 2 words depth
383	r_cc_receive_updt_fifo_data("r_cc_receive_updt_fifo_data", 2), // 2 words depth
384	r_cc_receive_updt_fifo_eop("r_cc_receive_updt_fifo_eop", 2), // 2 words depth
385
386	r_cc_receive_icache_req("r_cc_receive_icache_req"),
387	r_cc_receive_icache_type("r_cc_receive_icache_type"),
388	r_cc_receive_icache_way("r_cc_receive_icache_way"),
389	r_cc_receive_icache_set("r_cc_receive_icache_set"),
390	r_cc_receive_icache_updt_tab_idx("r_cc_receive_icache_updt_tab_idx"),
391	r_cc_receive_icache_nline("r_cc_receive_icache_nline"),
392
393	r_cc_receive_dcache_req("r_cc_receive_dcache_req"),
394	r_cc_receive_dcache_type("r_cc_receive_dcache_type"),
395	r_cc_receive_dcache_way("r_cc_receive_dcache_way"),
396	r_cc_receive_dcache_set("r_cc_receive_dcache_set"),
397	r_cc_receive_dcache_updt_tab_idx("r_cc_receive_dcache_updt_tab_idx"),
398	r_cc_receive_dcache_nline("r_cc_receive_dcache_nline"),
399
400	r_iss(this->name(), proc_id),
401	r_wbuf("wbuf", wbuf_nwords, wbuf_nlines, dcache_words ),
402	r_icache("icache", icache_ways, icache_sets, icache_words),
403	r_dcache("dcache", dcache_ways, dcache_sets, dcache_words),
404	r_itlb("itlb", proc_id, itlb_ways,itlb_sets,vci_param::N),
405	r_dtlb("dtlb", proc_id, dtlb_ways,dtlb_sets,vci_param::N)
406	{
407	std::cout << " - Building VciCcVcacheWrapper : " << name << std::endl;
408
409	assert( ((icache_words*vci_param::B) < (1<<vci_param::K)) and
410	"Need more PLEN bits.");
411
412	assert( (vci_param::T > 2) and ((1<<(vci_param::T-1)) >= (wbuf_nlines)) and
413	"Need more TRDID bits.");
414
415	assert( (icache_words == dcache_words) and
416	"icache_words and dcache_words parameters must be equal");
417
418	assert( (itlb_sets == dtlb_sets) and
419	"itlb_sets and dtlb_sets parameters must be etqual");
420
421	assert( (itlb_ways == dtlb_ways) and
422	"itlb_ways and dtlb_ways parameters must be etqual");
423
424	r_mmu_params = (uint32_log2(m_dtlb_ways) << 29) \| (uint32_log2(m_dtlb_sets) << 25) \|
425	(uint32_log2(m_dcache_ways) << 22) \| (uint32_log2(m_dcache_sets) << 18) \|
426	(uint32_log2(m_itlb_ways) << 15) \| (uint32_log2(m_itlb_sets) << 11) \|
427	(uint32_log2(m_icache_ways) << 8) \| (uint32_log2(m_icache_sets) << 4) \|
428	(uint32_log2(m_icache_words<<2));
429
430	r_mmu_release = (uint32_t)(1 << 16) \| 0x1;
431
432	r_dcache_in_tlb = new bool[dcache_ways*dcache_sets];
433	r_dcache_contains_ptd = new bool[dcache_ways*dcache_sets];
434
435	SC_METHOD(transition);
436	dont_initialize();
437	sensitive << p_clk.pos();
438
439	SC_METHOD(genMoore);
440	dont_initialize();
441	sensitive << p_clk.neg();
442
443	typename iss_t::CacheInfo cache_info;
444	cache_info.has_mmu = true;
445	cache_info.icache_line_size = icache_words*sizeof(uint32_t);
446	cache_info.icache_assoc = icache_ways;
447	cache_info.icache_n_lines = icache_sets;
448	cache_info.dcache_line_size = dcache_words*sizeof(uint32_t);
449	cache_info.dcache_assoc = dcache_ways;
450	cache_info.dcache_n_lines = dcache_sets;
451	r_iss.setCacheInfo(cache_info);
452	}
453
454	/////////////////////////////////////
455	tmpl(/**/)::~VciCcVCacheWrapper()
456	/////////////////////////////////////
457	{
458	delete [] r_dcache_in_tlb;
459	delete [] r_dcache_contains_ptd;
460	}
461
462	////////////////////////
463	tmpl(void)::print_cpi()
464	////////////////////////
465	{
466	std::cout << name() << " CPI = "
467	<< (float)m_cpt_total_cycles/(m_cpt_total_cycles - m_cpt_frz_cycles) << std::endl ;
468	}
469
470	////////////////////////////////////
471	tmpl(void)::print_trace(size_t mode)
472	////////////////////////////////////
473	{
474	// b0 : write buffer trace
475	// b2 : dcache trace
476	// b3 : icache trace
477	// b4 : dtlb trace
478	// b5 : itlb trace
479
480	std::cout << std::dec << "PROC " << name() << std::endl;
481
482	std::cout << " " << m_ireq << std::endl;
483	std::cout << " " << m_irsp << std::endl;
484	std::cout << " " << m_dreq << std::endl;
485	std::cout << " " << m_drsp << std::endl;
486
487	std::cout << " " << icache_fsm_state_str[r_icache_fsm.read()]
488	<< " \| " << dcache_fsm_state_str[r_dcache_fsm.read()]
489	<< " \| " << cmd_fsm_state_str[r_vci_cmd_fsm.read()]
490	<< " \| " << rsp_fsm_state_str[r_vci_rsp_fsm.read()]
491	<< " \| " << cc_receive_fsm_state_str[r_cc_receive_fsm.read()]
492	<< " \| " << cc_send_fsm_state_str[r_cc_send_fsm.read()]
493	<< " \| MMU = " << r_mmu_mode.read();
494
495	if (r_dcache_updt_req.read() ) std::cout << " \| P1_UPDT";
496	if (r_dcache_wbuf_req.read() ) std::cout << " \| P1_WBUF";
497	std::cout << std::endl;
498
499	if(mode & 0x01)
500	{
501	if ( r_icache_miss_req.read() ) std::cout << " IMISS_REQ" << std::endl;
502	if ( r_icache_unc_req.read() ) std::cout << " IUNC_REQ" << std::endl;
503	if ( r_dcache_vci_miss_req.read() ) std::cout << " DMISS_REQ" << std::endl;
504	if ( r_dcache_vci_unc_req.read() ) std::cout << " DUNC_REQ" << std::endl;
505
506	r_wbuf.printTrace((mode>>1)&1);
507	}
508	if(mode & 0x04)
509	{
510	std::cout << " Data Cache" << std::endl;
511	r_dcache.printTrace();
512	}
513	if(mode & 0x08)
514	{
515	std::cout << " Instruction Cache" << std::endl;
516	r_icache.printTrace();
517	}
518	if(mode & 0x10)
519	{
520	std::cout << " Data TLB" << std::endl;
521	r_dtlb.printTrace();
522	}
523	if(mode & 0x20)
524	{
525	std::cout << " Instruction TLB" << std::endl;
526	r_itlb.printTrace();
527	}
528	}
529
530	//////////////////////////////////////////
531	tmpl(void)::cache_monitor( paddr_t addr )
532	//////////////////////////////////////////
533	{
534	bool cache_hit;
535	size_t cache_way = 0;
536	size_t cache_set = 0;
537	size_t cache_word = 0;
538	uint32_t cache_rdata = 0;
539
540	cache_hit = r_dcache.read_neutral( addr,
541	&cache_rdata,
542	&cache_way,
543	&cache_set,
544	&cache_word );
545
546	if ( cache_hit != m_debug_previous_d_hit )
547	{
548	std::cout << "Monitor PROC " << name()
549	<< " DCACHE at cycle " << std::dec << m_cpt_total_cycles
550	<< " / HIT = " << cache_hit
551	<< " / PADDR = " << std::hex << addr
552	<< " / DATA = " << cache_rdata
553	<< " / WAY = " << cache_way << std::endl;
554	m_debug_previous_d_hit = cache_hit;
555	}
556
557	cache_hit = r_icache.read_neutral( addr,
558	&cache_rdata,
559	&cache_way,
560	&cache_set,
561	&cache_word );
562
563	if ( cache_hit != m_debug_previous_i_hit )
564	{
565	std::cout << "Monitor PROC " << name()
566	<< " ICACHE at cycle " << std::dec << m_cpt_total_cycles
567	<< " / HIT = " << cache_hit
568	<< " / PADDR = " << std::hex << addr
569	<< " / DATA = " << cache_rdata
570	<< " / WAY = " << cache_way << std::endl;
571	m_debug_previous_i_hit = cache_hit;
572	}
573	}
574
575	/*
576	////////////////////////
577	tmpl(void)::print_stats()
578	////////////////////////
579	{
580	float run_cycles = (float)(m_cpt_total_cycles - m_cpt_frz_cycles);
581	std::cout << name() << std::endl
582	<< "- CPI = " << (float)m_cpt_total_cycles/run_cycles << std::endl
583	<< "- READ RATE = " << (float)m_cpt_read/run_cycles << std::endl
584	<< "- WRITE RATE = " << (float)m_cpt_write/run_cycles << std::endl
585	<< "- IMISS_RATE = " << (float)m_cpt_ins_miss/m_cpt_ins_read << std::endl
586	<< "- DMISS RATE = " << (float)m_cpt_data_miss/(m_cpt_read-m_cpt_unc_read) << std::endl
587	<< "- INS MISS COST = " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl
588	<< "- DATA MISS COST = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl
589	<< "- WRITE COST = " << (float)m_cost_write_frz/m_cpt_write << std::endl
590	<< "- UNC COST = " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl
591	<< "- UNCACHED READ RATE = " << (float)m_cpt_unc_read/m_cpt_read << std::endl
592	<< "- CACHED WRITE RATE = " << (float)m_cpt_write_cached/m_cpt_write << std::endl
593	<< "- INS TLB MISS RATE = " << (float)m_cpt_ins_tlb_miss/m_cpt_ins_tlb_read << std::endl
594	<< "- DATA TLB MISS RATE = " << (float)m_cpt_data_tlb_miss/m_cpt_data_tlb_read << std::endl
595	<< "- ITLB MISS COST = " << (float)m_cost_ins_tlb_miss_frz/m_cpt_ins_tlb_miss << std::endl
596	<< "- DTLB MISS COST = " << (float)m_cost_data_tlb_miss_frz/m_cpt_data_tlb_miss << std::endl
597	<< "- ITLB UPDATE ACC COST = " << (float)m_cost_ins_tlb_update_acc_frz/m_cpt_ins_tlb_update_acc << std::endl
598	<< "- DTLB UPDATE ACC COST = " << (float)m_cost_data_tlb_update_acc_frz/m_cpt_data_tlb_update_acc << std::endl
599	<< "- DTLB UPDATE DIRTY COST = " << (float)m_cost_data_tlb_update_dirty_frz/m_cpt_data_tlb_update_dirty << std::endl
600	<< "- ITLB HIT IN DCACHE RATE= " << (float)m_cpt_ins_tlb_hit_dcache/m_cpt_ins_tlb_miss << std::endl
601	<< "- DTLB HIT IN DCACHE RATE= " << (float)m_cpt_data_tlb_hit_dcache/m_cpt_data_tlb_miss << std::endl
602	<< "- DCACHE FROZEN BY ITLB = " << (float)m_cost_ins_tlb_occup_cache_frz/m_cpt_dcache_frz_cycles << std::endl
603	<< "- DCACHE FOR TLB % = " << (float)m_cpt_tlb_occup_dcache/(m_dcache_ways*m_dcache_sets) << std::endl
604	<< "- NB CC BROADCAST = " << m_cpt_cc_broadcast << std::endl
605	<< "- NB CC UPDATE DATA = " << m_cpt_cc_update_data << std::endl
606	<< "- NB CC INVAL DATA = " << m_cpt_cc_inval_data << std::endl
607	<< "- NB CC INVAL INS = " << m_cpt_cc_inval_ins << std::endl
608	<< "- CC BROADCAST COST = " << (float)m_cost_broadcast_frz/m_cpt_cc_broadcast << std::endl
609	<< "- CC UPDATE DATA COST = " << (float)m_cost_updt_data_frz/m_cpt_cc_update_data << std::endl
610	<< "- CC INVAL DATA COST = " << (float)m_cost_inval_data_frz/m_cpt_cc_inval_data << std::endl
611	<< "- CC INVAL INS COST = " << (float)m_cost_inval_ins_frz/m_cpt_cc_inval_ins << std::endl
612	<< "- NB CC CLEANUP DATA = " << m_cpt_cc_cleanup_data << std::endl
613	<< "- NB CC CLEANUP INS = " << m_cpt_cc_cleanup_ins << std::endl
614	<< "- IMISS TRANSACTION = " << (float)m_cost_imiss_transaction/m_cpt_imiss_transaction << std::endl
615	<< "- DMISS TRANSACTION = " << (float)m_cost_dmiss_transaction/m_cpt_dmiss_transaction << std::endl
616	<< "- UNC TRANSACTION = " << (float)m_cost_unc_transaction/m_cpt_unc_transaction << std::endl
617	<< "- WRITE TRANSACTION = " << (float)m_cost_write_transaction/m_cpt_write_transaction << std::endl
618	<< "- WRITE LENGTH = " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl
619	<< "- ITLB MISS TRANSACTION = " << (float)m_cost_itlbmiss_transaction/m_cpt_itlbmiss_transaction << std::endl
620	<< "- DTLB MISS TRANSACTION = " << (float)m_cost_dtlbmiss_transaction/m_cpt_dtlbmiss_transaction << std::endl;
621	}
622
623	////////////////////////
624	tmpl(void)::clear_stats()
625	////////////////////////
626	{
627	m_cpt_dcache_data_read = 0;
628	m_cpt_dcache_data_write = 0;
629	m_cpt_dcache_dir_read = 0;
630	m_cpt_dcache_dir_write = 0;
631	m_cpt_icache_data_read = 0;
632	m_cpt_icache_data_write = 0;
633	m_cpt_icache_dir_read = 0;
634	m_cpt_icache_dir_write = 0;
635
636	m_cpt_frz_cycles = 0;
637	m_cpt_dcache_frz_cycles = 0;
638	m_cpt_total_cycles = 0;
639
640	m_cpt_read = 0;
641	m_cpt_write = 0;
642	m_cpt_data_miss = 0;
643	m_cpt_ins_miss = 0;
644	m_cpt_unc_read = 0;
645	m_cpt_write_cached = 0;
646	m_cpt_ins_read = 0;
647
648	m_cost_write_frz = 0;
649	m_cost_data_miss_frz = 0;
650	m_cost_unc_read_frz = 0;
651	m_cost_ins_miss_frz = 0;
652
653	m_cpt_imiss_transaction = 0;
654	m_cpt_dmiss_transaction = 0;
655	m_cpt_unc_transaction = 0;
656	m_cpt_write_transaction = 0;
657	m_cpt_icache_unc_transaction = 0;
658
659	m_cost_imiss_transaction = 0;
660	m_cost_dmiss_transaction = 0;
661	m_cost_unc_transaction = 0;
662	m_cost_write_transaction = 0;
663	m_cost_icache_unc_transaction = 0;
664	m_length_write_transaction = 0;
665
666	m_cpt_ins_tlb_read = 0;
667	m_cpt_ins_tlb_miss = 0;
668	m_cpt_ins_tlb_update_acc = 0;
669
670	m_cpt_data_tlb_read = 0;
671	m_cpt_data_tlb_miss = 0;
672	m_cpt_data_tlb_update_acc = 0;
673	m_cpt_data_tlb_update_dirty = 0;
674	m_cpt_ins_tlb_hit_dcache = 0;
675	m_cpt_data_tlb_hit_dcache = 0;
676	m_cpt_ins_tlb_occup_cache = 0;
677	m_cpt_data_tlb_occup_cache = 0;
678
679	m_cost_ins_tlb_miss_frz = 0;
680	m_cost_data_tlb_miss_frz = 0;
681	m_cost_ins_tlb_update_acc_frz = 0;
682	m_cost_data_tlb_update_acc_frz = 0;
683	m_cost_data_tlb_update_dirty_frz = 0;
684	m_cost_ins_tlb_occup_cache_frz = 0;
685	m_cost_data_tlb_occup_cache_frz = 0;
686
687	m_cpt_itlbmiss_transaction = 0;
688	m_cpt_itlb_ll_transaction = 0;
689	m_cpt_itlb_sc_transaction = 0;
690	m_cpt_dtlbmiss_transaction = 0;
691	m_cpt_dtlb_ll_transaction = 0;
692	m_cpt_dtlb_sc_transaction = 0;
693	m_cpt_dtlb_ll_dirty_transaction = 0;
694	m_cpt_dtlb_sc_dirty_transaction = 0;
695
696	m_cost_itlbmiss_transaction = 0;
697	m_cost_itlb_ll_transaction = 0;
698	m_cost_itlb_sc_transaction = 0;
699	m_cost_dtlbmiss_transaction = 0;
700	m_cost_dtlb_ll_transaction = 0;
701	m_cost_dtlb_sc_transaction = 0;
702	m_cost_dtlb_ll_dirty_transaction = 0;
703	m_cost_dtlb_sc_dirty_transaction = 0;
704
705	m_cpt_cc_update_data = 0;
706	m_cpt_cc_inval_ins = 0;
707	m_cpt_cc_inval_data = 0;
708	m_cpt_cc_broadcast = 0;
709
710	m_cost_updt_data_frz = 0;
711	m_cost_inval_ins_frz = 0;
712	m_cost_inval_data_frz = 0;
713	m_cost_broadcast_frz = 0;
714
715	m_cpt_cc_cleanup_data = 0;
716	m_cpt_cc_cleanup_ins = 0;
717	}
718
719	*/
720
721	/////////////////////////
722	tmpl(void)::transition()
723	/////////////////////////
724	{
725	if ( not p_resetn.read() )
726	{
727	r_iss.reset();
728	r_wbuf.reset();
729	r_icache.reset();
730	r_dcache.reset();
731	r_itlb.reset();
732	r_dtlb.reset();
733
734	r_dcache_fsm = DCACHE_IDLE;
735	r_icache_fsm = ICACHE_IDLE;
736	r_vci_cmd_fsm = CMD_IDLE;
737	r_vci_rsp_fsm = RSP_IDLE;
738	r_cc_receive_fsm = CC_RECEIVE_IDLE;
739	r_cc_send_fsm = CC_SEND_IDLE;
740
741	// reset data physical address extension
742	r_dcache_paddr_ext = 0;
743
744	// reset dcache directory extension
745	for (size_t i=0 ; i< m_dcache_ways*m_dcache_sets ; i++)
746	{
747	r_dcache_in_tlb[i] = false;
748	r_dcache_contains_ptd[i] = false;
749	}
750
751	// Response FIFOs and cleanup buffer
752	r_vci_rsp_fifo_icache.init();
753	r_vci_rsp_fifo_dcache.init();
754
755	// ICACHE & DCACHE activated
756	// ITLB & DTLB desactivated
757	r_mmu_mode = 0x3;
758
759	// No request from ICACHE FSM to CMD FSM
760	r_icache_miss_req = false;
761	r_icache_unc_req = false;
762
763	// No request from ICACHE_FSM to DCACHE FSM
764	r_icache_tlb_miss_req = false;
765
766	// No request from ICACHE_FSM to CC_SEND FSM
767	r_icache_cc_send_req = false;
768	r_icache_cleanup_victim_req = false;
769
770	r_icache_clack_req = false;
771
772	// No pending write in pipeline
773	r_dcache_wbuf_req = false;
774	r_dcache_updt_req = false;
775
776	// No request from DCACHE_FSM to CMD_FSM
777	r_dcache_vci_miss_req = false;
778	r_dcache_vci_unc_req = false;
779	r_dcache_vci_cas_req = false;
780	r_dcache_vci_ll_req = false;
781	r_dcache_vci_sc_req = false;
782
783	// No processor XTN request pending
784	r_dcache_xtn_req = false;
785
786	// No request from DCACHE FSM to CC_SEND FSM
787	r_dcache_cc_send_req = false;
788	r_dcache_cleanup_victim_req = false;
789
790	r_dcache_clack_req = false;
791
792	// No request from CC_RECEIVE FSM to ICACHE/DCACHE FSMs
793	r_cc_receive_icache_req = false;
794	r_cc_receive_dcache_req = false;
795
796	// last cc_send client was dcache
797	r_cc_send_last_client = false;
798
799	// No pending cleanup after a replacement
800	r_icache_miss_clack = false;
801	r_dcache_miss_clack = false;
802
803	// No signalisation of a coherence request matching a pending miss
804	r_icache_miss_inval = false;
805	r_dcache_miss_inval = false;
806
807	r_dspin_clack_req = false;
808
809	// No signalisation of errors
810	r_vci_rsp_ins_error = false;
811	r_vci_rsp_data_error = false;
812
813	// Debug variables
814	m_debug_previous_i_hit = false;
815	m_debug_previous_d_hit = false;
816	m_debug_icache_fsm = false;
817	m_debug_dcache_fsm = false;
818	m_debug_cmd_fsm = false;
819
820	// activity counters
821	m_cpt_dcache_data_read = 0;
822	m_cpt_dcache_data_write = 0;
823	m_cpt_dcache_dir_read = 0;
824	m_cpt_dcache_dir_write = 0;
825	m_cpt_icache_data_read = 0;
826	m_cpt_icache_data_write = 0;
827	m_cpt_icache_dir_read = 0;
828	m_cpt_icache_dir_write = 0;
829
830	m_cpt_frz_cycles = 0;
831	m_cpt_total_cycles = 0;
832	m_cpt_stop_simulation = 0;
833
834	m_cpt_data_miss = 0;
835	m_cpt_ins_miss = 0;
836	m_cpt_unc_read = 0;
837	m_cpt_write_cached = 0;
838	m_cpt_ins_read = 0;
839
840	m_cost_write_frz = 0;
841	m_cost_data_miss_frz = 0;
842	m_cost_unc_read_frz = 0;
843	m_cost_ins_miss_frz = 0;
844
845	m_cpt_imiss_transaction = 0;
846	m_cpt_dmiss_transaction = 0;
847	m_cpt_unc_transaction = 0;
848	m_cpt_write_transaction = 0;
849	m_cpt_icache_unc_transaction = 0;
850
851	m_cost_imiss_transaction = 0;
852	m_cost_dmiss_transaction = 0;
853	m_cost_unc_transaction = 0;
854	m_cost_write_transaction = 0;
855	m_cost_icache_unc_transaction = 0;
856	m_length_write_transaction = 0;
857
858	m_cpt_ins_tlb_read = 0;
859	m_cpt_ins_tlb_miss = 0;
860	m_cpt_ins_tlb_update_acc = 0;
861
862	m_cpt_data_tlb_read = 0;
863	m_cpt_data_tlb_miss = 0;
864	m_cpt_data_tlb_update_acc = 0;
865	m_cpt_data_tlb_update_dirty = 0;
866	m_cpt_ins_tlb_hit_dcache = 0;
867	m_cpt_data_tlb_hit_dcache = 0;
868	m_cpt_ins_tlb_occup_cache = 0;
869	m_cpt_data_tlb_occup_cache = 0;
870
871	m_cost_ins_tlb_miss_frz = 0;
872	m_cost_data_tlb_miss_frz = 0;
873	m_cost_ins_tlb_update_acc_frz = 0;
874	m_cost_data_tlb_update_acc_frz = 0;
875	m_cost_data_tlb_update_dirty_frz = 0;
876	m_cost_ins_tlb_occup_cache_frz = 0;
877	m_cost_data_tlb_occup_cache_frz = 0;
878
879	m_cpt_ins_tlb_inval = 0;
880	m_cpt_data_tlb_inval = 0;
881	m_cost_ins_tlb_inval_frz = 0;
882	m_cost_data_tlb_inval_frz = 0;
883
884	m_cpt_cc_broadcast = 0;
885
886	m_cost_updt_data_frz = 0;
887	m_cost_inval_ins_frz = 0;
888	m_cost_inval_data_frz = 0;
889	m_cost_broadcast_frz = 0;
890
891	m_cpt_cc_cleanup_data = 0;
892	m_cpt_cc_cleanup_ins = 0;
893
894	m_cpt_itlbmiss_transaction = 0;
895	m_cpt_itlb_ll_transaction = 0;
896	m_cpt_itlb_sc_transaction = 0;
897	m_cpt_dtlbmiss_transaction = 0;
898	m_cpt_dtlb_ll_transaction = 0;
899	m_cpt_dtlb_sc_transaction = 0;
900	m_cpt_dtlb_ll_dirty_transaction = 0;
901	m_cpt_dtlb_sc_dirty_transaction = 0;
902
903	m_cost_itlbmiss_transaction = 0;
904	m_cost_itlb_ll_transaction = 0;
905	m_cost_itlb_sc_transaction = 0;
906	m_cost_dtlbmiss_transaction = 0;
907	m_cost_dtlb_ll_transaction = 0;
908	m_cost_dtlb_sc_transaction = 0;
909	m_cost_dtlb_ll_dirty_transaction = 0;
910	m_cost_dtlb_sc_dirty_transaction = 0;
911	/*
912	m_cpt_dcache_frz_cycles = 0;
913	m_cpt_read = 0;
914	m_cpt_write = 0;
915	m_cpt_cc_update_data = 0;
916	m_cpt_cc_inval_ins = 0;
917	m_cpt_cc_inval_data = 0;
918	*/
919
920	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_icache [i] = 0;
921	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_dcache [i] = 0;
922	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_cmd [i] = 0;
923	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_rsp [i] = 0;
924
925	// init the llsc reservation buffer
926	r_dcache_llsc_valid = false;
927	m_monitor_ok = false;
928
929	return;
930	}
931
932	// Response FIFOs default values
933	bool vci_rsp_fifo_icache_get = false;
934	bool vci_rsp_fifo_icache_put = false;
935	uint32_t vci_rsp_fifo_icache_data = 0;
936
937	bool vci_rsp_fifo_dcache_get = false;
938	bool vci_rsp_fifo_dcache_put = false;
939	uint32_t vci_rsp_fifo_dcache_data = 0;
940
941	// updt fifo
942	bool cc_receive_updt_fifo_get = false;
943	bool cc_receive_updt_fifo_put = false;
944	uint32_t cc_receive_updt_fifo_be = 0;
945	uint32_t cc_receive_updt_fifo_data = 0;
946	bool cc_receive_updt_fifo_eop = false;
947
948	#ifdef INSTRUMENTATION
949	m_cpt_fsm_dcache [r_dcache_fsm.read() ] ++;
950	m_cpt_fsm_icache [r_icache_fsm.read() ] ++;
951	m_cpt_fsm_cmd [r_vci_cmd_fsm.read()] ++;
952	m_cpt_fsm_rsp [r_vci_rsp_fsm.read()] ++;
953	m_cpt_fsm_tgt [r_tgt_fsm.read() ] ++;
954	m_cpt_fsm_cleanup [r_cleanup_cmd_fsm.read()] ++;
955	#endif
956
957	m_cpt_total_cycles++;
958
959	m_debug_icache_fsm = m_debug_icache_fsm \|\|
960	((m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok);
961	m_debug_dcache_fsm = m_debug_dcache_fsm \|\|
962	((m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok);
963	m_debug_cmd_fsm = m_debug_cmd_fsm \|\|
964	((m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok);
965
966	/////////////////////////////////////////////////////////////////////
967	// Get data and instruction requests from processor
968	///////////////////////////////////////////////////////////////////////
969
970	r_iss.getRequests(m_ireq, m_dreq);
971
972	////////////////////////////////////////////////////////////////////////////////////
973	// ICACHE_FSM
974	//
975	// 1/ Coherence operations
976	// They are handled as interrupts generated by the CC_RECEIVE FSM.
977	// - There is a coherence request when r_tgt_icache_req is set.
978	// They are taken in IDLE, MISS_WAIT, MISS_DIR_UPDT, UNC_WAIT, states.
979	// - There is a cleanup ack request when r_cleanup_icache_req is set.
980	// They are taken in IDLE, MISS_SELECT, MISS_CLEAN, MISS_WAIT,
981	// MISS_DATA_UPDT, MISS_DIR_UPDT and UNC_WAIT states.
982	// - For both types of requests, actions associated to the pre-empted state
983	// are not executed. The DCACHE FSM goes to the proper sub-FSM (CC_CHECK
984	// or CC_CLACK) to execute the requested coherence operation, and returns
985	// to the pre-empted state.
986	//
987	// 2/ Processor requests
988	// They are taken in IDLE state only. In case of cache miss, or uncacheable
989	// instruction, the ICACHE FSM request a VCI transaction to CMD FSM,
990	// using the r_icache_miss_req or r_icache_unc_req flip-flops. These
991	// flip-flops are reset when the transaction starts.
992	// - In case of miss the ICACHE FSM goes to the ICACHE_MISS_SELECT state
993	// to select a slot and possibly request a cleanup transaction to the CC_SEND FSM.
994	// It goes next to the ICACHE_MISS_WAIT state waiting a response from RSP FSM,
995	// The availability of the missing cache line is signaled by the response fifo,
996	// and the cache update is done (one word per cycle) in the ICACHE_MISS_DATA_UPDT
997	// and ICACHE_MISS_DIR_UPDT states.
998	// - In case of uncacheable instruction, the ICACHE FSM goes to ICACHE_UNC_WAIT
999	// to wait the response from the RSP FSM, through the response fifo.
1000	// The missing instruction is directly returned to processor in this state.
1001	//
1002	// 3/ TLB miss
1003	// In case of tlb miss, the ICACHE FSM request to the DCACHE FSM to update the
1004	// ITLB using the r_icache_tlb_miss_req flip-flop and the r_icache_tlb_miss_vaddr
1005	// register, and goes to the ICACHE_TLB_WAIT state.
1006	// The tlb update is entirely done by the DCACHE FSM (who becomes the owner
1007	// of ITLB until the update is completed, and reset r_icache_tlb_miss_req
1008	// to signal the completion.
1009	//
1010	// 4/ XTN requests
1011	// The DCACHE FSM signals XTN processor requests to ICACHE_FSM
1012	// using the r_dcache_xtn_req flip-flop.
1013	// The request opcode and the address to be invalidated are transmitted
1014	// in the r_dcache_xtn_opcode and r_dcache_save_wdata registers respectively.
1015	// The r_dcache_xtn_req flip-flop is reset by the ICACHE_FSM when the operation
1016	// is completed.
1017	//
1018	// 5/ Error Handling
1019	// The r_vci_rsp_ins_error flip-flop is set by the RSP FSM in case of bus error
1020	// in a cache miss or uncacheable read VCI transaction. Nothing is written
1021	// in the response fifo. This flip-flop is reset by the ICACHE-FSM.
1022	////////////////////////////////////////////////////////////////////////////////////////
1023
1024	// default value for m_irsp
1025	m_irsp.valid = false;
1026	m_irsp.error = false;
1027	m_irsp.instruction = 0;
1028
1029	switch( r_icache_fsm.read() )
1030	{
1031	/////////////////
1032	case ICACHE_IDLE: // In this state, we handle processor requests, XTN requests,
1033	// and coherence requests with a fixed priority:
1034	// 1/ Coherence requests => ICACHE_CC_CHECK
1035	// 2/ XTN processor requests (from DCACHE FSM) => ICACHE_XTN_*
1036	// 3/ tlb miss => ICACHE_TLB_WAIT
1037	// 4/ cacheable read miss => ICACHE_MISS_SELECT
1038	// 5/ uncacheable read miss => ICACHE_UNC_REQ
1039	{
1040	// coherence clack interrupt
1041	if ( r_icache_clack_req.read() )
1042	{
1043	r_icache_fsm = ICACHE_CC_CHECK;
1044	r_icache_fsm_save = r_icache_fsm.read();
1045	break;
1046	}
1047
1048	// coherence interrupt
1049	if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read())
1050	{
1051	r_icache_fsm = ICACHE_CC_CHECK;
1052	r_icache_fsm_save = r_icache_fsm.read();
1053	break;
1054	}
1055
1056	// XTN requests sent by DCACHE FSM
1057	// These request are not executed in this IDLE state, because
1058	// they require access to icache or itlb, that are already accessed
1059	if ( r_dcache_xtn_req.read() )
1060	{
1061	if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_PTPR )
1062	{
1063	r_icache_fsm = ICACHE_XTN_TLB_FLUSH;
1064	}
1065	else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ICACHE_FLUSH)
1066	{
1067	r_icache_flush_count = 0;
1068	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH;
1069	}
1070	else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ITLB_INVAL)
1071	{
1072	r_icache_fsm = ICACHE_XTN_TLB_INVAL;
1073	}
1074	else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ICACHE_INVAL)
1075	{
1076	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_VA;
1077	}
1078	else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_MMU_ICACHE_PA_INV)
1079	{
1080	if (sizeof(paddr_t) <= 32)
1081	{
1082	assert(r_mmu_word_hi.read() == 0 &&
1083	"illegal XTN request in ICACHE: high bits should be 0 for 32bit paddr");
1084	r_icache_vci_paddr = (paddr_t)r_mmu_word_lo.read();
1085	}
1086	else
1087	{
1088	r_icache_vci_paddr = (paddr_t)r_mmu_word_hi.read() << 32 \|
1089	(paddr_t)r_mmu_word_lo.read();
1090	}
1091	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA;
1092	}
1093	else
1094	{
1095	assert( false and
1096	"undefined XTN request received by ICACHE FSM");
1097	}
1098	break;
1099	} // end if xtn_req
1100
1101	// processor request
1102	if ( m_ireq.valid )
1103	{
1104	bool cacheable;
1105	paddr_t paddr;
1106	bool tlb_hit = false;
1107	pte_info_t tlb_flags;
1108	size_t tlb_way;
1109	size_t tlb_set;
1110	paddr_t tlb_nline;
1111	uint32_t cache_inst = 0;
1112	size_t cache_way;
1113	size_t cache_set;
1114	size_t cache_word;
1115	int cache_state = CACHE_SLOT_STATE_EMPTY;
1116
1117	// We register processor request
1118	r_icache_vaddr_save = m_ireq.addr;
1119
1120	// sytematic itlb access (if activated)
1121	if ( r_mmu_mode.read() & INS_TLB_MASK )
1122	{
1123
1124	#ifdef INSTRUMENTATION
1125	m_cpt_itlb_read++;
1126	#endif
1127	tlb_hit = r_itlb.translate( m_ireq.addr,
1128	&paddr,
1129	&tlb_flags,
1130	&tlb_nline, // unused
1131	&tlb_way, // unused
1132	&tlb_set ); // unused
1133	}
1134	else
1135	{
1136	paddr = (paddr_t)m_ireq.addr;
1137	}
1138
1139	// systematic icache access (if activated)
1140	if ( r_mmu_mode.read() & INS_CACHE_MASK )
1141	{
1142
1143
1144	#ifdef INSTRUMENTATION
1145	m_cpt_icache_data_read++;
1146	m_cpt_icache_dir_read++;
1147	#endif
1148	r_icache.read( paddr,
1149	&cache_inst,
1150	&cache_way,
1151	&cache_set,
1152	&cache_word,
1153	&cache_state );
1154	}
1155
1156	// We compute cacheability and check access rights:
1157	// - If MMU activated : cacheability is defined by the C bit in the PTE,
1158	// and the access rights are defined by the U and X bits in the PTE.
1159	// - If MMU not activated : cacheability is defined by the segment table,
1160	// and there is no access rights checking
1161
1162	if ( not (r_mmu_mode.read() & INS_TLB_MASK) ) // tlb not activated:
1163	{
1164	// cacheability
1165	if ( not (r_mmu_mode.read() & INS_CACHE_MASK) ) cacheable = false;
1166	else cacheable = m_cacheability_table[(uint64_t)m_ireq.addr];
1167	}
1168	else // itlb activated
1169	{
1170	if ( tlb_hit ) // ITLB hit
1171	{
1172	// cacheability
1173	if ( not (r_mmu_mode.read() & INS_CACHE_MASK) ) cacheable = false;
1174	else cacheable = tlb_flags.c;
1175
1176	// access rights checking
1177	if ( not tlb_flags.u && (m_ireq.mode == iss_t::MODE_USER) )
1178	{
1179	r_mmu_ietr = MMU_READ_PRIVILEGE_VIOLATION;
1180	r_mmu_ibvar = m_ireq.addr;
1181	m_irsp.valid = true;
1182	m_irsp.error = true;
1183	m_irsp.instruction = 0;
1184	break;
1185	}
1186	else if ( not tlb_flags.x )
1187	{
1188	r_mmu_ietr = MMU_READ_EXEC_VIOLATION;
1189	r_mmu_ibvar = m_ireq.addr;
1190	m_irsp.valid = true;
1191	m_irsp.error = true;
1192	m_irsp.instruction = 0;
1193	break;
1194	}
1195	}
1196	else // ITLB miss
1197	{
1198
1199	#ifdef INSTRUMENTATION
1200	m_cpt_itlb_miss++;
1201	#endif
1202	r_icache_fsm = ICACHE_TLB_WAIT;
1203	r_icache_tlb_miss_req = true;
1204	break;
1205	}
1206	} // end if itlb activated
1207
1208	// physical address registration
1209	r_icache_vci_paddr = paddr;
1210
1211	// Finally, we send the response to processor, and compute next state
1212	if ( cacheable )
1213	{
1214	if (cache_state == CACHE_SLOT_STATE_EMPTY) // cache miss
1215	{
1216
1217	#ifdef INSTRUMENTATION
1218	m_cpt_icache_miss++;
1219	#endif
1220	// we request a VCI transaction
1221	r_icache_fsm = ICACHE_MISS_SELECT;
1222	#if DEBUG_ICACHE
1223	if ( m_debug_icache_fsm )
1224	std::cout << " <PROC " << name() << " ICACHE_IDLE> READ MISS in icache"
1225	<< " : PADDR = " << std::hex << paddr << std::endl;
1226	#endif
1227	r_icache_miss_req = true;
1228	}
1229	else if (cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup
1230	{
1231	// stalled until cleanup is acknowledged
1232	r_icache_fsm = ICACHE_IDLE;
1233	}
1234	else // cache hit
1235	{
1236
1237	#ifdef INSTRUMENTATION
1238	m_cpt_ins_read++;
1239	#endif
1240	// return instruction to processor
1241	m_irsp.valid = true;
1242	m_irsp.instruction = cache_inst;
1243	r_icache_fsm = ICACHE_IDLE;
1244	#if DEBUG_ICACHE
1245	if ( m_debug_icache_fsm )
1246	std::cout << " <PROC " << name() << " ICACHE_IDLE> READ HIT in icache"
1247	<< " : PADDR = " << std::hex << paddr
1248	<< " / INST = " << cache_inst << std::endl;
1249	#endif
1250	}
1251	}
1252	else // non cacheable read
1253	{
1254	r_icache_unc_req = true;
1255	r_icache_fsm = ICACHE_UNC_WAIT;
1256
1257	#if DEBUG_ICACHE
1258	if ( m_debug_icache_fsm )
1259	{
1260	std::cout << " <PROC " << name()
1261	<< " ICACHE_IDLE> READ UNCACHEABLE in icache"
1262	<< " : PADDR = " << std::hex << paddr << std::endl;
1263	}
1264	#endif
1265	}
1266	} // end if m_ireq.valid
1267	break;
1268	}
1269	/////////////////////
1270	case ICACHE_TLB_WAIT: // Waiting the itlb update by the DCACHE FSM after a tlb miss
1271	// the itlb is udated by the DCACHE FSM, as well as the
1272	// r_mmu_ietr and r_mmu_ibvar registers in case of error.
1273	// the itlb is not accessed by ICACHE FSM until DCACHE FSM
1274	// reset the r_icache_tlb_miss_req flip-flop
1275	// external coherence request are accepted in this state.
1276	{
1277	// coherence clack interrupt
1278	if ( r_icache_clack_req.read() )
1279	{
1280	r_icache_fsm = ICACHE_CC_CHECK;
1281	r_icache_fsm_save = r_icache_fsm.read();
1282	break;
1283	}
1284
1285	// coherence interrupt
1286	if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read())
1287	{
1288	r_icache_fsm = ICACHE_CC_CHECK;
1289	r_icache_fsm_save = r_icache_fsm.read();
1290	break;
1291	}
1292
1293	if ( m_ireq.valid ) m_cost_ins_tlb_miss_frz++;
1294
1295	// DCACHE FSM signals response by reseting the request flip-flop
1296	if ( not r_icache_tlb_miss_req.read() )
1297	{
1298	if ( r_icache_tlb_rsp_error.read() ) // error reported : tlb not updated
1299	{
1300	r_icache_tlb_rsp_error = false;
1301	m_irsp.error = true;
1302	m_irsp.valid = true;
1303	r_icache_fsm = ICACHE_IDLE;
1304	}
1305	else // tlb updated : return to IDLE state
1306	{
1307	r_icache_fsm = ICACHE_IDLE;
1308	}
1309	}
1310	break;
1311	}
1312	//////////////////////////
1313	case ICACHE_XTN_TLB_FLUSH: // invalidate in one cycle all non global TLB entries
1314	{
1315	r_itlb.flush();
1316	r_dcache_xtn_req = false;
1317	r_icache_fsm = ICACHE_IDLE;
1318	break;
1319	}
1320	////////////////////////////
1321	case ICACHE_XTN_CACHE_FLUSH: // Invalidate sequencially all cache lines, using
1322	// r_icache_flush_count as a slot counter,
1323	// looping in this state until all slots are visited.
1324	// It can require two cycles per slot:
1325	// We test here the slot state, and make the actual inval
1326	// (if line is valid) in ICACHE_XTN_CACHE_FLUSH_GO state.
1327	// A cleanup request is generated for each valid line
1328	{
1329	// coherence clack interrupt
1330	if ( r_icache_clack_req.read() )
1331	{
1332	r_icache_fsm = ICACHE_CC_CHECK;
1333	r_icache_fsm_save = r_icache_fsm.read();
1334	break;
1335	}
1336
1337	// coherence request (from CC_RECEIVE FSM)
1338	if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read())
1339	{
1340	r_icache_fsm = ICACHE_CC_CHECK;
1341	r_icache_fsm_save = r_icache_fsm.read();
1342	break;
1343	}
1344
1345	if ( not r_icache_cc_send_req.read() ) // blocked until previous cc_send request is sent
1346	{
1347	int state;
1348	paddr_t tag;
1349	size_t way = r_icache_flush_count.read()/m_icache_sets;
1350	size_t set = r_icache_flush_count.read()%m_icache_sets;
1351
1352	#ifdef INSTRUMENTATION
1353	m_cpt_icache_dir_read++;
1354	#endif
1355	r_icache.read_dir( way,
1356	set,
1357	&tag,
1358	&state );
1359
1360	if ( state == CACHE_SLOT_STATE_VALID ) // inval required
1361	{
1362	// request cleanup
1363	r_icache_cc_send_req = true;
1364	r_icache_cc_send_nline = tag * m_icache_sets + set;
1365	r_icache_cc_send_way = way;
1366	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1367
1368	// goes to ICACHE_XTN_CACHE_FLUSH_GO to make inval
1369	r_icache_miss_way = way;
1370	r_icache_miss_set = set;
1371	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH_GO;
1372	}
1373	else if ( r_icache_flush_count.read() ==
1374	(m_icache_sets*m_icache_ways - 1) ) // last slot
1375	{
1376	r_dcache_xtn_req = false;
1377	m_drsp.valid = true;
1378	r_icache_fsm = ICACHE_IDLE;
1379	}
1380
1381	// saturation counter, to have the same last slot condition
1382	// in ICACHE_XTN_CACHE_FLUSH and ICACHE_XTN_CACHE_FLUSH_GO states
1383	if ( r_icache_flush_count.read() < (m_icache_sets*m_icache_ways - 1) )
1384	{
1385	r_icache_flush_count = r_icache_flush_count.read() + 1;
1386	}
1387	}
1388	break;
1389	}
1390	///////////////////////////////
1391	case ICACHE_XTN_CACHE_FLUSH_GO: // Switch slot state to ZOMBI for an XTN flush
1392	{
1393	size_t way = r_icache_miss_way.read();
1394	size_t set = r_icache_miss_set.read();
1395
1396	#ifdef INSTRUMENTATION
1397	m_cpt_icache_dir_write++;
1398	#endif
1399
1400	r_icache.write_dir( way,
1401	set,
1402	CACHE_SLOT_STATE_ZOMBI );
1403
1404	if ( r_icache_flush_count.read() ==
1405	(m_icache_sets*m_icache_ways - 1) ) // last slot
1406	{
1407	r_dcache_xtn_req = false;
1408	m_drsp.valid = true;
1409	r_icache_fsm = ICACHE_IDLE;
1410	}
1411	else
1412	{
1413	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH;
1414	}
1415	break;
1416	}
1417
1418	//////////////////////////
1419	case ICACHE_XTN_TLB_INVAL: // invalidate one TLB entry selected by the virtual address
1420	// stored in the r_dcache_save_wdata register
1421	{
1422	r_itlb.inval(r_dcache_save_wdata.read());
1423	r_dcache_xtn_req = false;
1424	r_icache_fsm = ICACHE_IDLE;
1425	break;
1426	}
1427	///////////////////////////////
1428	case ICACHE_XTN_CACHE_INVAL_VA: // Selective cache line invalidate with virtual address
1429	// requires 3 cycles (in case of hit on itlb and icache).
1430	// In this state, access TLB to translate virtual address
1431	// stored in the r_dcache_save_wdata register.
1432	{
1433	paddr_t paddr;
1434	bool hit;
1435
1436	// read physical address in TLB when MMU activated
1437	if ( r_mmu_mode.read() & INS_TLB_MASK ) // itlb activated
1438	{
1439
1440	#ifdef INSTRUMENTATION
1441	m_cpt_itlb_read++;
1442	#endif
1443	hit = r_itlb.translate(r_dcache_save_wdata.read(),
1444	&paddr);
1445	}
1446	else // itlb not activated
1447	{
1448	paddr = (paddr_t)r_dcache_save_wdata.read();
1449	hit = true;
1450	}
1451
1452	if ( hit ) // continue the selective inval process
1453	{
1454	r_icache_vci_paddr = paddr;
1455	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA;
1456	}
1457	else // miss : send a request to DCACHE FSM
1458	{
1459
1460	#ifdef INSTRUMENTATION
1461	m_cpt_itlb_miss++;
1462	#endif
1463	r_icache_tlb_miss_req = true;
1464	r_icache_vaddr_save = r_dcache_save_wdata.read();
1465	r_icache_fsm = ICACHE_TLB_WAIT;
1466	}
1467	break;
1468	}
1469	///////////////////////////////
1470	case ICACHE_XTN_CACHE_INVAL_PA: // selective invalidate cache line with physical address
1471	// require 2 cycles. In this state, we read directory
1472	// with address stored in r_icache_vci_paddr register.
1473	{
1474	int state;
1475	size_t way;
1476	size_t set;
1477	size_t word;
1478
1479	#ifdef INSTRUMENTATION
1480	m_cpt_icache_dir_read++;
1481	#endif
1482	r_icache.read_dir(r_icache_vci_paddr.read(),
1483	&state,
1484	&way,
1485	&set,
1486	&word);
1487
1488	if ( state == CACHE_SLOT_STATE_VALID ) // inval to be done
1489	{
1490	r_icache_miss_way = way;
1491	r_icache_miss_set = set;
1492	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_GO;
1493	}
1494	else // miss : acknowlege the XTN request and return
1495	{
1496	r_dcache_xtn_req = false;
1497	r_icache_fsm = ICACHE_IDLE;
1498	}
1499	break;
1500	}
1501	///////////////////////////////
1502	case ICACHE_XTN_CACHE_INVAL_GO: // Switch slot to ZOMBI state for an XTN inval
1503	{
1504	if ( not r_icache_cc_send_req.read() ) // blocked until previous cc_send request not sent
1505	{
1506
1507	#ifdef INSTRUMENTATION
1508	m_cpt_icache_dir_write++;
1509	#endif
1510	r_icache.write_dir( r_icache_miss_way.read(),
1511	r_icache_miss_set.read(),
1512	CACHE_SLOT_STATE_ZOMBI );
1513
1514	// request cleanup
1515	r_icache_cc_send_req = true;
1516	r_icache_cc_send_nline = r_icache_vci_paddr.read() / (m_icache_words<<2);
1517	r_icache_cc_send_way = r_icache_miss_way.read();
1518	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1519
1520	// acknowledge the XTN request and return
1521	r_dcache_xtn_req = false;
1522	r_icache_fsm = ICACHE_IDLE;
1523	}
1524	break;
1525	}
1526	////////////////////////
1527	case ICACHE_MISS_SELECT: // Try to select a slot in associative set,
1528	// Waiting in this state if no slot available.
1529	// If a victim slot has been choosen and the r_icache_cc_send_req is false,
1530	// we send the cleanup request in this state.
1531	// If not, a r_icache_cleanup_victim_req flip-flop is
1532	// utilized for saving this cleanup request, and it will be sent later
1533	// in state ICACHE_MISS_WAIT or ICACHE_MISS_UPDT_DIR.
1534	// The r_icache_miss_clack flip-flop is set
1535	// when a cleanup is required
1536	{
1537	if (m_ireq.valid) m_cost_ins_miss_frz++;
1538
1539	// coherence clack interrupt
1540	if ( r_icache_clack_req.read() )
1541	{
1542	r_icache_fsm = ICACHE_CC_CHECK;
1543	r_icache_fsm_save = r_icache_fsm.read();
1544	break;
1545	}
1546
1547	// coherence interrupt
1548	if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read())
1549	{
1550	r_icache_fsm = ICACHE_CC_CHECK;
1551	r_icache_fsm_save = r_icache_fsm.read();
1552	break;
1553	}
1554
1555
1556	bool found;
1557	bool cleanup;
1558	size_t way;
1559	size_t set;
1560	paddr_t victim;
1561
1562	#ifdef INSTRUMENTATION
1563	m_cpt_icache_dir_read++;
1564	#endif
1565	r_icache.read_select(r_icache_vci_paddr.read(),
1566	&victim,
1567	&way,
1568	&set,
1569	&found,
1570	&cleanup );
1571	if ( not found )
1572	{
1573	break;
1574	}
1575	else
1576	{
1577	r_icache_miss_way = way;
1578	r_icache_miss_set = set;
1579
1580	if ( cleanup )
1581	{
1582	if ( not r_icache_cc_send_req.read() )
1583	{
1584	r_icache_cc_send_req = true;
1585	r_icache_cc_send_nline = victim;
1586	r_icache_cc_send_way = way;
1587	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1588	}
1589	else
1590	{
1591	r_icache_cleanup_victim_req = true;
1592	r_icache_cleanup_victim_nline = victim;
1593	}
1594
1595	r_icache_miss_clack = true;
1596	r_icache_fsm = ICACHE_MISS_CLEAN;
1597	}
1598	else
1599	{
1600	r_icache_fsm = ICACHE_MISS_WAIT;
1601	}
1602
1603	#if DEBUG_ICACHE
1604	if ( m_debug_icache_fsm )
1605	{
1606	std::cout << " <PROC " << name()
1607	<< " ICACHE_MISS_SELECT> Select a slot:" << std::dec
1608	<< " / WAY = " << way
1609	<< " / SET = " << set;
1610	if (cleanup) std::cout << " / VICTIM = " << std::hex << victim << std::endl;
1611	else std::cout << std::endl;
1612	}
1613	#endif
1614	}
1615	break;
1616	}
1617	///////////////////////
1618	case ICACHE_MISS_CLEAN: // switch the slot to zombi state
1619	{
1620	if (m_ireq.valid) m_cost_ins_miss_frz++;
1621
1622	#ifdef INSTRUMENTATION
1623	m_cpt_icache_dir_write++;
1624	#endif
1625	r_icache.write_dir( r_icache_miss_way.read(),
1626	r_icache_miss_set.read(),
1627	CACHE_SLOT_STATE_ZOMBI);
1628	#if DEBUG_ICACHE
1629	if ( m_debug_icache_fsm )
1630	{
1631	std::cout << " <PROC " << name()
1632	<< " ICACHE_MISS_CLEAN> Switch to ZOMBI state" << std::dec
1633	<< " / WAY = " << r_icache_miss_way.read()
1634	<< " / SET = " << r_icache_miss_set.read() << std::endl;
1635	}
1636	#endif
1637
1638	r_icache_fsm = ICACHE_MISS_WAIT;
1639	break;
1640	}
1641	//////////////////////
1642	case ICACHE_MISS_WAIT: // waiting response from VCI_RSP FSM
1643	{
1644	if (m_ireq.valid) m_cost_ins_miss_frz++;
1645
1646	// send cleanup victim request
1647	if ( r_icache_cleanup_victim_req.read() and not r_icache_cc_send_req.read() )
1648	{
1649	r_icache_cc_send_req = true;
1650	r_icache_cc_send_nline = r_icache_cleanup_victim_nline;
1651	r_icache_cc_send_way = r_icache_miss_way;
1652	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1653	r_icache_cleanup_victim_req = false;
1654	}
1655
1656	// coherence clack interrupt
1657	if ( r_icache_clack_req.read() )
1658	{
1659	r_icache_fsm = ICACHE_CC_CHECK;
1660	r_icache_fsm_save = r_icache_fsm.read();
1661	break;
1662	}
1663
1664	// coherence interrupt
1665	if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read() and not r_icache_cleanup_victim_req.read() )
1666	{
1667	r_icache_fsm = ICACHE_CC_CHECK;
1668	r_icache_fsm_save = r_icache_fsm.read();
1669	break;
1670	}
1671
1672	if ( r_vci_rsp_ins_error.read() ) // bus error
1673	{
1674	r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS;
1675	r_mmu_ibvar = r_icache_vaddr_save.read();
1676	m_irsp.valid = true;
1677	m_irsp.error = true;
1678	r_vci_rsp_ins_error = false;
1679	r_icache_fsm = ICACHE_IDLE;
1680	}
1681	else if ( r_vci_rsp_fifo_icache.rok() ) // response available
1682	{
1683	r_icache_miss_word = 0;
1684	r_icache_fsm = ICACHE_MISS_DATA_UPDT;
1685	}
1686	break;
1687	}
1688	///////////////////////////
1689	case ICACHE_MISS_DATA_UPDT: // update the cache (one word per cycle)
1690	{
1691	if ( m_ireq.valid ) m_cost_ins_miss_frz++;
1692
1693	if ( r_vci_rsp_fifo_icache.rok() ) // response available
1694	{
1695
1696	#ifdef INSTRUMENTATION
1697	m_cpt_icache_data_write++;
1698	#endif
1699	r_icache.write( r_icache_miss_way.read(),
1700	r_icache_miss_set.read(),
1701	r_icache_miss_word.read(),
1702	r_vci_rsp_fifo_icache.read() );
1703	#if DEBUG_ICACHE
1704	if ( m_debug_icache_fsm )
1705	{
1706	std::cout << " <PROC " << name()
1707	<< " ICACHE_MISS_DATA_UPDT> Write one word:"
1708	<< " WDATA = " << std::hex << r_vci_rsp_fifo_icache.read()
1709	<< " WAY = " << r_icache_miss_way.read()
1710	<< " SET = " << r_icache_miss_set.read()
1711	<< " WORD = " << r_icache_miss_word.read() << std::endl;
1712	}
1713	#endif
1714	vci_rsp_fifo_icache_get = true;
1715	r_icache_miss_word = r_icache_miss_word.read() + 1;
1716
1717	if ( r_icache_miss_word.read() == m_icache_words-1 ) // last word
1718	{
1719	r_icache_fsm = ICACHE_MISS_DIR_UPDT;
1720	}
1721	}
1722	break;
1723	}
1724	//////////////////////////
1725	case ICACHE_MISS_DIR_UPDT: // Stalled if a victim line has been evicted,
1726	// and the cleanup ack has not been received,
1727	// as indicated by r_icache_miss_clack.
1728	// - If no matching coherence request (r_icache_miss_inval)
1729	// switch directory slot to VALID state.
1730	// - If matching coherence request, switch directory slot
1731	// to ZOMBI state, and send a cleanup request.
1732	{
1733	if ( m_ireq.valid ) m_cost_ins_miss_frz++;
1734
1735	// send cleanup victim request
1736	if ( r_icache_cleanup_victim_req.read() and not r_icache_cc_send_req.read() )
1737	{
1738	r_icache_cc_send_req = true;
1739	r_icache_cc_send_nline = r_icache_cleanup_victim_nline;
1740	r_icache_cc_send_way = r_icache_miss_way;
1741	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1742	r_icache_cleanup_victim_req = false;
1743	}
1744
1745	// coherence clack interrupt
1746	if ( r_icache_clack_req.read() )
1747	{
1748	r_icache_fsm = ICACHE_CC_CHECK;
1749	r_icache_fsm_save = r_icache_fsm.read();
1750	break;
1751	}
1752
1753	// coherence interrupt
1754	if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read() and not r_icache_cleanup_victim_req.read() )
1755	{
1756	r_icache_fsm = ICACHE_CC_CHECK;
1757	r_icache_fsm_save = r_icache_fsm.read();
1758	break;
1759	}
1760
1761	if ( not r_icache_miss_clack.read() ) // waiting cleanup acknowledge for victim line
1762	{
1763	if ( r_icache_miss_inval ) // Switch slot to ZOMBI state, and new cleanup
1764	{
1765	if ( not r_icache_cc_send_req.read() )
1766	{
1767	r_icache_miss_inval = false;
1768	// request cleanup
1769	r_icache_cc_send_req = true;
1770	r_icache_cc_send_nline = r_icache_vci_paddr.read() / (m_icache_words<<2);
1771	r_icache_cc_send_way = r_icache_miss_way.read();
1772	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1773
1774	#ifdef INSTRUMENTATION
1775	m_cpt_icache_dir_write++;
1776	#endif
1777	r_icache.write_dir( r_icache_vci_paddr.read(),
1778	r_icache_miss_way.read(),
1779	r_icache_miss_set.read(),
1780	CACHE_SLOT_STATE_ZOMBI );
1781	#if DEBUG_ICACHE
1782	if ( m_debug_icache_fsm )
1783	{
1784	std::cout << " <PROC " << name()
1785	<< " ICACHE_MISS_DIR_UPDT> Switch cache slot to ZOMBI state"
1786	<< " PADDR = " << std::hex << r_icache_vci_paddr.read()
1787	<< " WAY = " << std::dec << r_icache_miss_way.read()
1788	<< " SET = " << r_icache_miss_set.read() << std::endl;
1789	}
1790	#endif
1791	}
1792	else
1793	break;
1794	}
1795	else // Switch slot to VALID state
1796	{
1797
1798	#ifdef INSTRUMENTATION
1799	m_cpt_icache_dir_write++;
1800	#endif
1801	r_icache.write_dir( r_icache_vci_paddr.read(),
1802	r_icache_miss_way.read(),
1803	r_icache_miss_set.read(),
1804	CACHE_SLOT_STATE_VALID );
1805	#if DEBUG_ICACHE
1806	if ( m_debug_icache_fsm )
1807	{
1808	std::cout << " <PROC " << name()
1809	<< " ICACHE_MISS_DIR_UPDT> Switch cache slot to VALID state"
1810	<< " PADDR = " << std::hex << r_icache_vci_paddr.read()
1811	<< " WAY = " << std::dec << r_icache_miss_way.read()
1812	<< " SET = " << r_icache_miss_set.read() << std::endl;
1813	}
1814	#endif
1815	}
1816
1817	r_icache_fsm = ICACHE_IDLE;
1818	}
1819	break;
1820	}
1821	////////////////////
1822	case ICACHE_UNC_WAIT: // waiting a response to an uncacheable read from VCI_RSP FSM
1823	{
1824	// coherence clack interrupt
1825	if ( r_icache_clack_req.read() )
1826	{
1827	r_icache_fsm = ICACHE_CC_CHECK;
1828	r_icache_fsm_save = r_icache_fsm.read();
1829	break;
1830	}
1831
1832	// coherence interrupt
1833	if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read())
1834	{
1835	r_icache_fsm = ICACHE_CC_CHECK;
1836	r_icache_fsm_save = r_icache_fsm.read();
1837	break;
1838	}
1839
1840	if ( r_vci_rsp_ins_error.read() ) // bus error
1841	{
1842	r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS;
1843	r_mmu_ibvar = m_ireq.addr;
1844	r_vci_rsp_ins_error = false;
1845	m_irsp.valid = true;
1846	m_irsp.error = true;
1847	r_icache_fsm = ICACHE_IDLE;
1848	}
1849	else if (r_vci_rsp_fifo_icache.rok() ) // instruction available
1850	{
1851	vci_rsp_fifo_icache_get = true;
1852	r_icache_fsm = ICACHE_IDLE;
1853	if ( m_ireq.valid and
1854	(m_ireq.addr == r_icache_vaddr_save.read()) ) // request unmodified
1855	{
1856	m_irsp.valid = true;
1857	m_irsp.instruction = r_vci_rsp_fifo_icache.read();
1858	}
1859	}
1860	break;
1861	}
1862	/////////////////////
1863	case ICACHE_CC_CHECK: // This state is the entry point of a sub-fsm
1864	// handling coherence requests.
1865	// if there is a matching pending miss, it is
1866	// signaled in the r_icache_miss_inval flip-flop.
1867	// The return state is defined in r_icache_fsm_save.
1868	{
1869	paddr_t paddr = r_cc_receive_icache_nline.read() * m_icache_words * 4;
1870	paddr_t mask = ~((m_icache_words<<2)-1);
1871
1872	// CLACK handler
1873	// We switch the directory slot to EMPTY state
1874	// and reset r_icache_miss_clack if the cleanup ack
1875	// is matching a pending miss.
1876	if ( r_icache_clack_req.read() )
1877	{
1878
1879	if ( m_ireq.valid ) m_cost_ins_miss_frz++;
1880
1881	#ifdef INSTRUMENTATION
1882	m_cpt_icache_dir_write++;
1883	#endif
1884	r_icache.write_dir( 0,
1885	r_icache_clack_way.read(),
1886	r_icache_clack_set.read(),
1887	CACHE_SLOT_STATE_EMPTY);
1888
1889	if ( (r_icache_miss_set.read() == r_icache_clack_set.read()) and
1890	(r_icache_miss_way.read() == r_icache_clack_way.read()) )
1891	{
1892	r_icache_miss_clack = false;
1893	}
1894
1895	r_icache_clack_req = false;
1896
1897	// return to cc_save state
1898	r_icache_fsm = r_icache_fsm_save.read();
1899
1900	#if DEBUG_ICACHE
1901	if ( m_debug_icache_fsm )
1902	{
1903	std::cout << " <PROC " << name()
1904	<< " ICACHE_CC_CHECK> CC_TYPE_CLACK slot returns to empty state"
1905	<< " set = " << r_icache_clack_set.read()
1906	<< " / way = " << r_icache_clack_way.read() << std::endl;
1907	}
1908	#endif
1909
1910	break;
1911	}
1912
1913	assert ( not r_icache_cc_send_req.read() and "CC_SEND must be available in ICACHE_CC_CHECK");
1914
1915	// Match between MISS address and CC address
1916	if (r_cc_receive_icache_req.read() and
1917	((r_icache_fsm_save.read() == ICACHE_MISS_SELECT ) or
1918	(r_icache_fsm_save.read() == ICACHE_MISS_WAIT ) or
1919	(r_icache_fsm_save.read() == ICACHE_MISS_DIR_UPDT)) and
1920	((r_icache_vci_paddr.read() & mask) == (paddr & mask)) ) // matching
1921	{
1922	// signaling the matching
1923	r_icache_miss_inval = true;
1924
1925	// in case of update, go to CC_UPDT
1926	// JUST TO POP THE FIFO
1927	if (r_cc_receive_icache_type.read() == CC_TYPE_UPDT)
1928	{
1929	r_icache_fsm = ICACHE_CC_UPDT;
1930	r_icache_cc_word = r_cc_receive_word_idx.read();
1931
1932	// just pop the fifo , don't write in icache
1933	r_icache_cc_need_write = false;
1934	}
1935	// the request is dealt with
1936	else
1937	{
1938	r_cc_receive_icache_req = false;
1939	r_icache_fsm = r_icache_fsm_save.read();
1940	}
1941	#if DEBUG_ICACHE
1942	if ( m_debug_icache_fsm )
1943	{
1944	std::cout << " <PROC " << name()
1945	<< " ICACHE_CC_CHECK> Coherence request matching a pending miss:"
1946	<< " PADDR = " << std::hex << paddr << std::endl;
1947	}
1948	#endif
1949	}
1950
1951	// CC request handler
1952
1953	int state = 0;
1954	size_t way = 0;
1955	size_t set = 0;
1956	size_t word = 0;
1957
1958	#ifdef INSTRUMENTATION
1959	m_cpt_icache_dir_read++;
1960	#endif
1961	r_icache.read_dir(paddr,
1962	&state,
1963	&way,
1964	&set,
1965	&word);
1966
1967	r_icache_cc_way = way;
1968	r_icache_cc_set = set;
1969
1970	if ( state == CACHE_SLOT_STATE_VALID) // hit
1971	{
1972	// need to update the cache state
1973	if (r_cc_receive_icache_type.read() == CC_TYPE_UPDT) // hit update
1974	{
1975	r_icache_cc_need_write = true;
1976	r_icache_fsm = ICACHE_CC_UPDT;
1977	r_icache_cc_word = r_cc_receive_word_idx.read();
1978	}
1979	else if ( r_cc_receive_icache_type.read() == CC_TYPE_INVAL ) // hit inval
1980	{
1981	r_icache_fsm = ICACHE_CC_INVAL;
1982	}
1983	}
1984	else // miss
1985	{
1986	// multicast acknowledgement required in case of update
1987	if(r_cc_receive_icache_type.read() == CC_TYPE_UPDT)
1988	{
1989	r_icache_fsm = ICACHE_CC_UPDT;
1990	r_icache_cc_word = r_cc_receive_word_idx.read();
1991
1992	// just pop the fifo , don't write in icache
1993	r_icache_cc_need_write = false;
1994	}
1995	else // No response needed
1996	{
1997	r_cc_receive_icache_req = false;
1998	r_icache_fsm = r_icache_fsm_save.read();
1999	}
2000	}
2001	break;
2002	}
2003	/////////////////////
2004	case ICACHE_CC_INVAL: // hit inval : switch slot to ZOMBI state
2005	{
2006	assert (not r_icache_cc_send_req.read() &&
2007	"ERROR in ICACHE_CC_INVAL: the r_icache_cc_send_req "
2008	"must not be set");
2009
2010	#ifdef INSTRUMENTATION
2011	m_cpt_icache_dir_read++;
2012	#endif
2013
2014	// Switch slot state to ZOMBI and send CLEANUP command
2015	r_icache.write_dir( r_icache_cc_way.read(),
2016	r_icache_cc_set.read(),
2017	CACHE_SLOT_STATE_ZOMBI );
2018
2019	// coherence request completed
2020	r_icache_cc_send_req = true;
2021	r_icache_cc_send_nline = r_cc_receive_icache_nline.read();
2022	r_icache_cc_send_way = r_icache_cc_way.read();
2023	r_icache_cc_send_type = CC_TYPE_CLEANUP;
2024
2025	r_icache_fsm = r_icache_fsm_save.read();
2026
2027	#if DEBUG_ICACHE
2028	if ( m_debug_icache_fsm )
2029	{
2030	std::cout << " <PROC " << name()
2031	<< " ICACHE_CC_INVAL> slot returns to ZOMBI state"
2032	<< " set = " << r_icache_cc_set.read()
2033	<< " / way = " << r_icache_cc_way.read() << std::endl;
2034	}
2035	#endif
2036
2037	break;
2038	}
2039	////////////////////
2040	case ICACHE_CC_UPDT: // hit update : write one word per cycle
2041	{
2042	assert (not r_icache_cc_send_req.read() &&
2043	"ERROR in ICACHE_CC_UPDT: the r_icache_cc_send_req "
2044	"must not be set");
2045
2046	if ( not r_cc_receive_updt_fifo_be.rok() ) break;
2047
2048
2049	size_t word = r_icache_cc_word.read();
2050	size_t way = r_icache_cc_way.read();
2051	size_t set = r_icache_cc_set.read();
2052
2053	if (r_icache_cc_need_write.read())
2054	{
2055	r_icache.write( way,
2056	set,
2057	word,
2058	r_cc_receive_updt_fifo_data.read(),
2059	r_cc_receive_updt_fifo_be.read() );
2060
2061	r_icache_cc_word = word+1;
2062
2063	#ifdef INSTRUMENTATION
2064	m_cpt_icache_data_write++;
2065	#endif
2066
2067	#if DEBUG_ICACHE
2068	if ( m_debug_icache_fsm )
2069	{
2070	std::cout << " <PROC " << name()
2071	<< " ICACHE_CC_UPDT> Write one word "
2072	<< " set = " << r_icache_cc_set.read()
2073	<< " / way = " << r_icache_cc_way.read()
2074	<< " / word = " << r_icache_cc_word.read() << std::endl;
2075	}
2076	#endif
2077	}
2078
2079	if ( r_cc_receive_updt_fifo_eop.read() ) // last word
2080	{
2081	// no need to write in the cache anymore
2082	r_icache_cc_need_write = false;
2083
2084	// coherence request completed
2085	r_cc_receive_icache_req = false;
2086
2087	// request multicast acknowledgement
2088	r_icache_cc_send_req = true;
2089	r_icache_cc_send_nline = r_cc_receive_icache_nline.read();
2090	r_icache_cc_send_updt_tab_idx = r_cc_receive_icache_updt_tab_idx.read();
2091	r_icache_cc_send_type = CC_TYPE_MULTI_ACK;
2092
2093	r_icache_fsm = r_icache_fsm_save.read();
2094	}
2095	//consume fifo if not eop
2096	cc_receive_updt_fifo_get = true;
2097
2098	break;
2099	}
2100
2101	} // end switch r_icache_fsm
2102
2103	////////////////////////////////////////////////////////////////////////////////////
2104	// DCACHE FSM
2105	//
2106	// 1/ Coherence operations
2107	// They are handled as interrupts generated by the CC_RECEIVE FSM.
2108	// - There is a coherence request when r_tgt_dcache_req is set.
2109	// They are taken in IDLE, MISS_WAIT, MISS_DIR_UPDT, UNC_WAIT, LL_WAIT
2110	// and SC_WAIT states.
2111	// - There is a cleanup acknowledge request when r_cleanup_dcache_req is set.
2112	// They are taken in IDLE, MISS_SELECT, MISS_CLEAN, MISS_WAIT, MISS_DATA_UPDT,
2113	// MISS_DIR_UPDT, UNC_WAIT, LL_WAIT, SC_WAIT states.
2114	// - For both types of requests, actions associated to the pre-empted state
2115	// are not executed. The DCACHE FSM goes to the proper sub-FSM (CC_CHECK
2116	// or CC_CLACK) to execute the requested coherence operation, and returns
2117	// to the pre-empted state.
2118	//
2119	// 2/ TLB miss
2120	// The page tables are generally cacheable.
2121	// In case of miss in itlb or dtlb, the tlb miss is handled by a dedicated
2122	// sub-fsm (DCACHE_TLB_MISS state), that handle possible miss in DCACHE,
2123	// this sub-fsm implement the table-walk...
2124	//
2125	// 3/ processor requests
2126	// Processor requests are taken in IDLE state only.
2127	// The IDLE state implements a two stages pipe-line to handle write bursts:
2128	// - Both DTLB and DCACHE are accessed in stage P0 (if processor request valid).
2129	// - The registration in wbuf and the dcache update is done in stage P1
2130	// (if the processor request is a write).
2131	// The two r_dcache_wbuf_req and r_dcache_updt_req flip-flops define
2132	// the operations that must be done in P1 stage, and the access type
2133	// (read or write) to the DATA part of DCACHE depends on r_dcache_updt_req.
2134	// READ requests are delayed if a cache update is requested.
2135	// WRITE or SC requests can require a PTE Dirty bit update (in memory),
2136	// that is done (before handling the processor request) by a dedicated sub-fsm.
2137	// If a PTE is modified, both the itlb and dtlb are selectively, but sequencially
2138	// cleared by a dedicated sub_fsm (DCACHE_INVAL_TLB_SCAN state).
2139	//
2140	// 4/ Atomic instructions LL/SC
2141	// The LL/SC address are non cacheable (systematic access to memory).
2142	// The llsc buffer contains a registration for an active LL/SC operation
2143	// (with an address, a registration key, an aging counter and a valid bit).
2144	// - LL requests from the processor are transmitted as a one flit VCI command
2145	// (CMD_LOCKED_READ as CMD, and TYPE_LL as PKTID value). PLEN must
2146	// be 8 as the response is 2 flits long (data and registration key)
2147	// - SC requests from the processor are systematically transmitted to the
2148	// memory cache as 2 flits VCI command (CMD_STORE_COND as CMD, and TYPE_SC
2149	// as PKTID value). The first flit contains the registration key, the second
2150	// flit contains the data to write in case of success.
2151	// The cache is not updated, as this is done in case of success by the
2152	// coherence transaction.
2153	//
2154	// 5/ Non cacheable access:
2155	// This component implement a strong order between non cacheable access
2156	// (read or write) : A new non cacheable VCI transaction starts only when
2157	// the previous non cacheable transaction is completed. After send the VCI
2158	// transaction, the DCACHE FSM wait for the respone in the DCACHE_UNC_WAIT state.
2159	// So the processor is blocked until the respone arrives in CACHE L1.
2160	//
2161	// 6/ Error handling:
2162	// When the MMU is not activated, Read Bus Errors are synchronous events,
2163	// Some Write Bus Errors are synchronous events when the request is a non cacheable access
2164	// but some Write Bus Errors are asynchronous events when the request is cacheable access
2165	// (processor is not frozen).
2166	// - If a Read Bus Error or a Non Cacheable Write Bus Error is detected, the VCI_RSP FSM sets the
2167	// r_vci_rsp_data_error flip-flop, without writing any data in the
2168	// r_vci_rsp_fifo_dcache FIFO, and the synchronous error is signaled
2169	// by the DCACHE FSM.
2170	// - If a Cacheable Write Bus Error is detected, the VCI_RSP_FSM signals
2171	// the asynchronous error using the setWriteBerr() method.
2172	// When the MMU is activated bus error are rare events, as the MMU
2173	// checks the physical address before the VCI transaction starts.
2174	////////////////////////////////////////////////////////////////////////////////////////
2175
2176	// default value for m_drsp
2177	m_drsp.valid = false;
2178	m_drsp.error = false;
2179	m_drsp.rdata = 0;
2180
2181	switch ( r_dcache_fsm.read() )
2182	{
2183	case DCACHE_IDLE: // There are 10 conditions to exit the IDLE state :
2184	// 1) ITLB/DTLB inval request (update) => DCACHE_INVAL_TLB_SCAN
2185	// 2) Coherence request (TGT FSM) => DCACHE_CC_CHECK
2186	// 3) ITLB miss request (ICACHE FSM) => DCACHE_TLB_MISS
2187	// 4) XTN request (processor) => DCACHE_XTN_*
2188	// 5) DTLB miss (processor) => DCACHE_TLB_MISS
2189	// 6) Dirty bit update (processor) => DCACHE_DIRTY_GET_PTE
2190	// 7) Cacheable read miss (processor) => DCACHE_MISS_SELECT
2191	// 8) Uncacheable read (processor) => DCACHE_UNC_WAIT
2192	// 9) LL access (processor) => DCACHE_LL_WAIT
2193	// 10) SC access (processor) => DCACHE_SC_WAIT
2194	//
2195	// There is a fixed priority to handle requests to DCACHE:
2196	// 1/ the ITLB/DTLB invalidate requests
2197	// 2/ the coherence requests,
2198	// 3/ the processor requests (including DTLB miss),
2199	// 4/ the ITLB miss requests,
2200	// The address space processor request are handled as follows:
2201	// - WRITE request is blocked if the Dirty bit mus be set.
2202	// If DTLB hit, the P1 stage is activated (writes WBUF, and
2203	// updates DCACHE if DCACHE hit) & processor request acknowledged.
2204	// - READ request generate a simultaneouss access to DCACHE.DATA
2205	// and DCACHE.DIR, but is delayed if DCACHE update required.
2206	//
2207	// There is 4 configurations defining the access type to
2208	// DTLB, DCACHE.DATA, and DCACHE.DIR, depending on the
2209	// dreq.valid (dreq) and r_dcache_updt_req (updt) signals:
2210	// dreq / updt / DTLB / DCACHE.DIR / DCACHE.DATA /
2211	// 0 / 0 / NOP / NOP / NOP /
2212	// 0 / 1 / NOP / NOP / WRITE /
2213	// 1 / 0 / READ / READ / NOP /
2214	// 1 / 1 / READ / READ / WRITE /
2215	// Those two registers are set at each cycle from the 3 signals
2216	// updt_request, wbuf_request, wbuf_write_miss.
2217	{
2218	paddr_t paddr; // physical address
2219	pte_info_t tlb_flags;
2220	size_t tlb_way;
2221	size_t tlb_set;
2222	paddr_t tlb_nline = 0;
2223	size_t cache_way;
2224	size_t cache_set;
2225	size_t cache_word;
2226	uint32_t cache_rdata = 0;
2227	bool tlb_hit = false;
2228	int cache_state = CACHE_SLOT_STATE_EMPTY;
2229
2230	bool tlb_inval_required = false; // request TLB inval after cache update
2231	bool wbuf_write_miss = false; // miss a WBUF write request
2232	bool updt_request = false; // request DCACHE update in P1 stage
2233	bool wbuf_request = false; // request WBUF write in P1 stage
2234
2235	// physical address computation : systematic DTLB access if activated)
2236	if ( m_dreq.valid )
2237	{
2238	if ( r_mmu_mode.read() & DATA_TLB_MASK ) // DTLB activated
2239	{
2240	tlb_hit = r_dtlb.translate( m_dreq.addr,
2241	&paddr,
2242	&tlb_flags,
2243	&tlb_nline,
2244	&tlb_way,
2245	&tlb_set );
2246	#ifdef INSTRUMENTATION
2247	m_cpt_dtlb_read++;
2248	#endif
2249	}
2250	else // identity mapping
2251	{
2252	paddr = (paddr_t)m_dreq.addr;
2253	// we take into account the paddr extension
2254	if (vci_param::N > 32)
2255	paddr = paddr \| ((paddr_t)(r_dcache_paddr_ext.read()) << 32);
2256	}
2257	} // end physical address computation
2258
2259	// systematic DCACHE access depending on r_dcache_updt_req (if activated)
2260	if ( r_mmu_mode.read() & DATA_CACHE_MASK)
2261	{
2262	if ( m_dreq.valid and r_dcache_updt_req.read() ) // read DIR and write DATA
2263	{
2264	r_dcache.read_dir( paddr,
2265	&cache_state,
2266	&cache_way,
2267	&cache_set,
2268	&cache_word );
2269
2270	r_dcache.write( r_dcache_save_cache_way.read(),
2271	r_dcache_save_cache_set.read(),
2272	r_dcache_save_cache_word.read(),
2273	r_dcache_save_wdata.read(),
2274	r_dcache_save_be.read() );
2275	#ifdef INSTRUMENTATION
2276	m_cpt_dcache_dir_read++;
2277	m_cpt_dcache_data_write++;
2278	#endif
2279	}
2280	else if ( m_dreq.valid and not r_dcache_updt_req.read() ) // read DIR and DATA
2281	{
2282	r_dcache.read( paddr,
2283	&cache_rdata,
2284	&cache_way,
2285	&cache_set,
2286	&cache_word,
2287	&cache_state );
2288
2289	#ifdef INSTRUMENTATION
2290	m_cpt_dcache_dir_read++;
2291	m_cpt_dcache_data_read++;
2292	#endif
2293	}
2294	else if ( not m_dreq.valid and r_dcache_updt_req.read() ) // write DATA
2295	{
2296	r_dcache.write( r_dcache_save_cache_way.read(),
2297	r_dcache_save_cache_set.read(),
2298	r_dcache_save_cache_word.read(),
2299	r_dcache_save_wdata.read(),
2300	r_dcache_save_be.read() );
2301	#ifdef INSTRUMENTATION
2302	m_cpt_dcache_data_write++;
2303	#endif
2304	}
2305	} // end dcache access
2306
2307	// DCACHE update in P1 stage can require ITLB / DTLB inval or flush
2308	if ( r_dcache_updt_req.read() )
2309	{
2310	size_t way = r_dcache_save_cache_way.read();
2311	size_t set = r_dcache_save_cache_set.read();
2312
2313	if ( r_dcache_in_tlb[way*m_dcache_sets+set] )
2314	{
2315	tlb_inval_required = true;
2316	r_dcache_tlb_inval_set = 0;
2317	r_dcache_tlb_inval_line = r_dcache_save_paddr.read()>>
2318	(uint32_log2(m_dcache_words<<2));
2319	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
2320	}
2321	else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] )
2322	{
2323	r_itlb.reset();
2324	r_dtlb.reset();
2325	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
2326	}
2327
2328	#if DEBUG_DCACHE
2329	if ( m_debug_dcache_fsm )
2330	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
2331	<< " Cache update in P1 stage" << std::dec
2332	<< " / WAY = " << r_dcache_save_cache_way.read()
2333	<< " / SET = " << r_dcache_save_cache_set.read()
2334	<< " / WORD = " << r_dcache_save_cache_word.read() << std::hex
2335	<< " / WDATA = " << r_dcache_save_wdata.read()
2336	<< " / BE = " << r_dcache_save_be.read() << std::endl;
2337	#endif
2338	} // end test TLB inval
2339
2340	// Try WBUF update in P1 stage
2341	// Miss if the write request is non cacheable, and there is a pending
2342	// non cacheable write, or if the write buffer is full.
2343	if ( r_dcache_wbuf_req.read() )
2344	{
2345	bool wok = r_wbuf.write( r_dcache_save_paddr.read(),
2346	r_dcache_save_be.read(),
2347	r_dcache_save_wdata.read(),
2348	true);
2349	#ifdef INSTRUMENTATION
2350	m_cpt_wbuf_write++;
2351	#endif
2352	if ( not wok ) // miss if write buffer full
2353	{
2354	wbuf_write_miss = true;
2355	}
2356	} // end WBUF update
2357
2358	// Computing the response to processor,
2359	// and the next value for r_dcache_fsm
2360
2361	// itlb/dtlb invalidation self-request
2362	if ( tlb_inval_required )
2363	{
2364	r_dcache_fsm_scan_save = r_dcache_fsm.read();
2365	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
2366	}
2367
2368	// coherence clack request (from DSPIN CLACK)
2369	else if ( r_dcache_clack_req.read() )
2370	{
2371	r_dcache_fsm = DCACHE_CC_CHECK;
2372	r_dcache_fsm_cc_save = r_dcache_fsm.read();
2373	}
2374	// coherence request (from CC_RECEIVE FSM)
2375	else if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
2376	{
2377	r_dcache_fsm = DCACHE_CC_CHECK;
2378	r_dcache_fsm_cc_save = r_dcache_fsm.read();
2379	}
2380
2381	// processor request (READ, WRITE, LL, SC, XTN_READ, XTN_WRITE)
2382	// we don't take the processor request, and registers
2383	// are frozen in case of wbuf_write_miss
2384	else if ( m_dreq.valid and not wbuf_write_miss )
2385	{
2386	// register processor request and DCACHE response
2387	r_dcache_save_vaddr = m_dreq.addr;
2388	r_dcache_save_be = m_dreq.be;
2389	r_dcache_save_wdata = m_dreq.wdata;
2390	r_dcache_save_paddr = paddr;
2391	r_dcache_save_cache_way = cache_way;
2392	r_dcache_save_cache_set = cache_set;
2393	r_dcache_save_cache_word = cache_word;
2394
2395	// READ XTN requests from processor
2396	// They are executed in this DCACHE_IDLE state.
2397	// The processor must not be in user mode
2398	if (m_dreq.type == iss_t::XTN_READ)
2399	{
2400	int xtn_opcode = (int)m_dreq.addr/4;
2401
2402	// checking processor mode:
2403	if (m_dreq.mode == iss_t::MODE_USER)
2404	{
2405	r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION;
2406	r_mmu_dbvar = m_dreq.addr;
2407	m_drsp.valid = true;
2408	m_drsp.error = true;
2409	m_drsp.rdata = 0;
2410	r_dcache_fsm = DCACHE_IDLE;
2411	}
2412	else
2413	{
2414	switch( xtn_opcode )
2415	{
2416	case iss_t::XTN_INS_ERROR_TYPE:
2417	m_drsp.rdata = r_mmu_ietr.read();
2418	m_drsp.valid = true;
2419	m_drsp.error = false;
2420	break;
2421
2422	case iss_t::XTN_DATA_ERROR_TYPE:
2423	m_drsp.rdata = r_mmu_detr.read();
2424	m_drsp.valid = true;
2425	m_drsp.error = false;
2426	break;
2427
2428	case iss_t::XTN_INS_BAD_VADDR:
2429	m_drsp.rdata = r_mmu_ibvar.read();
2430	m_drsp.valid = true;
2431	m_drsp.error = false;
2432	break;
2433
2434	case iss_t::XTN_DATA_BAD_VADDR:
2435	m_drsp.rdata = r_mmu_dbvar.read();
2436	m_drsp.valid = true;
2437	m_drsp.error = false;
2438	break;
2439
2440	case iss_t::XTN_PTPR:
2441	m_drsp.rdata = r_mmu_ptpr.read();
2442	m_drsp.valid = true;
2443	m_drsp.error = false;
2444	break;
2445
2446	case iss_t::XTN_TLB_MODE:
2447	m_drsp.rdata = r_mmu_mode.read();
2448	m_drsp.valid = true;
2449	m_drsp.error = false;
2450	break;
2451
2452	case iss_t::XTN_MMU_PARAMS:
2453	m_drsp.rdata = r_mmu_params;
2454	m_drsp.valid = true;
2455	m_drsp.error = false;
2456	break;
2457
2458	case iss_t::XTN_MMU_RELEASE:
2459	m_drsp.rdata = r_mmu_release;
2460	m_drsp.valid = true;
2461	m_drsp.error = false;
2462	break;
2463
2464	case iss_t::XTN_MMU_WORD_LO:
2465	m_drsp.rdata = r_mmu_word_lo.read();
2466	m_drsp.valid = true;
2467	m_drsp.error = false;
2468	break;
2469
2470	case iss_t::XTN_MMU_WORD_HI:
2471	m_drsp.rdata = r_mmu_word_hi.read();
2472	m_drsp.valid = true;
2473	m_drsp.error = false;
2474	break;
2475
2476	case iss_t::XTN_DATA_PADDR_EXT:
2477	m_drsp.rdata = r_dcache_paddr_ext.read();
2478	m_drsp.valid = true;
2479	m_drsp.error = false;
2480	break;
2481
2482	default:
2483	r_mmu_detr = MMU_READ_UNDEFINED_XTN;
2484	r_mmu_dbvar = m_dreq.addr;
2485	m_drsp.valid = true;
2486	m_drsp.error = true;
2487	m_drsp.rdata = 0;
2488	break;
2489	} // end switch xtn_opcode
2490	} // end else
2491	} // end if XTN_READ
2492
2493	// Handling WRITE XTN requests from processor.
2494	// They are not executed in this DCACHE_IDLE state
2495	// if they require access to the caches or the TLBs
2496	// that are already accessed.
2497	// Caches can be invalidated or flushed in user mode,
2498	// and the sync instruction can be executed in user mode
2499	else if (m_dreq.type == iss_t::XTN_WRITE)
2500	{
2501	int xtn_opcode = (int)m_dreq.addr/4;
2502	r_dcache_xtn_opcode = xtn_opcode;
2503
2504	// checking processor mode:
2505	if ( (m_dreq.mode == iss_t::MODE_USER) &&
2506	(xtn_opcode != iss_t::XTN_SYNC) &&
2507	(xtn_opcode != iss_t::XTN_DCACHE_INVAL) &&
2508	(xtn_opcode != iss_t::XTN_DCACHE_FLUSH) &&
2509	(xtn_opcode != iss_t::XTN_ICACHE_INVAL) &&
2510	(xtn_opcode != iss_t::XTN_ICACHE_FLUSH) )
2511	{
2512	r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION;
2513	r_mmu_dbvar = m_dreq.addr;
2514	m_drsp.valid = true;
2515	m_drsp.error = true;
2516	m_drsp.rdata = 0;
2517	r_dcache_fsm = DCACHE_IDLE;
2518	}
2519	else
2520	{
2521	switch( xtn_opcode )
2522	{
2523	case iss_t::XTN_PTPR: // itlb & dtlb must be flushed
2524	r_dcache_xtn_req = true;
2525	r_dcache_fsm = DCACHE_XTN_SWITCH;
2526	break;
2527
2528	case iss_t::XTN_TLB_MODE: // no cache or tlb access
2529	r_mmu_mode = m_dreq.wdata;
2530	m_drsp.valid = true;
2531	r_dcache_fsm = DCACHE_IDLE;
2532	break;
2533
2534	case iss_t::XTN_DTLB_INVAL: // dtlb access
2535	r_dcache_fsm = DCACHE_XTN_DT_INVAL;
2536	break;
2537
2538	case iss_t::XTN_ITLB_INVAL: // itlb access
2539	r_dcache_xtn_req = true;
2540	r_dcache_fsm = DCACHE_XTN_IT_INVAL;
2541	break;
2542
2543	case iss_t::XTN_DCACHE_INVAL: // dcache, dtlb & itlb access
2544	r_dcache_fsm = DCACHE_XTN_DC_INVAL_VA;
2545	break;
2546
2547	case iss_t::XTN_MMU_DCACHE_PA_INV: // dcache, dtlb & itlb access
2548	r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA;
2549	if (sizeof(paddr_t) <= 32)
2550	{
2551	assert(r_mmu_word_hi.read() == 0 &&
2552	"high bits should be 0 for 32bit paddr");
2553	r_dcache_save_paddr = (paddr_t)r_mmu_word_lo.read();
2554	}
2555	else
2556	{
2557	r_dcache_save_paddr = (paddr_t)r_mmu_word_hi.read() << 32 \|
2558	(paddr_t)r_mmu_word_lo.read();
2559	}
2560	break;
2561
2562	case iss_t::XTN_DCACHE_FLUSH: // itlb and dtlb must be reset
2563	r_dcache_flush_count = 0;
2564	r_dcache_fsm = DCACHE_XTN_DC_FLUSH;
2565	break;
2566
2567	case iss_t::XTN_ICACHE_INVAL: // icache and itlb access
2568	r_dcache_xtn_req = true;
2569	r_dcache_fsm = DCACHE_XTN_IC_INVAL_VA;
2570	break;
2571
2572	case iss_t::XTN_MMU_ICACHE_PA_INV: // icache access
2573	r_dcache_xtn_req = true;
2574	r_dcache_fsm = DCACHE_XTN_IC_INVAL_PA;
2575	break;
2576
2577	case iss_t::XTN_ICACHE_FLUSH: // icache access
2578	r_dcache_xtn_req = true;
2579	r_dcache_fsm = DCACHE_XTN_IC_FLUSH;
2580	break;
2581
2582	case iss_t::XTN_SYNC: // wait until write buffer empty
2583	r_dcache_fsm = DCACHE_XTN_SYNC;
2584	break;
2585
2586	case iss_t::XTN_MMU_WORD_LO: // no cache or tlb access
2587	r_mmu_word_lo = m_dreq.wdata;
2588	m_drsp.valid = true;
2589	r_dcache_fsm = DCACHE_IDLE;
2590	break;
2591
2592	case iss_t::XTN_MMU_WORD_HI: // no cache or tlb access
2593	r_mmu_word_hi = m_dreq.wdata;
2594	m_drsp.valid = true;
2595	r_dcache_fsm = DCACHE_IDLE;
2596	break;
2597
2598	case iss_t::XTN_MMU_LL_RESET: // no cache or tlb access
2599	r_dcache_llsc_valid = false;
2600	m_drsp.valid = true;
2601	r_dcache_fsm = DCACHE_IDLE;
2602	break;
2603
2604	case iss_t::XTN_DATA_PADDR_EXT: // no cache or tlb access
2605	r_dcache_paddr_ext = m_dreq.wdata;
2606	m_drsp.valid = true;
2607	r_dcache_fsm = DCACHE_IDLE;
2608	break;
2609
2610	case iss_t::XTN_ICACHE_PREFETCH: // not implemented : no action
2611	case iss_t::XTN_DCACHE_PREFETCH: // not implemented : no action
2612	m_drsp.valid = true;
2613	r_dcache_fsm = DCACHE_IDLE;
2614	break;
2615
2616	case iss_t::XTN_DEBUG_MASK: // debug mask
2617	m_debug_dcache_fsm = ((m_dreq.wdata & 0x1) != 0);
2618	m_debug_icache_fsm = ((m_dreq.wdata & 0x2) != 0);
2619	m_debug_cmd_fsm = ((m_dreq.wdata & 0x4) != 0);
2620	m_drsp.valid = true;
2621	r_dcache_fsm = DCACHE_IDLE;
2622	break;
2623
2624	default:
2625	r_mmu_detr = MMU_WRITE_UNDEFINED_XTN;
2626	r_mmu_dbvar = m_dreq.addr;
2627	m_drsp.valid = true;
2628	m_drsp.error = true;
2629	r_dcache_fsm = DCACHE_IDLE;
2630	break;
2631	} // end switch xtn_opcode
2632	} // end else
2633	} // end if XTN_WRITE
2634
2635	// Handling processor requests to address space (READ/WRITE/LL/SC)
2636	// The dtlb and dcache can be activated or not.
2637	// We compute the cacheability, and check processor request validity:
2638	// - If DTLB not activated : cacheability is defined by the segment table,
2639	// and there is no access rights checking.
2640	// - If DTLB activated : cacheability is defined by the C bit in the PTE,
2641	// and the U & W bits of the PTE are checked, as well as the DTLB hit.
2642	// Jumps to the TLB_MISS sub-fsm in case of dtlb miss.
2643	else
2644	{
2645	bool valid_req;
2646	bool cacheable;
2647
2648	if ( not (r_mmu_mode.read() & DATA_TLB_MASK) ) // dtlb not activated
2649	{
2650	valid_req = true;
2651
2652	if ( not (r_mmu_mode.read() & DATA_CACHE_MASK) ) cacheable = false;
2653	else cacheable = m_cacheability_table[(uint64_t)m_dreq.addr];
2654	}
2655	else // dtlb activated
2656	{
2657	if ( tlb_hit ) // tlb hit
2658	{
2659	// cacheability
2660	if ( not (r_mmu_mode.read() & DATA_CACHE_MASK) ) cacheable = false;
2661	else cacheable = tlb_flags.c;
2662
2663	// access rights checking
2664	if ( not tlb_flags.u and (m_dreq.mode == iss_t::MODE_USER))
2665	{
2666	if ( (m_dreq.type == iss_t::DATA_READ) or
2667	(m_dreq.type == iss_t::DATA_LL) )
2668	{
2669	r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION;
2670	}
2671	else
2672	{
2673	r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION;
2674	}
2675	valid_req = false;
2676	r_mmu_dbvar = m_dreq.addr;
2677	m_drsp.valid = true;
2678	m_drsp.error = true;
2679	m_drsp.rdata = 0;
2680	#if DEBUG_DCACHE
2681	if ( m_debug_dcache_fsm )
2682	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
2683	<< " HIT in dtlb, but privilege violation" << std::endl;
2684	#endif
2685	}
2686	else if ( not tlb_flags.w and
2687	((m_dreq.type == iss_t::DATA_WRITE) or
2688	(m_dreq.type == iss_t::DATA_SC)) )
2689	{
2690	r_mmu_detr = MMU_WRITE_ACCES_VIOLATION;
2691	valid_req = false;
2692	r_mmu_dbvar = m_dreq.addr;
2693	m_drsp.valid = true;
2694	m_drsp.error = true;
2695	m_drsp.rdata = 0;
2696	#if DEBUG_DCACHE
2697	if ( m_debug_dcache_fsm )
2698	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
2699	<< " HIT in dtlb, but writable violation" << std::endl;
2700	#endif
2701	}
2702	else
2703	{
2704	valid_req = true;
2705	}
2706	}
2707	else // tlb miss
2708	{
2709	valid_req = false;
2710	r_dcache_tlb_vaddr = m_dreq.addr;
2711	r_dcache_tlb_ins = false;
2712	r_dcache_fsm = DCACHE_TLB_MISS;
2713	}
2714	} // end DTLB activated
2715
2716	if ( valid_req ) // processor request is valid (after MMU check)
2717	{
2718	// READ request
2719	// The read requests are taken only if there is no cache update.
2720	// We request a VCI transaction to CMD FSM if miss or uncachable
2721
2722	if ( ((m_dreq.type == iss_t::DATA_READ))
2723	and not r_dcache_updt_req.read() )
2724	{
2725	if ( cacheable ) // cacheable read
2726	{
2727	if ( cache_state == CACHE_SLOT_STATE_EMPTY ) // cache miss
2728	{
2729	#ifdef INSTRUMENTATION
2730	m_cpt_dcache_miss++;
2731	#endif
2732	// request a VCI DMISS transaction
2733	r_dcache_vci_paddr = paddr;
2734	r_dcache_vci_miss_req = true;
2735	r_dcache_miss_type = PROC_MISS;
2736	r_dcache_fsm = DCACHE_MISS_SELECT;
2737	#if DEBUG_DCACHE
2738	if ( m_debug_dcache_fsm )
2739	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
2740	<< " READ MISS in dcache"
2741	<< " / PADDR = " << std::hex << paddr << std::endl;
2742	#endif
2743	}
2744	else if (cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup
2745	{
2746	// stalled until cleanup is acknowledged
2747	r_dcache_fsm = DCACHE_IDLE;
2748	#if DEBUG_DCACHE
2749	if ( m_debug_dcache_fsm )
2750	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
2751	<< " Pending cleanup, stalled until cleanup acknowledge"
2752	<< " / PADDR = " << std::hex << paddr << std::endl;
2753	#endif
2754	}
2755	else // cache hit
2756	{
2757	#ifdef INSTRUMENTATION
2758	m_cpt_data_read++;
2759	#endif
2760	// returns data to processor
2761	m_drsp.valid = true;
2762	m_drsp.error = false;
2763	m_drsp.rdata = cache_rdata;
2764	#if DEBUG_DCACHE
2765	if ( m_debug_dcache_fsm )
2766	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
2767	<< " READ HIT in dcache"
2768	<< " : PADDR = " << std::hex << paddr
2769	<< " / DATA = " << std::hex << cache_rdata << std::endl;
2770	#endif
2771	}
2772	}
2773	else // uncacheable read
2774	{
2775	r_dcache_vci_paddr = paddr;
2776	r_dcache_vci_unc_be = m_dreq.be;
2777	r_dcache_vci_unc_write = false;
2778	r_dcache_vci_unc_req = true;
2779	r_dcache_fsm = DCACHE_UNC_WAIT;
2780	#if DEBUG_DCACHE
2781	if ( m_debug_dcache_fsm )
2782	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
2783	<< " READ UNCACHEABLE in dcache"
2784	<< " / PADDR = " << std::hex << paddr << std::endl;
2785	#endif
2786	}
2787	} // end READ
2788
2789	// LL request (non cachable)
2790	// We request a VCI LL transaction to CMD FSM and register
2791	// the LL/SC operation in llsc buffer.
2792	else if (m_dreq.type == iss_t::DATA_LL)
2793	{
2794	// register paddr in LLSC buffer
2795	r_dcache_llsc_paddr = paddr;
2796	r_dcache_llsc_count = LLSC_TIMEOUT;
2797	r_dcache_llsc_valid = true;
2798
2799	// request an LL VCI transaction and go to DCACHE_LL_WAIT state
2800	r_dcache_vci_ll_req = true;
2801	r_dcache_vci_paddr = paddr;
2802	r_dcache_ll_rsp_count = 0;
2803	r_dcache_fsm = DCACHE_LL_WAIT;
2804
2805	}// end LL
2806
2807	// WRITE request:
2808	// If the TLB is activated and the PTE Dirty bit is not set, we stall
2809	// the processor and set the Dirty bit before handling the write request,
2810	// going to the DCACHE_DIRTY_GT_PTE state.
2811	// If we don't need to set the Dirty bit, we can acknowledge
2812	// the processor request, as the write arguments (including the
2813	// physical address) are registered in r_dcache_save registers,
2814	// and the write will be done in the P1 pipeline stage.
2815	else if ( m_dreq.type == iss_t::DATA_WRITE )
2816	{
2817	if ( (r_mmu_mode.read() & DATA_TLB_MASK )
2818	and not tlb_flags.d ) // Dirty bit must be set
2819	{
2820	// The PTE physical address is obtained from the nline value (dtlb),
2821	// and from the virtual address (word index)
2822	if ( tlb_flags.b ) // PTE1
2823	{
2824	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2825	(paddr_t)((m_dreq.addr>>19) & 0x3c);
2826	}
2827	else // PTE2
2828	{
2829	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2830	(paddr_t)((m_dreq.addr>>9) & 0x38);
2831	}
2832	r_dcache_fsm = DCACHE_DIRTY_GET_PTE;
2833	}
2834	else // Write request accepted
2835	{
2836	#ifdef INSTRUMENTATION
2837	m_cpt_data_write++;
2838	#endif
2839	// cleaning llsc buffer if address matching
2840	if ( paddr == r_dcache_llsc_paddr.read() )
2841	r_dcache_llsc_valid = false;
2842
2843	if (not cacheable)
2844	{
2845	r_dcache_vci_paddr = paddr;
2846	r_dcache_vci_wdata = m_dreq.wdata;
2847	r_dcache_vci_unc_write = true;
2848	r_dcache_vci_unc_be = m_dreq.be;
2849	r_dcache_vci_unc_req = true;
2850	r_dcache_fsm = DCACHE_UNC_WAIT;
2851	}
2852	else
2853	{
2854	// response to processor
2855	m_drsp.valid = true;
2856	// activating P1 stage
2857	wbuf_request = true;
2858	updt_request = (cache_state == CACHE_SLOT_STATE_VALID);
2859	}
2860	}
2861	} // end WRITE
2862
2863	// SC request:
2864	// If the TLB is activated and the PTE Dirty bit is not set, we stall
2865	// the processor and set the Dirty bit before handling the write request,
2866	// going to the DCACHE_DIRTY_GT_PTE state.
2867	// If we don't need to set the Dirty bit, we test the llsc buffer:
2868	// If failure, we send a negative response to processor.
2869	// If success, we request a SC transaction to CMD FSM and go
2870	// to DCACHE_SC_WAIT state.
2871	// We don't check a possible write hit in dcache, as the cache update
2872	// is done by the coherence transaction induced by the SC...
2873	else if ( m_dreq.type == iss_t::DATA_SC )
2874	{
2875	if ( (r_mmu_mode.read() & DATA_TLB_MASK )
2876	and not tlb_flags.d ) // Dirty bit must be set
2877	{
2878	// The PTE physical address is obtained from the nline value (dtlb),
2879	// and the word index (virtual address)
2880	if ( tlb_flags.b ) // PTE1
2881	{
2882	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2883	(paddr_t)((m_dreq.addr>>19) & 0x3c);
2884	}
2885	else // PTE2
2886	{
2887	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2888	(paddr_t)((m_dreq.addr>>9) & 0x38);
2889	}
2890	r_dcache_fsm = DCACHE_DIRTY_GET_PTE;
2891	m_drsp.valid = false;
2892	m_drsp.error = false;
2893	m_drsp.rdata = 0;
2894	}
2895	else // SC request accepted
2896	{
2897	#ifdef INSTRUMENTATION
2898	m_cpt_data_sc++;
2899	#endif
2900	// checking local success
2901	if( r_dcache_llsc_valid.read() and
2902	(r_dcache_llsc_paddr.read() == paddr) ) // local success
2903	{
2904	// request an SC CMD and go to DCACHE_SC_WAIT state
2905	r_dcache_vci_paddr = paddr;
2906	r_dcache_vci_sc_req = true;
2907	r_dcache_vci_sc_data = m_dreq.wdata;
2908	r_dcache_fsm = DCACHE_SC_WAIT;
2909	}
2910	else // local fail
2911	{
2912	m_drsp.valid = true;
2913	m_drsp.error = false;
2914	m_drsp.rdata = 0x1;
2915	}
2916	}
2917	} // end SC
2918	} // end valid_req
2919	} // end if read/write/ll/sc request
2920	} // end processor request
2921
2922	// itlb miss request
2923	else if ( r_icache_tlb_miss_req.read() and not wbuf_write_miss )
2924	{
2925	r_dcache_tlb_ins = true;
2926	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
2927	r_dcache_fsm = DCACHE_TLB_MISS;
2928	}
2929
2930	// Computing requests for P1 stage : r_dcache_wbuf_req & r_dcache_updt_req
2931	r_dcache_updt_req = updt_request;
2932	r_dcache_wbuf_req = wbuf_request or
2933	(r_dcache_wbuf_req.read() and wbuf_write_miss);
2934	break;
2935	}
2936	/////////////////////
2937	case DCACHE_TLB_MISS: // This is the entry point for the sub-fsm handling all tlb miss.
2938	// Input arguments are:
2939	// - r_dcache_tlb_vaddr
2940	// - r_dcache_tlb_ins (true when itlb miss)
2941	// The sub-fsm access the dcache to find the missing TLB entry,
2942	// and activates the cache miss procedure in case of miss.
2943	// It bypass the first level page table access if possible.
2944	// It uses atomic access to update the R/L access bits
2945	// in the page table if required.
2946	// It directly updates the itlb or dtlb, and writes into the
2947	// r_mmu_ins_* or r_mmu_data* error reporting registers.
2948	{
2949	uint32_t ptba = 0;
2950	bool bypass;
2951	paddr_t pte_paddr;
2952
2953	// evaluate bypass in order to skip first level page table access
2954	if ( r_dcache_tlb_ins.read() ) // itlb miss
2955	{
2956	bypass = r_itlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba);
2957	}
2958	else // dtlb miss
2959	{
2960	bypass = r_dtlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba);
2961	}
2962
2963	if ( not bypass ) // Try to read PTE1/PTD1 in dcache
2964	{
2965	pte_paddr = (((paddr_t)r_mmu_ptpr.read()) << (INDEX1_NBITS+2)) \|
2966	((((paddr_t)r_dcache_tlb_vaddr.read()) >> PAGE_M_NBITS) << 2);
2967	r_dcache_tlb_paddr = pte_paddr;
2968	r_dcache_fsm = DCACHE_TLB_PTE1_GET;
2969	}
2970	else // Try to read PTE2 in dcache
2971	{
2972	pte_paddr = (paddr_t)ptba << PAGE_K_NBITS \|
2973	(paddr_t)(r_dcache_tlb_vaddr.read()&PTD_ID2_MASK)>>(PAGE_K_NBITS-3);
2974	r_dcache_tlb_paddr = pte_paddr;
2975	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
2976	}
2977
2978	#if DEBUG_DCACHE
2979	if ( m_debug_dcache_fsm )
2980	{
2981	if ( r_dcache_tlb_ins.read() )
2982	std::cout << " <PROC " << name() << " DCACHE_TLB_MISS> ITLB miss";
2983	else
2984	std::cout << " <PROC " << name() << " DCACHE_TLB_MISS> DTLB miss";
2985	std::cout << " / VADDR = " << std::hex << r_dcache_tlb_vaddr.read()
2986	<< " / ptpr = " << (((paddr_t)r_mmu_ptpr.read()) << (INDEX1_NBITS+2))
2987	<< " / BYPASS = " << bypass
2988	<< " / PTE_ADR = " << pte_paddr << std::endl;
2989	}
2990	#endif
2991
2992	break;
2993	}
2994	/////////////////////////
2995	case DCACHE_TLB_PTE1_GET: // try to read a PT1 entry in dcache
2996	{
2997	// coherence clack request (from DSPIN CLACK)
2998	if ( r_dcache_clack_req.read() )
2999	{
3000	r_dcache_fsm = DCACHE_CC_CHECK;
3001	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3002	break;
3003	}
3004
3005	// coherence request (from CC_RECEIVE FSM)
3006	if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
3007	{
3008	r_dcache_fsm = DCACHE_CC_CHECK;
3009	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3010	break;
3011	}
3012
3013	uint32_t entry;
3014	size_t way;
3015	size_t set;
3016	size_t word;
3017	int cache_state;
3018	r_dcache.read( r_dcache_tlb_paddr.read(),
3019	&entry,
3020	&way,
3021	&set,
3022	&word,
3023	&cache_state );
3024	#ifdef INSTRUMENTATION
3025	m_cpt_dcache_data_read++;
3026	m_cpt_dcache_dir_read++;
3027	#endif
3028	if ( cache_state == CACHE_SLOT_STATE_VALID ) // hit in dcache
3029	{
3030	if ( not (entry & PTE_V_MASK) ) // unmapped
3031	{
3032	if ( r_dcache_tlb_ins.read() )
3033	{
3034	r_mmu_ietr = MMU_READ_PT1_UNMAPPED;
3035	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3036	r_icache_tlb_miss_req = false;
3037	r_icache_tlb_rsp_error = true;
3038	}
3039	else
3040	{
3041	r_mmu_detr = MMU_READ_PT1_UNMAPPED;
3042	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3043	m_drsp.valid = true;
3044	m_drsp.error = true;
3045	}
3046	r_dcache_fsm = DCACHE_IDLE;
3047
3048	#if DEBUG_DCACHE
3049	if ( m_debug_dcache_fsm )
3050	{
3051	std::cout << " <PROC " << name()
3052	<< " DCACHE_TLB_PTE1_GET> HIT in dcache, but unmapped"
3053	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
3054	<< std::dec << " / way = " << way
3055	<< std::dec << " / set = " << set
3056	<< std::dec << " / word = " << word
3057	<< std::hex << " / PTE1 = " << entry << std::endl;
3058	}
3059	#endif
3060
3061	}
3062	else if( entry & PTE_T_MASK ) // PTD : me must access PT2
3063	{
3064	// mark the cache line ac containing a PTD
3065	r_dcache_contains_ptd[m_dcache_sets*way+set] = true;
3066
3067	// register bypass
3068	if ( r_dcache_tlb_ins.read() ) // itlb
3069	{
3070	r_itlb.set_bypass(r_dcache_tlb_vaddr.read(),
3071	entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1),
3072	r_dcache_tlb_paddr.read() / (m_icache_words<<2) );
3073	}
3074	else // dtlb
3075	{
3076	r_dtlb.set_bypass(r_dcache_tlb_vaddr.read(),
3077	entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1),
3078	r_dcache_tlb_paddr.read() / (m_dcache_words<<2) );
3079	}
3080	r_dcache_tlb_paddr =
3081	(paddr_t)(entry & ((1<<(m_paddr_nbits-PAGE_K_NBITS))-1)) << PAGE_K_NBITS \|
3082	(paddr_t)(((r_dcache_tlb_vaddr.read() & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3);
3083	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
3084
3085	#if DEBUG_DCACHE
3086	if ( m_debug_dcache_fsm )
3087	{
3088	std::cout << " <PROC " << name()
3089	<< " DCACHE_TLB_PTE1_GET> HIT in dcache"
3090	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
3091	<< std::dec << " / way = " << way
3092	<< std::dec << " / set = " << set
3093	<< std::dec << " / word = " << word
3094	<< std::hex << " / PTD = " << entry << std::endl;
3095	}
3096	#endif
3097	}
3098	else // PTE1 : we must update the TLB
3099	{
3100	r_dcache_in_tlb[m_icache_sets*way+set] = true;
3101	r_dcache_tlb_pte_flags = entry;
3102	r_dcache_tlb_cache_way = way;
3103	r_dcache_tlb_cache_set = set;
3104	r_dcache_tlb_cache_word = word;
3105	r_dcache_fsm = DCACHE_TLB_PTE1_SELECT;
3106
3107	#if DEBUG_DCACHE
3108	if ( m_debug_dcache_fsm )
3109	{
3110	std::cout << " <PROC " << name()
3111	<< " DCACHE_TLB_PTE1_GET> HIT in dcache"
3112	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
3113	<< std::dec << " / way = " << way
3114	<< std::dec << " / set = " << set
3115	<< std::dec << " / word = " << word
3116	<< std::hex << " / PTE1 = " << entry << std::endl;
3117	}
3118	#endif
3119	}
3120	}
3121	else if ( cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup
3122	{
3123	// stalled until cleanup is acknowledged
3124	r_dcache_fsm = DCACHE_TLB_PTE1_GET;
3125	}
3126	else // we must load the missing cache line in dcache
3127	{
3128	r_dcache_vci_miss_req = true;
3129	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
3130	r_dcache_save_paddr = r_dcache_tlb_paddr.read();
3131	r_dcache_miss_type = PTE1_MISS;
3132	r_dcache_fsm = DCACHE_MISS_SELECT;
3133
3134	#if DEBUG_DCACHE
3135	if ( m_debug_dcache_fsm )
3136	{
3137	std::cout << " <PROC " << name()
3138	<< " DCACHE_TLB_PTE1_GET> MISS in dcache:"
3139	<< " PTE1 address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
3140	}
3141	#endif
3142	}
3143	break;
3144	}
3145	////////////////////////////
3146	case DCACHE_TLB_PTE1_SELECT: // select a slot for PTE1
3147	{
3148	size_t way;
3149	size_t set;
3150
3151	if ( r_dcache_tlb_ins.read() )
3152	{
3153	r_itlb.select( r_dcache_tlb_vaddr.read(),
3154	true, // PTE1
3155	&way,
3156	&set );
3157	#ifdef INSTRUMENTATION
3158	m_cpt_itlb_read++;
3159	#endif
3160	}
3161	else
3162	{
3163	r_dtlb.select( r_dcache_tlb_vaddr.read(),
3164	true, // PTE1
3165	&way,
3166	&set );
3167	#ifdef INSTRUMENTATION
3168	m_cpt_dtlb_read++;
3169	#endif
3170	}
3171	r_dcache_tlb_way = way;
3172	r_dcache_tlb_set = set;
3173	r_dcache_fsm = DCACHE_TLB_PTE1_UPDT;
3174
3175	#if DEBUG_DCACHE
3176	if ( m_debug_dcache_fsm )
3177	{
3178	if ( r_dcache_tlb_ins.read() )
3179	std::cout << " <PROC " << name()
3180	<< " DCACHE_TLB_PTE1_SELECT> Select a slot in ITLB:";
3181	else
3182	std::cout << " <PROC " << name()
3183	<< ".DCACHE_TLB_PTE1_SELECT> Select a slot in DTLB:";
3184	std::cout << " way = " << std::dec << way
3185	<< " / set = " << set << std::endl;
3186	}
3187	#endif
3188	break;
3189	}
3190	//////////////////////////
3191	case DCACHE_TLB_PTE1_UPDT: // write a new PTE1 in tlb after testing the L/R bit
3192	// - if L/R bit already set, exit the sub-fsm.
3193	// - if not, we update the page table but we dont write
3194	// neither in DCACHE, nor in TLB, as this will be done by
3195	// the coherence mechanism.
3196	{
3197	paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2);
3198	uint32_t pte = r_dcache_tlb_pte_flags.read();
3199	bool pt_updt = false;
3200	bool local = true;
3201
3202	// We should compute the access locality:
3203	// The PPN MSB bits define the destination cluster index.
3204	// The m_srcid MSB bits define the source cluster index.
3205	// The number of bits to compare depends on the number of clusters,
3206	// and can be obtained in the mapping table.
3207	// As long as this computation is not done, all access are local.
3208
3209	if ( local ) // local access
3210	{
3211	if ( not ((pte & PTE_L_MASK) == PTE_L_MASK) ) // we must set the L bit
3212	{
3213	pt_updt = true;
3214	r_dcache_vci_cas_old = pte;
3215	r_dcache_vci_cas_new = pte \| PTE_L_MASK;
3216	pte = pte \| PTE_L_MASK;
3217	r_dcache_tlb_pte_flags = pte;
3218	}
3219	}
3220	else // remote access
3221	{
3222	if ( not ((pte & PTE_R_MASK) == PTE_R_MASK) ) // we must set the R bit
3223	{
3224	pt_updt = true;
3225	r_dcache_vci_cas_old = pte;
3226	r_dcache_vci_cas_new = pte \| PTE_R_MASK;
3227	pte = pte \| PTE_R_MASK;
3228	r_dcache_tlb_pte_flags = pte;
3229	}
3230	}
3231
3232	if ( not pt_updt ) // update TLB and return
3233	{
3234	if ( r_dcache_tlb_ins.read() )
3235	{
3236	r_itlb.write( true, // 2M page
3237	pte,
3238	0, // argument unused for a PTE1
3239	r_dcache_tlb_vaddr.read(),
3240	r_dcache_tlb_way.read(),
3241	r_dcache_tlb_set.read(),
3242	nline );
3243	#ifdef INSTRUMENTATION
3244	m_cpt_itlb_write++;
3245	#endif
3246
3247	#if DEBUG_DCACHE
3248	if ( m_debug_dcache_fsm )
3249	{
3250	std::cout << " <PROC " << name()
3251	<< " DCACHE_TLB_PTE1_UPDT> write PTE1 in ITLB"
3252	<< " / set = " << std::dec << r_dcache_tlb_set.read()
3253	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3254	r_itlb.printTrace();
3255	}
3256	#endif
3257	}
3258	else
3259	{
3260	r_dtlb.write( true, // 2M page
3261	pte,
3262	0, // argument unused for a PTE1
3263	r_dcache_tlb_vaddr.read(),
3264	r_dcache_tlb_way.read(),
3265	r_dcache_tlb_set.read(),
3266	nline );
3267	#ifdef INSTRUMENTATION
3268	m_cpt_dtlb_write++;
3269	#endif
3270
3271	#if DEBUG_DCACHE
3272	if ( m_debug_dcache_fsm )
3273	{
3274	std::cout << " <PROC " << name()
3275	<< " DCACHE_TLB_PTE1_UPDT> write PTE1 in DTLB"
3276	<< " / set = " << std::dec << r_dcache_tlb_set.read()
3277	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3278	r_dtlb.printTrace();
3279	}
3280	#endif
3281	}
3282	r_dcache_fsm = DCACHE_TLB_RETURN;
3283	}
3284	else // update page table but not TLB
3285	{
3286	r_dcache_fsm = DCACHE_TLB_LR_UPDT;
3287
3288	#if DEBUG_DCACHE
3289	if ( m_debug_dcache_fsm )
3290	{
3291	std::cout << " <PROC " << name()
3292	<< " DCACHE_TLB_PTE1_UPDT> L/R bit update required"
3293	<< std::endl;
3294	}
3295	#endif
3296	}
3297	break;
3298	}
3299	/////////////////////////
3300	case DCACHE_TLB_PTE2_GET: // Try to get a PTE2 (64 bits) in the dcache
3301	{
3302	// coherence clack request (from DSPIN CLACK)
3303	if ( r_dcache_clack_req.read() )
3304	{
3305	r_dcache_fsm = DCACHE_CC_CHECK;
3306	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3307	break;
3308	}
3309
3310	// coherence request (from CC_RECEIVE FSM)
3311	if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
3312	{
3313	r_dcache_fsm = DCACHE_CC_CHECK;
3314	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3315	break;
3316	}
3317
3318	uint32_t pte_flags;
3319	uint32_t pte_ppn;
3320	size_t way;
3321	size_t set;
3322	size_t word;
3323	int cache_state;
3324
3325	r_dcache.read( r_dcache_tlb_paddr.read(),
3326	&pte_flags,
3327	&pte_ppn,
3328	&way,
3329	&set,
3330	&word,
3331	&cache_state );
3332	#ifdef INSTRUMENTATION
3333	m_cpt_dcache_data_read++;
3334	m_cpt_dcache_dir_read++;
3335	#endif
3336	if ( cache_state == CACHE_SLOT_STATE_VALID ) // hit in dcache
3337	{
3338	if ( not (pte_flags & PTE_V_MASK) ) // unmapped
3339	{
3340	if ( r_dcache_tlb_ins.read() )
3341	{
3342	r_mmu_ietr = MMU_READ_PT2_UNMAPPED;
3343	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3344	r_icache_tlb_miss_req = false;
3345	r_icache_tlb_rsp_error = true;
3346	}
3347	else
3348	{
3349	r_mmu_detr = MMU_READ_PT2_UNMAPPED;
3350	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3351	m_drsp.valid = true;
3352	m_drsp.error = true;
3353	}
3354	r_dcache_fsm = DCACHE_IDLE;
3355
3356	#if DEBUG_DCACHE
3357	if ( m_debug_dcache_fsm )
3358	{
3359	std::cout << " <PROC " << name()
3360	<< " DCACHE_TLB_PTE2_GET> HIT in dcache, but PTE unmapped"
3361	<< " PTE_FLAGS = " << std::hex << pte_flags
3362	<< " PTE_PPN = " << std::hex << pte_ppn << std::endl;
3363	}
3364	#endif
3365	}
3366	else // mapped : we must update the TLB
3367	{
3368	r_dcache_in_tlb[m_dcache_sets*way+set] = true;
3369	r_dcache_tlb_pte_flags = pte_flags;
3370	r_dcache_tlb_pte_ppn = pte_ppn;
3371	r_dcache_tlb_cache_way = way;
3372	r_dcache_tlb_cache_set = set;
3373	r_dcache_tlb_cache_word = word;
3374	r_dcache_fsm = DCACHE_TLB_PTE2_SELECT;
3375
3376	#if DEBUG_DCACHE
3377	if ( m_debug_dcache_fsm )
3378	{
3379	std::cout << " <PROC " << name()
3380	<< " DCACHE_TLB_PTE2_GET> HIT in dcache:"
3381	<< " PTE_FLAGS = " << std::hex << pte_flags
3382	<< " PTE_PPN = " << std::hex << pte_ppn << std::endl;
3383	}
3384	#endif
3385	}
3386	}
3387	else if ( cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup
3388	{
3389	// stalled until cleanup is acknowledged
3390	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
3391
3392	#if DEBUG_DCACHE
3393	if ( m_debug_dcache_fsm )
3394	{
3395	std::cout << " <PROC " << name()
3396	<< " DCACHE_TLB_PTE2_GET> ZOMBI in dcache: waiting cleanup ack"
3397	<< std::endl;
3398	}
3399	#endif
3400	}
3401	else // we must load the missing cache line in dcache
3402	{
3403	r_dcache_fsm = DCACHE_MISS_SELECT;
3404	r_dcache_vci_miss_req = true;
3405	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
3406	r_dcache_save_paddr = r_dcache_tlb_paddr.read();
3407	r_dcache_miss_type = PTE2_MISS;
3408
3409	#if DEBUG_DCACHE
3410	if ( m_debug_dcache_fsm )
3411	{
3412	std::cout << " <PROC " << name()
3413	<< " DCACHE_TLB_PTE2_GET> MISS in dcache:"
3414	<< " PTE address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
3415	}
3416	#endif
3417	}
3418	break;
3419	}
3420	////////////////////////////
3421	case DCACHE_TLB_PTE2_SELECT: // select a slot for PTE2
3422	{
3423	size_t way;
3424	size_t set;
3425
3426	if ( r_dcache_tlb_ins.read() )
3427	{
3428	r_itlb.select( r_dcache_tlb_vaddr.read(),
3429	false, // PTE2
3430	&way,
3431	&set );
3432	#ifdef INSTRUMENTATION
3433	m_cpt_itlb_read++;
3434	#endif
3435	}
3436	else
3437	{
3438	r_dtlb.select( r_dcache_tlb_vaddr.read(),
3439	false, // PTE2
3440	&way,
3441	&set );
3442	#ifdef INSTRUMENTATION
3443	m_cpt_dtlb_read++;
3444	#endif
3445	}
3446
3447	#if DEBUG_DCACHE
3448	if ( m_debug_dcache_fsm )
3449	{
3450	if ( r_dcache_tlb_ins.read() )
3451	std::cout << " <PROC " << name()
3452	<< " DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB:";
3453	else
3454	std::cout << " <PROC " << name()
3455	<< " DCACHE_TLB_PTE2_SELECT> Select a slot in DTLB:";
3456	std::cout << " way = " << std::dec << way
3457	<< " / set = " << set << std::endl;
3458	}
3459	#endif
3460	r_dcache_tlb_way = way;
3461	r_dcache_tlb_set = set;
3462	r_dcache_fsm = DCACHE_TLB_PTE2_UPDT;
3463	break;
3464	}
3465	//////////////////////////
3466	case DCACHE_TLB_PTE2_UPDT: // write a new PTE2 in tlb after testing the L/R bit
3467	// - if L/R bit already set, exit the sub-fsm.
3468	// - if not, we update the page table but we dont write
3469	// neither in DCACHE, nor in TLB, as this will be done by
3470	// the coherence mechanism.
3471	{
3472	paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2);
3473	uint32_t pte_flags = r_dcache_tlb_pte_flags.read();
3474	uint32_t pte_ppn = r_dcache_tlb_pte_ppn.read();
3475	bool pt_updt = false;
3476	bool local = true;
3477
3478	// We should compute the access locality:
3479	// The PPN MSB bits define the destination cluster index.
3480	// The m_srcid MSB bits define the source cluster index.
3481	// The number of bits to compare depends on the number of clusters,
3482	// and can be obtained in the mapping table.
3483	// As long as this computation is not done, all access are local.
3484
3485	if ( local ) // local access
3486	{
3487	if ( not ((pte_flags & PTE_L_MASK) == PTE_L_MASK) ) // we must set the L bit
3488	{
3489	pt_updt = true;
3490	r_dcache_vci_cas_old = pte_flags;
3491	r_dcache_vci_cas_new = pte_flags \| PTE_L_MASK;
3492	pte_flags = pte_flags \| PTE_L_MASK;
3493	r_dcache_tlb_pte_flags = pte_flags;
3494	}
3495	}
3496	else // remote access
3497	{
3498	if ( not ((pte_flags & PTE_R_MASK) == PTE_R_MASK) ) // we must set the R bit
3499	{
3500	pt_updt = true;
3501	r_dcache_vci_cas_old = pte_flags;
3502	r_dcache_vci_cas_new = pte_flags \| PTE_R_MASK;
3503	pte_flags = pte_flags \| PTE_R_MASK;
3504	r_dcache_tlb_pte_flags = pte_flags;
3505	}
3506	}
3507
3508	if ( not pt_updt ) // update TLB
3509	{
3510	if ( r_dcache_tlb_ins.read() )
3511	{
3512	r_itlb.write( false, // 4K page
3513	pte_flags,
3514	pte_ppn,
3515	r_dcache_tlb_vaddr.read(),
3516	r_dcache_tlb_way.read(),
3517	r_dcache_tlb_set.read(),
3518	nline );
3519	#ifdef INSTRUMENTATION
3520	m_cpt_itlb_write++;
3521	#endif
3522
3523	#if DEBUG_DCACHE
3524	if ( m_debug_dcache_fsm )
3525	{
3526	std::cout << " <PROC " << name()
3527	<< " DCACHE_TLB_PTE2_UPDT> write PTE2 in ITLB"
3528	<< " / set = " << std::dec << r_dcache_tlb_set.read()
3529	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3530	r_itlb.printTrace();
3531	}
3532	#endif
3533	}
3534	else
3535	{
3536	r_dtlb.write( false, // 4K page
3537	pte_flags,
3538	pte_ppn,
3539	r_dcache_tlb_vaddr.read(),
3540	r_dcache_tlb_way.read(),
3541	r_dcache_tlb_set.read(),
3542	nline );
3543	#ifdef INSTRUMENTATION
3544	m_cpt_dtlb_write++;
3545	#endif
3546
3547	#if DEBUG_DCACHE
3548	if ( m_debug_dcache_fsm )
3549	{
3550	std::cout << " <PROC " << name()
3551	<< " DCACHE_TLB_PTE2_UPDT> write PTE2 in DTLB"
3552	<< " / set = " << std::dec << r_dcache_tlb_set.read()
3553	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3554	r_dtlb.printTrace();
3555	}
3556	#endif
3557
3558	}
3559	r_dcache_fsm = DCACHE_TLB_RETURN;
3560	}
3561	else // update page table but not TLB
3562	{
3563	r_dcache_fsm = DCACHE_TLB_LR_UPDT; // dcache and page table update
3564
3565	#if DEBUG_DCACHE
3566	if ( m_debug_dcache_fsm )
3567	{
3568	std::cout << " <PROC " << name()
3569	<< " DCACHE_TLB_PTE2_UPDT> L/R bit update required" << std::endl;
3570	}
3571	#endif
3572	}
3573	break;
3574	}
3575	////////////////////////
3576	case DCACHE_TLB_LR_UPDT: // request a CAS transaction to update L/R bit
3577	{
3578	#if DEBUG_DCACHE
3579	if ( m_debug_dcache_fsm )
3580	{
3581	std::cout << " <PROC " << name()
3582	<< " DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit" << std::endl;
3583	}
3584	#endif
3585	// r_dcache_vci_cas_old & r_dcache_vci_cas_new registers are already set
3586	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
3587
3588	// checking llsc reservation buffer
3589	if ( r_dcache_llsc_paddr.read() == r_dcache_tlb_paddr.read() )
3590	r_dcache_llsc_valid = false;
3591
3592	// request a CAS CMD and go to DCACHE_TLB_LR_WAIT state
3593	r_dcache_vci_cas_req = true;
3594	r_dcache_fsm = DCACHE_TLB_LR_WAIT;
3595	break;
3596	}
3597	////////////////////////
3598	case DCACHE_TLB_LR_WAIT: // Waiting the response to SC transaction for DIRTY bit.
3599	// We consume the response in rsp FIFO,
3600	// and exit the sub-fsm, but we don't
3601	// analyse the response, because we don't
3602	// care if the L/R bit update is not done.
3603	// We must take the coherence requests because
3604	// there is a risk of dead-lock
3605
3606	{
3607	// coherence clack request (from DSPIN CLACK)
3608	if ( r_dcache_clack_req.read() )
3609	{
3610	r_dcache_fsm = DCACHE_CC_CHECK;
3611	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3612	break;
3613	}
3614
3615	// coherence request (from CC_RECEIVE FSM)
3616	if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
3617	{
3618	r_dcache_fsm = DCACHE_CC_CHECK;
3619	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3620	break;
3621	}
3622
3623	if ( r_vci_rsp_data_error.read() ) // bus error
3624	{
3625	std::cout << "BUS ERROR in DCACHE_TLB_LR_WAIT state" << std::endl;
3626	std::cout << "This should not happen in this state" << std::endl;
3627	exit(0);
3628	}
3629	else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
3630	{
3631	#if DEBUG_DCACHE
3632	if ( m_debug_dcache_fsm )
3633	{
3634	std::cout << " <PROC " << name()
3635	<< " DCACHE_TLB_LR_WAIT> SC response received" << std::endl;
3636	}
3637	#endif
3638	vci_rsp_fifo_dcache_get = true;
3639	r_dcache_fsm = DCACHE_TLB_RETURN;
3640	}
3641	break;
3642	}
3643	///////////////////////
3644	case DCACHE_TLB_RETURN: // return to caller depending on tlb miss type
3645	{
3646	#if DEBUG_DCACHE
3647	if ( m_debug_dcache_fsm )
3648	{
3649	std::cout << " <PROC " << name()
3650	<< " DCACHE_TLB_RETURN> TLB MISS completed" << std::endl;
3651	}
3652	#endif
3653	if ( r_dcache_tlb_ins.read() ) r_icache_tlb_miss_req = false;
3654	r_dcache_fsm = DCACHE_IDLE;
3655	break;
3656	}
3657	///////////////////////
3658	case DCACHE_XTN_SWITCH: // The r_ptpr registers must be written,
3659	// and both itlb and dtlb must be flushed.
3660	// Caution : the itlb miss requests must be taken
3661	// to avoid dead-lock in case of simultaneous ITLB miss
3662	// Caution : the clack and cc requests must be taken
3663	// to avoid dead-lock
3664	{
3665	// coherence clack request (from DSPIN CLACK)
3666	if ( r_dcache_clack_req.read() )
3667	{
3668	r_dcache_fsm = DCACHE_CC_CHECK;
3669	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3670	break;
3671	}
3672
3673	// coherence request (from CC_RECEIVE FSM)
3674	if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
3675	{
3676	r_dcache_fsm = DCACHE_CC_CHECK;
3677	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3678	break;
3679	}
3680
3681	// itlb miss request
3682	if ( r_icache_tlb_miss_req.read() )
3683	{
3684	r_dcache_tlb_ins = true;
3685	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
3686	r_dcache_fsm = DCACHE_TLB_MISS;
3687	break;
3688	}
3689
3690	if ( not r_dcache_xtn_req.read() )
3691	{
3692	r_dtlb.flush();
3693	r_mmu_ptpr = m_dreq.wdata;
3694	r_dcache_fsm = DCACHE_IDLE;
3695	m_drsp.valid = true;
3696	}
3697	break;
3698	}
3699	/////////////////////
3700	case DCACHE_XTN_SYNC: // waiting until write buffer empty
3701	// The coherence request must be taken
3702	// as there is a risk of dead-lock
3703	{
3704	// coherence clack request (from DSPIN CLACK)
3705	if ( r_dcache_clack_req.read() )
3706	{
3707	r_dcache_fsm = DCACHE_CC_CHECK;
3708	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3709	break;
3710	}
3711
3712	// coherence request (from CC_RECEIVE FSM)
3713	if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
3714	{
3715	r_dcache_fsm = DCACHE_CC_CHECK;
3716	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3717	break;
3718	}
3719
3720	if ( r_wbuf.empty() )
3721	{
3722	m_drsp.valid = true;
3723	r_dcache_fsm = DCACHE_IDLE;
3724	}
3725	break;
3726	}
3727	////////////////////////
3728	case DCACHE_XTN_IC_FLUSH: // Waiting completion of an XTN request to the ICACHE FSM
3729	case DCACHE_XTN_IC_INVAL_VA: // Caution : the itlb miss requests must be taken
3730	case DCACHE_XTN_IC_INVAL_PA: // because the XTN_ICACHE_INVAL request to icache
3731	case DCACHE_XTN_IT_INVAL: // can generate an itlb miss,
3732	// and because it can exist a simultaneous ITLB miss
3733	{
3734	// coherence clack request (from DSPIN CLACK)
3735	if ( r_dcache_clack_req.read() )
3736	{
3737	r_dcache_fsm = DCACHE_CC_CHECK;
3738	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3739	break;
3740	}
3741
3742	// coherence request (from CC_RECEIVE FSM)
3743	if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
3744	{
3745	r_dcache_fsm = DCACHE_CC_CHECK;
3746	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3747	break;
3748	}
3749
3750	// itlb miss request
3751	if ( r_icache_tlb_miss_req.read() )
3752	{
3753	r_dcache_tlb_ins = true;
3754	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
3755	r_dcache_fsm = DCACHE_TLB_MISS;
3756	break;
3757	}
3758
3759	// test if XTN request to icache completed
3760	if ( not r_dcache_xtn_req.read() )
3761	{
3762	r_dcache_fsm = DCACHE_IDLE;
3763	m_drsp.valid = true;
3764	}
3765	break;
3766	}
3767	/////////////////////////
3768	case DCACHE_XTN_DC_FLUSH: // Invalidate sequencially all cache lines, using
3769	// r_dcache_flush_count as a slot counter,
3770	// looping in this state until all slots have been visited.
3771	// It can require two cycles per slot:
3772	// We test here the slot state, and make the actual inval
3773	// (if line is valid) in DCACHE_XTN_DC_FLUSH_GO state.
3774	// A cleanup request is generated for each valid line.
3775	// returns to IDLE and flush TLBs when last slot
3776	{
3777	// coherence clack request (from DSPIN CLACK)
3778	if ( r_dcache_clack_req.read() )
3779	{
3780	r_dcache_fsm = DCACHE_CC_CHECK;
3781	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3782	break;
3783	}
3784
3785	// coherence request (from CC_RECEIVE FSM)
3786	if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
3787	{
3788	r_dcache_fsm = DCACHE_CC_CHECK;
3789	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3790	break;
3791	}
3792
3793	if ( not r_dcache_cc_send_req.read() ) // blocked until previous cc_send request is sent
3794	{
3795	int state;
3796	paddr_t tag;
3797	size_t way = r_dcache_flush_count.read()/m_dcache_sets;
3798	size_t set = r_dcache_flush_count.read()%m_dcache_sets;
3799
3800	#ifdef INSTRUMENTATION
3801	m_cpt_dcache_dir_read++;
3802	#endif
3803	r_dcache.read_dir( way,
3804	set,
3805	&tag,
3806	&state );
3807
3808	if ( state == CACHE_SLOT_STATE_VALID ) // inval required
3809	{
3810	// request cleanup
3811	r_dcache_cc_send_req = true;
3812	r_dcache_cc_send_nline = tag * m_dcache_sets + set;
3813	r_dcache_cc_send_way = way;
3814	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
3815
3816	// goes to DCACHE_XTN_DC_FLUSH_GO to inval directory
3817	r_dcache_miss_way = way;
3818	r_dcache_miss_set = set;
3819	r_dcache_fsm = DCACHE_XTN_DC_FLUSH_GO;
3820	}
3821	else if ( r_dcache_flush_count.read() ==
3822	(m_dcache_sets*m_dcache_ways - 1) ) // last slot
3823	{
3824	r_dtlb.reset();
3825	r_itlb.reset();
3826	r_dcache_fsm = DCACHE_IDLE;
3827	m_drsp.valid = true;
3828	}
3829
3830	// saturation counter
3831	if ( r_dcache_flush_count.read() < (m_dcache_sets*m_dcache_ways - 1) )
3832	r_dcache_flush_count = r_dcache_flush_count.read() + 1;
3833	}
3834	break;
3835	}
3836	////////////////////////////
3837	case DCACHE_XTN_DC_FLUSH_GO: // Switch the cache slot to ZOMBI state
3838	// and reset directory extension.
3839	// returns to IDLE and flush TLBs when last slot
3840	{
3841	size_t way = r_dcache_miss_way.read();
3842	size_t set = r_dcache_miss_set.read();
3843
3844	r_dcache_in_tlb[m_dcache_sets*way+set] = false;
3845	r_dcache_contains_ptd[m_dcache_sets*way+set] = false;
3846
3847	#ifdef INSTRUMENTATION
3848	m_cpt_dcache_dir_write++;
3849	#endif
3850	r_dcache.write_dir( way,
3851	set,
3852	CACHE_SLOT_STATE_ZOMBI );
3853
3854	if ( r_dcache_flush_count.read() ==
3855	(m_dcache_sets*m_dcache_ways - 1) ) // last slot
3856	{
3857	r_dtlb.reset();
3858	r_itlb.reset();
3859	r_dcache_fsm = DCACHE_IDLE;
3860	m_drsp.valid = true;
3861	}
3862	else
3863	{
3864	r_dcache_fsm = DCACHE_XTN_DC_FLUSH;
3865	}
3866	break;
3867	}
3868	/////////////////////////
3869	case DCACHE_XTN_DT_INVAL: // handling processor XTN_DTLB_INVAL request
3870	{
3871	r_dtlb.inval(r_dcache_save_wdata.read());
3872	r_dcache_fsm = DCACHE_IDLE;
3873	m_drsp.valid = true;
3874	break;
3875	}
3876	////////////////////////////
3877	case DCACHE_XTN_DC_INVAL_VA: // selective cache line invalidate with virtual address
3878	// requires 3 cycles: access tlb, read cache, inval cache
3879	// we compute the physical address in this state
3880	{
3881	paddr_t paddr;
3882	bool hit;
3883
3884	if ( r_mmu_mode.read() & DATA_TLB_MASK ) // dtlb activated
3885	{
3886
3887	#ifdef INSTRUMENTATION
3888	m_cpt_dtlb_read++;
3889	#endif
3890	hit = r_dtlb.translate( r_dcache_save_wdata.read(),
3891	&paddr );
3892	}
3893	else // dtlb not activated
3894	{
3895	paddr = (paddr_t)r_dcache_save_wdata.read();
3896	if (vci_param::N > 32)
3897	paddr = paddr \| ((paddr_t)(r_dcache_paddr_ext.read()) << 32);
3898	hit = true;
3899	}
3900
3901	if ( hit ) // tlb hit
3902	{
3903	r_dcache_save_paddr = paddr;
3904	r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA;
3905	}
3906	else // tlb miss
3907	{
3908
3909	#ifdef INSTRUMENTATION
3910	m_cpt_dtlb_miss++;
3911	#endif
3912	r_dcache_tlb_ins = false; // dtlb
3913	r_dcache_tlb_vaddr = r_dcache_save_wdata.read();
3914	r_dcache_fsm = DCACHE_TLB_MISS;
3915	}
3916
3917	#if DEBUG_DCACHE
3918	if ( m_debug_dcache_fsm )
3919	{
3920	std::cout << " <PROC " << name()
3921	<< " DCACHE_XTN_DC_INVAL_VA> Compute physical address" << std::hex
3922	<< " / VADDR = " << r_dcache_save_wdata.read()
3923	<< " / PADDR = " << paddr << std::endl;
3924	}
3925	#endif
3926
3927	break;
3928	}
3929	////////////////////////////
3930	case DCACHE_XTN_DC_INVAL_PA: // selective cache line invalidate with physical address
3931	// requires 2 cycles: read cache / inval cache
3932	// In this state we read dcache.
3933	{
3934	size_t way;
3935	size_t set;
3936	size_t word;
3937	int state;
3938
3939	#ifdef INSTRUMENTATION
3940	m_cpt_dcache_dir_read++;
3941	#endif
3942	r_dcache.read_dir( r_dcache_save_paddr.read(),
3943	&state,
3944	&way,
3945	&set,
3946	&word );
3947
3948	if ( state == CACHE_SLOT_STATE_VALID ) // inval to be done
3949	{
3950	r_dcache_xtn_way = way;
3951	r_dcache_xtn_set = set;
3952	r_dcache_fsm = DCACHE_XTN_DC_INVAL_GO;
3953	}
3954	else // miss : nothing to do
3955	{
3956	r_dcache_fsm = DCACHE_IDLE;
3957	m_drsp.valid = true;
3958	}
3959
3960	#if DEBUG_DCACHE
3961	if ( m_debug_dcache_fsm )
3962	{
3963	std::cout << " <PROC " << name()
3964	<< " DCACHE_XTN_DC_INVAL_PA> Test hit in dcache" << std::hex
3965	<< " / PADDR = " << r_dcache_save_paddr.read() << std::dec
3966	<< " / HIT = " << (state == CACHE_SLOT_STATE_VALID)
3967	<< " / SET = " << set
3968	<< " / WAY = " << way << std::endl;
3969	}
3970	#endif
3971	break;
3972	}
3973	////////////////////////////
3974	case DCACHE_XTN_DC_INVAL_GO: // In this state, we invalidate the cache line
3975	// Blocked if previous cleanup not completed
3976	// Test if itlb or dtlb inval is required
3977	{
3978	if ( not r_dcache_cc_send_req.read() ) // blocked until previous cc_send request is sent
3979	{
3980	size_t way = r_dcache_xtn_way.read();
3981	size_t set = r_dcache_xtn_set.read();
3982	paddr_t nline = r_dcache_save_paddr.read() / (m_dcache_words<<2);
3983
3984	#ifdef INSTRUMENTATION
3985	m_cpt_dcache_dir_write++;
3986	#endif
3987	r_dcache.write_dir( way,
3988	set,
3989	CACHE_SLOT_STATE_ZOMBI );
3990
3991	// request cleanup
3992	r_dcache_cc_send_req = true;
3993	r_dcache_cc_send_nline = nline;
3994	r_dcache_cc_send_way = way;
3995	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
3996
3997	// possible itlb & dtlb invalidate
3998	if ( r_dcache_in_tlb[way*m_dcache_sets+set] )
3999	{
4000	r_dcache_tlb_inval_line = nline;
4001	r_dcache_tlb_inval_set = 0;
4002	r_dcache_fsm_scan_save = DCACHE_XTN_DC_INVAL_END;
4003	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4004	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
4005	}
4006	else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] )
4007	{
4008	r_itlb.reset();
4009	r_dtlb.reset();
4010	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
4011	r_dcache_fsm = DCACHE_IDLE;
4012	m_drsp.valid = true;
4013	}
4014	else
4015	{
4016	r_dcache_fsm = DCACHE_IDLE;
4017	m_drsp.valid = true;
4018	}
4019
4020	#if DEBUG_DCACHE
4021	if ( m_debug_dcache_fsm )
4022	{
4023	std::cout << " <PROC " << name()
4024	<< " DCACHE_XTN_DC_INVAL_GO> Actual dcache inval" << std::hex
4025	<< " / PADDR = " << r_dcache_save_paddr.read() << std::endl;
4026	}
4027	#endif
4028	}
4029	break;
4030	}
4031	//////////////////////////////
4032	case DCACHE_XTN_DC_INVAL_END: // send response to processor XTN request
4033	{
4034	r_dcache_fsm = DCACHE_IDLE;
4035	m_drsp.valid = true;
4036	break;
4037	}
4038	////////////////////////
4039	case DCACHE_MISS_SELECT: // Try to select a slot in associative set,
4040	// Waiting in this state if no slot available.
4041	// If a victim slot has been choosen and the r_icache_cc_send_req is false,
4042	// we send the cleanup request in this state.
4043	// If not, a r_icache_cleanup_victim_req flip-flop is
4044	// utilized for saving this cleanup request, and it will be sent later
4045	// in state ICACHE_MISS_WAIT or ICACHE_MISS_UPDT_DIR.
4046	// The r_icache_miss_clack flip-flop is set
4047	// when a cleanup is required
4048	{
4049	if ( m_dreq.valid) m_cost_data_miss_frz++;
4050
4051	// coherence clack request (from DSPIN CLACK)
4052	if ( r_dcache_clack_req.read() )
4053	{
4054	r_dcache_fsm = DCACHE_CC_CHECK;
4055	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4056	break;
4057	}
4058
4059	// coherence request (from CC_RECEIVE FSM)
4060	if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
4061	{
4062	r_dcache_fsm = DCACHE_CC_CHECK;
4063	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4064	break;
4065	}
4066
4067	bool found = false;
4068	bool cleanup = false;
4069	size_t way = 0;
4070	size_t set = 0;
4071	paddr_t victim = 0;
4072
4073	#ifdef INSTRUMENTATION
4074	m_cpt_dcache_dir_read++;
4075	#endif
4076	r_dcache.read_select( r_dcache_save_paddr.read(),
4077	&victim,
4078	&way,
4079	&set,
4080	&found,
4081	&cleanup );
4082
4083	if ( not found )
4084	{
4085	break;
4086	}
4087	else
4088	{
4089	r_dcache_miss_way = way;
4090	r_dcache_miss_set = set;
4091
4092	if ( cleanup )
4093	{
4094	if ( not r_dcache_cc_send_req.read() )
4095	{
4096	r_dcache_cc_send_req = true;
4097	r_dcache_cc_send_nline = victim;
4098	r_dcache_cc_send_way = way;
4099	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
4100
4101	}
4102	else
4103	{
4104	r_dcache_cleanup_victim_req = true;
4105	r_dcache_cleanup_victim_nline = victim;
4106	}
4107
4108	r_dcache_miss_clack = true;
4109	r_dcache_fsm = DCACHE_MISS_CLEAN;
4110	}
4111	else
4112	{
4113	r_dcache_fsm = DCACHE_MISS_WAIT;
4114	}
4115
4116	#if DEBUG_DCACHE
4117	if ( m_debug_dcache_fsm )
4118	{
4119	std::cout << " <PROC " << name()
4120	<< " DCACHE_MISS_SELECT> Select a slot:" << std::dec
4121	<< " / WAY = " << way
4122	<< " / SET = " << set
4123	<< " / PADDR = " << std::hex << r_dcache_save_paddr.read();
4124	if(cleanup) std::cout << " / VICTIM = " << (victimm_dcache_words4) << std::endl;
4125	else std::cout << std::endl;
4126	}
4127	#endif
4128	} // end found
4129	break;
4130	}
4131	///////////////////////
4132	case DCACHE_MISS_CLEAN: // switch the slot to ZOMBI state
4133	// and possibly request itlb or dtlb invalidate
4134	{
4135	if ( m_dreq.valid) m_cost_data_miss_frz++;
4136
4137	size_t way = r_dcache_miss_way.read();
4138	size_t set = r_dcache_miss_set.read();
4139
4140	#ifdef INSTRUMENTATION
4141	m_cpt_dcache_dir_read++;
4142	#endif
4143	r_dcache.write_dir( way,
4144	set,
4145	CACHE_SLOT_STATE_ZOMBI );
4146	#if DEBUG_DCACHE
4147	if ( m_debug_dcache_fsm )
4148	{
4149	std::cout << " <PROC " << name()
4150	<< " DCACHE_MISS_CLEAN> Switch to ZOMBI state" << std::dec
4151	<< " / way = " << way
4152	<< " / set = " << set << std::endl;
4153	}
4154	#endif
4155	// if selective itlb & dtlb invalidate are required
4156	// the miss response is not handled before invalidate completed
4157	if ( r_dcache_in_tlb[way*m_dcache_sets+set] )
4158	{
4159	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
4160
4161	if( not r_dcache_cleanup_victim_req.read() )
4162	r_dcache_tlb_inval_line = r_dcache_cc_send_nline.read();
4163	else
4164	r_dcache_tlb_inval_line = r_dcache_cleanup_victim_nline.read();
4165
4166	r_dcache_tlb_inval_set = 0;
4167	r_dcache_fsm_scan_save = DCACHE_MISS_WAIT;
4168	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4169	}
4170	else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] )
4171	{
4172	r_itlb.reset();
4173	r_dtlb.reset();
4174	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
4175	r_dcache_fsm = DCACHE_MISS_WAIT;
4176	}
4177	else
4178	{
4179	r_dcache_fsm = DCACHE_MISS_WAIT;
4180	}
4181	break;
4182	}
4183	//////////////////////
4184	case DCACHE_MISS_WAIT: // waiting the response to a miss request from VCI_RSP FSM
4185	// This state is in charge of error signaling
4186	// There is 5 types of error depending on the requester
4187	{
4188	if ( m_dreq.valid) m_cost_data_miss_frz++;
4189
4190	// send cleanup victim request
4191	if ( r_dcache_cleanup_victim_req.read() and not r_dcache_cc_send_req.read() )
4192	{
4193	r_dcache_cc_send_req = true;
4194	r_dcache_cc_send_nline = r_dcache_cleanup_victim_nline;
4195	r_dcache_cc_send_way = r_dcache_miss_way;
4196	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
4197	r_dcache_cleanup_victim_req = false;
4198	}
4199
4200	// coherence clack request (from DSPIN CLACK)
4201	if ( r_dcache_clack_req.read() )
4202	{
4203	r_dcache_fsm = DCACHE_CC_CHECK;
4204	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4205	break;
4206	}
4207
4208	// coherence request (from CC_RECEIVE FSM)
4209	if ( r_cc_receive_dcache_req.read() and
4210	not r_dcache_cc_send_req.read() and
4211	not r_dcache_cleanup_victim_req.read())
4212	{
4213	r_dcache_fsm = DCACHE_CC_CHECK;
4214	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4215	break;
4216	}
4217
4218	if ( r_vci_rsp_data_error.read() ) // bus error
4219	{
4220	switch ( r_dcache_miss_type.read() )
4221	{
4222	case PROC_MISS:
4223	{
4224	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
4225	r_mmu_dbvar = r_dcache_save_vaddr.read();
4226	m_drsp.valid = true;
4227	m_drsp.error = true;
4228	r_dcache_fsm = DCACHE_IDLE;
4229	break;
4230	}
4231	case PTE1_MISS:
4232	{
4233	if ( r_dcache_tlb_ins.read() )
4234	{
4235	r_mmu_ietr = MMU_READ_PT1_ILLEGAL_ACCESS;
4236	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
4237	r_icache_tlb_miss_req = false;
4238	r_icache_tlb_rsp_error = true;
4239	}
4240	else
4241	{
4242	r_mmu_detr = MMU_READ_PT1_ILLEGAL_ACCESS;
4243	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
4244	m_drsp.valid = true;
4245	m_drsp.error = true;
4246	}
4247	r_dcache_fsm = DCACHE_IDLE;
4248	break;
4249	}
4250	case PTE2_MISS:
4251	{
4252	if ( r_dcache_tlb_ins.read() )
4253	{
4254	r_mmu_ietr = MMU_READ_PT2_ILLEGAL_ACCESS;
4255	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
4256	r_icache_tlb_miss_req = false;
4257	r_icache_tlb_rsp_error = true;
4258	}
4259	else
4260	{
4261	r_mmu_detr = MMU_READ_PT2_ILLEGAL_ACCESS;
4262	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
4263	m_drsp.valid = true;
4264	m_drsp.error = true;
4265	}
4266	r_dcache_fsm = DCACHE_IDLE;
4267	break;
4268	}
4269	} // end switch type
4270	r_vci_rsp_data_error = false;
4271	}
4272	else if ( r_vci_rsp_fifo_dcache.rok() ) // valid response available
4273	{
4274	r_dcache_miss_word = 0;
4275	r_dcache_fsm = DCACHE_MISS_DATA_UPDT;
4276	}
4277	break;
4278	}
4279	//////////////////////////
4280	case DCACHE_MISS_DATA_UPDT: // update the dcache (one word per cycle)
4281	{
4282	if ( m_dreq.valid) m_cost_data_miss_frz++;
4283
4284	if ( r_vci_rsp_fifo_dcache.rok() ) // one word available
4285	{
4286	#ifdef INSTRUMENTATION
4287	m_cpt_dcache_data_write++;
4288	#endif
4289	r_dcache.write( r_dcache_miss_way.read(),
4290	r_dcache_miss_set.read(),
4291	r_dcache_miss_word.read(),
4292	r_vci_rsp_fifo_dcache.read() );
4293	#if DEBUG_DCACHE
4294	if ( m_debug_dcache_fsm )
4295	{
4296	std::cout << " <PROC " << name()
4297	<< " DCACHE_MISS_DATA_UPDT> Write one word:"
4298	<< " / DATA = " << std::hex << r_vci_rsp_fifo_dcache.read()
4299	<< " / WAY = " << std::dec << r_dcache_miss_way.read()
4300	<< " / SET = " << r_dcache_miss_set.read()
4301	<< " / WORD = " << r_dcache_miss_word.read() << std::endl;
4302	}
4303	#endif
4304	vci_rsp_fifo_dcache_get = true;
4305	r_dcache_miss_word = r_dcache_miss_word.read() + 1;
4306
4307	if ( r_dcache_miss_word.read() == (m_dcache_words-1) ) // last word
4308	{
4309	r_dcache_fsm = DCACHE_MISS_DIR_UPDT;
4310	}
4311	}
4312	break;
4313	}
4314	//////////////////////////
4315	case DCACHE_MISS_DIR_UPDT: // Stalled if a victim line has been evicted
4316	// and the cleanup ack has not been received,
4317	// as indicated by the r_dcache_miss clack.
4318	// - If no matching coherence request (r_dcache_inval_miss)
4319	// switch directory slot to VALID state.
4320	// - If matching coherence request, switch directory slot
4321	// to ZOMBI state, and send a cleanup request.
4322	{
4323	if ( m_dreq.valid) m_cost_data_miss_frz++;
4324
4325	// send cleanup victim request
4326	if ( r_dcache_cleanup_victim_req.read() and not r_dcache_cc_send_req.read() )
4327	{
4328	r_dcache_cc_send_req = true;
4329	r_dcache_cc_send_nline = r_dcache_cleanup_victim_nline;
4330	r_dcache_cc_send_way = r_dcache_miss_way;
4331	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
4332	r_dcache_cleanup_victim_req = false;
4333	}
4334
4335	// coherence clack request (from DSPIN CLACK)
4336	if ( r_dcache_clack_req.read() )
4337	{
4338	r_dcache_fsm = DCACHE_CC_CHECK;
4339	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4340	break;
4341	}
4342
4343	// coherence request (from CC_RECEIVE FSM)
4344	if ( r_cc_receive_dcache_req.read() and
4345	not r_dcache_cc_send_req.read() and
4346	not r_dcache_cleanup_victim_req.read() )
4347	{
4348	r_dcache_fsm = DCACHE_CC_CHECK;
4349	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4350	break;
4351	}
4352
4353	if ( not r_dcache_miss_clack.read() ) // waiting cleanup acknowledge
4354	{
4355	if ( r_dcache_miss_inval.read() ) // switch slot to ZOMBI state, and new cleanup
4356	{
4357	if ( not r_dcache_cc_send_req.read() ) // blocked until previous request sent
4358	{
4359	r_dcache_miss_inval = false;
4360	// request cleanup
4361	r_dcache_cc_send_req = true;
4362	r_dcache_cc_send_nline = r_dcache_save_paddr.read()/(m_dcache_words<<2);
4363	r_dcache_cc_send_way = r_dcache_miss_way.read();
4364	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
4365
4366	#ifdef INSTRUMENTATION
4367	m_cpt_dcache_dir_write++;
4368	#endif
4369	r_dcache.write_dir( r_dcache_save_paddr.read(),
4370	r_dcache_miss_way.read(),
4371	r_dcache_miss_set.read(),
4372	CACHE_SLOT_STATE_ZOMBI );
4373	#if DEBUG_DCACHE
4374	if ( m_debug_dcache_fsm )
4375	std::cout << " <PROC " << name()
4376	<< " DCACHE_MISS_DIR_UPDT> Switch slot to ZOMBI state"
4377	<< " PADDR = " << std::hex << r_dcache_save_paddr.read()
4378	<< " / WAY = " << std::dec << r_dcache_miss_way.read()
4379	<< " / SET = " << r_dcache_miss_set.read() << std::endl;
4380	#endif
4381	}
4382	else
4383	break;
4384	}
4385	else // switch slot to VALID state
4386	{
4387
4388	#ifdef INSTRUMENTATION
4389	m_cpt_dcache_dir_write++;
4390	#endif
4391	r_dcache.write_dir( r_dcache_save_paddr.read(),
4392	r_dcache_miss_way.read(),
4393	r_dcache_miss_set.read(),
4394	CACHE_SLOT_STATE_VALID );
4395
4396	#if DEBUG_DCACHE
4397	if ( m_debug_dcache_fsm )
4398	std::cout << " <PROC " << name()
4399	<< " DCACHE_MISS_DIR_UPDT> Switch slot to VALID state"
4400	<< " PADDR = " << std::hex << r_dcache_save_paddr.read()
4401	<< " / WAY = " << std::dec << r_dcache_miss_way.read()
4402	<< " / SET = " << r_dcache_miss_set.read() << std::endl;
4403	#endif
4404	// reset directory extension
4405	size_t way = r_dcache_miss_way.read();
4406	size_t set = r_dcache_miss_set.read();
4407	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
4408	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
4409	}
4410	if (r_dcache_miss_type.read()==PTE1_MISS) r_dcache_fsm = DCACHE_TLB_PTE1_GET;
4411	else if (r_dcache_miss_type.read()==PTE2_MISS) r_dcache_fsm = DCACHE_TLB_PTE2_GET;
4412	else r_dcache_fsm = DCACHE_IDLE;
4413	}
4414	break;
4415	}
4416	/////////////////////
4417	case DCACHE_UNC_WAIT: // waiting a response to an uncacheable read
4418	{
4419	// coherence clack request (from DSPIN CLACK)
4420	if ( r_dcache_clack_req.read() )
4421	{
4422	r_dcache_fsm = DCACHE_CC_CHECK;
4423	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4424	break;
4425	}
4426
4427	// coherence request (from CC_RECEIVE FSM)
4428	if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
4429	{
4430	r_dcache_fsm = DCACHE_CC_CHECK;
4431	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4432	break;
4433	}
4434
4435	if ( r_vci_rsp_data_error.read() ) // bus error
4436	{
4437	if(r_dcache_vci_unc_write.read())
4438	r_mmu_detr = MMU_WRITE_DATA_ILLEGAL_ACCESS;
4439	else
4440	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
4441
4442	r_mmu_dbvar = m_dreq.addr;
4443	r_vci_rsp_data_error = false;
4444	m_drsp.error = true;
4445	m_drsp.valid = true;
4446	r_dcache_fsm = DCACHE_IDLE;
4447	break;
4448	}
4449	else if ( r_vci_rsp_fifo_dcache.rok() ) // data available
4450	{
4451	// consume data
4452	vci_rsp_fifo_dcache_get = true;
4453	r_dcache_fsm = DCACHE_IDLE;
4454
4455	// acknowledge the processor request if it has not been modified
4456	if ( m_dreq.valid and (m_dreq.addr == r_dcache_save_vaddr.read()) )
4457	{
4458	m_drsp.valid = true;
4459	m_drsp.error = false;
4460	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
4461	}
4462	}
4463	break;
4464	}
4465	/////////////////////
4466	case DCACHE_LL_WAIT: // waiting VCI response to a LL transaction
4467	{
4468	// coherence clack request (from DSPIN CLACK)
4469	if ( r_dcache_clack_req.read() )
4470	{
4471	r_dcache_fsm = DCACHE_CC_CHECK;
4472	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4473	break;
4474	}
4475
4476	// coherence request (from CC_RECEIVE FSM)
4477	if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
4478	{
4479	r_dcache_fsm = DCACHE_CC_CHECK;
4480	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4481	break;
4482	}
4483
4484	if ( r_vci_rsp_data_error.read() ) // bus error
4485	{
4486	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
4487	r_mmu_dbvar = m_dreq.addr;
4488	r_vci_rsp_data_error = false;
4489	m_drsp.error = true;
4490	m_drsp.valid = true;
4491	r_dcache_fsm = DCACHE_IDLE;
4492	break;
4493	}
4494	else if ( r_vci_rsp_fifo_dcache.rok() ) // data available
4495	{
4496	// consume data
4497	vci_rsp_fifo_dcache_get = true;
4498
4499	if(r_dcache_ll_rsp_count.read() == 0) // first flit
4500	{
4501	// set key value in llsc reservation buffer
4502	r_dcache_llsc_key = r_vci_rsp_fifo_dcache.read();
4503	r_dcache_ll_rsp_count = r_dcache_ll_rsp_count.read() + 1 ;
4504	}
4505	else // last flit
4506	{
4507	// acknowledge the processor request if it has not been modified
4508	if ( m_dreq.valid and (m_dreq.addr == r_dcache_save_vaddr.read()) )
4509	{
4510	m_drsp.valid = true;
4511	m_drsp.error = false;
4512	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
4513	}
4514	r_dcache_fsm = DCACHE_IDLE;
4515	}
4516	}
4517	break;
4518	}
4519	////////////////////
4520	case DCACHE_SC_WAIT: // waiting VCI response to a SC transaction
4521	{
4522	// coherence clack request (from DSPIN CLACK)
4523	if ( r_dcache_clack_req.read() )
4524	{
4525	r_dcache_fsm = DCACHE_CC_CHECK;
4526	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4527	break;
4528	}
4529
4530	// coherence request (from CC_RECEIVE FSM)
4531	if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
4532	{
4533	r_dcache_fsm = DCACHE_CC_CHECK;
4534	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4535	break;
4536	}
4537
4538	if ( r_vci_rsp_data_error.read() ) // bus error
4539	{
4540	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
4541	r_mmu_dbvar = m_dreq.addr;
4542	r_vci_rsp_data_error = false;
4543	m_drsp.error = true;
4544	m_drsp.valid = true;
4545	r_dcache_fsm = DCACHE_IDLE;
4546	break;
4547	}
4548	else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
4549	{
4550	// consume response
4551	vci_rsp_fifo_dcache_get = true;
4552	m_drsp.valid = true;
4553	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
4554	r_dcache_fsm = DCACHE_IDLE;
4555	}
4556	break;
4557	}
4558	//////////////////////////
4559	case DCACHE_DIRTY_GET_PTE: // This sub_fsm set the PTE Dirty bit in memory
4560	// before handling a processor WRITE or SC request
4561	// Input argument is r_dcache_dirty_paddr
4562	// In this first state, we get PTE value in dcache
4563	// and post a CAS request to CMD FSM
4564	{
4565	// get PTE in dcache
4566	uint32_t pte;
4567	size_t way;
4568	size_t set;
4569	size_t word; // unused
4570	int state;
4571
4572	#ifdef INSTRUMENTATION
4573	m_cpt_dcache_data_read++;
4574	m_cpt_dcache_dir_read++;
4575	#endif
4576	r_dcache.read( r_dcache_dirty_paddr.read(),
4577	&pte,
4578	&way,
4579	&set,
4580	&word,
4581	&state );
4582
4583	assert( (state == CACHE_SLOT_STATE_VALID) and
4584	"error in DCACHE_DIRTY_TLB_SET: the PTE should be in dcache" );
4585
4586	// request CAS transaction to CMD_FSM
4587	r_dcache_dirty_way = way;
4588	r_dcache_dirty_set = set;
4589
4590	// check llsc reservation buffer
4591	if (r_dcache_llsc_paddr.read() == r_dcache_dirty_paddr.read() )
4592	r_dcache_llsc_valid = false;
4593
4594	// request a CAS CMD and go to DCACHE_DIRTY_WAIT state
4595	r_dcache_vci_cas_req = true;
4596	r_dcache_vci_paddr = r_dcache_dirty_paddr.read();
4597	r_dcache_vci_cas_old = pte;
4598	r_dcache_vci_cas_new = pte \| PTE_D_MASK;
4599	r_dcache_fsm = DCACHE_DIRTY_WAIT;
4600
4601	#if DEBUG_DCACHE
4602	if ( m_debug_dcache_fsm )
4603	{
4604	std::cout << " <PROC " << name()
4605	<< " DCACHE_DIRTY_GET_PTE> CAS request" << std::hex
4606	<< " / PTE_PADDR = " << r_dcache_dirty_paddr.read()
4607	<< " / PTE_VALUE = " << pte << std::dec
4608	<< " / SET = " << set
4609	<< " / WAY = " << way << std::endl;
4610	}
4611	#endif
4612	break;
4613	}
4614	///////////////////////
4615	case DCACHE_DIRTY_WAIT: // wait completion of CAS for PTE Dirty bit,
4616	// and return to IDLE state when response is received.
4617	// we don't care if the CAS is a failure:
4618	// - if the CAS is a success, the coherence mechanism
4619	// updates the local copy.
4620	// - if the CAS is a failure, we just retry the write.
4621	{
4622	// coherence clack request (from DSPIN CLACK)
4623	if ( r_dcache_clack_req.read() )
4624	{
4625	r_dcache_fsm = DCACHE_CC_CHECK;
4626	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4627	break;
4628	}
4629
4630	// coherence request (from CC_RECEIVE FSM)
4631	if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
4632	{
4633	r_dcache_fsm = DCACHE_CC_CHECK;
4634	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4635	break;
4636	}
4637
4638	if ( r_vci_rsp_data_error.read() ) // bus error
4639	{
4640	std::cout << "BUS ERROR in DCACHE_DIRTY_WAIT state" << std::endl;
4641	std::cout << "This should not happen in this state" << std::endl;
4642	exit(0);
4643	}
4644	else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
4645	{
4646	vci_rsp_fifo_dcache_get = true;
4647	r_dcache_fsm = DCACHE_IDLE;
4648
4649	#if DEBUG_DCACHE
4650	if ( m_debug_dcache_fsm )
4651	{
4652	std::cout << " <PROC " << name()
4653	<< " DCACHE_DIRTY_WAIT> CAS completed" << std::endl;
4654	}
4655	#endif
4656	}
4657	break;
4658	}
4659	/////////////////////
4660	case DCACHE_CC_CHECK: // This state is the entry point for the sub-FSM
4661	// handling coherence requests for DCACHE.
4662	// If there is a matching pending miss on the modified cache
4663	// line this is signaled in the r_dcache_miss inval flip-flop.
4664	// If the updated (or invalidated) cache line has copies in TLBs
4665	// these TLB copies are invalidated.
4666	// The return state is defined in r_dcache_fsm_cc_save
4667	{
4668	paddr_t paddr = r_cc_receive_dcache_nline.read() * m_dcache_words * 4;
4669	paddr_t mask = ~((m_dcache_words<<2)-1);
4670
4671	// CLACK handler
4672	// We switch the directory slot to EMPTY state and reset
4673	// r_dcache_miss_clack if the cleanup ack is matching a pending miss.
4674	if ( r_dcache_clack_req.read() )
4675	{
4676	if ( m_dreq.valid ) m_cost_data_miss_frz++;
4677
4678	#ifdef INSTRUMENTATION
4679	m_cpt_dcache_dir_write++;
4680	#endif
4681	r_dcache.write_dir( 0,
4682	r_dcache_clack_way.read(),
4683	r_dcache_clack_set.read(),
4684	CACHE_SLOT_STATE_EMPTY);
4685
4686	if ( (r_dcache_miss_set.read() == r_dcache_clack_set.read()) and
4687	(r_dcache_miss_way.read() == r_dcache_clack_way.read()) )
4688	{
4689	r_dcache_miss_clack = false;
4690	}
4691
4692	r_dcache_clack_req = false;
4693
4694	// return to cc_save state
4695	r_dcache_fsm = r_dcache_fsm_cc_save.read() ;
4696
4697	#if DEBUG_DCACHE
4698	if ( m_debug_dcache_fsm )
4699	{
4700	std::cout << " <PROC " << name()
4701	<< " DCACHE_CC_CHECK> CLACK for PADDR " << paddr
4702	<< " Switch slot to EMPTY state : "
4703	<< " set = " << r_dcache_clack_set.read()
4704	<< " / way = " << r_dcache_clack_way.read() << std::endl;
4705	}
4706	#endif
4707	break;
4708	}
4709
4710	assert ( not r_dcache_cc_send_req.read() and
4711	"CC_SEND must be available in DCACHE_CC_CHECK" );
4712
4713	// Match between MISS address and CC address
4714	if (r_cc_receive_dcache_req.read() and
4715	((r_dcache_fsm_cc_save == DCACHE_MISS_SELECT ) or
4716	(r_dcache_fsm_cc_save == DCACHE_MISS_WAIT ) or
4717	(r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT)) and
4718	((r_dcache_vci_paddr.read() & mask) == (paddr & mask))) // matching
4719	{
4720	// signaling matching
4721	r_dcache_miss_inval = true;
4722
4723	// in case of update, go to CC_UPDT
4724	// JUST TO POP THE FIFO
4725	if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT)
4726	{
4727	r_dcache_fsm = DCACHE_CC_UPDT;
4728	r_dcache_cc_word = r_cc_receive_word_idx.read();
4729
4730	// just pop the fifo , don't write in icache
4731	r_dcache_cc_need_write = false;
4732	}
4733	// the request is dealt with
4734	else
4735	{
4736	r_cc_receive_dcache_req = false;
4737	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4738	}
4739
4740	#if DEBUG_DCACHE
4741	if ( m_debug_dcache_fsm )
4742	{
4743	std::cout << " <PROC " << name()
4744	<< " DCACHE_CC_CHECK> Coherence request matching a pending miss:"
4745	<< " PADDR = " << std::hex << paddr << std::endl;
4746	}
4747	#endif
4748	}
4749
4750	// CC request handler
4751
4752	int state = 0;
4753	size_t way = 0;
4754	size_t set = 0;
4755	size_t word = 0;
4756
4757	#ifdef INSTRUMENTATION
4758	m_cpt_dcache_dir_read++;
4759	#endif
4760	r_dcache.read_dir( paddr,
4761	&state,
4762	&way,
4763	&set,
4764	&word ); // unused
4765
4766	r_dcache_cc_way = way;
4767	r_dcache_cc_set = set;
4768
4769	if ( state == CACHE_SLOT_STATE_VALID) // hit
4770	{
4771	// need to update the cache state
4772	if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT) // hit update
4773	{
4774	r_dcache_cc_need_write = true;
4775	r_dcache_fsm = DCACHE_CC_UPDT;
4776	r_dcache_cc_word = r_cc_receive_word_idx.read();
4777	}
4778	else if ( r_cc_receive_dcache_type.read() == CC_TYPE_INVAL ) // hit inval
4779	{
4780	r_dcache_fsm = DCACHE_CC_INVAL;
4781	}
4782	}
4783	else // miss
4784	{
4785	// multicast acknowledgement required in case of update
4786	if(r_cc_receive_dcache_type.read() == CC_TYPE_UPDT)
4787	{
4788	r_dcache_fsm = DCACHE_CC_UPDT;
4789	r_dcache_cc_word = r_cc_receive_word_idx.read();
4790
4791	// just pop the fifo , don't write in icache
4792	r_dcache_cc_need_write = false;
4793	}
4794	else // No response needed
4795	{
4796	r_cc_receive_dcache_req = false;
4797	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4798	}
4799	}
4800
4801	#if DEBUG_DCACHE
4802	if ( m_debug_dcache_fsm )
4803	{
4804	std::cout << " <PROC " << name()
4805	<< " DCACHE_CC_CHECK> Coherence request received:"
4806	<< " PADDR = " << std::hex << paddr
4807	<< " / TYPE = " << std::dec << r_cc_receive_dcache_type.read()
4808	<< " / HIT = " << (state == CACHE_SLOT_STATE_VALID) << std::endl;
4809	}
4810	#endif
4811
4812	break;
4813	}
4814	/////////////////////
4815	case DCACHE_CC_INVAL: // hit inval: switch slot to ZOMBI state and send a
4816	// CLEANUP after possible invalidation of copies in
4817	// TLBs
4818	{
4819	size_t way = r_dcache_cc_way.read();
4820	size_t set = r_dcache_cc_set.read();
4821
4822	if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // selective TLB inval
4823	{
4824	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
4825	r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read();
4826	r_dcache_tlb_inval_set = 0;
4827	r_dcache_fsm_scan_save = r_dcache_fsm.read();
4828	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4829	break;
4830	}
4831
4832	if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // TLB flush
4833	{
4834	r_itlb.reset();
4835	r_dtlb.reset();
4836	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
4837
4838	#if DEBUG_DCACHE
4839	if ( m_debug_dcache_fsm )
4840	{
4841	std::cout << " <PROC " << name()
4842	<< " DCACHE_CC_INVAL> Flush DTLB & ITLB" << std::endl;
4843	}
4844	#endif
4845	}
4846
4847	assert (not r_dcache_cc_send_req.read() &&
4848	"ERROR in DCACHE_CC_INVAL: the r_dcache_cc_send_req "
4849	"must not be set");
4850
4851	// Switch slot state to ZOMBI and send CLEANUP command
4852	r_dcache.write_dir( way,
4853	set,
4854	CACHE_SLOT_STATE_ZOMBI );
4855
4856	// coherence request completed
4857	r_cc_receive_dcache_req = false;
4858	r_dcache_cc_send_req = true;
4859	r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read();
4860	r_dcache_cc_send_way = r_dcache_cc_way.read();
4861	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
4862	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4863
4864	#if DEBUG_DCACHE
4865	if ( m_debug_dcache_fsm )
4866	{
4867	std::cout << " <PROC " << name()
4868	<< " DCACHE_CC_INVAL> Switch slot to EMPTY state:" << std::dec
4869	<< " / WAY = " << way
4870	<< " / SET = " << set << std::endl;
4871	}
4872	#endif
4873	break;
4874	}
4875	///////////////////
4876	case DCACHE_CC_UPDT: // hit update: write one word per cycle,
4877	// after possible invalidation of copies in TLBs
4878	{
4879	size_t word = r_dcache_cc_word.read();
4880	size_t way = r_dcache_cc_way.read();
4881	size_t set = r_dcache_cc_set.read();
4882
4883	if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // selective TLB inval
4884	{
4885	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
4886	r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read();
4887	r_dcache_tlb_inval_set = 0;
4888	r_dcache_fsm_scan_save = r_dcache_fsm.read();
4889	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4890
4891	break;
4892	}
4893
4894	if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // TLB flush
4895	{
4896	r_itlb.reset();
4897	r_dtlb.reset();
4898	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
4899
4900	#if DEBUG_DCACHE
4901	if ( m_debug_dcache_fsm )
4902	{
4903	std::cout << " <PROC " << name()
4904	<< " DCACHE_CC_UPDT> Flush DTLB & ITLB" << std::endl;
4905	}
4906	#endif
4907	}
4908
4909	assert (not r_dcache_cc_send_req.read() &&
4910	"ERROR in DCACHE_CC_INVAL: the r_dcache_cc_send_req "
4911	"must not be set");
4912
4913	if ( not r_cc_receive_updt_fifo_be.rok() ) break;
4914
4915	if (r_dcache_cc_need_write.read())
4916	{
4917
4918	#ifdef INSTRUMENTATION
4919	m_cpt_dcache_data_write++;
4920	#endif
4921	r_dcache.write( way,
4922	set,
4923	word,
4924	r_cc_receive_updt_fifo_data.read(),
4925	r_cc_receive_updt_fifo_be.read() );
4926
4927	r_dcache_cc_word = word + 1;
4928
4929	#if DEBUG_DCACHE
4930	if ( m_debug_dcache_fsm )
4931	{
4932	std::cout << " <PROC " << name()
4933	<< " DCACHE_CC_UPDT> Write one word" << std::dec
4934	<< " / WAY = " << way
4935	<< " / SET = " << set
4936	<< " / WORD = " << word
4937	<< " / VALUE = " << std::hex << r_cc_receive_updt_fifo_data.read() << std::endl;
4938	}
4939	#endif
4940	}
4941
4942	if ( r_cc_receive_updt_fifo_eop.read() ) // last word
4943	{
4944	// no need to write in the cache anymore
4945	r_dcache_cc_need_write = false;
4946
4947	// coherence request completed
4948	r_cc_receive_dcache_req = false;
4949
4950	// request multicast acknowledgement
4951	r_dcache_cc_send_req = true;
4952	r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read();
4953	r_dcache_cc_send_updt_tab_idx = r_cc_receive_dcache_updt_tab_idx.read();
4954	r_dcache_cc_send_type = CC_TYPE_MULTI_ACK;
4955
4956	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4957	}
4958
4959	//consume fifo if not eop
4960	cc_receive_updt_fifo_get = true;
4961
4962	break;
4963	}
4964	///////////////////////////
4965	case DCACHE_INVAL_TLB_SCAN: // Scan sequencially all sets for both ITLB & DTLB
4966	// It makes assumption: m_itlb_sets == m_dtlb_sets
4967	// All ways are handled in parallel.
4968	// We enter this state when a DCACHE line is modified,
4969	// and there is a copy in itlb or dtlb.
4970	// It can be caused by:
4971	// - a coherence inval or updt transaction,
4972	// - a line inval caused by a cache miss
4973	// - a processor XTN inval request,
4974	// - a WRITE hit,
4975	// - a Dirty bit update
4976	// Input arguments are:
4977	// - r_dcache_tlb_inval_line
4978	// - r_dcache_tlb_inval_set
4979	// - r_dcache_fsm_scan_save
4980	{
4981	paddr_t line = r_dcache_tlb_inval_line.read();
4982	size_t set = r_dcache_tlb_inval_set.read();
4983	size_t way;
4984	bool ok;
4985
4986	for ( way = 0 ; way < m_itlb_ways ; way++ )
4987	{
4988	ok = r_itlb.inval( line, way, set );
4989
4990	#if DEBUG_DCACHE
4991	if ( m_debug_dcache_fsm and ok )
4992	{
4993	std::cout << " <PROC " << name()
4994	<< ".DCACHE_INVAL_TLB_SCAN> Invalidate ITLB entry:" << std::hex
4995	<< " line = " << line << std::dec
4996	<< " / set = " << set
4997	<< " / way = " << way << std::endl;
4998	}
4999	#endif
5000	}
5001
5002	for ( way = 0 ; way < m_dtlb_ways ; way++ )
5003	{
5004	ok = r_dtlb.inval( line, way, set );
5005
5006	#if DEBUG_DCACHE
5007	if ( m_debug_dcache_fsm and ok )
5008	std::cout << " <PROC " << name() << " DCACHE_INVAL_TLB_SCAN>"
5009	<< " Invalidate DTLB entry" << std::hex
5010	<< " / line = " << line << std::dec
5011	<< " / set = " << set
5012	<< " / way = " << way << std::endl;
5013	#endif
5014	}
5015
5016	// return to the calling state when TLB inval completed
5017	if ( r_dcache_tlb_inval_set.read() == (m_dtlb_sets-1) )
5018	{
5019	r_dcache_fsm = r_dcache_fsm_scan_save.read();
5020	}
5021	r_dcache_tlb_inval_set = r_dcache_tlb_inval_set.read() + 1;
5022	break;
5023	}
5024	} // end switch r_dcache_fsm
5025
5026	///////////////// wbuf update ///////////////////////////////////////////////////////
5027	r_wbuf.update();
5028
5029	///////////////// llsc update ///////////////////////////////////////////////////////
5030	if (r_dcache_llsc_valid.read()) r_dcache_llsc_count = r_dcache_llsc_count.read() - 1;
5031	if (r_dcache_llsc_count.read() == 1) r_dcache_llsc_valid = false;
5032
5033	//////////////// test processor frozen //////////////////////////////////////////////
5034	// The simulation exit if the number of consecutive frozen cycles
5035	// is larger than the m_max_frozen_cycles (constructor parameter)
5036	if ( (m_ireq.valid and not m_irsp.valid) or (m_dreq.valid and not m_drsp.valid) )
5037	{
5038	m_cpt_frz_cycles++; // used for instrumentation
5039	m_cpt_stop_simulation++; // used for debug
5040	if ( m_cpt_stop_simulation > m_max_frozen_cycles )
5041	{
5042	std::cout << std::dec << "ERROR in CC_VCACHE_WRAPPER " << name() << std::endl
5043	<< " stop at cycle " << m_cpt_total_cycles << std::endl
5044	<< " frozen since cycle " << m_cpt_total_cycles - m_max_frozen_cycles
5045	<< std::endl;
5046	r_iss.dump();
5047	exit(1);
5048	}
5049	}
5050	else
5051	{
5052	m_cpt_stop_simulation = 0;
5053	}
5054
5055	/////////// execute one iss cycle /////////////////////////////////
5056	{
5057	uint32_t it = 0;
5058	for (size_t i=0; i<(size_t)iss_t::n_irq; i++) if(p_irq[i].read()) it \|= (1<<i);
5059	r_iss.executeNCycles(1, m_irsp, m_drsp, it);
5060	}
5061
5062	////////////////////////////////////////////////////////////////////////////
5063	// The VCI_CMD FSM controls the following ressources:
5064	// - r_vci_cmd_fsm
5065	// - r_vci_cmd_min
5066	// - r_vci_cmd_max
5067	// - r_vci_cmd_cpt
5068	// - r_vci_cmd_imiss_prio
5069	// - wbuf (reset)
5070	// - r_icache_miss_req (reset)
5071	// - r_icache_unc_req (reset)
5072	// - r_dcache_vci_miss_req (reset)
5073	// - r_dcache_vci_unc_req (reset)
5074	// - r_dcache_vci_ll_req (reset)
5075	// - r_dcache_vci_sc_req (reset in case of local sc fail)
5076	// - r_dcache_vci_cas_req (reset)
5077	//
5078	// This FSM handles requests from both the DCACHE FSM & the ICACHE FSM.
5079	// There are 8 request types, with the following priorities :
5080	// 1 - Data Read Miss : r_dcache_vci_miss_req and miss in the write buffer
5081	// 2 - Data Read Uncachable : r_dcache_vci_unc_req
5082	// 3 - Instruction Miss : r_icache_miss_req and miss in the write buffer
5083	// 4 - Instruction Uncachable : r_icache_unc_req
5084	// 5 - Data Write : r_wbuf.rok()
5085	// 6 - Data Linked Load : r_dcache_vci_ll_req
5086	// 7 - Data Store Conditionnal: r_dcache_vci_sc_req
5087	// 8 - Compare And Swap : r_dcache_vci_cas_req
5088	//
5089	// As we want to support several simultaneous VCI transactions, the VCI_CMD_FSM
5090	// and the VCI_RSP_FSM are fully desynchronized.
5091	//
5092	// VCI formats:
5093	// According to the VCI advanced specification, all read requests packets
5094	// (data Uncached, Miss data, instruction Uncached, Miss instruction)
5095	// are one word packets.
5096	// For write burst packets, all words are in the same cache line,
5097	// and addresses must be contiguous (the BE field is 0 in case of "holes").
5098	// The sc command packet implements actually a compare-and-swap mechanism
5099	// and the packet contains two flits.
5100	////////////////////////////////////////////////////////////////////////////////////
5101
5102
5103	switch ( r_vci_cmd_fsm.read() )
5104	{
5105	//////////////
5106	case CMD_IDLE:
5107	{
5108	// DCACHE read requests (r_dcache_vci_miss_req or r_dcache_vci_ll_req), and
5109	// ICACHE read requests (r_icache_miss_req) require both a write_buffer access
5110	// to check a possible pending write on the same cache line.
5111	// As there is only one possible access per cycle to write buffer, we implement
5112	// a round-robin priority between DCACHE and ICACHE for this access,
5113	// using the r_vci_cmd_imiss_prio flip-flop.
5114
5115	size_t wbuf_min;
5116	size_t wbuf_max;
5117
5118	bool dcache_miss_req = r_dcache_vci_miss_req.read() and
5119	( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() );
5120
5121	bool dcache_ll_req = r_dcache_vci_ll_req.read() and
5122	( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() );
5123
5124	bool dcache_sc_req = r_dcache_vci_sc_req.read() and
5125	( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() );
5126
5127	bool dcache_cas_req = r_dcache_vci_cas_req.read() and
5128	( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() );
5129
5130	bool icache_miss_req = r_icache_miss_req.read() and
5131	( not (r_dcache_vci_miss_req.read() or
5132	r_dcache_vci_ll_req.read() or
5133	r_dcache_vci_cas_req.read() or
5134	r_dcache_vci_sc_req.read())
5135	or r_vci_cmd_imiss_prio.read() );
5136
5137	// 1 - Data unc write
5138	if ( r_dcache_vci_unc_req.read() and r_dcache_vci_unc_write.read())
5139	{
5140	r_vci_cmd_fsm = CMD_DATA_UNC_WRITE;
5141	r_dcache_vci_unc_req = false;
5142	// m_cpt_dunc_transaction++;
5143	}
5144	// 2 data read miss
5145	else if ( dcache_miss_req and r_wbuf.miss(r_dcache_vci_paddr.read()) )
5146	{
5147	r_vci_cmd_fsm = CMD_DATA_MISS;
5148	r_dcache_vci_miss_req = false;
5149	r_vci_cmd_imiss_prio = true;
5150	// m_cpt_dmiss_transaction++;
5151	}
5152	// 3 - Data Read Uncachable
5153	else if ( r_dcache_vci_unc_req.read() and not r_dcache_vci_unc_write.read() )
5154	{
5155	r_vci_cmd_fsm = CMD_DATA_UNC_READ;
5156	r_dcache_vci_unc_req = false;
5157	// m_cpt_dunc_transaction++;
5158	}
5159	// 4 - Data Linked Load
5160	else if ( dcache_ll_req and r_wbuf.miss(r_dcache_vci_paddr.read()))
5161	{
5162	r_vci_cmd_fsm = CMD_DATA_LL;
5163	r_dcache_vci_ll_req = false;
5164	r_vci_cmd_imiss_prio = true;
5165	// m_cpt_ll_transaction++;
5166	}
5167	// 5 - Instruction Miss
5168	else if ( icache_miss_req and r_wbuf.miss(r_icache_vci_paddr.read()) )
5169	{
5170	r_vci_cmd_fsm = CMD_INS_MISS;
5171	r_icache_miss_req = false;
5172	r_vci_cmd_imiss_prio = false;
5173	// m_cpt_imiss_transaction++;
5174	}
5175	// 6 - Instruction Uncachable
5176	else if ( r_icache_unc_req.read() )
5177	{
5178	r_vci_cmd_fsm = CMD_INS_UNC;
5179	r_icache_unc_req = false;
5180	// m_cpt_iunc_transaction++;
5181	}
5182	// 7 - Data Write
5183	else if ( r_wbuf.rok(&wbuf_min, &wbuf_max) )
5184	{
5185	r_vci_cmd_fsm = CMD_DATA_WRITE;
5186	r_vci_cmd_cpt = wbuf_min;
5187	r_vci_cmd_min = wbuf_min;
5188	r_vci_cmd_max = wbuf_max;
5189	// m_cpt_write_transaction++;
5190	// m_length_write_transaction += (wbuf_max-wbuf_min+1);
5191	}
5192	// 8 - Data Store Conditionnal
5193	else if ( dcache_sc_req and r_wbuf.miss(r_dcache_vci_paddr.read()) )
5194	{
5195	r_vci_cmd_fsm = CMD_DATA_SC;
5196	r_dcache_vci_sc_req = false;
5197	r_vci_cmd_imiss_prio = true;
5198	r_vci_cmd_cpt = 0;
5199	// m_cpt_sc_transaction++;
5200	}
5201	// 9 - Compare And Swap
5202	else if ( dcache_cas_req and r_wbuf.miss(r_dcache_vci_paddr.read()) )
5203	{
5204	r_vci_cmd_fsm = CMD_DATA_CAS;
5205	r_dcache_vci_cas_req = false;
5206	r_vci_cmd_imiss_prio = true;
5207	r_vci_cmd_cpt = 0;
5208	// m_cpt_cas_transaction++;
5209	}
5210
5211	#if DEBUG_CMD
5212	if ( m_debug_cmd_fsm )
5213	{
5214	std::cout << " <PROC " << name() << " CMD_IDLE>"
5215	<< " / dmiss_req = " << dcache_miss_req
5216	<< " / imiss_req = " << icache_miss_req
5217	<< std::endl;
5218	}
5219	#endif
5220	break;
5221	}
5222	////////////////////
5223	case CMD_DATA_WRITE:
5224	{
5225	if ( p_vci.cmdack.read() )
5226	{
5227	r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
5228	if (r_vci_cmd_cpt == r_vci_cmd_max) // last flit sent
5229	{
5230	r_vci_cmd_fsm = CMD_IDLE ;
5231	r_wbuf.sent() ;
5232	}
5233	}
5234	break;
5235	}
5236	/////////////////
5237	case CMD_DATA_SC:
5238	case CMD_DATA_CAS:
5239	{
5240	// The CAS and SC VCI commands contain two flits
5241	if ( p_vci.cmdack.read() )
5242	{
5243	r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
5244	if (r_vci_cmd_cpt == 1) r_vci_cmd_fsm = CMD_IDLE ;
5245	}
5246	break;
5247	}
5248	//////////////////
5249	case CMD_INS_MISS:
5250	case CMD_INS_UNC:
5251	case CMD_DATA_MISS:
5252	case CMD_DATA_UNC_READ:
5253	case CMD_DATA_UNC_WRITE:
5254	case CMD_DATA_LL:
5255	{
5256	// all read VCI commands contain one single flit
5257	if ( p_vci.cmdack.read() ) {
5258	r_vci_cmd_fsm = CMD_IDLE;
5259	}
5260	break;
5261	}
5262
5263	} // end switch r_vci_cmd_fsm
5264
5265	//////////////////////////////////////////////////////////////////////////
5266	// The VCI_RSP FSM controls the following ressources:
5267	// - r_vci_rsp_fsm:
5268	// - r_vci_rsp_fifo_icache (push)
5269	// - r_vci_rsp_fifo_dcache (push)
5270	// - r_vci_rsp_data_error (set)
5271	// - r_vci_rsp_ins_error (set)
5272	// - r_vci_rsp_cpt
5273	// - r_dcache_vci_sc_req (reset when SC response recieved)
5274	//
5275	// As the VCI_RSP and VCI_CMD are fully desynchronized to support several
5276	// simultaneous VCI transactions, this FSM uses the VCI RPKTID field
5277	// to identify the transactions.
5278	//
5279	// VCI vormat:
5280	// This component checks the response packet length and accepts only
5281	// single word packets for write response packets.
5282	//
5283	// Error handling:
5284	// This FSM analyzes the VCI error code and signals directly the Write Bus Error.
5285	// In case of Read Data Error, the VCI_RSP FSM sets the r_vci_rsp_data_error
5286	// flip_flop and the error is signaled by the DCACHE FSM.
5287	// In case of Instruction Error, the VCI_RSP FSM sets the r_vci_rsp_ins_error
5288	// flip_flop and the error is signaled by the ICACHE FSM.
5289	// In case of Cleanup Error, the simulation stops with an error message...
5290	//////////////////////////////////////////////////////////////////////////
5291
5292	switch ( r_vci_rsp_fsm.read() )
5293	{
5294	//////////////
5295	case RSP_IDLE:
5296	{
5297	if ( p_vci.rspval.read() )
5298	{
5299	r_vci_rsp_cpt = 0;
5300
5301	if ( (p_vci.rpktid.read() & 0x7) == TYPE_DATA_UNC )
5302	{
5303	r_vci_rsp_fsm = RSP_DATA_UNC;
5304	}
5305	else if ( (p_vci.rpktid.read() & 0x7) == TYPE_READ_DATA_MISS )
5306	{
5307	r_vci_rsp_fsm = RSP_DATA_MISS;
5308	}
5309	else if ( (p_vci.rpktid.read() & 0x7) == TYPE_READ_INS_UNC )
5310	{
5311	r_vci_rsp_fsm = RSP_INS_UNC;
5312	}
5313	else if ( (p_vci.rpktid.read() & 0x7) == TYPE_READ_INS_MISS )
5314	{
5315	r_vci_rsp_fsm = RSP_INS_MISS;
5316	}
5317	else if ( (p_vci.rpktid.read() & 0x7) == TYPE_WRITE )
5318	{
5319	r_vci_rsp_fsm = RSP_DATA_WRITE;
5320	}
5321	else if ( (p_vci.rpktid.read() & 0x7) == TYPE_CAS )
5322	{
5323	r_vci_rsp_fsm = RSP_DATA_UNC;
5324	}
5325	else if ( (p_vci.rpktid.read() & 0x7) == TYPE_LL )
5326	{
5327	r_vci_rsp_fsm = RSP_DATA_LL;
5328	}
5329	else if ( (p_vci.rpktid.read() & 0x7) == TYPE_SC )
5330	{
5331	r_vci_rsp_fsm = RSP_DATA_UNC;
5332	}
5333	else
5334	{
5335	assert(false and "Unexpected VCI response");
5336	}
5337	}
5338	break;
5339	}
5340	//////////////////
5341	case RSP_INS_MISS:
5342	{
5343	if ( p_vci.rspval.read() )
5344	{
5345	if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported
5346	{
5347	r_vci_rsp_ins_error = true;
5348	if ( p_vci.reop.read() ) r_vci_rsp_fsm = RSP_IDLE;
5349	}
5350	else // no error reported
5351	{
5352	if ( r_vci_rsp_fifo_icache.wok() )
5353	{
5354	if ( r_vci_rsp_cpt.read() >= m_icache_words )
5355	{
5356	std::cout << "ERROR in VCI_CC_VCACHE " << name()
5357	<< " VCI response packet too long "
5358	<< " for instruction miss" << std::endl;
5359	exit(0);
5360	}
5361	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
5362	vci_rsp_fifo_icache_put = true,
5363	vci_rsp_fifo_icache_data = p_vci.rdata.read();
5364	if ( p_vci.reop.read() )
5365	{
5366	if ( r_vci_rsp_cpt.read() != (m_icache_words - 1) )
5367	{
5368	std::cout << "ERROR in VCI_CC_VCACHE " << name()
5369	<< " VCI response packet too short"
5370	<< " for instruction miss" << std::endl;
5371	exit(0);
5372	}
5373	r_vci_rsp_fsm = RSP_IDLE;
5374	}
5375	}
5376	}
5377	}
5378	break;
5379	}
5380	/////////////////
5381	case RSP_INS_UNC:
5382	{
5383	if (p_vci.rspval.read() )
5384	{
5385	assert( p_vci.reop.read() and
5386	"illegal VCI response packet for uncachable instruction");
5387
5388	if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported
5389	{
5390	r_vci_rsp_ins_error = true;
5391	r_vci_rsp_fsm = RSP_IDLE;
5392	}
5393	else // no error reported
5394	{
5395	if ( r_vci_rsp_fifo_icache.wok())
5396	{
5397	vci_rsp_fifo_icache_put = true;
5398	vci_rsp_fifo_icache_data = p_vci.rdata.read();
5399	r_vci_rsp_fsm = RSP_IDLE;
5400	}
5401	}
5402	}
5403	break;
5404	}
5405	///////////////////
5406	case RSP_DATA_MISS:
5407	{
5408	if ( p_vci.rspval.read() )
5409	{
5410	if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported
5411	{
5412	r_vci_rsp_data_error = true;
5413	if ( p_vci.reop.read() ) r_vci_rsp_fsm = RSP_IDLE;
5414	}
5415	else // no error reported
5416	{
5417	if ( r_vci_rsp_fifo_dcache.wok() )
5418	{
5419	assert( (r_vci_rsp_cpt.read() < m_dcache_words) and
5420	"The VCI response packet for data miss is too long");
5421
5422	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
5423	vci_rsp_fifo_dcache_put = true,
5424	vci_rsp_fifo_dcache_data = p_vci.rdata.read();
5425	if ( p_vci.reop.read() )
5426	{
5427	assert( (r_vci_rsp_cpt.read() == m_dcache_words - 1) and
5428	"The VCI response packet for data miss is too short");
5429
5430	r_vci_rsp_fsm = RSP_IDLE;
5431	}
5432	}
5433	}
5434	}
5435	break;
5436	}
5437	//////////////////
5438	case RSP_DATA_UNC:
5439	{
5440	if (p_vci.rspval.read() )
5441	{
5442	assert( p_vci.reop.read() and
5443	"illegal VCI response packet for uncachable read data");
5444
5445	if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported
5446	{
5447	r_vci_rsp_data_error = true;
5448	r_vci_rsp_fsm = RSP_IDLE;
5449	}
5450	else // no error reported
5451	{
5452	if ( r_vci_rsp_fifo_dcache.wok())
5453	{
5454	vci_rsp_fifo_dcache_put = true;
5455	vci_rsp_fifo_dcache_data = p_vci.rdata.read();
5456	r_vci_rsp_fsm = RSP_IDLE;
5457	}
5458	}
5459	}
5460	break;
5461	}
5462	/////////////////
5463	case RSP_DATA_LL:
5464	{
5465	if ( p_vci.rspval.read() )
5466	{
5467	if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported
5468	{
5469	r_vci_rsp_data_error = true;
5470	r_vci_rsp_fsm = RSP_IDLE;
5471	break;
5472	}
5473	if (r_vci_rsp_cpt.read() == 0) //first flit
5474	{
5475	if(r_vci_rsp_fifo_dcache.wok())
5476	{
5477	assert(!p_vci.reop.read() &&
5478	"illegal VCI response packet for LL");
5479	vci_rsp_fifo_dcache_put = true;
5480	vci_rsp_fifo_dcache_data = p_vci.rdata.read();
5481	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
5482	}
5483	break;
5484	}
5485	else // last flit
5486	{
5487	if(r_vci_rsp_fifo_dcache.wok())
5488	{
5489	assert(p_vci.reop.read() &&
5490	"illegal VCI response packet for LL");
5491	vci_rsp_fifo_dcache_put = true;
5492	vci_rsp_fifo_dcache_data = p_vci.rdata.read();
5493	r_vci_rsp_fsm = RSP_IDLE;
5494	}
5495	break;
5496	}
5497	}
5498	break;
5499	}
5500	////////////////////
5501	case RSP_DATA_WRITE:
5502	{
5503	if (p_vci.rspval.read())
5504	{
5505	assert( p_vci.reop.read() and
5506	"a VCI response packet must contain one flit for a write transaction");
5507
5508	r_vci_rsp_fsm = RSP_IDLE;
5509	uint32_t wbuf_index = p_vci.rtrdid.read();
5510	r_wbuf.completed(wbuf_index);
5511	if ( (p_vci.rerror.read()&0x1) != 0 ) r_iss.setWriteBerr();
5512	}
5513	break;
5514	}
5515	} // end switch r_vci_rsp_fsm
5516
5517	/////////////////////////////////////////////////////////////////////////////////////
5518	// The CC_SEND FSM is in charge of sending cleanups and the multicast
5519	// acknowledgements on the coherence network. It has two clients (DCACHE FSM
5520	// and ICACHE FSM) that are served with a round-robin priority.
5521	// The CC_SEND FSM resets the r_*cache_cc_send_req request flip-flops as
5522	// soon as the request has been sent.
5523	/////////////////////////////////////////////////////////////////////////////////////
5524	switch ( r_cc_send_fsm.read() )
5525	{
5526	///////////////////////////
5527	case CC_SEND_IDLE:
5528	{
5529	///////////////////////////////////////////////////////
5530	// handling round robin between icache and dcache : //
5531	// we first check for the last client and listen for //
5532	// a request of the other, then update the client //
5533	// r_cc_send_last_client : 0 dcache / 1 icache
5534	///////////////////////////////////////////////////////
5535	bool update_last_client = r_cc_send_last_client.read();
5536	if ( r_cc_send_last_client.read() == 0 ) // last client was dcache
5537	{
5538	if (r_icache_cc_send_req.read()) // request from icache
5539	update_last_client = 1; // update last client to icache
5540	}
5541	else // last client was icache
5542	{
5543	if (r_dcache_cc_send_req.read()) // request from dcache
5544	update_last_client = 0; // update last client to dcache
5545	}
5546	r_cc_send_last_client = update_last_client;
5547
5548	// if there is an actual request
5549	if (r_dcache_cc_send_req.read() or r_icache_cc_send_req.read())
5550	{
5551	// the new client is dcache and has a cleanup request
5552	if ( (update_last_client == 0) and
5553	(r_dcache_cc_send_type.read() == CC_TYPE_CLEANUP))
5554	r_cc_send_fsm = CC_SEND_CLEANUP_1;
5555	// the new client is dcache and has a multi acknowledgement request
5556	else if ( (update_last_client == 0) and
5557	(r_dcache_cc_send_type.read() == CC_TYPE_MULTI_ACK))
5558	r_cc_send_fsm = CC_SEND_MULTI_ACK;
5559	// the new client is icache and has a cleanup request
5560	else if ( (update_last_client == 1) and
5561	(r_icache_cc_send_type.read() == CC_TYPE_CLEANUP))
5562	r_cc_send_fsm = CC_SEND_CLEANUP_1;
5563	// the new client is icache and has a multi acknowledgement request
5564	else if ( (update_last_client == 1) and
5565	(r_icache_cc_send_type.read() == CC_TYPE_MULTI_ACK))
5566	r_cc_send_fsm = CC_SEND_MULTI_ACK;
5567	}
5568	break;
5569	}
5570	///////////////////////////
5571	case CC_SEND_CLEANUP_1:
5572	{
5573	// wait for the first flit to be consumed
5574	if (p_dspin_p2m.read.read())
5575	r_cc_send_fsm = CC_SEND_CLEANUP_2;
5576
5577	break;
5578	}
5579	///////////////////////////
5580	case CC_SEND_CLEANUP_2:
5581	{
5582	// wait for the second flit to be consumed
5583	if (p_dspin_p2m.read.read())
5584	{
5585	if (r_cc_send_last_client.read() == 0) // dcache active request
5586	r_dcache_cc_send_req = false; // reset dcache request
5587	else // icache active request
5588	r_icache_cc_send_req = false; // reset icache request
5589
5590	// go back to idle state
5591	r_cc_send_fsm = CC_SEND_IDLE;
5592	}
5593	break;
5594	}
5595	///////////////////////////
5596	case CC_SEND_MULTI_ACK:
5597	{
5598	// wait for the flit to be consumed
5599	if(p_dspin_p2m.read.read())
5600	{
5601	if(r_cc_send_last_client.read() == 0) // dcache active request
5602	r_dcache_cc_send_req = false; // reset dcache request
5603	else // icache active request
5604	r_icache_cc_send_req = false; // reset icache request
5605	// go back to idle state
5606	r_cc_send_fsm = CC_SEND_IDLE;
5607	}
5608	break;
5609	}
5610	} // end switch CC_SEND FSM
5611
5612	///////////////////////////////////////////////////////////////////////////////
5613	// CC_RECEIVE FSM
5614	// This FSM receive all coherence packets on a DSPIN40 port.
5615	// There is 5 packet types:
5616	// - CC_DATA_INVAL : DCACHE invalidate request
5617	// - CC_DATA_UPDT : DCACHE update request (multi-words)
5618	// - CC_INST_INVAL : ICACHE invalidate request
5619	// - CC_INST_UPDT : ICACHE update request (multi-words)
5620	// - CC_BROADCAST : Broadcast invalidate request (both DCACHE & ICACHE)
5621	//////////////////////////////////////////////////////////////////////////////
5622	switch( r_cc_receive_fsm.read() )
5623	{
5624	/////////////////////
5625	case CC_RECEIVE_IDLE:
5626	{
5627	// a coherence request has arrived
5628	if (p_dspin_m2p.write.read())
5629	{
5630	// initialize dspin received data
5631	uint64_t receive_data = p_dspin_m2p.data.read();
5632	// initialize coherence packet type
5633	uint64_t receive_type = DspinDhccpParam::dspin_get(receive_data,
5634	DspinDhccpParam::M2P_TYPE);
5635	// test for a broadcast
5636	if (DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::M2P_BC))
5637	{
5638	r_cc_receive_fsm = CC_RECEIVE_BRDCAST_HEADER;
5639	}
5640	// test for a multi updt
5641	else if (receive_type == DspinDhccpParam::TYPE_MULTI_UPDT_DATA)
5642	{
5643	r_cc_receive_fsm = CC_RECEIVE_DATA_UPDT_HEADER;
5644	}
5645	else if (receive_type == DspinDhccpParam::TYPE_MULTI_UPDT_INST)
5646	{
5647	r_cc_receive_fsm = CC_RECEIVE_INS_UPDT_HEADER;
5648	}
5649	// test for a multi inval
5650	else if (receive_type == DspinDhccpParam::TYPE_MULTI_INVAL_DATA)
5651	{
5652	r_cc_receive_fsm = CC_RECEIVE_DATA_INVAL_HEADER;
5653	}
5654	else
5655	{
5656	r_cc_receive_fsm = CC_RECEIVE_INS_INVAL_HEADER;
5657	}
5658	}
5659	break;
5660	}
5661	///////////////////////////////
5662	case CC_RECEIVE_BRDCAST_HEADER:
5663	{
5664	// no actual data in the HEADER, just skip to second flit
5665	r_cc_receive_fsm = CC_RECEIVE_BRDCAST_NLINE;
5666	break;
5667	}
5668	//////////////////////////////
5669	case CC_RECEIVE_BRDCAST_NLINE:
5670	{
5671	// initialize dspin received data
5672	uint64_t receive_data = p_dspin_m2p.data.read();
5673	// wait for both dcache and icache to take the request
5674	// TODO maybe we need to wait for both only to leave the state, but
5675	// not to actually post a request to an available cache => need a
5676	// flip_flop to check that ?
5677	if (not (r_cc_receive_icache_req.read()) and
5678	not (r_cc_receive_dcache_req.read()) and
5679	(p_dspin_m2p.write.read()))
5680	{
5681	// request dcache to handle the BROADCAST
5682	r_cc_receive_dcache_req = true;
5683	r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,
5684	DspinDhccpParam::BROADCAST_NLINE);
5685	r_cc_receive_dcache_type = CC_TYPE_INVAL;
5686	// request icache to handle the BROADCAST
5687	r_cc_receive_icache_req = true;
5688	r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,
5689	DspinDhccpParam::BROADCAST_NLINE);
5690	r_cc_receive_icache_type = CC_TYPE_INVAL;
5691	// get back to idle state
5692	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5693	break;
5694	}
5695	// keep waiting for the caches to accept the request
5696	break;
5697	}
5698	/////////////////////////////
5699	case CC_RECEIVE_DATA_INVAL_HEADER:
5700	{
5701	// sample updt tab index in the HEADER, then skip to second flit
5702	r_cc_receive_fsm = CC_RECEIVE_DATA_INVAL_NLINE;
5703	break;
5704	}
5705	/////////////////////////////
5706	case CC_RECEIVE_INS_INVAL_HEADER:
5707	{
5708	// sample updt tab index in the HEADER, then skip to second flit
5709	r_cc_receive_fsm = CC_RECEIVE_INS_INVAL_NLINE;
5710	break;
5711	}
5712	////////////////////////////
5713	case CC_RECEIVE_DATA_INVAL_NLINE:
5714	{
5715	// sample nline in the second flit
5716	uint64_t receive_data = p_dspin_m2p.data.read();
5717	// for data INVAL, wait for dcache to take the request
5718	if (p_dspin_m2p.write.read() and
5719	not r_cc_receive_dcache_req.read() )
5720	{
5721	// request dcache to handle the INVAL
5722	r_cc_receive_dcache_req = true;
5723	r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_NLINE);
5724	r_cc_receive_dcache_type = CC_TYPE_INVAL;
5725	// get back to idle state
5726	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5727	break;
5728	}
5729	break;
5730	}
5731	//////////////////////////////
5732	case CC_RECEIVE_INS_INVAL_NLINE:
5733	{
5734	// sample nline in the second flit
5735	uint64_t receive_data = p_dspin_m2p.data.read();
5736	// for ins INVAL, wait for icache to take the request
5737	if (p_dspin_m2p.write.read() and
5738	not r_cc_receive_icache_req.read() )
5739	{
5740	// request icache to handle the INVAL
5741	r_cc_receive_icache_req = true;
5742	r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_NLINE);
5743	r_cc_receive_icache_type = CC_TYPE_INVAL;
5744	// get back to idle state
5745	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5746	break;
5747	}
5748	break;
5749	}
5750	////////////////////////////
5751	case CC_RECEIVE_DATA_UPDT_HEADER:
5752	{
5753	// sample updt tab index in the HEADER, than skip to second flit
5754	uint64_t receive_data = p_dspin_m2p.data.read();
5755	// for data INVAL, wait for dcache to take the request and fifo to
5756	// be empty
5757	if (not r_cc_receive_dcache_req.read())
5758	{
5759	r_cc_receive_dcache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_UPDT_INDEX);
5760	r_cc_receive_fsm = CC_RECEIVE_DATA_UPDT_NLINE;
5761	break;
5762	}
5763	break;
5764	}
5765	////////////////////////////
5766	case CC_RECEIVE_INS_UPDT_HEADER:
5767	{
5768	// sample updt tab index in the HEADER, than skip to second flit
5769	uint64_t receive_data = p_dspin_m2p.data.read();
5770	// for ins INVAL, wait for icache to take the request and fifo to be
5771	// empty
5772	if (not r_cc_receive_icache_req.read())
5773	{
5774	r_cc_receive_icache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_UPDT_INDEX);
5775	r_cc_receive_fsm = CC_RECEIVE_INS_UPDT_NLINE;
5776	break;
5777	}
5778	// keep waiting for the correct cache to accept the request
5779	break;
5780	}
5781	///////////////////////////
5782	case CC_RECEIVE_DATA_UPDT_NLINE:
5783	{
5784	// sample nline and word index in the second flit
5785	uint64_t receive_data = p_dspin_m2p.data.read();
5786	// for data INVAL, wait for dcache to take the request and fifo to
5787	// be empty
5788	if ( r_cc_receive_updt_fifo_be.empty() and
5789	p_dspin_m2p.write.read() )
5790	{
5791	r_cc_receive_dcache_req = true;
5792	r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_NLINE);
5793	r_cc_receive_word_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_WORD_INDEX);
5794	r_cc_receive_dcache_type = CC_TYPE_UPDT;
5795	// get back to idle state
5796	r_cc_receive_fsm = CC_RECEIVE_DATA_UPDT_DATA;
5797	break;
5798	}
5799	break;
5800	}
5801	////////////////////////////
5802	case CC_RECEIVE_INS_UPDT_NLINE:
5803	{
5804	// sample nline and word index in the second flit
5805	uint64_t receive_data = p_dspin_m2p.data.read();
5806	// for ins INVAL, wait for icache to take the request and fifo to be
5807	// empty
5808	if ( r_cc_receive_updt_fifo_be.empty() and
5809	p_dspin_m2p.write.read() )
5810	{
5811	r_cc_receive_icache_req = true;
5812	r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_NLINE);
5813	r_cc_receive_word_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_WORD_INDEX);
5814	r_cc_receive_icache_type = CC_TYPE_UPDT;
5815	// get back to idle state
5816	r_cc_receive_fsm = CC_RECEIVE_INS_UPDT_DATA;
5817	break;
5818	}
5819	break;
5820	}
5821	//////////////////////////
5822	case CC_RECEIVE_DATA_UPDT_DATA:
5823	{
5824	// wait for the fifo
5825	if (r_cc_receive_updt_fifo_be.wok() and (p_dspin_m2p.write.read()))
5826	{
5827	uint64_t receive_data = p_dspin_m2p.data.read();
5828	bool receive_eop = p_dspin_m2p.eop.read();
5829	cc_receive_updt_fifo_be = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_BE);
5830	cc_receive_updt_fifo_data = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_DATA);
5831	cc_receive_updt_fifo_eop = receive_eop;
5832	cc_receive_updt_fifo_put = true;
5833	if ( receive_eop ) r_cc_receive_fsm = CC_RECEIVE_IDLE;
5834	}
5835	break;
5836	}
5837	//////////////////////////
5838	case CC_RECEIVE_INS_UPDT_DATA:
5839	{
5840	// wait for the fifo
5841	if (r_cc_receive_updt_fifo_be.wok() and (p_dspin_m2p.write.read()))
5842	{
5843	uint64_t receive_data = p_dspin_m2p.data.read();
5844	bool receive_eop = p_dspin_m2p.eop.read();
5845	cc_receive_updt_fifo_be = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_BE);
5846	cc_receive_updt_fifo_data = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_DATA);
5847	cc_receive_updt_fifo_eop = receive_eop;
5848	cc_receive_updt_fifo_put = true;
5849	if ( receive_eop ) r_cc_receive_fsm = CC_RECEIVE_IDLE;
5850	}
5851	break;
5852	}
5853
5854	} // end switch CC_RECEIVE FSM
5855
5856	///////////////// DSPIN CLACK interface ///////////////
5857
5858	uint64_t clack_type = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(),
5859	DspinDhccpParam::CLACK_TYPE);
5860
5861	size_t clack_way = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(),
5862	DspinDhccpParam::CLACK_WAY);
5863
5864	size_t clack_set = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(),
5865	DspinDhccpParam::CLACK_SET);
5866
5867	bool dspin_clack_get = false;
5868	bool dcache_clack_request = (clack_type == DspinDhccpParam::TYPE_CLACK_DATA);
5869	bool icache_clack_request = (clack_type == DspinDhccpParam::TYPE_CLACK_INST);
5870
5871	if (r_dspin_clack_req.read())
5872	{
5873	// CLACK DATA: Send request to DCACHE FSM
5874	if (dcache_clack_request and not r_dcache_clack_req.read()){
5875	r_dcache_clack_req = true;
5876	r_dcache_clack_way = clack_way & ((1ULL<<(uint32_log2(m_dcache_ways)))-1);
5877	r_dcache_clack_set = clack_set & ((1ULL<<(uint32_log2(m_dcache_sets)))-1);
5878	dspin_clack_get = true;
5879	}
5880
5881	// CLACK INST: Send request to ICACHE FSM
5882	else if (icache_clack_request and not r_icache_clack_req.read()){
5883	r_icache_clack_req = true;
5884	r_icache_clack_way = clack_way & ((1ULL<<(uint32_log2(m_dcache_ways)))-1);
5885	r_icache_clack_set = clack_set & ((1ULL<<(uint32_log2(m_icache_sets)))-1);
5886	dspin_clack_get = true;
5887	}
5888	}
5889	else
5890	{
5891	dspin_clack_get = true;
5892	}
5893
5894	if (dspin_clack_get)
5895	{
5896	r_dspin_clack_req = p_dspin_clack.write.read();
5897	r_dspin_clack_flit = p_dspin_clack.data.read();
5898	}
5899
5900	///////////////// Response FIFOs update //////////////////////
5901	r_vci_rsp_fifo_icache.update(vci_rsp_fifo_icache_get,
5902	vci_rsp_fifo_icache_put,
5903	vci_rsp_fifo_icache_data);
5904
5905	r_vci_rsp_fifo_dcache.update(vci_rsp_fifo_dcache_get,
5906	vci_rsp_fifo_dcache_put,
5907	vci_rsp_fifo_dcache_data);
5908
5909	///////////////// updt FIFO update //////////////////////
5910	//TODO check this
5911	r_cc_receive_updt_fifo_be.update(cc_receive_updt_fifo_get,
5912	cc_receive_updt_fifo_put,
5913	cc_receive_updt_fifo_be);
5914	r_cc_receive_updt_fifo_data.update(cc_receive_updt_fifo_get,
5915	cc_receive_updt_fifo_put,
5916	cc_receive_updt_fifo_data);
5917	r_cc_receive_updt_fifo_eop.update(cc_receive_updt_fifo_get,
5918	cc_receive_updt_fifo_put,
5919	cc_receive_updt_fifo_eop);
5920
5921	} // end transition()
5922
5923	///////////////////////
5924	tmpl(void)::genMoore()
5925	///////////////////////
5926	{
5927
5928	// VCI initiator command on the direct network
5929	// it depends on the CMD FSM state
5930
5931	bool is_sc_or_cas = (r_vci_cmd_fsm.read() == CMD_DATA_CAS) or
5932	(r_vci_cmd_fsm.read() == CMD_DATA_SC );
5933
5934	p_vci.pktid = 0;
5935	p_vci.srcid = m_srcid;
5936	p_vci.cons = is_sc_or_cas;
5937	p_vci.contig = not is_sc_or_cas;
5938	p_vci.wrap = false;
5939	p_vci.clen = 0;
5940	p_vci.cfixed = false;
5941
5942	if ( m_monitor_ok ) {
5943	if ( p_vci.cmdack.read() == true and p_vci.cmdval == true) {
5944	if (((p_vci.address.read()) >= m_monitor_base) and
5945	((p_vci.address.read()) < m_monitor_base + m_monitor_length) ) {
5946	std::cout << "CC_VCACHE Monitor " << name() << std::hex
5947	<< " Access type = " << vci_cmd_type_str[p_vci.cmd.read()]
5948	<< " Pktid type = " << vci_pktid_type_str[p_vci.pktid.read()]
5949	<< " : address = " << p_vci.address.read()
5950	<< " / be = " << p_vci.be.read();
5951	if ( p_vci.cmd.read() == vci_param::CMD_WRITE ) {
5952	std::cout << " / data = " << p_vci.wdata.read();
5953	}
5954	std::cout << std::dec << std::endl;
5955	}
5956	}
5957	}
5958
5959	switch ( r_vci_cmd_fsm.read() ) {
5960
5961	case CMD_IDLE:
5962	p_vci.cmdval = false;
5963	p_vci.address = 0;
5964	p_vci.wdata = 0;
5965	p_vci.be = 0;
5966	p_vci.trdid = 0;
5967	p_vci.pktid = 0;
5968	p_vci.plen = 0;
5969	p_vci.cmd = vci_param::CMD_NOP;
5970	p_vci.eop = false;
5971	break;
5972
5973	case CMD_INS_MISS:
5974	p_vci.cmdval = true;
5975	p_vci.address = r_icache_vci_paddr.read() & m_icache_yzmask;
5976	p_vci.wdata = 0;
5977	p_vci.be = 0xF;
5978	p_vci.trdid = 0;
5979	p_vci.pktid = TYPE_READ_INS_MISS;
5980	p_vci.plen = m_icache_words<<2;
5981	p_vci.cmd = vci_param::CMD_READ;
5982	p_vci.eop = true;
5983	break;
5984
5985	case CMD_INS_UNC:
5986	p_vci.cmdval = true;
5987	p_vci.address = r_icache_vci_paddr.read() & ~0x3;
5988	p_vci.wdata = 0;
5989	p_vci.be = 0xF;
5990	p_vci.trdid = 0;
5991	p_vci.pktid = TYPE_READ_INS_UNC;
5992	p_vci.plen = 4;
5993	p_vci.cmd = vci_param::CMD_READ;
5994	p_vci.eop = true;
5995	break;
5996
5997	case CMD_DATA_MISS:
5998	p_vci.cmdval = true;
5999	p_vci.address = r_dcache_vci_paddr.read() & m_dcache_yzmask;
6000	p_vci.wdata = 0;
6001	p_vci.be = 0xF;
6002	p_vci.trdid = 0;
6003	p_vci.pktid = TYPE_READ_DATA_MISS;
6004	p_vci.plen = m_dcache_words << 2;
6005	p_vci.cmd = vci_param::CMD_READ;
6006	p_vci.eop = true;
6007	break;
6008
6009	case CMD_DATA_UNC_READ:
6010	p_vci.cmdval = true;
6011	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
6012	p_vci.wdata = 0;
6013	p_vci.be = r_dcache_vci_unc_be.read();
6014	p_vci.trdid = 0;
6015	p_vci.pktid = TYPE_DATA_UNC;
6016	p_vci.plen = 4;
6017	p_vci.cmd = vci_param::CMD_READ;
6018	p_vci.eop = true;
6019	break;
6020
6021	case CMD_DATA_UNC_WRITE:
6022	p_vci.cmdval = true;
6023	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
6024	p_vci.wdata = r_dcache_vci_wdata.read();
6025	p_vci.be = r_dcache_vci_unc_be.read();
6026	p_vci.trdid = 0;
6027	p_vci.pktid = TYPE_DATA_UNC;
6028	p_vci.plen = 4;
6029	p_vci.cmd = vci_param::CMD_WRITE;
6030	p_vci.eop = true;
6031	break;
6032
6033	case CMD_DATA_WRITE:
6034	p_vci.cmdval = true;
6035	p_vci.address = r_wbuf.getAddress(r_vci_cmd_cpt.read()) & ~0x3;
6036	p_vci.wdata = r_wbuf.getData(r_vci_cmd_cpt.read());
6037	p_vci.be = r_wbuf.getBe(r_vci_cmd_cpt.read());
6038	p_vci.trdid = r_wbuf.getIndex();
6039	p_vci.pktid = TYPE_WRITE;
6040	p_vci.plen = (r_vci_cmd_max.read() - r_vci_cmd_min.read() + 1) << 2;
6041	p_vci.cmd = vci_param::CMD_WRITE;
6042	p_vci.eop = (r_vci_cmd_cpt.read() == r_vci_cmd_max.read());
6043	break;
6044
6045	case CMD_DATA_LL:
6046	p_vci.cmdval = true;
6047	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
6048	p_vci.wdata = 0;
6049	p_vci.be = 0xF;
6050	p_vci.trdid = 0;
6051	p_vci.pktid = TYPE_LL;
6052	p_vci.plen = 8;
6053	p_vci.cmd = vci_param::CMD_LOCKED_READ;
6054	p_vci.eop = true;
6055	break;
6056
6057	case CMD_DATA_SC:
6058	p_vci.cmdval = true;
6059	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
6060	if ( r_vci_cmd_cpt.read() == 0 ) p_vci.wdata = r_dcache_llsc_key.read();
6061	else p_vci.wdata = r_dcache_vci_sc_data.read();
6062	p_vci.be = 0xF;
6063	p_vci.trdid = 0;
6064	p_vci.pktid = TYPE_SC;
6065	p_vci.plen = 8;
6066	p_vci.cmd = vci_param::CMD_NOP;
6067	p_vci.eop = (r_vci_cmd_cpt.read() == 1);
6068	break;
6069
6070	case CMD_DATA_CAS:
6071	p_vci.cmdval = true;
6072	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
6073	if ( r_vci_cmd_cpt.read() == 0 ) p_vci.wdata = r_dcache_vci_cas_old.read();
6074	else p_vci.wdata = r_dcache_vci_cas_new.read();
6075	p_vci.be = 0xF;
6076	p_vci.trdid = 0;
6077	p_vci.pktid = TYPE_CAS;
6078	p_vci.plen = 8;
6079	p_vci.cmd = vci_param::CMD_NOP;
6080	p_vci.eop = (r_vci_cmd_cpt.read() == 1);
6081	break;
6082	} // end switch r_vci_cmd_fsm
6083
6084	// VCI initiator response on the direct network
6085	// it depends on the VCI_RSP FSM
6086
6087	switch (r_vci_rsp_fsm.read() )
6088	{
6089	case RSP_DATA_WRITE : p_vci.rspack = true; break;
6090	case RSP_INS_MISS : p_vci.rspack = r_vci_rsp_fifo_icache.wok(); break;
6091	case RSP_INS_UNC : p_vci.rspack = r_vci_rsp_fifo_icache.wok(); break;
6092	case RSP_DATA_MISS : p_vci.rspack = r_vci_rsp_fifo_dcache.wok(); break;
6093	case RSP_DATA_UNC : p_vci.rspack = r_vci_rsp_fifo_dcache.wok(); break;
6094	case RSP_DATA_LL : p_vci.rspack = r_vci_rsp_fifo_dcache.wok(); break;
6095	case RSP_IDLE : p_vci.rspack = false; break;
6096	} // end switch r_vci_rsp_fsm
6097
6098
6099	// Send coherence packets on DSPIN P2M
6100	// it depends on the CC_SEND FSM
6101
6102	uint64_t dspin_send_data = 0;
6103	switch ( r_cc_send_fsm.read() )
6104	{
6105	//////////////////
6106	case CC_SEND_IDLE:
6107	{
6108	p_dspin_p2m.write = false;
6109	break;
6110	}
6111	///////////////////////
6112	case CC_SEND_CLEANUP_1:
6113	{
6114	// initialize dspin send data
6115	// DspinDhccpParam::dspin_set(dspin_send_data,
6116	// 0,
6117	// DspinDhccpParam::P2M_EOP);
6118	DspinDhccpParam::dspin_set(dspin_send_data,
6119	m_cc_global_id,
6120	DspinDhccpParam::CLEANUP_SRCID);
6121	DspinDhccpParam::dspin_set(dspin_send_data,
6122	0,
6123	DspinDhccpParam::P2M_BC);
6124
6125	if(r_cc_send_last_client.read() == 0) // dcache active request
6126	{
6127	uint64_t dest = (uint64_t) r_dcache_cc_send_nline.read()
6128	>> (m_nline_width - m_x_width - m_y_width)
6129	<< (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
6130
6131	DspinDhccpParam::dspin_set(dspin_send_data,
6132	dest,
6133	DspinDhccpParam::CLEANUP_DEST);
6134
6135	DspinDhccpParam::dspin_set(dspin_send_data,
6136	(r_dcache_cc_send_nline.read() & 0x300000000ULL)>>32,
6137	DspinDhccpParam::CLEANUP_NLINE_MSB);
6138
6139	DspinDhccpParam::dspin_set(dspin_send_data,
6140	r_dcache_cc_send_way.read(),
6141	DspinDhccpParam::CLEANUP_WAY_INDEX);
6142
6143	DspinDhccpParam::dspin_set(dspin_send_data,
6144	DspinDhccpParam::TYPE_CLEANUP_DATA,
6145	DspinDhccpParam::P2M_TYPE);
6146	}
6147	else // icache active request
6148	{
6149	uint64_t dest = (uint64_t) r_icache_cc_send_nline.read()
6150	>> (m_nline_width - m_x_width - m_y_width)
6151	<< (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
6152
6153	DspinDhccpParam::dspin_set(dspin_send_data,
6154	dest,
6155	DspinDhccpParam::CLEANUP_DEST);
6156
6157	DspinDhccpParam::dspin_set(dspin_send_data,
6158	(r_icache_cc_send_nline.read() & 0x300000000ULL)>>32,
6159	DspinDhccpParam::CLEANUP_NLINE_MSB);
6160
6161	DspinDhccpParam::dspin_set(dspin_send_data,
6162	r_icache_cc_send_way.read(),
6163	DspinDhccpParam::CLEANUP_WAY_INDEX);
6164
6165	DspinDhccpParam::dspin_set(dspin_send_data,
6166	DspinDhccpParam::TYPE_CLEANUP_INST,
6167	DspinDhccpParam::P2M_TYPE);
6168	}
6169	// send flit
6170	p_dspin_p2m.data = dspin_send_data;
6171	p_dspin_p2m.write = true;
6172	p_dspin_p2m.eop = false;
6173	break;
6174	}
6175	///////////////////////
6176	case CC_SEND_CLEANUP_2:
6177	{
6178	// initialize dspin send data
6179	// DspinDhccpParam::dspin_set(dspin_send_data,
6180	// 1,
6181	// DspinDhccpParam::P2M_EOP);
6182
6183	if(r_cc_send_last_client.read() == 0) // dcache active request
6184	{
6185	DspinDhccpParam::dspin_set(dspin_send_data,
6186	r_dcache_cc_send_nline.read() & 0xFFFFFFFFULL,
6187	DspinDhccpParam::CLEANUP_NLINE_LSB);
6188	}
6189	else // icache active request
6190	{
6191	DspinDhccpParam::dspin_set(dspin_send_data,
6192	r_icache_cc_send_nline.read() & 0xFFFFFFFFULL,
6193	DspinDhccpParam::CLEANUP_NLINE_LSB);
6194	}
6195	// send flit
6196	p_dspin_p2m.data = dspin_send_data;
6197	p_dspin_p2m.write = true;
6198	p_dspin_p2m.eop = true;
6199	break;
6200	}
6201	///////////////////////
6202	case CC_SEND_MULTI_ACK:
6203	{
6204	// initialize dspin send data
6205	// DspinDhccpParam::dspin_set(dspin_send_data,
6206	// 1,
6207	// DspinDhccpParam::P2M_EOP);
6208	DspinDhccpParam::dspin_set(dspin_send_data,
6209	0,
6210	DspinDhccpParam::P2M_BC);
6211	DspinDhccpParam::dspin_set(dspin_send_data,
6212	DspinDhccpParam::TYPE_MULTI_ACK,
6213	DspinDhccpParam::P2M_TYPE);
6214
6215	if(r_cc_send_last_client.read() == 0) // dcache active request
6216	{
6217	uint64_t dest = (uint64_t) r_dcache_cc_send_nline.read()
6218	>> (m_nline_width - m_x_width - m_y_width)
6219	<< (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
6220
6221	DspinDhccpParam::dspin_set(dspin_send_data,
6222	dest,
6223	DspinDhccpParam::MULTI_ACK_DEST);
6224
6225	DspinDhccpParam::dspin_set(dspin_send_data,
6226	r_dcache_cc_send_updt_tab_idx.read(),
6227	DspinDhccpParam::MULTI_ACK_UPDT_INDEX);
6228	}
6229	else // icache active request
6230	{
6231	uint64_t dest = (uint64_t) r_icache_cc_send_nline.read()
6232	>> (m_nline_width - m_x_width - m_y_width)
6233	<< (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
6234
6235
6236	DspinDhccpParam::dspin_set(dspin_send_data,
6237	dest,
6238	DspinDhccpParam::MULTI_ACK_DEST);
6239
6240	DspinDhccpParam::dspin_set(dspin_send_data,
6241	r_icache_cc_send_updt_tab_idx.read(),
6242	DspinDhccpParam::MULTI_ACK_UPDT_INDEX);
6243	}
6244	// send flit
6245	p_dspin_p2m.data = dspin_send_data;
6246	p_dspin_p2m.write = true;
6247	p_dspin_p2m.eop = true;
6248
6249	break;
6250	}
6251	} // end switch CC_SEND FSM
6252
6253	// Receive coherence packets
6254	// It depends on the CC_RECEIVE FSM
6255	switch( r_cc_receive_fsm.read() )
6256	{
6257	/////////////////////
6258	case CC_RECEIVE_IDLE:
6259	{
6260	p_dspin_m2p.read = false;
6261	break;
6262	}
6263	///////////////////////////////
6264	case CC_RECEIVE_BRDCAST_HEADER:
6265	{
6266	p_dspin_m2p.read = true;
6267	break;
6268	}
6269	//////////////////////////////
6270	case CC_RECEIVE_BRDCAST_NLINE:
6271	{
6272	// TODO maybe we need to wait for both only to leave the state, but
6273	// not to actually post a request to an available cache => need a
6274	// flip_flop to check that ?
6275	if (not (r_cc_receive_icache_req.read()) and not (r_cc_receive_dcache_req.read()))
6276	p_dspin_m2p.read = true;
6277	else
6278	p_dspin_m2p.read = false;
6279	break;
6280	}
6281	/////////////////////////////
6282	case CC_RECEIVE_DATA_INVAL_HEADER:
6283	case CC_RECEIVE_INS_INVAL_HEADER:
6284	{
6285	p_dspin_m2p.read = true;
6286	break;
6287	}
6288	////////////////////////////
6289	case CC_RECEIVE_DATA_INVAL_NLINE:
6290	{
6291	p_dspin_m2p.read = not r_cc_receive_dcache_req.read();
6292	break;
6293	}
6294	case CC_RECEIVE_INS_INVAL_NLINE:
6295	{
6296	p_dspin_m2p.read = not r_cc_receive_icache_req.read();
6297	break;
6298	}
6299	///////////////////////////
6300	case CC_RECEIVE_DATA_UPDT_HEADER:
6301	{
6302	if (not r_cc_receive_dcache_req.read())
6303	p_dspin_m2p.read = true;
6304	else
6305	p_dspin_m2p.read = false;
6306	break;
6307	}
6308	////////////////////////////
6309	case CC_RECEIVE_INS_UPDT_HEADER:
6310	{
6311	if ( not r_cc_receive_icache_req.read())
6312	p_dspin_m2p.read = true;
6313	else
6314	p_dspin_m2p.read = false;
6315	break;
6316	}
6317	///////////////////////////
6318	case CC_RECEIVE_DATA_UPDT_NLINE:
6319	case CC_RECEIVE_INS_UPDT_NLINE:
6320	{
6321	if(r_cc_receive_updt_fifo_be.empty())
6322	p_dspin_m2p.read = true;
6323	else
6324	p_dspin_m2p.read = false;
6325	break;
6326	}
6327	///////////////////////////
6328	case CC_RECEIVE_DATA_UPDT_DATA:
6329	case CC_RECEIVE_INS_UPDT_DATA:
6330	{
6331	if (r_cc_receive_updt_fifo_be.wok())
6332	p_dspin_m2p.read = true;
6333	else
6334	p_dspin_m2p.read = false;
6335	break;
6336	}
6337	} // end switch CC_RECEIVE FSM
6338
6339
6340	int clack_type = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(),
6341	DspinDhccpParam::CLACK_TYPE);
6342
6343	bool dspin_clack_get = false;
6344	bool dcache_clack_request = (clack_type == DspinDhccpParam::TYPE_CLACK_DATA);
6345	bool icache_clack_request = (clack_type == DspinDhccpParam::TYPE_CLACK_INST);
6346
6347	if (r_dspin_clack_req.read())
6348	{
6349	// CLACK DATA: wait if pending request to DCACHE FSM
6350	if (dcache_clack_request and not r_dcache_clack_req.read())
6351	{
6352	dspin_clack_get = true;
6353	}
6354
6355	// CLACK INST: wait if pending request to ICACHE FSM
6356	else if (icache_clack_request and not r_icache_clack_req.read())
6357	{
6358	dspin_clack_get = true;
6359	}
6360	}
6361	else
6362	{
6363	dspin_clack_get = true;
6364	}
6365
6366	p_dspin_clack.read = dspin_clack_get;
6367	} // end genMoore
6368
6369	tmpl(void)::start_monitor(paddr_t base, paddr_t length)
6370	// This version of monitor print both Read and Write request
6371	{
6372	m_monitor_ok = true;
6373	m_monitor_base = base;
6374	m_monitor_length = length;
6375	}
6376
6377	tmpl(void)::stop_monitor()
6378	{
6379	m_monitor_ok = false;
6380	}
6381
6382	}}
6383
6384	// Local Variables:
6385	// tab-width: 4
6386	// c-basic-offset: 4
6387	// c-file-offsets:((innamespace . 0)(inline-open . 0))
6388	// indent-tabs-mode: nil
6389	// End:
6390
6391	// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4

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