Context Navigation

vci_cc_vcache_wrapper2_v1.h @ 130

Last change on this file since 130 was 130, checked in by gao, 13 years ago
Cleanup fsm seperated from vci fsm to evite deadlock
Property svn:eol-style set to `native` Property svn:keywords set to `"Author Date Id Rev URL Revision"` Property svn:mime-type set to `text/plain`
File size: 28.3 KB

Line
1	/* -- c++ --
2	* File : vci_cc_vcache_wrapper2_v1.h
3	* Copyright (c) UPMC, Lip6, SoC
4	* Authors : Alain GREINER, Yang GAO
5	*
6	* SOCLIB_LGPL_HEADER_BEGIN
7	*
8	* This file is part of SoCLib, GNU LGPLv2.1.
9	*
10	* SoCLib is free software; you can redistribute it and/or modify it
11	* under the terms of the GNU Lesser General Public License as published
12	* by the Free Software Foundation; version 2.1 of the License.
13	*
14	* SoCLib is distributed in the hope that it will be useful, but
15	* WITHOUT ANY WARRANTY; without even the implied warranty of
16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17	* Lesser General Public License for more details.
18	*
19	* You should have received a copy of the GNU Lesser General Public
20	* License along with SoCLib; if not, write to the Free Software
21	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
22	* 02110-1301 USA
23	*
24	* SOCLIB_LGPL_HEADER_END
25	*/
26
27	#ifndef SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER2_V1_H
28	#define SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER2_V1_H
29
30	#include <inttypes.h>
31	#include <systemc>
32	#include "caba_base_module.h"
33	#include "write_buffer.h"
34	#include "generic_cache.h"
35	#include "vci_initiator.h"
36	#include "vci_target.h"
37	#include "mapping_table.h"
38	#include "generic_tlb.h"
39	#include "static_assert.h"
40
41	namespace soclib {
42	namespace caba {
43
44	using namespace sc_core;
45
46	////////////////////////////////////////////
47	template<typename vci_param, typename iss_t>
48	class VciCcVCacheWrapper2V1
49	////////////////////////////////////////////
50	: public soclib::caba::BaseModule
51	{
52	typedef uint32_t vaddr_t;
53	typedef uint32_t data_t;
54	typedef uint32_t tag_t;
55	typedef uint32_t type_t;
56	typedef typename iss_t::DataOperationType data_op_t;
57
58	typedef typename vci_param::addr_t paddr_t;
59	typedef typename vci_param::be_t vci_be_t;
60	typedef typename vci_param::srcid_t vci_srcid_t;
61	typedef typename vci_param::trdid_t vci_trdid_t;
62	typedef typename vci_param::pktid_t vci_pktid_t;
63	typedef typename vci_param::plen_t vci_plen_t;
64
65	enum icache_fsm_state_e {
66	ICACHE_IDLE, // 00
67	ICACHE_BIS, // 01
68	ICACHE_TLB1_READ, // 02
69	ICACHE_TLB1_WRITE, // 03
70	ICACHE_TLB1_UPDT_SEL, // 04
71	ICACHE_TLB1_UPDT, // 05
72	ICACHE_TLB2_READ, // 06
73	ICACHE_TLB2_WRITE, // 07
74	ICACHE_TLB2_UPDT_SEL, // 08
75	ICACHE_TLB2_UPDT, // 09
76	ICACHE_SW_FLUSH, // 0a
77	ICACHE_TLB_FLUSH, // 0b
78	ICACHE_CACHE_FLUSH, // 0c
79	ICACHE_TLB_INVAL, // 0d
80	ICACHE_CACHE_INVAL, // 0e
81	ICACHE_CACHE_INVAL_PA, // 0f
82	ICACHE_MISS_WAIT, // 10
83	ICACHE_UNC_WAIT, // 11
84	ICACHE_MISS_UPDT, // 12
85	ICACHE_ERROR, // 13
86	ICACHE_CC_INVAL, // 14
87	ICACHE_TLB_CC_INVAL, // 15
88	};
89
90	enum dcache_fsm_state_e {
91	DCACHE_IDLE, // 00
92	DCACHE_BIS, // 01
93	DCACHE_DTLB1_READ_CACHE, // 02
94	DCACHE_TLB1_LL_WAIT, // 03
95	DCACHE_TLB1_SC_WAIT, // 04
96	DCACHE_TLB1_READ, // 05
97	DCACHE_TLB1_READ_UPDT, // 06
98	DCACHE_TLB1_UPDT_SEL, // 07
99	DCACHE_TLB1_UPDT, // 08
100	DCACHE_DTLB2_READ_CACHE, // 09
101	DCACHE_TLB2_LL_WAIT, // 0a
102	DCACHE_TLB2_SC_WAIT, // 0b
103	DCACHE_TLB2_READ, // 0c
104	DCACHE_TLB2_READ_UPDT, // 0d
105	DCACHE_TLB2_UPDT_SEL, // 0e
106	DCACHE_TLB2_UPDT, // 0f
107	DCACHE_CTXT_SWITCH, // 10
108	DCACHE_ICACHE_FLUSH, // 11
109	DCACHE_DCACHE_FLUSH, // 12
110	DCACHE_ITLB_INVAL, // 13
111	DCACHE_DTLB_INVAL, // 14
112	DCACHE_ICACHE_INVAL, // 15
113	DCACHE_DCACHE_INVAL, // 16
114	DCACHE_ICACHE_INVAL_PA, // 17
115	DCACHE_DCACHE_INVAL_PA, // 18
116	DCACHE_DCACHE_SYNC, // 19
117	DCACHE_LL_DIRTY_WAIT, // 1a
118	DCACHE_SC_DIRTY_WAIT, // 1b
119	DCACHE_WRITE_UPDT, // 1c
120	DCACHE_WRITE_DIRTY, // 1d
121	DCACHE_WRITE_REQ, // 1e
122	DCACHE_MISS_WAIT, // 1f
123	DCACHE_MISS_UPDT, // 20
124	DCACHE_UNC_WAIT, // 21
125	DCACHE_ERROR, // 22
126	DCACHE_ITLB_READ, // 23
127	DCACHE_ITLB_UPDT, // 24
128	DCACHE_ITLB_LL_WAIT, // 25
129	DCACHE_ITLB_SC_WAIT, // 26
130	DCACHE_CC_CHECK, // 27
131	DCACHE_CC_INVAL, // 28
132	DCACHE_CC_UPDT, // 29
133	DCACHE_CC_NOP, // 2a
134	DCACHE_TLB_CC_INVAL, // 2b
135	DCACHE_ITLB_CLEANUP, // 2c
136	};
137
138	enum cmd_fsm_state_e {
139	CMD_IDLE, // 00
140	CMD_ITLB_READ, // 01
141	CMD_ITLB_ACC_LL, // 02
142	CMD_ITLB_ACC_SC, // 03
143	CMD_INS_MISS, // 04
144	CMD_INS_UNC, // 05
145	CMD_DTLB_READ, // 06
146	CMD_DTLB_ACC_LL, // 07
147	CMD_DTLB_ACC_SC, // 08
148	CMD_DTLB_DIRTY_LL, // 09
149	CMD_DTLB_DIRTY_SC, // 0a
150	CMD_DATA_UNC, // 0b
151	CMD_DATA_MISS, // 0c
152	CMD_DATA_WRITE, // 0d
153	};
154
155	enum rsp_fsm_state_e {
156	RSP_IDLE, // 00
157	RSP_ITLB_READ, // 01
158	RSP_ITLB_ACC_LL, // 02
159	RSP_ITLB_ACC_SC, // 03
160	RSP_INS_MISS, // 04
161	RSP_INS_UNC, // 05
162	RSP_DTLB_READ, // 06
163	RSP_DTLB_ACC_LL, // 07
164	RSP_DTLB_ACC_SC, // 08
165	RSP_DTLB_DIRTY_LL, // 09
166	RSP_DTLB_DIRTY_SC, // 0a
167	RSP_DATA_MISS, // 0b
168	RSP_DATA_UNC, // 0c
169	RSP_DATA_WRITE, // 0d
170	};
171	enum cleanup_fsm_state_e {
172	CLEANUP_IDLE, // 00
173	CLEANUP_DATA, // 01
174	CLEANUP_INS, // 02
175	};
176
177	enum tgt_fsm_state_e {
178	TGT_IDLE, // 00
179	TGT_UPDT_WORD, // 01
180	TGT_UPDT_DATA, // 02
181	TGT_REQ_BROADCAST, // 03
182	TGT_REQ_ICACHE, // 04
183	TGT_REQ_DCACHE, // 05
184	TGT_RSP_BROADCAST, // 06
185	TGT_RSP_ICACHE, // 07
186	TGT_RSP_DCACHE, // 08
187	};
188
189	enum inval_itlb_fsm_state_e {
190	INVAL_ITLB_IDLE, // 00
191	INVAL_ITLB_CHECK, // 01
192	INVAL_ITLB_INVAL, // 02
193	INVAL_ITLB_CLEAR, // 03
194	};
195
196	enum inval_dtlb_fsm_state_e {
197	INVAL_DTLB_IDLE, // 00
198	INVAL_DTLB_CHECK, // 01
199	INVAL_DTLB_INVAL, // 02
200	INVAL_DTLB_CLEAR, // 03
201	};
202
203	// TLB Mode ITLB / DTLB / ICACHE / DCACHE
204	enum {
205	ALL_DEACTIVE = 0x0000, // TLBs disactive caches disactive
206	INS_TLB_MASK = 0x8,
207	DATA_TLB_MASK = 0x4,
208	INS_CACHE_MASK = 0x2,
209	DATA_CACHE_MASK = 0x1,
210	};
211
212	// Error Type
213	enum mmu_error_type_e {
214	MMU_NONE = 0x0000, // None
215	MMU_WRITE_PT1_UNMAPPED = 0x0001, // Write access of Page fault on Page Table 1 (non fatal error)
216	MMU_WRITE_PT2_UNMAPPED = 0x0002, // Write access of Page fault on Page Table 2 (non fatal error)
217	MMU_WRITE_PRIVILEGE_VIOLATION = 0x0004, // Write access of Protected access in user mode (user error)
218	MMU_WRITE_ACCES_VIOLATION = 0x0008, // Write access of write access to a non writable page (user error)
219	MMU_WRITE_UNDEFINED_XTN = 0x0020, // Write access of undefined external access address (user error)
220	MMU_WRITE_PT1_ILLEGAL_ACCESS = 0x0040, // Write access of Bus Error accessing Table 1 (kernel error)
221	MMU_WRITE_PT2_ILLEGAL_ACCESS = 0x0080, // Write access of Bus Error accessing Table 2 (kernel error)
222	MMU_WRITE_DATA_ILLEGAL_ACCESS = 0x0100, // Write access of Bus Error in cache access (kernel error)
223	MMU_READ_PT1_UNMAPPED = 0x1001, // Read access of Page fault on Page Table 1 (non fatal error)
224	MMU_READ_PT2_UNMAPPED = 0x1002, // Read access of Page fault on Page Table 2 (non fatal error)
225	MMU_READ_PRIVILEGE_VIOLATION = 0x1004, // Read access of Protected access in user mode (user error)
226	MMU_READ_EXEC_VIOLATION = 0x1010, // Exec access to a non exec page (user error)
227	MMU_READ_UNDEFINED_XTN = 0x1020, // Read access of Undefined external access address (user error)
228	MMU_READ_PT1_ILLEGAL_ACCESS = 0x1040, // Read access of Bus Error in Table1 access (kernel error)
229	MMU_READ_PT2_ILLEGAL_ACCESS = 0x1080, // Read access of Bus Error in Table2 access (kernel error)
230	MMU_READ_DATA_ILLEGAL_ACCESS = 0x1100, // Read access of Bus Error in cache access (kernel error)
231	};
232
233	public:
234	sc_in<bool> p_clk;
235	sc_in<bool> p_resetn;
236	sc_in<bool> p_irq[iss_t::n_irq];
237	soclib::caba::VciInitiator<vci_param> p_vci_ini_rw;
238	soclib::caba::VciInitiator<vci_param> p_vci_ini_c;
239	soclib::caba::VciTarget<vci_param> p_vci_tgt;
240
241	private:
242	// STRUCTURAL PARAMETERS
243	soclib::common::AddressDecodingTable<uint32_t, bool> m_cacheability_table;
244	const soclib::common::Segment m_segment;
245	iss_t m_iss;
246	const vci_srcid_t m_srcid_rw;
247	const vci_srcid_t m_srcid_c;
248
249	const size_t m_itlb_ways;
250	const size_t m_itlb_sets;
251
252	const size_t m_dtlb_ways;
253	const size_t m_dtlb_sets;
254
255	const size_t m_icache_ways;
256	const size_t m_icache_sets;
257	const size_t m_icache_yzmask;
258	const size_t m_icache_words;
259
260	const size_t m_dcache_ways;
261	const size_t m_dcache_sets;
262	const size_t m_dcache_yzmask;
263	const size_t m_dcache_words;
264
265	const size_t m_write_buf_size;
266	const size_t m_paddr_nbits;
267
268	// instruction and data vcache tlb instances
269	soclib::caba::GenericCcTlb<paddr_t> icache_tlb;
270	soclib::caba::GenericCcTlb<paddr_t> dcache_tlb;
271
272	sc_signal<vaddr_t> r_mmu_ptpr; // page table pointer register
273	sc_signal<int> r_mmu_mode; // tlb mode register
274	sc_signal<int> r_mmu_params; // mmu parameters register
275	sc_signal<int> r_mmu_release; // mmu release register
276	sc_signal<int> r_mmu_word_lo; // mmu misc data low
277	sc_signal<int> r_mmu_word_hi; // mmu mmu misc data hight
278
279	// DCACHE FSM REGISTERS
280	sc_signal<int> r_dcache_fsm; // state register
281	sc_signal<paddr_t> r_dcache_paddr_save; // physical address
282	sc_signal<data_t> r_dcache_wdata_save; // write data
283	sc_signal<data_t> r_dcache_rdata_save; // read data
284	sc_signal<type_t> r_dcache_type_save; // access type
285	sc_signal<vci_be_t> r_dcache_be_save; // byte enable
286	sc_signal<bool> r_dcache_cached_save; // used by the write buffer
287	sc_signal<paddr_t> r_dcache_tlb_paddr; // physical address of tlb miss
288	sc_signal<bool> r_dcache_dirty_save; // used for TLB dirty bit update
289	sc_signal<size_t> r_dcache_tlb_set_save; // used for TLB dirty bit update
290	sc_signal<size_t> r_dcache_tlb_way_save; // used for TLB dirty bit update
291	sc_signal<vaddr_t> r_dcache_id1_save; // used by the PT1 bypass
292	sc_signal<paddr_t> r_dcache_ptba_save; // used by the PT1 bypass
293	sc_signal<bool> r_dcache_ptba_ok; // used by the PT1 bypass
294	sc_signal<data_t> r_dcache_pte_update; // used for page table update
295	sc_signal<data_t> r_dcache_ppn_update; // used for physical page number update
296	sc_signal<tag_t> r_dcache_ppn_save; // used for speculative cache access
297	sc_signal<tag_t> r_dcache_vpn_save; // used for speculative cache access
298	sc_signal<bool> r_dtlb_translation_valid; // used for speculative address
299	sc_signal<bool> r_dcache_buf_unc_valid; // used for uncached read
300	sc_signal<bool> r_dcache_hit_p_save; // used to save hit_p in case BIS
301
302	sc_signal<data_t> r_dcache_error_type; // software visible register
303	sc_signal<vaddr_t> r_dcache_bad_vaddr; // software visible register
304
305	sc_signal<bool> r_dcache_miss_req; // used for cached read miss
306	sc_signal<bool> r_dcache_unc_req; // used for uncached read miss
307	sc_signal<bool> r_dcache_write_req; // used for write
308	sc_signal<bool> r_dcache_tlb_read_req; // used for tlb ptba or pte read
309
310	sc_signal<bool> r_dcache_llsc_reserved; // used for check address reserved
311	sc_signal<paddr_t> r_dcache_llsc_addr_save; // used for save llsc address
312
313	sc_signal<bool> r_dcache_tlb_ll_acc_req; // used for tlb access bit update
314	sc_signal<bool> r_dcache_tlb_sc_acc_req; // used for tlb access bit update
315	sc_signal<bool> r_dcache_tlb_ll_dirty_req; // used for tlb dirty bit update
316	sc_signal<bool> r_dcache_tlb_sc_dirty_req; // used for tlb dirty bit update
317	sc_signal<bool> r_dcache_sc_updt_dirty; // used for tlb dirty bit update
318	sc_signal<bool> r_dcache_tlb_ptba_read; // used for tlb ptba read when write dirty bit
319	sc_signal<bool> r_dcache_xtn_req; // used for xtn write for ICACHE
320
321	bool *r_dcache_in_itlb; // indicates some words of dcache line in ins TLB
322	bool *r_dcache_in_dtlb; // indicates some words of dcache line in data TLB
323
324	// coherence registers
325	sc_signal<int> r_dcache_fsm_save; // state save register
326	sc_signal<size_t> r_dcache_way;
327	sc_signal<size_t> r_dcache_set;
328	sc_signal<bool> r_dcache_cleanup_req; // data cleanup request
329	sc_signal<paddr_t> r_dcache_cleanup_line; // data cleanup NLINE
330	sc_signal<bool> r_dcache_inval_rsp; // data cache invalidate
331
332	// ICACHE FSM REGISTERS
333	sc_signal<int> r_icache_fsm; // state register
334	sc_signal<paddr_t> r_icache_paddr_save; // physical address
335	sc_signal<vaddr_t> r_icache_id1_save; // used by the PT1 bypass
336	sc_signal<paddr_t> r_icache_ptba_save; // used by the PT1 bypass
337	sc_signal<bool> r_icache_ptba_ok; // used by the PT1 bypass
338	sc_signal<data_t> r_icache_pte_update; // used for page table update
339	sc_signal<tag_t> r_icache_ppn_save; // used for speculative cache access
340	sc_signal<tag_t> r_icache_vpn_save; // used for speculative cache access
341	sc_signal<bool> r_itlb_translation_valid; // used for speculative physical address
342	sc_signal<bool> r_icache_buf_unc_valid; // used for uncached read
343
344	sc_signal<data_t> r_icache_error_type; // software visible registers
345	sc_signal<vaddr_t> r_icache_bad_vaddr; // software visible registers
346
347	sc_signal<bool> r_icache_miss_req; // used for cached read miss
348	sc_signal<bool> r_icache_unc_req; // used for uncached read miss
349	sc_signal<bool> r_dcache_itlb_read_req; // used for tlb ptba or pte read
350
351	sc_signal<bool> r_dcache_itlb_ll_acc_req; // used for tlb access bit update
352	sc_signal<bool> r_dcache_itlb_sc_acc_req; // used for tlb access bit update
353
354	sc_signal<bool> r_itlb_read_dcache_req; // used for instruction tlb miss, request in data cache
355	sc_signal<bool> r_itlb_k_read_dcache; // used for instruction tlb miss, request in data cache
356	sc_signal<bool> r_itlb_acc_dcache_req; // used for itlb update access bit via dcache
357	sc_signal<bool> r_itlb_acc_redo_req; // used for itlb update access bit via dcache
358	sc_signal<bool> r_dcache_rsp_itlb_error; // used for data cache rsp error when itlb miss
359	sc_signal<data_t> r_dcache_rsp_itlb_miss; // used for dcache rsp data when itlb miss
360	sc_signal<data_t> r_dcache_rsp_itlb_ppn; // used for dcache rsp ppn when itlb miss
361	sc_signal<vaddr_t> r_icache_vaddr_req; // virtual address requested by the CPU
362
363	// coherence registers
364	sc_signal<int> r_icache_fsm_save; // state save register
365	sc_signal<size_t> r_icache_way;
366	sc_signal<size_t> r_icache_set;
367	sc_signal<bool> r_icache_cleanup_req; // ins cleanup request
368	sc_signal<paddr_t> r_icache_cleanup_line; // ins cleanup NLINE
369	sc_signal<bool> r_icache_inval_rsp; // ins cache invalidate
370
371	// VCI_CMD FSM REGISTERS
372	sc_signal<int> r_vci_cmd_fsm;
373	sc_signal<size_t> r_vci_cmd_min;
374	sc_signal<size_t> r_vci_cmd_max;
375	sc_signal<size_t> r_vci_cmd_cpt;
376
377	// VCI_RSP FSM REGISTERS
378	sc_signal<int> r_vci_rsp_fsm;
379	sc_signal<size_t> r_vci_rsp_cpt;
380	sc_signal<bool> r_vci_rsp_ins_error;
381	sc_signal<bool> r_vci_rsp_data_error;
382	sc_signal<bool> r_dcache_tlb_sc_fail;
383
384	data_t *r_icache_miss_buf;
385	data_t *r_dcache_miss_buf;
386
387	sc_signal<int> r_cleanup_fsm;
388
389	// VCI_TGT FSM REGISTERS
390	data_t *r_tgt_buf;
391	bool *r_tgt_val;
392
393	sc_signal<int> r_vci_tgt_fsm;
394	sc_signal<paddr_t> r_tgt_addr;
395	sc_signal<size_t> r_tgt_word;
396	sc_signal<bool> r_tgt_update;
397	sc_signal<vci_srcid_t> r_tgt_srcid;
398	sc_signal<vci_pktid_t> r_tgt_pktid;
399	sc_signal<vci_trdid_t> r_tgt_trdid;
400	sc_signal<vci_plen_t> r_tgt_plen;
401	sc_signal<bool> r_tgt_req;
402	sc_signal<bool> r_tgt_icache_req;
403	sc_signal<bool> r_tgt_dcache_req;
404	sc_signal<bool> r_tgt_icache_rsp;
405	sc_signal<bool> r_tgt_dcache_rsp;
406
407	// INVAL CHECK FSM
408	sc_signal<int> r_inval_itlb_fsm;
409	sc_signal<bool> r_dcache_itlb_inval_req;
410	sc_signal<paddr_t> r_dcache_itlb_inval_line;
411	sc_signal<bool> r_itlb_cc_check_end;
412	sc_signal<size_t> r_ccinval_itlb_way;
413	sc_signal<size_t> r_ccinval_itlb_set;
414	sc_signal<bool> r_icache_inval_tlb_rsp;
415	sc_signal<paddr_t> r_icache_tlb_nline;
416
417	sc_signal<int> r_inval_dtlb_fsm;
418	sc_signal<bool> r_dcache_dtlb_inval_req;
419	sc_signal<paddr_t> r_dcache_dtlb_inval_line;
420	sc_signal<bool> r_dtlb_cc_check_end;
421	sc_signal<size_t> r_ccinval_dtlb_way;
422	sc_signal<size_t> r_ccinval_dtlb_set;
423	sc_signal<bool> r_dcache_inval_tlb_rsp;
424	sc_signal<paddr_t> r_dcache_tlb_nline;
425
426	sc_signal<bool> r_dcache_itlb_cleanup_req;
427	sc_signal<paddr_t> r_dcache_itlb_cleanup_line;
428
429	sc_signal<bool> r_dcache_dtlb_cleanup_req;
430	sc_signal<paddr_t> r_dcache_dtlb_cleanup_line;
431
432	sc_signal<bool> r_itlb_inval_req;
433	sc_signal<bool> r_dcache_cc_check;
434
435	WriteBuffer<paddr_t> r_wbuf;
436	GenericCache<paddr_t> r_icache;
437	GenericCache<paddr_t> r_dcache;
438
439	// Activity counters
440	uint32_t m_cpt_dcache_data_read; // DCACHE DATA READ
441	uint32_t m_cpt_dcache_data_write; // DCACHE DATA WRITE
442	uint32_t m_cpt_dcache_dir_read; // DCACHE DIR READ
443	uint32_t m_cpt_dcache_dir_write; // DCACHE DIR WRITE
444
445	uint32_t m_cpt_icache_data_read; // ICACHE DATA READ
446	uint32_t m_cpt_icache_data_write; // ICACHE DATA WRITE
447	uint32_t m_cpt_icache_dir_read; // ICACHE DIR READ
448	uint32_t m_cpt_icache_dir_write; // ICACHE DIR WRITE
449
450	uint32_t m_cpt_frz_cycles; // number of cycles where the cpu is frozen
451	uint32_t m_cpt_total_cycles; // total number of cycles
452	uint32_t m_cpt_dcache_frz_cycles; // number of cycles where the data cache is frozen
453
454	// Cache activity counters
455	uint32_t m_cpt_read; // total number of read data
456	uint32_t m_cpt_write; // total number of write data
457	uint32_t m_cpt_data_miss; // number of read miss
458	uint32_t m_cpt_ins_miss; // number of instruction miss
459	uint32_t m_cpt_unc_read; // number of read uncached
460	uint32_t m_cpt_write_cached; // number of cached write
461	uint32_t m_cpt_ins_read; // number of instruction read
462
463	uint32_t m_cost_write_frz; // number of frozen cycles related to write buffer
464	uint32_t m_cost_data_miss_frz; // number of frozen cycles related to data miss
465	uint32_t m_cost_unc_read_frz; // number of frozen cycles related to uncached read
466	uint32_t m_cost_ins_miss_frz; // number of frozen cycles related to ins miss
467
468	uint32_t m_cpt_imiss_transaction; // number of VCI instruction miss transactions
469	uint32_t m_cpt_dmiss_transaction; // number of VCI data miss transactions
470	uint32_t m_cpt_unc_transaction; // number of VCI uncached read transactions
471	uint32_t m_cpt_write_transaction; // number of VCI write transactions
472	uint32_t m_cpt_icache_unc_transaction;
473
474	uint32_t m_cost_imiss_transaction; // cumulated duration for VCI IMISS transactions
475	uint32_t m_cost_dmiss_transaction; // cumulated duration for VCI DMISS transactions
476	uint32_t m_cost_unc_transaction; // cumulated duration for VCI UNC transactions
477	uint32_t m_cost_write_transaction; // cumulated duration for VCI WRITE transactions
478	uint32_t m_cost_icache_unc_transaction; // cumulated duration for VCI IUNC transactions
479	uint32_t m_length_write_transaction; // cumulated length for VCI WRITE transactions
480
481	// TLB activity counters
482	uint32_t m_cpt_ins_tlb_read; // number of instruction tlb read
483	uint32_t m_cpt_ins_tlb_miss; // number of instruction tlb miss
484	uint32_t m_cpt_ins_tlb_update_acc; // number of instruction tlb update acc
485	uint32_t m_cpt_data_tlb_read; // number of data tlb read
486	uint32_t m_cpt_data_tlb_miss; // number of data tlb miss
487	uint32_t m_cpt_data_tlb_update_acc; // number of data tlb update acc
488	uint32_t m_cpt_data_tlb_update_dirty; // number of data tlb update dirty
489	uint32_t m_cpt_ins_tlb_hit_dcache; // number of instruction tlb hit in data cache
490	uint32_t m_cpt_data_tlb_hit_dcache; // number of data tlb hit in data cache
491	uint32_t m_cpt_ins_tlb_occup_cache; // number of instruction tlb occupy data cache line
492	uint32_t m_cpt_data_tlb_occup_cache; // number of data tlb occupy data cache line
493	uint32_t m_cpt_tlb_occup_dcache;
494
495	uint32_t m_cost_ins_tlb_miss_frz; // number of frozen cycles related to instruction tlb miss
496	uint32_t m_cost_data_tlb_miss_frz; // number of frozen cycles related to data tlb miss
497	uint32_t m_cost_ins_tlb_update_acc_frz; // number of frozen cycles related to instruction tlb update acc
498	uint32_t m_cost_data_tlb_update_acc_frz; // number of frozen cycles related to data tlb update acc
499	uint32_t m_cost_data_tlb_update_dirty_frz; // number of frozen cycles related to data tlb update dirty
500	uint32_t m_cost_ins_tlb_occup_cache_frz; // number of frozen cycles related to instruction tlb miss operate in dcache
501	uint32_t m_cost_data_tlb_occup_cache_frz; // number of frozen cycles related to data tlb miss operate in dcache
502
503	uint32_t m_cpt_itlbmiss_transaction; // number of itlb miss transactions
504	uint32_t m_cpt_itlb_ll_transaction; // number of itlb ll acc transactions
505	uint32_t m_cpt_itlb_sc_transaction; // number of itlb sc acc transactions
506	uint32_t m_cpt_dtlbmiss_transaction; // number of dtlb miss transactions
507	uint32_t m_cpt_dtlb_ll_transaction; // number of dtlb ll acc transactions
508	uint32_t m_cpt_dtlb_sc_transaction; // number of dtlb sc acc transactions
509	uint32_t m_cpt_dtlb_ll_dirty_transaction; // number of dtlb ll dirty transactions
510	uint32_t m_cpt_dtlb_sc_dirty_transaction; // number of dtlb sc dirty transactions
511
512	uint32_t m_cost_itlbmiss_transaction; // cumulated duration for VCI instruction TLB miss transactions
513	uint32_t m_cost_itlb_ll_transaction; // cumulated duration for VCI instruction TLB ll acc transactions
514	uint32_t m_cost_itlb_sc_transaction; // cumulated duration for VCI instruction TLB sc acc transactions
515	uint32_t m_cost_dtlbmiss_transaction; // cumulated duration for VCI data TLB miss transactions
516	uint32_t m_cost_dtlb_ll_transaction; // cumulated duration for VCI data TLB ll acc transactions
517	uint32_t m_cost_dtlb_sc_transaction; // cumulated duration for VCI data TLB sc acc transactions
518	uint32_t m_cost_dtlb_ll_dirty_transaction;// cumulated duration for VCI data TLB ll dirty transactions
519	uint32_t m_cost_dtlb_sc_dirty_transaction;// cumulated duration for VCI data TLB sc dirty transactions
520
521	uint32_t m_cpt_cc_update_data; // number of coherence update data packets
522	uint32_t m_cpt_cc_inval_ins; // number of coherence inval instruction packets
523	uint32_t m_cpt_cc_inval_data; // number of coherence inval data packets
524	uint32_t m_cpt_cc_broadcast; // number of coherence broadcast packets
525	uint32_t m_cpt_cc_cleanup_ins; // number of coherence cleanup packets
526	uint32_t m_cpt_cc_cleanup_data; // number of coherence cleanup packets
527
528	uint32_t m_cpt_icleanup_transaction; // number of instruction cleanup transactions
529	uint32_t m_cpt_dcleanup_transaction; // number of instructinumber of data cleanup transactions
530	uint32_t m_cost_icleanup_transaction; // cumulated duration for VCI instruction cleanup transactions
531	uint32_t m_cost_dcleanup_transaction; // cumulated duration for VCI data cleanup transactions
532
533	uint32_t m_cost_ins_tlb_inval_frz; // number of frozen cycles related to checking ins tlb invalidate
534	uint32_t m_cpt_ins_tlb_inval; // number of ins tlb invalidate
535
536	uint32_t m_cost_data_tlb_inval_frz; // number of frozen cycles related to checking data tlb invalidate
537	uint32_t m_cpt_data_tlb_inval; // number of data tlb invalidate
538
539	protected:
540	SC_HAS_PROCESS(VciCcVCacheWrapper2V1);
541
542	public:
543	VciCcVCacheWrapper2V1(
544	sc_module_name insname,
545	int proc_id,
546	const soclib::common::MappingTable &mtp,
547	const soclib::common::MappingTable &mtc,
548	const soclib::common::IntTab &initiator_index_rw,
549	const soclib::common::IntTab &initiator_index_c,
550	const soclib::common::IntTab &target_index,
551	size_t itlb_ways,
552	size_t itlb_sets,
553	size_t dtlb_ways,
554	size_t dtlb_sets,
555	size_t icache_ways,
556	size_t icache_sets,
557	size_t icache_words,
558	size_t dcache_ways,
559	size_t dcache_sets,
560	size_t dcache_words,
561	size_t write_buf_size );
562
563	~VciCcVCacheWrapper2V1();
564
565	void print_cpi();
566	void print_stats();
567	void clear_stats();
568	void print_trace(size_t mode = 0);
569
570	private:
571	void transition();
572	void genMoore();
573
574	soclib_static_assert((int)iss_t::SC_ATOMIC == (int)vci_param::STORE_COND_ATOMIC);
575	soclib_static_assert((int)iss_t::SC_NOT_ATOMIC == (int)vci_param::STORE_COND_NOT_ATOMIC);
576	};
577
578	}}
579
580	#endif /* SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER2_V1_H */
581
582	// Local Variables:
583	// tab-width: 4
584	// c-basic-offset: 4
585	// c-file-offsets:((innamespace . 0)(inline-open . 0))
586	// indent-tabs-mode: nil
587	// End:
588
589	// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
590
591
592
593

Note: See TracBrowser for help on using the repository browser.

Download in other formats:

Original Format