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source: trunk/modules/vci_cc_vcache_wrapper_v4/caba/source/src/vci_cc_vcache_wrapper_v4.cpp @ 236

Last change on this file since 236 was 236, checked in by haoliu, 12 years ago
fix bug in state ICACHE_XTN_CACHE_INVAL_VA*
File size: 188.6 KB

Line
1	/* i- c++ --C
2	* File : vci_cc_vcache_wrapper_v4.cpp
3	* Copyright (c) UPMC, Lip6, SoC
4	* Authors : Alain GREINER, Yang GAO
5	*
6	* SOCLIB_LGPL_HEADER_BEGIN
7	*
8	* This file is part of SoCLib, GNU LGPLv2.1.
9	*
10	* SoCLib is free software; you can redistribute it and/or modify it
11	* under the terms of the GNU Lesser General Public License as published
12	* by the Free Software Foundation; version 2.1 of the License.
13	*
14	* SoCLib is distributed in the hope that it will be useful, but
15	* WITHOUT ANY WARRANTY; without even the implied warranty of
16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17	* Lesser General Public License for more details.
18	*
19	* You should have received a copy of the GNU Lesser General Public
20	* License along with SoCLib; if not, write to the Free Software
21	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
22	* 02110-1301 USA
23	*
24	* SOCLIB_LGPL_HEADER_END
25	*/
26
27	#include <cassert>
28	#include "arithmetics.h"
29	#include "../include/vci_cc_vcache_wrapper_v4.h"
30
31	#define DEBUG_DCACHE 1
32	#define DEBUG_ICACHE 1
33	#define DEBUG_CLEANUP 0
34
35	namespace soclib {
36	namespace caba {
37
38	namespace {
39	const char *icache_fsm_state_str[] = {
40	"ICACHE_IDLE",
41
42	"ICACHE_XTN_TLB_FLUSH",
43	"ICACHE_XTN_CACHE_FLUSH",
44	"ICACHE_XTN_TLB_INVAL",
45	"ICACHE_XTN_CACHE_INVAL_VA",
46	"ICACHE_XTN_CACHE_INVAL_PA",
47	"ICACHE_XTN_CACHE_INVAL_GO",
48
49	"ICACHE_TLB_WAIT",
50
51	"ICACHE_MISS_VICTIM",
52	"ICACHE_MISS_INVAL",
53	"ICACHE_MISS_WAIT",
54	"ICACHE_MISS_UPDT",
55
56	"ICACHE_UNC_WAIT",
57
58	"ICACHE_CC_CHECK",
59	"ICACHE_CC_INVAL",
60	"ICACHE_CC_UPDT",
61
62	};
63	const char *dcache_fsm_state_str[] = {
64	"DCACHE_IDLE",
65
66	"DCACHE_TLB_MISS",
67	"DCACHE_TLB_PTE1_GET",
68	"DCACHE_TLB_PTE1_SELECT",
69	"DCACHE_TLB_PTE1_UPDT",
70	"DCACHE_TLB_PTE2_GET",
71	"DCACHE_TLB_PTE2_SELECT",
72	"DCACHE_TLB_PTE2_UPDT",
73	"DCACHE_TLB_LR_UPDT",
74	"DCACHE_TLB_LR_WAIT",
75	"DCACHE_TLB_RETURN",
76
77	"DCACHE_XTN_SWITCH",
78	"DCACHE_XTN_SYNC",
79	"DCACHE_XTN_IC_INVAL_VA",
80	"DCACHE_XTN_IC_FLUSH",
81	"DCACHE_XTN_IC_INVAL_PA",
82	"DCACHE_XTN_IT_INVAL",
83	"DCACHE_XTN_DC_FLUSH",
84	"DCACHE_XTN_DC_INVAL_VA",
85	"DCACHE_XTN_DC_INVAL_PA",
86	"DCACHE_XTN_DC_INVAL_END",
87	"DCACHE_XTN_DC_INVAL_GO",
88	"DCACHE_XTN_DT_INVAL",
89
90	"DCACHE_DIRTY_PTE_GET",
91	"DCACHE_DIRTY_SC_WAIT",
92
93	"DCACHE_MISS_VICTIM",
94	"DCACHE_MISS_INVAL",
95	"DCACHE_MISS_WAIT",
96	"DCACHE_MISS_UPDT",
97
98	"DCACHE_UNC_WAIT",
99	"DCACHE_SC_WAIT",
100
101	"DCACHE_CC_CHECK",
102	"DCACHE_CC_INVAL",
103	"DCACHE_CC_UPDT",
104
105	"DCACHE_INVAL_TLB_SCAN",
106	};
107	const char *cmd_fsm_state_str[] = {
108	"CMD_IDLE",
109	"CMD_INS_MISS",
110	"CMD_INS_UNC",
111	"CMD_DATA_MISS",
112	"CMD_DATA_UNC",
113	"CMD_DATA_WRITE",
114	"CMD_DATA_SC",
115	};
116	const char *rsp_fsm_state_str[] = {
117	"RSP_IDLE",
118	"RSP_INS_MISS",
119	"RSP_INS_UNC",
120	"RSP_DATA_MISS",
121	"RSP_DATA_UNC",
122	"RSP_DATA_WRITE",
123	};
124	const char *cleanup_fsm_state_str[] = {
125	"CLEANUP_DATA_IDLE",
126	"CLEANUP_DATA_GO",
127	"CLEANUP_INS_IDLE",
128	"CLEANUP_INS_GO",
129	};
130	const char *tgt_fsm_state_str[] = {
131	"TGT_IDLE",
132	"TGT_UPDT_WORD",
133	"TGT_UPDT_DATA",
134	"TGT_REQ_BROADCAST",
135	"TGT_REQ_ICACHE",
136	"TGT_REQ_DCACHE",
137	"TGT_RSP_BROADCAST",
138	"TGT_RSP_ICACHE",
139	"TGT_RSP_DCACHE",
140	};
141	}
142
143	#define tmpl(...) template<typename vci_param, typename iss_t> __VA_ARGS__ VciCcVCacheWrapperV4<vci_param, iss_t>
144
145	using soclib::common::uint32_log2;
146
147	/////////////////////////////////
148	tmpl(/**/)::VciCcVCacheWrapperV4(
149	sc_module_name name,
150	int proc_id,
151	const soclib::common::MappingTable &mtd,
152	const soclib::common::MappingTable &mtc,
153	const soclib::common::IntTab &initiator_index_d,
154	const soclib::common::IntTab &initiator_index_c,
155	const soclib::common::IntTab &target_index_c,
156	size_t itlb_ways,
157	size_t itlb_sets,
158	size_t dtlb_ways,
159	size_t dtlb_sets,
160	size_t icache_ways,
161	size_t icache_sets,
162	size_t icache_words,
163	size_t dcache_ways,
164	size_t dcache_sets,
165	size_t dcache_words,
166	size_t wbuf_nlines,
167	size_t wbuf_nwords,
168	uint32_t max_frozen_cycles,
169	uint32_t debug_start_cycle,
170	bool debug_ok)
171	: soclib::caba::BaseModule(name),
172
173	p_clk("clk"),
174	p_resetn("resetn"),
175	p_vci_ini_d("vci_ini_d"),
176	p_vci_ini_c("vci_ini_c"),
177	p_vci_tgt_c("vci_tgt_d"),
178
179	m_cacheability_table(mtd.getCacheabilityTable()),
180	m_segment(mtc.getSegment(target_index_c)),
181	m_srcid_d(mtd.indexForId(initiator_index_d)),
182	m_srcid_c(mtc.indexForId(initiator_index_c)),
183
184	m_itlb_ways(itlb_ways),
185	m_itlb_sets(itlb_sets),
186
187	m_dtlb_ways(dtlb_ways),
188	m_dtlb_sets(dtlb_sets),
189
190	m_icache_ways(icache_ways),
191	m_icache_sets(icache_sets),
192	m_icache_yzmask((~0)<<(uint32_log2(icache_words) + 2)),
193	m_icache_words(icache_words),
194
195	m_dcache_ways(dcache_ways),
196	m_dcache_sets(dcache_sets),
197	m_dcache_yzmask((~0)<<(uint32_log2(dcache_words) + 2)),
198	m_dcache_words(dcache_words),
199
200	m_proc_id(proc_id),
201
202	m_max_frozen_cycles(max_frozen_cycles),
203
204	m_paddr_nbits(vci_param::N),
205
206	m_debug_start_cycle(debug_start_cycle),
207	m_debug_ok(debug_ok),
208
209	r_mmu_ptpr("r_mmu_ptpr"),
210	r_mmu_mode("r_mmu_mode"),
211	r_mmu_word_lo("r_mmu_word_lo"),
212	r_mmu_word_hi("r_mmu_word_hi"),
213	r_mmu_ibvar("r_mmu_ibvar"),
214	r_mmu_dbvar("r_mmu_dbvar"),
215	r_mmu_ietr("r_mmu_ietr"),
216	r_mmu_detr("r_mmu_detr"),
217
218	r_icache_fsm("r_icache_fsm"),
219	r_icache_fsm_save("r_icache_fsm_save"),
220
221	r_icache_vci_paddr("r_icache_vci_paddr"),
222	r_icache_vaddr_save("r_icache_vaddr_save"),
223
224	r_icache_miss_way("r_icache_miss_way"),
225	r_icache_miss_set("r_icache_miss_set"),
226	r_icache_miss_word("r_icache_miss_word"),
227	r_icache_miss_inval("r_icache_miss_inval"),
228
229	r_icache_cc_way("r_icache_cc_way"),
230	r_icache_cc_set("r_icache_cc_set"),
231	r_icache_cc_word("r_icache_cc_word"),
232
233	r_icache_flush_count("r_icache_flush_count"),
234
235	r_icache_miss_req("r_icache_miss_req"),
236	r_icache_unc_req("r_icache_unc_req"),
237
238	r_icache_tlb_miss_req("r_icache_tlb_read_req"),
239	r_icache_tlb_rsp_error("r_icache_tlb_rsp_error"),
240
241	r_icache_cleanup_req("r_icache_cleanup_req"),
242	r_icache_cleanup_line("r_icache_cleanup_line"),
243
244	r_dcache_fsm("r_dcache_fsm"),
245	r_dcache_fsm_cc_save("r_dcache_fsm_cc_save"),
246	r_dcache_fsm_scan_save("r_dcache_fsm_scan_save"),
247
248	r_dcache_p0_valid("r_dcache_p0_valid"),
249	r_dcache_p0_vaddr("r_dcache_p0_vaddr"),
250	r_dcache_p0_wdata("r_dcache_p0_wdata"),
251	r_dcache_p0_be("r_dcache_p0_be"),
252	r_dcache_p0_paddr("r_dcache_p0_paddr"),
253	r_dcache_p0_cacheable("r_dcache_p0_cacheable"),
254
255	r_dcache_p1_valid("r_dcache_p1_valid"),
256	r_dcache_p1_wdata("r_dcache_p1_wdata"),
257	r_dcache_p1_be("r_dcache_p1_be"),
258	r_dcache_p1_paddr("r_dcache_p1_paddr"),
259	r_dcache_p1_cache_way("r_dcache_p1_cache_way"),
260	r_dcache_p1_cache_set("r_dcache_p1_cache_set"),
261	r_dcache_p1_cache_word("r_dcache_p1_word_save"),
262
263	r_dcache_dirty_paddr("r_dcache_dirty_paddr"),
264	r_dcache_dirty_way("r_dcache_dirty_way"),
265	r_dcache_dirty_set("r_dcache_dirty_set"),
266
267	r_dcache_vci_paddr("r_dcache_vci_paddr"),
268	r_dcache_vci_miss_req("r_dcache_vci_miss_req"),
269	r_dcache_vci_unc_req("r_dcache_vci_unc_req"),
270	r_dcache_vci_unc_be("r_dcache_vci_unc_be"),
271	r_dcache_vci_sc_req("r_dcache_vci_sc_req"),
272	r_dcache_vci_sc_old("r_dcache_vci_sc_old"),
273	r_dcache_vci_sc_new("r_dcache_vci_sc_new"),
274
275	r_dcache_xtn_way("r_dcache_xtn_way"),
276	r_dcache_xtn_set("r_dcache_xtn_set"),
277
278	r_dcache_pending_unc_write("r_dcache_pending_unc_write"),
279
280	r_dcache_miss_type("r_dcache_miss_type"),
281	r_dcache_miss_word("r_dcache_miss_word"),
282	r_dcache_miss_way("r_dcache_miss_way"),
283	r_dcache_miss_set("r_dcache_miss_set"),
284	r_dcache_miss_inval("r_dcache_miss_inval"),
285
286	r_dcache_cc_way("r_dcache_cc_way"),
287	r_dcache_cc_set("r_dcache_cc_set"),
288	r_dcache_cc_word("r_dcache_cc_word"),
289
290	r_dcache_flush_count("r_dcache_flush_count"),
291
292	r_dcache_tlb_vaddr("r_dcache_tlb_vaddr"),
293	r_dcache_tlb_ins("r_dcache_tlb_ins"),
294	r_dcache_tlb_pte_flags("r_dcache_tlb_pte_flags"),
295	r_dcache_tlb_pte_ppn("r_dcache_tlb_pte_ppn"),
296	r_dcache_tlb_cache_way("r_dcache_tlb_cache_way"),
297	r_dcache_tlb_cache_set("r_dcache_tlb_cache_set"),
298	r_dcache_tlb_cache_word("r_dcache_tlb_cache_word"),
299	r_dcache_tlb_way("r_dcache_tlb_way"),
300	r_dcache_tlb_set("r_dcache_tlb_set"),
301
302	r_dcache_ll_valid("r_dcache_ll_valid"),
303	r_dcache_ll_data("r_dcache_ll_data"),
304	r_dcache_ll_vaddr("r_dcache_ll_vaddr"),
305
306	r_dcache_tlb_inval_line("r_dcache_tlb_inval_line"),
307	r_dcache_tlb_inval_count("r_dcache_tlb_inval_count"),
308
309	r_dcache_xtn_req("r_dcache_xtn_req"),
310	r_dcache_xtn_opcode("r_dcache_xtn_opcode"),
311
312	r_dcache_cleanup_req("r_dcache_cleanup_req"),
313	r_dcache_cleanup_line("r_dcache_cleanup_line"),
314
315	r_vci_cmd_fsm("r_vci_cmd_fsm"),
316	r_vci_cmd_min("r_vci_cmd_min"),
317	r_vci_cmd_max("r_vci_cmd_max"),
318	r_vci_cmd_cpt("r_vci_cmd_cpt"),
319	r_vci_cmd_imiss_prio("r_vci_cmd_imiss_prio"),
320
321	r_vci_rsp_fsm("r_vci_rsp_fsm"),
322	r_vci_rsp_cpt("r_vci_rsp_cpt"),
323	r_vci_rsp_ins_error("r_vci_rsp_ins_error"),
324	r_vci_rsp_data_error("r_vci_rsp_data_error"),
325	r_vci_rsp_fifo_icache("r_vci_rsp_fifo_icache", 2), // 2 words depth
326	r_vci_rsp_fifo_dcache("r_vci_rsp_fifo_dcache", 2), // 2 words depth
327
328	r_cleanup_fsm("r_cleanup_fsm"),
329	r_cleanup_trdid("r_cleanup_trdid"),
330	r_cleanup_buffer(4), // up to 4 simultaneous cleanups
331
332	r_tgt_fsm("r_tgt_fsm"),
333	r_tgt_paddr("r_tgt_paddr"),
334	r_tgt_word_count("r_tgt_word_count"),
335	r_tgt_word_min("r_tgt_word_min"),
336	r_tgt_word_max("r_tgt_word_max"),
337	r_tgt_update("r_tgt_update"),
338	r_tgt_update_data("r_tgt_update_data"),
339	r_tgt_srcid("r_tgt_srcid"),
340	r_tgt_pktid("r_tgt_pktid"),
341	r_tgt_trdid("r_tgt_trdid"),
342
343	r_tgt_icache_req("r_tgt_icache_req"),
344	r_tgt_dcache_req("r_tgt_dcache_req"),
345	r_tgt_icache_rsp("r_tgt_icache_rsp"),
346	r_tgt_dcache_rsp("r_tgt_dcache_rsp"),
347
348	r_iss(this->name(), proc_id),
349	r_wbuf("wbuf", wbuf_nwords, wbuf_nlines, dcache_words ),
350	r_icache("icache", icache_ways, icache_sets, icache_words),
351	r_dcache("dcache", dcache_ways, dcache_sets, dcache_words),
352	r_itlb("itlb", proc_id, itlb_ways,itlb_sets,vci_param::N),
353	r_dtlb("dtlb", proc_id, dtlb_ways,dtlb_sets,vci_param::N)
354	{
355	assert( ((icache_words*vci_param::B) < (1<<vci_param::K)) and
356	"Need more PLEN bits.");
357
358	assert( (vci_param::T > 2) and ((1<<(vci_param::T-1)) >= (wbuf_nlines)) and
359	"Need more TRDID bits.");
360
361	assert( (icache_words == dcache_words) and
362	"icache_words and dcache_words parameters must be equal");
363
364	assert( (itlb_sets == dtlb_sets) and
365	"itlb_sets and dtlb_sets parameters must be etqual");
366
367	assert( (itlb_ways == dtlb_ways) and
368	"itlb_ways and dtlb_ways parameters must be etqual");
369
370	r_mmu_params = (uint32_log2(m_dtlb_ways) << 29) \| (uint32_log2(m_dtlb_sets) << 25) \|
371	(uint32_log2(m_dcache_ways) << 22) \| (uint32_log2(m_dcache_sets) << 18) \|
372	(uint32_log2(m_itlb_ways) << 15) \| (uint32_log2(m_itlb_sets) << 11) \|
373	(uint32_log2(m_icache_ways) << 8) \| (uint32_log2(m_icache_sets) << 4) \|
374	(uint32_log2(m_icache_words<<2));
375
376	r_mmu_release = (uint32_t)(1 << 16) \| 0x1;
377
378	r_tgt_buf = new uint32_t[dcache_words];
379	r_tgt_be = new vci_be_t[dcache_words];
380	r_dcache_in_tlb = new bool[dcache_ways*dcache_sets];
381	r_dcache_contains_ptd = new bool[dcache_ways*dcache_sets];
382
383	SC_METHOD(transition);
384	dont_initialize();
385	sensitive << p_clk.pos();
386
387	SC_METHOD(genMoore);
388	dont_initialize();
389	sensitive << p_clk.neg();
390
391	typename iss_t::CacheInfo cache_info;
392	cache_info.has_mmu = true;
393	cache_info.icache_line_size = icache_words*sizeof(uint32_t);
394	cache_info.icache_assoc = icache_ways;
395	cache_info.icache_n_lines = icache_sets;
396	cache_info.dcache_line_size = dcache_words*sizeof(uint32_t);
397	cache_info.dcache_assoc = dcache_ways;
398	cache_info.dcache_n_lines = dcache_sets;
399	r_iss.setCacheInfo(cache_info);
400	}
401
402	/////////////////////////////////////
403	tmpl(/**/)::~VciCcVCacheWrapperV4()
404	/////////////////////////////////////
405	{
406	delete [] r_tgt_be;
407	delete [] r_tgt_buf;
408	delete [] r_dcache_in_tlb;
409	delete [] r_dcache_contains_ptd;
410	}
411
412	////////////////////////
413	tmpl(void)::print_cpi()
414	////////////////////////
415	{
416	std::cout << name() << " CPI = "
417	<< (float)m_cpt_total_cycles/(m_cpt_total_cycles - m_cpt_frz_cycles) << std::endl ;
418	}
419
420	////////////////////////////////////
421	tmpl(void)::print_trace(size_t mode)
422	////////////////////////////////////
423	{
424	// b0 : write buffer trace
425	// b1 : write buffer verbose
426	// b2 : dcache trace
427	// b3 : icache trace
428	// b4 : dtlb trace
429	// b5 : itlb trace
430
431	std::cout << std::dec << "PROC " << name() << std::endl;
432
433	std::cout << " " << m_ireq << std::endl;
434	std::cout << " " << m_irsp << std::endl;
435	std::cout << " " << m_dreq << std::endl;
436	std::cout << " " << m_drsp << std::endl;
437
438	std::cout << " " << icache_fsm_state_str[r_icache_fsm.read()]
439	<< " \| " << dcache_fsm_state_str[r_dcache_fsm.read()]
440	<< " \| " << cmd_fsm_state_str[r_vci_cmd_fsm.read()]
441	<< " \| " << rsp_fsm_state_str[r_vci_rsp_fsm.read()]
442	<< " \| " << tgt_fsm_state_str[r_tgt_fsm.read()]
443	<< " \| " << cleanup_fsm_state_str[r_cleanup_fsm.read()];
444	if (r_dcache_p0_valid.read() ) std::cout << " \| P1_WRITE";
445	if (r_dcache_p1_valid.read() ) std::cout << " \| P2_WRITE";
446	std::cout << std::endl;
447
448	if(mode & 0x01)
449	{
450	r_wbuf.printTrace((mode>>1)&1);
451	}
452	if(mode & 0x04)
453	{
454	std::cout << " Data Cache" << std::endl;
455	r_dcache.printTrace();
456	}
457	if(mode & 0x08)
458	{
459	std::cout << " Instruction Cache" << std::endl;
460	r_icache.printTrace();
461	}
462	if(mode & 0x10)
463	{
464	std::cout << " Data TLB" << std::endl;
465	r_dtlb.printTrace();
466	}
467	if(mode & 0x20)
468	{
469	std::cout << " Instruction TLB" << std::endl;
470	r_itlb.printTrace();
471	}
472	}
473
474	//////////////////////////////////////////
475	tmpl(void)::cache_monitor( paddr_t addr )
476	//////////////////////////////////////////
477	{
478	size_t cache_way;
479	size_t cache_set;
480	size_t cache_word;
481	uint32_t cache_rdata;
482	bool cache_hit = r_dcache.read_neutral( addr,
483	&cache_rdata,
484	&cache_way,
485	&cache_set,
486	&cache_word );
487	bool icache_hit = r_icache.read_neutral( addr,
488	&cache_rdata,
489	&cache_way,
490	&cache_set,
491	&cache_word );
492	if ( cache_hit != m_debug_previous_hit )
493	{
494	std::cout << "PROC " << name()
495	<< " dcache change at cycle " << std::dec << m_cpt_total_cycles
496	<< " for adresse " << std::hex << addr
497	<< " / HIT = " << std::dec << cache_hit << std::endl;
498	m_debug_previous_hit = cache_hit;
499	}
500	if ( icache_hit != m_idebug_previous_hit )
501	{
502	std::cout << "PROC " << name()
503	<< " icache change at cycle " << std::dec << m_cpt_total_cycles
504	<< " for adresse " << std::hex << addr
505	<< " / HIT = " << icache_hit << std::endl;
506	m_idebug_previous_hit = icache_hit;
507	}
508	}
509
510	/*
511	////////////////////////
512	tmpl(void)::print_stats()
513	////////////////////////
514	{
515	float run_cycles = (float)(m_cpt_total_cycles - m_cpt_frz_cycles);
516	std::cout << name() << std::endl
517	<< "- CPI = " << (float)m_cpt_total_cycles/run_cycles << std::endl
518	<< "- READ RATE = " << (float)m_cpt_read/run_cycles << std::endl
519	<< "- WRITE RATE = " << (float)m_cpt_write/run_cycles << std::endl
520	<< "- IMISS_RATE = " << (float)m_cpt_ins_miss/m_cpt_ins_read << std::endl
521	<< "- DMISS RATE = " << (float)m_cpt_data_miss/(m_cpt_read-m_cpt_unc_read) << std::endl
522	<< "- INS MISS COST = " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl
523	<< "- DATA MISS COST = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl
524	<< "- WRITE COST = " << (float)m_cost_write_frz/m_cpt_write << std::endl
525	<< "- UNC COST = " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl
526	<< "- UNCACHED READ RATE = " << (float)m_cpt_unc_read/m_cpt_read << std::endl
527	<< "- CACHED WRITE RATE = " << (float)m_cpt_write_cached/m_cpt_write << std::endl
528	<< "- INS TLB MISS RATE = " << (float)m_cpt_ins_tlb_miss/m_cpt_ins_tlb_read << std::endl
529	<< "- DATA TLB MISS RATE = " << (float)m_cpt_data_tlb_miss/m_cpt_data_tlb_read << std::endl
530	<< "- ITLB MISS COST = " << (float)m_cost_ins_tlb_miss_frz/m_cpt_ins_tlb_miss << std::endl
531	<< "- DTLB MISS COST = " << (float)m_cost_data_tlb_miss_frz/m_cpt_data_tlb_miss << std::endl
532	<< "- ITLB UPDATE ACC COST = " << (float)m_cost_ins_tlb_update_acc_frz/m_cpt_ins_tlb_update_acc << std::endl
533	<< "- DTLB UPDATE ACC COST = " << (float)m_cost_data_tlb_update_acc_frz/m_cpt_data_tlb_update_acc << std::endl
534	<< "- DTLB UPDATE DIRTY COST = " << (float)m_cost_data_tlb_update_dirty_frz/m_cpt_data_tlb_update_dirty << std::endl
535	<< "- ITLB HIT IN DCACHE RATE= " << (float)m_cpt_ins_tlb_hit_dcache/m_cpt_ins_tlb_miss << std::endl
536	<< "- DTLB HIT IN DCACHE RATE= " << (float)m_cpt_data_tlb_hit_dcache/m_cpt_data_tlb_miss << std::endl
537	<< "- DCACHE FROZEN BY ITLB = " << (float)m_cost_ins_tlb_occup_cache_frz/m_cpt_dcache_frz_cycles << std::endl
538	<< "- DCACHE FOR TLB % = " << (float)m_cpt_tlb_occup_dcache/(m_dcache_ways*m_dcache_sets) << std::endl
539	<< "- NB CC BROADCAST = " << m_cpt_cc_broadcast << std::endl
540	<< "- NB CC UPDATE DATA = " << m_cpt_cc_update_data << std::endl
541	<< "- NB CC INVAL DATA = " << m_cpt_cc_inval_data << std::endl
542	<< "- NB CC INVAL INS = " << m_cpt_cc_inval_ins << std::endl
543	<< "- CC BROADCAST COST = " << (float)m_cost_broadcast_frz/m_cpt_cc_broadcast << std::endl
544	<< "- CC UPDATE DATA COST = " << (float)m_cost_updt_data_frz/m_cpt_cc_update_data << std::endl
545	<< "- CC INVAL DATA COST = " << (float)m_cost_inval_data_frz/m_cpt_cc_inval_data << std::endl
546	<< "- CC INVAL INS COST = " << (float)m_cost_inval_ins_frz/m_cpt_cc_inval_ins << std::endl
547	<< "- NB CC CLEANUP DATA = " << m_cpt_cc_cleanup_data << std::endl
548	<< "- NB CC CLEANUP INS = " << m_cpt_cc_cleanup_ins << std::endl
549	<< "- IMISS TRANSACTION = " << (float)m_cost_imiss_transaction/m_cpt_imiss_transaction << std::endl
550	<< "- DMISS TRANSACTION = " << (float)m_cost_dmiss_transaction/m_cpt_dmiss_transaction << std::endl
551	<< "- UNC TRANSACTION = " << (float)m_cost_unc_transaction/m_cpt_unc_transaction << std::endl
552	<< "- WRITE TRANSACTION = " << (float)m_cost_write_transaction/m_cpt_write_transaction << std::endl
553	<< "- WRITE LENGTH = " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl
554	<< "- ITLB MISS TRANSACTION = " << (float)m_cost_itlbmiss_transaction/m_cpt_itlbmiss_transaction << std::endl
555	<< "- DTLB MISS TRANSACTION = " << (float)m_cost_dtlbmiss_transaction/m_cpt_dtlbmiss_transaction << std::endl;
556	}
557
558	////////////////////////
559	tmpl(void)::clear_stats()
560	////////////////////////
561	{
562	m_cpt_dcache_data_read = 0;
563	m_cpt_dcache_data_write = 0;
564	m_cpt_dcache_dir_read = 0;
565	m_cpt_dcache_dir_write = 0;
566	m_cpt_icache_data_read = 0;
567	m_cpt_icache_data_write = 0;
568	m_cpt_icache_dir_read = 0;
569	m_cpt_icache_dir_write = 0;
570
571	m_cpt_frz_cycles = 0;
572	m_cpt_dcache_frz_cycles = 0;
573	m_cpt_total_cycles = 0;
574
575	m_cpt_read = 0;
576	m_cpt_write = 0;
577	m_cpt_data_miss = 0;
578	m_cpt_ins_miss = 0;
579	m_cpt_unc_read = 0;
580	m_cpt_write_cached = 0;
581	m_cpt_ins_read = 0;
582
583	m_cost_write_frz = 0;
584	m_cost_data_miss_frz = 0;
585	m_cost_unc_read_frz = 0;
586	m_cost_ins_miss_frz = 0;
587
588	m_cpt_imiss_transaction = 0;
589	m_cpt_dmiss_transaction = 0;
590	m_cpt_unc_transaction = 0;
591	m_cpt_write_transaction = 0;
592	m_cpt_icache_unc_transaction = 0;
593
594	m_cost_imiss_transaction = 0;
595	m_cost_dmiss_transaction = 0;
596	m_cost_unc_transaction = 0;
597	m_cost_write_transaction = 0;
598	m_cost_icache_unc_transaction = 0;
599	m_length_write_transaction = 0;
600
601	m_cpt_ins_tlb_read = 0;
602	m_cpt_ins_tlb_miss = 0;
603	m_cpt_ins_tlb_update_acc = 0;
604
605	m_cpt_data_tlb_read = 0;
606	m_cpt_data_tlb_miss = 0;
607	m_cpt_data_tlb_update_acc = 0;
608	m_cpt_data_tlb_update_dirty = 0;
609	m_cpt_ins_tlb_hit_dcache = 0;
610	m_cpt_data_tlb_hit_dcache = 0;
611	m_cpt_ins_tlb_occup_cache = 0;
612	m_cpt_data_tlb_occup_cache = 0;
613
614	m_cost_ins_tlb_miss_frz = 0;
615	m_cost_data_tlb_miss_frz = 0;
616	m_cost_ins_tlb_update_acc_frz = 0;
617	m_cost_data_tlb_update_acc_frz = 0;
618	m_cost_data_tlb_update_dirty_frz = 0;
619	m_cost_ins_tlb_occup_cache_frz = 0;
620	m_cost_data_tlb_occup_cache_frz = 0;
621
622	m_cpt_itlbmiss_transaction = 0;
623	m_cpt_itlb_ll_transaction = 0;
624	m_cpt_itlb_sc_transaction = 0;
625	m_cpt_dtlbmiss_transaction = 0;
626	m_cpt_dtlb_ll_transaction = 0;
627	m_cpt_dtlb_sc_transaction = 0;
628	m_cpt_dtlb_ll_dirty_transaction = 0;
629	m_cpt_dtlb_sc_dirty_transaction = 0;
630
631	m_cost_itlbmiss_transaction = 0;
632	m_cost_itlb_ll_transaction = 0;
633	m_cost_itlb_sc_transaction = 0;
634	m_cost_dtlbmiss_transaction = 0;
635	m_cost_dtlb_ll_transaction = 0;
636	m_cost_dtlb_sc_transaction = 0;
637	m_cost_dtlb_ll_dirty_transaction = 0;
638	m_cost_dtlb_sc_dirty_transaction = 0;
639
640	m_cpt_cc_update_data = 0;
641	m_cpt_cc_inval_ins = 0;
642	m_cpt_cc_inval_data = 0;
643	m_cpt_cc_broadcast = 0;
644
645	m_cost_updt_data_frz = 0;
646	m_cost_inval_ins_frz = 0;
647	m_cost_inval_data_frz = 0;
648	m_cost_broadcast_frz = 0;
649
650	m_cpt_cc_cleanup_data = 0;
651	m_cpt_cc_cleanup_ins = 0;
652	}
653
654	*/
655
656	/////////////////////////
657	tmpl(void)::transition()
658	/////////////////////////
659	{
660	if ( not p_resetn.read() )
661	{
662	r_iss.reset();
663	r_wbuf.reset();
664	r_icache.reset();
665	r_dcache.reset();
666	r_itlb.reset();
667	r_dtlb.reset();
668
669	r_dcache_fsm = DCACHE_IDLE;
670	r_icache_fsm = ICACHE_IDLE;
671	r_vci_cmd_fsm = CMD_IDLE;
672	r_vci_rsp_fsm = RSP_IDLE;
673	r_tgt_fsm = TGT_IDLE;
674	r_cleanup_fsm = CLEANUP_DATA_IDLE;
675
676	// reset dcache directory extension
677	for (size_t i=0 ; i< m_dcache_ways*m_dcache_sets ; i++)
678	{
679	r_dcache_in_tlb[i] = false;
680	r_dcache_contains_ptd[i] = false;
681	}
682
683	// Response FIFOs and cleanup buffer
684	r_vci_rsp_fifo_icache.init();
685	r_vci_rsp_fifo_dcache.init();
686	r_cleanup_buffer.reset();
687
688	// ICACHE & DCACHE activated
689	r_mmu_mode = 0x3;
690
691	// No request from ICACHE FSM to CMD FSM
692	r_icache_miss_req = false;
693	r_icache_unc_req = false;
694
695	// No request from ICACHE_FSM to DCACHE FSM
696	r_icache_tlb_miss_req = false;
697
698	// No request from ICACHE_FSM to CLEANUP FSMs
699	r_icache_cleanup_req = false;
700
701	// No pending write in pipeline
702	r_dcache_p0_valid = false;
703	r_dcache_p1_valid = false;
704
705	// No request from DCACHE_FSM to CMD_FSM
706	r_dcache_vci_miss_req = false;
707	r_dcache_vci_unc_req = false;
708	r_dcache_vci_sc_req = false;
709
710	// No uncacheable write pending
711	r_dcache_pending_unc_write = false;
712
713	// No LL reservation
714	r_dcache_ll_valid = false;
715
716	// No processor XTN request pending
717	r_dcache_xtn_req = false;
718
719	// No request from DCACHE FSM to CLEANUP FSMs
720	r_dcache_cleanup_req = false;
721
722	// No request from TGT FSM to ICACHE/DCACHE FSMs
723	r_tgt_icache_req = false;
724	r_tgt_dcache_req = false;
725
726	// No signalisation of a coherence request matching a pending miss
727	r_icache_miss_inval = false;
728	r_dcache_miss_inval = false;
729
730	// No signalisation of errors
731	r_vci_rsp_ins_error = false;
732	r_vci_rsp_data_error = false;
733
734	// Debug variables
735	m_debug_previous_hit = false;
736	m_idebug_previous_hit = false;
737	m_debug_dcache_fsm = false;
738	m_debug_icache_fsm = false;
739	m_debug_cleanup_fsm = false;
740
741	// activity counters
742	m_cpt_dcache_data_read = 0;
743	m_cpt_dcache_data_write = 0;
744	m_cpt_dcache_dir_read = 0;
745	m_cpt_dcache_dir_write = 0;
746	m_cpt_icache_data_read = 0;
747	m_cpt_icache_data_write = 0;
748	m_cpt_icache_dir_read = 0;
749	m_cpt_icache_dir_write = 0;
750
751	m_cpt_frz_cycles = 0;
752	m_cpt_total_cycles = 0;
753	m_cpt_stop_simulation = 0;
754
755	m_cpt_data_miss = 0;
756	m_cpt_ins_miss = 0;
757	m_cpt_unc_read = 0;
758	m_cpt_write_cached = 0;
759	m_cpt_ins_read = 0;
760
761	m_cost_write_frz = 0;
762	m_cost_data_miss_frz = 0;
763	m_cost_unc_read_frz = 0;
764	m_cost_ins_miss_frz = 0;
765
766	m_cpt_imiss_transaction = 0;
767	m_cpt_dmiss_transaction = 0;
768	m_cpt_unc_transaction = 0;
769	m_cpt_write_transaction = 0;
770	m_cpt_icache_unc_transaction = 0;
771
772	m_cost_imiss_transaction = 0;
773	m_cost_dmiss_transaction = 0;
774	m_cost_unc_transaction = 0;
775	m_cost_write_transaction = 0;
776	m_cost_icache_unc_transaction = 0;
777	m_length_write_transaction = 0;
778
779	m_cpt_ins_tlb_read = 0;
780	m_cpt_ins_tlb_miss = 0;
781	m_cpt_ins_tlb_update_acc = 0;
782
783	m_cpt_data_tlb_read = 0;
784	m_cpt_data_tlb_miss = 0;
785	m_cpt_data_tlb_update_acc = 0;
786	m_cpt_data_tlb_update_dirty = 0;
787	m_cpt_ins_tlb_hit_dcache = 0;
788	m_cpt_data_tlb_hit_dcache = 0;
789	m_cpt_ins_tlb_occup_cache = 0;
790	m_cpt_data_tlb_occup_cache = 0;
791
792	m_cost_ins_tlb_miss_frz = 0;
793	m_cost_data_tlb_miss_frz = 0;
794	m_cost_ins_tlb_update_acc_frz = 0;
795	m_cost_data_tlb_update_acc_frz = 0;
796	m_cost_data_tlb_update_dirty_frz = 0;
797	m_cost_ins_tlb_occup_cache_frz = 0;
798	m_cost_data_tlb_occup_cache_frz = 0;
799
800	m_cpt_ins_tlb_inval = 0;
801	m_cpt_data_tlb_inval = 0;
802	m_cost_ins_tlb_inval_frz = 0;
803	m_cost_data_tlb_inval_frz = 0;
804
805	m_cpt_cc_broadcast = 0;
806
807	m_cost_updt_data_frz = 0;
808	m_cost_inval_ins_frz = 0;
809	m_cost_inval_data_frz = 0;
810	m_cost_broadcast_frz = 0;
811
812	m_cpt_cc_cleanup_data = 0;
813	m_cpt_cc_cleanup_ins = 0;
814
815	m_cpt_itlbmiss_transaction = 0;
816	m_cpt_itlb_ll_transaction = 0;
817	m_cpt_itlb_sc_transaction = 0;
818	m_cpt_dtlbmiss_transaction = 0;
819	m_cpt_dtlb_ll_transaction = 0;
820	m_cpt_dtlb_sc_transaction = 0;
821	m_cpt_dtlb_ll_dirty_transaction = 0;
822	m_cpt_dtlb_sc_dirty_transaction = 0;
823
824	m_cost_itlbmiss_transaction = 0;
825	m_cost_itlb_ll_transaction = 0;
826	m_cost_itlb_sc_transaction = 0;
827	m_cost_dtlbmiss_transaction = 0;
828	m_cost_dtlb_ll_transaction = 0;
829	m_cost_dtlb_sc_transaction = 0;
830	m_cost_dtlb_ll_dirty_transaction = 0;
831	m_cost_dtlb_sc_dirty_transaction = 0;
832	/*
833	m_cpt_dcache_frz_cycles = 0;
834	m_cpt_read = 0;
835	m_cpt_write = 0;
836	m_cpt_cc_update_data = 0;
837	m_cpt_cc_inval_ins = 0;
838	m_cpt_cc_inval_data = 0;
839	*/
840
841	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_icache [i] = 0;
842	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_dcache [i] = 0;
843	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_cmd [i] = 0;
844	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_rsp [i] = 0;
845	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_tgt [i] = 0;
846	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_cmd_cleanup [i] = 0;
847	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_rsp_cleanup [i] = 0;
848
849	return;
850	}
851
852	// Response FIFOs default values
853	bool vci_rsp_fifo_icache_get = false;
854	bool vci_rsp_fifo_icache_put = false;
855	uint32_t vci_rsp_fifo_icache_data = 0;
856
857	bool vci_rsp_fifo_dcache_get = false;
858	bool vci_rsp_fifo_dcache_put = false;
859	uint32_t vci_rsp_fifo_dcache_data = 0;
860
861	#ifdef INSTRUMENTATION
862	m_cpt_fsm_dcache [r_dcache_fsm.read() ] ++;
863	m_cpt_fsm_icache [r_icache_fsm.read() ] ++;
864	m_cpt_fsm_cmd [r_vci_cmd_fsm.read()] ++;
865	m_cpt_fsm_rsp [r_vci_rsp_fsm.read()] ++;
866	m_cpt_fsm_tgt [r_tgt_fsm.read() ] ++;
867	m_cpt_fsm_cleanup [r_cleanup_fsm.read()] ++;
868	#endif
869
870	m_cpt_total_cycles++;
871
872	m_debug_cleanup_fsm = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok;
873	m_debug_icache_fsm = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok;
874	m_debug_dcache_fsm = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok;
875
876	/////////////////////////////////////////////////////////////////////
877	// The TGT_FSM controls the following ressources:
878	// - r_tgt_fsm
879	// - r_tgt_buf[nwords]
880	// - r_tgt_be[nwords]
881	// - r_tgt_update
882	// - r_tgt_word_min
883	// - r_tgt_word_max
884	// - r_tgt_word_count
885	// - r_tgt_paddr
886	// - r_tgt_srcid
887	// - r_tgt_trdid
888	// - r_tgt_pktid
889	// - r_tgt_icache_req (set)
890	// - r_tgt_dcache_req (set)
891	//
892	// All VCI commands must be CMD_WRITE.
893	// - If the 2 LSB bits of the VCI address are 11, it is a broadcast request.
894	// It is a multicast request otherwise.
895	// - For multicast requests, the ADDRESS[2] bit distinguishes DATA/INS
896	// (0 for data / 1 for instruction), and the ADDRESS[3] bit distinguishes
897	// INVAL/UPDATE (0 for invalidate / 1 for UPDATE).
898	//
899	// For all types of coherence request, the line index (i.e. the Z & Y fields)
900	// is coded on 34 bits, and is contained in the WDATA and BE fields
901	// of the first VCI flit.
902	// - for a multicast invalidate or for a broadcast invalidate request
903	// the VCI packet length is 1 word.
904	// - for an update request the VCI packet length is (n+2) words.
905	// The WDATA field of the second VCI word contains the word index.
906	// The WDATA field of the n following words contains the values.
907	// - for all transaction types, the VCI response is one single word.
908	// In case of errors in the VCI command packet, the simulation
909	// is stopped with an error message.
910	//
911	// This FSM is NOT pipelined : It consumes a new coherence request
912	// on the VCI port only when the previous request is completed.
913	//
914	// The VCI_TGT FSM stores the external request arguments in the
915	// IDLE, UPDT_WORD & UPDT_DATA states. It sets the r_tgt_icache_req
916	// and/or the r_tgt_dcache_req flip-flops to signal the coherence request
917	// to the ICACHE & DCACHE FSMs in the REQ_ICACHE, REQ_DCACHE & REQ_BROADCAST
918	// states. It waits the completion of the coherence request by polling the
919	// r_tgt_*cache_req flip-flops in the RSP_ICACHE, RSP_DCACHE & RSP_BROADCAST
920	// states. These flip-flops are reset by the ICACHE and DCACHE FSMs.
921	// These two FSMs signal if a VCI answer must be send by setting
922	// the r_tgt_icache_rsp and/or the r_tgt_dcache_rsp flip_flops.
923	///////////////////////////////////////////////////////////////////////////////
924
925	switch( r_tgt_fsm.read() )
926	{
927	//////////////
928	case TGT_IDLE:
929	{
930	if ( p_vci_tgt_c.cmdval.read() )
931	{
932	paddr_t address = p_vci_tgt_c.address.read();
933
934	// command checking
935	if ( p_vci_tgt_c.cmd.read() != vci_param::CMD_WRITE)
936	{
937	std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
938	std::cout << "the received VCI coherence command is not a write" << std::endl;
939	exit(0);
940	}
941
942	// address checking
943	if ( ( (address & 0x3) != 0x3 ) && ( not m_segment.contains(address)) )
944	{
945	std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
946	std::cout << "out of segment VCI coherence command received" << std::endl;
947	exit(0);
948	}
949
950	r_tgt_srcid = p_vci_tgt_c.srcid.read();
951	r_tgt_trdid = p_vci_tgt_c.trdid.read();
952	r_tgt_pktid = p_vci_tgt_c.pktid.read();
953
954	if (sizeof(paddr_t) <= 32) {
955	assert(p_vci_tgt_c.be.read() == 0 && "byte enable should be 0 for 32bits paddr");
956	r_tgt_paddr =
957	(paddr_t)p_vci_tgt_c.wdata.read() * m_dcache_words * 4;
958	} else {
959	r_tgt_paddr = (paddr_t)(p_vci_tgt_c.be.read() & 0x3) << 32 \|
960	(paddr_t)p_vci_tgt_c.wdata.read() * m_dcache_words * 4;
961	}
962
963	if ( (address&0x3) == 0x3 ) // broadcast invalidate for data or instruction type
964	{
965	if ( not p_vci_tgt_c.eop.read() )
966	{
967	std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
968	std::cout << "the BROADCAST INVALIDATE command must be one flit" << std::endl;
969	exit(0);
970	}
971	r_tgt_update = false;
972	r_tgt_fsm = TGT_REQ_BROADCAST;
973
974	#ifdef INSTRUMENTATION
975	m_cpt_cc_broadcast++;
976	#endif
977	}
978	else // multi-update or multi-invalidate for data type
979	{
980	paddr_t cell = address - m_segment.baseAddress();
981
982	if (cell == 0) // invalidate data
983	{
984	if ( not p_vci_tgt_c.eop.read() )
985	{
986	std::cout << "error in VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
987	std::cout << "the MULTI-INVALIDATE command must be one flit" << std::endl;
988	exit(0);
989	}
990	r_tgt_update = false;
991	r_tgt_fsm = TGT_REQ_DCACHE;
992
993	#ifdef INSTRUMENTATION
994	m_cpt_cc_inval_dcache++;
995	#endif
996	}
997	else if (cell == 4) // invalidate instruction
998	{
999	if ( not p_vci_tgt_c.eop.read() )
1000	{
1001	std::cout << "error in VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
1002	std::cout << "the MULTI-INVALIDATE command must be one flit" << std::endl;
1003	exit(0);
1004	}
1005	r_tgt_update = false;
1006	r_tgt_fsm = TGT_REQ_ICACHE;
1007
1008	#ifdef INSTRUMENTATION
1009	m_cpt_cc_inval_icache++;
1010	#endif
1011	}
1012	else if (cell == 8) // update data
1013	{
1014	if ( p_vci_tgt_c.eop.read() )
1015	{
1016	std::cout << "error in VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
1017	std::cout << "the MULTI-UPDATE command must be N+2 flits" << std::endl;
1018	exit(0);
1019	}
1020	r_tgt_update = true;
1021	r_tgt_update_data = true;
1022	r_tgt_fsm = TGT_UPDT_WORD;
1023
1024	#ifdef INSTRUMENTATION
1025	m_cpt_cc_update_dcache++;
1026	#endif
1027	}
1028	else // update instruction
1029	{
1030	if ( p_vci_tgt_c.eop.read() )
1031	{
1032	std::cout << "error in VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
1033	std::cout << "the MULTI-UPDATE command must be N+2 flits" << std::endl;
1034	exit(0);
1035	}
1036	r_tgt_update = true;
1037	r_tgt_update_data = false;
1038	r_tgt_fsm = TGT_UPDT_WORD;
1039
1040	#ifdef INSTRUMENTATION
1041	m_cpt_cc_update_icache++;
1042	#endif
1043	}
1044	} // end if multi
1045	} // end if cmdval
1046	break;
1047	}
1048	///////////////////
1049	case TGT_UPDT_WORD: // first word index acquisition
1050	{
1051	if (p_vci_tgt_c.cmdval.read())
1052	{
1053	if ( p_vci_tgt_c.eop.read() )
1054	{
1055	std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
1056	std::cout << "the MULTI-UPDATE command must be N+2 flits" << std::endl;
1057	exit(0);
1058	}
1059	for ( size_t i=0 ; i<m_dcache_words ; i++ ) r_tgt_be[i] = false;
1060
1061	r_tgt_word_min = p_vci_tgt_c.wdata.read(); // first modifid word index
1062	r_tgt_word_count = p_vci_tgt_c.wdata.read(); // initializing word index
1063	r_tgt_fsm = TGT_UPDT_DATA;
1064	}
1065	break;
1066	}
1067	///////////////////
1068	case TGT_UPDT_DATA:
1069	{
1070	if (p_vci_tgt_c.cmdval.read())
1071	{
1072	size_t word = r_tgt_word_count.read();
1073	if (word >= m_dcache_words)
1074	{
1075	std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
1076	std::cout << "the reveived MULTI-UPDATE command is wrong" << std::endl;
1077	exit(0);
1078	}
1079	r_tgt_buf[word] = p_vci_tgt_c.wdata.read();
1080	r_tgt_be[word] = p_vci_tgt_c.be.read();
1081	r_tgt_word_count = word + 1;
1082
1083	if (p_vci_tgt_c.eop.read()) // last word
1084	{
1085	r_tgt_word_max = word;
1086	if ( r_tgt_update_data.read() ) r_tgt_fsm = TGT_REQ_DCACHE;
1087	else r_tgt_fsm = TGT_REQ_ICACHE;
1088	}
1089	}
1090	break;
1091	}
1092	///////////////////////
1093	case TGT_REQ_BROADCAST: // set requests to DCACHE & ICACHE FSMs
1094	{
1095	if ( not r_tgt_icache_req.read() and not r_tgt_dcache_req.read() )
1096	{
1097	r_tgt_fsm = TGT_RSP_BROADCAST;
1098	r_tgt_icache_req = true;
1099	r_tgt_dcache_req = true;
1100	}
1101	break;
1102	}
1103	/////////////////////
1104	case TGT_REQ_ICACHE: // set request to ICACHE FSM (if no previous request pending)
1105	{
1106	if ( not r_tgt_icache_req.read() )
1107	{
1108	r_tgt_fsm = TGT_RSP_ICACHE;
1109	r_tgt_icache_req = true;
1110	}
1111	break;
1112	}
1113	////////////////////
1114	case TGT_REQ_DCACHE: // set request to DCACHE FSM (if no previous request pending)
1115	{
1116	if ( not r_tgt_dcache_req.read() )
1117	{
1118	r_tgt_fsm = TGT_RSP_DCACHE;
1119	r_tgt_dcache_req = true;
1120	}
1121	break;
1122	}
1123	///////////////////////
1124	case TGT_RSP_BROADCAST: // waiting acknowledge from both DCACHE & ICACHE FSMs
1125	// no response when r_tgt_*cache_rsp is false
1126	{
1127	if ( not r_tgt_icache_req.read() and not r_tgt_dcache_req.read() ) // both completed
1128	{
1129	if ( r_tgt_icache_rsp.read() or r_tgt_dcache_rsp.read() ) // at least one response
1130	{
1131	if ( p_vci_tgt_c.rspack.read() )
1132	{
1133	// reset dcache first if activated
1134	if (r_tgt_dcache_rsp) r_tgt_dcache_rsp = false;
1135	else r_tgt_icache_rsp = false;
1136	}
1137	}
1138	else
1139	{
1140	r_tgt_fsm = TGT_IDLE;
1141	}
1142	}
1143	break;
1144	}
1145	////////////////////
1146	case TGT_RSP_ICACHE: // waiting acknowledge from ICACHE FSM
1147	{
1148	// no response when r_tgt_icache_rsp is false
1149	if ( not r_tgt_icache_req.read() and p_vci_tgt_c.rspack.read() )
1150	{
1151	r_tgt_fsm = TGT_IDLE;
1152	r_tgt_icache_rsp = false;
1153	}
1154	break;
1155	}
1156	////////////////////
1157	case TGT_RSP_DCACHE:
1158	{
1159	// no response when r_tgt_dcache_rsp is false
1160	if ( not r_tgt_dcache_req.read() and p_vci_tgt_c.rspack.read() )
1161	{
1162	r_tgt_fsm = TGT_IDLE;
1163	r_tgt_dcache_rsp = false;
1164	}
1165	break;
1166	}
1167	} // end switch TGT_FSM
1168
1169	/////////////////////////////////////////////////////////////////////
1170	// Get data and instruction requests from processor
1171	///////////////////////////////////////////////////////////////////////
1172
1173	r_iss.getRequests(m_ireq, m_dreq);
1174
1175	////////////////////////////////////////////////////////////////////////////////////
1176	// ICACHE_FSM
1177	//
1178	// There is 9 conditions to exit the IDLE state:
1179	// One condition is a coherence request from TGT FSM :
1180	// - Coherence operation => ICACHE_CC_CHEK
1181	// Five configurations corresponding to XTN processor requests sent by DCACHE FSM :
1182	// - Flush TLB => ICACHE_XTN_TLB_FLUSH
1183	// - Flush cache => ICACHE_XTN_CACHE_FLUSH
1184	// - Invalidate a TLB entry => ICACHE_XTN_TLB_INVAL
1185	// - Invalidate a cache line => ICACHE_XTN_CACHE_INVAL_VA@
1186	// - Invalidate a cache line using physical address => ICACHE_XTN_CACHE_INVAL_PA
1187	// three configurations corresponding to instruction processor requests :
1188	// - tlb miss => ICACHE_TLB_WAIT
1189	// - cacheable read miss => ICACHE_MISS_VICTIM
1190	// - uncacheable read miss => ICACHE_UNC_REQ
1191	//
1192	// In case of cache miss, the ICACHE FSM request a VCI transaction to CMD FSM
1193	// using the r_icache_tlb_miss_req flip-flop, that reset this flip-flop when the
1194	// transaction starts. Then the ICACHE FSM goes to the ICACHE_MISS VICTIM
1195	// state to select a slot and request a VCI transaction to the CLEANUP FSM.
1196	// It goes next to the ICACHE_MISS_WAIT state waiting a response from RSP FSM.
1197	// The availability of the missing cache line is signaled by the response fifo,
1198	// and the cache update is done (one word per cycle) in the ICACHE_MISS_UPDT state.
1199	//
1200	// In case of uncacheable address, the ICACHE FSM request an uncached VCI transaction
1201	// to CMD FSM using the r_icache_unc_req flip-flop, that reset this flip-flop
1202	// when the transaction starts. The ICACHE FSM goes to ICACHE_UNC_WAIT to wait
1203	// the response from the RSP FSM, through the response fifo. The missing instruction
1204	// is directly returned to processor in this state.
1205	//
1206	// In case of tlb miss, the ICACHE FSM request to the DCACHE FSM to update the tlb
1207	// using the r_icache_tlb_miss_req flip-flop and the r_icache_tlb_miss_vaddr register,
1208	// and goes to the ICACHE_TLB_WAIT state.
1209	// The tlb update is entirely done by the DCACHE FSM (who becomes the owner of dtlb until
1210	// the update is completed, and reset r_icache_tlb_miss_req to signal the completion.
1211	//
1212	// The DCACHE FSM signals XTN processor requests to ICACHE_FSM
1213	// using the r_dcache_xtn_req flip-flop.
1214	// The request opcode and the address to be invalidated are transmitted
1215	// in the r_dcache_xtn_opcode and r_dcache_p0_wdata registers respectively.
1216	// The r_dcache_xtn_req flip-flop is reset by the ICACHE_FSM when the operation
1217	// is completed.
1218	//
1219	// The r_vci_rsp_ins_error flip-flop is set by the RSP FSM in case of bus error
1220	// in a cache miss or uncacheable read VCI transaction. Nothing is written
1221	// in the response fifo. This flip-flop is reset by the ICACHE-FSM.
1222	////////////////////////////////////////////////////////////////////////////////////////
1223
1224	// default value for m_irsp
1225	m_irsp.valid = false;
1226	m_irsp.error = false;
1227	m_irsp.instruction = 0;
1228
1229	switch( r_icache_fsm.read() )
1230	{
1231	/////////////////
1232	case ICACHE_IDLE: // In this state, we handle processor requests, XTN requests sent
1233	// by DCACHE FSM, and coherence requests with a fixed priority:
1234	// coherence > XTN > instruction
1235	// We access the itlb and dcache in parallel with the virtual address
1236	// for itlb, and with a speculative physical address for icache,
1237	// computed during the previous cycle.
1238	{
1239	// coherence request from the target FSM
1240	if ( r_tgt_icache_req.read() )
1241	{
1242	r_icache_fsm = ICACHE_CC_CHECK;
1243	r_icache_fsm_save = r_icache_fsm.read();
1244	break;
1245	}
1246
1247	// Decoding processor XTN requests sent by DCACHE FSM
1248	// These request are not executed in this IDLE state, because
1249	// they require access to icache or itlb, that are already accessed
1250	if ( r_dcache_xtn_req.read() )
1251	{
1252	if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_PTPR )
1253	{
1254	r_icache_fsm = ICACHE_XTN_TLB_FLUSH;
1255	break;
1256	}
1257	if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ICACHE_FLUSH)
1258	{
1259	r_icache_flush_count = 0;
1260	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH;
1261	break;
1262	}
1263	if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ITLB_INVAL)
1264	{
1265	r_icache_fsm = ICACHE_XTN_TLB_INVAL;
1266	break;
1267	}
1268	if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ICACHE_INVAL)
1269	{
1270	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_VA;
1271	break;
1272	}
1273	if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_MMU_ICACHE_PA_INV)
1274	{
1275	if (sizeof(paddr_t) <= 32) {
1276	assert(r_mmu_word_hi.read() == 0 &&
1277	"high bits should be 0 for 32bit paddr");
1278	r_icache_vci_paddr = (paddr_t)r_mmu_word_lo.read();
1279	} else {
1280	r_icache_vci_paddr =
1281	(paddr_t)r_mmu_word_hi.read() << 32 \|
1282	(paddr_t)r_mmu_word_lo.read();
1283	}
1284	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA;
1285	break;
1286	}
1287	} // end if xtn_req
1288
1289	// processor request
1290	if ( m_ireq.valid )
1291	{
1292	bool cacheable;
1293	paddr_t paddr;
1294
1295	// We register processor request
1296	r_icache_vaddr_save = m_ireq.addr;
1297
1298	// speculative icache access (if cache activated)
1299	// we use the speculative PPN computed during the previous cycle
1300
1301	uint32_t cache_inst = 0;
1302	bool cache_hit = false;
1303
1304	if ( r_mmu_mode.read() & INS_CACHE_MASK )
1305	{
1306	paddr_t spc_paddr = (r_icache_vci_paddr.read() & ~PAGE_K_MASK) \|
1307	((paddr_t)m_ireq.addr & PAGE_K_MASK);
1308
1309	#ifdef INSTRUMENTATION
1310	m_cpt_icache_data_read++;
1311	m_cpt_icache_dir_read++;
1312	#endif
1313	cache_hit = r_icache.read( spc_paddr,
1314	&cache_inst );
1315	}
1316
1317	// systematic itlb access (if tlb activated)
1318	// we use the virtual address
1319
1320	paddr_t tlb_paddr;
1321	pte_info_t tlb_flags;
1322	size_t tlb_way;
1323	size_t tlb_set;
1324	paddr_t tlb_nline;
1325	bool tlb_hit = false;;
1326
1327	if ( r_mmu_mode.read() & INS_TLB_MASK )
1328	{
1329
1330	#ifdef INSTRUMENTATION
1331	m_cpt_itlb_read++;
1332	#endif
1333	tlb_hit = r_itlb.translate( m_ireq.addr,
1334	&tlb_paddr,
1335	&tlb_flags,
1336	&tlb_nline, // unused
1337	&tlb_way, // unused
1338	&tlb_set ); // unused
1339	}
1340
1341	// We compute cacheability, physical address and check access rights:
1342	// - If MMU activated : cacheability is defined by the C bit in the PTE,
1343	// the physical address is obtained from the TLB, and the access rights are
1344	// defined by the U and X bits in the PTE.
1345	// - If MMU not activated : cacheability is defined by the segment table,
1346	// the physical address is equal to the virtual address (identity mapping)
1347	// and there is no access rights checking
1348
1349	if ( not (r_mmu_mode.read() & INS_TLB_MASK) ) // tlb not activated:
1350	{
1351	// cacheability
1352	if ( not (r_mmu_mode.read() & INS_CACHE_MASK) ) cacheable = false;
1353	else cacheable = m_cacheability_table[m_ireq.addr];
1354
1355	// physical address
1356	paddr = (paddr_t)m_ireq.addr;
1357	}
1358	else // itlb activated
1359	{
1360	if ( tlb_hit ) // tlb hit
1361	{
1362	// cacheability
1363	if ( not (r_mmu_mode.read() & INS_CACHE_MASK) ) cacheable = false;
1364	else cacheable = tlb_flags.c;
1365
1366	// physical address
1367	paddr = tlb_paddr;
1368
1369	// access rights checking
1370	if ( not tlb_flags.u && (m_ireq.mode == iss_t::MODE_USER) )
1371	{
1372	r_mmu_ietr = MMU_READ_PRIVILEGE_VIOLATION;
1373	r_mmu_ibvar = m_ireq.addr;
1374	m_irsp.valid = true;
1375	m_irsp.error = true;
1376	m_irsp.instruction = 0;
1377	break;
1378	}
1379	else if ( not tlb_flags.x )
1380	{
1381	r_mmu_ietr = MMU_READ_EXEC_VIOLATION;
1382	r_mmu_ibvar = m_ireq.addr;
1383	m_irsp.valid = true;
1384	m_irsp.error = true;
1385	m_irsp.instruction = 0;
1386	break;
1387	}
1388	}
1389	// in case of TLB miss we send an itlb miss request to DCACHE FSM and break
1390	else
1391	{
1392
1393	#ifdef INSTRUMENTATION
1394	m_cpt_itlb_miss++;
1395	#endif
1396	r_icache_fsm = ICACHE_TLB_WAIT;
1397	r_icache_tlb_miss_req = true;
1398	break;
1399	}
1400	} // end if itlb activated
1401
1402	// physical address registration (for next cycle)
1403	r_icache_vci_paddr = paddr;
1404
1405	// We enter this section only in case of TLB hit:
1406	// Finally, we get the instruction depending on cacheability,
1407	// we send the response to processor, and compute next state
1408	if ( cacheable ) // cacheable read
1409	{
1410	if ( (r_icache_vci_paddr.read() & ~PAGE_K_MASK)
1411	!= (paddr & ~PAGE_K_MASK) ) // speculative access KO
1412	{
1413
1414	#ifdef INSTRUMENTATION
1415	m_cpt_icache_spc_miss++;
1416	#endif
1417	// we return an invalid response and stay in IDLE state
1418	// the cache access will cost one extra cycle.
1419	break;
1420	}
1421
1422	if ( not cache_hit ) // cache miss
1423	{
1424
1425	#ifdef INSTRUMENTATION
1426	m_cpt_icache_miss++;
1427	#endif
1428	r_icache_fsm = ICACHE_MISS_VICTIM;
1429	r_icache_miss_req = true;
1430	}
1431	else // cache hit
1432	{
1433
1434	#ifdef INSTRUMENTATION
1435	m_cpt_ins_read++;
1436	#endif
1437	m_irsp.valid = true;
1438	m_irsp.instruction = cache_inst;
1439	}
1440	}
1441	else // non cacheable read
1442	{
1443	r_icache_unc_req = true;
1444	r_icache_fsm = ICACHE_UNC_WAIT;
1445	}
1446	} // end if m_ireq.valid
1447	break;
1448	}
1449	/////////////////////
1450	case ICACHE_TLB_WAIT: // Waiting the itlb update by the DCACHE FSM after a tlb miss
1451	// the itlb is udated by the DCACHE FSM, as well as the
1452	// r_mmu_ietr and r_mmu_ibvar registers in case of error.
1453	// the itlb is not accessed by ICACHE FSM until DCACHE FSM
1454	// reset the r_icache_tlb_miss_req flip-flop
1455	// external coherence request are accepted in this state.
1456	{
1457	// external coherence request
1458	if ( r_tgt_icache_req.read() )
1459	{
1460	r_icache_fsm = ICACHE_CC_CHECK;
1461	r_icache_fsm_save = r_icache_fsm.read();
1462	break;
1463	}
1464
1465	if ( m_ireq.valid ) m_cost_ins_tlb_miss_frz++;
1466
1467	// DCACHE FSM signals response by reseting the request flip-flop
1468	if ( not r_icache_tlb_miss_req.read() )
1469	{
1470	if ( r_icache_tlb_rsp_error.read() ) // error reported : tlb not updated
1471	{
1472	r_icache_tlb_rsp_error = false;
1473	m_irsp.error = true;
1474	m_irsp.valid = true;
1475	r_icache_fsm = ICACHE_IDLE;
1476	}
1477	else // tlb updated : return to IDLE state
1478	{
1479	r_icache_fsm = ICACHE_IDLE;
1480	}
1481	}
1482	break;
1483	}
1484	//////////////////////////
1485	case ICACHE_XTN_TLB_FLUSH: // invalidate in one cycle all non global TLB entries
1486	{
1487	r_itlb.flush();
1488	r_dcache_xtn_req = false;
1489	r_icache_fsm = ICACHE_IDLE;
1490	break;
1491	}
1492	////////////////////////////
1493	case ICACHE_XTN_CACHE_FLUSH: // Invalidate sequencially all cache lines using
1494	// the r_icache_flush_count register as a slot counter.
1495	// We loop in this state until all slots have been visited.
1496	// A cleanup request is generated for each valid line
1497	// and we are blocked until the previous cleanup is completed
1498	{
1499	if ( not r_icache_cleanup_req.read() )
1500	{
1501	size_t way = r_icache_flush_count.read()/m_icache_sets;
1502	size_t set = r_icache_flush_count.read()%m_icache_sets;
1503	paddr_t nline;
1504	bool cleanup_req = r_icache.inval( way,
1505	set,
1506	&nline );
1507	if ( cleanup_req )
1508	{
1509	r_icache_cleanup_req = true;
1510	r_icache_cleanup_line = nline;
1511	}
1512	r_icache_flush_count = r_icache_flush_count.read() + 1;
1513
1514
1515	if ( r_icache_flush_count.read() == (m_icache_sets*m_icache_ways - 1) )
1516	{
1517	r_dcache_xtn_req = false;
1518	r_icache_fsm = ICACHE_IDLE;
1519	}
1520	}
1521
1522	break;
1523	}
1524	//////////////////////////
1525	case ICACHE_XTN_TLB_INVAL: // invalidate one TLB entry selected by the virtual address
1526	// stored in the r_dcache_p0_wdata register
1527	{
1528	r_itlb.inval(r_dcache_p0_wdata.read());
1529	r_dcache_xtn_req = false;
1530	r_icache_fsm = ICACHE_IDLE;
1531	break;
1532	}
1533	///////////////////////////////
1534	case ICACHE_XTN_CACHE_INVAL_VA: // Selective cache line invalidate with virtual address
1535	// requires 3 cycles (in case of hit on itlb and icache).
1536	// In this state, we access TLB to translate virtual address
1537	// stored in the r_dcache_p0_wdata register.
1538	{
1539	paddr_t paddr;
1540	bool hit;
1541
1542	// read physical address in TLB when MMU activated
1543	if ( r_mmu_mode.read() & INS_TLB_MASK ) // itlb activated
1544	{
1545
1546	#ifdef INSTRUMENTATION
1547	m_cpt_itlb_read++;
1548	#endif
1549	hit = r_itlb.translate(r_dcache_p0_wdata.read(),
1550	&paddr);
1551	}
1552	else // itlb not activated
1553	{
1554	paddr = (paddr_t)r_dcache_p0_wdata.read();
1555	hit = true;
1556	}
1557
1558	if ( hit ) // continue the selective inval process
1559	{
1560	r_icache_vci_paddr = paddr;
1561	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA;
1562	}
1563	else // miss : send a request to DCACHE FSM
1564	{
1565
1566	#ifdef INSTRUMENTATION
1567	m_cpt_itlb_miss++;
1568	#endif
1569	r_icache_tlb_miss_req = true;
1570	r_icache_vaddr_save = r_dcache_p0_wdata.read();
1571	r_icache_fsm = ICACHE_TLB_WAIT;
1572	}
1573	break;
1574	}
1575	///////////////////////////////
1576	case ICACHE_XTN_CACHE_INVAL_PA: // selective invalidate cache line with physical address
1577	// require 2 cycles. In this state, we read dcache,
1578	// with address stored in r_icache_vci_paddr register.
1579	{
1580	uint32_t data;
1581	size_t way;
1582	size_t set;
1583	size_t word;
1584	bool hit = r_icache.read(r_icache_vci_paddr.read(),
1585	&data,
1586	&way,
1587	&set,
1588	&word);
1589	if ( hit ) // inval to be done
1590	{
1591	r_icache_miss_way = way;
1592	r_icache_miss_set = set;
1593	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_GO;
1594	}
1595	else // miss : acknowlege the XTN request and return
1596	{
1597	r_dcache_xtn_req = false;
1598	r_icache_fsm = ICACHE_IDLE;
1599	}
1600	break;
1601	}
1602	///////////////////////////////
1603	case ICACHE_XTN_CACHE_INVAL_GO: // In this state, we invalidate the cache line & cleanup.
1604	// We are blocked if the previous cleanup is not completed
1605	{
1606	paddr_t nline;
1607
1608	if ( not r_icache_cleanup_req.read() )
1609	{
1610	bool hit;
1611	hit = r_icache.inval( r_icache_miss_way.read(),
1612	r_icache_miss_set.read(),
1613	&nline );
1614	assert(hit && "XTN_ICACHE_INVAL way/set should still be in icache");
1615
1616	// request cleanup
1617	r_icache_cleanup_req = true;
1618	r_icache_cleanup_line = nline;
1619	// acknowledge the XTN request and return
1620	r_dcache_xtn_req = false;
1621	r_icache_fsm = ICACHE_IDLE;
1622	}
1623	break;
1624	}
1625
1626	////////////////////////
1627	case ICACHE_MISS_VICTIM: // Selects a victim line
1628	// Set the r_icache_cleanup_req flip-flop
1629	// when the selected slot is not empty
1630	{
1631	m_cost_ins_miss_frz++;
1632
1633	size_t index; // unused
1634	bool hit = r_cleanup_buffer.hit( r_icache_vci_paddr.read()>>(uint32_log2(m_icache_words)+2), &index );
1635	if ( not hit and not r_icache_cleanup_req.read() )
1636	{
1637	bool valid;
1638	size_t way;
1639	size_t set;
1640	paddr_t victim;
1641
1642	valid = r_icache.victim_select(r_icache_vci_paddr.read(),
1643	&victim,
1644	&way,
1645	&set);
1646	r_icache_miss_way = way;
1647	r_icache_miss_set = set;
1648
1649	if ( valid )
1650	{
1651	r_icache_cleanup_req = true;
1652	r_icache_cleanup_line = victim;
1653	r_icache_fsm = ICACHE_MISS_INVAL;
1654	}
1655	else
1656	{
1657	r_icache_fsm = ICACHE_MISS_WAIT;
1658	}
1659	}
1660	break;
1661	}
1662	///////////////////////
1663	case ICACHE_MISS_INVAL: // invalidate the victim line
1664	{
1665	paddr_t nline;
1666	bool hit;
1667
1668	hit = r_icache.inval( r_icache_miss_way.read(),
1669	r_icache_miss_set.read(),
1670	&nline ); // unused
1671	assert(hit && "selected way/set line should be in icache");
1672
1673	r_icache_fsm = ICACHE_MISS_WAIT;
1674	break;
1675	}
1676	//////////////////////
1677	case ICACHE_MISS_WAIT: // waiting a response to a miss request from VCI_RSP FSM
1678	{
1679	if ( m_ireq.valid ) m_cost_ins_miss_frz++;
1680
1681	// external coherence request
1682	if ( r_tgt_icache_req.read() )
1683	{
1684	r_icache_fsm = ICACHE_CC_CHECK;
1685	r_icache_fsm_save = r_icache_fsm.read();
1686	break;
1687	}
1688
1689	if ( r_vci_rsp_ins_error.read() ) // bus error
1690	{
1691	r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS;
1692	r_mmu_ibvar = r_icache_vaddr_save.read();
1693	m_irsp.valid = true;
1694	m_irsp.error = true;
1695	r_vci_rsp_ins_error = false;
1696	r_icache_fsm = ICACHE_IDLE;
1697	}
1698	else if ( r_vci_rsp_fifo_icache.rok() ) // response available
1699	{
1700	r_icache_miss_word = 0;
1701	r_icache_fsm = ICACHE_MISS_UPDT;
1702	}
1703	break;
1704	}
1705	//////////////////////
1706	case ICACHE_MISS_UPDT: // update the cache (one word per cycle)
1707	{
1708	if ( m_ireq.valid ) m_cost_ins_miss_frz++;
1709
1710	if ( r_vci_rsp_fifo_icache.rok() ) // response available
1711	{
1712	if ( r_icache_miss_inval ) // Matching coherence request
1713	// We pop the response FIFO, without updating the cache
1714	// We send a cleanup for the missing line at the last word
1715	// Blocked if the previous cleanup is not completed
1716	{
1717	if ( r_icache_miss_word.read() < m_icache_words-1 ) // not the last word
1718	{
1719	vci_rsp_fifo_icache_get = true;
1720	r_icache_miss_word = r_icache_miss_word.read() + 1;
1721	}
1722	else // last word
1723	{
1724	if ( not r_icache_cleanup_req.read() ) // no pending cleanup
1725	{
1726	vci_rsp_fifo_icache_get = true;
1727	r_icache_cleanup_req = true;
1728	r_icache_cleanup_line = r_icache_vci_paddr.read() >> (uint32_log2(m_icache_words<<2));
1729	r_icache_miss_inval = false;
1730	r_icache_fsm = ICACHE_IDLE;
1731	}
1732	}
1733	}
1734	else // No matching coherence request
1735	// We pop the FIFO and update the cache
1736	// We update the directory at the last word
1737	{
1738
1739	#ifdef INSTRUMENTATION
1740	m_cpt_icache_data_write++;
1741	#endif
1742	r_icache.write( r_icache_miss_way.read(),
1743	r_icache_miss_set.read(),
1744	r_icache_miss_word.read(),
1745	r_vci_rsp_fifo_icache.read() );
1746	vci_rsp_fifo_icache_get = true;
1747	r_icache_miss_word = r_icache_miss_word.read() + 1;
1748	if ( r_icache_miss_word.read() == m_icache_words-1 ) // last word
1749	{
1750
1751	#ifdef INSTRUMENTATION
1752	m_cpt_icache_dir_write++;
1753	#endif
1754	r_icache.victim_update_tag( r_icache_vci_paddr.read(),
1755	r_icache_miss_way.read(),
1756	r_icache_miss_set.read() );
1757	r_icache_fsm = ICACHE_IDLE;
1758	}
1759	}
1760	}
1761	break;
1762	}
1763	////////////////////
1764	case ICACHE_UNC_WAIT: // waiting a response to an uncacheable read from VCI_RSP FSM
1765	//
1766	{
1767	// external coherence request
1768	if ( r_tgt_icache_req.read() )
1769	{
1770	r_icache_fsm = ICACHE_CC_CHECK;
1771	r_icache_fsm_save = r_icache_fsm.read();
1772	break;
1773	}
1774
1775	if ( r_vci_rsp_ins_error.read() ) // bus error
1776	{
1777	r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS;
1778	r_mmu_ibvar = m_ireq.addr;
1779	r_vci_rsp_ins_error = false;
1780	m_irsp.valid = true;
1781	m_irsp.error = true;
1782	r_icache_fsm = ICACHE_IDLE;
1783	}
1784	else if (r_vci_rsp_fifo_icache.rok() ) // instruction available
1785	{
1786	vci_rsp_fifo_icache_get = true;
1787	r_icache_fsm = ICACHE_IDLE;
1788	if ( m_ireq.valid and (m_ireq.addr == r_icache_vaddr_save.read()) ) // request not modified
1789	{
1790	m_irsp.valid = true;
1791	m_irsp.instruction = r_vci_rsp_fifo_icache.read();
1792	}
1793	}
1794	break;
1795	}
1796	/////////////////////
1797	case ICACHE_CC_CHECK: // This state is the entry point of a sub-fsm
1798	// handling coherence requests.
1799	// the return state is defined in r_icache_fsm_save.
1800	{
1801	paddr_t paddr = r_tgt_paddr.read();
1802	paddr_t mask = ~((m_icache_words<<2)-1);
1803
1804	if( (r_icache_fsm_save.read() == ICACHE_MISS_WAIT) and
1805	((r_icache_vci_paddr.read() & mask) == (paddr & mask))) // matching a pending miss
1806	{
1807	r_icache_miss_inval = true; // signaling the matching
1808	r_tgt_icache_req = false; // coherence request completed
1809	r_tgt_icache_rsp = r_tgt_update.read(); // response required if update
1810	r_icache_fsm = r_icache_fsm_save.read();
1811	}
1812	else // no match
1813	{
1814
1815	#ifdef INSTRUMENTATION
1816	m_cpt_icache_dir_read++;
1817	#endif
1818	uint32_t inst;
1819	size_t way;
1820	size_t set;
1821	size_t word;
1822	bool hit = r_icache.read(paddr,
1823	&inst,
1824	&way,
1825	&set,
1826	&word);
1827	r_icache_cc_way = way;
1828	r_icache_cc_set = set;
1829
1830	if ( hit and r_tgt_update.read() ) // hit update
1831	{
1832	r_icache_fsm = ICACHE_CC_UPDT;
1833	r_icache_cc_word = r_tgt_word_min.read();
1834	}
1835	else if ( hit and not r_tgt_update.read() ) // hit inval
1836	{
1837	r_icache_fsm = ICACHE_CC_INVAL;
1838	}
1839	else // miss can happen
1840	{
1841	r_tgt_icache_req = false;
1842	r_tgt_icache_rsp = r_tgt_update.read();
1843	r_icache_fsm = r_icache_fsm_save.read();
1844	}
1845	}
1846	break;
1847	}
1848
1849	/////////////////////
1850	case ICACHE_CC_INVAL: // invalidate a cache line
1851	{
1852	paddr_t nline;
1853	bool hit;
1854	hit = r_icache.inval( r_icache_cc_way.read(),
1855	r_icache_cc_set.read(),
1856	&nline );
1857	assert (hit && "ICACHE_CC_INVAL way/set should still be in icache");
1858	r_tgt_icache_req = false;
1859	r_tgt_icache_rsp = true;
1860	r_icache_fsm = r_icache_fsm_save.read();
1861	break;
1862	}
1863	////////////////////
1864	case ICACHE_CC_UPDT: // write one word per cycle (from word_min to word_max)
1865	{
1866	size_t word = r_icache_cc_word.read();
1867	size_t way = r_icache_cc_way.read();
1868	size_t set = r_icache_cc_set.read();
1869
1870	r_icache.write( way,
1871	set,
1872	word,
1873	r_tgt_buf[word],
1874	r_tgt_be[word] );
1875
1876	r_icache_cc_word = word+1;
1877
1878	if ( word == r_tgt_word_max.read() ) // last word
1879	{
1880	r_tgt_icache_req = false;
1881	r_tgt_icache_rsp = true;
1882	r_icache_fsm = r_icache_fsm_save.read();
1883	}
1884	break;
1885	}
1886
1887	} // end switch r_icache_fsm
1888
1889	////////////////////////////////////////////////////////////////////////////////////
1890	// DCACHE FSM
1891	//
1892	// Both the Cacheability Table, and the MMU cacheable bit are used to define
1893	// the cacheability, depending on the MMU mode.
1894	//
1895	// 1/ Coherence requests :
1896	// There is a coherence request when the tgt_dcache_req flip-flop is set,
1897	// requesting a line invalidation or a line update.
1898	// Coherence requests are taken into account in IDLE, UNC_WAIT, MISS_WAIT states.
1899	// The actions associated to the pre-empted state are not executed, the DCACHE FSM
1900	// goes to the CC_CHECK state to execute the requested action, and returns to the
1901	// pre-empted state.
1902	//
1903	// 2/ TLB miss
1904	// The page tables can be cacheable.
1905	// In case of miss in itlb or dtlb, the tlb miss is handled by a dedicated
1906	// sub-fsm (DCACHE_TLB_MISS state), that handle possible miss in DCACHE,
1907	// this sub-fsm implement the table-walk...
1908	//
1909	// 3/ processor requests :
1910	// Processor READ, WRITE, LL or SC requests are taken in IDLE state only.
1911	// The IDLE state implements a three stages pipe-line to handle write bursts:
1912	// - The physical address is computed by dtlb in stage P0.
1913	// - The registration in wbuf and the dcache hit are computed in stage P1.
1914	// - The dcache update is done in stage P2.
1915	// WRITE or SC requests can require a PTE Dirty bit update (in memory),
1916	// that is done (before handling the processor request) by a dedicated sub-fsm
1917	// (DCACHE_DIRTY_TLB_SET state).
1918	// If a PTE is modified, both the itlb and dtlb are selectively, but sequencially
1919	// cleared by a dedicated sub_fsm (DCACHE_INVAL_TLB_SCAN state).
1920	// If there is no write in the pipe, dcache and dtlb are accessed in parallel,
1921	// (virtual address for itlb, and speculative physical address computed during
1922	// previous cycle for dcache) in order to return the data in one cycle for a READ
1923	// request. We just pay an extra cycle when the speculative access is failing.
1924	//
1925	// 4/ Atomic instructions LL/SC
1926	// The LL/SC address can be cacheable or non cacheable.
1927	// The reservation registers (r_dcache_ll_valid, r_dcache_ll_vaddr and
1928	// r_dcache_ll_data are stored in the L1 cache controller, and not in the
1929	// memory controller.
1930	// - LL requests from the processor are transmitted as standard VCI
1931	// READ transactions (one word / one line, depending on the cacheability).
1932	// - SC requests from the processor are systematically transmitted to the
1933	// memory cache as Compare&swap requests (both the data value stored in the
1934	// r_dcache_ll_data register and the new value).
1935	// The cache is not updated, as this is done in case of success by the
1936	// coherence transaction.
1937	//
1938	// 5/ Non cacheable access:
1939	// This component implement a strong order between non cacheable access
1940	// (read or write) : A new non cacheable VCI transaction starts only when
1941	// the previous non cacheable transaction is completed. Both cacheable and
1942	// non cacheable transactions use the write buffer, but the DCACHE FSM registers
1943	// a non cacheable write transaction posted in the write buffer by setting the
1944	// r_dcache_pending_unc_write flip_flop. All other non cacheable requests
1945	// are stalled until this flip-flop is reset by the VCI_RSP_FSM (when the
1946	// pending non cacheable write transaction completes).
1947	//
1948	// 6/ Error handling:
1949	// When the MMU is not activated, Read Bus Errors are synchronous events,
1950	// but Write Bus Errors are asynchronous events (processor is not frozen).
1951	// - If a Read Bus Error is detected, the VCI_RSP FSM sets the
1952	// r_vci_rsp_data_error flip-flop, without writing any data in the
1953	// r_vci_rsp_fifo_dcache FIFO, and the synchronous error is signaled
1954	// by the DCACHE FSM.
1955	// - If a Write Bus Error is detected, the VCI_RSP FSM signals
1956	// the asynchronous error using the setWriteBerr() method.
1957	// When the MMU is activated bus error are rare events, as the MMU
1958	// checks the physical address before the VCI transaction starts.
1959	////////////////////////////////////////////////////////////////////////////////////////
1960
1961	// default value for m_drsp
1962	m_drsp.valid = false;
1963	m_drsp.error = false;
1964	m_drsp.rdata = 0;
1965
1966	switch ( r_dcache_fsm.read() )
1967	{
1968	case DCACHE_IDLE: // There is 8 conditions to exit the IDLE state :
1969	// 1) Dirty bit update (processor) => DCACHE_DIRTY_GET_PTE
1970	// 2) Coherence request (TGT FSM) => DCACHE_CC_CHECK
1971	// 3) ITLB miss request (ICACHE FSM) => DCACHE_TLB_MISS
1972	// 4) XTN request (processor) => DCACHE_XTN_*
1973	// 5) DTLB miss (processor) => DCACHE_TLB_MISS
1974	// 6) Cacheable read miss (processor) => DCACHE_MISS_VICTIM
1975	// 7) Uncacheable read (processor) => DCACHE_UNC_WAIT
1976	// 8) SC access (processor) => DCACHE_SC_WAIT
1977	//
1978	// The dtlb is unconditionally accessed to translate the
1979	// virtual adress from processor.
1980	//
1981	// There is 4 configurations to access the cache,
1982	// depending on the pipe-line state, defined
1983	// by the r_dcache_p0_valid (V0) flip-flop : P1 stage activated
1984	// and r_dcache_p1_valid (V1) flip-flop : P2 stage activated
1985	// V0 / V1 / Data / Directory / comment
1986	// 0 / 0 / read(A0) / read(A0) / read speculative access
1987	// 0 / 1 / write(A2) / nop / read request delayed
1988	// 1 / 0 / nop / read(A1) / read request delayed
1989	// 1 / 1 / write(A2) / read(A1) / read request delayed
1990	{
1991	bool tlb_inval_required = false;
1992	bool write_pipe_frozen = false;
1993
1994	////////////////////////////////////////////////////////////////////////////////
1995	// Handling P2 pipe-line stage
1996	// Inputs are r_dcache_p1_* registers.
1997	// If r_dcache_p1_valid is true, we update the local copy in dcache.
1998	// If the modified cache line has copies in TLBs, we launch a TLB invalidate
1999	// operation, going to DCACHE_INVAL_TLB_SCAN state.
2000
2001	if ( r_dcache_p1_valid.read() ) // P2 stage activated
2002	{
2003	size_t way = r_dcache_p1_cache_way.read();
2004	size_t set = r_dcache_p1_cache_set.read();
2005	size_t word = r_dcache_p1_cache_word.read();
2006	uint32_t wdata = r_dcache_p1_wdata.read();
2007	vci_be_t be = r_dcache_p1_be.read();
2008
2009	r_dcache.write( way,
2010	set,
2011	word,
2012	wdata,
2013	be );
2014	#ifdef INSTRUMENTATION
2015	m_cpt_dcache_data_write++;
2016	#endif
2017	// cache update after a WRITE hit can require itlb & dtlb inval or flush
2018	if ( r_dcache_in_tlb[way*m_dcache_sets+set] )
2019	{
2020	tlb_inval_required = true;
2021	r_dcache_tlb_inval_count = 0;
2022	r_dcache_tlb_inval_line = r_dcache_p1_paddr.read()>>
2023	(uint32_log2(m_dcache_words<<2));
2024	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
2025	}
2026	else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] )
2027	{
2028	r_itlb.reset();
2029	r_dtlb.reset();
2030	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
2031	}
2032
2033	#if DEBUG_DCACHE
2034	if ( m_debug_dcache_fsm )
2035	{
2036	std::cout << " <PROC.DCACHE_IDLE> Cache update in P2 stage" << std::dec
2037	<< " / WAY = " << way
2038	<< " / SET = " << set
2039	<< " / WORD = " << word << std::hex
2040	<< " / DATA = " << wdata
2041	<< " / BE = " << be << std::endl;
2042	}
2043	#endif
2044	} // end P2 stage
2045
2046	///////////////////////////////////////////////////////////////////////////
2047	// Handling P1 pipe-line stage
2048	// Inputs are r_dcache_p0_* registers.
2049	// We must write into wbuf and test the hit in dcache.
2050	// If the write request is non cacheable, and there is a pending
2051	// non cacheable write, or if the write buffer is full, the P0 and P1 stages
2052	// are frozen until the write request registration is possible,
2053	// while the P2 stage is not frozen.
2054	// The r_dcache_p1_valid bit must be computed at all cycles, and
2055	// the P2 stage must be activated if there is a local copy in dcache.
2056
2057	if ( r_dcache_p0_valid.read() ) // P1 stage activated
2058	{
2059	// frozen if write not cacheable, and previous non cacheable write registered
2060	if ( not r_dcache_p0_cacheable.read() and r_dcache_pending_unc_write.read() )
2061	{
2062	r_dcache_p1_valid = false;
2063	write_pipe_frozen = true;
2064	}
2065	else // try a registration into write buffer
2066	{
2067
2068	bool wok = r_wbuf.write( r_dcache_p0_paddr.read(),
2069	r_dcache_p0_be.read(),
2070	r_dcache_p0_wdata.read(),
2071	r_dcache_p0_cacheable.read() );
2072	#ifdef INSTRUMENTATION
2073	m_cpt_wbuf_write++;
2074	#endif
2075	if ( not wok ) // frozen if write buffer full
2076	{
2077	r_dcache_p1_valid = false;
2078	write_pipe_frozen = true;
2079	}
2080	else // update the write_buffer state extension
2081	{
2082	r_dcache_pending_unc_write = not r_dcache_p0_cacheable.read();
2083
2084	// read directory to check local copy
2085	size_t cache_way;
2086	size_t cache_set;
2087	size_t cache_word;
2088	bool local_copy;
2089	if ( r_mmu_mode.read() & DATA_CACHE_MASK) // cache activated
2090	{
2091	local_copy = r_dcache.hit( r_dcache_p0_paddr.read(),
2092	&cache_way,
2093	&cache_set,
2094	&cache_word );
2095	#ifdef INSTRUMENTATION
2096	m_cpt_dcache_dir_read++;
2097	#endif
2098	}
2099	else
2100	{
2101	local_copy = false;
2102	}
2103
2104	// store values for P2 pipe stage
2105	if ( local_copy )
2106	{
2107	r_dcache_p1_valid = true;
2108	r_dcache_p1_wdata = r_dcache_p0_wdata.read();
2109	r_dcache_p1_be = r_dcache_p0_be.read();
2110	r_dcache_p1_paddr = r_dcache_p0_paddr.read();
2111	r_dcache_p1_cache_way = cache_way;
2112	r_dcache_p1_cache_set = cache_set;
2113	r_dcache_p1_cache_word = cache_word;
2114	}
2115	else
2116	{
2117	r_dcache_p1_valid = false;
2118	}
2119	}
2120	}
2121	}
2122	else // P1 stage not activated
2123	{
2124	r_dcache_p1_valid = false;
2125	} // end P1 stage
2126
2127	/////////////////////////////////////////////////////////////////////////////////
2128	// handling P0 pipe-line stage
2129	// This stage is controlling r_dcache_fsm and r_dcache_p0_* registers.
2130	// The r_dcache_p0_valid flip-flop is only set in case of a WRITE request.
2131	// - the TLB invalidate requests have the highest priority,
2132	// - then the external coherence requests,
2133	// - then the itlb miss requests,
2134	// - and finally the processor requests.
2135	// If dtlb is activated, there is an unconditionnal access to dtlb,
2136	// for address translation.
2137	// 1) A processor WRITE request is blocked if the Dirty bit mus be set, or if
2138	// dtlb miss. If dtlb is OK, It enters the three stage pipe-line (fully
2139	// handled by the IDLE state), and the processor request is acknowledged.
2140	// 2) A processor READ or LL request generate a simultaneouss access to
2141	// both dcache data and dcache directoty, using speculative PPN, but
2142	// is delayed if the write pipe-line is not empty.
2143	// In case of miss, we wait the VCI response in DCACHE_UNC_WAIT or
2144	// DCACHE_MISS_WAIT states.
2145	// 3) A processor SC request is delayed until the write pipe-line is empty.
2146	// A VCI SC transaction is launched, and we wait the VCI response in
2147	// DCACHE_SC_WAIT state. It can be completed by a "long write" if the
2148	// PTE dirty bit must be updated in dtlb, dcache, and RAM.
2149	// The data is not modified in dcache, as it will be done by the
2150	// coherence transaction.
2151
2152	// TLB inval required after a write hit
2153	if ( tlb_inval_required )
2154	{
2155	r_dcache_fsm_scan_save = r_dcache_fsm.read();
2156	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
2157	r_dcache_p0_valid = false;
2158	}
2159	// external coherence request
2160	else if ( r_tgt_dcache_req.read() )
2161	{
2162	r_dcache_fsm_cc_save = r_dcache_fsm.read();
2163	r_dcache_fsm = DCACHE_CC_CHECK;
2164	r_dcache_p0_valid = false;
2165	}
2166
2167	// itlb miss request
2168	else if ( r_icache_tlb_miss_req.read() )
2169	{
2170	r_dcache_tlb_ins = true;
2171	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
2172	r_dcache_fsm = DCACHE_TLB_MISS;
2173	r_dcache_p0_valid = false;
2174	}
2175
2176	// processor request
2177	else if ( m_dreq.valid and not write_pipe_frozen )
2178	{
2179	// dcache access using speculative PPN only if pipe-line empty
2180	paddr_t cache_paddr;
2181	size_t cache_way;
2182	size_t cache_set;
2183	size_t cache_word;
2184	uint32_t cache_rdata;
2185	bool cache_hit;
2186
2187	if ( (r_mmu_mode.read() & DATA_CACHE_MASK) and // cache activated
2188	not r_dcache_p0_valid.read() and
2189	not r_dcache_p1_valid.read() ) // pipe-line empty
2190	{
2191	cache_paddr = (r_dcache_p0_paddr.read() & ~PAGE_K_MASK) \|
2192	((paddr_t)m_dreq.addr & PAGE_K_MASK);
2193
2194	cache_hit = r_dcache.read( cache_paddr,
2195	&cache_rdata,
2196	&cache_way,
2197	&cache_set,
2198	&cache_word );
2199	#ifdef INSTRUMENTATION
2200	m_cpt_dcache_dir_read++;
2201	m_cpt_dcache_data_read++;
2202	#endif
2203	}
2204	else
2205	{
2206	cache_hit = false;
2207	} // end dcache access
2208
2209	// systematic dtlb access using virtual address
2210	paddr_t tlb_paddr;
2211	pte_info_t tlb_flags;
2212	size_t tlb_way;
2213	size_t tlb_set;
2214	paddr_t tlb_nline;
2215	bool tlb_hit;
2216
2217	if ( r_mmu_mode.read() & DATA_TLB_MASK ) // DTLB activated
2218	{
2219	tlb_hit = r_dtlb.translate( m_dreq.addr,
2220	&tlb_paddr,
2221	&tlb_flags,
2222	&tlb_nline,
2223	&tlb_way,
2224	&tlb_set );
2225	#ifdef INSTRUMENTATION
2226	m_cpt_dtlb_read++;
2227	#endif
2228	}
2229	else
2230	{
2231	tlb_hit = false;
2232	} // end dtlb access
2233
2234	// register the processor request
2235	r_dcache_p0_vaddr = m_dreq.addr;
2236	r_dcache_p0_be = m_dreq.be;
2237	r_dcache_p0_wdata = m_dreq.wdata;
2238
2239	// Handling READ XTN requests from processor
2240	// They are executed in this DCACHE_IDLE state.
2241	// The processor must not be in user mode
2242	if (m_dreq.type == iss_t::XTN_READ)
2243	{
2244	int xtn_opcode = (int)m_dreq.addr/4;
2245
2246	// checking processor mode:
2247	if (m_dreq.mode == iss_t::MODE_USER)
2248	{
2249	r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION;
2250	r_mmu_dbvar = m_dreq.addr;
2251	m_drsp.valid = true;
2252	m_drsp.error = true;
2253	r_dcache_fsm = DCACHE_IDLE;
2254	}
2255	else
2256	{
2257	switch( xtn_opcode )
2258	{
2259	case iss_t::XTN_INS_ERROR_TYPE:
2260	m_drsp.rdata = r_mmu_ietr.read();
2261	m_drsp.valid = true;
2262	break;
2263
2264	case iss_t::XTN_DATA_ERROR_TYPE:
2265	m_drsp.rdata = r_mmu_detr.read();
2266	m_drsp.valid = true;
2267	break;
2268
2269	case iss_t::XTN_INS_BAD_VADDR:
2270	m_drsp.rdata = r_mmu_ibvar.read();
2271	m_drsp.valid = true;
2272	break;
2273
2274	case iss_t::XTN_DATA_BAD_VADDR:
2275	m_drsp.rdata = r_mmu_dbvar.read();
2276	m_drsp.valid = true;
2277	break;
2278
2279	case iss_t::XTN_PTPR:
2280	m_drsp.rdata = r_mmu_ptpr.read();
2281	m_drsp.valid = true;
2282	break;
2283
2284	case iss_t::XTN_TLB_MODE:
2285	m_drsp.rdata = r_mmu_mode.read();
2286	m_drsp.valid = true;
2287	break;
2288
2289	case iss_t::XTN_MMU_PARAMS:
2290	m_drsp.rdata = r_mmu_params;
2291	m_drsp.valid = true;
2292	break;
2293
2294	case iss_t::XTN_MMU_RELEASE:
2295	m_drsp.rdata = r_mmu_release;
2296	m_drsp.valid = true;
2297	break;
2298
2299	case iss_t::XTN_MMU_WORD_LO:
2300	m_drsp.rdata = r_mmu_word_lo.read();
2301	m_drsp.valid = true;
2302	break;
2303
2304	case iss_t::XTN_MMU_WORD_HI:
2305	m_drsp.rdata = r_mmu_word_hi.read();
2306	m_drsp.valid = true;
2307	break;
2308
2309	default:
2310	r_mmu_detr = MMU_READ_UNDEFINED_XTN;
2311	r_mmu_dbvar = m_dreq.addr;
2312	m_drsp.valid = true;
2313	m_drsp.error = true;
2314	break;
2315	} // end switch xtn_opcode
2316	} // end else
2317	r_dcache_p0_valid = false;
2318	} // end if XTN_READ
2319
2320	// Handling WRITE XTN requests from processor.
2321	// They are not executed in this DCACHE_IDLE state,
2322	// if they require access to the caches or the TLBs
2323	// that are already accessed for speculative read.
2324	// Caches can be invalidated or flushed in user mode,
2325	// and the sync instruction can be executed in user mode
2326	else if (m_dreq.type == iss_t::XTN_WRITE)
2327	{
2328	int xtn_opcode = (int)m_dreq.addr/4;
2329	r_dcache_xtn_opcode = xtn_opcode;
2330
2331	// checking processor mode:
2332	if ( (m_dreq.mode == iss_t::MODE_USER) &&
2333	(xtn_opcode != iss_t:: XTN_SYNC) &&
2334	(xtn_opcode != iss_t::XTN_DCACHE_INVAL) &&
2335	(xtn_opcode != iss_t::XTN_DCACHE_FLUSH) &&
2336	(xtn_opcode != iss_t::XTN_ICACHE_INVAL) &&
2337	(xtn_opcode != iss_t::XTN_ICACHE_FLUSH) )
2338	{
2339	r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION;
2340	r_mmu_dbvar = m_dreq.addr;
2341	m_drsp.valid = true;
2342	m_drsp.error = true;
2343	r_dcache_fsm = DCACHE_IDLE;
2344	}
2345	else
2346	{
2347	switch( xtn_opcode )
2348	{
2349	case iss_t::XTN_PTPR: // itlb & dtlb must be flushed
2350	r_mmu_ptpr = m_dreq.wdata;
2351	r_dcache_xtn_req = true;
2352	r_dcache_fsm = DCACHE_XTN_SWITCH;
2353	break;
2354
2355	case iss_t::XTN_TLB_MODE: // no cache or tlb access
2356	r_mmu_mode = m_dreq.wdata;
2357	m_drsp.valid = true;
2358	r_dcache_fsm = DCACHE_IDLE;
2359	break;
2360
2361	case iss_t::XTN_DTLB_INVAL: // dtlb access
2362	r_dcache_fsm = DCACHE_XTN_DT_INVAL;
2363	break;
2364
2365	case iss_t::XTN_ITLB_INVAL: // itlb access
2366	r_dcache_xtn_req = true;
2367	r_dcache_fsm = DCACHE_XTN_IT_INVAL;
2368	break;
2369
2370	case iss_t::XTN_DCACHE_INVAL: // dcache, dtlb & itlb access
2371	r_dcache_fsm = DCACHE_XTN_DC_INVAL_VA;
2372	break;
2373
2374	case iss_t::XTN_MMU_DCACHE_PA_INV: // dcache, dtlb & itlb access
2375	r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA;
2376	if (sizeof(paddr_t) <= 32) {
2377	assert(r_mmu_word_hi.read() == 0 &&
2378	"high bits should be 0 for 32bit paddr");
2379	r_dcache_p0_paddr =
2380	(paddr_t)r_mmu_word_lo.read();
2381	} else {
2382	r_dcache_p0_paddr =
2383	(paddr_t)r_mmu_word_hi.read() << 32 \|
2384	(paddr_t)r_mmu_word_lo.read();
2385	}
2386	break;
2387
2388	case iss_t::XTN_DCACHE_FLUSH: // itlb and dtlb must be reset
2389	r_dcache_flush_count = 0;
2390	r_dcache_fsm = DCACHE_XTN_DC_FLUSH;
2391	break;
2392
2393	case iss_t::XTN_ICACHE_INVAL: // icache and itlb access
2394	r_dcache_xtn_req = true;
2395	r_dcache_fsm = DCACHE_XTN_IC_INVAL_VA;
2396	break;
2397
2398	case iss_t::XTN_MMU_ICACHE_PA_INV: // icache access
2399	r_dcache_xtn_req = true;
2400	r_dcache_fsm = DCACHE_XTN_IC_INVAL_PA;
2401	break;
2402
2403	case iss_t::XTN_ICACHE_FLUSH: // icache access
2404	r_dcache_xtn_req = true;
2405	r_dcache_fsm = DCACHE_XTN_IC_FLUSH;
2406	break;
2407
2408	case iss_t::XTN_SYNC: // wait until write buffer empty
2409	r_dcache_fsm = DCACHE_XTN_SYNC;
2410	break;
2411
2412	case iss_t::XTN_MMU_WORD_LO: // no cache or tlb access
2413	r_mmu_word_lo = m_dreq.wdata;
2414	m_drsp.valid = true;
2415	r_dcache_fsm = DCACHE_IDLE;
2416	break;
2417
2418	case iss_t::XTN_MMU_WORD_HI: // no cache or tlb access
2419	r_mmu_word_hi = m_dreq.wdata;
2420	m_drsp.valid = true;
2421	r_dcache_fsm = DCACHE_IDLE;
2422	break;
2423
2424	case iss_t::XTN_ICACHE_PREFETCH: // not implemented : no action
2425	case iss_t::XTN_DCACHE_PREFETCH: // not implemented : no action
2426	m_drsp.valid = true;
2427	r_dcache_fsm = DCACHE_IDLE;
2428	break;
2429
2430	default:
2431	r_mmu_detr = MMU_WRITE_UNDEFINED_XTN;
2432	r_mmu_dbvar = m_dreq.addr;
2433	m_drsp.valid = true;
2434	m_drsp.error = true;
2435	r_dcache_fsm = DCACHE_IDLE;
2436	break;
2437	} // end switch xtn_opcode
2438	} // end else
2439	r_dcache_p0_valid = false;
2440	} // end if XTN_WRITE
2441
2442	// Handling read/write/ll/sc processor requests.
2443	// The dtlb and dcache can be activated or not.
2444	// We compute the physical address, the cacheability, and check processor request.
2445	// - If DTLB not activated : cacheability is defined by the segment table,
2446	// the physical address is equal to the virtual address (identity mapping)
2447	// - If DTLB activated : cacheability is defined by the C bit in the PTE,
2448	// the physical address is obtained from the TLB, and the U & W bits
2449	// of the PTE are checked.
2450	// The processor request is decoded only if the TLB is not activated or if
2451	// the virtual address hits in tLB and access rights are OK.
2452	// We call the TLB_MISS sub-fsm in case of dtlb miss.
2453	else
2454	{
2455	bool valid_req = false;
2456	bool cacheable = false;
2457	paddr_t paddr = 0;
2458
2459	if ( not (r_mmu_mode.read() & DATA_TLB_MASK) ) // dtlb not activated
2460	{
2461	valid_req = true;
2462
2463	// cacheability
2464	if ( not (r_mmu_mode.read() & DATA_CACHE_MASK) ) cacheable = false;
2465	else cacheable = m_cacheability_table[m_dreq.addr];
2466
2467	// physical address
2468	paddr = (paddr_t)m_dreq.addr;
2469	}
2470	else // dtlb activated
2471	{
2472	if ( tlb_hit ) // tlb hit
2473	{
2474	// cacheability
2475	if ( not (r_mmu_mode.read() & DATA_CACHE_MASK) ) cacheable = false;
2476	else cacheable = tlb_flags.c;
2477
2478	// access rights checking
2479	if ( not tlb_flags.u and (m_dreq.mode == iss_t::MODE_USER))
2480	{
2481	if ( (m_dreq.type == iss_t::DATA_READ) or (m_dreq.type == iss_t::DATA_LL) )
2482	r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION;
2483	else
2484	r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION;
2485
2486	r_mmu_dbvar = m_dreq.addr;
2487	m_drsp.valid = true;
2488	m_drsp.error = true;
2489	m_drsp.rdata = 0;
2490	#if DEBUG_DCACHE
2491	if ( m_debug_dcache_fsm )
2492	{
2493	std::cout << " <PROC.DCACHE_IDLE> HIT in dtlb, but privilege violation" << std::endl;
2494	}
2495	#endif
2496	}
2497	else if ( not tlb_flags.w and
2498	((m_dreq.type == iss_t::DATA_WRITE) or
2499	(m_dreq.type == iss_t::DATA_SC)) )
2500	{
2501	r_mmu_detr = MMU_WRITE_ACCES_VIOLATION;
2502	r_mmu_dbvar = m_dreq.addr;
2503	m_drsp.valid = true;
2504	m_drsp.error = true;
2505	m_drsp.rdata = 0;
2506	#if DEBUG_DCACHE
2507	if ( m_debug_dcache_fsm )
2508	{
2509	std::cout << " <PROC.DCACHE_IDLE> HIT in dtlb, but writable violation" << std::endl;
2510	}
2511	#endif
2512	}
2513	else
2514	{
2515	valid_req = true;
2516	}
2517
2518	// physical address
2519	paddr = tlb_paddr;
2520	}
2521	else // tlb miss
2522	{
2523	r_dcache_tlb_vaddr = m_dreq.addr;
2524	r_dcache_tlb_ins = false;
2525	r_dcache_fsm = DCACHE_TLB_MISS;
2526	}
2527	} // end DTLB activated
2528
2529	if ( valid_req ) // processor request is valid after TLB check
2530	{
2531	// physical address and cacheability registration
2532	r_dcache_p0_paddr = paddr;
2533	r_dcache_p0_cacheable = cacheable;
2534
2535	// READ or LL request
2536	// The read requests are taken only if the write pipe-line is empty.
2537	// If dcache hit, dtlb hit, and speculative PPN OK, data in one cycle.
2538	// If speculative access is KO we just pay one extra cycle.
2539	// If dcache miss, we go to DCACHE_MISS_VICTIM state.
2540	// If uncacheable, we go to DCACHE_UNC_WAIT state.
2541	// In case of LL, the LL registration is done when the data is returned:
2542	// in DCACHE_IDLE if cacheable / in DCACHE_UNC_WAIT if uncacheable
2543	if ( ((m_dreq.type == iss_t::DATA_READ) or (m_dreq.type == iss_t::DATA_LL))
2544	and not r_dcache_p0_valid.read() and not r_dcache_p1_valid.read() )
2545	{
2546	if ( cacheable ) // cacheable read
2547	{
2548	// if the speculative access is illegal, we pay an extra cycle
2549	if ( (r_dcache_p0_paddr.read() & ~PAGE_K_MASK)
2550	!= (paddr & ~PAGE_K_MASK))
2551	{
2552	#ifdef INSTRUMENTATION
2553	m_cpt_dcache_spec_miss++;
2554	#endif
2555	#if DEBUG_DCACHE
2556	if ( m_debug_dcache_fsm )
2557	{
2558	std::cout << " <PROC.DCACHE_IDLE> Speculative access miss" << std::endl;
2559	}
2560	#endif
2561	}
2562	// if cache miss, try to get the missing line
2563	else if ( not cache_hit )
2564	{
2565	#ifdef INSTRUMENTATION
2566	m_cpt_dcache_miss++;
2567	#endif
2568	r_dcache_vci_paddr = paddr;
2569	r_dcache_vci_miss_req = true;
2570	r_dcache_miss_type = PROC_MISS;
2571	r_dcache_fsm = DCACHE_MISS_VICTIM;
2572	}
2573	// if cache hit return the data
2574	else
2575	{
2576	#ifdef INSTRUMENTATION
2577	m_cpt_data_read++;
2578	#endif
2579	m_drsp.valid = true;
2580	m_drsp.rdata = cache_rdata;
2581
2582	// makes reservation in case of LL
2583	if ( m_dreq.type == iss_t::DATA_LL )
2584	{
2585	r_dcache_ll_valid = true;
2586	r_dcache_ll_vaddr = m_dreq.addr;
2587	r_dcache_ll_data = cache_rdata;
2588	}
2589	#if DEBUG_DCACHE
2590	if ( m_debug_dcache_fsm )
2591	{
2592	std::cout << " <PROC.DCACHE_IDLE> HIT in dcache" << std::endl;
2593	}
2594	#endif
2595	}
2596	}
2597	else // uncacheable read
2598	{
2599	r_dcache_vci_paddr = paddr;
2600	r_dcache_vci_unc_be = m_dreq.be;
2601	r_dcache_vci_unc_req = true;
2602	r_dcache_fsm = DCACHE_UNC_WAIT;
2603	}
2604
2605	r_dcache_p0_valid = false;
2606	} // end READ or LL
2607
2608	// WRITE request:
2609	// If the TLB is activated and the PTE Dirty bit is not set, we stall
2610	// the processor and set the Dirty bit before handling the write request.
2611	// If we don't need to set the Dirty bit, we can acknowledge
2612	// the processor request, as the write arguments (including the
2613	// physical address) are registered in r_dcache_p0 registers:
2614	// We simply activate the P1 pipeline stage.
2615	else if ( m_dreq.type == iss_t::DATA_WRITE )
2616	{
2617	if ( (r_mmu_mode.read() & DATA_TLB_MASK )
2618	and not tlb_flags.d ) // Dirty bit must be set
2619	{
2620	// The PTE physical address is obtained from the nline value (dtlb),
2621	// and the word index (proper bits of the virtual address)
2622	if ( tlb_flags.b ) // PTE1
2623	{
2624	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2625	(paddr_t)((m_dreq.addr>>19) & 0x3c);
2626	}
2627	else // PTE2
2628	{
2629	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2630	(paddr_t)((m_dreq.addr>>9) & 0x38);
2631	}
2632	r_dcache_fsm = DCACHE_DIRTY_GET_PTE;
2633	r_dcache_p0_valid = false;
2634	}
2635	else // Write request accepted
2636	{
2637	#ifdef INSTRUMENTATION
2638	m_cpt_data_write++;
2639	#endif
2640	m_drsp.valid = true;
2641	m_drsp.rdata = 0;
2642	r_dcache_p0_valid = true;
2643	}
2644	} // end WRITE
2645
2646	// SC request:
2647	// The SC requests are taken only if the write pipe-line is empty.
2648	// - if there is no valid registered LL, we just return rdata = 1
2649	// (atomic access failed) and the SC transaction is completed.
2650	// - if a valid LL reservation (with the same address) is registered,
2651	// we test if a DIRTY bit update is required.
2652	// If the TLB is activated and the PTE Dirty bit is not set, we stall
2653	// the processor and set the Dirty bit before handling the write request.
2654	// If we don't need to set the Dirty bit, we request a SC transaction
2655	// to CMD FSM and go to DCACHE_SC_WAIT state, that will return
2656	// the response to the processor.
2657	// We don't check a possible write hit in dcache, as the cache update
2658	// is done by the coherence transaction induced by the SC...
2659	else if ( ( m_dreq.type == iss_t::DATA_SC )
2660	and not r_dcache_p0_valid.read() and not r_dcache_p1_valid.read() )
2661	{
2662	if ( (r_dcache_ll_vaddr.read() != m_dreq.addr)
2663	or not r_dcache_ll_valid.read() ) // no valid registered LL
2664	{
2665	#ifdef INSTRUMENTATION
2666	m_cpt_data_sc++;
2667	#endif
2668	m_drsp.valid = true;
2669	m_drsp.rdata = 1;
2670	r_dcache_ll_valid = false;
2671	}
2672	else // valid registered LL
2673	{
2674	if ( (r_mmu_mode.read() & DATA_TLB_MASK )
2675	and not tlb_flags.d ) // Dirty bit must be set
2676	{
2677	// The PTE physical address is obtained from the nline value (dtlb),
2678	// and the word index (virtual address)
2679	if ( tlb_flags.b ) // PTE1
2680	{
2681	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2682	(paddr_t)((m_dreq.addr>>19) & 0x3c);
2683	}
2684	else // PTE2
2685	{
2686	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2687	(paddr_t)((m_dreq.addr>>9) & 0x38);
2688	}
2689	r_dcache_fsm = DCACHE_DIRTY_GET_PTE;
2690	}
2691	else // SC request accepted
2692	{
2693	#ifdef INSTRUMENTATION
2694	m_cpt_data_sc++;
2695	#endif
2696
2697	r_dcache_vci_paddr = paddr;
2698	r_dcache_vci_sc_req = true;
2699	r_dcache_vci_sc_old = r_dcache_ll_data.read();
2700	r_dcache_vci_sc_new = m_dreq.wdata;
2701	r_dcache_ll_valid = false;
2702	r_dcache_fsm = DCACHE_SC_WAIT;
2703	}
2704	}
2705	r_dcache_p0_valid = false;
2706	} // end SC
2707	else
2708	{
2709	r_dcache_p0_valid = false;
2710	}
2711	} // end valid_req
2712	else
2713	{
2714	r_dcache_p0_valid = false;
2715	}
2716	} // end if read/write/ll/sc request
2717	} // end dreq.valid
2718	else
2719	{
2720	r_dcache_p0_valid = false;
2721	} // end P0 pipe stage
2722	break;
2723	}
2724	/////////////////////
2725	case DCACHE_TLB_MISS: // This is the entry point for the sub-fsm handling all tlb miss.
2726	// Input arguments are:
2727	// - r_dcache_tlb_vaddr
2728	// - r_dcache_tlb_ins (true when itlb miss)
2729	// The sub-fsm access the dcache to find the missing TLB entry,
2730	// and activates the cache miss procedure in case of miss.
2731	// It bypass the first level page table access if possible.
2732	// It uses atomic access to update the R/L access bits
2733	// in the page table if required.
2734	// It directly updates the itlb or dtlb, and writes into the
2735	// r_mmu_ins_* or r_mmu_data* error reporting registers.
2736	{
2737	uint32_t ptba = 0;
2738	bool bypass;
2739	paddr_t pte_paddr;
2740
2741	// evaluate bypass in order to skip first level page table access
2742	if ( r_dcache_tlb_ins.read() ) // itlb miss
2743	{
2744	bypass = r_itlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba);
2745	}
2746	else // dtlb miss
2747	{
2748	bypass = r_dtlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba);
2749	}
2750
2751	if ( not bypass ) // Try to read PTE1/PTD1 in dcache
2752	{
2753	pte_paddr = (paddr_t)r_mmu_ptpr.read() << (INDEX1_NBITS+2) \|
2754	(paddr_t)((r_dcache_tlb_vaddr.read() >> PAGE_M_NBITS) << 2);
2755	r_dcache_tlb_paddr = pte_paddr;
2756	r_dcache_fsm = DCACHE_TLB_PTE1_GET;
2757	}
2758	else // Try to read PTE2 in dcache
2759	{
2760	pte_paddr = (paddr_t)ptba << PAGE_K_NBITS \|
2761	(paddr_t)(r_dcache_tlb_vaddr.read()&PTD_ID2_MASK)>>(PAGE_K_NBITS-3);
2762	r_dcache_tlb_paddr = pte_paddr;
2763	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
2764	}
2765
2766	#if DEBUG_DCACHE
2767	if ( m_debug_dcache_fsm )
2768	{
2769	if ( r_dcache_tlb_ins.read() )
2770	{
2771	std::cout << " <PROC.DCACHE_TLB_MISS> ITLB miss";
2772	}
2773	else
2774	{
2775	std::cout << " <PROC.DCACHE_TLB_MISS> DTLB miss";
2776	}
2777	std::cout << " / VADDR = " << std::hex << r_dcache_tlb_vaddr.read()
2778	<< " / BYPASS = " << bypass
2779	<< " / PTE_ADR = " << pte_paddr << std::endl;
2780	}
2781	#endif
2782
2783	break;
2784	}
2785	/////////////////////////
2786	case DCACHE_TLB_PTE1_GET: // try to read a PT1 entry in dcache
2787	{
2788	uint32_t entry;
2789	size_t way;
2790	size_t set;
2791	size_t word;
2792
2793	bool hit = r_dcache.read( r_dcache_tlb_paddr.read(),
2794	&entry,
2795	&way,
2796	&set,
2797	&word );
2798	#ifdef INSTRUMENTATION
2799	m_cpt_dcache_data_read++;
2800	m_cpt_dcache_dir_read++;
2801	#endif
2802	if ( hit ) // hit in dcache
2803	{
2804	if ( not (entry & PTE_V_MASK) ) // unmapped
2805	{
2806	if ( r_dcache_tlb_ins.read() )
2807	{
2808	r_mmu_ietr = MMU_READ_PT1_UNMAPPED;
2809	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
2810	r_icache_tlb_miss_req = false;
2811	r_icache_tlb_rsp_error = true;
2812	}
2813	else
2814	{
2815	r_mmu_detr = MMU_READ_PT1_UNMAPPED;
2816	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
2817	m_drsp.valid = true;
2818	m_drsp.error = true;
2819	}
2820	r_dcache_fsm = DCACHE_IDLE;
2821
2822	#if DEBUG_DCACHE
2823	if ( m_debug_dcache_fsm )
2824	{
2825	std::cout << " <PROC.DCACHE_TLB_PTE1_GET> HIT in dcache, but unmapped"
2826	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
2827	<< std::dec << " / way = " << way
2828	<< std::dec << " / set = " << set
2829	<< std::dec << " / word = " << word
2830	<< std::hex << " / PTE1 = " << entry << std::endl;
2831	}
2832	#endif
2833
2834	}
2835	else if( entry & PTE_T_MASK ) // PTD : me must access PT2
2836	{
2837	// mark the cache line ac containing a PTD
2838	r_dcache_contains_ptd[m_dcache_sets*way+set] = true;
2839
2840	// register bypass
2841	if ( r_dcache_tlb_ins.read() ) // itlb
2842	{
2843	r_itlb.set_bypass(r_dcache_tlb_vaddr.read(),
2844	entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1),
2845	r_dcache_tlb_paddr.read() >> (uint32_log2(m_icache_words<<2)));
2846	}
2847	else // dtlb
2848	{
2849	r_dtlb.set_bypass(r_dcache_tlb_vaddr.read(),
2850	entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1),
2851	r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2));
2852	}
2853	r_dcache_tlb_paddr = (paddr_t)(entry & ((1<<(m_paddr_nbits-PAGE_K_NBITS))-1)) << PAGE_K_NBITS \|
2854	(paddr_t)(((r_dcache_tlb_vaddr.read() & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3);
2855	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
2856
2857	#if DEBUG_DCACHE
2858	if ( m_debug_dcache_fsm )
2859	{
2860	std::cout << " <PROC.DCACHE_TLB_PTE1_GET> HIT in dcache"
2861	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
2862	<< std::dec << " / way = " << way
2863	<< std::dec << " / set = " << set
2864	<< std::dec << " / word = " << word
2865	<< std::hex << " / PTD = " << entry << std::endl;
2866	}
2867	#endif
2868	}
2869	else // PTE1 : we must update the TLB
2870	{
2871	r_dcache_in_tlb[m_icache_sets*way+set] = true;
2872	r_dcache_tlb_pte_flags = entry;
2873	r_dcache_tlb_cache_way = way;
2874	r_dcache_tlb_cache_set = set;
2875	r_dcache_tlb_cache_word = word;
2876	r_dcache_fsm = DCACHE_TLB_PTE1_SELECT;
2877
2878	#if DEBUG_DCACHE
2879	if ( m_debug_dcache_fsm )
2880	{
2881	std::cout << " <PROC.DCACHE_TLB_PTE1_GET> HIT in dcache"
2882	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
2883	<< std::dec << " / way = " << way
2884	<< std::dec << " / set = " << set
2885	<< std::dec << " / word = " << word
2886	<< std::hex << " / PTE1 = " << entry << std::endl;
2887	}
2888	#endif
2889	}
2890	}
2891	else // we must load the missing cache line in dcache
2892	{
2893	r_dcache_vci_miss_req = true;
2894	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
2895	r_dcache_miss_type = PTE1_MISS;
2896	r_dcache_fsm = DCACHE_MISS_VICTIM;
2897
2898	#if DEBUG_DCACHE
2899	if ( m_debug_dcache_fsm )
2900	{
2901	std::cout << " <PROC.DCACHE_TLB_PTE1_GET> MISS in dcache:"
2902	<< " PTE1 address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
2903	}
2904	#endif
2905	}
2906	break;
2907	}
2908	////////////////////////////
2909	case DCACHE_TLB_PTE1_SELECT: // select a slot for PTE1
2910	{
2911	size_t way;
2912	size_t set;
2913
2914	if ( r_dcache_tlb_ins.read() )
2915	{
2916	r_itlb.select( r_dcache_tlb_vaddr.read(),
2917	true, // PTE1
2918	&way,
2919	&set );
2920	#ifdef INSTRUMENTATION
2921	m_cpt_itlb_read++;
2922	#endif
2923	}
2924	else
2925	{
2926	r_dtlb.select( r_dcache_tlb_vaddr.read(),
2927	true, // PTE1
2928	&way,
2929	&set );
2930	#ifdef INSTRUMENTATION
2931	m_cpt_dtlb_read++;
2932	#endif
2933	}
2934	r_dcache_tlb_way = way;
2935	r_dcache_tlb_set = set;
2936	r_dcache_fsm = DCACHE_TLB_PTE1_UPDT;
2937
2938	#if DEBUG_DCACHE
2939	if ( m_debug_dcache_fsm )
2940	{
2941	if ( r_dcache_tlb_ins.read() )
2942	std::cout << " <PROC.DCACHE_TLB_PTE1_SELECT> Select a slot in ITLB:";
2943	else
2944	std::cout << " <PROC.DCACHE_TLB_PTE1_SELECT> Select a slot in DTLB:";
2945	std::cout << " way = " << std::dec << way
2946	<< " / set = " << set << std::endl;
2947	}
2948	#endif
2949	break;
2950	}
2951	//////////////////////////
2952	case DCACHE_TLB_PTE1_UPDT: // write a new PTE1 in tlb after testing the L/R bit
2953	// if L/R bit already set, exit the sub-fsm
2954	// if not, the page table must be updated
2955	{
2956	paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2);
2957	uint32_t pte = r_dcache_tlb_pte_flags.read();
2958	bool updt = false;
2959	bool local = true;
2960
2961	// We should compute the access locality:
2962	// The PPN MSB bits define the destination cluster index.
2963	// The m_srcid_d MSB bits define the source cluster index.
2964	// The number of bits to compare depends on the number of clusters,
2965	// and can be obtained in the mapping table.
2966	// As long as this computation is not done, all access are local.
2967
2968	if ( local ) // local access
2969	{
2970	if ( not ((pte & PTE_L_MASK) == PTE_L_MASK) ) // we must set the L bit
2971	{
2972	updt = true;
2973	r_dcache_vci_sc_old = pte;
2974	r_dcache_vci_sc_new = pte \| PTE_L_MASK;
2975	pte = pte \| PTE_L_MASK;
2976	}
2977	}
2978	else // remote access
2979	{
2980	if ( not ((pte & PTE_R_MASK) == PTE_R_MASK) ) // we must set the R bit
2981	{
2982	updt = true;
2983	r_dcache_vci_sc_old = pte;
2984	r_dcache_vci_sc_new = pte \| PTE_R_MASK;
2985	pte = pte \| PTE_R_MASK;
2986	}
2987	}
2988
2989	// update TLB
2990	if ( r_dcache_tlb_ins.read() )
2991	{
2992	r_itlb.write( true, // 2M page
2993	pte,
2994	0, // argument unused for a PTE1
2995	r_dcache_tlb_vaddr.read(),
2996	r_dcache_tlb_way.read(),
2997	r_dcache_tlb_set.read(),
2998	nline );
2999	#ifdef INSTRUMENTATION
3000	m_cpt_itlb_write++;
3001	#endif
3002	}
3003	else
3004	{
3005	r_dtlb.write( true, // 2M page
3006	pte,
3007	0, // argument unused for a PTE1
3008	r_dcache_tlb_vaddr.read(),
3009	r_dcache_tlb_way.read(),
3010	r_dcache_tlb_set.read(),
3011	nline );
3012	#ifdef INSTRUMENTATION
3013	m_cpt_dtlb_write++;
3014	#endif
3015	}
3016	// next state
3017	if ( updt ) r_dcache_fsm = DCACHE_TLB_LR_UPDT; // dcache and page table update
3018	else r_dcache_fsm = DCACHE_TLB_RETURN; // exit sub-fsm
3019
3020	#if DEBUG_DCACHE
3021	if ( m_debug_dcache_fsm )
3022	{
3023	if ( r_dcache_tlb_ins.read() )
3024	{
3025	std::cout << " <PROC.DCACHE_TLB_PTE1_UPDT> write PTE1 in ITLB";
3026	std::cout << " / set = " << std::dec << r_dcache_tlb_set.read()
3027	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3028	r_itlb.printTrace();
3029	}
3030	else
3031	{
3032	std::cout << " <PROC.DCACHE_TLB_PTE1_UPDT> write PTE1 in DTLB";
3033	std::cout << " / set = " << std::dec << r_dcache_tlb_set.read()
3034	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3035	r_dtlb.printTrace();
3036	}
3037
3038	}
3039	#endif
3040	break;
3041	}
3042	/////////////////////////
3043	case DCACHE_TLB_PTE2_GET: // Try to get a PTE2 (64 bits) in the dcache
3044	{
3045	uint32_t pte_flags;
3046	uint32_t pte_ppn;
3047	size_t way;
3048	size_t set;
3049	size_t word;
3050
3051	bool hit = r_dcache.read( r_dcache_tlb_paddr.read(),
3052	&pte_flags,
3053	&pte_ppn,
3054	&way,
3055	&set,
3056	&word );
3057	#ifdef INSTRUMENTATION
3058	m_cpt_dcache_data_read++;
3059	m_cpt_dcache_dir_read++;
3060	#endif
3061	if ( hit ) // request hits in dcache
3062	{
3063	if ( not (pte_flags & PTE_V_MASK) ) // unmapped
3064	{
3065	if ( r_dcache_tlb_ins.read() )
3066	{
3067	r_mmu_ietr = MMU_READ_PT2_UNMAPPED;
3068	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3069	r_icache_tlb_miss_req = false;
3070	r_icache_tlb_rsp_error = true;
3071	}
3072	else
3073	{
3074	r_mmu_detr = MMU_READ_PT2_UNMAPPED;
3075	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3076	m_drsp.valid = true;
3077	m_drsp.error = true;
3078	}
3079	r_dcache_fsm = DCACHE_IDLE;
3080
3081	#if DEBUG_DCACHE
3082	if ( m_debug_dcache_fsm )
3083	{
3084	std::cout << " <PROC.DCACHE_TLB_PTE2_GET> HIT in dcache, but PTE is unmapped"
3085	<< " PTE_FLAGS = " << std::hex << pte_flags
3086	<< " PTE_PPN = " << std::hex << pte_ppn << std::endl;
3087	}
3088	#endif
3089	}
3090	else // mapped : we must update the TLB
3091	{
3092	r_dcache_in_tlb[m_dcache_sets*way+set] = true;
3093	r_dcache_tlb_pte_flags = pte_flags;
3094	r_dcache_tlb_pte_ppn = pte_ppn;
3095	r_dcache_tlb_cache_way = way;
3096	r_dcache_tlb_cache_set = set;
3097	r_dcache_tlb_cache_word = word;
3098	r_dcache_fsm = DCACHE_TLB_PTE2_SELECT;
3099
3100	#if DEBUG_DCACHE
3101	if ( m_debug_dcache_fsm )
3102	{
3103	std::cout << " <PROC.DCACHE_TLB_PTE2_GET> HIT in dcache:"
3104	<< " PTE_FLAGS = " << std::hex << pte_flags
3105	<< " PTE_PPN = " << std::hex << pte_ppn << std::endl;
3106	}
3107	#endif
3108	}
3109	}
3110	else // we must load the missing cache line in dcache
3111	{
3112	r_dcache_fsm = DCACHE_MISS_VICTIM;
3113	r_dcache_vci_miss_req = true;
3114	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
3115	r_dcache_miss_type = PTE2_MISS;
3116
3117	#if DEBUG_DCACHE
3118	if ( m_debug_dcache_fsm )
3119	{
3120	std::cout << " <PROC.DCACHE_TLB_PTE2_GET> MISS in dcache:"
3121	<< " PTE address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
3122	}
3123	#endif
3124	}
3125	break;
3126	}
3127	////////////////////////////
3128	case DCACHE_TLB_PTE2_SELECT: // select a slot for PTE2
3129	{
3130	size_t way;
3131	size_t set;
3132
3133	if ( r_dcache_tlb_ins.read() )
3134	{
3135	r_itlb.select( r_dcache_tlb_vaddr.read(),
3136	false, // PTE2
3137	&way,
3138	&set );
3139	#ifdef INSTRUMENTATION
3140	m_cpt_itlb_read++;
3141	#endif
3142	}
3143	else
3144	{
3145	r_dtlb.select( r_dcache_tlb_vaddr.read(),
3146	false, // PTE2
3147	&way,
3148	&set );
3149	#ifdef INSTRUMENTATION
3150	m_cpt_dtlb_read++;
3151	#endif
3152	}
3153
3154	#if DEBUG_DCACHE
3155	if ( m_debug_dcache_fsm )
3156	{
3157	if ( r_dcache_tlb_ins.read() )
3158	std::cout << " <PROC.DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB:";
3159	else
3160	std::cout << " <PROC.DCACHE_TLB_PTE2_SELECT> Select a slot in DTLB:";
3161	std::cout << " way = " << std::dec << way
3162	<< " / set = " << set << std::endl;
3163	}
3164	#endif
3165	r_dcache_tlb_way = way;
3166	r_dcache_tlb_set = set;
3167	r_dcache_fsm = DCACHE_TLB_PTE2_UPDT;
3168	break;
3169	}
3170	//////////////////////////
3171	case DCACHE_TLB_PTE2_UPDT: // write a new PTE2 in tlb after testing the L/R bit
3172	// if L/R bit already set, exit the sub-fsm
3173	// if not, the page table must be updated by an atomic access
3174	{
3175	paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2);
3176	uint32_t pte_flags = r_dcache_tlb_pte_flags.read();
3177	uint32_t pte_ppn = r_dcache_tlb_pte_ppn.read();
3178	bool updt = false;
3179	bool local = true;
3180
3181	// We should compute the access locality:
3182	// The PPN MSB bits define the destination cluster index.
3183	// The m_srcid_d MSB bits define the source cluster index.
3184	// The number of bits to compare depends on the number of clusters,
3185	// and can be obtained in the mapping table.
3186	// As long as this computation is not done, all access are local.
3187
3188	if ( local ) // local access
3189	{
3190	if ( not ((pte_flags & PTE_L_MASK) == PTE_L_MASK) ) // we must set the L bit
3191	{
3192	updt = true;
3193	r_dcache_vci_sc_old = pte_flags;
3194	r_dcache_vci_sc_new = pte_flags \| PTE_L_MASK;
3195	pte_flags = pte_flags \| PTE_L_MASK;
3196	}
3197	}
3198	else // remote access
3199	{
3200	if ( not ((pte_flags & PTE_R_MASK) == PTE_R_MASK) ) // we must set the R bit
3201	{
3202	updt = true;
3203	r_dcache_vci_sc_old = pte_flags;
3204	r_dcache_vci_sc_new = pte_flags \| PTE_R_MASK;
3205	pte_flags = pte_flags \| PTE_R_MASK;
3206	}
3207	}
3208
3209	// update TLB for a PTE2
3210	if ( r_dcache_tlb_ins.read() )
3211	{
3212	r_itlb.write( false, // 4K page
3213	pte_flags,
3214	pte_ppn,
3215	r_dcache_tlb_vaddr.read(),
3216	r_dcache_tlb_way.read(),
3217	r_dcache_tlb_set.read(),
3218	nline );
3219	#ifdef INSTRUMENTATION
3220	m_cpt_itlb_write++;
3221	#endif
3222	}
3223	else
3224	{
3225	r_dtlb.write( false, // 4K page
3226	pte_flags,
3227	pte_ppn,
3228	r_dcache_tlb_vaddr.read(),
3229	r_dcache_tlb_way.read(),
3230	r_dcache_tlb_set.read(),
3231	nline );
3232	#ifdef INSTRUMENTATION
3233	m_cpt_dtlb_write++;
3234	#endif
3235	}
3236
3237	#if DEBUG_DCACHE
3238	if ( m_debug_dcache_fsm )
3239	{
3240	if ( r_dcache_tlb_ins.read() )
3241	{
3242	std::cout << " <PROC.DCACHE_TLB_PTE2_UPDT> write PTE2 in ITLB";
3243	std::cout << " / set = " << std::dec << r_dcache_tlb_set.read()
3244	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3245	r_itlb.printTrace();
3246	}
3247	else
3248	{
3249	std::cout << " <PROC.DCACHE_TLB_PTE2_UPDT> write PTE2 in DTLB";
3250	std::cout << " / set = " << std::dec << r_dcache_tlb_set.read()
3251	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3252	r_dtlb.printTrace();
3253	}
3254	}
3255	#endif
3256	// next state
3257	if ( updt ) r_dcache_fsm = DCACHE_TLB_LR_UPDT; // dcache and page table update
3258	else r_dcache_fsm = DCACHE_TLB_RETURN; // exit sub-fsm
3259	break;
3260	}
3261	////////////////////////
3262	case DCACHE_TLB_LR_UPDT: // update the dcache after a tlb miss (L/R bit),
3263	// request a SC transaction to CMD FSM
3264	{
3265	#if DEBUG_DCACHE
3266	if ( m_debug_dcache_fsm )
3267	{
3268	std::cout << " <PROC.DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit" << std::endl;
3269	}
3270	#endif
3271	r_dcache.write(r_dcache_tlb_cache_way.read(),
3272	r_dcache_tlb_cache_set.read(),
3273	r_dcache_tlb_cache_word.read(),
3274	r_dcache_tlb_pte_flags.read());
3275	#ifdef INSTRUMENTATION
3276	m_cpt_dcache_data_write++;
3277	#endif
3278	// r_dcache_vci_sc_old & r_dcache_vci_sc_new registers are already set
3279	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
3280	r_dcache_vci_sc_req = true;
3281	r_dcache_fsm = DCACHE_TLB_LR_WAIT;
3282	break;
3283	}
3284	////////////////////////
3285	case DCACHE_TLB_LR_WAIT: // Waiting a response to SC transaction.
3286	// We consume the response in rsp FIFO,
3287	// and exit the sub-fsm, but we don't
3288	// analyse the response, because we don't
3289	// care if the L/R bit update is not done.
3290	// We must take the coherence requests because
3291	// there is a risk of dead-lock
3292
3293	{
3294	// external coherence request
3295	if ( r_tgt_dcache_req )
3296	{
3297	r_dcache_fsm = DCACHE_CC_CHECK;
3298	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3299	break;
3300	}
3301
3302	if ( r_vci_rsp_data_error.read() ) // bus error
3303	{
3304	std::cout << "BUS ERROR in DCACHE_TLB_LR_WAIT state" << std::endl;
3305	std::cout << "This should not happen in this state" << std::endl;
3306	exit(0);
3307	}
3308	else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
3309	{
3310	#if DEBUG_DCACHE
3311	if ( m_debug_dcache_fsm )
3312	{
3313	std::cout << " <PROC.DCACHE_TLB_LR_WAIT> SC response received" << std::endl;
3314	}
3315	#endif
3316	vci_rsp_fifo_dcache_get = true;
3317	r_dcache_fsm = DCACHE_TLB_RETURN;
3318	}
3319	break;
3320	}
3321	///////////////////////
3322	case DCACHE_TLB_RETURN: // return to caller depending on tlb miss type
3323	{
3324	#if DEBUG_DCACHE
3325	if ( m_debug_dcache_fsm )
3326	{
3327	std::cout << " <PROC.DCACHE_TLB_RETURN> TLB MISS completed" << std::endl;
3328	}
3329	#endif
3330	if ( r_dcache_tlb_ins.read() ) r_icache_tlb_miss_req = false;
3331	r_dcache_fsm = DCACHE_IDLE;
3332	break;
3333	}
3334	///////////////////////
3335	case DCACHE_XTN_SWITCH: // Both itlb and dtlb must be flushed
3336	{
3337	if ( not r_dcache_xtn_req.read() )
3338	{
3339	r_dtlb.flush();
3340	r_dcache_fsm = DCACHE_IDLE;
3341	m_drsp.valid = true;
3342	}
3343	break;
3344	}
3345	/////////////////////
3346	case DCACHE_XTN_SYNC: // waiting until write buffer empty
3347	// The coherence request must be taken
3348	// as there is a risk of dead-lock
3349	{
3350	// external coherence request
3351	if ( r_tgt_dcache_req.read() )
3352	{
3353	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3354	r_dcache_fsm = DCACHE_CC_CHECK;
3355	}
3356
3357	if ( r_wbuf.empty() )
3358	{
3359	m_drsp.valid = true;
3360	r_dcache_fsm = DCACHE_IDLE;
3361	}
3362	break;
3363	}
3364	////////////////////////
3365	case DCACHE_XTN_IC_FLUSH: // Waiting completion of an XTN request to the ICACHE FSM
3366	case DCACHE_XTN_IC_INVAL_VA: // Caution : the itlb miss requests must be taken
3367	case DCACHE_XTN_IC_INVAL_PA: // because the XTN_ICACHE_INVAL request to icache
3368	case DCACHE_XTN_IT_INVAL: // can generate an itlb miss...
3369	{
3370	// external coherence request
3371	if ( r_tgt_dcache_req )
3372	{
3373	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3374	r_dcache_fsm = DCACHE_CC_CHECK;
3375	break;
3376	}
3377
3378	// itlb miss request
3379	if ( r_icache_tlb_miss_req.read() )
3380	{
3381	r_dcache_tlb_ins = true;
3382	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
3383	r_dcache_fsm = DCACHE_TLB_MISS;
3384	break;
3385	}
3386
3387	// test if XTN request to icache completed
3388	if ( not r_dcache_xtn_req.read() )
3389	{
3390	r_dcache_fsm = DCACHE_IDLE;
3391	m_drsp.valid = true;
3392	}
3393	break;
3394	}
3395	/////////////////////////
3396	case DCACHE_XTN_DC_FLUSH: // Invalidate sequencially all cache lines, using
3397	// the r_dcache_flush counter as a slot counter.
3398	// We loop in this state until all slots have been visited.
3399	// A cleanup request is generated for each valid line
3400	// and we are blocked until the previous cleanup is completed
3401	// Finally, both the itlb and dtlb are flushed
3402	// (including global entries)
3403	{
3404	if ( not r_dcache_cleanup_req )
3405	{
3406	paddr_t nline;
3407	size_t way = r_dcache_flush_count.read()/m_icache_sets;
3408	size_t set = r_dcache_flush_count.read()%m_icache_sets;
3409
3410	bool cleanup_req = r_dcache.inval( way,
3411	set,
3412	&nline );
3413	if ( cleanup_req )
3414	{
3415	r_dcache_cleanup_req = true;
3416	r_dcache_cleanup_line = nline;
3417	}
3418
3419	r_dcache_in_tlb[m_dcache_sets*way+set] = false;
3420	r_dcache_contains_ptd[m_dcache_sets*way+set] = false;
3421
3422	r_dcache_flush_count = r_dcache_flush_count.read() + 1;
3423
3424	if ( r_dcache_flush_count.read() == (m_dcache_sets*m_dcache_ways - 1) ) // last
3425	{
3426	r_dtlb.reset();
3427	r_itlb.reset();
3428	r_dcache_fsm = DCACHE_IDLE;
3429	m_drsp.valid = true;
3430	}
3431	}
3432	break;
3433	}
3434	/////////////////////////
3435	case DCACHE_XTN_DT_INVAL: // handling processor XTN_DTLB_INVAL request
3436	{
3437	r_dtlb.inval(r_dcache_p0_wdata.read());
3438	r_dcache_fsm = DCACHE_IDLE;
3439	m_drsp.valid = true;
3440	break;
3441	}
3442	////////////////////////////
3443	case DCACHE_XTN_DC_INVAL_VA: // selective cache line invalidate with virtual address
3444	// requires 3 cycles: access tlb, read cache, inval cache
3445	// we compute the physical address in this state
3446	{
3447	paddr_t paddr;
3448	bool hit;
3449
3450	if ( r_mmu_mode.read() & DATA_TLB_MASK ) // dtlb activated
3451	{
3452	#ifdef INSTRUMENTATION
3453	m_cpt_dtlb_read++;
3454	#endif
3455	hit = r_dtlb.translate( r_dcache_p0_wdata.read(),
3456	&paddr );
3457	}
3458	else // dtlb not activated
3459	{
3460	paddr = (paddr_t)r_dcache_p0_wdata.read();
3461	hit = true;
3462	}
3463
3464	if ( hit ) // tlb hit
3465	{
3466	r_dcache_p0_paddr = paddr;
3467	r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA;
3468	}
3469	else // tlb miss
3470	{
3471	#ifdef INSTRUMENTATION
3472	m_cpt_dtlb_miss++;
3473	#endif
3474	r_dcache_tlb_ins = false; // dtlb
3475	r_dcache_tlb_vaddr = r_dcache_p0_wdata.read();
3476	r_dcache_fsm = DCACHE_TLB_MISS;
3477	}
3478
3479	#if DEBUG_DCACHE
3480	if ( m_debug_dcache_fsm )
3481	{
3482	std::cout << " <PROC.DCACHE_XTN_DC_INVAL_VA> Compute physical address" << std::hex
3483	<< " / VADDR = " << r_dcache_p0_wdata.read()
3484	<< " / PADDR = " << paddr << std::endl;
3485	}
3486	#endif
3487
3488	break;
3489	}
3490	////////////////////////////
3491	case DCACHE_XTN_DC_INVAL_PA: // selective cache line invalidate with physical address
3492	// requires 2 cycles: read cache / inval cache
3493	// In this state we read dcache.
3494	{
3495	uint32_t data;
3496	size_t way;
3497	size_t set;
3498	size_t word;
3499	bool hit = r_dcache.read( r_dcache_p0_paddr.read(),
3500	&data,
3501	&way,
3502	&set,
3503	&word );
3504	#ifdef INSTRUMENTATION
3505	m_cpt_dcache_data_read++;
3506	m_cpt_dcache_dir_read++;
3507	#endif
3508	if ( hit ) // inval to be done
3509	{
3510	r_dcache_xtn_way = way;
3511	r_dcache_xtn_set = set;
3512	r_dcache_fsm = DCACHE_XTN_DC_INVAL_GO;
3513	}
3514	else // miss : nothing to do
3515	{
3516	r_dcache_fsm = DCACHE_IDLE;
3517	m_drsp.valid = true;
3518	}
3519
3520	#if DEBUG_DCACHE
3521	if ( m_debug_dcache_fsm )
3522	{
3523	std::cout << " <PROC.DCACHE_XTN_DC_INVAL_PA> Test hit in dcache" << std::hex
3524	<< " / PADDR = " << r_dcache_p0_paddr.read() << std::dec
3525	<< " / HIT = " << hit
3526	<< " / SET = " << set
3527	<< " / WAY = " << way << std::endl;
3528	}
3529	#endif
3530	break;
3531	}
3532	////////////////////////////
3533	case DCACHE_XTN_DC_INVAL_GO: // In this state, we invalidate the cache line
3534	// Blocked if previous cleanup not completed
3535	// Test if itlb or dtlb inval is required
3536	{
3537	if ( not r_dcache_cleanup_req.read() )
3538	{
3539	paddr_t nline;
3540	size_t way = r_dcache_xtn_way.read();
3541	size_t set = r_dcache_xtn_set.read();
3542	bool hit;
3543
3544	hit = r_dcache.inval( way,
3545	set,
3546	&nline );
3547	assert(hit && "XTN_DC_INVAL way/set should still be in cache");
3548
3549	// request cleanup
3550	r_dcache_cleanup_req = true;
3551	r_dcache_cleanup_line = nline;
3552
3553	// possible itlb & dtlb invalidate
3554	if ( r_dcache_in_tlb[way*m_dcache_sets+set] )
3555	{
3556	r_dcache_tlb_inval_line = nline;
3557	r_dcache_tlb_inval_count = 0;
3558	r_dcache_fsm_scan_save = DCACHE_XTN_DC_INVAL_END;
3559	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
3560	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
3561	}
3562	else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] )
3563	{
3564	r_itlb.reset();
3565	r_dtlb.reset();
3566	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
3567	r_dcache_fsm = DCACHE_IDLE;
3568	m_drsp.valid = true;
3569	}
3570	else
3571	{
3572	r_dcache_fsm = DCACHE_IDLE;
3573	m_drsp.valid = true;
3574	}
3575
3576	#if DEBUG_DCACHE
3577	if ( m_debug_dcache_fsm )
3578	{
3579	std::cout << " <PROC.DCACHE_XTN_DC_INVAL_GO> Actual dcache inval" << std::hex
3580	<< " / NLINE = " << nline << std::endl;
3581	}
3582	#endif
3583	}
3584	break;
3585	}
3586	//////////////////////////////
3587	case DCACHE_XTN_DC_INVAL_END: // send response to processor XTN request
3588	{
3589	r_dcache_fsm = DCACHE_IDLE;
3590	m_drsp.valid = true;
3591	break;
3592	}
3593	////////////////////////
3594	case DCACHE_MISS_VICTIM: // Selects a victim line if there is no pending cleanup
3595	// on the missing line, and if a new cleanup can be posted.
3596	// Set the r_dcache_cleanup_req flip-flop if required
3597	{
3598	size_t index; // unused
3599	bool hit = r_cleanup_buffer.hit( r_dcache_vci_paddr.read()>>(uint32_log2(m_dcache_words)+2), &index );
3600	if ( not hit and not r_dcache_cleanup_req.read() )
3601	{
3602	bool valid;
3603	size_t way;
3604	size_t set;
3605	paddr_t victim;
3606
3607	valid = r_dcache.victim_select( r_dcache_vci_paddr.read(),
3608	&victim,
3609	&way,
3610	&set );
3611	r_dcache_miss_way = way;
3612	r_dcache_miss_set = set;
3613
3614	if ( valid )
3615	{
3616	r_dcache_cleanup_req = true;
3617	r_dcache_cleanup_line = victim;
3618	r_dcache_fsm = DCACHE_MISS_INVAL;
3619	}
3620	else
3621	{
3622	r_dcache_fsm = DCACHE_MISS_WAIT;
3623	}
3624
3625	#if DEBUG_DCACHE
3626	if ( m_debug_dcache_fsm )
3627	{
3628	std::cout << " <PROC.DCACHE_MISS_VICTIM> Select a slot:" << std::dec
3629	<< " / WAY = " << way
3630	<< " / SET = " << set
3631	<< " / VALID = " << valid
3632	<< " / LINE = " << std::hex << victim << std::endl;
3633	}
3634	#endif
3635	}
3636	break;
3637	}
3638	///////////////////////
3639	case DCACHE_MISS_INVAL: // invalidate the victim line
3640	// and possibly request itlb or dtlb invalidate
3641	{
3642	paddr_t nline;
3643	size_t way = r_dcache_miss_way.read();
3644	size_t set = r_dcache_miss_set.read();
3645	bool hit;
3646
3647	hit = r_dcache.inval( way,
3648	set,
3649	&nline );
3650
3651	assert(hit && "selected way/set line should be in dcache");
3652
3653	#if DEBUG_DCACHE
3654	if ( m_debug_dcache_fsm )
3655	{
3656	std::cout << " <PROC.DCACHE_MISS_INVAL> inval line:" << std::dec
3657	<< " / way = " << way
3658	<< " / set = " << set
3659	<< " / nline = " << std::hex << nline << std::endl;
3660	}
3661	#endif
3662	// if selective itlb & dtlb invalidate are required
3663	// the miss response is not handled before invalidate completed
3664	if ( r_dcache_in_tlb[way*m_dcache_sets+set] )
3665	{
3666	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
3667	r_dcache_tlb_inval_line = nline;
3668	r_dcache_tlb_inval_count = 0;
3669	r_dcache_fsm_scan_save = DCACHE_MISS_WAIT;
3670	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
3671	}
3672	else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] )
3673	{
3674	r_itlb.reset();
3675	r_dtlb.reset();
3676	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
3677	r_dcache_fsm = DCACHE_MISS_WAIT;
3678	}
3679	else
3680	{
3681	r_dcache_fsm = DCACHE_MISS_WAIT;
3682	}
3683	break;
3684	}
3685	//////////////////////
3686	case DCACHE_MISS_WAIT: // waiting the response to a miss request from VCI_RSP FSM
3687	// This state is in charge of error signaling
3688	// There is 5 types of error depending on the requester
3689	{
3690	// external coherence request
3691	if ( r_tgt_dcache_req )
3692	{
3693	r_dcache_fsm_cc_save = r_dcache_fsm;
3694	r_dcache_fsm = DCACHE_CC_CHECK;
3695	break;
3696	}
3697
3698	if ( r_vci_rsp_data_error.read() ) // bus error
3699	{
3700	switch ( r_dcache_miss_type.read() )
3701	{
3702	case PROC_MISS:
3703	{
3704	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
3705	r_mmu_dbvar = r_dcache_p0_vaddr.read();
3706	m_drsp.valid = true;
3707	m_drsp.error = true;
3708	r_dcache_fsm = DCACHE_IDLE;
3709	break;
3710	}
3711	case PTE1_MISS:
3712	{
3713	if ( r_dcache_tlb_ins.read() )
3714	{
3715	r_mmu_ietr = MMU_READ_PT1_ILLEGAL_ACCESS;
3716	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3717	r_icache_tlb_miss_req = false;
3718	r_icache_tlb_rsp_error = true;
3719	}
3720	else
3721	{
3722	r_mmu_detr = MMU_READ_PT1_ILLEGAL_ACCESS;
3723	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3724	m_drsp.valid = true;
3725	m_drsp.error = true;
3726	}
3727	r_dcache_fsm = DCACHE_IDLE;
3728	break;
3729	}
3730	case PTE2_MISS:
3731	{
3732	if ( r_dcache_tlb_ins.read() )
3733	{
3734	r_mmu_ietr = MMU_READ_PT2_ILLEGAL_ACCESS;
3735	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3736	r_icache_tlb_miss_req = false;
3737	r_icache_tlb_rsp_error = true;
3738	}
3739	else
3740	{
3741	r_mmu_detr = MMU_READ_PT2_ILLEGAL_ACCESS;
3742	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3743	m_drsp.valid = true;
3744	m_drsp.error = true;
3745	}
3746	r_dcache_fsm = DCACHE_IDLE;
3747	break;
3748	}
3749	} // end switch type
3750	r_vci_rsp_data_error = false;
3751	}
3752	else if ( r_vci_rsp_fifo_dcache.rok() ) // valid response available
3753	{
3754	r_dcache_miss_word = 0;
3755	r_dcache_fsm = DCACHE_MISS_UPDT;
3756	}
3757	break;
3758	}
3759	//////////////////////
3760	case DCACHE_MISS_UPDT: // update the dcache (one word per cycle)
3761	// returns the response depending on the miss type
3762	{
3763	if ( r_vci_rsp_fifo_dcache.rok() ) // one word available
3764	{
3765	if ( r_dcache_miss_inval.read() ) // Matching coherence request
3766	// pop the FIFO, without cache update
3767	// send a cleanup for the missing line
3768	// if the previous cleanup is completed
3769	{
3770	if ( r_dcache_miss_word.read() < (m_dcache_words - 1) ) // not the last
3771	{
3772	vci_rsp_fifo_dcache_get = true;
3773	r_dcache_miss_word = r_dcache_miss_word.read() + 1;
3774	}
3775	else // last word
3776	{
3777	if ( not r_dcache_cleanup_req.read() ) // no pending cleanup
3778	{
3779	vci_rsp_fifo_dcache_get = true;
3780	r_dcache_cleanup_req = true;
3781	r_dcache_cleanup_line = r_dcache_vci_paddr.read() >>
3782	(uint32_log2(m_dcache_words)+2);
3783	r_dcache_miss_inval = false;
3784	r_dcache_fsm = DCACHE_IDLE;
3785	}
3786	}
3787	}
3788	else // No matching coherence request
3789	// pop the FIFO and update the cache
3790	// update the directory at the last word
3791	{
3792	size_t way = r_dcache_miss_way.read();
3793	size_t set = r_dcache_miss_set.read();
3794	size_t word = r_dcache_miss_word.read();
3795
3796	#ifdef INSTRUMENTATION
3797	m_cpt_dcache_data_write++;
3798	#endif
3799	r_dcache.write( way,
3800	set,
3801	word,
3802	r_vci_rsp_fifo_dcache.read());
3803
3804	vci_rsp_fifo_dcache_get = true;
3805	r_dcache_miss_word = r_dcache_miss_word.read() + 1;
3806
3807	// if last word, update directory, set in_tlb & contains_ptd bits
3808	if ( r_dcache_miss_word.read() == (m_dcache_words - 1) )
3809	{
3810
3811	#ifdef INSTRUMENTATION
3812	m_cpt_dcache_dir_write++;
3813	#endif
3814	r_dcache.victim_update_tag( r_dcache_vci_paddr.read(),
3815	r_dcache_miss_way.read(),
3816	r_dcache_miss_set.read() );
3817
3818	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
3819	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
3820
3821	if (r_dcache_miss_type.read()==PTE1_MISS) r_dcache_fsm = DCACHE_TLB_PTE1_GET;
3822	else if (r_dcache_miss_type.read()==PTE2_MISS) r_dcache_fsm = DCACHE_TLB_PTE2_GET;
3823	else r_dcache_fsm = DCACHE_IDLE;
3824	}
3825	}
3826
3827	#if DEBUG_DCACHE
3828	if ( m_debug_dcache_fsm )
3829	{
3830	if ( r_dcache_miss_inval.read() )
3831	{
3832	if ( r_dcache_miss_word.read() < m_dcache_words-1 )
3833	{
3834	std::cout << " <PROC.DCACHE_MISS_UPDT> Matching coherence request:"
3835	<< " pop the FIFO, don't update the cache" << std::endl;
3836	}
3837	else
3838	{
3839	std::cout << " <PROC.DCACHE_MISS_UPDT> Matching coherence request:"
3840	<< " last word : send a cleanup request " << std::endl;
3841	}
3842	}
3843	else
3844	{
3845	std::cout << " <PROC.DCACHE_MISS_UPDT> Write one word:"
3846	<< " address = " << std::hex << r_dcache_vci_paddr.read()
3847	<< " / data = " << r_vci_rsp_fifo_dcache.read()
3848	<< " / way = " << std::dec << r_dcache_miss_way.read()
3849	<< " / set = " << r_dcache_miss_set.read()
3850	<< " / word = " << r_dcache_miss_word.read() << std::endl;
3851	}
3852	}
3853	#endif
3854
3855	} // end if rok
3856	break;
3857	}
3858	/////////////////////
3859	case DCACHE_UNC_WAIT:
3860	{
3861	// external coherence request
3862	if ( r_tgt_dcache_req.read() )
3863	{
3864	r_dcache_fsm_cc_save = r_dcache_fsm;
3865	r_dcache_fsm = DCACHE_CC_CHECK;
3866	break;
3867	}
3868
3869	if ( r_vci_rsp_data_error.read() ) // bus error
3870	{
3871	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
3872	r_mmu_dbvar = m_dreq.addr;
3873	r_vci_rsp_data_error = false;
3874	m_drsp.error = true;
3875	m_drsp.valid = true;
3876	r_dcache_fsm = DCACHE_IDLE;
3877	break;
3878	}
3879	else if ( r_vci_rsp_fifo_dcache.rok() ) // data available
3880	{
3881	// consume data
3882	vci_rsp_fifo_dcache_get = true;
3883	r_dcache_fsm = DCACHE_IDLE;
3884
3885	// acknowledge the processor request if it has not been modified
3886	if ( m_dreq.valid and (m_dreq.addr == r_dcache_p0_vaddr.read()) )
3887	{
3888	m_drsp.valid = true;
3889	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
3890
3891	// makes reservation in case of LL
3892	if ( m_dreq.type == iss_t::DATA_LL )
3893	{
3894	r_dcache_ll_valid = true;
3895	r_dcache_ll_data = r_vci_rsp_fifo_dcache.read();
3896	r_dcache_ll_vaddr = m_dreq.addr;
3897	}
3898	}
3899	}
3900	break;
3901	}
3902	////////////////////
3903	case DCACHE_SC_WAIT: // waiting VCI response after a processor SC request
3904	{
3905	// external coherence request
3906	if ( r_tgt_dcache_req.read() )
3907	{
3908	r_dcache_fsm_cc_save = r_dcache_fsm;
3909	r_dcache_fsm = DCACHE_CC_CHECK;
3910	break;
3911	}
3912
3913	if ( r_vci_rsp_data_error.read() ) // bus error
3914	{
3915	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
3916	r_mmu_dbvar = m_dreq.addr;
3917	r_vci_rsp_data_error = false;
3918	m_drsp.error = true;
3919	m_drsp.valid = true;
3920	r_dcache_fsm = DCACHE_IDLE;
3921	break;
3922	}
3923	else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
3924	{
3925	vci_rsp_fifo_dcache_get = true;
3926	m_drsp.valid = true;
3927	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
3928	r_dcache_fsm = DCACHE_IDLE;
3929	}
3930	break;
3931	}
3932	//////////////////////////
3933	case DCACHE_DIRTY_GET_PTE: // This sub_fsm set the PTE Dirty bit in memory
3934	// before handling a processor WRITE or SC request
3935	// Input argument is r_dcache_dirty_paddr
3936	// In this first state, we get PTE value in dcache
3937	// and post a SC request to CMD FSM
3938	{
3939	// get PTE in dcache
3940	uint32_t pte;
3941	size_t way;
3942	size_t set;
3943	size_t word; // unused
3944	bool hit = r_dcache.read( r_dcache_dirty_paddr.read(),
3945	&pte,
3946	&way,
3947	&set,
3948	&word );
3949	#ifdef INSTRUMENTATION
3950	m_cpt_dcache_data_read++;
3951	m_cpt_dcache_dir_read++;
3952	#endif
3953	assert( hit and "error in DCACHE_DIRTY_TLB_SET: the PTE should be in dcache" );
3954
3955	// request sc transaction to CMD_FSM
3956	r_dcache_dirty_way = way;
3957	r_dcache_dirty_set = set;
3958	r_dcache_vci_sc_req = true;
3959	r_dcache_vci_paddr = r_dcache_dirty_paddr.read();
3960	r_dcache_vci_sc_old = pte;
3961	r_dcache_vci_sc_new = pte \| PTE_D_MASK;
3962	r_dcache_fsm = DCACHE_DIRTY_SC_WAIT;
3963
3964	#if DEBUG_DCACHE
3965	if ( m_debug_dcache_fsm )
3966	{
3967	std::cout << " <PROC.DCACHE_DIRTY_GET_PTE> Get PTE in dcache" << std::hex
3968	<< " / PTE_PADDR = " << r_dcache_dirty_paddr.read()
3969	<< " / PTE_VALUE = " << pte << std::dec
3970	<< " / CACHE_SET = " << set
3971	<< " / CACHE_WAY = " << way << std::endl;
3972	}
3973	#endif
3974	break;
3975	}
3976	//////////////////////////
3977	case DCACHE_DIRTY_SC_WAIT: // wait completion of SC for PTE Dirty bit
3978	// If PTE update is a success, return to IDLE state.
3979	// If PTE update is a failure, invalidate cache line
3980	// in DCACHE and invalidate the matching TLB entries.
3981	{
3982	// external coherence request
3983	if ( r_tgt_dcache_req )
3984	{
3985	r_dcache_fsm_cc_save = r_dcache_fsm;
3986	r_dcache_fsm = DCACHE_CC_CHECK;
3987	break;
3988	}
3989
3990	if ( r_vci_rsp_data_error.read() ) // bus error
3991	{
3992	std::cout << "BUS ERROR in DCACHE_DIRTY_SC_WAIT state" << std::endl;
3993	std::cout << "This should not happen in this state" << std::endl;
3994	exit(0);
3995	}
3996	else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
3997	{
3998	vci_rsp_fifo_dcache_get = true;
3999	if ( r_vci_rsp_fifo_dcache.read() == 0 ) // exit if dirty bit update atomic
4000	{
4001	r_dcache_fsm = DCACHE_IDLE;
4002
4003	#if DEBUG_DCACHE
4004	if ( m_debug_dcache_fsm )
4005	{
4006	std::cout << " <PROC.DCACHE_DIRTY_SC_WAIT> Dirty bit successfully set"
4007	<< std::endl;
4008	}
4009	#endif
4010	}
4011	else // invalidate the cache line TLBs
4012	{
4013
4014	#if DEBUG_DCACHE
4015	if ( m_debug_dcache_fsm )
4016	{
4017	std::cout << " <PROC.DCACHE_DIRTY_SC_WAIT> PTE modified : Inval cache line & TLBs"
4018	<< std::endl;
4019	}
4020	#endif
4021	paddr_t nline;
4022	size_t way = r_dcache_dirty_way.read();
4023	size_t set = r_dcache_dirty_set.read();
4024	bool hit;
4025
4026	hit = r_dcache.inval( way,
4027	set,
4028	&nline );
4029
4030	assert(hit && "PTE should still be in dcache");
4031
4032	// request cleanup
4033	r_dcache_cleanup_req = true;
4034	r_dcache_cleanup_line = nline;
4035
4036	if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // contains PTE
4037	{
4038	r_dcache_tlb_inval_line = nline;
4039	r_dcache_tlb_inval_count = 0;
4040	r_dcache_fsm_scan_save = DCACHE_IDLE;
4041	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4042	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
4043	}
4044	else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // contains PTD
4045	{
4046	r_itlb.reset();
4047	r_dtlb.reset();
4048	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
4049	r_dcache_fsm = DCACHE_IDLE;
4050	}
4051	else
4052	{
4053	r_dcache_fsm = DCACHE_IDLE;
4054	}
4055	}
4056	}
4057	break;
4058	}
4059	/////////////////////
4060	case DCACHE_CC_CHECK: // This state is the entry point for the sub-FSM
4061	// handling coherence requests.
4062	// If there is a matching pending miss on the modified cache
4063	// line this is signaled in the r_dcache_miss inval flip-flop.
4064	// If the updated (or invalidated) cache line has copies in TLBs
4065	// these TLB copies are invalidated.
4066	// The return state is defined in r_dcache_fsm_cc_save
4067	{
4068	paddr_t paddr = r_tgt_paddr.read();
4069	paddr_t mask = ~((m_dcache_words<<2)-1);
4070
4071
4072	if( (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) and
4073	((r_dcache_vci_paddr.read() & mask) == (paddr & mask)) ) // matching pending miss
4074	{
4075	r_dcache_miss_inval = true; // signaling the match
4076	r_tgt_dcache_req = false; // coherence request completed
4077	r_tgt_dcache_rsp = r_tgt_update.read(); // response required if update
4078	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4079
4080	#if DEBUG_DCACHE
4081	if ( m_debug_dcache_fsm )
4082	{
4083	std::cout << " <PROC.DCACHE_CC_CHECK> Coherence request matching a pending miss:"
4084	<< " address = " << std::hex << paddr << std::endl;
4085	}
4086	#endif
4087
4088	}
4089	else // no match
4090	{
4091	uint32_t rdata;
4092	size_t way;
4093	size_t set;
4094	size_t word;
4095
4096	bool hit = r_dcache.read(paddr,
4097	&rdata, // unused
4098	&way,
4099	&set,
4100	&word); // unused
4101	#ifdef INSTRUMENTATION
4102	m_cpt_dcache_data_read++;
4103	m_cpt_dcache_dir_read++;
4104	#endif
4105	r_dcache_cc_way = way;
4106	r_dcache_cc_set = set;
4107
4108	if ( hit and r_tgt_update.read() ) // hit update
4109	{
4110	r_dcache_fsm = DCACHE_CC_UPDT;
4111	r_dcache_cc_word = r_tgt_word_min.read();
4112	}
4113	else if ( hit and not r_tgt_update.read() ) // hit inval
4114	{
4115	r_dcache_fsm = DCACHE_CC_INVAL;
4116	}
4117	else // miss can happen
4118	{
4119	r_tgt_dcache_req = false;
4120	r_tgt_dcache_rsp = r_tgt_update.read();
4121	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4122	}
4123
4124	#if DEBUG_DCACHE
4125	if ( m_debug_dcache_fsm )
4126	{
4127
4128	std::cout << " <PROC.DCACHE_CC_CHECK> Coherence request received :"
4129	<< " address = " << std::hex << paddr << std::dec;
4130	if ( hit )
4131	{
4132	std::cout << " / HIT" << " / way = " << way << " / set = " << set << std::endl;
4133	}
4134	else
4135	{
4136	std::cout << " / MISS" << std::endl;
4137	}
4138	}
4139	#endif
4140
4141	}
4142	break;
4143	}
4144	/////////////////////
4145	case DCACHE_CC_INVAL: // invalidate one cache line
4146	// and test possible copies in TLBs
4147	{
4148	paddr_t nline;
4149	size_t way = r_dcache_cc_way.read();
4150	size_t set = r_dcache_cc_set.read();
4151	bool hit;
4152
4153	if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // selective TLB inval
4154	{
4155	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
4156	r_dcache_tlb_inval_line = nline;
4157	r_dcache_tlb_inval_count = 0;
4158	r_dcache_fsm_scan_save = r_dcache_fsm.read();
4159	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4160	}
4161	else // actual cache line inval
4162	{
4163	if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // TLB flush
4164	{
4165	r_itlb.reset();
4166	r_dtlb.reset();
4167	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
4168	}
4169	r_tgt_dcache_rsp = true;
4170	r_tgt_dcache_req = false;
4171	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4172
4173	hit = r_dcache.inval( way,
4174	set,
4175	&nline );
4176	#if DEBUG_DCACHE
4177	if ( m_debug_dcache_fsm )
4178	{
4179	std::cout << " <PROC.DCACHE_CC_INVAL> Invalidate cache line" << std::dec
4180	<< " / WAY = " << way
4181	<< " / SET = " << set << std::endl;
4182	}
4183	#endif
4184
4185	assert(hit && "CC_INVAL way/set should still be in dcache");
4186	}
4187	break;
4188	}
4189	///////////////////
4190	case DCACHE_CC_UPDT: // write one word per cycle (from word_min to word_max)
4191	// and test possible copies in TLBs
4192	{
4193	size_t word = r_dcache_cc_word.read();
4194	size_t way = r_dcache_cc_way.read();
4195	size_t set = r_dcache_cc_set.read();
4196	paddr_t nline = r_tgt_paddr.read() >> (uint32_log2(m_dcache_words)+2);
4197
4198	if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // selective TLB inval
4199	{
4200	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
4201	r_dcache_tlb_inval_line = nline;
4202	r_dcache_tlb_inval_count = 0;
4203	r_dcache_fsm_scan_save = r_dcache_fsm.read();
4204	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4205	}
4206	else // cache update
4207	{
4208	if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // TLB flush
4209	{
4210	r_itlb.reset();
4211	r_dtlb.reset();
4212	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
4213	}
4214
4215	r_dcache.write( way,
4216	set,
4217	word,
4218	r_tgt_buf[word],
4219	r_tgt_be[word] );
4220	#ifdef INSTRUMENTATION
4221	m_cpt_dcache_data_write++;
4222	#endif
4223	r_dcache_cc_word = word + 1;
4224
4225	#if DEBUG_DCACHE
4226	if ( m_debug_dcache_fsm )
4227	{
4228	std::cout << " <PROC.DCACHE_CC_UPDT> Update one word" << std::dec
4229	<< " / WAY = " << way
4230	<< " / SET = " << set
4231	<< " / WORD = " << word
4232	<< " / VALUE = " << std::hex << r_tgt_buf[word] << std::endl;
4233	}
4234	#endif
4235	if ( word == r_tgt_word_max.read() ) // last word
4236	{
4237	r_tgt_dcache_rsp = true;
4238	r_tgt_dcache_req = false;
4239	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4240	}
4241	}
4242
4243	break;
4244	}
4245	///////////////////////////
4246	case DCACHE_INVAL_TLB_SCAN: // Scan sequencially all TLB entries for both ITLB & DTLB
4247	// It makes the assumption that (m_itlb_sets == m_dtlb_sets)
4248	// and (m_itlb_ways == m_dtlb_ways)
4249	// We enter this state when a DCACHE line is modified,
4250	// and there is a copy in itlb or dtlb.
4251	// It can be caused by:
4252	// - a coherence inval or updt transaction,
4253	// - a line inval caused by a cache miss
4254	// - a processor XTN inval request,
4255	// - a WRITE hit,
4256	// - a Dirty bit update failure
4257	// Input arguments are:
4258	// - r_dcache_tlb_inval_line
4259	// - r_dcache_tlb_inval_count
4260	// - r_dcache_fsm_cc_save
4261	{
4262	paddr_t line = r_dcache_tlb_inval_line.read(); // nline
4263	size_t way = r_dcache_tlb_inval_count.read()/m_itlb_sets; // way
4264	size_t set = r_dcache_tlb_inval_count.read()%m_itlb_sets; // set
4265	bool ok;
4266
4267	ok = r_itlb.inval( line,
4268	way,
4269	set );
4270	#if DEBUG_DCACHE
4271	if ( m_debug_dcache_fsm and ok )
4272	{
4273	std::cout << " <PROC.DCACHE_INVAL_TLB_SCAN> Invalidate ITLB entry:" << std::hex
4274	<< " line = " << line << std::dec
4275	<< " / set = " << set
4276	<< " / way = " << way << std::endl;
4277	r_itlb.printTrace();
4278	}
4279	#endif
4280	ok = r_dtlb.inval( line,
4281	way,
4282	set );
4283	#if DEBUG_DCACHE
4284	if ( m_debug_dcache_fsm and ok )
4285	{
4286	std::cout << " <PROC.DCACHE_INVAL_TLB_SCAN> Invalidate DTLB entry:" << std::hex
4287	<< " line = " << line << std::dec
4288	<< " / set = " << set
4289	<< " / way = " << way << std::endl;
4290	r_dtlb.printTrace();
4291	}
4292	#endif
4293
4294	// return to the calling state when TLB inval completed
4295	if ( r_dcache_tlb_inval_count.read() == ((m_dtlb_sets*m_dtlb_ways)-1) )
4296	{
4297	r_dcache_fsm = r_dcache_fsm_scan_save.read();
4298	}
4299	r_dcache_tlb_inval_count = r_dcache_tlb_inval_count.read() + 1;
4300	break;
4301	}
4302	} // end switch r_dcache_fsm
4303
4304	///////////////// wbuf update //////////////////////////////////////////////////////
4305	r_wbuf.update();
4306
4307	//////////////// test processor frozen /////////////////////////////////////////////
4308	// The simulation exit if the number of consecutive frozen cycles
4309	// is larger than the m_max_frozen_cycles (constructor parameter)
4310	if ( (m_ireq.valid and not m_irsp.valid) or (m_dreq.valid and not m_drsp.valid) )
4311	{
4312	m_cpt_frz_cycles++; // used for instrumentation
4313	m_cpt_stop_simulation++; // used for debug
4314	if ( m_cpt_stop_simulation > m_max_frozen_cycles )
4315	{
4316	std::cout << std::dec << "ERROR in CC_VCACHE_WRAPPER " << name() << std::endl
4317	<< " stop at cycle " << m_cpt_total_cycles << std::endl
4318	<< " frozen since cycle " << m_cpt_total_cycles - m_max_frozen_cycles
4319	<< std::endl;
4320	exit(1);
4321	}
4322	}
4323	else
4324	{
4325	m_cpt_stop_simulation = 0;
4326	}
4327
4328	/////////// execute one iss cycle /////////////////////////////////
4329	{
4330	uint32_t it = 0;
4331	for (size_t i=0; i<(size_t)iss_t::n_irq; i++) if(p_irq[i].read()) it \|= (1<<i);
4332	r_iss.executeNCycles(1, m_irsp, m_drsp, it);
4333	}
4334
4335	////////////////////////////////////////////////////////////////////////////
4336	// The VCI_CMD FSM controls the following ressources:
4337	// - r_vci_cmd_fsm
4338	// - r_vci_cmd_min
4339	// - r_vci_cmd_max
4340	// - r_vci_cmd_cpt
4341	// - r_vci_cmd_imiss_prio
4342	// - wbuf (reset)
4343	// - r_icache_miss_req (reset)
4344	// - r_icache_unc_req (reset)
4345	// - r_dcache_vci_miss_req (reset)
4346	// - r_dcache_vci_unc_req (reset)
4347	// - r_dcache_vci_sc_req (reset)
4348	//
4349	// This FSM handles requests from both the DCACHE FSM & the ICACHE FSM.
4350	// There is 6 request types, with the following priorities :
4351	// 1 - Data Read Miss : r_dcache_vci_miss_req and miss in the write buffer
4352	// 2 - Data Read Uncachable : r_dcache_vci_unc_req
4353	// 3 - Instruction Miss : r_icache_miss_req and miss in the write buffer
4354	// 4 - Instruction Uncachable : r_icache_unc_req
4355	// 5 - Data Write : r_wbuf.rok()
4356	// 6 - Data Store Conditionnal: r_dcache_vci_sc_req
4357	//
4358	// As we want to support several simultaneous VCI transactions, the VCI_CMD_FSM
4359	// and the VCI_RSP_FSM are fully desynchronized.
4360	//
4361	// VCI formats:
4362	// According to the VCI advanced specification, all read requests packets
4363	// (data Uncached, Miss data, instruction Uncached, Miss instruction)
4364	// are one word packets.
4365	// For write burst packets, all words are in the same cache line,
4366	// and addresses must be contiguous (the BE field is 0 in case of "holes").
4367	// The sc command packet implements actually a compare-and-swap mechanism
4368	// and the packet contains two flits.
4369	////////////////////////////////////////////////////////////////////////////////////
4370
4371	switch ( r_vci_cmd_fsm.read() )
4372	{
4373	//////////////
4374	case CMD_IDLE:
4375	{
4376	// r_dcache_vci_miss_req and r_icache_miss_req require both a write_buffer access
4377	// to check a possible pending write on the same cache line.
4378	// As there is only one possible access per cycle to write buffer, we implement
4379	// a round-robin priority for this access, using the r_vci_cmd_imiss_prio flip-flop.
4380
4381	size_t wbuf_min;
4382	size_t wbuf_max;
4383
4384	bool dcache_miss_req = r_dcache_vci_miss_req.read()
4385	and ( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() );
4386
4387	bool icache_miss_req = r_icache_miss_req.read()
4388	and ( not r_dcache_vci_miss_req.read() or r_vci_cmd_imiss_prio.read() );
4389
4390	// 1 - Data Read Miss
4391	if ( dcache_miss_req and r_wbuf.miss(r_dcache_vci_paddr.read()) )
4392	{
4393	r_vci_cmd_fsm = CMD_DATA_MISS;
4394	r_dcache_vci_miss_req = false;
4395	r_vci_cmd_imiss_prio = true;
4396	// m_cpt_dmiss_transaction++;
4397	}
4398	// 2 - Data Read Uncachable
4399	else if ( r_dcache_vci_unc_req.read() )
4400	{
4401	r_vci_cmd_fsm = CMD_DATA_UNC;
4402	r_dcache_vci_unc_req = false;
4403	// m_cpt_dunc_transaction++;
4404	}
4405	// 3 - Instruction Miss
4406	else if ( icache_miss_req and r_wbuf.miss(r_icache_vci_paddr.read()) )
4407	{
4408	r_vci_cmd_fsm = CMD_INS_MISS;
4409	r_icache_miss_req = false;
4410	r_vci_cmd_imiss_prio = false;
4411	// m_cpt_imiss_transaction++;
4412	}
4413	// 4 - Instruction Uncachable
4414	else if ( r_icache_unc_req.read() )
4415	{
4416	r_vci_cmd_fsm = CMD_INS_UNC;
4417	r_icache_unc_req = false;
4418	// m_cpt_iunc_transaction++;
4419	}
4420	// 5 - Data Write
4421	else if ( r_wbuf.rok(&wbuf_min, &wbuf_max) )
4422	{
4423	r_vci_cmd_fsm = CMD_DATA_WRITE;
4424	r_vci_cmd_cpt = wbuf_min;
4425	r_vci_cmd_min = wbuf_min;
4426	r_vci_cmd_max = wbuf_max;
4427	// m_cpt_write_transaction++;
4428	// m_length_write_transaction += (wbuf_max-wbuf_min+1);
4429	}
4430	// 6 - Data Store Conditionnal
4431	else if ( r_dcache_vci_sc_req.read() )
4432	{
4433	r_vci_cmd_fsm = CMD_DATA_SC;
4434	r_dcache_vci_sc_req = false;
4435	r_vci_cmd_cpt = 0;
4436	// m_cpt_sc_transaction++;
4437	}
4438	break;
4439	}
4440	////////////////////
4441	case CMD_DATA_WRITE:
4442	{
4443	if ( p_vci_ini_d.cmdack.read() )
4444	{
4445	// m_conso_wbuf_read++;
4446	r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
4447	if (r_vci_cmd_cpt == r_vci_cmd_max) // last flit sent
4448	{
4449	r_vci_cmd_fsm = CMD_IDLE ;
4450	r_wbuf.sent() ;
4451	}
4452	}
4453	break;
4454	}
4455	/////////////////
4456	case CMD_DATA_SC:
4457	{
4458	// The SC VCI command contains two flits
4459	if ( p_vci_ini_d.cmdack.read() )
4460	{
4461	r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
4462	if (r_vci_cmd_cpt == 1) r_vci_cmd_fsm = CMD_IDLE ;
4463	}
4464	break;
4465	}
4466	//////////////////
4467	case CMD_INS_MISS:
4468	case CMD_INS_UNC:
4469	case CMD_DATA_MISS:
4470	case CMD_DATA_UNC:
4471	{
4472	// all read VCI commands contain one single flit
4473	if ( p_vci_ini_d.cmdack.read() ) r_vci_cmd_fsm = CMD_IDLE;
4474	break;
4475	}
4476
4477	} // end switch r_vci_cmd_fsm
4478
4479	//////////////////////////////////////////////////////////////////////////
4480	// The VCI_RSP FSM controls the following ressources:
4481	// - r_vci_rsp_fsm:
4482	// - r_vci_rsp_fifo_icache (push)
4483	// - r_vci_rsp_fifo_dcache (push)
4484	// - r_vci_rsp_data_error (set)
4485	// - r_vci_rsp_ins_error (set)
4486	// - r_vci_rsp_cpt
4487	//
4488	// As the VCI_RSP and VCI_CMD are fully desynchronized to support several
4489	// simultaneous VCI transactions, this FSM uses the VCI TRDID field
4490	// to identify the transactions.
4491	//
4492	// VCI vormat:
4493	// This component checks the response packet length and accepts only
4494	// single word packets for write response packets.
4495	//
4496	// Error handling:
4497	// This FSM analyzes the VCI error code and signals directly the Write Bus Error.
4498	// In case of Read Data Error, the VCI_RSP FSM sets the r_vci_rsp_data_error
4499	// flip_flop and the error is signaled by the DCACHE FSM.
4500	// In case of Instruction Error, the VCI_RSP FSM sets the r_vci_rsp_ins_error
4501	// flip_flop and the error is signaled by the ICACHE FSM.
4502	// In case of Cleanup Error, the simulation stops with an error message...
4503	//////////////////////////////////////////////////////////////////////////
4504
4505	switch ( r_vci_rsp_fsm.read() )
4506	{
4507	//////////////
4508	case RSP_IDLE:
4509	{
4510	if ( p_vci_ini_d.rspval.read() )
4511	{
4512	r_vci_rsp_cpt = 0;
4513
4514	if ( (p_vci_ini_d.rtrdid.read() >> (vci_param::T-1)) != 0 ) // Write transaction
4515	{
4516	r_vci_rsp_fsm = RSP_DATA_WRITE;
4517	}
4518	else if ( p_vci_ini_d.rtrdid.read() == TYPE_INS_MISS )
4519	{
4520	r_vci_rsp_fsm = RSP_INS_MISS;
4521	}
4522	else if ( p_vci_ini_d.rtrdid.read() == TYPE_INS_UNC )
4523	{
4524	r_vci_rsp_fsm = RSP_INS_UNC;
4525	}
4526	else if ( p_vci_ini_d.rtrdid.read() == TYPE_DATA_MISS )
4527	{
4528	r_vci_rsp_fsm = RSP_DATA_MISS;
4529	}
4530	else if ( p_vci_ini_d.rtrdid.read() == TYPE_DATA_UNC )
4531	{
4532	r_vci_rsp_fsm = RSP_DATA_UNC;
4533	}
4534	else
4535	{
4536	assert(false and "Unexpected VCI response");
4537	}
4538	}
4539	break;
4540	}
4541	//////////////////
4542	case RSP_INS_MISS:
4543	{
4544	if ( p_vci_ini_d.rspval.read() )
4545	{
4546	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported
4547	{
4548	r_vci_rsp_ins_error = true;
4549	if ( p_vci_ini_d.reop.read() ) r_vci_rsp_fsm = RSP_IDLE;
4550	}
4551	else // no error reported
4552	{
4553	if ( r_vci_rsp_fifo_icache.wok() )
4554	{
4555	assert( (r_vci_rsp_cpt.read() < m_icache_words) and
4556	"The VCI response packet for instruction miss is too long" );
4557
4558	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
4559	vci_rsp_fifo_icache_put = true,
4560	vci_rsp_fifo_icache_data = p_vci_ini_d.rdata.read();
4561	if ( p_vci_ini_d.reop.read() )
4562	{
4563	assert( (r_vci_rsp_cpt.read() == m_icache_words - 1) and
4564	"The VCI response packet for instruction miss is too short");
4565
4566	r_vci_rsp_fsm = RSP_IDLE;
4567	}
4568	}
4569	}
4570	}
4571	break;
4572	}
4573	/////////////////
4574	case RSP_INS_UNC:
4575	{
4576	if (p_vci_ini_d.rspval.read() )
4577	{
4578	assert( p_vci_ini_d.reop.read() and
4579	"illegal VCI response packet for uncachable instruction");
4580
4581	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported
4582	{
4583	r_vci_rsp_ins_error = true;
4584	r_vci_rsp_fsm = RSP_IDLE;
4585	}
4586	else // no error reported
4587	{
4588	if ( r_vci_rsp_fifo_icache.wok())
4589	{
4590	vci_rsp_fifo_icache_put = true;
4591	vci_rsp_fifo_icache_data = p_vci_ini_d.rdata.read();
4592	r_vci_rsp_fsm = RSP_IDLE;
4593	}
4594	}
4595	}
4596	break;
4597	}
4598	///////////////////
4599	case RSP_DATA_MISS:
4600	{
4601	if ( p_vci_ini_d.rspval.read() )
4602	{
4603	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported
4604	{
4605	r_vci_rsp_data_error = true;
4606	if ( p_vci_ini_d.reop.read() ) r_vci_rsp_fsm = RSP_IDLE;
4607	}
4608	else // no error reported
4609	{
4610	if ( r_vci_rsp_fifo_dcache.wok() )
4611	{
4612	assert( (r_vci_rsp_cpt.read() < m_dcache_words) and
4613	"The VCI response packet for data miss is too long");
4614
4615	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
4616	vci_rsp_fifo_dcache_put = true,
4617	vci_rsp_fifo_dcache_data = p_vci_ini_d.rdata.read();
4618	if ( p_vci_ini_d.reop.read() )
4619	{
4620	assert( (r_vci_rsp_cpt.read() == m_dcache_words - 1) and
4621	"The VCI response packet for data miss is too short");
4622
4623	r_vci_rsp_fsm = RSP_IDLE;
4624	}
4625	}
4626	}
4627	}
4628	break;
4629	}
4630	//////////////////
4631	case RSP_DATA_UNC:
4632	{
4633	if (p_vci_ini_d.rspval.read() )
4634	{
4635	assert( p_vci_ini_d.reop.read() and
4636	"illegal VCI response packet for uncachable read data");
4637
4638	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported
4639	{
4640	r_vci_rsp_data_error = true;
4641	r_vci_rsp_fsm = RSP_IDLE;
4642	}
4643	else // no error reported
4644	{
4645	if ( r_vci_rsp_fifo_dcache.wok())
4646	{
4647	vci_rsp_fifo_dcache_put = true;
4648	vci_rsp_fifo_dcache_data = p_vci_ini_d.rdata.read();
4649	r_vci_rsp_fsm = RSP_IDLE;
4650	}
4651	}
4652	}
4653	break;
4654	}
4655	////////////////////
4656	case RSP_DATA_WRITE:
4657	{
4658	if (p_vci_ini_d.rspval.read())
4659	{
4660	assert( p_vci_ini_d.reop.read() and
4661	"a VCI response packet must contain one flit for a write transaction");
4662
4663	r_vci_rsp_fsm = RSP_IDLE;
4664	uint32_t wbuf_index = p_vci_ini_d.rtrdid.read() - (1<<(vci_param::T-1));
4665	bool cacheable = r_wbuf.completed(wbuf_index);
4666	if ( not cacheable ) r_dcache_pending_unc_write = false;
4667	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) r_iss.setWriteBerr();
4668	}
4669	break;
4670	}
4671	} // end switch r_vci_rsp_fsm
4672
4673	/////////////////////////////////////////////////////////////////////////////////////
4674	// The CLEANUP FSM is in charge to send the cleanup commands on the coherence
4675	// network. It has two clients (DCACHE FSM and ICACHE FSM) that are served
4676	// with a round-robin priority. All cleanup commands are registered in the
4677	// r_cleanup_buffer, because we must avoid to send a Read Miss command
4678	// for line (X) if there is a pending cleanup for line (X): the r_cleanup_buffer
4679	// is tested by the ICACHE FSM and DCACHE FSM before posting a miss request.
4680	// The CLEANUP FSM resets the r_*cache_cleanup request flip-flops as soon as
4681	// the request has been sent and registered in the buffer.
4682	// The buffer itself is cleared when the cleanup response is received.
4683	// We use an assocative registration buffer (CAM) in order to support several
4684	// simultaneous cleanup transactions (up to 4 simultaneous clenups).
4685	// The VCI TRDID field is used to distinguish data/instruction cleanups:
4686	// - if data cleanup : TRDID = 2*index + 0
4687	// - if instruction cleanup : TRDID = 2*index + 1
4688	/////////////////////////////////////////////////////////////////////////////////////
4689
4690	switch ( r_cleanup_fsm.read() )
4691	{
4692	///////////////////////
4693	case CLEANUP_DATA_IDLE: // dcache has highest priority
4694	{
4695	size_t index = 0;
4696	bool ok;
4697	if ( r_dcache_cleanup_req.read() ) // dcache request
4698	{
4699	ok = r_cleanup_buffer.write( r_dcache_cleanup_line.read(),
4700	&index );
4701	if ( ok ) // successful registration
4702	{
4703	r_cleanup_fsm = CLEANUP_DATA_GO;
4704	r_cleanup_trdid = index<<1;
4705	}
4706	}
4707	else if ( r_icache_cleanup_req.read() ) // icache request
4708	{
4709	ok = r_cleanup_buffer.write( r_icache_cleanup_line.read(),
4710	&index );
4711	if ( ok ) // successful registration
4712	{
4713	r_cleanup_fsm = CLEANUP_INS_GO;
4714	r_cleanup_trdid = (index<<1) + 1;
4715	}
4716	}
4717	break;
4718	}
4719	//////////////////////
4720	case CLEANUP_INS_IDLE: // icache has highest priority
4721	{
4722	size_t index = 0;
4723	bool ok;
4724	if ( r_icache_cleanup_req.read() ) // icache request
4725	{
4726	ok = r_cleanup_buffer.write( r_icache_cleanup_line.read(),
4727	&index );
4728	if ( ok ) // successful registration
4729	{
4730	r_cleanup_fsm = CLEANUP_INS_GO;
4731	r_cleanup_trdid = (index<<1) + 1;
4732	}
4733	}
4734	else if ( r_dcache_cleanup_req.read() ) // dcache request
4735	{
4736	ok = r_cleanup_buffer.write( r_dcache_cleanup_line.read(),
4737	&index );
4738	if ( ok ) // successful registration
4739	{
4740	r_cleanup_fsm = CLEANUP_DATA_GO;
4741	r_cleanup_trdid = index<<1;
4742	}
4743	}
4744	break;
4745	}
4746	/////////////////////
4747	case CLEANUP_DATA_GO:
4748	{
4749	if ( p_vci_ini_c.cmdack.read() )
4750	{
4751	r_cleanup_fsm = CLEANUP_INS_IDLE;
4752	r_dcache_cleanup_req = false;
4753
4754	#if DEBUG_CLEANUP
4755	if ( m_debug_cleanup_fsm )
4756	{
4757	std::cout << " <PROC.CLEANUP_DATA_GO> Cleanup request for icache:" << std::hex
4758	<< " address = " << (r_dcache_cleanup_line.read()m_dcache_words4)
4759	<< " / trdid = " << std::dec << r_cleanup_trdid.read() << std::endl;
4760	}
4761	#endif
4762	}
4763	break;
4764	}
4765	////////////////////
4766	case CLEANUP_INS_GO:
4767	{
4768	if ( p_vci_ini_c.cmdack.read() )
4769	{
4770	r_cleanup_fsm = CLEANUP_DATA_IDLE;
4771	r_icache_cleanup_req = false;
4772
4773	#if DEBUG_CLEANUP
4774	if ( m_debug_cleanup_fsm )
4775	{
4776	std::cout << " <PROC.CLEANUP_INS_GO> Cleanup request for dcache:" << std::hex
4777	<< " address = " << (r_icache_cleanup_line.read()m_icache_words4)
4778	<< " / trdid = " << std::dec << r_cleanup_trdid.read() << std::endl;
4779	}
4780	#endif
4781	}
4782	break;
4783	}
4784	} // end switch CLEANUP FSM
4785
4786	//////////////// Handling cleanup responses //////////////////
4787	if ( p_vci_ini_c.rspval.read() )
4788	{
4789	r_cleanup_buffer.inval( p_vci_ini_c.rtrdid.read() >> 1);
4790	}
4791
4792	///////////////// Response FIFOs update //////////////////////
4793	r_vci_rsp_fifo_icache.update(vci_rsp_fifo_icache_get,
4794	vci_rsp_fifo_icache_put,
4795	vci_rsp_fifo_icache_data);
4796
4797	r_vci_rsp_fifo_dcache.update(vci_rsp_fifo_dcache_get,
4798	vci_rsp_fifo_dcache_put,
4799	vci_rsp_fifo_dcache_data);
4800	} // end transition()
4801
4802	///////////////////////
4803	tmpl(void)::genMoore()
4804	///////////////////////
4805	{
4806	////////////////////////////////////////////////////////////////
4807	// VCI initiator command on the coherence network (cleanup)
4808	// it depends on the CLEANUP FSM state
4809
4810	paddr_t address;
4811
4812	if ( r_cleanup_fsm.read() == CLEANUP_DATA_GO )
4813	address = r_dcache_cleanup_line.read()m_dcache_words4;
4814	else if ( r_cleanup_fsm.read() == CLEANUP_INS_GO )
4815	address = r_icache_cleanup_line.read()m_icache_words4;
4816	else
4817	address = 0;
4818
4819	p_vci_ini_c.cmdval = ((r_cleanup_fsm.read() == CLEANUP_DATA_GO) or
4820	(r_cleanup_fsm.read() == CLEANUP_INS_GO) );
4821	p_vci_ini_c.address = address;
4822	p_vci_ini_c.wdata = 0;
4823	p_vci_ini_c.be = 0xF;
4824	p_vci_ini_c.plen = 4;
4825	p_vci_ini_c.cmd = vci_param::CMD_WRITE;
4826	p_vci_ini_c.trdid = r_cleanup_trdid.read();
4827	p_vci_ini_c.pktid = 0;
4828	p_vci_ini_c.srcid = m_srcid_c;
4829	p_vci_ini_c.cons = false;
4830	p_vci_ini_c.wrap = false;
4831	p_vci_ini_c.contig = false;
4832	p_vci_ini_c.clen = 0;
4833	p_vci_ini_c.cfixed = false;
4834	p_vci_ini_c.eop = true;
4835
4836	/////////////////////////////////////////////////////////////////
4837	// VCI initiator response on the coherence network (cleanup)
4838	// We always consume the response, and we don't use it.
4839
4840	p_vci_ini_c.rspack = true;
4841
4842	/////////////////////////////////////////////////////////////////
4843	// VCI initiator command on the direct network
4844	// it depends on the CMD FSM state
4845
4846	p_vci_ini_d.pktid = 0;
4847	p_vci_ini_d.srcid = m_srcid_d;
4848	p_vci_ini_d.cons = (r_vci_cmd_fsm.read() == CMD_DATA_SC);
4849	p_vci_ini_d.contig = not (r_vci_cmd_fsm.read() == CMD_DATA_SC);
4850	p_vci_ini_d.wrap = false;
4851	p_vci_ini_d.clen = 0;
4852	p_vci_ini_d.cfixed = false;
4853
4854	switch ( r_vci_cmd_fsm.read() ) {
4855
4856	case CMD_IDLE:
4857	p_vci_ini_d.cmdval = false;
4858	p_vci_ini_d.address = 0;
4859	p_vci_ini_d.wdata = 0;
4860	p_vci_ini_d.be = 0;
4861	p_vci_ini_d.trdid = 0;
4862	p_vci_ini_d.plen = 0;
4863	p_vci_ini_d.cmd = vci_param::CMD_NOP;
4864	p_vci_ini_d.eop = false;
4865	break;
4866
4867	case CMD_INS_MISS:
4868	p_vci_ini_d.cmdval = true;
4869	p_vci_ini_d.address = r_icache_vci_paddr.read() & m_icache_yzmask;
4870	p_vci_ini_d.wdata = 0;
4871	p_vci_ini_d.be = 0xF;
4872	p_vci_ini_d.trdid = TYPE_INS_MISS;
4873	p_vci_ini_d.plen = m_icache_words<<2;
4874	p_vci_ini_d.cmd = vci_param::CMD_READ;
4875	p_vci_ini_d.eop = true;
4876	break;
4877
4878	case CMD_INS_UNC:
4879	p_vci_ini_d.cmdval = true;
4880	p_vci_ini_d.address = r_icache_vci_paddr.read() & ~0x3;
4881	p_vci_ini_d.wdata = 0;
4882	p_vci_ini_d.be = 0xF;
4883	p_vci_ini_d.trdid = TYPE_INS_UNC;
4884	p_vci_ini_d.plen = 4;
4885	p_vci_ini_d.cmd = vci_param::CMD_READ;
4886	p_vci_ini_d.eop = true;
4887	break;
4888
4889	case CMD_DATA_MISS:
4890	p_vci_ini_d.cmdval = true;
4891	p_vci_ini_d.address = r_dcache_vci_paddr.read() & m_dcache_yzmask;
4892	p_vci_ini_d.wdata = 0;
4893	p_vci_ini_d.be = 0xF;
4894	p_vci_ini_d.trdid = TYPE_DATA_MISS;
4895	p_vci_ini_d.plen = m_dcache_words << 2;
4896	p_vci_ini_d.cmd = vci_param::CMD_READ;
4897	p_vci_ini_d.eop = true;
4898	break;
4899
4900	case CMD_DATA_UNC:
4901	p_vci_ini_d.cmdval = true;
4902	p_vci_ini_d.address = r_dcache_vci_paddr.read() & ~0x3;
4903	p_vci_ini_d.wdata = 0;
4904	p_vci_ini_d.be = r_dcache_vci_unc_be.read();
4905	p_vci_ini_d.trdid = TYPE_DATA_UNC;
4906	p_vci_ini_d.plen = 4;
4907	p_vci_ini_d.cmd = vci_param::CMD_READ;
4908	p_vci_ini_d.eop = true;
4909	break;
4910
4911	case CMD_DATA_WRITE:
4912	p_vci_ini_d.cmdval = true;
4913	p_vci_ini_d.address = r_wbuf.getAddress(r_vci_cmd_cpt.read()) & ~0x3;
4914	p_vci_ini_d.wdata = r_wbuf.getData(r_vci_cmd_cpt.read());
4915	p_vci_ini_d.be = r_wbuf.getBe(r_vci_cmd_cpt.read());
4916	p_vci_ini_d.trdid = r_wbuf.getIndex() + (1<<(vci_param::T-1));
4917	p_vci_ini_d.plen = (r_vci_cmd_max.read() - r_vci_cmd_min.read() + 1) << 2;
4918	p_vci_ini_d.cmd = vci_param::CMD_WRITE;
4919	p_vci_ini_d.eop = (r_vci_cmd_cpt.read() == r_vci_cmd_max.read());
4920	break;
4921
4922	case CMD_DATA_SC:
4923	p_vci_ini_d.cmdval = true;
4924	p_vci_ini_d.address = r_dcache_vci_paddr.read() & ~0x3;
4925	if ( r_vci_cmd_cpt.read() == 0 ) p_vci_ini_d.wdata = r_dcache_vci_sc_old.read();
4926	else p_vci_ini_d.wdata = r_dcache_vci_sc_new.read();
4927	p_vci_ini_d.be = 0xF;
4928	p_vci_ini_d.trdid = TYPE_DATA_UNC;
4929	p_vci_ini_d.plen = 8;
4930	p_vci_ini_d.cmd = vci_param::CMD_STORE_COND;
4931	p_vci_ini_d.eop = (r_vci_cmd_cpt.read() == 1);
4932	break;
4933	} // end switch r_vci_cmd_fsm
4934
4935	//////////////////////////////////////////////////////////
4936	// VCI initiator response on the direct network
4937	// it depends on the VCI RSP state
4938
4939	switch (r_vci_rsp_fsm.read() )
4940	{
4941	case RSP_DATA_WRITE : p_vci_ini_d.rspack = true; break;
4942	case RSP_INS_MISS : p_vci_ini_d.rspack = r_vci_rsp_fifo_icache.wok(); break;
4943	case RSP_INS_UNC : p_vci_ini_d.rspack = r_vci_rsp_fifo_icache.wok(); break;
4944	case RSP_DATA_MISS : p_vci_ini_d.rspack = r_vci_rsp_fifo_dcache.wok(); break;
4945	case RSP_DATA_UNC : p_vci_ini_d.rspack = r_vci_rsp_fifo_dcache.wok(); break;
4946	case RSP_IDLE : p_vci_ini_d.rspack = false; break;
4947	} // end switch r_vci_rsp_fsm
4948
4949	////////////////////////////////////////////////////////////////
4950	// VCI target command and response on the coherence network
4951	switch ( r_tgt_fsm.read() )
4952	{
4953	case TGT_IDLE:
4954	case TGT_UPDT_WORD:
4955	case TGT_UPDT_DATA:
4956	p_vci_tgt_c.cmdack = true;
4957	p_vci_tgt_c.rspval = false;
4958	break;
4959
4960	case TGT_RSP_BROADCAST:
4961	p_vci_tgt_c.cmdack = false;
4962	p_vci_tgt_c.rspval = not r_tgt_icache_req.read() and not r_tgt_dcache_req.read()
4963	and ( r_tgt_icache_rsp.read() or r_tgt_dcache_rsp.read() );
4964	p_vci_tgt_c.rsrcid = r_tgt_srcid.read();
4965	p_vci_tgt_c.rpktid = r_tgt_pktid.read();
4966	p_vci_tgt_c.rtrdid = r_tgt_trdid.read();
4967	p_vci_tgt_c.rdata = 0;
4968	p_vci_tgt_c.rerror = 0;
4969	p_vci_tgt_c.reop = true;
4970	break;
4971
4972	case TGT_RSP_ICACHE:
4973	p_vci_tgt_c.cmdack = false;
4974	p_vci_tgt_c.rspval = not r_tgt_icache_req.read() and r_tgt_icache_rsp.read();
4975	p_vci_tgt_c.rsrcid = r_tgt_srcid.read();
4976	p_vci_tgt_c.rpktid = r_tgt_pktid.read();
4977	p_vci_tgt_c.rtrdid = r_tgt_trdid.read();
4978	p_vci_tgt_c.rdata = 0;
4979	p_vci_tgt_c.rerror = 0;
4980	p_vci_tgt_c.reop = true;
4981	break;
4982
4983	case TGT_RSP_DCACHE:
4984	p_vci_tgt_c.cmdack = false;
4985	p_vci_tgt_c.rspval = not r_tgt_dcache_req.read() and r_tgt_dcache_rsp.read();
4986	p_vci_tgt_c.rsrcid = r_tgt_srcid.read();
4987	p_vci_tgt_c.rpktid = r_tgt_pktid.read();
4988	p_vci_tgt_c.rtrdid = r_tgt_trdid.read();
4989	p_vci_tgt_c.rdata = 0;
4990	p_vci_tgt_c.rerror = 0;
4991	p_vci_tgt_c.reop = true;
4992	break;
4993
4994	case TGT_REQ_BROADCAST:
4995	case TGT_REQ_ICACHE:
4996	case TGT_REQ_DCACHE:
4997	p_vci_tgt_c.cmdack = false;
4998	p_vci_tgt_c.rspval = false;
4999	break;
5000
5001	} // end switch TGT_FSM
5002	} // end genMoore
5003
5004	}}
5005
5006	// Local Variables:
5007	// tab-width: 4
5008	// c-basic-offset: 4
5009	// c-file-offsets:((innamespace . 0)(inline-open . 0))
5010	// indent-tabs-mode: nil
5011	// End:
5012
5013	// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
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