Context Navigation

source: trunk/modules/vci_cc_vcache_wrapper_v4/caba/source/src/vci_cc_vcache_wrapper_v4.cpp @ 251

Last change on this file since 251 was 251, checked in by cfuguet, 12 years ago
Add the r_tgt_dcache_rsp and r_tgt_icache_rsp in the condition to go into the IDLE state of the TGT_RSP FSM. When an inval command is received in the cache L1 and there is a miss we must not send a response on the coherence network.
File size: 189.8 KB

Line
1	/* i- c++ --C
2	* File : vci_cc_vcache_wrapper_v4.cpp
3	* Copyright (c) UPMC, Lip6, SoC
4	* Authors : Alain GREINER, Yang GAO
5	*
6	* SOCLIB_LGPL_HEADER_BEGIN
7	*
8	* This file is part of SoCLib, GNU LGPLv2.1.
9	*
10	* SoCLib is free software; you can redistribute it and/or modify it
11	* under the terms of the GNU Lesser General Public License as published
12	* by the Free Software Foundation; version 2.1 of the License.
13	*
14	* SoCLib is distributed in the hope that it will be useful, but
15	* WITHOUT ANY WARRANTY; without even the implied warranty of
16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17	* Lesser General Public License for more details.
18	*
19	* You should have received a copy of the GNU Lesser General Public
20	* License along with SoCLib; if not, write to the Free Software
21	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
22	* 02110-1301 USA
23	*
24	* SOCLIB_LGPL_HEADER_END
25	*/
26
27	#include <cassert>
28	#include "arithmetics.h"
29	#include "../include/vci_cc_vcache_wrapper_v4.h"
30
31	#define DEBUG_DCACHE 1
32	#define DEBUG_ICACHE 1
33	#define DEBUG_CLEANUP 0
34
35	namespace soclib {
36	namespace caba {
37
38	namespace {
39	const char *icache_fsm_state_str[] = {
40	"ICACHE_IDLE",
41
42	"ICACHE_XTN_TLB_FLUSH",
43	"ICACHE_XTN_CACHE_FLUSH",
44	"ICACHE_XTN_TLB_INVAL",
45	"ICACHE_XTN_CACHE_INVAL_VA",
46	"ICACHE_XTN_CACHE_INVAL_PA",
47	"ICACHE_XTN_CACHE_INVAL_GO",
48
49	"ICACHE_TLB_WAIT",
50
51	"ICACHE_MISS_VICTIM",
52	"ICACHE_MISS_INVAL",
53	"ICACHE_MISS_WAIT",
54	"ICACHE_MISS_UPDT",
55
56	"ICACHE_UNC_WAIT",
57
58	"ICACHE_CC_CHECK",
59	"ICACHE_CC_INVAL",
60	"ICACHE_CC_UPDT",
61
62	};
63	const char *dcache_fsm_state_str[] = {
64	"DCACHE_IDLE",
65
66	"DCACHE_TLB_MISS",
67	"DCACHE_TLB_PTE1_GET",
68	"DCACHE_TLB_PTE1_SELECT",
69	"DCACHE_TLB_PTE1_UPDT",
70	"DCACHE_TLB_PTE2_GET",
71	"DCACHE_TLB_PTE2_SELECT",
72	"DCACHE_TLB_PTE2_UPDT",
73	"DCACHE_TLB_LR_UPDT",
74	"DCACHE_TLB_LR_WAIT",
75	"DCACHE_TLB_RETURN",
76
77	"DCACHE_XTN_SWITCH",
78	"DCACHE_XTN_SYNC",
79	"DCACHE_XTN_IC_INVAL_VA",
80	"DCACHE_XTN_IC_FLUSH",
81	"DCACHE_XTN_IC_INVAL_PA",
82	"DCACHE_XTN_IT_INVAL",
83	"DCACHE_XTN_DC_FLUSH",
84	"DCACHE_XTN_DC_INVAL_VA",
85	"DCACHE_XTN_DC_INVAL_PA",
86	"DCACHE_XTN_DC_INVAL_END",
87	"DCACHE_XTN_DC_INVAL_GO",
88	"DCACHE_XTN_DT_INVAL",
89
90	"DCACHE_DIRTY_PTE_GET",
91	"DCACHE_DIRTY_SC_WAIT",
92
93	"DCACHE_MISS_VICTIM",
94	"DCACHE_MISS_INVAL",
95	"DCACHE_MISS_WAIT",
96	"DCACHE_MISS_UPDT",
97
98	"DCACHE_UNC_WAIT",
99	"DCACHE_SC_WAIT",
100
101	"DCACHE_CC_CHECK",
102	"DCACHE_CC_INVAL",
103	"DCACHE_CC_UPDT",
104
105	"DCACHE_INVAL_TLB_SCAN",
106	};
107	const char *cmd_fsm_state_str[] = {
108	"CMD_IDLE",
109	"CMD_INS_MISS",
110	"CMD_INS_UNC",
111	"CMD_DATA_MISS",
112	"CMD_DATA_UNC",
113	"CMD_DATA_WRITE",
114	"CMD_DATA_SC",
115	};
116	const char *rsp_fsm_state_str[] = {
117	"RSP_IDLE",
118	"RSP_INS_MISS",
119	"RSP_INS_UNC",
120	"RSP_DATA_MISS",
121	"RSP_DATA_UNC",
122	"RSP_DATA_WRITE",
123	};
124	const char *cleanup_fsm_state_str[] = {
125	"CLEANUP_DATA_IDLE",
126	"CLEANUP_DATA_GO",
127	"CLEANUP_INS_IDLE",
128	"CLEANUP_INS_GO",
129	};
130	const char *tgt_fsm_state_str[] = {
131	"TGT_IDLE",
132	"TGT_UPDT_WORD",
133	"TGT_UPDT_DATA",
134	"TGT_REQ_BROADCAST",
135	"TGT_REQ_ICACHE",
136	"TGT_REQ_DCACHE",
137	"TGT_RSP_BROADCAST",
138	"TGT_RSP_ICACHE",
139	"TGT_RSP_DCACHE",
140	};
141	}
142
143	#define tmpl(...) template<typename vci_param, typename iss_t> __VA_ARGS__ VciCcVCacheWrapperV4<vci_param, iss_t>
144
145	using soclib::common::uint32_log2;
146
147	/////////////////////////////////
148	tmpl(/**/)::VciCcVCacheWrapperV4(
149	sc_module_name name,
150	int proc_id,
151	const soclib::common::MappingTable &mtd,
152	const soclib::common::MappingTable &mtc,
153	const soclib::common::IntTab &initiator_index_d,
154	const soclib::common::IntTab &initiator_index_c,
155	const soclib::common::IntTab &target_index_c,
156	size_t itlb_ways,
157	size_t itlb_sets,
158	size_t dtlb_ways,
159	size_t dtlb_sets,
160	size_t icache_ways,
161	size_t icache_sets,
162	size_t icache_words,
163	size_t dcache_ways,
164	size_t dcache_sets,
165	size_t dcache_words,
166	size_t wbuf_nlines,
167	size_t wbuf_nwords,
168	size_t x_width,
169	size_t y_width,
170	uint32_t memory_cache_local_id,
171	uint32_t max_frozen_cycles,
172	uint32_t debug_start_cycle,
173	bool debug_ok)
174	: soclib::caba::BaseModule(name),
175
176	p_clk("clk"),
177	p_resetn("resetn"),
178	p_vci_ini_d("vci_ini_d"),
179	p_vci_ini_c("vci_ini_c"),
180	p_vci_tgt_c("vci_tgt_d"),
181
182	m_cacheability_table(mtd.getCacheabilityTable()),
183	m_segment(mtc.getSegment(target_index_c)),
184	m_srcid_d(mtd.indexForId(initiator_index_d)),
185	m_srcid_c(mtc.indexForId(initiator_index_c)),
186
187	m_itlb_ways(itlb_ways),
188	m_itlb_sets(itlb_sets),
189
190	m_dtlb_ways(dtlb_ways),
191	m_dtlb_sets(dtlb_sets),
192
193	m_icache_ways(icache_ways),
194	m_icache_sets(icache_sets),
195	m_icache_yzmask((~0)<<(uint32_log2(icache_words) + 2)),
196	m_icache_words(icache_words),
197
198	m_dcache_ways(dcache_ways),
199	m_dcache_sets(dcache_sets),
200	m_dcache_yzmask((~0)<<(uint32_log2(dcache_words) + 2)),
201	m_dcache_words(dcache_words),
202
203	m_x_width(x_width),
204	m_y_width(y_width),
205
206	m_memory_cache_local_id(memory_cache_local_id),
207
208	m_proc_id(proc_id),
209
210	m_max_frozen_cycles(max_frozen_cycles),
211
212	m_paddr_nbits(vci_param::N),
213
214	m_debug_start_cycle(debug_start_cycle),
215	m_debug_ok(debug_ok),
216
217	r_mmu_ptpr("r_mmu_ptpr"),
218	r_mmu_mode("r_mmu_mode"),
219	r_mmu_word_lo("r_mmu_word_lo"),
220	r_mmu_word_hi("r_mmu_word_hi"),
221	r_mmu_ibvar("r_mmu_ibvar"),
222	r_mmu_dbvar("r_mmu_dbvar"),
223	r_mmu_ietr("r_mmu_ietr"),
224	r_mmu_detr("r_mmu_detr"),
225
226	r_icache_fsm("r_icache_fsm"),
227	r_icache_fsm_save("r_icache_fsm_save"),
228
229	r_icache_vci_paddr("r_icache_vci_paddr"),
230	r_icache_vaddr_save("r_icache_vaddr_save"),
231
232	r_icache_miss_way("r_icache_miss_way"),
233	r_icache_miss_set("r_icache_miss_set"),
234	r_icache_miss_word("r_icache_miss_word"),
235	r_icache_miss_inval("r_icache_miss_inval"),
236
237	r_icache_cc_way("r_icache_cc_way"),
238	r_icache_cc_set("r_icache_cc_set"),
239	r_icache_cc_word("r_icache_cc_word"),
240
241	r_icache_flush_count("r_icache_flush_count"),
242
243	r_icache_miss_req("r_icache_miss_req"),
244	r_icache_unc_req("r_icache_unc_req"),
245
246	r_icache_tlb_miss_req("r_icache_tlb_read_req"),
247	r_icache_tlb_rsp_error("r_icache_tlb_rsp_error"),
248
249	r_icache_cleanup_req("r_icache_cleanup_req"),
250	r_icache_cleanup_line("r_icache_cleanup_line"),
251
252	r_dcache_fsm("r_dcache_fsm"),
253	r_dcache_fsm_cc_save("r_dcache_fsm_cc_save"),
254	r_dcache_fsm_scan_save("r_dcache_fsm_scan_save"),
255
256	r_dcache_p0_valid("r_dcache_p0_valid"),
257	r_dcache_p0_vaddr("r_dcache_p0_vaddr"),
258	r_dcache_p0_wdata("r_dcache_p0_wdata"),
259	r_dcache_p0_be("r_dcache_p0_be"),
260	r_dcache_p0_paddr("r_dcache_p0_paddr"),
261	r_dcache_p0_cacheable("r_dcache_p0_cacheable"),
262
263	r_dcache_p1_valid("r_dcache_p1_valid"),
264	r_dcache_p1_wdata("r_dcache_p1_wdata"),
265	r_dcache_p1_be("r_dcache_p1_be"),
266	r_dcache_p1_paddr("r_dcache_p1_paddr"),
267	r_dcache_p1_cache_way("r_dcache_p1_cache_way"),
268	r_dcache_p1_cache_set("r_dcache_p1_cache_set"),
269	r_dcache_p1_cache_word("r_dcache_p1_word_save"),
270
271	r_dcache_dirty_paddr("r_dcache_dirty_paddr"),
272	r_dcache_dirty_way("r_dcache_dirty_way"),
273	r_dcache_dirty_set("r_dcache_dirty_set"),
274
275	r_dcache_vci_paddr("r_dcache_vci_paddr"),
276	r_dcache_vci_miss_req("r_dcache_vci_miss_req"),
277	r_dcache_vci_unc_req("r_dcache_vci_unc_req"),
278	r_dcache_vci_unc_be("r_dcache_vci_unc_be"),
279	r_dcache_vci_sc_req("r_dcache_vci_sc_req"),
280	r_dcache_vci_sc_old("r_dcache_vci_sc_old"),
281	r_dcache_vci_sc_new("r_dcache_vci_sc_new"),
282
283	r_dcache_xtn_way("r_dcache_xtn_way"),
284	r_dcache_xtn_set("r_dcache_xtn_set"),
285
286	r_dcache_pending_unc_write("r_dcache_pending_unc_write"),
287
288	r_dcache_miss_type("r_dcache_miss_type"),
289	r_dcache_miss_word("r_dcache_miss_word"),
290	r_dcache_miss_way("r_dcache_miss_way"),
291	r_dcache_miss_set("r_dcache_miss_set"),
292	r_dcache_miss_inval("r_dcache_miss_inval"),
293
294	r_dcache_cc_way("r_dcache_cc_way"),
295	r_dcache_cc_set("r_dcache_cc_set"),
296	r_dcache_cc_word("r_dcache_cc_word"),
297
298	r_dcache_flush_count("r_dcache_flush_count"),
299
300	r_dcache_tlb_vaddr("r_dcache_tlb_vaddr"),
301	r_dcache_tlb_ins("r_dcache_tlb_ins"),
302	r_dcache_tlb_pte_flags("r_dcache_tlb_pte_flags"),
303	r_dcache_tlb_pte_ppn("r_dcache_tlb_pte_ppn"),
304	r_dcache_tlb_cache_way("r_dcache_tlb_cache_way"),
305	r_dcache_tlb_cache_set("r_dcache_tlb_cache_set"),
306	r_dcache_tlb_cache_word("r_dcache_tlb_cache_word"),
307	r_dcache_tlb_way("r_dcache_tlb_way"),
308	r_dcache_tlb_set("r_dcache_tlb_set"),
309
310	r_dcache_ll_valid("r_dcache_ll_valid"),
311	r_dcache_ll_data("r_dcache_ll_data"),
312	r_dcache_ll_vaddr("r_dcache_ll_vaddr"),
313
314	r_dcache_tlb_inval_line("r_dcache_tlb_inval_line"),
315	r_dcache_tlb_inval_count("r_dcache_tlb_inval_count"),
316
317	r_dcache_xtn_req("r_dcache_xtn_req"),
318	r_dcache_xtn_opcode("r_dcache_xtn_opcode"),
319
320	r_dcache_cleanup_req("r_dcache_cleanup_req"),
321	r_dcache_cleanup_line("r_dcache_cleanup_line"),
322
323	r_vci_cmd_fsm("r_vci_cmd_fsm"),
324	r_vci_cmd_min("r_vci_cmd_min"),
325	r_vci_cmd_max("r_vci_cmd_max"),
326	r_vci_cmd_cpt("r_vci_cmd_cpt"),
327	r_vci_cmd_imiss_prio("r_vci_cmd_imiss_prio"),
328
329	r_vci_rsp_fsm("r_vci_rsp_fsm"),
330	r_vci_rsp_cpt("r_vci_rsp_cpt"),
331	r_vci_rsp_ins_error("r_vci_rsp_ins_error"),
332	r_vci_rsp_data_error("r_vci_rsp_data_error"),
333	r_vci_rsp_fifo_icache("r_vci_rsp_fifo_icache", 2), // 2 words depth
334	r_vci_rsp_fifo_dcache("r_vci_rsp_fifo_dcache", 2), // 2 words depth
335
336	r_cleanup_fsm("r_cleanup_fsm"),
337	r_cleanup_trdid("r_cleanup_trdid"),
338	r_cleanup_buffer(4), // up to 4 simultaneous cleanups
339
340	r_tgt_fsm("r_tgt_fsm"),
341	r_tgt_paddr("r_tgt_paddr"),
342	r_tgt_word_count("r_tgt_word_count"),
343	r_tgt_word_min("r_tgt_word_min"),
344	r_tgt_word_max("r_tgt_word_max"),
345	r_tgt_update("r_tgt_update"),
346	r_tgt_update_data("r_tgt_update_data"),
347	r_tgt_srcid("r_tgt_srcid"),
348	r_tgt_pktid("r_tgt_pktid"),
349	r_tgt_trdid("r_tgt_trdid"),
350
351	r_tgt_icache_req("r_tgt_icache_req"),
352	r_tgt_dcache_req("r_tgt_dcache_req"),
353	r_tgt_icache_rsp("r_tgt_icache_rsp"),
354	r_tgt_dcache_rsp("r_tgt_dcache_rsp"),
355
356	r_iss(this->name(), proc_id),
357	r_wbuf("wbuf", wbuf_nwords, wbuf_nlines, dcache_words ),
358	r_icache("icache", icache_ways, icache_sets, icache_words),
359	r_dcache("dcache", dcache_ways, dcache_sets, dcache_words),
360	r_itlb("itlb", proc_id, itlb_ways,itlb_sets,vci_param::N),
361	r_dtlb("dtlb", proc_id, dtlb_ways,dtlb_sets,vci_param::N)
362	{
363	assert( ((icache_words*vci_param::B) < (1<<vci_param::K)) and
364	"Need more PLEN bits.");
365
366	assert( (vci_param::T > 2) and ((1<<(vci_param::T-1)) >= (wbuf_nlines)) and
367	"Need more TRDID bits.");
368
369	assert( (icache_words == dcache_words) and
370	"icache_words and dcache_words parameters must be equal");
371
372	assert( (itlb_sets == dtlb_sets) and
373	"itlb_sets and dtlb_sets parameters must be etqual");
374
375	assert( (itlb_ways == dtlb_ways) and
376	"itlb_ways and dtlb_ways parameters must be etqual");
377
378	r_mmu_params = (uint32_log2(m_dtlb_ways) << 29) \| (uint32_log2(m_dtlb_sets) << 25) \|
379	(uint32_log2(m_dcache_ways) << 22) \| (uint32_log2(m_dcache_sets) << 18) \|
380	(uint32_log2(m_itlb_ways) << 15) \| (uint32_log2(m_itlb_sets) << 11) \|
381	(uint32_log2(m_icache_ways) << 8) \| (uint32_log2(m_icache_sets) << 4) \|
382	(uint32_log2(m_icache_words<<2));
383
384	r_mmu_release = (uint32_t)(1 << 16) \| 0x1;
385
386	r_tgt_buf = new uint32_t[dcache_words];
387	r_tgt_be = new vci_be_t[dcache_words];
388	r_dcache_in_tlb = new bool[dcache_ways*dcache_sets];
389	r_dcache_contains_ptd = new bool[dcache_ways*dcache_sets];
390
391	SC_METHOD(transition);
392	dont_initialize();
393	sensitive << p_clk.pos();
394
395	SC_METHOD(genMoore);
396	dont_initialize();
397	sensitive << p_clk.neg();
398
399	typename iss_t::CacheInfo cache_info;
400	cache_info.has_mmu = true;
401	cache_info.icache_line_size = icache_words*sizeof(uint32_t);
402	cache_info.icache_assoc = icache_ways;
403	cache_info.icache_n_lines = icache_sets;
404	cache_info.dcache_line_size = dcache_words*sizeof(uint32_t);
405	cache_info.dcache_assoc = dcache_ways;
406	cache_info.dcache_n_lines = dcache_sets;
407	r_iss.setCacheInfo(cache_info);
408	}
409
410	/////////////////////////////////////
411	tmpl(/**/)::~VciCcVCacheWrapperV4()
412	/////////////////////////////////////
413	{
414	delete [] r_tgt_be;
415	delete [] r_tgt_buf;
416	delete [] r_dcache_in_tlb;
417	delete [] r_dcache_contains_ptd;
418	}
419
420	////////////////////////
421	tmpl(void)::print_cpi()
422	////////////////////////
423	{
424	std::cout << name() << " CPI = "
425	<< (float)m_cpt_total_cycles/(m_cpt_total_cycles - m_cpt_frz_cycles) << std::endl ;
426	}
427
428	////////////////////////////////////
429	tmpl(void)::print_trace(size_t mode)
430	////////////////////////////////////
431	{
432	// b0 : write buffer trace
433	// b1 : write buffer verbose
434	// b2 : dcache trace
435	// b3 : icache trace
436	// b4 : dtlb trace
437	// b5 : itlb trace
438
439	std::cout << std::dec << "PROC " << name() << std::endl;
440
441	std::cout << " " << m_ireq << std::endl;
442	std::cout << " " << m_irsp << std::endl;
443	std::cout << " " << m_dreq << std::endl;
444	std::cout << " " << m_drsp << std::endl;
445
446	std::cout << " " << icache_fsm_state_str[r_icache_fsm.read()]
447	<< " \| " << dcache_fsm_state_str[r_dcache_fsm.read()]
448	<< " \| " << cmd_fsm_state_str[r_vci_cmd_fsm.read()]
449	<< " \| " << rsp_fsm_state_str[r_vci_rsp_fsm.read()]
450	<< " \| " << tgt_fsm_state_str[r_tgt_fsm.read()]
451	<< " \| " << cleanup_fsm_state_str[r_cleanup_fsm.read()];
452	if (r_dcache_p0_valid.read() ) std::cout << " \| P1_WRITE";
453	if (r_dcache_p1_valid.read() ) std::cout << " \| P2_WRITE";
454	std::cout << std::endl;
455
456	if(mode & 0x01)
457	{
458	r_wbuf.printTrace((mode>>1)&1);
459	}
460	if(mode & 0x04)
461	{
462	std::cout << " Data Cache" << std::endl;
463	r_dcache.printTrace();
464	}
465	if(mode & 0x08)
466	{
467	std::cout << " Instruction Cache" << std::endl;
468	r_icache.printTrace();
469	}
470	if(mode & 0x10)
471	{
472	std::cout << " Data TLB" << std::endl;
473	r_dtlb.printTrace();
474	}
475	if(mode & 0x20)
476	{
477	std::cout << " Instruction TLB" << std::endl;
478	r_itlb.printTrace();
479	}
480	}
481
482	//////////////////////////////////////////
483	tmpl(void)::cache_monitor( paddr_t addr )
484	//////////////////////////////////////////
485	{
486	size_t cache_way;
487	size_t cache_set;
488	size_t cache_word;
489	uint32_t cache_rdata;
490	bool cache_hit = r_dcache.read_neutral( addr,
491	&cache_rdata,
492	&cache_way,
493	&cache_set,
494	&cache_word );
495	bool icache_hit = r_icache.read_neutral( addr,
496	&cache_rdata,
497	&cache_way,
498	&cache_set,
499	&cache_word );
500	if ( cache_hit != m_debug_previous_hit )
501	{
502	std::cout << "PROC " << name()
503	<< " dcache change at cycle " << std::dec << m_cpt_total_cycles
504	<< " for adresse " << std::hex << addr
505	<< " / HIT = " << std::dec << cache_hit << std::endl;
506	m_debug_previous_hit = cache_hit;
507	}
508	if ( icache_hit != m_idebug_previous_hit )
509	{
510	std::cout << "PROC " << name()
511	<< " icache change at cycle " << std::dec << m_cpt_total_cycles
512	<< " for adresse " << std::hex << addr
513	<< " / HIT = " << icache_hit << std::endl;
514	m_idebug_previous_hit = icache_hit;
515	}
516	}
517
518	/*
519	////////////////////////
520	tmpl(void)::print_stats()
521	////////////////////////
522	{
523	float run_cycles = (float)(m_cpt_total_cycles - m_cpt_frz_cycles);
524	std::cout << name() << std::endl
525	<< "- CPI = " << (float)m_cpt_total_cycles/run_cycles << std::endl
526	<< "- READ RATE = " << (float)m_cpt_read/run_cycles << std::endl
527	<< "- WRITE RATE = " << (float)m_cpt_write/run_cycles << std::endl
528	<< "- IMISS_RATE = " << (float)m_cpt_ins_miss/m_cpt_ins_read << std::endl
529	<< "- DMISS RATE = " << (float)m_cpt_data_miss/(m_cpt_read-m_cpt_unc_read) << std::endl
530	<< "- INS MISS COST = " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl
531	<< "- DATA MISS COST = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl
532	<< "- WRITE COST = " << (float)m_cost_write_frz/m_cpt_write << std::endl
533	<< "- UNC COST = " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl
534	<< "- UNCACHED READ RATE = " << (float)m_cpt_unc_read/m_cpt_read << std::endl
535	<< "- CACHED WRITE RATE = " << (float)m_cpt_write_cached/m_cpt_write << std::endl
536	<< "- INS TLB MISS RATE = " << (float)m_cpt_ins_tlb_miss/m_cpt_ins_tlb_read << std::endl
537	<< "- DATA TLB MISS RATE = " << (float)m_cpt_data_tlb_miss/m_cpt_data_tlb_read << std::endl
538	<< "- ITLB MISS COST = " << (float)m_cost_ins_tlb_miss_frz/m_cpt_ins_tlb_miss << std::endl
539	<< "- DTLB MISS COST = " << (float)m_cost_data_tlb_miss_frz/m_cpt_data_tlb_miss << std::endl
540	<< "- ITLB UPDATE ACC COST = " << (float)m_cost_ins_tlb_update_acc_frz/m_cpt_ins_tlb_update_acc << std::endl
541	<< "- DTLB UPDATE ACC COST = " << (float)m_cost_data_tlb_update_acc_frz/m_cpt_data_tlb_update_acc << std::endl
542	<< "- DTLB UPDATE DIRTY COST = " << (float)m_cost_data_tlb_update_dirty_frz/m_cpt_data_tlb_update_dirty << std::endl
543	<< "- ITLB HIT IN DCACHE RATE= " << (float)m_cpt_ins_tlb_hit_dcache/m_cpt_ins_tlb_miss << std::endl
544	<< "- DTLB HIT IN DCACHE RATE= " << (float)m_cpt_data_tlb_hit_dcache/m_cpt_data_tlb_miss << std::endl
545	<< "- DCACHE FROZEN BY ITLB = " << (float)m_cost_ins_tlb_occup_cache_frz/m_cpt_dcache_frz_cycles << std::endl
546	<< "- DCACHE FOR TLB % = " << (float)m_cpt_tlb_occup_dcache/(m_dcache_ways*m_dcache_sets) << std::endl
547	<< "- NB CC BROADCAST = " << m_cpt_cc_broadcast << std::endl
548	<< "- NB CC UPDATE DATA = " << m_cpt_cc_update_data << std::endl
549	<< "- NB CC INVAL DATA = " << m_cpt_cc_inval_data << std::endl
550	<< "- NB CC INVAL INS = " << m_cpt_cc_inval_ins << std::endl
551	<< "- CC BROADCAST COST = " << (float)m_cost_broadcast_frz/m_cpt_cc_broadcast << std::endl
552	<< "- CC UPDATE DATA COST = " << (float)m_cost_updt_data_frz/m_cpt_cc_update_data << std::endl
553	<< "- CC INVAL DATA COST = " << (float)m_cost_inval_data_frz/m_cpt_cc_inval_data << std::endl
554	<< "- CC INVAL INS COST = " << (float)m_cost_inval_ins_frz/m_cpt_cc_inval_ins << std::endl
555	<< "- NB CC CLEANUP DATA = " << m_cpt_cc_cleanup_data << std::endl
556	<< "- NB CC CLEANUP INS = " << m_cpt_cc_cleanup_ins << std::endl
557	<< "- IMISS TRANSACTION = " << (float)m_cost_imiss_transaction/m_cpt_imiss_transaction << std::endl
558	<< "- DMISS TRANSACTION = " << (float)m_cost_dmiss_transaction/m_cpt_dmiss_transaction << std::endl
559	<< "- UNC TRANSACTION = " << (float)m_cost_unc_transaction/m_cpt_unc_transaction << std::endl
560	<< "- WRITE TRANSACTION = " << (float)m_cost_write_transaction/m_cpt_write_transaction << std::endl
561	<< "- WRITE LENGTH = " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl
562	<< "- ITLB MISS TRANSACTION = " << (float)m_cost_itlbmiss_transaction/m_cpt_itlbmiss_transaction << std::endl
563	<< "- DTLB MISS TRANSACTION = " << (float)m_cost_dtlbmiss_transaction/m_cpt_dtlbmiss_transaction << std::endl;
564	}
565
566	////////////////////////
567	tmpl(void)::clear_stats()
568	////////////////////////
569	{
570	m_cpt_dcache_data_read = 0;
571	m_cpt_dcache_data_write = 0;
572	m_cpt_dcache_dir_read = 0;
573	m_cpt_dcache_dir_write = 0;
574	m_cpt_icache_data_read = 0;
575	m_cpt_icache_data_write = 0;
576	m_cpt_icache_dir_read = 0;
577	m_cpt_icache_dir_write = 0;
578
579	m_cpt_frz_cycles = 0;
580	m_cpt_dcache_frz_cycles = 0;
581	m_cpt_total_cycles = 0;
582
583	m_cpt_read = 0;
584	m_cpt_write = 0;
585	m_cpt_data_miss = 0;
586	m_cpt_ins_miss = 0;
587	m_cpt_unc_read = 0;
588	m_cpt_write_cached = 0;
589	m_cpt_ins_read = 0;
590
591	m_cost_write_frz = 0;
592	m_cost_data_miss_frz = 0;
593	m_cost_unc_read_frz = 0;
594	m_cost_ins_miss_frz = 0;
595
596	m_cpt_imiss_transaction = 0;
597	m_cpt_dmiss_transaction = 0;
598	m_cpt_unc_transaction = 0;
599	m_cpt_write_transaction = 0;
600	m_cpt_icache_unc_transaction = 0;
601
602	m_cost_imiss_transaction = 0;
603	m_cost_dmiss_transaction = 0;
604	m_cost_unc_transaction = 0;
605	m_cost_write_transaction = 0;
606	m_cost_icache_unc_transaction = 0;
607	m_length_write_transaction = 0;
608
609	m_cpt_ins_tlb_read = 0;
610	m_cpt_ins_tlb_miss = 0;
611	m_cpt_ins_tlb_update_acc = 0;
612
613	m_cpt_data_tlb_read = 0;
614	m_cpt_data_tlb_miss = 0;
615	m_cpt_data_tlb_update_acc = 0;
616	m_cpt_data_tlb_update_dirty = 0;
617	m_cpt_ins_tlb_hit_dcache = 0;
618	m_cpt_data_tlb_hit_dcache = 0;
619	m_cpt_ins_tlb_occup_cache = 0;
620	m_cpt_data_tlb_occup_cache = 0;
621
622	m_cost_ins_tlb_miss_frz = 0;
623	m_cost_data_tlb_miss_frz = 0;
624	m_cost_ins_tlb_update_acc_frz = 0;
625	m_cost_data_tlb_update_acc_frz = 0;
626	m_cost_data_tlb_update_dirty_frz = 0;
627	m_cost_ins_tlb_occup_cache_frz = 0;
628	m_cost_data_tlb_occup_cache_frz = 0;
629
630	m_cpt_itlbmiss_transaction = 0;
631	m_cpt_itlb_ll_transaction = 0;
632	m_cpt_itlb_sc_transaction = 0;
633	m_cpt_dtlbmiss_transaction = 0;
634	m_cpt_dtlb_ll_transaction = 0;
635	m_cpt_dtlb_sc_transaction = 0;
636	m_cpt_dtlb_ll_dirty_transaction = 0;
637	m_cpt_dtlb_sc_dirty_transaction = 0;
638
639	m_cost_itlbmiss_transaction = 0;
640	m_cost_itlb_ll_transaction = 0;
641	m_cost_itlb_sc_transaction = 0;
642	m_cost_dtlbmiss_transaction = 0;
643	m_cost_dtlb_ll_transaction = 0;
644	m_cost_dtlb_sc_transaction = 0;
645	m_cost_dtlb_ll_dirty_transaction = 0;
646	m_cost_dtlb_sc_dirty_transaction = 0;
647
648	m_cpt_cc_update_data = 0;
649	m_cpt_cc_inval_ins = 0;
650	m_cpt_cc_inval_data = 0;
651	m_cpt_cc_broadcast = 0;
652
653	m_cost_updt_data_frz = 0;
654	m_cost_inval_ins_frz = 0;
655	m_cost_inval_data_frz = 0;
656	m_cost_broadcast_frz = 0;
657
658	m_cpt_cc_cleanup_data = 0;
659	m_cpt_cc_cleanup_ins = 0;
660	}
661
662	*/
663
664	/////////////////////////
665	tmpl(void)::transition()
666	/////////////////////////
667	{
668	if ( not p_resetn.read() )
669	{
670	r_iss.reset();
671	r_wbuf.reset();
672	r_icache.reset();
673	r_dcache.reset();
674	r_itlb.reset();
675	r_dtlb.reset();
676
677	r_dcache_fsm = DCACHE_IDLE;
678	r_icache_fsm = ICACHE_IDLE;
679	r_vci_cmd_fsm = CMD_IDLE;
680	r_vci_rsp_fsm = RSP_IDLE;
681	r_tgt_fsm = TGT_IDLE;
682	r_cleanup_fsm = CLEANUP_DATA_IDLE;
683
684	// reset dcache directory extension
685	for (size_t i=0 ; i< m_dcache_ways*m_dcache_sets ; i++)
686	{
687	r_dcache_in_tlb[i] = false;
688	r_dcache_contains_ptd[i] = false;
689	}
690
691	// Response FIFOs and cleanup buffer
692	r_vci_rsp_fifo_icache.init();
693	r_vci_rsp_fifo_dcache.init();
694	r_cleanup_buffer.reset();
695
696	// ICACHE & DCACHE activated
697	r_mmu_mode = 0x3;
698
699	// No request from ICACHE FSM to CMD FSM
700	r_icache_miss_req = false;
701	r_icache_unc_req = false;
702
703	// No request from ICACHE_FSM to DCACHE FSM
704	r_icache_tlb_miss_req = false;
705
706	// No request from ICACHE_FSM to CLEANUP FSMs
707	r_icache_cleanup_req = false;
708
709	// No pending write in pipeline
710	r_dcache_p0_valid = false;
711	r_dcache_p1_valid = false;
712
713	// No request from DCACHE_FSM to CMD_FSM
714	r_dcache_vci_miss_req = false;
715	r_dcache_vci_unc_req = false;
716	r_dcache_vci_sc_req = false;
717
718	// No uncacheable write pending
719	r_dcache_pending_unc_write = false;
720
721	// No LL reservation
722	r_dcache_ll_valid = false;
723
724	// No processor XTN request pending
725	r_dcache_xtn_req = false;
726
727	// No request from DCACHE FSM to CLEANUP FSMs
728	r_dcache_cleanup_req = false;
729
730	// No request from TGT FSM to ICACHE/DCACHE FSMs
731	r_tgt_icache_req = false;
732	r_tgt_dcache_req = false;
733
734	// No signalisation of a coherence request matching a pending miss
735	r_icache_miss_inval = false;
736	r_dcache_miss_inval = false;
737
738	// No signalisation of errors
739	r_vci_rsp_ins_error = false;
740	r_vci_rsp_data_error = false;
741
742	// Debug variables
743	m_debug_previous_hit = false;
744	m_idebug_previous_hit = false;
745	m_debug_dcache_fsm = false;
746	m_debug_icache_fsm = false;
747	m_debug_cleanup_fsm = false;
748
749	// activity counters
750	m_cpt_dcache_data_read = 0;
751	m_cpt_dcache_data_write = 0;
752	m_cpt_dcache_dir_read = 0;
753	m_cpt_dcache_dir_write = 0;
754	m_cpt_icache_data_read = 0;
755	m_cpt_icache_data_write = 0;
756	m_cpt_icache_dir_read = 0;
757	m_cpt_icache_dir_write = 0;
758
759	m_cpt_frz_cycles = 0;
760	m_cpt_total_cycles = 0;
761	m_cpt_stop_simulation = 0;
762
763	m_cpt_data_miss = 0;
764	m_cpt_ins_miss = 0;
765	m_cpt_unc_read = 0;
766	m_cpt_write_cached = 0;
767	m_cpt_ins_read = 0;
768
769	m_cost_write_frz = 0;
770	m_cost_data_miss_frz = 0;
771	m_cost_unc_read_frz = 0;
772	m_cost_ins_miss_frz = 0;
773
774	m_cpt_imiss_transaction = 0;
775	m_cpt_dmiss_transaction = 0;
776	m_cpt_unc_transaction = 0;
777	m_cpt_write_transaction = 0;
778	m_cpt_icache_unc_transaction = 0;
779
780	m_cost_imiss_transaction = 0;
781	m_cost_dmiss_transaction = 0;
782	m_cost_unc_transaction = 0;
783	m_cost_write_transaction = 0;
784	m_cost_icache_unc_transaction = 0;
785	m_length_write_transaction = 0;
786
787	m_cpt_ins_tlb_read = 0;
788	m_cpt_ins_tlb_miss = 0;
789	m_cpt_ins_tlb_update_acc = 0;
790
791	m_cpt_data_tlb_read = 0;
792	m_cpt_data_tlb_miss = 0;
793	m_cpt_data_tlb_update_acc = 0;
794	m_cpt_data_tlb_update_dirty = 0;
795	m_cpt_ins_tlb_hit_dcache = 0;
796	m_cpt_data_tlb_hit_dcache = 0;
797	m_cpt_ins_tlb_occup_cache = 0;
798	m_cpt_data_tlb_occup_cache = 0;
799
800	m_cost_ins_tlb_miss_frz = 0;
801	m_cost_data_tlb_miss_frz = 0;
802	m_cost_ins_tlb_update_acc_frz = 0;
803	m_cost_data_tlb_update_acc_frz = 0;
804	m_cost_data_tlb_update_dirty_frz = 0;
805	m_cost_ins_tlb_occup_cache_frz = 0;
806	m_cost_data_tlb_occup_cache_frz = 0;
807
808	m_cpt_ins_tlb_inval = 0;
809	m_cpt_data_tlb_inval = 0;
810	m_cost_ins_tlb_inval_frz = 0;
811	m_cost_data_tlb_inval_frz = 0;
812
813	m_cpt_cc_broadcast = 0;
814
815	m_cost_updt_data_frz = 0;
816	m_cost_inval_ins_frz = 0;
817	m_cost_inval_data_frz = 0;
818	m_cost_broadcast_frz = 0;
819
820	m_cpt_cc_cleanup_data = 0;
821	m_cpt_cc_cleanup_ins = 0;
822
823	m_cpt_itlbmiss_transaction = 0;
824	m_cpt_itlb_ll_transaction = 0;
825	m_cpt_itlb_sc_transaction = 0;
826	m_cpt_dtlbmiss_transaction = 0;
827	m_cpt_dtlb_ll_transaction = 0;
828	m_cpt_dtlb_sc_transaction = 0;
829	m_cpt_dtlb_ll_dirty_transaction = 0;
830	m_cpt_dtlb_sc_dirty_transaction = 0;
831
832	m_cost_itlbmiss_transaction = 0;
833	m_cost_itlb_ll_transaction = 0;
834	m_cost_itlb_sc_transaction = 0;
835	m_cost_dtlbmiss_transaction = 0;
836	m_cost_dtlb_ll_transaction = 0;
837	m_cost_dtlb_sc_transaction = 0;
838	m_cost_dtlb_ll_dirty_transaction = 0;
839	m_cost_dtlb_sc_dirty_transaction = 0;
840	/*
841	m_cpt_dcache_frz_cycles = 0;
842	m_cpt_read = 0;
843	m_cpt_write = 0;
844	m_cpt_cc_update_data = 0;
845	m_cpt_cc_inval_ins = 0;
846	m_cpt_cc_inval_data = 0;
847	*/
848
849	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_icache [i] = 0;
850	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_dcache [i] = 0;
851	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_cmd [i] = 0;
852	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_rsp [i] = 0;
853	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_tgt [i] = 0;
854	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_cmd_cleanup [i] = 0;
855	for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_rsp_cleanup [i] = 0;
856
857	return;
858	}
859
860	// Response FIFOs default values
861	bool vci_rsp_fifo_icache_get = false;
862	bool vci_rsp_fifo_icache_put = false;
863	uint32_t vci_rsp_fifo_icache_data = 0;
864
865	bool vci_rsp_fifo_dcache_get = false;
866	bool vci_rsp_fifo_dcache_put = false;
867	uint32_t vci_rsp_fifo_dcache_data = 0;
868
869	#ifdef INSTRUMENTATION
870	m_cpt_fsm_dcache [r_dcache_fsm.read() ] ++;
871	m_cpt_fsm_icache [r_icache_fsm.read() ] ++;
872	m_cpt_fsm_cmd [r_vci_cmd_fsm.read()] ++;
873	m_cpt_fsm_rsp [r_vci_rsp_fsm.read()] ++;
874	m_cpt_fsm_tgt [r_tgt_fsm.read() ] ++;
875	m_cpt_fsm_cleanup [r_cleanup_fsm.read()] ++;
876	#endif
877
878	m_cpt_total_cycles++;
879
880	m_debug_cleanup_fsm = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok;
881	m_debug_icache_fsm = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok;
882	m_debug_dcache_fsm = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok;
883
884	/////////////////////////////////////////////////////////////////////
885	// The TGT_FSM controls the following ressources:
886	// - r_tgt_fsm
887	// - r_tgt_buf[nwords]
888	// - r_tgt_be[nwords]
889	// - r_tgt_update
890	// - r_tgt_word_min
891	// - r_tgt_word_max
892	// - r_tgt_word_count
893	// - r_tgt_paddr
894	// - r_tgt_srcid
895	// - r_tgt_trdid
896	// - r_tgt_pktid
897	// - r_tgt_icache_req (set)
898	// - r_tgt_dcache_req (set)
899	//
900	// All VCI commands must be CMD_WRITE.
901	// - If the 2 LSB bits of the VCI address are 11, it is a broadcast request.
902	// It is a multicast request otherwise.
903	// - For multicast requests, the ADDRESS[2] bit distinguishes DATA/INS
904	// (0 for data / 1 for instruction), and the ADDRESS[3] bit distinguishes
905	// INVAL/UPDATE (0 for invalidate / 1 for UPDATE).
906	//
907	// For all types of coherence request, the line index (i.e. the Z & Y fields)
908	// is coded on 34 bits, and is contained in the WDATA and BE fields
909	// of the first VCI flit.
910	// - for a multicast invalidate or for a broadcast invalidate request
911	// the VCI packet length is 1 word.
912	// - for an update request the VCI packet length is (n+2) words.
913	// The WDATA field of the second VCI word contains the word index.
914	// The WDATA field of the n following words contains the values.
915	// - for all transaction types, the VCI response is one single word.
916	// In case of errors in the VCI command packet, the simulation
917	// is stopped with an error message.
918	//
919	// This FSM is NOT pipelined : It consumes a new coherence request
920	// on the VCI port only when the previous request is completed.
921	//
922	// The VCI_TGT FSM stores the external request arguments in the
923	// IDLE, UPDT_WORD & UPDT_DATA states. It sets the r_tgt_icache_req
924	// and/or the r_tgt_dcache_req flip-flops to signal the coherence request
925	// to the ICACHE & DCACHE FSMs in the REQ_ICACHE, REQ_DCACHE & REQ_BROADCAST
926	// states. It waits the completion of the coherence request by polling the
927	// r_tgt_*cache_req flip-flops in the RSP_ICACHE, RSP_DCACHE & RSP_BROADCAST
928	// states. These flip-flops are reset by the ICACHE and DCACHE FSMs.
929	// These two FSMs signal if a VCI answer must be send by setting
930	// the r_tgt_icache_rsp and/or the r_tgt_dcache_rsp flip_flops.
931	///////////////////////////////////////////////////////////////////////////////
932
933	switch( r_tgt_fsm.read() )
934	{
935	//////////////
936	case TGT_IDLE:
937	{
938	if ( p_vci_tgt_c.cmdval.read() )
939	{
940	paddr_t address = p_vci_tgt_c.address.read();
941
942	// command checking
943	if ( p_vci_tgt_c.cmd.read() != vci_param::CMD_WRITE)
944	{
945	std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
946	std::cout << "the received VCI coherence command is not a write" << std::endl;
947	exit(0);
948	}
949
950	// address checking
951	if ( ( (address & 0x3) != 0x3 ) && ( not m_segment.contains(address)) )
952	{
953	std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
954	std::cout << "out of segment VCI coherence command received" << std::endl;
955	exit(0);
956	}
957
958	r_tgt_srcid = p_vci_tgt_c.srcid.read();
959	r_tgt_trdid = p_vci_tgt_c.trdid.read();
960	r_tgt_pktid = p_vci_tgt_c.pktid.read();
961
962	if (sizeof(paddr_t) <= 32) {
963	assert(p_vci_tgt_c.be.read() == 0 && "byte enable should be 0 for 32bits paddr");
964	r_tgt_paddr =
965	(paddr_t)p_vci_tgt_c.wdata.read() * m_dcache_words * 4;
966	} else {
967	r_tgt_paddr = (paddr_t)(p_vci_tgt_c.be.read() & 0x3) << 32 \|
968	(paddr_t)p_vci_tgt_c.wdata.read() * m_dcache_words * 4;
969	}
970
971	if ( (address&0x3) == 0x3 ) // broadcast invalidate for data or instruction type
972	{
973	if ( not p_vci_tgt_c.eop.read() )
974	{
975	std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
976	std::cout << "the BROADCAST INVALIDATE command must be one flit" << std::endl;
977	exit(0);
978	}
979	r_tgt_update = false;
980	r_tgt_fsm = TGT_REQ_BROADCAST;
981
982	#ifdef INSTRUMENTATION
983	m_cpt_cc_broadcast++;
984	#endif
985	}
986	else // multi-update or multi-invalidate for data type
987	{
988	paddr_t cell = address - m_segment.baseAddress();
989
990	if (cell == 0) // invalidate data
991	{
992	if ( not p_vci_tgt_c.eop.read() )
993	{
994	std::cout << "error in VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
995	std::cout << "the MULTI-INVALIDATE command must be one flit" << std::endl;
996	exit(0);
997	}
998	r_tgt_update = false;
999	r_tgt_fsm = TGT_REQ_DCACHE;
1000
1001	#ifdef INSTRUMENTATION
1002	m_cpt_cc_inval_dcache++;
1003	#endif
1004	}
1005	else if (cell == 4) // invalidate instruction
1006	{
1007	if ( not p_vci_tgt_c.eop.read() )
1008	{
1009	std::cout << "error in VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
1010	std::cout << "the MULTI-INVALIDATE command must be one flit" << std::endl;
1011	exit(0);
1012	}
1013	r_tgt_update = false;
1014	r_tgt_fsm = TGT_REQ_ICACHE;
1015
1016	#ifdef INSTRUMENTATION
1017	m_cpt_cc_inval_icache++;
1018	#endif
1019	}
1020	else if (cell == 8) // update data
1021	{
1022	if ( p_vci_tgt_c.eop.read() )
1023	{
1024	std::cout << "error in VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
1025	std::cout << "the MULTI-UPDATE command must be N+2 flits" << std::endl;
1026	exit(0);
1027	}
1028	r_tgt_update = true;
1029	r_tgt_update_data = true;
1030	r_tgt_fsm = TGT_UPDT_WORD;
1031
1032	#ifdef INSTRUMENTATION
1033	m_cpt_cc_update_dcache++;
1034	#endif
1035	}
1036	else // update instruction
1037	{
1038	if ( p_vci_tgt_c.eop.read() )
1039	{
1040	std::cout << "error in VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
1041	std::cout << "the MULTI-UPDATE command must be N+2 flits" << std::endl;
1042	exit(0);
1043	}
1044	r_tgt_update = true;
1045	r_tgt_update_data = false;
1046	r_tgt_fsm = TGT_UPDT_WORD;
1047
1048	#ifdef INSTRUMENTATION
1049	m_cpt_cc_update_icache++;
1050	#endif
1051	}
1052	} // end if multi
1053	} // end if cmdval
1054	break;
1055	}
1056	///////////////////
1057	case TGT_UPDT_WORD: // first word index acquisition
1058	{
1059	if (p_vci_tgt_c.cmdval.read())
1060	{
1061	if ( p_vci_tgt_c.eop.read() )
1062	{
1063	std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
1064	std::cout << "the MULTI-UPDATE command must be N+2 flits" << std::endl;
1065	exit(0);
1066	}
1067	for ( size_t i=0 ; i<m_dcache_words ; i++ ) r_tgt_be[i] = false;
1068
1069	r_tgt_word_min = p_vci_tgt_c.wdata.read(); // first modifid word index
1070	r_tgt_word_count = p_vci_tgt_c.wdata.read(); // initializing word index
1071	r_tgt_fsm = TGT_UPDT_DATA;
1072	}
1073	break;
1074	}
1075	///////////////////
1076	case TGT_UPDT_DATA:
1077	{
1078	if (p_vci_tgt_c.cmdval.read())
1079	{
1080	size_t word = r_tgt_word_count.read();
1081	if (word >= m_dcache_words)
1082	{
1083	std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
1084	std::cout << "the reveived MULTI-UPDATE command is wrong" << std::endl;
1085	exit(0);
1086	}
1087	r_tgt_buf[word] = p_vci_tgt_c.wdata.read();
1088	r_tgt_be[word] = p_vci_tgt_c.be.read();
1089	r_tgt_word_count = word + 1;
1090
1091	if (p_vci_tgt_c.eop.read()) // last word
1092	{
1093	r_tgt_word_max = word;
1094	if ( r_tgt_update_data.read() ) r_tgt_fsm = TGT_REQ_DCACHE;
1095	else r_tgt_fsm = TGT_REQ_ICACHE;
1096	}
1097	}
1098	break;
1099	}
1100	///////////////////////
1101	case TGT_REQ_BROADCAST: // set requests to DCACHE & ICACHE FSMs
1102	{
1103	if ( not r_tgt_icache_req.read() and not r_tgt_dcache_req.read() )
1104	{
1105	r_tgt_fsm = TGT_RSP_BROADCAST;
1106	r_tgt_icache_req = true;
1107	r_tgt_dcache_req = true;
1108	}
1109	break;
1110	}
1111	/////////////////////
1112	case TGT_REQ_ICACHE: // set request to ICACHE FSM (if no previous request pending)
1113	{
1114	if ( not r_tgt_icache_req.read() )
1115	{
1116	r_tgt_fsm = TGT_RSP_ICACHE;
1117	r_tgt_icache_req = true;
1118	}
1119	break;
1120	}
1121	////////////////////
1122	case TGT_REQ_DCACHE: // set request to DCACHE FSM (if no previous request pending)
1123	{
1124	if ( not r_tgt_dcache_req.read() )
1125	{
1126	r_tgt_fsm = TGT_RSP_DCACHE;
1127	r_tgt_dcache_req = true;
1128	}
1129	break;
1130	}
1131	///////////////////////
1132	case TGT_RSP_BROADCAST: // waiting acknowledge from both DCACHE & ICACHE FSMs
1133	// no response when r_tgt_*cache_rsp is false
1134	{
1135	if ( not r_tgt_icache_req.read() and not r_tgt_dcache_req.read() ) // both completed
1136	{
1137	if ( r_tgt_icache_rsp.read() or r_tgt_dcache_rsp.read() ) // at least one response
1138	{
1139	if ( p_vci_tgt_c.rspack.read() )
1140	{
1141	// reset dcache first if activated
1142	if (r_tgt_dcache_rsp) r_tgt_dcache_rsp = false;
1143	else r_tgt_icache_rsp = false;
1144	}
1145	}
1146	else
1147	{
1148	r_tgt_fsm = TGT_IDLE;
1149	}
1150	}
1151	break;
1152	}
1153	////////////////////
1154	case TGT_RSP_ICACHE: // waiting acknowledge from ICACHE FSM
1155	{
1156	// no response when r_tgt_icache_rsp is false
1157	if ( not r_tgt_icache_req.read() and (p_vci_tgt_c.rspack.read() or not r_tgt_icache_rsp.read()))
1158	{
1159	r_tgt_fsm = TGT_IDLE;
1160	r_tgt_icache_rsp = false;
1161	}
1162	break;
1163	}
1164	////////////////////
1165	case TGT_RSP_DCACHE:
1166	{
1167	// no response when r_tgt_dcache_rsp is false
1168	if ( not r_tgt_dcache_req.read() and (p_vci_tgt_c.rspack.read() or not r_tgt_dcache_rsp.read()))
1169	{
1170	r_tgt_fsm = TGT_IDLE;
1171	r_tgt_dcache_rsp = false;
1172	}
1173	break;
1174	}
1175	} // end switch TGT_FSM
1176
1177	/////////////////////////////////////////////////////////////////////
1178	// Get data and instruction requests from processor
1179	///////////////////////////////////////////////////////////////////////
1180
1181	r_iss.getRequests(m_ireq, m_dreq);
1182
1183	////////////////////////////////////////////////////////////////////////////////////
1184	// ICACHE_FSM
1185	//
1186	// There is 9 conditions to exit the IDLE state:
1187	// One condition is a coherence request from TGT FSM :
1188	// - Coherence operation => ICACHE_CC_CHEK
1189	// Five configurations corresponding to XTN processor requests sent by DCACHE FSM :
1190	// - Flush TLB => ICACHE_XTN_TLB_FLUSH
1191	// - Flush cache => ICACHE_XTN_CACHE_FLUSH
1192	// - Invalidate a TLB entry => ICACHE_XTN_TLB_INVAL
1193	// - Invalidate a cache line => ICACHE_XTN_CACHE_INVAL_VA@
1194	// - Invalidate a cache line using physical address => ICACHE_XTN_CACHE_INVAL_PA
1195	// three configurations corresponding to instruction processor requests :
1196	// - tlb miss => ICACHE_TLB_WAIT
1197	// - cacheable read miss => ICACHE_MISS_VICTIM
1198	// - uncacheable read miss => ICACHE_UNC_REQ
1199	//
1200	// In case of cache miss, the ICACHE FSM request a VCI transaction to CMD FSM
1201	// using the r_icache_tlb_miss_req flip-flop, that reset this flip-flop when the
1202	// transaction starts. Then the ICACHE FSM goes to the ICACHE_MISS VICTIM
1203	// state to select a slot and request a VCI transaction to the CLEANUP FSM.
1204	// It goes next to the ICACHE_MISS_WAIT state waiting a response from RSP FSM.
1205	// The availability of the missing cache line is signaled by the response fifo,
1206	// and the cache update is done (one word per cycle) in the ICACHE_MISS_UPDT state.
1207	//
1208	// In case of uncacheable address, the ICACHE FSM request an uncached VCI transaction
1209	// to CMD FSM using the r_icache_unc_req flip-flop, that reset this flip-flop
1210	// when the transaction starts. The ICACHE FSM goes to ICACHE_UNC_WAIT to wait
1211	// the response from the RSP FSM, through the response fifo. The missing instruction
1212	// is directly returned to processor in this state.
1213	//
1214	// In case of tlb miss, the ICACHE FSM request to the DCACHE FSM to update the tlb
1215	// using the r_icache_tlb_miss_req flip-flop and the r_icache_tlb_miss_vaddr register,
1216	// and goes to the ICACHE_TLB_WAIT state.
1217	// The tlb update is entirely done by the DCACHE FSM (who becomes the owner of dtlb until
1218	// the update is completed, and reset r_icache_tlb_miss_req to signal the completion.
1219	//
1220	// The DCACHE FSM signals XTN processor requests to ICACHE_FSM
1221	// using the r_dcache_xtn_req flip-flop.
1222	// The request opcode and the address to be invalidated are transmitted
1223	// in the r_dcache_xtn_opcode and r_dcache_p0_wdata registers respectively.
1224	// The r_dcache_xtn_req flip-flop is reset by the ICACHE_FSM when the operation
1225	// is completed.
1226	//
1227	// The r_vci_rsp_ins_error flip-flop is set by the RSP FSM in case of bus error
1228	// in a cache miss or uncacheable read VCI transaction. Nothing is written
1229	// in the response fifo. This flip-flop is reset by the ICACHE-FSM.
1230	////////////////////////////////////////////////////////////////////////////////////////
1231
1232	// default value for m_irsp
1233	m_irsp.valid = false;
1234	m_irsp.error = false;
1235	m_irsp.instruction = 0;
1236
1237	switch( r_icache_fsm.read() )
1238	{
1239	/////////////////
1240	case ICACHE_IDLE: // In this state, we handle processor requests, XTN requests sent
1241	// by DCACHE FSM, and coherence requests with a fixed priority:
1242	// coherence > XTN > instruction
1243	// We access the itlb and dcache in parallel with the virtual address
1244	// for itlb, and with a speculative physical address for icache,
1245	// computed during the previous cycle.
1246	{
1247	// coherence request from the target FSM
1248	if ( r_tgt_icache_req.read() )
1249	{
1250	r_icache_fsm = ICACHE_CC_CHECK;
1251	r_icache_fsm_save = r_icache_fsm.read();
1252	break;
1253	}
1254
1255	// Decoding processor XTN requests sent by DCACHE FSM
1256	// These request are not executed in this IDLE state, because
1257	// they require access to icache or itlb, that are already accessed
1258	if ( r_dcache_xtn_req.read() )
1259	{
1260	if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_PTPR )
1261	{
1262	r_icache_fsm = ICACHE_XTN_TLB_FLUSH;
1263	break;
1264	}
1265	if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ICACHE_FLUSH)
1266	{
1267	r_icache_flush_count = 0;
1268	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH;
1269	break;
1270	}
1271	if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ITLB_INVAL)
1272	{
1273	r_icache_fsm = ICACHE_XTN_TLB_INVAL;
1274	break;
1275	}
1276	if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ICACHE_INVAL)
1277	{
1278	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_VA;
1279	break;
1280	}
1281	if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_MMU_ICACHE_PA_INV)
1282	{
1283	if (sizeof(paddr_t) <= 32) {
1284	assert(r_mmu_word_hi.read() == 0 &&
1285	"high bits should be 0 for 32bit paddr");
1286	r_icache_vci_paddr = (paddr_t)r_mmu_word_lo.read();
1287	} else {
1288	r_icache_vci_paddr =
1289	(paddr_t)r_mmu_word_hi.read() << 32 \|
1290	(paddr_t)r_mmu_word_lo.read();
1291	}
1292	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA;
1293	break;
1294	}
1295	} // end if xtn_req
1296
1297	// processor request
1298	if ( m_ireq.valid )
1299	{
1300	bool cacheable;
1301	paddr_t paddr;
1302
1303	// We register processor request
1304	r_icache_vaddr_save = m_ireq.addr;
1305
1306	// speculative icache access (if cache activated)
1307	// we use the speculative PPN computed during the previous cycle
1308
1309	uint32_t cache_inst = 0;
1310	bool cache_hit = false;
1311
1312	if ( r_mmu_mode.read() & INS_CACHE_MASK )
1313	{
1314	paddr_t spc_paddr = (r_icache_vci_paddr.read() & ~PAGE_K_MASK) \|
1315	((paddr_t)m_ireq.addr & PAGE_K_MASK);
1316
1317	#ifdef INSTRUMENTATION
1318	m_cpt_icache_data_read++;
1319	m_cpt_icache_dir_read++;
1320	#endif
1321	cache_hit = r_icache.read( spc_paddr,
1322	&cache_inst );
1323	}
1324
1325	// systematic itlb access (if tlb activated)
1326	// we use the virtual address
1327
1328	paddr_t tlb_paddr;
1329	pte_info_t tlb_flags;
1330	size_t tlb_way;
1331	size_t tlb_set;
1332	paddr_t tlb_nline;
1333	bool tlb_hit = false;;
1334
1335	if ( r_mmu_mode.read() & INS_TLB_MASK )
1336	{
1337
1338	#ifdef INSTRUMENTATION
1339	m_cpt_itlb_read++;
1340	#endif
1341	tlb_hit = r_itlb.translate( m_ireq.addr,
1342	&tlb_paddr,
1343	&tlb_flags,
1344	&tlb_nline, // unused
1345	&tlb_way, // unused
1346	&tlb_set ); // unused
1347	}
1348
1349	// We compute cacheability, physical address and check access rights:
1350	// - If MMU activated : cacheability is defined by the C bit in the PTE,
1351	// the physical address is obtained from the TLB, and the access rights are
1352	// defined by the U and X bits in the PTE.
1353	// - If MMU not activated : cacheability is defined by the segment table,
1354	// the physical address is equal to the virtual address (identity mapping)
1355	// and there is no access rights checking
1356
1357	if ( not (r_mmu_mode.read() & INS_TLB_MASK) ) // tlb not activated:
1358	{
1359	// cacheability
1360	if ( not (r_mmu_mode.read() & INS_CACHE_MASK) ) cacheable = false;
1361	else cacheable = m_cacheability_table[m_ireq.addr];
1362
1363	// physical address
1364	paddr = (paddr_t)m_ireq.addr;
1365	}
1366	else // itlb activated
1367	{
1368	if ( tlb_hit ) // tlb hit
1369	{
1370	// cacheability
1371	if ( not (r_mmu_mode.read() & INS_CACHE_MASK) ) cacheable = false;
1372	else cacheable = tlb_flags.c;
1373
1374	// physical address
1375	paddr = tlb_paddr;
1376
1377	// access rights checking
1378	if ( not tlb_flags.u && (m_ireq.mode == iss_t::MODE_USER) )
1379	{
1380	r_mmu_ietr = MMU_READ_PRIVILEGE_VIOLATION;
1381	r_mmu_ibvar = m_ireq.addr;
1382	m_irsp.valid = true;
1383	m_irsp.error = true;
1384	m_irsp.instruction = 0;
1385	break;
1386	}
1387	else if ( not tlb_flags.x )
1388	{
1389	r_mmu_ietr = MMU_READ_EXEC_VIOLATION;
1390	r_mmu_ibvar = m_ireq.addr;
1391	m_irsp.valid = true;
1392	m_irsp.error = true;
1393	m_irsp.instruction = 0;
1394	break;
1395	}
1396	}
1397	// in case of TLB miss we send an itlb miss request to DCACHE FSM and break
1398	else
1399	{
1400
1401	#ifdef INSTRUMENTATION
1402	m_cpt_itlb_miss++;
1403	#endif
1404	r_icache_fsm = ICACHE_TLB_WAIT;
1405	r_icache_tlb_miss_req = true;
1406	break;
1407	}
1408	} // end if itlb activated
1409
1410	// physical address registration (for next cycle)
1411	r_icache_vci_paddr = paddr;
1412
1413	// We enter this section only in case of TLB hit:
1414	// Finally, we get the instruction depending on cacheability,
1415	// we send the response to processor, and compute next state
1416	if ( cacheable ) // cacheable read
1417	{
1418	if ( (r_icache_vci_paddr.read() & ~PAGE_K_MASK)
1419	!= (paddr & ~PAGE_K_MASK) ) // speculative access KO
1420	{
1421
1422	#ifdef INSTRUMENTATION
1423	m_cpt_icache_spc_miss++;
1424	#endif
1425	// we return an invalid response and stay in IDLE state
1426	// the cache access will cost one extra cycle.
1427	break;
1428	}
1429
1430	if ( not cache_hit ) // cache miss
1431	{
1432
1433	#ifdef INSTRUMENTATION
1434	m_cpt_icache_miss++;
1435	#endif
1436	r_icache_fsm = ICACHE_MISS_VICTIM;
1437	r_icache_miss_req = true;
1438	}
1439	else // cache hit
1440	{
1441
1442	#ifdef INSTRUMENTATION
1443	m_cpt_ins_read++;
1444	#endif
1445	m_irsp.valid = true;
1446	m_irsp.instruction = cache_inst;
1447	}
1448	}
1449	else // non cacheable read
1450	{
1451	r_icache_unc_req = true;
1452	r_icache_fsm = ICACHE_UNC_WAIT;
1453	}
1454	} // end if m_ireq.valid
1455	break;
1456	}
1457	/////////////////////
1458	case ICACHE_TLB_WAIT: // Waiting the itlb update by the DCACHE FSM after a tlb miss
1459	// the itlb is udated by the DCACHE FSM, as well as the
1460	// r_mmu_ietr and r_mmu_ibvar registers in case of error.
1461	// the itlb is not accessed by ICACHE FSM until DCACHE FSM
1462	// reset the r_icache_tlb_miss_req flip-flop
1463	// external coherence request are accepted in this state.
1464	{
1465	// external coherence request
1466	if ( r_tgt_icache_req.read() )
1467	{
1468	r_icache_fsm = ICACHE_CC_CHECK;
1469	r_icache_fsm_save = r_icache_fsm.read();
1470	break;
1471	}
1472
1473	if ( m_ireq.valid ) m_cost_ins_tlb_miss_frz++;
1474
1475	// DCACHE FSM signals response by reseting the request flip-flop
1476	if ( not r_icache_tlb_miss_req.read() )
1477	{
1478	if ( r_icache_tlb_rsp_error.read() ) // error reported : tlb not updated
1479	{
1480	r_icache_tlb_rsp_error = false;
1481	m_irsp.error = true;
1482	m_irsp.valid = true;
1483	r_icache_fsm = ICACHE_IDLE;
1484	}
1485	else // tlb updated : return to IDLE state
1486	{
1487	r_icache_fsm = ICACHE_IDLE;
1488	}
1489	}
1490	break;
1491	}
1492	//////////////////////////
1493	case ICACHE_XTN_TLB_FLUSH: // invalidate in one cycle all non global TLB entries
1494	{
1495	r_itlb.flush();
1496	r_dcache_xtn_req = false;
1497	r_icache_fsm = ICACHE_IDLE;
1498	break;
1499	}
1500	////////////////////////////
1501	case ICACHE_XTN_CACHE_FLUSH: // Invalidate sequencially all cache lines using
1502	// the r_icache_flush_count register as a slot counter.
1503	// We loop in this state until all slots have been visited.
1504	// A cleanup request is generated for each valid line
1505	// and we are blocked until the previous cleanup is completed
1506	{
1507	if ( not r_icache_cleanup_req.read() )
1508	{
1509	size_t way = r_icache_flush_count.read()/m_icache_sets;
1510	size_t set = r_icache_flush_count.read()%m_icache_sets;
1511	paddr_t nline;
1512	bool cleanup_req = r_icache.inval( way,
1513	set,
1514	&nline );
1515	if ( cleanup_req )
1516	{
1517	r_icache_cleanup_req = true;
1518	r_icache_cleanup_line = nline;
1519	}
1520	r_icache_flush_count = r_icache_flush_count.read() + 1;
1521
1522
1523	if ( r_icache_flush_count.read() == (m_icache_sets*m_icache_ways - 1) )
1524	{
1525	r_dcache_xtn_req = false;
1526	r_icache_fsm = ICACHE_IDLE;
1527	}
1528	}
1529
1530	break;
1531	}
1532	//////////////////////////
1533	case ICACHE_XTN_TLB_INVAL: // invalidate one TLB entry selected by the virtual address
1534	// stored in the r_dcache_p0_wdata register
1535	{
1536	r_itlb.inval(r_dcache_p0_wdata.read());
1537	r_dcache_xtn_req = false;
1538	r_icache_fsm = ICACHE_IDLE;
1539	break;
1540	}
1541	///////////////////////////////
1542	case ICACHE_XTN_CACHE_INVAL_VA: // Selective cache line invalidate with virtual address
1543	// requires 3 cycles (in case of hit on itlb and icache).
1544	// In this state, we access TLB to translate virtual address
1545	// stored in the r_dcache_p0_wdata register.
1546	{
1547	paddr_t paddr;
1548	bool hit;
1549
1550	// read physical address in TLB when MMU activated
1551	if ( r_mmu_mode.read() & INS_TLB_MASK ) // itlb activated
1552	{
1553
1554	#ifdef INSTRUMENTATION
1555	m_cpt_itlb_read++;
1556	#endif
1557	hit = r_itlb.translate(r_dcache_p0_wdata.read(),
1558	&paddr);
1559	}
1560	else // itlb not activated
1561	{
1562	paddr = (paddr_t)r_dcache_p0_wdata.read();
1563	hit = true;
1564	}
1565
1566	if ( hit ) // continue the selective inval process
1567	{
1568	r_icache_vci_paddr = paddr;
1569	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA;
1570	}
1571	else // miss : send a request to DCACHE FSM
1572	{
1573
1574	#ifdef INSTRUMENTATION
1575	m_cpt_itlb_miss++;
1576	#endif
1577	r_icache_tlb_miss_req = true;
1578	r_icache_vaddr_save = r_dcache_p0_wdata.read();
1579	r_icache_fsm = ICACHE_TLB_WAIT;
1580	}
1581	break;
1582	}
1583	///////////////////////////////
1584	case ICACHE_XTN_CACHE_INVAL_PA: // selective invalidate cache line with physical address
1585	// require 2 cycles. In this state, we read dcache,
1586	// with address stored in r_icache_vci_paddr register.
1587	{
1588	uint32_t data;
1589	size_t way;
1590	size_t set;
1591	size_t word;
1592	bool hit = r_icache.read(r_icache_vci_paddr.read(),
1593	&data,
1594	&way,
1595	&set,
1596	&word);
1597	if ( hit ) // inval to be done
1598	{
1599	r_icache_miss_way = way;
1600	r_icache_miss_set = set;
1601	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_GO;
1602	}
1603	else // miss : acknowlege the XTN request and return
1604	{
1605	r_dcache_xtn_req = false;
1606	r_icache_fsm = ICACHE_IDLE;
1607	}
1608	break;
1609	}
1610	///////////////////////////////
1611	case ICACHE_XTN_CACHE_INVAL_GO: // In this state, we invalidate the cache line & cleanup.
1612	// We are blocked if the previous cleanup is not completed
1613	{
1614	paddr_t nline;
1615
1616	if ( not r_icache_cleanup_req.read() )
1617	{
1618	bool hit;
1619	hit = r_icache.inval( r_icache_miss_way.read(),
1620	r_icache_miss_set.read(),
1621	&nline );
1622	assert(hit && "XTN_ICACHE_INVAL way/set should still be in icache");
1623
1624	// request cleanup
1625	r_icache_cleanup_req = true;
1626	r_icache_cleanup_line = nline;
1627	// acknowledge the XTN request and return
1628	r_dcache_xtn_req = false;
1629	r_icache_fsm = ICACHE_IDLE;
1630	}
1631	break;
1632	}
1633
1634	////////////////////////
1635	case ICACHE_MISS_VICTIM: // Selects a victim line
1636	// Set the r_icache_cleanup_req flip-flop
1637	// when the selected slot is not empty
1638	{
1639	m_cost_ins_miss_frz++;
1640
1641	size_t index; // unused
1642	bool hit = r_cleanup_buffer.hit( r_icache_vci_paddr.read()>>(uint32_log2(m_icache_words)+2), &index );
1643	if ( not hit and not r_icache_cleanup_req.read() )
1644	{
1645	bool valid;
1646	size_t way;
1647	size_t set;
1648	paddr_t victim;
1649
1650	valid = r_icache.victim_select(r_icache_vci_paddr.read(),
1651	&victim,
1652	&way,
1653	&set);
1654	r_icache_miss_way = way;
1655	r_icache_miss_set = set;
1656
1657	if ( valid )
1658	{
1659	r_icache_cleanup_req = true;
1660	r_icache_cleanup_line = victim;
1661	r_icache_fsm = ICACHE_MISS_INVAL;
1662	}
1663	else
1664	{
1665	r_icache_fsm = ICACHE_MISS_WAIT;
1666	}
1667	}
1668	break;
1669	}
1670	///////////////////////
1671	case ICACHE_MISS_INVAL: // invalidate the victim line
1672	{
1673	paddr_t nline;
1674	bool hit;
1675
1676	hit = r_icache.inval( r_icache_miss_way.read(),
1677	r_icache_miss_set.read(),
1678	&nline ); // unused
1679	assert(hit && "selected way/set line should be in icache");
1680
1681	r_icache_fsm = ICACHE_MISS_WAIT;
1682	break;
1683	}
1684	//////////////////////
1685	case ICACHE_MISS_WAIT: // waiting a response to a miss request from VCI_RSP FSM
1686	{
1687	if ( m_ireq.valid ) m_cost_ins_miss_frz++;
1688
1689	// external coherence request
1690	if ( r_tgt_icache_req.read() )
1691	{
1692	r_icache_fsm = ICACHE_CC_CHECK;
1693	r_icache_fsm_save = r_icache_fsm.read();
1694	break;
1695	}
1696
1697	if ( r_vci_rsp_ins_error.read() ) // bus error
1698	{
1699	r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS;
1700	r_mmu_ibvar = r_icache_vaddr_save.read();
1701	m_irsp.valid = true;
1702	m_irsp.error = true;
1703	r_vci_rsp_ins_error = false;
1704	r_icache_fsm = ICACHE_IDLE;
1705	}
1706	else if ( r_vci_rsp_fifo_icache.rok() ) // response available
1707	{
1708	r_icache_miss_word = 0;
1709	r_icache_fsm = ICACHE_MISS_UPDT;
1710	}
1711	break;
1712	}
1713	//////////////////////
1714	case ICACHE_MISS_UPDT: // update the cache (one word per cycle)
1715	{
1716	if ( m_ireq.valid ) m_cost_ins_miss_frz++;
1717
1718	if ( r_vci_rsp_fifo_icache.rok() ) // response available
1719	{
1720	if ( r_icache_miss_inval ) // Matching coherence request
1721	// We pop the response FIFO, without updating the cache
1722	// We send a cleanup for the missing line at the last word
1723	// Blocked if the previous cleanup is not completed
1724	{
1725	if ( r_icache_miss_word.read() < m_icache_words-1 ) // not the last word
1726	{
1727	vci_rsp_fifo_icache_get = true;
1728	r_icache_miss_word = r_icache_miss_word.read() + 1;
1729	}
1730	else // last word
1731	{
1732	if ( not r_icache_cleanup_req.read() ) // no pending cleanup
1733	{
1734	vci_rsp_fifo_icache_get = true;
1735	r_icache_cleanup_req = true;
1736	r_icache_cleanup_line = r_icache_vci_paddr.read() >> (uint32_log2(m_icache_words<<2));
1737	r_icache_miss_inval = false;
1738	r_icache_fsm = ICACHE_IDLE;
1739	}
1740	}
1741	}
1742	else // No matching coherence request
1743	// We pop the FIFO and update the cache
1744	// We update the directory at the last word
1745	{
1746
1747	#ifdef INSTRUMENTATION
1748	m_cpt_icache_data_write++;
1749	#endif
1750	r_icache.write( r_icache_miss_way.read(),
1751	r_icache_miss_set.read(),
1752	r_icache_miss_word.read(),
1753	r_vci_rsp_fifo_icache.read() );
1754	vci_rsp_fifo_icache_get = true;
1755	r_icache_miss_word = r_icache_miss_word.read() + 1;
1756	if ( r_icache_miss_word.read() == m_icache_words-1 ) // last word
1757	{
1758
1759	#ifdef INSTRUMENTATION
1760	m_cpt_icache_dir_write++;
1761	#endif
1762	r_icache.victim_update_tag( r_icache_vci_paddr.read(),
1763	r_icache_miss_way.read(),
1764	r_icache_miss_set.read() );
1765	r_icache_fsm = ICACHE_IDLE;
1766	}
1767	}
1768	}
1769	break;
1770	}
1771	////////////////////
1772	case ICACHE_UNC_WAIT: // waiting a response to an uncacheable read from VCI_RSP FSM
1773	//
1774	{
1775	// external coherence request
1776	if ( r_tgt_icache_req.read() )
1777	{
1778	r_icache_fsm = ICACHE_CC_CHECK;
1779	r_icache_fsm_save = r_icache_fsm.read();
1780	break;
1781	}
1782
1783	if ( r_vci_rsp_ins_error.read() ) // bus error
1784	{
1785	r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS;
1786	r_mmu_ibvar = m_ireq.addr;
1787	r_vci_rsp_ins_error = false;
1788	m_irsp.valid = true;
1789	m_irsp.error = true;
1790	r_icache_fsm = ICACHE_IDLE;
1791	}
1792	else if (r_vci_rsp_fifo_icache.rok() ) // instruction available
1793	{
1794	vci_rsp_fifo_icache_get = true;
1795	r_icache_fsm = ICACHE_IDLE;
1796	if ( m_ireq.valid and (m_ireq.addr == r_icache_vaddr_save.read()) ) // request not modified
1797	{
1798	m_irsp.valid = true;
1799	m_irsp.instruction = r_vci_rsp_fifo_icache.read();
1800	}
1801	}
1802	break;
1803	}
1804	/////////////////////
1805	case ICACHE_CC_CHECK: // This state is the entry point of a sub-fsm
1806	// handling coherence requests.
1807	// the return state is defined in r_icache_fsm_save.
1808	{
1809	paddr_t paddr = r_tgt_paddr.read();
1810	paddr_t mask = ~((m_icache_words<<2)-1);
1811
1812	if( (r_icache_fsm_save.read() == ICACHE_MISS_WAIT) and
1813	((r_icache_vci_paddr.read() & mask) == (paddr & mask))) // matching a pending miss
1814	{
1815	r_icache_miss_inval = true; // signaling the matching
1816	r_tgt_icache_req = false; // coherence request completed
1817	r_tgt_icache_rsp = r_tgt_update.read(); // response required if update
1818	r_icache_fsm = r_icache_fsm_save.read();
1819	}
1820	else // no match
1821	{
1822
1823	#ifdef INSTRUMENTATION
1824	m_cpt_icache_dir_read++;
1825	#endif
1826	uint32_t inst;
1827	size_t way;
1828	size_t set;
1829	size_t word;
1830	bool hit = r_icache.read(paddr,
1831	&inst,
1832	&way,
1833	&set,
1834	&word);
1835	r_icache_cc_way = way;
1836	r_icache_cc_set = set;
1837
1838	if ( hit and r_tgt_update.read() ) // hit update
1839	{
1840	r_icache_fsm = ICACHE_CC_UPDT;
1841	r_icache_cc_word = r_tgt_word_min.read();
1842	}
1843	else if ( hit and not r_tgt_update.read() ) // hit inval
1844	{
1845	r_icache_fsm = ICACHE_CC_INVAL;
1846	}
1847	else // miss can happen
1848	{
1849	r_tgt_icache_req = false;
1850	r_tgt_icache_rsp = r_tgt_update.read();
1851	r_icache_fsm = r_icache_fsm_save.read();
1852	}
1853	}
1854	break;
1855	}
1856
1857	/////////////////////
1858	case ICACHE_CC_INVAL: // invalidate a cache line
1859	{
1860	paddr_t nline;
1861	bool hit;
1862	hit = r_icache.inval( r_icache_cc_way.read(),
1863	r_icache_cc_set.read(),
1864	&nline );
1865	assert (hit && "ICACHE_CC_INVAL way/set should still be in icache");
1866	r_tgt_icache_req = false;
1867	r_tgt_icache_rsp = true;
1868	r_icache_fsm = r_icache_fsm_save.read();
1869	break;
1870	}
1871	////////////////////
1872	case ICACHE_CC_UPDT: // write one word per cycle (from word_min to word_max)
1873	{
1874	size_t word = r_icache_cc_word.read();
1875	size_t way = r_icache_cc_way.read();
1876	size_t set = r_icache_cc_set.read();
1877
1878	r_icache.write( way,
1879	set,
1880	word,
1881	r_tgt_buf[word],
1882	r_tgt_be[word] );
1883
1884	r_icache_cc_word = word+1;
1885
1886	if ( word == r_tgt_word_max.read() ) // last word
1887	{
1888	r_tgt_icache_req = false;
1889	r_tgt_icache_rsp = true;
1890	r_icache_fsm = r_icache_fsm_save.read();
1891	}
1892	break;
1893	}
1894
1895	} // end switch r_icache_fsm
1896
1897	////////////////////////////////////////////////////////////////////////////////////
1898	// DCACHE FSM
1899	//
1900	// Both the Cacheability Table, and the MMU cacheable bit are used to define
1901	// the cacheability, depending on the MMU mode.
1902	//
1903	// 1/ Coherence requests :
1904	// There is a coherence request when the tgt_dcache_req flip-flop is set,
1905	// requesting a line invalidation or a line update.
1906	// Coherence requests are taken into account in IDLE, UNC_WAIT, MISS_WAIT states.
1907	// The actions associated to the pre-empted state are not executed, the DCACHE FSM
1908	// goes to the CC_CHECK state to execute the requested action, and returns to the
1909	// pre-empted state.
1910	//
1911	// 2/ TLB miss
1912	// The page tables can be cacheable.
1913	// In case of miss in itlb or dtlb, the tlb miss is handled by a dedicated
1914	// sub-fsm (DCACHE_TLB_MISS state), that handle possible miss in DCACHE,
1915	// this sub-fsm implement the table-walk...
1916	//
1917	// 3/ processor requests :
1918	// Processor READ, WRITE, LL or SC requests are taken in IDLE state only.
1919	// The IDLE state implements a three stages pipe-line to handle write bursts:
1920	// - The physical address is computed by dtlb in stage P0.
1921	// - The registration in wbuf and the dcache hit are computed in stage P1.
1922	// - The dcache update is done in stage P2.
1923	// WRITE or SC requests can require a PTE Dirty bit update (in memory),
1924	// that is done (before handling the processor request) by a dedicated sub-fsm
1925	// (DCACHE_DIRTY_TLB_SET state).
1926	// If a PTE is modified, both the itlb and dtlb are selectively, but sequencially
1927	// cleared by a dedicated sub_fsm (DCACHE_INVAL_TLB_SCAN state).
1928	// If there is no write in the pipe, dcache and dtlb are accessed in parallel,
1929	// (virtual address for itlb, and speculative physical address computed during
1930	// previous cycle for dcache) in order to return the data in one cycle for a READ
1931	// request. We just pay an extra cycle when the speculative access is failing.
1932	//
1933	// 4/ Atomic instructions LL/SC
1934	// The LL/SC address can be cacheable or non cacheable.
1935	// The reservation registers (r_dcache_ll_valid, r_dcache_ll_vaddr and
1936	// r_dcache_ll_data are stored in the L1 cache controller, and not in the
1937	// memory controller.
1938	// - LL requests from the processor are transmitted as standard VCI
1939	// READ transactions (one word / one line, depending on the cacheability).
1940	// - SC requests from the processor are systematically transmitted to the
1941	// memory cache as Compare&swap requests (both the data value stored in the
1942	// r_dcache_ll_data register and the new value).
1943	// The cache is not updated, as this is done in case of success by the
1944	// coherence transaction.
1945	//
1946	// 5/ Non cacheable access:
1947	// This component implement a strong order between non cacheable access
1948	// (read or write) : A new non cacheable VCI transaction starts only when
1949	// the previous non cacheable transaction is completed. Both cacheable and
1950	// non cacheable transactions use the write buffer, but the DCACHE FSM registers
1951	// a non cacheable write transaction posted in the write buffer by setting the
1952	// r_dcache_pending_unc_write flip_flop. All other non cacheable requests
1953	// are stalled until this flip-flop is reset by the VCI_RSP_FSM (when the
1954	// pending non cacheable write transaction completes).
1955	//
1956	// 6/ Error handling:
1957	// When the MMU is not activated, Read Bus Errors are synchronous events,
1958	// but Write Bus Errors are asynchronous events (processor is not frozen).
1959	// - If a Read Bus Error is detected, the VCI_RSP FSM sets the
1960	// r_vci_rsp_data_error flip-flop, without writing any data in the
1961	// r_vci_rsp_fifo_dcache FIFO, and the synchronous error is signaled
1962	// by the DCACHE FSM.
1963	// - If a Write Bus Error is detected, the VCI_RSP FSM signals
1964	// the asynchronous error using the setWriteBerr() method.
1965	// When the MMU is activated bus error are rare events, as the MMU
1966	// checks the physical address before the VCI transaction starts.
1967	////////////////////////////////////////////////////////////////////////////////////////
1968
1969	// default value for m_drsp
1970	m_drsp.valid = false;
1971	m_drsp.error = false;
1972	m_drsp.rdata = 0;
1973
1974	switch ( r_dcache_fsm.read() )
1975	{
1976	case DCACHE_IDLE: // There is 8 conditions to exit the IDLE state :
1977	// 1) Dirty bit update (processor) => DCACHE_DIRTY_GET_PTE
1978	// 2) Coherence request (TGT FSM) => DCACHE_CC_CHECK
1979	// 3) ITLB miss request (ICACHE FSM) => DCACHE_TLB_MISS
1980	// 4) XTN request (processor) => DCACHE_XTN_*
1981	// 5) DTLB miss (processor) => DCACHE_TLB_MISS
1982	// 6) Cacheable read miss (processor) => DCACHE_MISS_VICTIM
1983	// 7) Uncacheable read (processor) => DCACHE_UNC_WAIT
1984	// 8) SC access (processor) => DCACHE_SC_WAIT
1985	//
1986	// The dtlb is unconditionally accessed to translate the
1987	// virtual adress from processor.
1988	//
1989	// There is 4 configurations to access the cache,
1990	// depending on the pipe-line state, defined
1991	// by the r_dcache_p0_valid (V0) flip-flop : P1 stage activated
1992	// and r_dcache_p1_valid (V1) flip-flop : P2 stage activated
1993	// V0 / V1 / Data / Directory / comment
1994	// 0 / 0 / read(A0) / read(A0) / read speculative access
1995	// 0 / 1 / write(A2) / nop / read request delayed
1996	// 1 / 0 / nop / read(A1) / read request delayed
1997	// 1 / 1 / write(A2) / read(A1) / read request delayed
1998	{
1999	bool tlb_inval_required = false;
2000	bool write_pipe_frozen = false;
2001
2002	////////////////////////////////////////////////////////////////////////////////
2003	// Handling P2 pipe-line stage
2004	// Inputs are r_dcache_p1_* registers.
2005	// If r_dcache_p1_valid is true, we update the local copy in dcache.
2006	// If the modified cache line has copies in TLBs, we launch a TLB invalidate
2007	// operation, going to DCACHE_INVAL_TLB_SCAN state.
2008
2009	if ( r_dcache_p1_valid.read() ) // P2 stage activated
2010	{
2011	size_t way = r_dcache_p1_cache_way.read();
2012	size_t set = r_dcache_p1_cache_set.read();
2013	size_t word = r_dcache_p1_cache_word.read();
2014	uint32_t wdata = r_dcache_p1_wdata.read();
2015	vci_be_t be = r_dcache_p1_be.read();
2016
2017	r_dcache.write( way,
2018	set,
2019	word,
2020	wdata,
2021	be );
2022	#ifdef INSTRUMENTATION
2023	m_cpt_dcache_data_write++;
2024	#endif
2025	// cache update after a WRITE hit can require itlb & dtlb inval or flush
2026	if ( r_dcache_in_tlb[way*m_dcache_sets+set] )
2027	{
2028	tlb_inval_required = true;
2029	r_dcache_tlb_inval_count = 0;
2030	r_dcache_tlb_inval_line = r_dcache_p1_paddr.read()>>
2031	(uint32_log2(m_dcache_words<<2));
2032	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
2033	}
2034	else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] )
2035	{
2036	r_itlb.reset();
2037	r_dtlb.reset();
2038	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
2039	}
2040
2041	#if DEBUG_DCACHE
2042	if ( m_debug_dcache_fsm )
2043	{
2044	std::cout << " <PROC.DCACHE_IDLE> Cache update in P2 stage" << std::dec
2045	<< " / WAY = " << way
2046	<< " / SET = " << set
2047	<< " / WORD = " << word << std::hex
2048	<< " / DATA = " << wdata
2049	<< " / BE = " << be << std::endl;
2050	}
2051	#endif
2052	} // end P2 stage
2053
2054	///////////////////////////////////////////////////////////////////////////
2055	// Handling P1 pipe-line stage
2056	// Inputs are r_dcache_p0_* registers.
2057	// We must write into wbuf and test the hit in dcache.
2058	// If the write request is non cacheable, and there is a pending
2059	// non cacheable write, or if the write buffer is full, the P0 and P1 stages
2060	// are frozen until the write request registration is possible,
2061	// while the P2 stage is not frozen.
2062	// The r_dcache_p1_valid bit must be computed at all cycles, and
2063	// the P2 stage must be activated if there is a local copy in dcache.
2064
2065	if ( r_dcache_p0_valid.read() ) // P1 stage activated
2066	{
2067	// frozen if write not cacheable, and previous non cacheable write registered
2068	if ( not r_dcache_p0_cacheable.read() and r_dcache_pending_unc_write.read() )
2069	{
2070	r_dcache_p1_valid = false;
2071	write_pipe_frozen = true;
2072	}
2073	else // try a registration into write buffer
2074	{
2075
2076	bool wok = r_wbuf.write( r_dcache_p0_paddr.read(),
2077	r_dcache_p0_be.read(),
2078	r_dcache_p0_wdata.read(),
2079	r_dcache_p0_cacheable.read() );
2080	#ifdef INSTRUMENTATION
2081	m_cpt_wbuf_write++;
2082	#endif
2083	if ( not wok ) // frozen if write buffer full
2084	{
2085	r_dcache_p1_valid = false;
2086	write_pipe_frozen = true;
2087	}
2088	else // update the write_buffer state extension
2089	{
2090	r_dcache_pending_unc_write = not r_dcache_p0_cacheable.read();
2091
2092	// read directory to check local copy
2093	size_t cache_way;
2094	size_t cache_set;
2095	size_t cache_word;
2096	bool local_copy;
2097	if ( r_mmu_mode.read() & DATA_CACHE_MASK) // cache activated
2098	{
2099	local_copy = r_dcache.hit( r_dcache_p0_paddr.read(),
2100	&cache_way,
2101	&cache_set,
2102	&cache_word );
2103	#ifdef INSTRUMENTATION
2104	m_cpt_dcache_dir_read++;
2105	#endif
2106	}
2107	else
2108	{
2109	local_copy = false;
2110	}
2111
2112	// store values for P2 pipe stage
2113	if ( local_copy )
2114	{
2115	r_dcache_p1_valid = true;
2116	r_dcache_p1_wdata = r_dcache_p0_wdata.read();
2117	r_dcache_p1_be = r_dcache_p0_be.read();
2118	r_dcache_p1_paddr = r_dcache_p0_paddr.read();
2119	r_dcache_p1_cache_way = cache_way;
2120	r_dcache_p1_cache_set = cache_set;
2121	r_dcache_p1_cache_word = cache_word;
2122	}
2123	else
2124	{
2125	r_dcache_p1_valid = false;
2126	}
2127	}
2128	}
2129	}
2130	else // P1 stage not activated
2131	{
2132	r_dcache_p1_valid = false;
2133	} // end P1 stage
2134
2135	/////////////////////////////////////////////////////////////////////////////////
2136	// handling P0 pipe-line stage
2137	// This stage is controlling r_dcache_fsm and r_dcache_p0_* registers.
2138	// The r_dcache_p0_valid flip-flop is only set in case of a WRITE request.
2139	// - the TLB invalidate requests have the highest priority,
2140	// - then the external coherence requests,
2141	// - then the itlb miss requests,
2142	// - and finally the processor requests.
2143	// If dtlb is activated, there is an unconditionnal access to dtlb,
2144	// for address translation.
2145	// 1) A processor WRITE request is blocked if the Dirty bit mus be set, or if
2146	// dtlb miss. If dtlb is OK, It enters the three stage pipe-line (fully
2147	// handled by the IDLE state), and the processor request is acknowledged.
2148	// 2) A processor READ or LL request generate a simultaneouss access to
2149	// both dcache data and dcache directoty, using speculative PPN, but
2150	// is delayed if the write pipe-line is not empty.
2151	// In case of miss, we wait the VCI response in DCACHE_UNC_WAIT or
2152	// DCACHE_MISS_WAIT states.
2153	// 3) A processor SC request is delayed until the write pipe-line is empty.
2154	// A VCI SC transaction is launched, and we wait the VCI response in
2155	// DCACHE_SC_WAIT state. It can be completed by a "long write" if the
2156	// PTE dirty bit must be updated in dtlb, dcache, and RAM.
2157	// The data is not modified in dcache, as it will be done by the
2158	// coherence transaction.
2159
2160	// TLB inval required after a write hit
2161	if ( tlb_inval_required )
2162	{
2163	r_dcache_fsm_scan_save = r_dcache_fsm.read();
2164	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
2165	r_dcache_p0_valid = r_dcache_p0_valid.read() and write_pipe_frozen;
2166	}
2167	// external coherence request
2168	else if ( r_tgt_dcache_req.read() )
2169	{
2170	r_dcache_fsm_cc_save = r_dcache_fsm.read();
2171	r_dcache_fsm = DCACHE_CC_CHECK;
2172	r_dcache_p0_valid = r_dcache_p0_valid.read() and write_pipe_frozen;
2173	}
2174
2175	// processor request
2176	else if ( m_dreq.valid and not write_pipe_frozen )
2177	{
2178	// dcache access using speculative PPN only if pipe-line empty
2179	paddr_t cache_paddr;
2180	size_t cache_way;
2181	size_t cache_set;
2182	size_t cache_word;
2183	uint32_t cache_rdata;
2184	bool cache_hit;
2185
2186	if ( (r_mmu_mode.read() & DATA_CACHE_MASK) and // cache activated
2187	not r_dcache_p0_valid.read() and
2188	not r_dcache_p1_valid.read() ) // pipe-line empty
2189	{
2190	cache_paddr = (r_dcache_p0_paddr.read() & ~PAGE_K_MASK) \|
2191	((paddr_t)m_dreq.addr & PAGE_K_MASK);
2192
2193	cache_hit = r_dcache.read( cache_paddr,
2194	&cache_rdata,
2195	&cache_way,
2196	&cache_set,
2197	&cache_word );
2198	#ifdef INSTRUMENTATION
2199	m_cpt_dcache_dir_read++;
2200	m_cpt_dcache_data_read++;
2201	#endif
2202	}
2203	else
2204	{
2205	cache_hit = false;
2206	} // end dcache access
2207
2208	// systematic dtlb access using virtual address
2209	paddr_t tlb_paddr;
2210	pte_info_t tlb_flags;
2211	size_t tlb_way;
2212	size_t tlb_set;
2213	paddr_t tlb_nline;
2214	bool tlb_hit;
2215
2216	if ( r_mmu_mode.read() & DATA_TLB_MASK ) // DTLB activated
2217	{
2218	tlb_hit = r_dtlb.translate( m_dreq.addr,
2219	&tlb_paddr,
2220	&tlb_flags,
2221	&tlb_nline,
2222	&tlb_way,
2223	&tlb_set );
2224	#ifdef INSTRUMENTATION
2225	m_cpt_dtlb_read++;
2226	#endif
2227	}
2228	else
2229	{
2230	tlb_hit = false;
2231	} // end dtlb access
2232
2233	// register the processor request
2234	r_dcache_p0_vaddr = m_dreq.addr;
2235	r_dcache_p0_be = m_dreq.be;
2236	r_dcache_p0_wdata = m_dreq.wdata;
2237
2238	// Handling READ XTN requests from processor
2239	// They are executed in this DCACHE_IDLE state.
2240	// The processor must not be in user mode
2241	if (m_dreq.type == iss_t::XTN_READ)
2242	{
2243	int xtn_opcode = (int)m_dreq.addr/4;
2244
2245	// checking processor mode:
2246	if (m_dreq.mode == iss_t::MODE_USER)
2247	{
2248	r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION;
2249	r_mmu_dbvar = m_dreq.addr;
2250	m_drsp.valid = true;
2251	m_drsp.error = true;
2252	r_dcache_fsm = DCACHE_IDLE;
2253	}
2254	else
2255	{
2256	switch( xtn_opcode )
2257	{
2258	case iss_t::XTN_INS_ERROR_TYPE:
2259	m_drsp.rdata = r_mmu_ietr.read();
2260	m_drsp.valid = true;
2261	break;
2262
2263	case iss_t::XTN_DATA_ERROR_TYPE:
2264	m_drsp.rdata = r_mmu_detr.read();
2265	m_drsp.valid = true;
2266	break;
2267
2268	case iss_t::XTN_INS_BAD_VADDR:
2269	m_drsp.rdata = r_mmu_ibvar.read();
2270	m_drsp.valid = true;
2271	break;
2272
2273	case iss_t::XTN_DATA_BAD_VADDR:
2274	m_drsp.rdata = r_mmu_dbvar.read();
2275	m_drsp.valid = true;
2276	break;
2277
2278	case iss_t::XTN_PTPR:
2279	m_drsp.rdata = r_mmu_ptpr.read();
2280	m_drsp.valid = true;
2281	break;
2282
2283	case iss_t::XTN_TLB_MODE:
2284	m_drsp.rdata = r_mmu_mode.read();
2285	m_drsp.valid = true;
2286	break;
2287
2288	case iss_t::XTN_MMU_PARAMS:
2289	m_drsp.rdata = r_mmu_params;
2290	m_drsp.valid = true;
2291	break;
2292
2293	case iss_t::XTN_MMU_RELEASE:
2294	m_drsp.rdata = r_mmu_release;
2295	m_drsp.valid = true;
2296	break;
2297
2298	case iss_t::XTN_MMU_WORD_LO:
2299	m_drsp.rdata = r_mmu_word_lo.read();
2300	m_drsp.valid = true;
2301	break;
2302
2303	case iss_t::XTN_MMU_WORD_HI:
2304	m_drsp.rdata = r_mmu_word_hi.read();
2305	m_drsp.valid = true;
2306	break;
2307
2308	default:
2309	r_mmu_detr = MMU_READ_UNDEFINED_XTN;
2310	r_mmu_dbvar = m_dreq.addr;
2311	m_drsp.valid = true;
2312	m_drsp.error = true;
2313	break;
2314	} // end switch xtn_opcode
2315	} // end else
2316	r_dcache_p0_valid = false;
2317	} // end if XTN_READ
2318
2319	// Handling WRITE XTN requests from processor.
2320	// They are not executed in this DCACHE_IDLE state,
2321	// if they require access to the caches or the TLBs
2322	// that are already accessed for speculative read.
2323	// Caches can be invalidated or flushed in user mode,
2324	// and the sync instruction can be executed in user mode
2325	else if (m_dreq.type == iss_t::XTN_WRITE)
2326	{
2327	int xtn_opcode = (int)m_dreq.addr/4;
2328	r_dcache_xtn_opcode = xtn_opcode;
2329
2330	// checking processor mode:
2331	if ( (m_dreq.mode == iss_t::MODE_USER) &&
2332	(xtn_opcode != iss_t:: XTN_SYNC) &&
2333	(xtn_opcode != iss_t::XTN_DCACHE_INVAL) &&
2334	(xtn_opcode != iss_t::XTN_DCACHE_FLUSH) &&
2335	(xtn_opcode != iss_t::XTN_ICACHE_INVAL) &&
2336	(xtn_opcode != iss_t::XTN_ICACHE_FLUSH) )
2337	{
2338	r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION;
2339	r_mmu_dbvar = m_dreq.addr;
2340	m_drsp.valid = true;
2341	m_drsp.error = true;
2342	r_dcache_fsm = DCACHE_IDLE;
2343	}
2344	else
2345	{
2346	switch( xtn_opcode )
2347	{
2348	case iss_t::XTN_PTPR: // itlb & dtlb must be flushed
2349	r_mmu_ptpr = m_dreq.wdata;
2350	r_dcache_xtn_req = true;
2351	r_dcache_fsm = DCACHE_XTN_SWITCH;
2352	break;
2353
2354	case iss_t::XTN_TLB_MODE: // no cache or tlb access
2355	r_mmu_mode = m_dreq.wdata;
2356	m_drsp.valid = true;
2357	r_dcache_fsm = DCACHE_IDLE;
2358	break;
2359
2360	case iss_t::XTN_DTLB_INVAL: // dtlb access
2361	r_dcache_fsm = DCACHE_XTN_DT_INVAL;
2362	break;
2363
2364	case iss_t::XTN_ITLB_INVAL: // itlb access
2365	r_dcache_xtn_req = true;
2366	r_dcache_fsm = DCACHE_XTN_IT_INVAL;
2367	break;
2368
2369	case iss_t::XTN_DCACHE_INVAL: // dcache, dtlb & itlb access
2370	r_dcache_fsm = DCACHE_XTN_DC_INVAL_VA;
2371	break;
2372
2373	case iss_t::XTN_MMU_DCACHE_PA_INV: // dcache, dtlb & itlb access
2374	r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA;
2375	if (sizeof(paddr_t) <= 32) {
2376	assert(r_mmu_word_hi.read() == 0 &&
2377	"high bits should be 0 for 32bit paddr");
2378	r_dcache_p0_paddr =
2379	(paddr_t)r_mmu_word_lo.read();
2380	} else {
2381	r_dcache_p0_paddr =
2382	(paddr_t)r_mmu_word_hi.read() << 32 \|
2383	(paddr_t)r_mmu_word_lo.read();
2384	}
2385	break;
2386
2387	case iss_t::XTN_DCACHE_FLUSH: // itlb and dtlb must be reset
2388	r_dcache_flush_count = 0;
2389	r_dcache_fsm = DCACHE_XTN_DC_FLUSH;
2390	break;
2391
2392	case iss_t::XTN_ICACHE_INVAL: // icache and itlb access
2393	r_dcache_xtn_req = true;
2394	r_dcache_fsm = DCACHE_XTN_IC_INVAL_VA;
2395	break;
2396
2397	case iss_t::XTN_MMU_ICACHE_PA_INV: // icache access
2398	r_dcache_xtn_req = true;
2399	r_dcache_fsm = DCACHE_XTN_IC_INVAL_PA;
2400	break;
2401
2402	case iss_t::XTN_ICACHE_FLUSH: // icache access
2403	r_dcache_xtn_req = true;
2404	r_dcache_fsm = DCACHE_XTN_IC_FLUSH;
2405	break;
2406
2407	case iss_t::XTN_SYNC: // wait until write buffer empty
2408	r_dcache_fsm = DCACHE_XTN_SYNC;
2409	break;
2410
2411	case iss_t::XTN_MMU_WORD_LO: // no cache or tlb access
2412	r_mmu_word_lo = m_dreq.wdata;
2413	m_drsp.valid = true;
2414	r_dcache_fsm = DCACHE_IDLE;
2415	break;
2416
2417	case iss_t::XTN_MMU_WORD_HI: // no cache or tlb access
2418	r_mmu_word_hi = m_dreq.wdata;
2419	m_drsp.valid = true;
2420	r_dcache_fsm = DCACHE_IDLE;
2421	break;
2422
2423	case iss_t::XTN_ICACHE_PREFETCH: // not implemented : no action
2424	case iss_t::XTN_DCACHE_PREFETCH: // not implemented : no action
2425	m_drsp.valid = true;
2426	r_dcache_fsm = DCACHE_IDLE;
2427	break;
2428
2429	default:
2430	r_mmu_detr = MMU_WRITE_UNDEFINED_XTN;
2431	r_mmu_dbvar = m_dreq.addr;
2432	m_drsp.valid = true;
2433	m_drsp.error = true;
2434	r_dcache_fsm = DCACHE_IDLE;
2435	break;
2436	} // end switch xtn_opcode
2437	} // end else
2438	r_dcache_p0_valid = false;
2439	} // end if XTN_WRITE
2440
2441	// Handling read/write/ll/sc processor requests.
2442	// The dtlb and dcache can be activated or not.
2443	// We compute the physical address, the cacheability, and check processor request.
2444	// - If DTLB not activated : cacheability is defined by the segment table,
2445	// the physical address is equal to the virtual address (identity mapping)
2446	// - If DTLB activated : cacheability is defined by the C bit in the PTE,
2447	// the physical address is obtained from the TLB, and the U & W bits
2448	// of the PTE are checked.
2449	// The processor request is decoded only if the TLB is not activated or if
2450	// the virtual address hits in tLB and access rights are OK.
2451	// We call the TLB_MISS sub-fsm in case of dtlb miss.
2452	else
2453	{
2454	bool valid_req = false;
2455	bool cacheable = false;
2456	paddr_t paddr = 0;
2457
2458	if ( not (r_mmu_mode.read() & DATA_TLB_MASK) ) // dtlb not activated
2459	{
2460	valid_req = true;
2461
2462	// cacheability
2463	if ( not (r_mmu_mode.read() & DATA_CACHE_MASK) ) cacheable = false;
2464	else cacheable = m_cacheability_table[m_dreq.addr];
2465
2466	// physical address
2467	paddr = (paddr_t)m_dreq.addr;
2468	}
2469	else // dtlb activated
2470	{
2471	if ( tlb_hit ) // tlb hit
2472	{
2473	// cacheability
2474	if ( not (r_mmu_mode.read() & DATA_CACHE_MASK) ) cacheable = false;
2475	else cacheable = tlb_flags.c;
2476
2477	// access rights checking
2478	if ( not tlb_flags.u and (m_dreq.mode == iss_t::MODE_USER))
2479	{
2480	if ( (m_dreq.type == iss_t::DATA_READ) or (m_dreq.type == iss_t::DATA_LL) )
2481	r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION;
2482	else
2483	r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION;
2484
2485	r_mmu_dbvar = m_dreq.addr;
2486	m_drsp.valid = true;
2487	m_drsp.error = true;
2488	m_drsp.rdata = 0;
2489	#if DEBUG_DCACHE
2490	if ( m_debug_dcache_fsm )
2491	{
2492	std::cout << " <PROC.DCACHE_IDLE> HIT in dtlb, but privilege violation" << std::endl;
2493	}
2494	#endif
2495	}
2496	else if ( not tlb_flags.w and
2497	((m_dreq.type == iss_t::DATA_WRITE) or
2498	(m_dreq.type == iss_t::DATA_SC)) )
2499	{
2500	r_mmu_detr = MMU_WRITE_ACCES_VIOLATION;
2501	r_mmu_dbvar = m_dreq.addr;
2502	m_drsp.valid = true;
2503	m_drsp.error = true;
2504	m_drsp.rdata = 0;
2505	#if DEBUG_DCACHE
2506	if ( m_debug_dcache_fsm )
2507	{
2508	std::cout << " <PROC.DCACHE_IDLE> HIT in dtlb, but writable violation" << std::endl;
2509	}
2510	#endif
2511	}
2512	else
2513	{
2514	valid_req = true;
2515	}
2516
2517	// physical address
2518	paddr = tlb_paddr;
2519	}
2520	else // tlb miss
2521	{
2522	r_dcache_tlb_vaddr = m_dreq.addr;
2523	r_dcache_tlb_ins = false;
2524	r_dcache_fsm = DCACHE_TLB_MISS;
2525	}
2526	} // end DTLB activated
2527
2528	if ( valid_req ) // processor request is valid after TLB check
2529	{
2530	// physical address and cacheability registration
2531	r_dcache_p0_paddr = paddr;
2532	r_dcache_p0_cacheable = cacheable;
2533
2534	// READ or LL request
2535	// The read requests are taken only if the write pipe-line is empty.
2536	// If dcache hit, dtlb hit, and speculative PPN OK, data in one cycle.
2537	// If speculative access is KO we just pay one extra cycle.
2538	// If dcache miss, we go to DCACHE_MISS_VICTIM state.
2539	// If uncacheable, we go to DCACHE_UNC_WAIT state.
2540	// In case of LL, the LL registration is done when the data is returned:
2541	// in DCACHE_IDLE if cacheable / in DCACHE_UNC_WAIT if uncacheable
2542	if ( ((m_dreq.type == iss_t::DATA_READ) or (m_dreq.type == iss_t::DATA_LL))
2543	and not r_dcache_p0_valid.read() and not r_dcache_p1_valid.read() )
2544	{
2545	if ( cacheable ) // cacheable read
2546	{
2547	// if the speculative access is illegal, we pay an extra cycle
2548	if ( (r_dcache_p0_paddr.read() & ~PAGE_K_MASK)
2549	!= (paddr & ~PAGE_K_MASK))
2550	{
2551	#ifdef INSTRUMENTATION
2552	m_cpt_dcache_spec_miss++;
2553	#endif
2554	#if DEBUG_DCACHE
2555	if ( m_debug_dcache_fsm )
2556	{
2557	std::cout << " <PROC.DCACHE_IDLE> Speculative access miss" << std::endl;
2558	}
2559	#endif
2560	}
2561	// if cache miss, try to get the missing line
2562	else if ( not cache_hit )
2563	{
2564	#ifdef INSTRUMENTATION
2565	m_cpt_dcache_miss++;
2566	#endif
2567	r_dcache_vci_paddr = paddr;
2568	r_dcache_vci_miss_req = true;
2569	r_dcache_miss_type = PROC_MISS;
2570	r_dcache_fsm = DCACHE_MISS_VICTIM;
2571	}
2572	// if cache hit return the data
2573	else
2574	{
2575	#ifdef INSTRUMENTATION
2576	m_cpt_data_read++;
2577	#endif
2578	m_drsp.valid = true;
2579	m_drsp.rdata = cache_rdata;
2580
2581	// makes reservation in case of LL
2582	if ( m_dreq.type == iss_t::DATA_LL )
2583	{
2584	r_dcache_ll_valid = true;
2585	r_dcache_ll_vaddr = m_dreq.addr;
2586	r_dcache_ll_data = cache_rdata;
2587	}
2588	#if DEBUG_DCACHE
2589	if ( m_debug_dcache_fsm )
2590	{
2591	std::cout << " <PROC.DCACHE_IDLE> HIT in dcache" << std::endl;
2592	}
2593	#endif
2594	}
2595	}
2596	else // uncacheable read
2597	{
2598	r_dcache_vci_paddr = paddr;
2599	r_dcache_vci_unc_be = m_dreq.be;
2600	r_dcache_vci_unc_req = true;
2601	r_dcache_fsm = DCACHE_UNC_WAIT;
2602	}
2603
2604	r_dcache_p0_valid = false;
2605	} // end READ or LL
2606
2607	// WRITE request:
2608	// If the TLB is activated and the PTE Dirty bit is not set, we stall
2609	// the processor and set the Dirty bit before handling the write request.
2610	// If we don't need to set the Dirty bit, we can acknowledge
2611	// the processor request, as the write arguments (including the
2612	// physical address) are registered in r_dcache_p0 registers:
2613	// We simply activate the P1 pipeline stage.
2614	else if ( m_dreq.type == iss_t::DATA_WRITE )
2615	{
2616	if ( (r_mmu_mode.read() & DATA_TLB_MASK )
2617	and not tlb_flags.d ) // Dirty bit must be set
2618	{
2619	// The PTE physical address is obtained from the nline value (dtlb),
2620	// and the word index (proper bits of the virtual address)
2621	if ( tlb_flags.b ) // PTE1
2622	{
2623	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2624	(paddr_t)((m_dreq.addr>>19) & 0x3c);
2625	}
2626	else // PTE2
2627	{
2628	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2629	(paddr_t)((m_dreq.addr>>9) & 0x38);
2630	}
2631	r_dcache_fsm = DCACHE_DIRTY_GET_PTE;
2632	r_dcache_p0_valid = false;
2633	}
2634	else // Write request accepted
2635	{
2636	#ifdef INSTRUMENTATION
2637	m_cpt_data_write++;
2638	#endif
2639	m_drsp.valid = true;
2640	m_drsp.rdata = 0;
2641	r_dcache_p0_valid = true;
2642	}
2643	} // end WRITE
2644
2645	// SC request:
2646	// The SC requests are taken only if the write pipe-line is empty.
2647	// - if there is no valid registered LL, we just return rdata = 1
2648	// (atomic access failed) and the SC transaction is completed.
2649	// - if a valid LL reservation (with the same address) is registered,
2650	// we test if a DIRTY bit update is required.
2651	// If the TLB is activated and the PTE Dirty bit is not set, we stall
2652	// the processor and set the Dirty bit before handling the write request.
2653	// If we don't need to set the Dirty bit, we request a SC transaction
2654	// to CMD FSM and go to DCACHE_SC_WAIT state, that will return
2655	// the response to the processor.
2656	// We don't check a possible write hit in dcache, as the cache update
2657	// is done by the coherence transaction induced by the SC...
2658	else if ( ( m_dreq.type == iss_t::DATA_SC )
2659	and not r_dcache_p0_valid.read() and not r_dcache_p1_valid.read() )
2660	{
2661	if ( (r_dcache_ll_vaddr.read() != m_dreq.addr)
2662	or not r_dcache_ll_valid.read() ) // no valid registered LL
2663	{
2664	#ifdef INSTRUMENTATION
2665	m_cpt_data_sc++;
2666	#endif
2667	m_drsp.valid = true;
2668	m_drsp.rdata = 1;
2669	r_dcache_ll_valid = false;
2670	}
2671	else // valid registered LL
2672	{
2673	if ( (r_mmu_mode.read() & DATA_TLB_MASK )
2674	and not tlb_flags.d ) // Dirty bit must be set
2675	{
2676	// The PTE physical address is obtained from the nline value (dtlb),
2677	// and the word index (virtual address)
2678	if ( tlb_flags.b ) // PTE1
2679	{
2680	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2681	(paddr_t)((m_dreq.addr>>19) & 0x3c);
2682	}
2683	else // PTE2
2684	{
2685	r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) \|
2686	(paddr_t)((m_dreq.addr>>9) & 0x38);
2687	}
2688	r_dcache_fsm = DCACHE_DIRTY_GET_PTE;
2689	}
2690	else // SC request accepted
2691	{
2692	#ifdef INSTRUMENTATION
2693	m_cpt_data_sc++;
2694	#endif
2695
2696	r_dcache_vci_paddr = paddr;
2697	r_dcache_vci_sc_req = true;
2698	r_dcache_vci_sc_old = r_dcache_ll_data.read();
2699	r_dcache_vci_sc_new = m_dreq.wdata;
2700	r_dcache_ll_valid = false;
2701	r_dcache_fsm = DCACHE_SC_WAIT;
2702	}
2703	}
2704	r_dcache_p0_valid = false;
2705	} // end SC
2706	else
2707	{
2708	r_dcache_p0_valid = false;
2709	}
2710	} // end valid_req
2711	else
2712	{
2713	r_dcache_p0_valid = false;
2714	}
2715	} // end if read/write/ll/sc request
2716	} // end dreq.valid
2717
2718	// itlb miss request
2719	else if ( r_icache_tlb_miss_req.read() )
2720	{
2721	r_dcache_tlb_ins = true;
2722	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
2723	r_dcache_fsm = DCACHE_TLB_MISS;
2724	r_dcache_p0_valid = r_dcache_p0_valid.read() and write_pipe_frozen;
2725	}
2726	else
2727	{
2728	r_dcache_p0_valid = r_dcache_p0_valid.read() and write_pipe_frozen;
2729	} // end P0 pipe stage
2730	break;
2731	}
2732	/////////////////////
2733	case DCACHE_TLB_MISS: // This is the entry point for the sub-fsm handling all tlb miss.
2734	// Input arguments are:
2735	// - r_dcache_tlb_vaddr
2736	// - r_dcache_tlb_ins (true when itlb miss)
2737	// The sub-fsm access the dcache to find the missing TLB entry,
2738	// and activates the cache miss procedure in case of miss.
2739	// It bypass the first level page table access if possible.
2740	// It uses atomic access to update the R/L access bits
2741	// in the page table if required.
2742	// It directly updates the itlb or dtlb, and writes into the
2743	// r_mmu_ins_* or r_mmu_data* error reporting registers.
2744	{
2745	uint32_t ptba = 0;
2746	bool bypass;
2747	paddr_t pte_paddr;
2748
2749	// evaluate bypass in order to skip first level page table access
2750	if ( r_dcache_tlb_ins.read() ) // itlb miss
2751	{
2752	bypass = r_itlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba);
2753	}
2754	else // dtlb miss
2755	{
2756	bypass = r_dtlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba);
2757	}
2758
2759	if ( not bypass ) // Try to read PTE1/PTD1 in dcache
2760	{
2761	pte_paddr = (paddr_t)r_mmu_ptpr.read() << (INDEX1_NBITS+2) \|
2762	(paddr_t)((r_dcache_tlb_vaddr.read() >> PAGE_M_NBITS) << 2);
2763	r_dcache_tlb_paddr = pte_paddr;
2764	r_dcache_fsm = DCACHE_TLB_PTE1_GET;
2765	}
2766	else // Try to read PTE2 in dcache
2767	{
2768	pte_paddr = (paddr_t)ptba << PAGE_K_NBITS \|
2769	(paddr_t)(r_dcache_tlb_vaddr.read()&PTD_ID2_MASK)>>(PAGE_K_NBITS-3);
2770	r_dcache_tlb_paddr = pte_paddr;
2771	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
2772	}
2773
2774	#if DEBUG_DCACHE
2775	if ( m_debug_dcache_fsm )
2776	{
2777	if ( r_dcache_tlb_ins.read() )
2778	{
2779	std::cout << " <PROC.DCACHE_TLB_MISS> ITLB miss";
2780	}
2781	else
2782	{
2783	std::cout << " <PROC.DCACHE_TLB_MISS> DTLB miss";
2784	}
2785	std::cout << " / VADDR = " << std::hex << r_dcache_tlb_vaddr.read()
2786	<< " / BYPASS = " << bypass
2787	<< " / PTE_ADR = " << pte_paddr << std::endl;
2788	}
2789	#endif
2790
2791	break;
2792	}
2793	/////////////////////////
2794	case DCACHE_TLB_PTE1_GET: // try to read a PT1 entry in dcache
2795	{
2796	uint32_t entry;
2797	size_t way;
2798	size_t set;
2799	size_t word;
2800
2801	bool hit = r_dcache.read( r_dcache_tlb_paddr.read(),
2802	&entry,
2803	&way,
2804	&set,
2805	&word );
2806	#ifdef INSTRUMENTATION
2807	m_cpt_dcache_data_read++;
2808	m_cpt_dcache_dir_read++;
2809	#endif
2810	if ( hit ) // hit in dcache
2811	{
2812	if ( not (entry & PTE_V_MASK) ) // unmapped
2813	{
2814	if ( r_dcache_tlb_ins.read() )
2815	{
2816	r_mmu_ietr = MMU_READ_PT1_UNMAPPED;
2817	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
2818	r_icache_tlb_miss_req = false;
2819	r_icache_tlb_rsp_error = true;
2820	}
2821	else
2822	{
2823	r_mmu_detr = MMU_READ_PT1_UNMAPPED;
2824	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
2825	m_drsp.valid = true;
2826	m_drsp.error = true;
2827	}
2828	r_dcache_fsm = DCACHE_IDLE;
2829
2830	#if DEBUG_DCACHE
2831	if ( m_debug_dcache_fsm )
2832	{
2833	std::cout << " <PROC.DCACHE_TLB_PTE1_GET> HIT in dcache, but unmapped"
2834	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
2835	<< std::dec << " / way = " << way
2836	<< std::dec << " / set = " << set
2837	<< std::dec << " / word = " << word
2838	<< std::hex << " / PTE1 = " << entry << std::endl;
2839	}
2840	#endif
2841
2842	}
2843	else if( entry & PTE_T_MASK ) // PTD : me must access PT2
2844	{
2845	// mark the cache line ac containing a PTD
2846	r_dcache_contains_ptd[m_dcache_sets*way+set] = true;
2847
2848	// register bypass
2849	if ( r_dcache_tlb_ins.read() ) // itlb
2850	{
2851	r_itlb.set_bypass(r_dcache_tlb_vaddr.read(),
2852	entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1),
2853	r_dcache_tlb_paddr.read() >> (uint32_log2(m_icache_words<<2)));
2854	}
2855	else // dtlb
2856	{
2857	r_dtlb.set_bypass(r_dcache_tlb_vaddr.read(),
2858	entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1),
2859	r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2));
2860	}
2861	r_dcache_tlb_paddr = (paddr_t)(entry & ((1<<(m_paddr_nbits-PAGE_K_NBITS))-1)) << PAGE_K_NBITS \|
2862	(paddr_t)(((r_dcache_tlb_vaddr.read() & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3);
2863	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
2864
2865	#if DEBUG_DCACHE
2866	if ( m_debug_dcache_fsm )
2867	{
2868	std::cout << " <PROC.DCACHE_TLB_PTE1_GET> HIT in dcache"
2869	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
2870	<< std::dec << " / way = " << way
2871	<< std::dec << " / set = " << set
2872	<< std::dec << " / word = " << word
2873	<< std::hex << " / PTD = " << entry << std::endl;
2874	}
2875	#endif
2876	}
2877	else // PTE1 : we must update the TLB
2878	{
2879	r_dcache_in_tlb[m_icache_sets*way+set] = true;
2880	r_dcache_tlb_pte_flags = entry;
2881	r_dcache_tlb_cache_way = way;
2882	r_dcache_tlb_cache_set = set;
2883	r_dcache_tlb_cache_word = word;
2884	r_dcache_fsm = DCACHE_TLB_PTE1_SELECT;
2885
2886	#if DEBUG_DCACHE
2887	if ( m_debug_dcache_fsm )
2888	{
2889	std::cout << " <PROC.DCACHE_TLB_PTE1_GET> HIT in dcache"
2890	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
2891	<< std::dec << " / way = " << way
2892	<< std::dec << " / set = " << set
2893	<< std::dec << " / word = " << word
2894	<< std::hex << " / PTE1 = " << entry << std::endl;
2895	}
2896	#endif
2897	}
2898	}
2899	else // we must load the missing cache line in dcache
2900	{
2901	r_dcache_vci_miss_req = true;
2902	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
2903	r_dcache_miss_type = PTE1_MISS;
2904	r_dcache_fsm = DCACHE_MISS_VICTIM;
2905
2906	#if DEBUG_DCACHE
2907	if ( m_debug_dcache_fsm )
2908	{
2909	std::cout << " <PROC.DCACHE_TLB_PTE1_GET> MISS in dcache:"
2910	<< " PTE1 address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
2911	}
2912	#endif
2913	}
2914	break;
2915	}
2916	////////////////////////////
2917	case DCACHE_TLB_PTE1_SELECT: // select a slot for PTE1
2918	{
2919	size_t way;
2920	size_t set;
2921
2922	if ( r_dcache_tlb_ins.read() )
2923	{
2924	r_itlb.select( r_dcache_tlb_vaddr.read(),
2925	true, // PTE1
2926	&way,
2927	&set );
2928	#ifdef INSTRUMENTATION
2929	m_cpt_itlb_read++;
2930	#endif
2931	}
2932	else
2933	{
2934	r_dtlb.select( r_dcache_tlb_vaddr.read(),
2935	true, // PTE1
2936	&way,
2937	&set );
2938	#ifdef INSTRUMENTATION
2939	m_cpt_dtlb_read++;
2940	#endif
2941	}
2942	r_dcache_tlb_way = way;
2943	r_dcache_tlb_set = set;
2944	r_dcache_fsm = DCACHE_TLB_PTE1_UPDT;
2945
2946	#if DEBUG_DCACHE
2947	if ( m_debug_dcache_fsm )
2948	{
2949	if ( r_dcache_tlb_ins.read() )
2950	std::cout << " <PROC.DCACHE_TLB_PTE1_SELECT> Select a slot in ITLB:";
2951	else
2952	std::cout << " <PROC.DCACHE_TLB_PTE1_SELECT> Select a slot in DTLB:";
2953	std::cout << " way = " << std::dec << way
2954	<< " / set = " << set << std::endl;
2955	}
2956	#endif
2957	break;
2958	}
2959	//////////////////////////
2960	case DCACHE_TLB_PTE1_UPDT: // write a new PTE1 in tlb after testing the L/R bit
2961	// if L/R bit already set, exit the sub-fsm
2962	// if not, the page table must be updated
2963	{
2964	paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2);
2965	uint32_t pte = r_dcache_tlb_pte_flags.read();
2966	bool updt = false;
2967	bool local = true;
2968
2969	// We should compute the access locality:
2970	// The PPN MSB bits define the destination cluster index.
2971	// The m_srcid_d MSB bits define the source cluster index.
2972	// The number of bits to compare depends on the number of clusters,
2973	// and can be obtained in the mapping table.
2974	// As long as this computation is not done, all access are local.
2975
2976	if ( local ) // local access
2977	{
2978	if ( not ((pte & PTE_L_MASK) == PTE_L_MASK) ) // we must set the L bit
2979	{
2980	updt = true;
2981	r_dcache_vci_sc_old = pte;
2982	r_dcache_vci_sc_new = pte \| PTE_L_MASK;
2983	pte = pte \| PTE_L_MASK;
2984	r_dcache_tlb_pte_flags = pte;
2985	}
2986	}
2987	else // remote access
2988	{
2989	if ( not ((pte & PTE_R_MASK) == PTE_R_MASK) ) // we must set the R bit
2990	{
2991	updt = true;
2992	r_dcache_vci_sc_old = pte;
2993	r_dcache_vci_sc_new = pte \| PTE_R_MASK;
2994	pte = pte \| PTE_R_MASK;
2995	r_dcache_tlb_pte_flags = pte;
2996	}
2997	}
2998
2999	// update TLB
3000	if ( r_dcache_tlb_ins.read() )
3001	{
3002	r_itlb.write( true, // 2M page
3003	pte,
3004	0, // argument unused for a PTE1
3005	r_dcache_tlb_vaddr.read(),
3006	r_dcache_tlb_way.read(),
3007	r_dcache_tlb_set.read(),
3008	nline );
3009	#ifdef INSTRUMENTATION
3010	m_cpt_itlb_write++;
3011	#endif
3012	}
3013	else
3014	{
3015	r_dtlb.write( true, // 2M page
3016	pte,
3017	0, // argument unused for a PTE1
3018	r_dcache_tlb_vaddr.read(),
3019	r_dcache_tlb_way.read(),
3020	r_dcache_tlb_set.read(),
3021	nline );
3022	#ifdef INSTRUMENTATION
3023	m_cpt_dtlb_write++;
3024	#endif
3025	}
3026	// next state
3027	if ( updt ) r_dcache_fsm = DCACHE_TLB_LR_UPDT; // dcache and page table update
3028	else r_dcache_fsm = DCACHE_TLB_RETURN; // exit sub-fsm
3029
3030	#if DEBUG_DCACHE
3031	if ( m_debug_dcache_fsm )
3032	{
3033	if ( r_dcache_tlb_ins.read() )
3034	{
3035	std::cout << " <PROC.DCACHE_TLB_PTE1_UPDT> write PTE1 in ITLB";
3036	std::cout << " / set = " << std::dec << r_dcache_tlb_set.read()
3037	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3038	r_itlb.printTrace();
3039	}
3040	else
3041	{
3042	std::cout << " <PROC.DCACHE_TLB_PTE1_UPDT> write PTE1 in DTLB";
3043	std::cout << " / set = " << std::dec << r_dcache_tlb_set.read()
3044	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3045	r_dtlb.printTrace();
3046	}
3047
3048	}
3049	#endif
3050	break;
3051	}
3052	/////////////////////////
3053	case DCACHE_TLB_PTE2_GET: // Try to get a PTE2 (64 bits) in the dcache
3054	{
3055	uint32_t pte_flags;
3056	uint32_t pte_ppn;
3057	size_t way;
3058	size_t set;
3059	size_t word;
3060
3061	bool hit = r_dcache.read( r_dcache_tlb_paddr.read(),
3062	&pte_flags,
3063	&pte_ppn,
3064	&way,
3065	&set,
3066	&word );
3067	#ifdef INSTRUMENTATION
3068	m_cpt_dcache_data_read++;
3069	m_cpt_dcache_dir_read++;
3070	#endif
3071	if ( hit ) // request hits in dcache
3072	{
3073	if ( not (pte_flags & PTE_V_MASK) ) // unmapped
3074	{
3075	if ( r_dcache_tlb_ins.read() )
3076	{
3077	r_mmu_ietr = MMU_READ_PT2_UNMAPPED;
3078	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3079	r_icache_tlb_miss_req = false;
3080	r_icache_tlb_rsp_error = true;
3081	}
3082	else
3083	{
3084	r_mmu_detr = MMU_READ_PT2_UNMAPPED;
3085	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3086	m_drsp.valid = true;
3087	m_drsp.error = true;
3088	}
3089	r_dcache_fsm = DCACHE_IDLE;
3090
3091	#if DEBUG_DCACHE
3092	if ( m_debug_dcache_fsm )
3093	{
3094	std::cout << " <PROC.DCACHE_TLB_PTE2_GET> HIT in dcache, but PTE is unmapped"
3095	<< " PTE_FLAGS = " << std::hex << pte_flags
3096	<< " PTE_PPN = " << std::hex << pte_ppn << std::endl;
3097	}
3098	#endif
3099	}
3100	else // mapped : we must update the TLB
3101	{
3102	r_dcache_in_tlb[m_dcache_sets*way+set] = true;
3103	r_dcache_tlb_pte_flags = pte_flags;
3104	r_dcache_tlb_pte_ppn = pte_ppn;
3105	r_dcache_tlb_cache_way = way;
3106	r_dcache_tlb_cache_set = set;
3107	r_dcache_tlb_cache_word = word;
3108	r_dcache_fsm = DCACHE_TLB_PTE2_SELECT;
3109
3110	#if DEBUG_DCACHE
3111	if ( m_debug_dcache_fsm )
3112	{
3113	std::cout << " <PROC.DCACHE_TLB_PTE2_GET> HIT in dcache:"
3114	<< " PTE_FLAGS = " << std::hex << pte_flags
3115	<< " PTE_PPN = " << std::hex << pte_ppn << std::endl;
3116	}
3117	#endif
3118	}
3119	}
3120	else // we must load the missing cache line in dcache
3121	{
3122	r_dcache_fsm = DCACHE_MISS_VICTIM;
3123	r_dcache_vci_miss_req = true;
3124	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
3125	r_dcache_miss_type = PTE2_MISS;
3126
3127	#if DEBUG_DCACHE
3128	if ( m_debug_dcache_fsm )
3129	{
3130	std::cout << " <PROC.DCACHE_TLB_PTE2_GET> MISS in dcache:"
3131	<< " PTE address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
3132	}
3133	#endif
3134	}
3135	break;
3136	}
3137	////////////////////////////
3138	case DCACHE_TLB_PTE2_SELECT: // select a slot for PTE2
3139	{
3140	size_t way;
3141	size_t set;
3142
3143	if ( r_dcache_tlb_ins.read() )
3144	{
3145	r_itlb.select( r_dcache_tlb_vaddr.read(),
3146	false, // PTE2
3147	&way,
3148	&set );
3149	#ifdef INSTRUMENTATION
3150	m_cpt_itlb_read++;
3151	#endif
3152	}
3153	else
3154	{
3155	r_dtlb.select( r_dcache_tlb_vaddr.read(),
3156	false, // PTE2
3157	&way,
3158	&set );
3159	#ifdef INSTRUMENTATION
3160	m_cpt_dtlb_read++;
3161	#endif
3162	}
3163
3164	#if DEBUG_DCACHE
3165	if ( m_debug_dcache_fsm )
3166	{
3167	if ( r_dcache_tlb_ins.read() )
3168	std::cout << " <PROC.DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB:";
3169	else
3170	std::cout << " <PROC.DCACHE_TLB_PTE2_SELECT> Select a slot in DTLB:";
3171	std::cout << " way = " << std::dec << way
3172	<< " / set = " << set << std::endl;
3173	}
3174	#endif
3175	r_dcache_tlb_way = way;
3176	r_dcache_tlb_set = set;
3177	r_dcache_fsm = DCACHE_TLB_PTE2_UPDT;
3178	break;
3179	}
3180	//////////////////////////
3181	case DCACHE_TLB_PTE2_UPDT: // write a new PTE2 in tlb after testing the L/R bit
3182	// if L/R bit already set, exit the sub-fsm
3183	// if not, the page table must be updated by an atomic access
3184	{
3185	paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2);
3186	uint32_t pte_flags = r_dcache_tlb_pte_flags.read();
3187	uint32_t pte_ppn = r_dcache_tlb_pte_ppn.read();
3188	bool updt = false;
3189	bool local = true;
3190
3191	// We should compute the access locality:
3192	// The PPN MSB bits define the destination cluster index.
3193	// The m_srcid_d MSB bits define the source cluster index.
3194	// The number of bits to compare depends on the number of clusters,
3195	// and can be obtained in the mapping table.
3196	// As long as this computation is not done, all access are local.
3197
3198	if ( local ) // local access
3199	{
3200	if ( not ((pte_flags & PTE_L_MASK) == PTE_L_MASK) ) // we must set the L bit
3201	{
3202	updt = true;
3203	r_dcache_vci_sc_old = pte_flags;
3204	r_dcache_vci_sc_new = pte_flags \| PTE_L_MASK;
3205	pte_flags = pte_flags \| PTE_L_MASK;
3206	r_dcache_tlb_pte_flags = pte_flags;
3207	}
3208	}
3209	else // remote access
3210	{
3211	if ( not ((pte_flags & PTE_R_MASK) == PTE_R_MASK) ) // we must set the R bit
3212	{
3213	updt = true;
3214	r_dcache_vci_sc_old = pte_flags;
3215	r_dcache_vci_sc_new = pte_flags \| PTE_R_MASK;
3216	pte_flags = pte_flags \| PTE_R_MASK;
3217	r_dcache_tlb_pte_flags = pte_flags;
3218	}
3219	}
3220
3221	// update TLB for a PTE2
3222	if ( r_dcache_tlb_ins.read() )
3223	{
3224	r_itlb.write( false, // 4K page
3225	pte_flags,
3226	pte_ppn,
3227	r_dcache_tlb_vaddr.read(),
3228	r_dcache_tlb_way.read(),
3229	r_dcache_tlb_set.read(),
3230	nline );
3231	#ifdef INSTRUMENTATION
3232	m_cpt_itlb_write++;
3233	#endif
3234	}
3235	else
3236	{
3237	r_dtlb.write( false, // 4K page
3238	pte_flags,
3239	pte_ppn,
3240	r_dcache_tlb_vaddr.read(),
3241	r_dcache_tlb_way.read(),
3242	r_dcache_tlb_set.read(),
3243	nline );
3244	#ifdef INSTRUMENTATION
3245	m_cpt_dtlb_write++;
3246	#endif
3247	}
3248
3249	#if DEBUG_DCACHE
3250	if ( m_debug_dcache_fsm )
3251	{
3252	if ( r_dcache_tlb_ins.read() )
3253	{
3254	std::cout << " <PROC.DCACHE_TLB_PTE2_UPDT> write PTE2 in ITLB";
3255	std::cout << " / set = " << std::dec << r_dcache_tlb_set.read()
3256	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3257	r_itlb.printTrace();
3258	}
3259	else
3260	{
3261	std::cout << " <PROC.DCACHE_TLB_PTE2_UPDT> write PTE2 in DTLB";
3262	std::cout << " / set = " << std::dec << r_dcache_tlb_set.read()
3263	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3264	r_dtlb.printTrace();
3265	}
3266	}
3267	#endif
3268	// next state
3269	if ( updt ) r_dcache_fsm = DCACHE_TLB_LR_UPDT; // dcache and page table update
3270	else r_dcache_fsm = DCACHE_TLB_RETURN; // exit sub-fsm
3271	break;
3272	}
3273	////////////////////////
3274	case DCACHE_TLB_LR_UPDT: // update the dcache after a tlb miss (L/R bit),
3275	// request a SC transaction to CMD FSM
3276	{
3277	#if DEBUG_DCACHE
3278	if ( m_debug_dcache_fsm )
3279	{
3280	std::cout << " <PROC.DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit" << std::endl;
3281	}
3282	#endif
3283	r_dcache.write(r_dcache_tlb_cache_way.read(),
3284	r_dcache_tlb_cache_set.read(),
3285	r_dcache_tlb_cache_word.read(),
3286	r_dcache_tlb_pte_flags.read());
3287	#ifdef INSTRUMENTATION
3288	m_cpt_dcache_data_write++;
3289	#endif
3290	// r_dcache_vci_sc_old & r_dcache_vci_sc_new registers are already set
3291	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
3292	r_dcache_vci_sc_req = true;
3293	r_dcache_fsm = DCACHE_TLB_LR_WAIT;
3294	break;
3295	}
3296	////////////////////////
3297	case DCACHE_TLB_LR_WAIT: // Waiting a response to SC transaction.
3298	// We consume the response in rsp FIFO,
3299	// and exit the sub-fsm, but we don't
3300	// analyse the response, because we don't
3301	// care if the L/R bit update is not done.
3302	// We must take the coherence requests because
3303	// there is a risk of dead-lock
3304
3305	{
3306	// external coherence request
3307	if ( r_tgt_dcache_req )
3308	{
3309	r_dcache_fsm = DCACHE_CC_CHECK;
3310	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3311	break;
3312	}
3313
3314	if ( r_vci_rsp_data_error.read() ) // bus error
3315	{
3316	std::cout << "BUS ERROR in DCACHE_TLB_LR_WAIT state" << std::endl;
3317	std::cout << "This should not happen in this state" << std::endl;
3318	exit(0);
3319	}
3320	else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
3321	{
3322	#if DEBUG_DCACHE
3323	if ( m_debug_dcache_fsm )
3324	{
3325	std::cout << " <PROC.DCACHE_TLB_LR_WAIT> SC response received" << std::endl;
3326	}
3327	#endif
3328	vci_rsp_fifo_dcache_get = true;
3329	r_dcache_fsm = DCACHE_TLB_RETURN;
3330	}
3331	break;
3332	}
3333	///////////////////////
3334	case DCACHE_TLB_RETURN: // return to caller depending on tlb miss type
3335	{
3336	#if DEBUG_DCACHE
3337	if ( m_debug_dcache_fsm )
3338	{
3339	std::cout << " <PROC.DCACHE_TLB_RETURN> TLB MISS completed" << std::endl;
3340	}
3341	#endif
3342	if ( r_dcache_tlb_ins.read() ) r_icache_tlb_miss_req = false;
3343	r_dcache_fsm = DCACHE_IDLE;
3344	break;
3345	}
3346	///////////////////////
3347	case DCACHE_XTN_SWITCH: // Both itlb and dtlb must be flushed
3348	{
3349	if ( not r_dcache_xtn_req.read() )
3350	{
3351	r_dtlb.flush();
3352	r_dcache_fsm = DCACHE_IDLE;
3353	m_drsp.valid = true;
3354	}
3355	break;
3356	}
3357	/////////////////////
3358	case DCACHE_XTN_SYNC: // waiting until write buffer empty
3359	// The coherence request must be taken
3360	// as there is a risk of dead-lock
3361	{
3362	// external coherence request
3363	if ( r_tgt_dcache_req.read() )
3364	{
3365	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3366	r_dcache_fsm = DCACHE_CC_CHECK;
3367	}
3368
3369	if ( r_wbuf.empty() )
3370	{
3371	m_drsp.valid = true;
3372	r_dcache_fsm = DCACHE_IDLE;
3373	}
3374	break;
3375	}
3376	////////////////////////
3377	case DCACHE_XTN_IC_FLUSH: // Waiting completion of an XTN request to the ICACHE FSM
3378	case DCACHE_XTN_IC_INVAL_VA: // Caution : the itlb miss requests must be taken
3379	case DCACHE_XTN_IC_INVAL_PA: // because the XTN_ICACHE_INVAL request to icache
3380	case DCACHE_XTN_IT_INVAL: // can generate an itlb miss...
3381	{
3382	// external coherence request
3383	if ( r_tgt_dcache_req )
3384	{
3385	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3386	r_dcache_fsm = DCACHE_CC_CHECK;
3387	break;
3388	}
3389
3390	// itlb miss request
3391	if ( r_icache_tlb_miss_req.read() )
3392	{
3393	r_dcache_tlb_ins = true;
3394	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
3395	r_dcache_fsm = DCACHE_TLB_MISS;
3396	break;
3397	}
3398
3399	// test if XTN request to icache completed
3400	if ( not r_dcache_xtn_req.read() )
3401	{
3402	r_dcache_fsm = DCACHE_IDLE;
3403	m_drsp.valid = true;
3404	}
3405	break;
3406	}
3407	/////////////////////////
3408	case DCACHE_XTN_DC_FLUSH: // Invalidate sequencially all cache lines, using
3409	// the r_dcache_flush counter as a slot counter.
3410	// We loop in this state until all slots have been visited.
3411	// A cleanup request is generated for each valid line
3412	// and we are blocked until the previous cleanup is completed
3413	// Finally, both the itlb and dtlb are flushed
3414	// (including global entries)
3415	{
3416	if ( not r_dcache_cleanup_req )
3417	{
3418	paddr_t nline;
3419	size_t way = r_dcache_flush_count.read()/m_icache_sets;
3420	size_t set = r_dcache_flush_count.read()%m_icache_sets;
3421
3422	bool cleanup_req = r_dcache.inval( way,
3423	set,
3424	&nline );
3425	if ( cleanup_req )
3426	{
3427	r_dcache_cleanup_req = true;
3428	r_dcache_cleanup_line = nline;
3429	}
3430
3431	r_dcache_in_tlb[m_dcache_sets*way+set] = false;
3432	r_dcache_contains_ptd[m_dcache_sets*way+set] = false;
3433
3434	r_dcache_flush_count = r_dcache_flush_count.read() + 1;
3435
3436	if ( r_dcache_flush_count.read() == (m_dcache_sets*m_dcache_ways - 1) ) // last
3437	{
3438	r_dtlb.reset();
3439	r_itlb.reset();
3440	r_dcache_fsm = DCACHE_IDLE;
3441	m_drsp.valid = true;
3442	}
3443	}
3444	break;
3445	}
3446	/////////////////////////
3447	case DCACHE_XTN_DT_INVAL: // handling processor XTN_DTLB_INVAL request
3448	{
3449	r_dtlb.inval(r_dcache_p0_wdata.read());
3450	r_dcache_fsm = DCACHE_IDLE;
3451	m_drsp.valid = true;
3452	break;
3453	}
3454	////////////////////////////
3455	case DCACHE_XTN_DC_INVAL_VA: // selective cache line invalidate with virtual address
3456	// requires 3 cycles: access tlb, read cache, inval cache
3457	// we compute the physical address in this state
3458	{
3459	paddr_t paddr;
3460	bool hit;
3461
3462	if ( r_mmu_mode.read() & DATA_TLB_MASK ) // dtlb activated
3463	{
3464	#ifdef INSTRUMENTATION
3465	m_cpt_dtlb_read++;
3466	#endif
3467	hit = r_dtlb.translate( r_dcache_p0_wdata.read(),
3468	&paddr );
3469	}
3470	else // dtlb not activated
3471	{
3472	paddr = (paddr_t)r_dcache_p0_wdata.read();
3473	hit = true;
3474	}
3475
3476	if ( hit ) // tlb hit
3477	{
3478	r_dcache_p0_paddr = paddr;
3479	r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA;
3480	}
3481	else // tlb miss
3482	{
3483	#ifdef INSTRUMENTATION
3484	m_cpt_dtlb_miss++;
3485	#endif
3486	r_dcache_tlb_ins = false; // dtlb
3487	r_dcache_tlb_vaddr = r_dcache_p0_wdata.read();
3488	r_dcache_fsm = DCACHE_TLB_MISS;
3489	}
3490
3491	#if DEBUG_DCACHE
3492	if ( m_debug_dcache_fsm )
3493	{
3494	std::cout << " <PROC.DCACHE_XTN_DC_INVAL_VA> Compute physical address" << std::hex
3495	<< " / VADDR = " << r_dcache_p0_wdata.read()
3496	<< " / PADDR = " << paddr << std::endl;
3497	}
3498	#endif
3499
3500	break;
3501	}
3502	////////////////////////////
3503	case DCACHE_XTN_DC_INVAL_PA: // selective cache line invalidate with physical address
3504	// requires 2 cycles: read cache / inval cache
3505	// In this state we read dcache.
3506	{
3507	uint32_t data;
3508	size_t way;
3509	size_t set;
3510	size_t word;
3511	bool hit = r_dcache.read( r_dcache_p0_paddr.read(),
3512	&data,
3513	&way,
3514	&set,
3515	&word );
3516	#ifdef INSTRUMENTATION
3517	m_cpt_dcache_data_read++;
3518	m_cpt_dcache_dir_read++;
3519	#endif
3520	if ( hit ) // inval to be done
3521	{
3522	r_dcache_xtn_way = way;
3523	r_dcache_xtn_set = set;
3524	r_dcache_fsm = DCACHE_XTN_DC_INVAL_GO;
3525	}
3526	else // miss : nothing to do
3527	{
3528	r_dcache_fsm = DCACHE_IDLE;
3529	m_drsp.valid = true;
3530	}
3531
3532	#if DEBUG_DCACHE
3533	if ( m_debug_dcache_fsm )
3534	{
3535	std::cout << " <PROC.DCACHE_XTN_DC_INVAL_PA> Test hit in dcache" << std::hex
3536	<< " / PADDR = " << r_dcache_p0_paddr.read() << std::dec
3537	<< " / HIT = " << hit
3538	<< " / SET = " << set
3539	<< " / WAY = " << way << std::endl;
3540	}
3541	#endif
3542	break;
3543	}
3544	////////////////////////////
3545	case DCACHE_XTN_DC_INVAL_GO: // In this state, we invalidate the cache line
3546	// Blocked if previous cleanup not completed
3547	// Test if itlb or dtlb inval is required
3548	{
3549	if ( not r_dcache_cleanup_req.read() )
3550	{
3551	paddr_t nline;
3552	size_t way = r_dcache_xtn_way.read();
3553	size_t set = r_dcache_xtn_set.read();
3554	bool hit;
3555
3556	hit = r_dcache.inval( way,
3557	set,
3558	&nline );
3559	assert(hit && "XTN_DC_INVAL way/set should still be in cache");
3560
3561	// request cleanup
3562	r_dcache_cleanup_req = true;
3563	r_dcache_cleanup_line = nline;
3564
3565	// possible itlb & dtlb invalidate
3566	if ( r_dcache_in_tlb[way*m_dcache_sets+set] )
3567	{
3568	r_dcache_tlb_inval_line = nline;
3569	r_dcache_tlb_inval_count = 0;
3570	r_dcache_fsm_scan_save = DCACHE_XTN_DC_INVAL_END;
3571	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
3572	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
3573	}
3574	else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] )
3575	{
3576	r_itlb.reset();
3577	r_dtlb.reset();
3578	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
3579	r_dcache_fsm = DCACHE_IDLE;
3580	m_drsp.valid = true;
3581	}
3582	else
3583	{
3584	r_dcache_fsm = DCACHE_IDLE;
3585	m_drsp.valid = true;
3586	}
3587
3588	#if DEBUG_DCACHE
3589	if ( m_debug_dcache_fsm )
3590	{
3591	std::cout << " <PROC.DCACHE_XTN_DC_INVAL_GO> Actual dcache inval" << std::hex
3592	<< " / NLINE = " << nline << std::endl;
3593	}
3594	#endif
3595	}
3596	break;
3597	}
3598	//////////////////////////////
3599	case DCACHE_XTN_DC_INVAL_END: // send response to processor XTN request
3600	{
3601	r_dcache_fsm = DCACHE_IDLE;
3602	m_drsp.valid = true;
3603	break;
3604	}
3605	////////////////////////
3606	case DCACHE_MISS_VICTIM: // Selects a victim line if there is no pending cleanup
3607	// on the missing line, and if a new cleanup can be posted.
3608	// Set the r_dcache_cleanup_req flip-flop if required
3609	{
3610	size_t index; // unused
3611	bool hit = r_cleanup_buffer.hit( r_dcache_vci_paddr.read()>>(uint32_log2(m_dcache_words)+2), &index );
3612	if ( not hit and not r_dcache_cleanup_req.read() )
3613	{
3614	bool valid;
3615	size_t way;
3616	size_t set;
3617	paddr_t victim;
3618
3619	valid = r_dcache.victim_select( r_dcache_vci_paddr.read(),
3620	&victim,
3621	&way,
3622	&set );
3623	r_dcache_miss_way = way;
3624	r_dcache_miss_set = set;
3625
3626	if ( valid )
3627	{
3628	r_dcache_cleanup_req = true;
3629	r_dcache_cleanup_line = victim;
3630	r_dcache_fsm = DCACHE_MISS_INVAL;
3631	}
3632	else
3633	{
3634	r_dcache_fsm = DCACHE_MISS_WAIT;
3635	}
3636
3637	#if DEBUG_DCACHE
3638	if ( m_debug_dcache_fsm )
3639	{
3640	std::cout << " <PROC.DCACHE_MISS_VICTIM> Select a slot:" << std::dec
3641	<< " / WAY = " << way
3642	<< " / SET = " << set
3643	<< " / VALID = " << valid
3644	<< " / LINE = " << std::hex << victim << std::endl;
3645	}
3646	#endif
3647	}
3648	break;
3649	}
3650	///////////////////////
3651	case DCACHE_MISS_INVAL: // invalidate the victim line
3652	// and possibly request itlb or dtlb invalidate
3653	{
3654	paddr_t nline;
3655	size_t way = r_dcache_miss_way.read();
3656	size_t set = r_dcache_miss_set.read();
3657	bool hit;
3658
3659	hit = r_dcache.inval( way,
3660	set,
3661	&nline );
3662
3663	assert(hit && "selected way/set line should be in dcache");
3664
3665	#if DEBUG_DCACHE
3666	if ( m_debug_dcache_fsm )
3667	{
3668	std::cout << " <PROC.DCACHE_MISS_INVAL> inval line:" << std::dec
3669	<< " / way = " << way
3670	<< " / set = " << set
3671	<< " / nline = " << std::hex << nline << std::endl;
3672	}
3673	#endif
3674	// if selective itlb & dtlb invalidate are required
3675	// the miss response is not handled before invalidate completed
3676	if ( r_dcache_in_tlb[way*m_dcache_sets+set] )
3677	{
3678	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
3679	r_dcache_tlb_inval_line = nline;
3680	r_dcache_tlb_inval_count = 0;
3681	r_dcache_fsm_scan_save = DCACHE_MISS_WAIT;
3682	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
3683	}
3684	else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] )
3685	{
3686	r_itlb.reset();
3687	r_dtlb.reset();
3688	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
3689	r_dcache_fsm = DCACHE_MISS_WAIT;
3690	}
3691	else
3692	{
3693	r_dcache_fsm = DCACHE_MISS_WAIT;
3694	}
3695	break;
3696	}
3697	//////////////////////
3698	case DCACHE_MISS_WAIT: // waiting the response to a miss request from VCI_RSP FSM
3699	// This state is in charge of error signaling
3700	// There is 5 types of error depending on the requester
3701	{
3702	// external coherence request
3703	if ( r_tgt_dcache_req )
3704	{
3705	r_dcache_fsm_cc_save = r_dcache_fsm;
3706	r_dcache_fsm = DCACHE_CC_CHECK;
3707	break;
3708	}
3709
3710	if ( r_vci_rsp_data_error.read() ) // bus error
3711	{
3712	switch ( r_dcache_miss_type.read() )
3713	{
3714	case PROC_MISS:
3715	{
3716	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
3717	r_mmu_dbvar = r_dcache_p0_vaddr.read();
3718	m_drsp.valid = true;
3719	m_drsp.error = true;
3720	r_dcache_fsm = DCACHE_IDLE;
3721	break;
3722	}
3723	case PTE1_MISS:
3724	{
3725	if ( r_dcache_tlb_ins.read() )
3726	{
3727	r_mmu_ietr = MMU_READ_PT1_ILLEGAL_ACCESS;
3728	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3729	r_icache_tlb_miss_req = false;
3730	r_icache_tlb_rsp_error = true;
3731	}
3732	else
3733	{
3734	r_mmu_detr = MMU_READ_PT1_ILLEGAL_ACCESS;
3735	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3736	m_drsp.valid = true;
3737	m_drsp.error = true;
3738	}
3739	r_dcache_fsm = DCACHE_IDLE;
3740	break;
3741	}
3742	case PTE2_MISS:
3743	{
3744	if ( r_dcache_tlb_ins.read() )
3745	{
3746	r_mmu_ietr = MMU_READ_PT2_ILLEGAL_ACCESS;
3747	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3748	r_icache_tlb_miss_req = false;
3749	r_icache_tlb_rsp_error = true;
3750	}
3751	else
3752	{
3753	r_mmu_detr = MMU_READ_PT2_ILLEGAL_ACCESS;
3754	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3755	m_drsp.valid = true;
3756	m_drsp.error = true;
3757	}
3758	r_dcache_fsm = DCACHE_IDLE;
3759	break;
3760	}
3761	} // end switch type
3762	r_vci_rsp_data_error = false;
3763	}
3764	else if ( r_vci_rsp_fifo_dcache.rok() ) // valid response available
3765	{
3766	r_dcache_miss_word = 0;
3767	r_dcache_fsm = DCACHE_MISS_UPDT;
3768	}
3769	break;
3770	}
3771	//////////////////////
3772	case DCACHE_MISS_UPDT: // update the dcache (one word per cycle)
3773	// returns the response depending on the miss type
3774	{
3775	if ( r_vci_rsp_fifo_dcache.rok() ) // one word available
3776	{
3777	if ( r_dcache_miss_inval.read() ) // Matching coherence request
3778	// pop the FIFO, without cache update
3779	// send a cleanup for the missing line
3780	// if the previous cleanup is completed
3781	{
3782	if ( r_dcache_miss_word.read() < (m_dcache_words - 1) ) // not the last
3783	{
3784	vci_rsp_fifo_dcache_get = true;
3785	r_dcache_miss_word = r_dcache_miss_word.read() + 1;
3786	}
3787	else // last word
3788	{
3789	if ( not r_dcache_cleanup_req.read() ) // no pending cleanup
3790	{
3791	vci_rsp_fifo_dcache_get = true;
3792	r_dcache_cleanup_req = true;
3793	r_dcache_cleanup_line = r_dcache_vci_paddr.read() >>
3794	(uint32_log2(m_dcache_words)+2);
3795	r_dcache_miss_inval = false;
3796	r_dcache_fsm = DCACHE_IDLE;
3797	}
3798	}
3799	}
3800	else // No matching coherence request
3801	// pop the FIFO and update the cache
3802	// update the directory at the last word
3803	{
3804	size_t way = r_dcache_miss_way.read();
3805	size_t set = r_dcache_miss_set.read();
3806	size_t word = r_dcache_miss_word.read();
3807
3808	#ifdef INSTRUMENTATION
3809	m_cpt_dcache_data_write++;
3810	#endif
3811	r_dcache.write( way,
3812	set,
3813	word,
3814	r_vci_rsp_fifo_dcache.read());
3815
3816	vci_rsp_fifo_dcache_get = true;
3817	r_dcache_miss_word = r_dcache_miss_word.read() + 1;
3818
3819	// if last word, update directory, set in_tlb & contains_ptd bits
3820	if ( r_dcache_miss_word.read() == (m_dcache_words - 1) )
3821	{
3822
3823	#ifdef INSTRUMENTATION
3824	m_cpt_dcache_dir_write++;
3825	#endif
3826	r_dcache.victim_update_tag( r_dcache_vci_paddr.read(),
3827	r_dcache_miss_way.read(),
3828	r_dcache_miss_set.read() );
3829
3830	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
3831	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
3832
3833	if (r_dcache_miss_type.read()==PTE1_MISS) r_dcache_fsm = DCACHE_TLB_PTE1_GET;
3834	else if (r_dcache_miss_type.read()==PTE2_MISS) r_dcache_fsm = DCACHE_TLB_PTE2_GET;
3835	else r_dcache_fsm = DCACHE_IDLE;
3836	}
3837	}
3838
3839	#if DEBUG_DCACHE
3840	if ( m_debug_dcache_fsm )
3841	{
3842	if ( r_dcache_miss_inval.read() )
3843	{
3844	if ( r_dcache_miss_word.read() < m_dcache_words-1 )
3845	{
3846	std::cout << " <PROC.DCACHE_MISS_UPDT> Matching coherence request:"
3847	<< " pop the FIFO, don't update the cache" << std::endl;
3848	}
3849	else
3850	{
3851	std::cout << " <PROC.DCACHE_MISS_UPDT> Matching coherence request:"
3852	<< " last word : send a cleanup request " << std::endl;
3853	}
3854	}
3855	else
3856	{
3857	std::cout << " <PROC.DCACHE_MISS_UPDT> Write one word:"
3858	<< " address = " << std::hex << r_dcache_vci_paddr.read()
3859	<< " / data = " << r_vci_rsp_fifo_dcache.read()
3860	<< " / way = " << std::dec << r_dcache_miss_way.read()
3861	<< " / set = " << r_dcache_miss_set.read()
3862	<< " / word = " << r_dcache_miss_word.read() << std::endl;
3863	}
3864	}
3865	#endif
3866
3867	} // end if rok
3868	break;
3869	}
3870	/////////////////////
3871	case DCACHE_UNC_WAIT:
3872	{
3873	// external coherence request
3874	if ( r_tgt_dcache_req.read() )
3875	{
3876	r_dcache_fsm_cc_save = r_dcache_fsm;
3877	r_dcache_fsm = DCACHE_CC_CHECK;
3878	break;
3879	}
3880
3881	if ( r_vci_rsp_data_error.read() ) // bus error
3882	{
3883	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
3884	r_mmu_dbvar = m_dreq.addr;
3885	r_vci_rsp_data_error = false;
3886	m_drsp.error = true;
3887	m_drsp.valid = true;
3888	r_dcache_fsm = DCACHE_IDLE;
3889	break;
3890	}
3891	else if ( r_vci_rsp_fifo_dcache.rok() ) // data available
3892	{
3893	// consume data
3894	vci_rsp_fifo_dcache_get = true;
3895	r_dcache_fsm = DCACHE_IDLE;
3896
3897	// acknowledge the processor request if it has not been modified
3898	if ( m_dreq.valid and (m_dreq.addr == r_dcache_p0_vaddr.read()) )
3899	{
3900	m_drsp.valid = true;
3901	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
3902
3903	// makes reservation in case of LL
3904	if ( m_dreq.type == iss_t::DATA_LL )
3905	{
3906	r_dcache_ll_valid = true;
3907	r_dcache_ll_data = r_vci_rsp_fifo_dcache.read();
3908	r_dcache_ll_vaddr = m_dreq.addr;
3909	}
3910	}
3911	}
3912	break;
3913	}
3914	////////////////////
3915	case DCACHE_SC_WAIT: // waiting VCI response after a processor SC request
3916	{
3917	// external coherence request
3918	if ( r_tgt_dcache_req.read() )
3919	{
3920	r_dcache_fsm_cc_save = r_dcache_fsm;
3921	r_dcache_fsm = DCACHE_CC_CHECK;
3922	break;
3923	}
3924
3925	if ( r_vci_rsp_data_error.read() ) // bus error
3926	{
3927	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
3928	r_mmu_dbvar = m_dreq.addr;
3929	r_vci_rsp_data_error = false;
3930	m_drsp.error = true;
3931	m_drsp.valid = true;
3932	r_dcache_fsm = DCACHE_IDLE;
3933	break;
3934	}
3935	else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
3936	{
3937	vci_rsp_fifo_dcache_get = true;
3938	m_drsp.valid = true;
3939	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
3940	r_dcache_fsm = DCACHE_IDLE;
3941	}
3942	break;
3943	}
3944	//////////////////////////
3945	case DCACHE_DIRTY_GET_PTE: // This sub_fsm set the PTE Dirty bit in memory
3946	// before handling a processor WRITE or SC request
3947	// Input argument is r_dcache_dirty_paddr
3948	// In this first state, we get PTE value in dcache
3949	// and post a SC request to CMD FSM
3950	{
3951	// get PTE in dcache
3952	uint32_t pte;
3953	size_t way;
3954	size_t set;
3955	size_t word; // unused
3956	bool hit = r_dcache.read( r_dcache_dirty_paddr.read(),
3957	&pte,
3958	&way,
3959	&set,
3960	&word );
3961	#ifdef INSTRUMENTATION
3962	m_cpt_dcache_data_read++;
3963	m_cpt_dcache_dir_read++;
3964	#endif
3965	assert( hit and "error in DCACHE_DIRTY_TLB_SET: the PTE should be in dcache" );
3966
3967	// request sc transaction to CMD_FSM
3968	r_dcache_dirty_way = way;
3969	r_dcache_dirty_set = set;
3970	r_dcache_vci_sc_req = true;
3971	r_dcache_vci_paddr = r_dcache_dirty_paddr.read();
3972	r_dcache_vci_sc_old = pte;
3973	r_dcache_vci_sc_new = pte \| PTE_D_MASK;
3974	r_dcache_fsm = DCACHE_DIRTY_SC_WAIT;
3975
3976	#if DEBUG_DCACHE
3977	if ( m_debug_dcache_fsm )
3978	{
3979	std::cout << " <PROC.DCACHE_DIRTY_GET_PTE> Get PTE in dcache" << std::hex
3980	<< " / PTE_PADDR = " << r_dcache_dirty_paddr.read()
3981	<< " / PTE_VALUE = " << pte << std::dec
3982	<< " / CACHE_SET = " << set
3983	<< " / CACHE_WAY = " << way << std::endl;
3984	}
3985	#endif
3986	break;
3987	}
3988	//////////////////////////
3989	case DCACHE_DIRTY_SC_WAIT: // wait completion of SC for PTE Dirty bit
3990	// If PTE update is a success, return to IDLE state.
3991	// If PTE update is a failure, invalidate cache line
3992	// in DCACHE and invalidate the matching TLB entries.
3993	{
3994	// external coherence request
3995	if ( r_tgt_dcache_req )
3996	{
3997	r_dcache_fsm_cc_save = r_dcache_fsm;
3998	r_dcache_fsm = DCACHE_CC_CHECK;
3999	break;
4000	}
4001
4002	if ( r_vci_rsp_data_error.read() ) // bus error
4003	{
4004	std::cout << "BUS ERROR in DCACHE_DIRTY_SC_WAIT state" << std::endl;
4005	std::cout << "This should not happen in this state" << std::endl;
4006	exit(0);
4007	}
4008	else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
4009	{
4010	vci_rsp_fifo_dcache_get = true;
4011	if ( r_vci_rsp_fifo_dcache.read() == 0 ) // exit if dirty bit update atomic
4012	{
4013	r_dcache_fsm = DCACHE_IDLE;
4014
4015	#if DEBUG_DCACHE
4016	if ( m_debug_dcache_fsm )
4017	{
4018	std::cout << " <PROC.DCACHE_DIRTY_SC_WAIT> Dirty bit successfully set"
4019	<< std::endl;
4020	}
4021	#endif
4022	}
4023	else // invalidate the cache line TLBs
4024	{
4025
4026	#if DEBUG_DCACHE
4027	if ( m_debug_dcache_fsm )
4028	{
4029	std::cout << " <PROC.DCACHE_DIRTY_SC_WAIT> PTE modified : Inval cache line & TLBs"
4030	<< std::endl;
4031	}
4032	#endif
4033	paddr_t nline;
4034	size_t way = r_dcache_dirty_way.read();
4035	size_t set = r_dcache_dirty_set.read();
4036	bool hit;
4037
4038	hit = r_dcache.inval( way,
4039	set,
4040	&nline );
4041
4042	assert(hit && "PTE should still be in dcache");
4043
4044	// request cleanup
4045	r_dcache_cleanup_req = true;
4046	r_dcache_cleanup_line = nline;
4047
4048	if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // contains PTE
4049	{
4050	r_dcache_tlb_inval_line = nline;
4051	r_dcache_tlb_inval_count = 0;
4052	r_dcache_fsm_scan_save = DCACHE_IDLE;
4053	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4054	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
4055	}
4056	else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // contains PTD
4057	{
4058	r_itlb.reset();
4059	r_dtlb.reset();
4060	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
4061	r_dcache_fsm = DCACHE_IDLE;
4062	}
4063	else
4064	{
4065	r_dcache_fsm = DCACHE_IDLE;
4066	}
4067	}
4068	}
4069	break;
4070	}
4071	/////////////////////
4072	case DCACHE_CC_CHECK: // This state is the entry point for the sub-FSM
4073	// handling coherence requests.
4074	// If there is a matching pending miss on the modified cache
4075	// line this is signaled in the r_dcache_miss inval flip-flop.
4076	// If the updated (or invalidated) cache line has copies in TLBs
4077	// these TLB copies are invalidated.
4078	// The return state is defined in r_dcache_fsm_cc_save
4079	{
4080	paddr_t paddr = r_tgt_paddr.read();
4081	paddr_t mask = ~((m_dcache_words<<2)-1);
4082
4083
4084	if( (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) and
4085	((r_dcache_vci_paddr.read() & mask) == (paddr & mask)) ) // matching pending miss
4086	{
4087	r_dcache_miss_inval = true; // signaling the match
4088	r_tgt_dcache_req = false; // coherence request completed
4089	r_tgt_dcache_rsp = r_tgt_update.read(); // response required if update
4090	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4091
4092	#if DEBUG_DCACHE
4093	if ( m_debug_dcache_fsm )
4094	{
4095	std::cout << " <PROC.DCACHE_CC_CHECK> Coherence request matching a pending miss:"
4096	<< " address = " << std::hex << paddr << std::endl;
4097	}
4098	#endif
4099
4100	}
4101	else // no match
4102	{
4103	uint32_t rdata;
4104	size_t way;
4105	size_t set;
4106	size_t word;
4107
4108	bool hit = r_dcache.read(paddr,
4109	&rdata, // unused
4110	&way,
4111	&set,
4112	&word); // unused
4113	#ifdef INSTRUMENTATION
4114	m_cpt_dcache_data_read++;
4115	m_cpt_dcache_dir_read++;
4116	#endif
4117	r_dcache_cc_way = way;
4118	r_dcache_cc_set = set;
4119
4120	if ( hit and r_tgt_update.read() ) // hit update
4121	{
4122	r_dcache_fsm = DCACHE_CC_UPDT;
4123	r_dcache_cc_word = r_tgt_word_min.read();
4124	}
4125	else if ( hit and not r_tgt_update.read() ) // hit inval
4126	{
4127	r_dcache_fsm = DCACHE_CC_INVAL;
4128	}
4129	else // miss can happen
4130	{
4131	r_tgt_dcache_req = false;
4132	r_tgt_dcache_rsp = r_tgt_update.read();
4133	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4134	}
4135
4136	#if DEBUG_DCACHE
4137	if ( m_debug_dcache_fsm )
4138	{
4139
4140	std::cout << " <PROC.DCACHE_CC_CHECK> Coherence request received :"
4141	<< " address = " << std::hex << paddr << std::dec;
4142	if ( hit )
4143	{
4144	std::cout << " / HIT" << " / way = " << way << " / set = " << set << std::endl;
4145	}
4146	else
4147	{
4148	std::cout << " / MISS" << std::endl;
4149	}
4150	}
4151	#endif
4152
4153	}
4154	break;
4155	}
4156	/////////////////////
4157	case DCACHE_CC_INVAL: // invalidate one cache line
4158	// and test possible copies in TLBs
4159	{
4160	paddr_t nline;
4161	size_t way = r_dcache_cc_way.read();
4162	size_t set = r_dcache_cc_set.read();
4163	bool hit;
4164
4165	if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // selective TLB inval
4166	{
4167	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
4168	r_dcache_tlb_inval_line = nline;
4169	r_dcache_tlb_inval_count = 0;
4170	r_dcache_fsm_scan_save = r_dcache_fsm.read();
4171	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4172	}
4173	else // actual cache line inval
4174	{
4175	if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // TLB flush
4176	{
4177	r_itlb.reset();
4178	r_dtlb.reset();
4179	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
4180	}
4181	r_tgt_dcache_rsp = true;
4182	r_tgt_dcache_req = false;
4183	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4184
4185	hit = r_dcache.inval( way,
4186	set,
4187	&nline );
4188	#if DEBUG_DCACHE
4189	if ( m_debug_dcache_fsm )
4190	{
4191	std::cout << " <PROC.DCACHE_CC_INVAL> Invalidate cache line" << std::dec
4192	<< " / WAY = " << way
4193	<< " / SET = " << set << std::endl;
4194	}
4195	#endif
4196
4197	assert(hit && "CC_INVAL way/set should still be in dcache");
4198	}
4199	break;
4200	}
4201	///////////////////
4202	case DCACHE_CC_UPDT: // write one word per cycle (from word_min to word_max)
4203	// and test possible copies in TLBs
4204	{
4205	size_t word = r_dcache_cc_word.read();
4206	size_t way = r_dcache_cc_way.read();
4207	size_t set = r_dcache_cc_set.read();
4208	paddr_t nline = r_tgt_paddr.read() >> (uint32_log2(m_dcache_words)+2);
4209
4210	if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // selective TLB inval
4211	{
4212	r_dcache_in_tlb[way*m_dcache_sets+set] = false;
4213	r_dcache_tlb_inval_line = nline;
4214	r_dcache_tlb_inval_count = 0;
4215	r_dcache_fsm_scan_save = r_dcache_fsm.read();
4216	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4217	}
4218	else // cache update
4219	{
4220	if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // TLB flush
4221	{
4222	r_itlb.reset();
4223	r_dtlb.reset();
4224	r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
4225	}
4226
4227	r_dcache.write( way,
4228	set,
4229	word,
4230	r_tgt_buf[word],
4231	r_tgt_be[word] );
4232	#ifdef INSTRUMENTATION
4233	m_cpt_dcache_data_write++;
4234	#endif
4235	r_dcache_cc_word = word + 1;
4236
4237	#if DEBUG_DCACHE
4238	if ( m_debug_dcache_fsm )
4239	{
4240	std::cout << " <PROC.DCACHE_CC_UPDT> Update one word" << std::dec
4241	<< " / WAY = " << way
4242	<< " / SET = " << set
4243	<< " / WORD = " << word
4244	<< " / VALUE = " << std::hex << r_tgt_buf[word] << std::endl;
4245	}
4246	#endif
4247	if ( word == r_tgt_word_max.read() ) // last word
4248	{
4249	r_tgt_dcache_rsp = true;
4250	r_tgt_dcache_req = false;
4251	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4252	}
4253	}
4254
4255	break;
4256	}
4257	///////////////////////////
4258	case DCACHE_INVAL_TLB_SCAN: // Scan sequencially all TLB entries for both ITLB & DTLB
4259	// It makes the assumption that (m_itlb_sets == m_dtlb_sets)
4260	// and (m_itlb_ways == m_dtlb_ways)
4261	// We enter this state when a DCACHE line is modified,
4262	// and there is a copy in itlb or dtlb.
4263	// It can be caused by:
4264	// - a coherence inval or updt transaction,
4265	// - a line inval caused by a cache miss
4266	// - a processor XTN inval request,
4267	// - a WRITE hit,
4268	// - a Dirty bit update failure
4269	// Input arguments are:
4270	// - r_dcache_tlb_inval_line
4271	// - r_dcache_tlb_inval_count
4272	// - r_dcache_fsm_cc_save
4273	{
4274	paddr_t line = r_dcache_tlb_inval_line.read(); // nline
4275	size_t way = r_dcache_tlb_inval_count.read()/m_itlb_sets; // way
4276	size_t set = r_dcache_tlb_inval_count.read()%m_itlb_sets; // set
4277	bool ok;
4278
4279	ok = r_itlb.inval( line,
4280	way,
4281	set );
4282	#if DEBUG_DCACHE
4283	if ( m_debug_dcache_fsm and ok )
4284	{
4285	std::cout << " <PROC.DCACHE_INVAL_TLB_SCAN> Invalidate ITLB entry:" << std::hex
4286	<< " line = " << line << std::dec
4287	<< " / set = " << set
4288	<< " / way = " << way << std::endl;
4289	r_itlb.printTrace();
4290	}
4291	#endif
4292	ok = r_dtlb.inval( line,
4293	way,
4294	set );
4295	#if DEBUG_DCACHE
4296	if ( m_debug_dcache_fsm and ok )
4297	{
4298	std::cout << " <PROC.DCACHE_INVAL_TLB_SCAN> Invalidate DTLB entry:" << std::hex
4299	<< " line = " << line << std::dec
4300	<< " / set = " << set
4301	<< " / way = " << way << std::endl;
4302	r_dtlb.printTrace();
4303	}
4304	#endif
4305
4306	// return to the calling state when TLB inval completed
4307	if ( r_dcache_tlb_inval_count.read() == ((m_dtlb_sets*m_dtlb_ways)-1) )
4308	{
4309	r_dcache_fsm = r_dcache_fsm_scan_save.read();
4310	}
4311	r_dcache_tlb_inval_count = r_dcache_tlb_inval_count.read() + 1;
4312	break;
4313	}
4314	} // end switch r_dcache_fsm
4315
4316	///////////////// wbuf update //////////////////////////////////////////////////////
4317	r_wbuf.update();
4318
4319	//////////////// test processor frozen /////////////////////////////////////////////
4320	// The simulation exit if the number of consecutive frozen cycles
4321	// is larger than the m_max_frozen_cycles (constructor parameter)
4322	if ( (m_ireq.valid and not m_irsp.valid) or (m_dreq.valid and not m_drsp.valid) )
4323	{
4324	m_cpt_frz_cycles++; // used for instrumentation
4325	m_cpt_stop_simulation++; // used for debug
4326	if ( m_cpt_stop_simulation > m_max_frozen_cycles )
4327	{
4328	std::cout << std::dec << "ERROR in CC_VCACHE_WRAPPER " << name() << std::endl
4329	<< " stop at cycle " << m_cpt_total_cycles << std::endl
4330	<< " frozen since cycle " << m_cpt_total_cycles - m_max_frozen_cycles
4331	<< std::endl;
4332	exit(1);
4333	}
4334	}
4335	else
4336	{
4337	m_cpt_stop_simulation = 0;
4338	}
4339
4340	/////////// execute one iss cycle /////////////////////////////////
4341	{
4342	uint32_t it = 0;
4343	for (size_t i=0; i<(size_t)iss_t::n_irq; i++) if(p_irq[i].read()) it \|= (1<<i);
4344	r_iss.executeNCycles(1, m_irsp, m_drsp, it);
4345	}
4346
4347	////////////////////////////////////////////////////////////////////////////
4348	// The VCI_CMD FSM controls the following ressources:
4349	// - r_vci_cmd_fsm
4350	// - r_vci_cmd_min
4351	// - r_vci_cmd_max
4352	// - r_vci_cmd_cpt
4353	// - r_vci_cmd_imiss_prio
4354	// - wbuf (reset)
4355	// - r_icache_miss_req (reset)
4356	// - r_icache_unc_req (reset)
4357	// - r_dcache_vci_miss_req (reset)
4358	// - r_dcache_vci_unc_req (reset)
4359	// - r_dcache_vci_sc_req (reset)
4360	//
4361	// This FSM handles requests from both the DCACHE FSM & the ICACHE FSM.
4362	// There is 6 request types, with the following priorities :
4363	// 1 - Data Read Miss : r_dcache_vci_miss_req and miss in the write buffer
4364	// 2 - Data Read Uncachable : r_dcache_vci_unc_req
4365	// 3 - Instruction Miss : r_icache_miss_req and miss in the write buffer
4366	// 4 - Instruction Uncachable : r_icache_unc_req
4367	// 5 - Data Write : r_wbuf.rok()
4368	// 6 - Data Store Conditionnal: r_dcache_vci_sc_req
4369	//
4370	// As we want to support several simultaneous VCI transactions, the VCI_CMD_FSM
4371	// and the VCI_RSP_FSM are fully desynchronized.
4372	//
4373	// VCI formats:
4374	// According to the VCI advanced specification, all read requests packets
4375	// (data Uncached, Miss data, instruction Uncached, Miss instruction)
4376	// are one word packets.
4377	// For write burst packets, all words are in the same cache line,
4378	// and addresses must be contiguous (the BE field is 0 in case of "holes").
4379	// The sc command packet implements actually a compare-and-swap mechanism
4380	// and the packet contains two flits.
4381	////////////////////////////////////////////////////////////////////////////////////
4382
4383	switch ( r_vci_cmd_fsm.read() )
4384	{
4385	//////////////
4386	case CMD_IDLE:
4387	{
4388	// r_dcache_vci_miss_req and r_icache_miss_req require both a write_buffer access
4389	// to check a possible pending write on the same cache line.
4390	// As there is only one possible access per cycle to write buffer, we implement
4391	// a round-robin priority for this access, using the r_vci_cmd_imiss_prio flip-flop.
4392
4393	size_t wbuf_min;
4394	size_t wbuf_max;
4395
4396	bool dcache_miss_req = r_dcache_vci_miss_req.read()
4397	and ( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() );
4398
4399	bool icache_miss_req = r_icache_miss_req.read()
4400	and ( not r_dcache_vci_miss_req.read() or r_vci_cmd_imiss_prio.read() );
4401
4402	// 1 - Data Read Miss
4403	if ( dcache_miss_req and r_wbuf.miss(r_dcache_vci_paddr.read()) )
4404	{
4405	r_vci_cmd_fsm = CMD_DATA_MISS;
4406	r_dcache_vci_miss_req = false;
4407	r_vci_cmd_imiss_prio = true;
4408	// m_cpt_dmiss_transaction++;
4409	}
4410	// 2 - Data Read Uncachable
4411	else if ( r_dcache_vci_unc_req.read() )
4412	{
4413	r_vci_cmd_fsm = CMD_DATA_UNC;
4414	r_dcache_vci_unc_req = false;
4415	// m_cpt_dunc_transaction++;
4416	}
4417	// 3 - Instruction Miss
4418	else if ( icache_miss_req and r_wbuf.miss(r_icache_vci_paddr.read()) )
4419	{
4420	r_vci_cmd_fsm = CMD_INS_MISS;
4421	r_icache_miss_req = false;
4422	r_vci_cmd_imiss_prio = false;
4423	// m_cpt_imiss_transaction++;
4424	}
4425	// 4 - Instruction Uncachable
4426	else if ( r_icache_unc_req.read() )
4427	{
4428	r_vci_cmd_fsm = CMD_INS_UNC;
4429	r_icache_unc_req = false;
4430	// m_cpt_iunc_transaction++;
4431	}
4432	// 5 - Data Write
4433	else if ( r_wbuf.rok(&wbuf_min, &wbuf_max) )
4434	{
4435	r_vci_cmd_fsm = CMD_DATA_WRITE;
4436	r_vci_cmd_cpt = wbuf_min;
4437	r_vci_cmd_min = wbuf_min;
4438	r_vci_cmd_max = wbuf_max;
4439	// m_cpt_write_transaction++;
4440	// m_length_write_transaction += (wbuf_max-wbuf_min+1);
4441	}
4442	// 6 - Data Store Conditionnal
4443	else if ( r_dcache_vci_sc_req.read() )
4444	{
4445	r_vci_cmd_fsm = CMD_DATA_SC;
4446	r_dcache_vci_sc_req = false;
4447	r_vci_cmd_cpt = 0;
4448	// m_cpt_sc_transaction++;
4449	}
4450	break;
4451	}
4452	////////////////////
4453	case CMD_DATA_WRITE:
4454	{
4455	if ( p_vci_ini_d.cmdack.read() )
4456	{
4457	// m_conso_wbuf_read++;
4458	r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
4459	if (r_vci_cmd_cpt == r_vci_cmd_max) // last flit sent
4460	{
4461	r_vci_cmd_fsm = CMD_IDLE ;
4462	r_wbuf.sent() ;
4463	}
4464	}
4465	break;
4466	}
4467	/////////////////
4468	case CMD_DATA_SC:
4469	{
4470	// The SC VCI command contains two flits
4471	if ( p_vci_ini_d.cmdack.read() )
4472	{
4473	r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
4474	if (r_vci_cmd_cpt == 1) r_vci_cmd_fsm = CMD_IDLE ;
4475	}
4476	break;
4477	}
4478	//////////////////
4479	case CMD_INS_MISS:
4480	case CMD_INS_UNC:
4481	case CMD_DATA_MISS:
4482	case CMD_DATA_UNC:
4483	{
4484	// all read VCI commands contain one single flit
4485	if ( p_vci_ini_d.cmdack.read() ) r_vci_cmd_fsm = CMD_IDLE;
4486	break;
4487	}
4488
4489	} // end switch r_vci_cmd_fsm
4490
4491	//////////////////////////////////////////////////////////////////////////
4492	// The VCI_RSP FSM controls the following ressources:
4493	// - r_vci_rsp_fsm:
4494	// - r_vci_rsp_fifo_icache (push)
4495	// - r_vci_rsp_fifo_dcache (push)
4496	// - r_vci_rsp_data_error (set)
4497	// - r_vci_rsp_ins_error (set)
4498	// - r_vci_rsp_cpt
4499	//
4500	// As the VCI_RSP and VCI_CMD are fully desynchronized to support several
4501	// simultaneous VCI transactions, this FSM uses the VCI TRDID field
4502	// to identify the transactions.
4503	//
4504	// VCI vormat:
4505	// This component checks the response packet length and accepts only
4506	// single word packets for write response packets.
4507	//
4508	// Error handling:
4509	// This FSM analyzes the VCI error code and signals directly the Write Bus Error.
4510	// In case of Read Data Error, the VCI_RSP FSM sets the r_vci_rsp_data_error
4511	// flip_flop and the error is signaled by the DCACHE FSM.
4512	// In case of Instruction Error, the VCI_RSP FSM sets the r_vci_rsp_ins_error
4513	// flip_flop and the error is signaled by the ICACHE FSM.
4514	// In case of Cleanup Error, the simulation stops with an error message...
4515	//////////////////////////////////////////////////////////////////////////
4516
4517	switch ( r_vci_rsp_fsm.read() )
4518	{
4519	//////////////
4520	case RSP_IDLE:
4521	{
4522	if ( p_vci_ini_d.rspval.read() )
4523	{
4524	r_vci_rsp_cpt = 0;
4525
4526	if ( (p_vci_ini_d.rtrdid.read() >> (vci_param::T-1)) != 0 ) // Write transaction
4527	{
4528	r_vci_rsp_fsm = RSP_DATA_WRITE;
4529	}
4530	else if ( p_vci_ini_d.rtrdid.read() == TYPE_INS_MISS )
4531	{
4532	r_vci_rsp_fsm = RSP_INS_MISS;
4533	}
4534	else if ( p_vci_ini_d.rtrdid.read() == TYPE_INS_UNC )
4535	{
4536	r_vci_rsp_fsm = RSP_INS_UNC;
4537	}
4538	else if ( p_vci_ini_d.rtrdid.read() == TYPE_DATA_MISS )
4539	{
4540	r_vci_rsp_fsm = RSP_DATA_MISS;
4541	}
4542	else if ( p_vci_ini_d.rtrdid.read() == TYPE_DATA_UNC )
4543	{
4544	r_vci_rsp_fsm = RSP_DATA_UNC;
4545	}
4546	else
4547	{
4548	assert(false and "Unexpected VCI response");
4549	}
4550	}
4551	break;
4552	}
4553	//////////////////
4554	case RSP_INS_MISS:
4555	{
4556	if ( p_vci_ini_d.rspval.read() )
4557	{
4558	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported
4559	{
4560	r_vci_rsp_ins_error = true;
4561	if ( p_vci_ini_d.reop.read() ) r_vci_rsp_fsm = RSP_IDLE;
4562	}
4563	else // no error reported
4564	{
4565	if ( r_vci_rsp_fifo_icache.wok() )
4566	{
4567	assert( (r_vci_rsp_cpt.read() < m_icache_words) and
4568	"The VCI response packet for instruction miss is too long" );
4569
4570	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
4571	vci_rsp_fifo_icache_put = true,
4572	vci_rsp_fifo_icache_data = p_vci_ini_d.rdata.read();
4573	if ( p_vci_ini_d.reop.read() )
4574	{
4575	assert( (r_vci_rsp_cpt.read() == m_icache_words - 1) and
4576	"The VCI response packet for instruction miss is too short");
4577
4578	r_vci_rsp_fsm = RSP_IDLE;
4579	}
4580	}
4581	}
4582	}
4583	break;
4584	}
4585	/////////////////
4586	case RSP_INS_UNC:
4587	{
4588	if (p_vci_ini_d.rspval.read() )
4589	{
4590	assert( p_vci_ini_d.reop.read() and
4591	"illegal VCI response packet for uncachable instruction");
4592
4593	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported
4594	{
4595	r_vci_rsp_ins_error = true;
4596	r_vci_rsp_fsm = RSP_IDLE;
4597	}
4598	else // no error reported
4599	{
4600	if ( r_vci_rsp_fifo_icache.wok())
4601	{
4602	vci_rsp_fifo_icache_put = true;
4603	vci_rsp_fifo_icache_data = p_vci_ini_d.rdata.read();
4604	r_vci_rsp_fsm = RSP_IDLE;
4605	}
4606	}
4607	}
4608	break;
4609	}
4610	///////////////////
4611	case RSP_DATA_MISS:
4612	{
4613	if ( p_vci_ini_d.rspval.read() )
4614	{
4615	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported
4616	{
4617	r_vci_rsp_data_error = true;
4618	if ( p_vci_ini_d.reop.read() ) r_vci_rsp_fsm = RSP_IDLE;
4619	}
4620	else // no error reported
4621	{
4622	if ( r_vci_rsp_fifo_dcache.wok() )
4623	{
4624	assert( (r_vci_rsp_cpt.read() < m_dcache_words) and
4625	"The VCI response packet for data miss is too long");
4626
4627	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
4628	vci_rsp_fifo_dcache_put = true,
4629	vci_rsp_fifo_dcache_data = p_vci_ini_d.rdata.read();
4630	if ( p_vci_ini_d.reop.read() )
4631	{
4632	assert( (r_vci_rsp_cpt.read() == m_dcache_words - 1) and
4633	"The VCI response packet for data miss is too short");
4634
4635	r_vci_rsp_fsm = RSP_IDLE;
4636	}
4637	}
4638	}
4639	}
4640	break;
4641	}
4642	//////////////////
4643	case RSP_DATA_UNC:
4644	{
4645	if (p_vci_ini_d.rspval.read() )
4646	{
4647	assert( p_vci_ini_d.reop.read() and
4648	"illegal VCI response packet for uncachable read data");
4649
4650	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported
4651	{
4652	r_vci_rsp_data_error = true;
4653	r_vci_rsp_fsm = RSP_IDLE;
4654	}
4655	else // no error reported
4656	{
4657	if ( r_vci_rsp_fifo_dcache.wok())
4658	{
4659	vci_rsp_fifo_dcache_put = true;
4660	vci_rsp_fifo_dcache_data = p_vci_ini_d.rdata.read();
4661	r_vci_rsp_fsm = RSP_IDLE;
4662	}
4663	}
4664	}
4665	break;
4666	}
4667	////////////////////
4668	case RSP_DATA_WRITE:
4669	{
4670	if (p_vci_ini_d.rspval.read())
4671	{
4672	assert( p_vci_ini_d.reop.read() and
4673	"a VCI response packet must contain one flit for a write transaction");
4674
4675	r_vci_rsp_fsm = RSP_IDLE;
4676	uint32_t wbuf_index = p_vci_ini_d.rtrdid.read() - (1<<(vci_param::T-1));
4677	bool cacheable = r_wbuf.completed(wbuf_index);
4678	if ( not cacheable ) r_dcache_pending_unc_write = false;
4679	if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) r_iss.setWriteBerr();
4680	}
4681	break;
4682	}
4683	} // end switch r_vci_rsp_fsm
4684
4685	/////////////////////////////////////////////////////////////////////////////////////
4686	// The CLEANUP FSM is in charge to send the cleanup commands on the coherence
4687	// network. It has two clients (DCACHE FSM and ICACHE FSM) that are served
4688	// with a round-robin priority. All cleanup commands are registered in the
4689	// r_cleanup_buffer, because we must avoid to send a Read Miss command
4690	// for line (X) if there is a pending cleanup for line (X): the r_cleanup_buffer
4691	// is tested by the ICACHE FSM and DCACHE FSM before posting a miss request.
4692	// The CLEANUP FSM resets the r_*cache_cleanup request flip-flops as soon as
4693	// the request has been sent and registered in the buffer.
4694	// The buffer itself is cleared when the cleanup response is received.
4695	// We use an assocative registration buffer (CAM) in order to support several
4696	// simultaneous cleanup transactions (up to 4 simultaneous clenups).
4697	// The VCI TRDID field is used to distinguish data/instruction cleanups:
4698	// - if data cleanup : TRDID = 2*index + 0
4699	// - if instruction cleanup : TRDID = 2*index + 1
4700	/////////////////////////////////////////////////////////////////////////////////////
4701
4702	switch ( r_cleanup_fsm.read() )
4703	{
4704	///////////////////////
4705	case CLEANUP_DATA_IDLE: // dcache has highest priority
4706	{
4707	size_t index = 0;
4708	bool ok;
4709	if ( r_dcache_cleanup_req.read() ) // dcache request
4710	{
4711	ok = r_cleanup_buffer.write( r_dcache_cleanup_line.read(),
4712	&index );
4713	if ( ok ) // successful registration
4714	{
4715	r_cleanup_fsm = CLEANUP_DATA_GO;
4716	r_cleanup_trdid = index<<1;
4717	}
4718	}
4719	else if ( r_icache_cleanup_req.read() ) // icache request
4720	{
4721	ok = r_cleanup_buffer.write( r_icache_cleanup_line.read(),
4722	&index );
4723	if ( ok ) // successful registration
4724	{
4725	r_cleanup_fsm = CLEANUP_INS_GO;
4726	r_cleanup_trdid = (index<<1) + 1;
4727	}
4728	}
4729	break;
4730	}
4731	//////////////////////
4732	case CLEANUP_INS_IDLE: // icache has highest priority
4733	{
4734	size_t index = 0;
4735	bool ok;
4736	if ( r_icache_cleanup_req.read() ) // icache request
4737	{
4738	ok = r_cleanup_buffer.write( r_icache_cleanup_line.read(),
4739	&index );
4740	if ( ok ) // successful registration
4741	{
4742	r_cleanup_fsm = CLEANUP_INS_GO;
4743	r_cleanup_trdid = (index<<1) + 1;
4744	}
4745	}
4746	else if ( r_dcache_cleanup_req.read() ) // dcache request
4747	{
4748	ok = r_cleanup_buffer.write( r_dcache_cleanup_line.read(),
4749	&index );
4750	if ( ok ) // successful registration
4751	{
4752	r_cleanup_fsm = CLEANUP_DATA_GO;
4753	r_cleanup_trdid = index<<1;
4754	}
4755	}
4756	break;
4757	}
4758	/////////////////////
4759	case CLEANUP_DATA_GO:
4760	{
4761	if ( p_vci_ini_c.cmdack.read() )
4762	{
4763	r_cleanup_fsm = CLEANUP_INS_IDLE;
4764	r_dcache_cleanup_req = false;
4765
4766	#if DEBUG_CLEANUP
4767	if ( m_debug_cleanup_fsm )
4768	{
4769	std::cout << " <PROC.CLEANUP_DATA_GO> Cleanup request for icache:" << std::hex
4770	<< " address = " << (r_dcache_cleanup_line.read()m_dcache_words4)
4771	<< " / trdid = " << std::dec << r_cleanup_trdid.read() << std::endl;
4772	}
4773	#endif
4774	}
4775	break;
4776	}
4777	////////////////////
4778	case CLEANUP_INS_GO:
4779	{
4780	if ( p_vci_ini_c.cmdack.read() )
4781	{
4782	r_cleanup_fsm = CLEANUP_DATA_IDLE;
4783	r_icache_cleanup_req = false;
4784
4785	#if DEBUG_CLEANUP
4786	if ( m_debug_cleanup_fsm )
4787	{
4788	std::cout << " <PROC.CLEANUP_INS_GO> Cleanup request for dcache:" << std::hex
4789	<< " address = " << (r_icache_cleanup_line.read()m_icache_words4)
4790	<< " / trdid = " << std::dec << r_cleanup_trdid.read() << std::endl;
4791	}
4792	#endif
4793	}
4794	break;
4795	}
4796	} // end switch CLEANUP FSM
4797
4798	//////////////// Handling cleanup responses //////////////////
4799	if ( p_vci_ini_c.rspval.read() )
4800	{
4801	r_cleanup_buffer.inval( p_vci_ini_c.rtrdid.read() >> 1);
4802	}
4803
4804	///////////////// Response FIFOs update //////////////////////
4805	r_vci_rsp_fifo_icache.update(vci_rsp_fifo_icache_get,
4806	vci_rsp_fifo_icache_put,
4807	vci_rsp_fifo_icache_data);
4808
4809	r_vci_rsp_fifo_dcache.update(vci_rsp_fifo_dcache_get,
4810	vci_rsp_fifo_dcache_put,
4811	vci_rsp_fifo_dcache_data);
4812	} // end transition()
4813
4814	///////////////////////
4815	tmpl(void)::genMoore()
4816	///////////////////////
4817	{
4818	////////////////////////////////////////////////////////////////
4819	// VCI initiator command on the coherence network (cleanup)
4820	// it depends on the CLEANUP FSM state
4821
4822	paddr_t cleanup_nline;
4823	paddr_t address;
4824
4825	if ( r_cleanup_fsm.read() == CLEANUP_DATA_GO )
4826	{
4827	cleanup_nline = r_dcache_cleanup_line.read();
4828	address = (m_x_width + m_y_width) ? (cleanup_nline * m_dcache_words * 4 ) >>
4829	(vci_param::N - m_x_width - m_y_width ) : 0;
4830	}
4831	else if ( r_cleanup_fsm.read() == CLEANUP_INS_GO )
4832	{
4833	cleanup_nline = r_icache_cleanup_line.read();
4834	address = (m_x_width + m_y_width) ? (cleanup_nline * m_icache_words * 4 ) >>
4835	(vci_param::N - m_x_width - m_y_width ) : 0;
4836	}
4837	else
4838	{
4839	cleanup_nline = 0;
4840	address = 0;
4841	}
4842
4843	address <<= vci_param::S - m_x_width - m_y_width;
4844	address \|= m_memory_cache_local_id;
4845	address <<= vci_param::N - vci_param::S;
4846
4847	p_vci_ini_c.cmdval = ((r_cleanup_fsm.read() == CLEANUP_DATA_GO) or
4848	(r_cleanup_fsm.read() == CLEANUP_INS_GO) );
4849	p_vci_ini_c.address = address;
4850	p_vci_ini_c.wdata = (uint32_t) cleanup_nline;
4851	p_vci_ini_c.be = (cleanup_nline >> 32) & 0x3;
4852	p_vci_ini_c.plen = 4;
4853	p_vci_ini_c.cmd = vci_param::CMD_WRITE;
4854	p_vci_ini_c.trdid = r_cleanup_trdid.read();
4855	p_vci_ini_c.pktid = 0;
4856	p_vci_ini_c.srcid = m_srcid_c;
4857	p_vci_ini_c.cons = false;
4858	p_vci_ini_c.wrap = false;
4859	p_vci_ini_c.contig = false;
4860	p_vci_ini_c.clen = 0;
4861	p_vci_ini_c.cfixed = false;
4862	p_vci_ini_c.eop = true;
4863
4864	/////////////////////////////////////////////////////////////////
4865	// VCI initiator response on the coherence network (cleanup)
4866	// We always consume the response, and we don't use it.
4867
4868	p_vci_ini_c.rspack = true;
4869
4870	/////////////////////////////////////////////////////////////////
4871	// VCI initiator command on the direct network
4872	// it depends on the CMD FSM state
4873
4874	p_vci_ini_d.pktid = 0;
4875	p_vci_ini_d.srcid = m_srcid_d;
4876	p_vci_ini_d.cons = (r_vci_cmd_fsm.read() == CMD_DATA_SC);
4877	p_vci_ini_d.contig = not (r_vci_cmd_fsm.read() == CMD_DATA_SC);
4878	p_vci_ini_d.wrap = false;
4879	p_vci_ini_d.clen = 0;
4880	p_vci_ini_d.cfixed = false;
4881
4882	switch ( r_vci_cmd_fsm.read() ) {
4883
4884	case CMD_IDLE:
4885	p_vci_ini_d.cmdval = false;
4886	p_vci_ini_d.address = 0;
4887	p_vci_ini_d.wdata = 0;
4888	p_vci_ini_d.be = 0;
4889	p_vci_ini_d.trdid = 0;
4890	p_vci_ini_d.plen = 0;
4891	p_vci_ini_d.cmd = vci_param::CMD_NOP;
4892	p_vci_ini_d.eop = false;
4893	break;
4894
4895	case CMD_INS_MISS:
4896	p_vci_ini_d.cmdval = true;
4897	p_vci_ini_d.address = r_icache_vci_paddr.read() & m_icache_yzmask;
4898	p_vci_ini_d.wdata = 0;
4899	p_vci_ini_d.be = 0xF;
4900	p_vci_ini_d.trdid = TYPE_INS_MISS;
4901	p_vci_ini_d.plen = m_icache_words<<2;
4902	p_vci_ini_d.cmd = vci_param::CMD_READ;
4903	p_vci_ini_d.eop = true;
4904	break;
4905
4906	case CMD_INS_UNC:
4907	p_vci_ini_d.cmdval = true;
4908	p_vci_ini_d.address = r_icache_vci_paddr.read() & ~0x3;
4909	p_vci_ini_d.wdata = 0;
4910	p_vci_ini_d.be = 0xF;
4911	p_vci_ini_d.trdid = TYPE_INS_UNC;
4912	p_vci_ini_d.plen = 4;
4913	p_vci_ini_d.cmd = vci_param::CMD_READ;
4914	p_vci_ini_d.eop = true;
4915	break;
4916
4917	case CMD_DATA_MISS:
4918	p_vci_ini_d.cmdval = true;
4919	p_vci_ini_d.address = r_dcache_vci_paddr.read() & m_dcache_yzmask;
4920	p_vci_ini_d.wdata = 0;
4921	p_vci_ini_d.be = 0xF;
4922	p_vci_ini_d.trdid = TYPE_DATA_MISS;
4923	p_vci_ini_d.plen = m_dcache_words << 2;
4924	p_vci_ini_d.cmd = vci_param::CMD_READ;
4925	p_vci_ini_d.eop = true;
4926	break;
4927
4928	case CMD_DATA_UNC:
4929	p_vci_ini_d.cmdval = true;
4930	p_vci_ini_d.address = r_dcache_vci_paddr.read() & ~0x3;
4931	p_vci_ini_d.wdata = 0;
4932	p_vci_ini_d.be = r_dcache_vci_unc_be.read();
4933	p_vci_ini_d.trdid = TYPE_DATA_UNC;
4934	p_vci_ini_d.plen = 4;
4935	p_vci_ini_d.cmd = vci_param::CMD_READ;
4936	p_vci_ini_d.eop = true;
4937	break;
4938
4939	case CMD_DATA_WRITE:
4940	p_vci_ini_d.cmdval = true;
4941	p_vci_ini_d.address = r_wbuf.getAddress(r_vci_cmd_cpt.read()) & ~0x3;
4942	p_vci_ini_d.wdata = r_wbuf.getData(r_vci_cmd_cpt.read());
4943	p_vci_ini_d.be = r_wbuf.getBe(r_vci_cmd_cpt.read());
4944	p_vci_ini_d.trdid = r_wbuf.getIndex() + (1<<(vci_param::T-1));
4945	p_vci_ini_d.plen = (r_vci_cmd_max.read() - r_vci_cmd_min.read() + 1) << 2;
4946	p_vci_ini_d.cmd = vci_param::CMD_WRITE;
4947	p_vci_ini_d.eop = (r_vci_cmd_cpt.read() == r_vci_cmd_max.read());
4948	break;
4949
4950	case CMD_DATA_SC:
4951	p_vci_ini_d.cmdval = true;
4952	p_vci_ini_d.address = r_dcache_vci_paddr.read() & ~0x3;
4953	if ( r_vci_cmd_cpt.read() == 0 ) p_vci_ini_d.wdata = r_dcache_vci_sc_old.read();
4954	else p_vci_ini_d.wdata = r_dcache_vci_sc_new.read();
4955	p_vci_ini_d.be = 0xF;
4956	p_vci_ini_d.trdid = TYPE_DATA_UNC;
4957	p_vci_ini_d.plen = 8;
4958	p_vci_ini_d.cmd = vci_param::CMD_STORE_COND;
4959	p_vci_ini_d.eop = (r_vci_cmd_cpt.read() == 1);
4960	break;
4961	} // end switch r_vci_cmd_fsm
4962
4963	//////////////////////////////////////////////////////////
4964	// VCI initiator response on the direct network
4965	// it depends on the VCI RSP state
4966
4967	switch (r_vci_rsp_fsm.read() )
4968	{
4969	case RSP_DATA_WRITE : p_vci_ini_d.rspack = true; break;
4970	case RSP_INS_MISS : p_vci_ini_d.rspack = r_vci_rsp_fifo_icache.wok(); break;
4971	case RSP_INS_UNC : p_vci_ini_d.rspack = r_vci_rsp_fifo_icache.wok(); break;
4972	case RSP_DATA_MISS : p_vci_ini_d.rspack = r_vci_rsp_fifo_dcache.wok(); break;
4973	case RSP_DATA_UNC : p_vci_ini_d.rspack = r_vci_rsp_fifo_dcache.wok(); break;
4974	case RSP_IDLE : p_vci_ini_d.rspack = false; break;
4975	} // end switch r_vci_rsp_fsm
4976
4977	////////////////////////////////////////////////////////////////
4978	// VCI target command and response on the coherence network
4979	switch ( r_tgt_fsm.read() )
4980	{
4981	case TGT_IDLE:
4982	case TGT_UPDT_WORD:
4983	case TGT_UPDT_DATA:
4984	p_vci_tgt_c.cmdack = true;
4985	p_vci_tgt_c.rspval = false;
4986	break;
4987
4988	case TGT_RSP_BROADCAST:
4989	p_vci_tgt_c.cmdack = false;
4990	p_vci_tgt_c.rspval = not r_tgt_icache_req.read() and not r_tgt_dcache_req.read()
4991	and ( r_tgt_icache_rsp.read() or r_tgt_dcache_rsp.read() );
4992	p_vci_tgt_c.rsrcid = r_tgt_srcid.read();
4993	p_vci_tgt_c.rpktid = r_tgt_pktid.read();
4994	p_vci_tgt_c.rtrdid = r_tgt_trdid.read();
4995	p_vci_tgt_c.rdata = 0;
4996	p_vci_tgt_c.rerror = 0;
4997	p_vci_tgt_c.reop = true;
4998	break;
4999
5000	case TGT_RSP_ICACHE:
5001	p_vci_tgt_c.cmdack = false;
5002	p_vci_tgt_c.rspval = not r_tgt_icache_req.read() and r_tgt_icache_rsp.read();
5003	p_vci_tgt_c.rsrcid = r_tgt_srcid.read();
5004	p_vci_tgt_c.rpktid = r_tgt_pktid.read();
5005	p_vci_tgt_c.rtrdid = r_tgt_trdid.read();
5006	p_vci_tgt_c.rdata = 0;
5007	p_vci_tgt_c.rerror = 0;
5008	p_vci_tgt_c.reop = true;
5009	break;
5010
5011	case TGT_RSP_DCACHE:
5012	p_vci_tgt_c.cmdack = false;
5013	p_vci_tgt_c.rspval = not r_tgt_dcache_req.read() and r_tgt_dcache_rsp.read();
5014	p_vci_tgt_c.rsrcid = r_tgt_srcid.read();
5015	p_vci_tgt_c.rpktid = r_tgt_pktid.read();
5016	p_vci_tgt_c.rtrdid = r_tgt_trdid.read();
5017	p_vci_tgt_c.rdata = 0;
5018	p_vci_tgt_c.rerror = 0;
5019	p_vci_tgt_c.reop = true;
5020	break;
5021
5022	case TGT_REQ_BROADCAST:
5023	case TGT_REQ_ICACHE:
5024	case TGT_REQ_DCACHE:
5025	p_vci_tgt_c.cmdack = false;
5026	p_vci_tgt_c.rspval = false;
5027	break;
5028
5029	} // end switch TGT_FSM
5030	} // end genMoore
5031
5032	}}
5033
5034	// Local Variables:
5035	// tab-width: 4
5036	// c-basic-offset: 4
5037	// c-file-offsets:((innamespace . 0)(inline-open . 0))
5038	// indent-tabs-mode: nil
5039	// End:
5040
5041	// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
5042
5043
5044
5045
5046
5047
5048
5049
5050
5051

Note: See TracBrowser for help on using the repository browser.

Download in other formats:

Project-Id-Version: Trac 0.12
Report-Msgid-Bugs-To: trac-dev@googlegroups.com
POT-Creation-Date: 2018-07-07 16:55+0000
PO-Revision-Date: 2010-07-19 23:05+0200
Last-Translator: Jeroen Ruigrok van der Werven <asmodai@in-nomine.org>
Language: en_US
Language-Team: en_US <trac-dev@googlegroups.com>
Plural-Forms: nplurals=2; plural=(n != 1)
MIME-Version: 1.0
Content-Type: text/plain; charset=utf-8
Content-Transfer-Encoding: 8bit
Generated-By: Babel 2.8.0