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vci_cc_xcache_wrapper_multi.h @ 2

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1	/* -- c++ --
2	*
3	* SOCLIB_LGPL_HEADER_BEGIN
4	*
5	* This file is part of SoCLib, GNU LGPLv2.1.
6	*
7	* SoCLib is free software; you can redistribute it and/or modify it
8	* under the terms of the GNU Lesser General Public License as published
9	* by the Free Software Foundation; version 2.1 of the License.
10	*
11	* SoCLib is distributed in the hope that it will be useful, but
12	* WITHOUT ANY WARRANTY; without even the implied warranty of
13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14	* Lesser General Public License for more details.
15	*
16	* You should have received a copy of the GNU Lesser General Public
17	* License along with SoCLib; if not, write to the Free Software
18	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
19	* 02110-1301 USA
20	*
21	* SOCLIB_LGPL_HEADER_END
22	*
23	* Copyright (c) UPMC, Lip6, SoC
24	* Alain Greiner <alain.greiner@lip6.fr>, 2008
25	*
26	* Maintainers: alain
27	*/
28
29	#ifndef SOCLIB_CABA_VCI_CC_XCACHE_WRAPPER_MULTI_H
30	#define SOCLIB_CABA_VCI_CC_XCACHE_WRAPPER_MULTI_H
31
32	#include <inttypes.h>
33	#include <systemc>
34	#include "caba_base_module.h"
35	#include "multi_write_buffer.h"
36	#include "generic_cache.h"
37	#include "vci_initiator.h"
38	#include "vci_target.h"
39	#include "mapping_table.h"
40	#include "static_assert.h"
41
42
43	namespace soclib {
44	namespace caba {
45
46	using namespace sc_core;
47
48	////////////////////////////////////////////
49	template<typename vci_param, typename iss_t>
50	class VciCcXCacheWrapperMulti
51	///////////////////////////////////////////
52	: public soclib::caba::BaseModule
53	{
54	typedef uint32_t data_t;
55	typedef uint32_t be_t;
56	typedef typename vci_param::fast_addr_t addr_t;
57
58	enum dcache_fsm_state_e {
59	DCACHE_IDLE,
60	DCACHE_WRITE_UPDT,
61	DCACHE_WRITE_REQ,
62	DCACHE_MISS_SELECT,
63	DCACHE_MISS_CLEANUP,
64	DCACHE_MISS_WAIT,
65	DCACHE_MISS_UPDT,
66	DCACHE_UNC_WAIT,
67	DCACHE_INVAL,
68	DCACHE_SYNC,
69	DCACHE_ERROR,
70	DCACHE_CC_CHECK,
71	DCACHE_CC_INVAL,
72	DCACHE_CC_UPDT,
73	};
74
75	enum icache_fsm_state_e {
76	ICACHE_IDLE,
77	ICACHE_MISS_SELECT,
78	ICACHE_MISS_CLEANUP,
79	ICACHE_MISS_WAIT,
80	ICACHE_MISS_UPDT,
81	ICACHE_UNC_WAIT,
82	ICACHE_ERROR,
83	ICACHE_CC_CHECK,
84	ICACHE_CC_INVAL,
85	ICACHE_CC_UPDT,
86	};
87
88	enum cmd_fsm_state_e {
89	CMD_IDLE,
90	CMD_INS_MISS,
91	CMD_INS_UNC,
92	CMD_DATA_MISS,
93	CMD_DATA_UNC,
94	CMD_DATA_WRITE,
95	};
96
97	enum rsp_fsm_state_e {
98	RSP_IDLE,
99	RSP_INS_MISS,
100	RSP_INS_UNC,
101	RSP_DATA_MISS,
102	RSP_DATA_UNC,
103	RSP_DATA_WRITE,
104	};
105
106	enum tgt_fsm_state_e {
107	TGT_IDLE,
108	TGT_UPDT_WORD,
109	TGT_UPDT_DATA,
110	TGT_REQ_BROADCAST,
111	TGT_REQ_ICACHE,
112	TGT_REQ_DCACHE,
113	TGT_RSP_BROADCAST,
114	TGT_RSP_ICACHE,
115	TGT_RSP_DCACHE,
116	};
117
118	enum cleanup_fsm_state_e {
119	CLEANUP_CMD,
120	CLEANUP_DCACHE_RSP,
121	CLEANUP_ICACHE_RSP,
122	};
123
124	enum transaction_type_e {
125	TYPE_DATA_UNC = 0,
126	TYPE_DATA_MISS = 1,
127	TYPE_INS_UNC = 2,
128	TYPE_INS_MISS = 3,
129	};
130
131	public:
132
133	// PORTS
134	sc_in<bool> p_clk;
135	sc_in<bool> p_resetn;
136	sc_in<bool> p_irq[iss_t::n_irq];
137	soclib::caba::VciInitiator<vci_param> p_vci_ini_d;
138	soclib::caba::VciInitiator<vci_param> p_vci_ini_c;
139	soclib::caba::VciTarget<vci_param> p_vci_tgt_c;
140
141	private:
142
143	// STRUCTURAL PARAMETERS
144	const soclib::common::AddressDecodingTable<addr_t, bool> m_cacheability_table;
145	const soclib::common::Segment m_segment;
146	iss_t m_iss;
147	const uint32_t m_srcid_d;
148	const uint32_t m_srcid_c;
149
150	const size_t m_wbuf_nlines;
151	const size_t m_dcache_ways;
152	const size_t m_dcache_words;
153	const size_t m_dcache_yzmask;
154	const size_t m_icache_ways;
155	const size_t m_icache_words;
156	const size_t m_icache_yzmask;
157
158	// REGISTERS
159	sc_signal<int> r_dcache_fsm; // controls the data cache interface
160	sc_signal<int> r_dcache_fsm_save;
161	sc_signal<addr_t> r_dcache_addr_save;
162	sc_signal<data_t> r_dcache_wdata_save;
163	sc_signal<data_t> r_dcache_rdata_save;
164	sc_signal<int> r_dcache_type_save;
165	sc_signal<be_t> r_dcache_be_save;
166	sc_signal<addr_t> r_dcache_cleanup_save; // victim line index for cleanup
167	sc_signal<size_t> r_dcache_way_save; // selected slot for the replacement
168	sc_signal<bool> r_dcache_cleanup_req; // send a cleanup request to CLEANUP FSM
169	sc_signal<addr_t> r_dcache_cleanup_line; // define the victim line index
170	sc_signal<bool> r_dcache_miss_req; // send a miss request to CMD FSM
171	sc_signal<bool> r_dcache_unc_req; // send a uncached request to CMD FSM
172	sc_signal<bool> r_dcache_inval_pending; // external inval or update request pending
173
174	sc_signal<int> r_icache_fsm; // controls the instruction cache interface
175	sc_signal<int> r_icache_fsm_save;
176	sc_signal<addr_t> r_icache_addr_save;
177	sc_signal<addr_t> r_icache_cleanup_save; // victim line index for cleanup
178	sc_signal<size_t> r_icache_way_save; // selected slot for the replacement
179	sc_signal<bool> r_icache_miss_req; // send a miss request to to CMD FSM
180	sc_signal<bool> r_icache_unc_req; // send an uncached request to CMD FSM
181	sc_signal<bool> r_icache_cleanup_req; // send a cleanup request to CLEANUP FSM
182	sc_signal<addr_t> r_icache_cleanup_line; // define the victim line index
183	sc_signal<bool> r_icache_inval_pending; // external inval or update request pending
184
185	sc_signal<int> r_cmd_fsm; // controls the command on the direct network
186	sc_signal<size_t> r_cmd_min;
187	sc_signal<size_t> r_cmd_max;
188	sc_signal<size_t> r_cmd_cpt;
189
190	sc_signal<int> r_rsp_fsm; // controls the response on the direct network
191	sc_signal<bool> r_rsp_ins_error; // signals an error to the ICACHE FSM
192	sc_signal<bool> r_rsp_data_error; // signals an error to the DCACHE FSM
193	sc_signal<size_t> r_rsp_cpt;
194	sc_signal<bool> r_rsp_ins_ok; // signals an available data to the ICACHE FSM
195	sc_signal<bool> r_rsp_data_ok; // signals an available data to the DCACHE FSM;
196
197	data_t *r_icache_miss_buf;
198	data_t *r_dcache_miss_buf;
199
200	data_t *r_tgt_buf;
201	bool *r_tgt_val;
202
203	sc_signal<int> r_tgt_fsm; // controls the target port of the coherence network
204	sc_signal<addr_t> r_tgt_addr;
205	sc_signal<size_t> r_tgt_word;
206	sc_signal<bool> r_tgt_update;
207	sc_signal<bool> r_tgt_data;
208	sc_signal<bool> r_tgt_brdcast;
209	sc_signal<size_t> r_tgt_srcid;
210	sc_signal<size_t> r_tgt_pktid;
211	sc_signal<size_t> r_tgt_trdid;
212	sc_signal<size_t> r_tgt_plen;
213	sc_signal<bool> r_tgt_icache_req; // coherence request from TGT FSM to ICACHE FSM
214	sc_signal<bool> r_tgt_dcache_req; // coherence request from TGT FSM to DCACHE FSM
215	sc_signal<bool> r_tgt_icache_rsp; // response from ICACHE FSM to TGT FSM : true == hit
216	sc_signal<bool> r_tgt_dcache_rsp; // response from DCACHE FSM to TGT FSM : true == hit
217
218	sc_signal<int> r_cleanup_fsm; // controls initiator port of the coherence network
219
220	MultiWriteBuffer<addr_t> r_wbuf;
221	GenericCache<addr_t> r_icache;
222	GenericCache<addr_t> r_dcache;
223
224	// Activity counters
225	uint32_t m_cpt_dcache_data_read; // DCACHE DATA READ
226	uint32_t m_cpt_dcache_data_write; // DCACHE DATA WRITE
227	uint32_t m_cpt_dcache_dir_read; // DCACHE DIR READ
228	uint32_t m_cpt_dcache_dir_write; // DCACHE DIR WRITE
229
230	uint32_t m_cpt_icache_data_read; // ICACHE DATA READ
231	uint32_t m_cpt_icache_data_write; // ICACHE DATA WRITE
232	uint32_t m_cpt_icache_dir_read; // ICACHE DIR READ
233	uint32_t m_cpt_icache_dir_write; // ICACHE DIR WRITE
234
235	uint32_t m_cpt_cc_update; // number of coherence update packets
236	uint32_t m_cpt_cc_inval; // number of coherence inval packets
237
238	uint32_t m_cpt_frz_cycles; // number of cycles where the cpu is frozen
239	uint32_t m_cpt_total_cycles; // total number of cycles
240
241	uint32_t m_cpt_read; // total number of read instructions
242	uint32_t m_cpt_write; // total number of write instructions
243	uint32_t m_cpt_data_miss; // number of read miss
244	uint32_t m_cpt_ins_miss; // number of instruction miss
245	uint32_t m_cpt_unc_read; // number of read uncached
246	uint32_t m_cpt_write_cached; // number of cached write
247
248	uint32_t m_cost_write_frz; // number of frozen cycles related to write buffer
249	uint32_t m_cost_data_miss_frz; // number of frozen cycles related to data miss
250	uint32_t m_cost_unc_read_frz; // number of frozen cycles related to uncached read
251	uint32_t m_cost_ins_miss_frz; // number of frozen cycles related to ins miss
252
253	uint32_t m_cpt_imiss_transaction; // number of VCI instruction miss transactions
254	uint32_t m_cpt_dmiss_transaction; // number of VCI data miss transactions
255	uint32_t m_cpt_unc_transaction; // number of VCI uncached read transactions
256	uint32_t m_cpt_write_transaction; // number of VCI write transactions
257
258	uint32_t m_length_write_transaction; // cumulated length for VCI WRITE transactions
259
260	protected:
261	SC_HAS_PROCESS(VciCcXCacheWrapperMulti);
262
263	public:
264
265	VciCcXCacheWrapperMulti(
266	sc_module_name insname,
267	int proc_id,
268	const soclib::common::MappingTable &mtp,
269	const soclib::common::MappingTable &mtc,
270	const soclib::common::IntTab &initiator_index_p,
271	const soclib::common::IntTab &initiator_index_c,
272	const soclib::common::IntTab &target_index_c,
273	size_t icache_ways,
274	size_t icache_sets,
275	size_t icache_words,
276	size_t dcache_ways,
277	size_t dcache_sets,
278	size_t dcache_words,
279	size_t wbuf_nwords,
280	size_t wbuf_nlines );
281
282	~VciCcXCacheWrapperMulti();
283
284	void print_cpi();
285	void print_stats();
286
287	private:
288
289	void transition();
290	void genMoore();
291
292	soclib_static_assert((int)iss_t::SC_ATOMIC == (int)vci_param::STORE_COND_ATOMIC);
293	soclib_static_assert((int)iss_t::SC_NOT_ATOMIC == (int)vci_param::STORE_COND_NOT_ATOMIC);
294	};
295
296	}}
297
298	#endif /* SOCLIB_CABA_VCI_CC_XCACHE_WRAPPER_MULTI_H */
299
300	// Local Variables:
301	// tab-width: 4
302	// c-basic-offset: 4
303	// c-file-offsets:((innamespace . 0)(inline-open . 0))
304	// indent-tabs-mode: nil
305	// End:
306
307	// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
308
309
310

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