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vci_cc_xcache_wrapper_v1.cpp @ 83

Last change on this file since 83 was 83, checked in by guthmull, 14 years ago
Fix the masking of RERROR field
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1	/* -- c++ --
2	*
3	* SOCLIB_LGPL_HEADER_BEGIN
4	*
5	* This file is part of SoCLib, GNU LGPLv2.1.
6	*
7	* SoCLib is free software; you can redistribute it and/or modify it
8	* under the terms of the GNU Lesser General Public License as published
9	* by the Free Software Foundation; version 2.1 of the License.
10	*
11	* SoCLib is distributed in the hope that it will be useful, but
12	* WITHOUT ANY WARRANTY; without even the implied warranty of
13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14	* Lesser General Public License for more details.
15	*
16	* You should have received a copy of the GNU Lesser General Public
17	* License along with SoCLib; if not, write to the Free Software
18	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
19	* 02110-1301 USA
20	*
21	* SOCLIB_LGPL_HEADER_END
22	*
23	* Copyright (c) UPMC, Lip6, SoC
24	* Alain Greiner <alain.greiner@lip6.fr>, 2008
25	*
26	* Maintainers: alain
27	* eric.guthmuller@polytechnique.edu
28	* nipo
29	* malek <abdelmalek.si-merabet@lip6.fr>
30	*/
31
32	/////////////////////////////////////////////////////////////////////////////
33	// History
34	// - 25/04/2008
35	// The existing vci_xcache component has been extended to include
36	// a VCI target port to support a directory based coherence protocol.
37	// Two types of packets can be send by the L2 cache to the L1 cache
38	// * INVALIDATE packets : length = 1
39	// * UPDATE packets : length = n + 2
40	// The CLEANUP packets are sent by the L1 cache to the L2 cache,
41	// to signal a replaced cache line.
42	// - 12/08/2008
43	// The vci_cc_xcache_wrapper component instanciates directly the processsor
44	// iss, in order to supress the processor/cache interface.
45	// According to the VCI advanced specification, this component uses one
46	// word VCI CMD packets for MISS transactions, and accept one word VCI RSP
47	// packets for Write burst transactions.
48	// The write buffer has been modified to use the WriteBuffer object.
49	// A VCI write burst is constructed when two conditions are satisfied :
50	// The processor make strictly successive write requests, and they are
51	// in the same cache line. The write buffer performs re-ordering, to
52	// respect the contiguous addresses VCI constraint. In case of several
53	// WRITE_WORD requests in the same word, only the last request is conserved.
54	// In case of several WRITE_HALF or WRITE_WORD requests in the same word,
55	// the requests are merged in the same word. In case of uncached write
56	// requests, each request is transmited as a single VCI transaction.
57	// Both the data & instruction caches can be flushed in one single cycle.
58	// 08/12/2009
59	// adding update instruction (code X"C")
60	///////////////////////////////////////////////////////////////////////////////
61
62	#include <cassert>
63	#include "arithmetics.h"
64	#include "../include/vci_cc_xcache_wrapper_v1.h"
65
66	//#define DEBUG_CC_XCACHE_WRAPPER 1
67
68	namespace soclib {
69	namespace caba {
70
71	#if DEBUG_CC_XCACHE_WRAPPER
72	namespace {
73	const char *dcache_fsm_state_str[] = {
74	"DCACHE_IDLE",
75	"DCACHE_WRITE_UPDT",
76	"DCACHE_WRITE_REQ",
77	"DCACHE_MISS_WAIT",
78	"DCACHE_MISS_UPDT",
79	"DCACHE_UNC_WAIT",
80	"DCACHE_INVAL",
81	"DCACHE_ERROR",
82	"DCACHE_CC_CHECK",
83	"DCACHE_CC_INVAL",
84	"DCACHE_CC_UPDT",
85	"DCACHE_CC_NOP",
86	"DCACHE_CC_CLEANUP",
87	};
88	const char *icache_fsm_state_str[] = {
89	"ICACHE_IDLE",
90	"ICACHE_MISS_WAIT",
91	"ICACHE_MISS_UPDT",
92	"ICACHE_UNC_WAIT",
93	"ICACHE_ERROR",
94	"ICACHE_CC_CHECK",
95	"ICACHE_CC_INVAL",
96	"ICACHE_CC_UPDT",
97	"ICACHE_CC_CLEANUP",
98	};
99	const char *cmd_fsm_state_str[] = {
100	"CMD_IDLE",
101	"CMD_INS_MISS",
102	"CMD_INS_UNC",
103	"CMD_DATA_MISS",
104	"CMD_DATA_UNC",
105	"CMD_DATA_WRITE",
106	"CMD_INS_CLEANUP",
107	"CMD_DATA_CLEANUP",
108	};
109	const char *rsp_fsm_state_str[] = {
110	"RSP_IDLE",
111	"RSP_INS_MISS",
112	"RSP_INS_UNC",
113	"RSP_DATA_MISS",
114	"RSP_DATA_UNC",
115	"RSP_DATA_WRITE",
116	"RSP_INS_CLEANUP",
117	"RSP_DATA_CLEANUP",
118	};
119	const char *tgt_fsm_state_str[] = {
120	"TGT_IDLE",
121	"TGT_UPDT_WORD",
122	"TGT_UPDT_DATA",
123	"TGT_REQ_BROADCAST",
124	"TGT_REQ_ICACHE",
125	"TGT_REQ_DCACHE",
126	"TGT_RSP_BROADCAST",
127	"TGT_RSP_ICACHE",
128	"TGT_RSP_DCACHE",
129	};
130	}
131	#endif
132
133	#define tmpl(...) template<typename vci_param, typename iss_t> __VA_ARGS__ VciCcXCacheWrapperV1<vci_param, iss_t>
134
135	using soclib::common::uint32_log2;
136
137	/////////////////////////////////
138	tmpl(/**/)::VciCcXCacheWrapperV1(
139	/////////////////////////////////
140	sc_module_name name,
141	int proc_id,
142	const soclib::common::MappingTable &mtp,
143	const soclib::common::MappingTable &mtc,
144	const soclib::common::IntTab &initiator_index_rw,
145	const soclib::common::IntTab &initiator_index_c,
146	const soclib::common::IntTab &target_index,
147	size_t icache_ways,
148	size_t icache_sets,
149	size_t icache_words,
150	size_t dcache_ways,
151	size_t dcache_sets,
152	size_t dcache_words )
153	:
154	soclib::caba::BaseModule(name),
155
156	p_clk("clk"),
157	p_resetn("resetn"),
158	p_vci_ini_rw("vci_ini_rw"),
159	p_vci_ini_c("vci_ini_c"),
160	p_vci_tgt("vci_tgt"),
161
162	m_cacheability_table(mtp.getCacheabilityTable<vci_addr_t>()),
163	m_segment(mtc.getSegment(target_index)),
164	m_iss(this->name(), proc_id),
165	m_srcid_rw(mtp.indexForId(initiator_index_rw)),
166	m_srcid_c(mtc.indexForId(initiator_index_c)),
167
168	m_dcache_ways(dcache_ways),
169	m_dcache_words(dcache_words),
170	m_dcache_yzmask((~0)<<(uint32_log2(dcache_words) + 2)),
171	m_icache_ways(icache_ways),
172	m_icache_words(icache_words),
173	m_icache_yzmask((~0)<<(uint32_log2(icache_words) + 2)),
174
175	r_dcache_fsm("r_dcache_fsm"),
176	r_dcache_fsm_save("r_dcache_fsm_save"),
177	r_dcache_addr_save("r_dcache_addr_save"),
178	r_dcache_wdata_save("r_dcache_wdata_save"),
179	r_dcache_rdata_save("r_dcache_rdata_save"),
180	r_dcache_type_save("r_dcache_type_save"),
181	r_dcache_be_save("r_dcache_be_save"),
182	r_dcache_cached_save("r_dcache_cached_save"),
183	r_dcache_cleanup_req("r_dcache_cleanup_req"),
184	r_dcache_cleanup_line("r_dcache_cleanup_line"),
185	r_dcache_miss_req("r_dcache_miss_req"),
186	r_dcache_unc_req("r_dcache_unc_req"),
187	r_dcache_write_req("r_dcache_write_req"),
188
189	r_icache_fsm("r_icache_fsm"),
190	r_icache_fsm_save("r_icache_fsm_save"),
191	r_icache_addr_save("r_icache_addr_save"),
192	r_icache_miss_req("r_icache_miss_req"),
193	r_icache_cleanup_req("r_icache_cleanup_req"),
194	r_icache_cleanup_line("r_icache_cleanup_line"),
195
196	r_vci_cmd_fsm("r_vci_cmd_fsm"),
197	r_vci_cmd_min("r_vci_cmd_min"),
198	r_vci_cmd_max("r_vci_cmd_max"),
199	r_vci_cmd_cpt("r_vci_cmd_cpt"),
200
201	r_vci_rsp_fsm("r_vci_rsp_fsm"),
202	r_vci_rsp_ins_error("r_vci_rsp_ins_error"),
203	r_vci_rsp_data_error("r_vci_rsp_data_error"),
204	r_vci_rsp_cpt("r_vci_rsp_cpt"),
205
206	r_icache_buf_unc_valid("r_icache_buf_unc_valid"),
207	r_dcache_buf_unc_valid("r_dcache_buf_unc_valid"),
208
209	r_vci_tgt_fsm("r_vci_tgt_fsm"),
210	r_tgt_addr("r_tgt_addr"),
211	r_tgt_word("r_tgt_word"),
212	r_tgt_update("r_tgt_update"),
213	r_data_update("r_data_update"),
214	r_tgt_srcid("r_tgt_srcid"),
215	r_tgt_pktid("r_tgt_pktid"),
216	r_tgt_trdid("r_tgt_trdid"),
217	r_tgt_icache_req("r_tgt_icache_req"),
218	r_tgt_dcache_req("r_tgt_dcache_req"),
219
220	r_wbuf("r_wbuf", dcache_words ),
221	r_icache("icache", icache_ways, icache_sets, icache_words),
222	r_dcache("dcache", dcache_ways, dcache_sets, dcache_words)
223
224	{
225	r_icache_miss_buf = new data_t[icache_words];
226	r_dcache_miss_buf = new data_t[dcache_words];
227	r_tgt_buf = new data_t[dcache_words];
228	r_tgt_be = new be_t[dcache_words];
229
230	SC_METHOD(transition);
231	dont_initialize();
232	sensitive << p_clk.pos();
233
234	SC_METHOD(genMoore);
235	dont_initialize();
236	sensitive << p_clk.neg();
237
238	typename iss_t::CacheInfo cache_info;
239	cache_info.has_mmu = false;
240	cache_info.icache_line_size = icache_words*sizeof(data_t);
241	cache_info.icache_assoc = icache_ways;
242	cache_info.icache_n_lines = icache_sets;
243	cache_info.dcache_line_size = dcache_words*sizeof(data_t);
244	cache_info.dcache_assoc = dcache_ways;
245	cache_info.dcache_n_lines = dcache_sets;
246	m_iss.setCacheInfo(cache_info);
247
248	} // end constructor
249
250	///////////////////////////////////
251	tmpl(/**/)::~VciCcXCacheWrapperV1()
252	///////////////////////////////////
253	{
254	delete [] r_icache_miss_buf;
255	delete [] r_dcache_miss_buf;
256	delete [] r_tgt_be;
257	delete [] r_tgt_buf;
258	}
259
260	////////////////////////
261	tmpl(void)::print_cpi()
262	////////////////////////
263	{
264	std::cout << "CPU " << m_srcid_rw << " : CPI = "
265	<< (float)m_cpt_total_cycles/(m_cpt_total_cycles - m_cpt_frz_cycles) << std::endl ;
266	}
267	////////////////////////
268	tmpl(void)::print_stats()
269	////////////////////////
270	{
271	float run_cycles = (float)(m_cpt_total_cycles - m_cpt_frz_cycles);
272	std::cout << "------------------------------------" << std:: dec << std::endl;
273	std::cout << "CPU " << m_srcid_rw << " / Time = " << m_cpt_total_cycles << std::endl;
274	std::cout << "- CPI = " << (float)m_cpt_total_cycles/run_cycles << std::endl ;
275	std::cout << "- READ RATE = " << (float)m_cpt_read/run_cycles << std::endl ;
276	std::cout << "- WRITE RATE = " << (float)m_cpt_write/run_cycles << std::endl;
277	std::cout << "- UNCACHED READ RATE = " << (float)m_cpt_unc_read/m_cpt_read << std::endl ;
278	std::cout << "- CACHED WRITE RATE = " << (float)m_cpt_write_cached/m_cpt_write << std::endl ;
279	std::cout << "- IMISS_RATE = " << (float)m_cpt_ins_miss/run_cycles << std::endl;
280	std::cout << "- DMISS RATE = " << (float)m_cpt_data_miss/(m_cpt_read-m_cpt_unc_read) << std::endl ;
281	std::cout << "- INS MISS COST = " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl;
282	std::cout << "- IMISS TRANSACTION = " << (float)m_cost_imiss_transaction/m_cpt_imiss_transaction << std::endl;
283	std::cout << "- DMISS COST = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl;
284	std::cout << "- DMISS TRANSACTION = " << (float)m_cost_dmiss_transaction/m_cpt_dmiss_transaction << std::endl;
285	std::cout << "- UNC COST = " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl;
286	std::cout << "- UNC TRANSACTION = " << (float)m_cost_unc_transaction/m_cpt_unc_transaction << std::endl;
287	std::cout << "- WRITE COST = " << (float)m_cost_write_frz/m_cpt_write << std::endl;
288	std::cout << "- WRITE TRANSACTION = " << (float)m_cost_write_transaction/m_cpt_write_transaction << std::endl;
289	std::cout << "- WRITE LENGTH = " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl;
290	}
291
292	//////////////////////////
293	tmpl(void)::transition()
294	//////////////////////////
295	{
296	if ( ! p_resetn.read() ) {
297
298	m_iss.reset();
299
300	// FSM states
301	r_dcache_fsm = DCACHE_IDLE;
302	r_icache_fsm = ICACHE_IDLE;
303	r_vci_cmd_fsm = CMD_IDLE;
304	r_vci_rsp_fsm = RSP_IDLE;
305	r_vci_tgt_fsm = TGT_IDLE;
306
307	// write buffer & caches
308	r_wbuf.reset();
309	r_icache.reset();
310	r_dcache.reset();
311
312	// synchronisation flip-flops from ICACHE & DCACHE FSMs to VCI FSMs
313	r_icache_miss_req = false;
314	r_icache_unc_req = false;
315	r_icache_cleanup_req = false;
316	r_dcache_miss_req = false;
317	r_dcache_unc_req = false;
318	r_dcache_write_req = false;
319	r_dcache_cleanup_req = false;
320
321	// synchronisation flip-flops from TGT FSM to ICACHE & DCACHE FSMs
322	r_tgt_icache_req = false;
323	r_tgt_dcache_req = false;
324
325	// internal messages in DCACHE et ICACHE FSMs
326	r_icache_inval_rsp = false;
327	r_dcache_inval_rsp = false;
328
329	// error signals from the VCI RSP FSM to the ICACHE or DCACHE FSMs
330	r_dcache_buf_unc_valid = false;
331	r_icache_buf_unc_valid = false;
332	r_vci_rsp_data_error = false;
333	r_vci_rsp_ins_error = false;
334
335	// activity counters
336	m_cpt_dcache_data_read = 0;
337	m_cpt_dcache_data_write = 0;
338	m_cpt_dcache_dir_read = 0;
339	m_cpt_dcache_dir_write = 0;
340	m_cpt_icache_data_read = 0;
341	m_cpt_icache_data_write = 0;
342	m_cpt_icache_dir_read = 0;
343	m_cpt_icache_dir_write = 0;
344
345	m_cpt_cc_update = 0;
346	m_cpt_cc_inval = 0;
347
348	m_cpt_frz_cycles = 0;
349	m_cpt_total_cycles = 0;
350
351	m_cpt_read = 0;
352	m_cpt_write = 0;
353	m_cpt_data_miss = 0;
354	m_cpt_ins_miss = 0;
355	m_cpt_unc_read = 0;
356	m_cpt_write_cached = 0;
357
358	m_cost_write_frz = 0;
359	m_cost_data_miss_frz = 0;
360	m_cost_unc_read_frz = 0;
361	m_cost_ins_miss_frz = 0;
362
363	m_cpt_imiss_transaction = 0;
364	m_cpt_dmiss_transaction = 0;
365	m_cpt_unc_transaction = 0;
366	m_cpt_write_transaction = 0;
367
368	m_cost_imiss_transaction = 0;
369	m_cost_dmiss_transaction = 0;
370	m_cost_unc_transaction = 0;
371	m_cost_write_transaction = 0;
372	m_length_write_transaction = 0;
373
374	return;
375	}
376
377	#if DEBUG_CC_XCACHE_WRAPPER
378	std::cout << "--------------------------------------------" << std::endl;
379	std::cout << std::dec << "CC_XCACHE_WRAPPER " << m_srcid_rw << " / Time = " << m_cpt_total_cycles << std::endl;
380	std::cout << " tgt fsm = " << tgt_fsm_state_str[r_vci_tgt_fsm] << std::endl
381	<< " dcache fsm = " << dcache_fsm_state_str[r_dcache_fsm] << std::endl
382	<< " icache fsm = " << icache_fsm_state_str[r_icache_fsm] << std::endl
383	<< " cmd fsm = " << cmd_fsm_state_str[r_vci_cmd_fsm] << std::endl
384	<< " rsp fsm = " << rsp_fsm_state_str[r_vci_rsp_fsm] << std::endl;
385	#endif
386
387	m_cpt_total_cycles++;
388
389	/////////////////////////////////////////////////////////////////////
390	// The TGT_FSM controls the following ressources:
391	// - r_vci_tgt_fsm
392	// - r_tgt_buf[nwords]
393	// - r_tgt_be[nwords]
394	// - r_tgt_update
395	// - r_data_update
396	// - r_tgt_word
397	// - r_tgt_addr
398	// - r_tgt_srcid
399	// - r_tgt_trdid
400	// - r_tgt_pktid
401	// All VCI commands must be CMD_WRITE.
402	// If the VCI address offset is null, the command is an invalidate
403	// request. It is an update request otherwise.
404	// The VCI_TGT FSM stores the external request arguments in the
405	// IDLE, UPDT_WORD & UPDT_DATA states. It sets the r_tgt_icache_req
406	// & r_tgt_dcache_req flip-flops to signal the external request to
407	// the ICACHE & DCACHE FSMs in the REQ state. It waits the completion
408	// of the update or invalidate request in the RSP state.
409	// - for an invalidate request the VCI packet length is 1 word.
410	// The WDATA field contains the line index (i.e. the Z & Y fields).
411	// - for an update request the VCI packet length is (n+2) words.
412	// The WDATA field of the first VCI word contains the line number.
413	// The WDATA field of the second VCI word contains the word index.
414	// The WDATA field of the n following words contains the values.
415	// - for both invalidate & update requests, the VCI response
416	// is one single word.
417	// In case of errors in the VCI command packet, the simulation
418	// is stopped with an error message.
419	/////////////////////////////////////////////////////////////////////
420
421	switch(r_vci_tgt_fsm) {
422
423	case TGT_IDLE:
424	if ( p_vci_tgt.cmdval.read() )
425	{
426	addr_40 address = p_vci_tgt.address.read();
427
428	if ( p_vci_tgt.cmd.read() != vci_param::CMD_WRITE)
429	{
430	std::cout << "error in component VCI_CC_XCACHE_WRAPPER " << name() << std::endl;
431	std::cout << "the received VCI command from " << std::dec << p_vci_tgt.srcid.read() << " is not a write" << std::endl;
432	exit(0);
433	}
434
435	// multi-update or multi-invalidate for data type
436	if ( ((address&0x3) != 0x3) && (! m_segment.contains(address)) )
437	{
438	std::cout << "error in component VCI_CC_XCACHE_WRAPPER " << name() << std::endl;
439	std::cout << "out of segment VCI command received for a multi-updt or multi-inval request" << std::endl;
440	exit(0);
441	}
442
443	r_tgt_addr = (((addr_40) ((p_vci_tgt.be.read() & 0x3) << 32)) \|
444	((addr_40) (p_vci_tgt.wdata.read()))) * m_dcache_words * 4;
445	r_tgt_srcid = p_vci_tgt.srcid.read();
446	r_tgt_trdid = p_vci_tgt.trdid.read();
447	r_tgt_pktid = p_vci_tgt.pktid.read();
448	r_tgt_plen = p_vci_tgt.plen.read();
449
450	if ( (address&0x3) == 0x3 ) // broadcast invalidate for data or instruction type
451	{
452	if ( ! p_vci_tgt.eop.read() )
453	{
454	std::cout << "error in component VCI_CC_XCACHE_WRAPPER " << name() << std::endl;
455	std::cout << "the BROADCAST INVALIDATE command length must be one word" << std::endl;
456	exit(0);
457	}
458	r_tgt_update = false;
459	r_tgt_brdcast= true;
460	r_vci_tgt_fsm = TGT_REQ_BROADCAST;
461	m_cpt_cc_inval++ ;
462	}
463	else // multi-update or multi-invalidate for data type
464	{
465	uint32_t cell = address - m_segment.baseAddress(); // addr_40
466	r_tgt_brdcast = false;
467	if (cell == 0)
468	{ // invalidate
469	if ( ! p_vci_tgt.eop.read() )
470	{
471	std::cout << "error in component VCI_CC_XCACHE_WRAPPER " << name() << std::endl;
472	std::cout << "the MULTI-INVALIDATE command length must be one word" << std::endl;
473	exit(0);
474	}
475	r_tgt_update = false;
476	r_vci_tgt_fsm = TGT_REQ_DCACHE;
477	m_cpt_cc_inval++ ;
478	}
479	else if (cell == 4) // update data
480	{
481	if ( p_vci_tgt.eop.read() )
482	{
483	std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
484	std::cout << "the MULTI-UPDATE command length must be N+2 words" << std::endl;
485	exit(0);
486	}
487	r_data_update = true;
488	r_tgt_update = true;
489	r_vci_tgt_fsm = TGT_UPDT_WORD;
490	m_cpt_cc_update++ ;
491	}
492	else if (cell == 8) // invalidate instruction
493	{
494	if ( ! p_vci_tgt.eop.read() )
495	{
496	std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
497	std::cout << "the MULTI-INVALIDATE command length must be one word" << std::endl;
498	exit(0);
499	}
500	r_tgt_update = false;
501	r_vci_tgt_fsm = TGT_REQ_ICACHE;
502	m_cpt_cc_inval++ ;
503	}
504	else if (cell == 12) // update ins
505	{
506	if ( p_vci_tgt.eop.read() )
507	{
508	std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
509	std::cout << "the MULTI-UPDATE command length must be N+2 words" << std::endl;
510	exit(0);
511	}
512	r_data_update = false;
513	r_tgt_update = true;
514	r_vci_tgt_fsm = TGT_UPDT_WORD;
515	m_cpt_cc_update++ ;
516	}
517
518	} // end if address
519	} // end if cmdval
520	break;
521
522	case TGT_UPDT_WORD:
523	if (p_vci_tgt.cmdval.read())
524	{
525	if ( p_vci_tgt.eop.read() )
526	{
527	std::cout << "error in component VCI_CC_XCACHE_WRAPPER " << name() << std::endl;
528	std::cout << "the MULTI-UPDATE command length must be N+2 words" << std::endl;
529	exit(0);
530	}
531	for ( size_t i=0 ; i<m_dcache_words ; i++ ) r_tgt_be[i] = 0;
532	r_tgt_word = p_vci_tgt.wdata.read(); // the first modified word index
533	r_vci_tgt_fsm = TGT_UPDT_DATA;
534	}
535	break;
536
537	case TGT_UPDT_DATA:
538	if (p_vci_tgt.cmdval.read())
539	{
540	size_t word = r_tgt_word.read();
541	if ( word >= m_dcache_words )
542	{
543	std::cout << "error in component VCI_CC_XCACHE_WRAPPER " << name() << std::endl;
544	std::cout << "the received MULTI-UPDATE command length is wrong" << std::endl;
545	exit(0);
546	}
547	r_tgt_buf[word] = p_vci_tgt.wdata.read();
548	r_tgt_be[word] = p_vci_tgt.be.read();
549	r_tgt_word = word + 1;
550	if (p_vci_tgt.eop.read()) {
551	if (r_data_update.read()) r_vci_tgt_fsm = TGT_REQ_DCACHE;
552	else r_vci_tgt_fsm = TGT_REQ_ICACHE;
553	}
554	}
555	break;
556
557	case TGT_REQ_BROADCAST:
558	if ( !r_tgt_icache_req.read() && !r_tgt_dcache_req.read() )
559	{
560	r_vci_tgt_fsm = TGT_RSP_BROADCAST;
561	r_tgt_icache_req = true;
562	r_tgt_dcache_req = true;
563	}
564	break;
565	////////////////////
566	case TGT_REQ_ICACHE:
567	{
568	if ( !r_tgt_icache_req.read() )
569	{
570	r_vci_tgt_fsm = TGT_RSP_ICACHE;
571	r_tgt_icache_req = true;
572	}
573	break;
574	}
575
576	case TGT_REQ_DCACHE:
577	if ( !r_tgt_dcache_req.read() )
578	{
579	r_vci_tgt_fsm = TGT_RSP_DCACHE;
580	r_tgt_dcache_req = true;
581	}
582	break;
583
584	case TGT_RSP_BROADCAST:
585	if ( !r_tgt_icache_req.read() && !r_tgt_dcache_req.read() )
586	{
587	// one response
588	if ( !r_tgt_icache_rsp \|\| !r_tgt_dcache_rsp )
589	{
590	if ( p_vci_tgt.rspack.read() )
591	{
592	r_vci_tgt_fsm = TGT_IDLE;
593	r_tgt_icache_rsp = false;
594	r_tgt_dcache_rsp = false;
595	}
596	}
597
598	// if data and instruction have the inval line, need two responses
599	if ( r_tgt_icache_rsp && r_tgt_dcache_rsp )
600	{
601	if ( p_vci_tgt.rspack.read() )
602	{
603	r_tgt_icache_rsp = false; // only reset one for respond the second time
604	}
605	}
606
607	// if there is no need for a response
608	if ( !r_tgt_icache_rsp && !r_tgt_dcache_rsp )
609	{
610	r_vci_tgt_fsm = TGT_IDLE;
611	}
612
613	}
614	break;
615	////////////////////
616	case TGT_RSP_ICACHE:
617	{
618	if ( (p_vci_tgt.rspack.read() \|\| !r_tgt_icache_rsp.read()) && !r_tgt_icache_req.read() )
619	{
620	r_vci_tgt_fsm = TGT_IDLE;
621	r_tgt_icache_rsp = false;
622	}
623	break;
624	}
625
626	case TGT_RSP_DCACHE:
627	{
628	if ( (p_vci_tgt.rspack.read() \|\| !r_tgt_dcache_rsp.read()) && !r_tgt_dcache_req.read() )
629	{
630	r_vci_tgt_fsm = TGT_IDLE;
631	r_tgt_dcache_rsp = false;
632	}
633	break;
634	}
635	} // end switch TGT_FSM
636
637	/////////////////////////////////////////////////////////////////////
638	// The ICACHE FSM controls the following ressources:
639	// - r_icache_fsm
640	// - r_icache_fsm_save
641	// - r_icache instruction cache access
642	// - r_icache_addr_save
643	// - r_icache_miss_req set
644	// - r_icache_unc_req set
645	// - r_icache_buf_unc_valid set
646	// - r_vci_rsp_ins_error reset
647	// - r_tgt_icache_req reset
648	// - ireq & irsp structures for communication with the processor
649	//
650	// 1/ External requests (update or invalidate) have highest priority.
651	// They are taken into account in the IDLE and WAIT states.
652	// As external hit should be extremly rare on the ICACHE,
653	// all external requests are handled as invalidate...
654	// In case of external request the ICACHE FSM goes to the CC_CHECK
655	// state to test the external hit, and returns in the
656	// pre-empted state after completion.
657	// 2/ Processor requests are taken into account only in the IDLE state.
658	// In case of MISS, or in case of uncached instruction, the FSM
659	// writes the missing address line in the r_icache_addr_save register
660	// and sets the r_icache_miss_req or the r_icache_unc_req flip-flops.
661	// These request flip-flops are reset by the VCI_RSP FSM
662	// when the VCI transaction is completed and the r_icache_buf_unc_valid
663	// is set in case of uncached access.
664	// In case of bus error, the VCI_RSP FSM sets the r_vci_rsp_ins_error
665	// flip-flop. It is reset by the ICACHE FSM.
666	///////////////////////////////////////////////////////////////////////
667
668	typename iss_t::InstructionRequest ireq = ISS_IREQ_INITIALIZER;
669	typename iss_t::InstructionResponse irsp = ISS_IRSP_INITIALIZER;
670
671	typename iss_t::DataRequest dreq = ISS_DREQ_INITIALIZER;
672	typename iss_t::DataResponse drsp = ISS_DRSP_INITIALIZER;
673
674	m_iss.getRequests( ireq, dreq );
675
676	#if DEBUG_CC_XCACHE_WRAPPER
677	std::cout << " Instruction Request: " << ireq << std::endl;
678	#endif
679
680	switch(r_icache_fsm) {
681	/////////////////
682	case ICACHE_IDLE:
683	{
684	if ( r_tgt_icache_req ) { // external request
685	if ( ireq.valid ) m_cost_ins_miss_frz++;
686	r_icache_fsm = ICACHE_CC_CHECK;
687	r_icache_fsm_save = r_icache_fsm;
688	break;
689	}
690	if ( ireq.valid ) {
691	data_t icache_ins = 0;
692	bool icache_hit = false;
693	bool icache_cached = m_cacheability_table[(vci_addr_t)ireq.addr];
694	// icache_hit & icache_ins evaluation
695	if ( icache_cached ) {
696	icache_hit = r_icache.read((vci_addr_t) ireq.addr, &icache_ins);
697	} else {
698	icache_hit = ( r_icache_buf_unc_valid && ((addr_40) ireq.addr == (addr_40)r_icache_addr_save) );
699	icache_ins = r_icache_miss_buf[0];
700	}
701	if ( ! icache_hit ) {
702	m_cpt_ins_miss++;
703	m_cost_ins_miss_frz++;
704	r_icache_addr_save = (addr_40) ireq.addr;
705	if ( icache_cached ) {
706	r_icache_fsm = ICACHE_MISS_WAIT;
707	r_icache_miss_req = true;
708	} else {
709	r_icache_fsm = ICACHE_UNC_WAIT;
710	r_icache_unc_req = true;
711	}
712	} else {
713	r_icache_buf_unc_valid = false;
714	}
715	m_cpt_icache_dir_read += m_icache_ways;
716	m_cpt_icache_data_read += m_icache_ways;
717	irsp.valid = icache_hit;
718	irsp.instruction = icache_ins;
719	}
720	break;
721	}
722	//////////////////////
723	case ICACHE_MISS_WAIT:
724	{
725	m_cost_ins_miss_frz++;
726	if ( r_tgt_icache_req ) { // external request
727	r_icache_fsm = ICACHE_CC_CHECK;
728	r_icache_fsm_save = r_icache_fsm;
729	break;
730	}
731	if ( !r_icache_miss_req && !r_icache_inval_rsp ) { // Miss read response and no invalidation
732	if ( r_vci_rsp_ins_error ) {
733	r_icache_fsm = ICACHE_ERROR;
734	} else {
735	r_icache_fsm = ICACHE_MISS_UPDT;
736	}
737	}
738	if ( !r_icache_miss_req && r_icache_inval_rsp ) { // Miss read response and invalidation
739	if ( r_vci_rsp_ins_error ) {
740	r_icache_inval_rsp = false;
741	r_icache_fsm = ICACHE_ERROR;
742	} else {
743	r_icache_inval_rsp = false;
744	r_icache_fsm = ICACHE_CC_CLEANUP;
745	}
746	}
747	break;
748	}
749	/////////////////////
750	case ICACHE_UNC_WAIT:
751	{
752	m_cost_ins_miss_frz++;
753	if ( r_tgt_icache_req ) { // external request
754	r_icache_fsm = ICACHE_CC_CHECK;
755	r_icache_fsm_save = r_icache_fsm;
756	break;
757	}
758	if ( !r_icache_unc_req ) {
759	if ( r_vci_rsp_ins_error ) {
760	r_icache_fsm = ICACHE_ERROR;
761	} else {
762	r_icache_fsm = ICACHE_IDLE;
763	r_icache_buf_unc_valid = true;
764	}
765	}
766	break;
767	}
768	//////////////////
769	case ICACHE_ERROR:
770	{
771	r_icache_fsm = ICACHE_IDLE;
772	r_vci_rsp_ins_error = false;
773	irsp.error = true;
774	irsp.valid = true;
775	break;
776	}
777	//////////////////////
778	case ICACHE_MISS_UPDT:
779	{
780	if ( r_tgt_icache_req ) { // external request
781	r_icache_fsm = ICACHE_CC_CHECK;
782	r_icache_fsm_save = r_icache_fsm;
783	break;
784	}
785	if(!r_icache_cleanup_req.read() && !r_icache_inval_rsp){
786	vci_addr_t ad = 0;
787	ad = (vci_addr_t) r_icache_addr_save.read();
788	data_t* buf = r_icache_miss_buf;
789	vci_addr_t victim_index = 0;
790	m_cpt_icache_dir_write++;
791	m_cpt_icache_data_write++;
792	if ( ireq.valid ) m_cost_ins_miss_frz++;
793
794	r_icache_cleanup_req = r_icache.update(ad, buf, &victim_index);
795	r_icache_cleanup_line = (addr_40) victim_index;
796
797	r_icache_fsm = ICACHE_IDLE;
798	break;
799	}
800	if(r_icache_inval_rsp){
801	if ( ireq.valid ) m_cost_ins_miss_frz++;
802	r_icache_inval_rsp = false;
803	r_icache_fsm = ICACHE_CC_CLEANUP;
804	break;
805	}
806	if ( ireq.valid ) m_cost_ins_miss_frz++;
807	}
808	////////////////////
809	case ICACHE_CC_CLEANUP:
810	{
811	// external cache invalidate request
812	if ( r_tgt_icache_req )
813	{
814	r_icache_fsm = ICACHE_CC_CHECK;
815	r_icache_fsm_save = r_icache_fsm;
816	break;
817	}
818	// cleanup
819	if(!r_icache_cleanup_req){
820	r_icache_cleanup_req = true;
821	r_icache_cleanup_line = r_icache_addr_save.read() >> (uint32_log2(m_icache_words) + 2);
822	r_icache_fsm = ICACHE_IDLE;
823	}
824	break;
825	}
826	case ICACHE_CC_CHECK: // read directory in case of invalidate or update request
827	{
828
829	m_cpt_icache_dir_read += m_icache_ways;
830	m_cpt_icache_data_read += m_icache_ways;
831	addr_40 ad = r_tgt_addr;
832	data_t icache_rdata = 0;
833
834	if(( ( r_icache_fsm_save == ICACHE_MISS_WAIT ) \|\| ( r_icache_fsm_save == ICACHE_MISS_UPDT ) ) &&
835	( (r_icache_addr_save.read() & ~((m_icache_words<<2)-1)) == (ad & ~((m_icache_words<<2)-1)))) {
836	r_icache_inval_rsp = true;
837	r_tgt_icache_req = false;
838	if(r_tgt_update){ // Also send a cleanup and answer
839	r_tgt_icache_rsp = true;
840	} else { // Also send a cleanup but don't answer
841	r_tgt_icache_rsp = false;
842	}
843	r_icache_fsm = r_icache_fsm_save;
844	} else {
845	bool icache_hit = r_icache.read(ad, &icache_rdata);
846	if ( icache_hit && r_tgt_update ) {
847	r_icache_fsm = ICACHE_CC_UPDT;
848	// complete the line buffer in case of update
849	for ( size_t word = 0 ; word < m_icache_words ; word++ ) {
850	data_t mask = vci_param::be2mask(r_tgt_be[word]);
851	addr_40 ad = addr_40 (r_tgt_addr.read() + word*4); //(addr_40)word;
852	r_icache.read(ad, &icache_rdata);
853	r_tgt_buf[word] = (mask & r_tgt_buf[word]) \| (~mask & icache_rdata);
854	}
855	} else if ( icache_hit && !r_tgt_update ) {
856	r_icache_fsm = ICACHE_CC_INVAL;
857	} else { // instruction not found (can happen)
858	r_tgt_icache_req = false;
859	if(r_tgt_update){
860	r_tgt_icache_rsp = true;
861	} else {
862	r_tgt_icache_rsp = false;
863	}
864	r_icache_fsm = r_icache_fsm_save;
865	}
866	}
867	break;
868	}
869	///////////////////
870	case ICACHE_CC_UPDT: // update directory and data cache
871	{
872	m_cpt_icache_dir_write++;
873	m_cpt_icache_data_write++;
874	addr_40 ad = r_tgt_addr;
875	data_t* buf = r_tgt_buf;
876	for(size_t i=0; i<m_icache_words; i++){
877	if(r_tgt_be[i]) r_icache.write( ad + i*4, buf[i]);
878	}
879	r_tgt_icache_req = false;
880	r_tgt_icache_rsp = true;
881	r_icache_fsm = r_icache_fsm_save;
882	break;
883	}
884
885	/////////////////////
886	case ICACHE_CC_INVAL: // invalidate a cache line
887	{
888	addr_40 ad = r_tgt_addr;
889	r_tgt_icache_rsp = r_icache.inval(ad);
890	r_tgt_icache_req = false;
891	r_icache_fsm = r_icache_fsm_save;
892	break;
893	}
894
895	} // end switch r_icache_fsm
896
897	#if DEBUG_CC_XCACHE_WRAPPER
898	std::cout << " Instruction Response: " << irsp << std::endl;
899	#endif
900
901	//////////////////////////////////////////////////////////////////////://///////////
902	// The DCACHE FSM controls the following ressources:
903	// - r_dcache_fsm
904	// - r_dcache_fsm_save
905	// - r_dcache (data cache access)
906	// - r_dcache_addr_save
907	// - r_dcache_wdata_save
908	// - r_dcache_rdata_save
909	// - r_dcache_type_save
910	// - r_dcache_be_save
911	// - r_dcache_cached_save
912	// - r_dcache_miss_req set
913	// - r_dcache_unc_req set
914	// - r_dcache_write_req set
915	// - r_dcache_cleanup_req set
916	// - r_vci_rsp_data_error reset
917	// - r_tgt_dcache_req reset
918	// - r_wbuf write
919	// - dreq & drsp structures for communication with the processor
920	//
921	// 1/ EXTERNAL REQUEST :
922	// There is an external request when the tgt_dcache req flip-flop is set,
923	// requesting a line invalidation or a line update.
924	// External requests are taken into account in the states IDLE, WRITE_REQ,
925	// UNC_WAIT, MISS_WAIT, and have the highest priority :
926	// The actions associated to the pre-empted state are not executed, the DCACHE FSM
927	// goes to the CC_CHECK state to execute the requested action, and returns to the
928	// pre-empted state.
929	// 2/ PROCESSOR REQUEST :
930	// In order to support VCI write burst, the processor requests are taken into account
931	// in the WRITE_REQ state as well as in the IDLE state.
932	// - In the IDLE state, the processor request cannot be satisfied if
933	// there is a cached read miss, or an uncached read.
934	// - In the WRITE_REQ state, the request cannot be satisfied if
935	// there is a cached read miss, or an uncached read,
936	// or when the write buffer is full.
937	// - In all other states, the processor request is not satisfied.
938	//
939	// The cache access takes into account the cacheability_table.
940	// In case of processor request, there is five conditions to exit the IDLE state:
941	// - CACHED READ MISS => to the MISS_WAIT state (waiting the r_miss_ok signal),
942	// then to the MISS_UPDT state, and finally to the IDLE state.
943	// - UNCACHED READ => to the UNC_WAIT state (waiting the r_miss_ok signal),
944	// and to the IDLE state.
945	// - CACHE INVALIDATE HIT => to the INVAL state for one cycle, then to IDLE state.
946	// - WRITE MISS => directly to the WRITE_REQ state to access the write buffer.
947	// - WRITE HIT => to the WRITE_UPDT state, then to the WRITE_REQ state.
948	//
949	// Error handling : Read Bus Errors are synchronous events, but
950	// Write Bus Errors are asynchronous events (processor is not frozen).
951	// - If a Read Bus Error is detected, the VCI_RSP FSM sets the
952	// r_vci_rsp_data_error flip-flop, and the synchronous error is signaled
953	// by the DCACHE FSM.
954	// - If a Write Bus Error is detected, the VCI_RSP FSM signals
955	// the asynchronous error using the setWriteBerr() method.
956	///////////////////////////////////////////////////////////////////////////////////
957
958	#if DEBUG_CC_XCACHE_WRAPPER
959	std::cout << " Data Request: " << dreq << std::endl;
960	#endif
961
962	//if( (m_cpt_total_cycles % 10000) ==0 ) std::cout << std::dec << "Proc " << m_srcid << " Data Request: " << dreq << std::endl;
963
964	switch ( r_dcache_fsm ) {
965
966	/////////////////////
967	case DCACHE_WRITE_REQ:
968	{
969	if ( r_tgt_dcache_req ) { // external request
970	r_dcache_fsm = DCACHE_CC_CHECK;
971	r_dcache_fsm_save = r_dcache_fsm;
972	break;
973	}
974	// try to post the write request in the write buffer
975	if ( !r_dcache_write_req ) { // no previous write transaction
976	if ( r_wbuf.wok(r_dcache_addr_save) ) { // write request in the same cache line
977	r_wbuf.write(r_dcache_addr_save, r_dcache_be_save, r_dcache_wdata_save);
978	// close the write packet if uncached
979	if ( !r_dcache_cached_save ){
980	r_dcache_write_req = true ;
981	}
982	} else {
983	// close the write packet if write request not in the same cache line
984	r_dcache_write_req = true;
985	if(!m_srcid_rw) {
986	}
987	m_cost_write_frz++;
988	break; // posting request not possible : stay in DCACHE_WRITEREQ state
989	}
990	} else { // previous write transaction not completed
991	m_cost_write_frz++;
992	break; // posting request not possible : stay in DCACHE_WRITEREQ state
993	}
994
995	// close the write packet if the next processor request is not a write
996	if ( !dreq.valid \|\| (dreq.type != iss_t::DATA_WRITE) ) {
997	r_dcache_write_req = true ;
998	}
999
1000	// The next state and the processor request parameters are computed
1001	// as in the DCACHE_IDLE state (see below ...)
1002	}
1003	/////////////////
1004	case DCACHE_IDLE:
1005	{
1006	if ( r_tgt_dcache_req ) { // external request
1007	r_dcache_fsm = DCACHE_CC_CHECK;
1008	r_dcache_fsm_save = r_dcache_fsm;
1009	break;
1010	}
1011
1012	if ( dreq.valid ) {
1013	bool dcache_hit = false;
1014	data_t dcache_rdata = 0;
1015	bool dcache_cached;
1016	m_cpt_dcache_data_read += m_dcache_ways;
1017	m_cpt_dcache_dir_read += m_dcache_ways;
1018
1019	// dcache_cached evaluation
1020	switch (dreq.type) {
1021	case iss_t::DATA_LL:
1022	case iss_t::DATA_SC:
1023	case iss_t::XTN_READ:
1024	case iss_t::XTN_WRITE:
1025	dcache_cached = false;
1026	break;
1027	default:
1028	dcache_cached = m_cacheability_table[(vci_addr_t)dreq.addr];
1029	}
1030
1031	// dcache_hit & dcache_rdata evaluation
1032	if ( dcache_cached ) {
1033	dcache_hit = r_dcache.read((vci_addr_t) dreq.addr, &dcache_rdata);
1034	} else {
1035	dcache_hit = ( r_dcache_buf_unc_valid.read() && ((addr_40) dreq.addr == (addr_40)r_dcache_addr_save) );
1036	dcache_rdata = r_dcache_miss_buf[0];
1037	}
1038
1039	switch( dreq.type ) {
1040	case iss_t::DATA_READ:
1041	case iss_t::DATA_LL:
1042	case iss_t::DATA_SC:
1043	m_cpt_read++;
1044	if ( dcache_hit ) {
1045	r_dcache_fsm = DCACHE_IDLE;
1046	drsp.valid = true;
1047	drsp.rdata = dcache_rdata;
1048	r_dcache_buf_unc_valid = false;
1049	} else {
1050	if ( dcache_cached ) {
1051	m_cpt_data_miss++;
1052	m_cost_data_miss_frz++;
1053	r_dcache_miss_req = true;
1054	r_dcache_fsm = DCACHE_MISS_WAIT;
1055	} else {
1056	m_cpt_unc_read++;
1057	m_cost_unc_read_frz++;
1058	r_dcache_unc_req = true;
1059	r_dcache_fsm = DCACHE_UNC_WAIT;
1060	}
1061	}
1062	break;
1063	case iss_t::XTN_READ:
1064	case iss_t::XTN_WRITE:
1065	// only DCACHE INVALIDATE request are supported
1066	if ( dreq.addr/4 == iss_t::XTN_DCACHE_INVAL ){
1067	r_dcache_fsm = DCACHE_INVAL;
1068	} else {
1069	r_dcache_fsm = DCACHE_IDLE;
1070	}
1071	drsp.valid = true;
1072	drsp.rdata = 0;
1073	break;
1074	case iss_t::DATA_WRITE:
1075	m_cpt_write++;
1076	if ( dcache_hit && dcache_cached ) {
1077	r_dcache_fsm = DCACHE_WRITE_UPDT;
1078	m_cpt_write_cached++;
1079	} else {
1080	r_dcache_fsm = DCACHE_WRITE_REQ;
1081	}
1082	drsp.valid = true;
1083	drsp.rdata = 0;
1084	break;
1085	} // end switch dreq.type
1086
1087	r_dcache_addr_save = (addr_40) dreq.addr;
1088	r_dcache_type_save = dreq.type;
1089	r_dcache_wdata_save = dreq.wdata;
1090	r_dcache_be_save = dreq.be;
1091	r_dcache_rdata_save = dcache_rdata;
1092	r_dcache_cached_save = dcache_cached;
1093
1094	} else { // end if dreq.valid
1095	r_dcache_fsm = DCACHE_IDLE;
1096	}
1097	// processor request are not accepted in the WRITE_REQUEST state
1098	// when the write buffer is not writeable
1099	if ( (r_dcache_fsm == DCACHE_WRITE_REQ) &&
1100	(r_dcache_write_req \|\| !r_wbuf.wok(r_dcache_addr_save)) ) {
1101	drsp.valid = false;
1102	drsp.rdata = 0;
1103	}
1104	break;
1105	}
1106	///////////////////////
1107	case DCACHE_WRITE_UPDT:
1108	{
1109	m_cpt_dcache_data_write++;
1110	data_t mask = vci_param::be2mask(r_dcache_be_save);
1111	data_t wdata = (mask & r_dcache_wdata_save) \| (~mask & r_dcache_rdata_save);
1112	vci_addr_t ad = r_dcache_addr_save.read();
1113	r_dcache.write(ad, wdata);
1114	r_dcache_fsm = DCACHE_WRITE_REQ;
1115	break;
1116	}
1117	//////////////////////
1118	case DCACHE_MISS_WAIT:
1119	{
1120
1121	if ( dreq.valid ) m_cost_data_miss_frz++;
1122	if ( r_tgt_dcache_req.read() ) { // external request
1123	r_dcache_fsm = DCACHE_CC_CHECK;
1124	r_dcache_fsm_save = r_dcache_fsm;
1125	break;
1126	}
1127	if ( !r_dcache_miss_req && !r_dcache_inval_rsp ) { // Miss read response and no invalidation
1128	if ( r_vci_rsp_data_error ) {
1129	r_dcache_fsm = DCACHE_ERROR;
1130	} else {
1131	r_dcache_fsm = DCACHE_MISS_UPDT;
1132	}
1133	break;
1134	}
1135	if ( !r_dcache_miss_req && r_dcache_inval_rsp ) { // Miss read response and invalidation
1136	if ( r_vci_rsp_data_error ) {
1137	r_dcache_inval_rsp = false;
1138	r_dcache_fsm = DCACHE_ERROR;
1139	} else {
1140	r_dcache_inval_rsp = false;
1141	r_dcache_fsm = DCACHE_CC_CLEANUP;
1142	}
1143	break;
1144	}
1145	break;
1146	}
1147	//////////////////////
1148	case DCACHE_MISS_UPDT:
1149
1150	{
1151	if ( r_tgt_dcache_req.read() ) { // external request
1152	r_dcache_fsm = DCACHE_CC_CHECK;
1153	r_dcache_fsm_save = r_dcache_fsm;
1154	break;
1155	}
1156	if( !r_dcache_cleanup_req.read() && !r_dcache_inval_rsp ){
1157	vci_addr_t ad = 0;
1158	ad = (vci_addr_t) r_dcache_addr_save.read();
1159	data_t* buf = new data_t[m_dcache_words];
1160	for(size_t i=0; i<m_dcache_words; i++) {
1161	buf[i] = r_dcache_miss_buf[i];
1162	}
1163	vci_addr_t victim_index = 0;
1164	if ( dreq.valid ) m_cost_data_miss_frz++;
1165	m_cpt_dcache_data_write++;
1166	m_cpt_dcache_dir_write++;
1167
1168	r_dcache_cleanup_req = r_dcache.update(ad, buf, &victim_index);
1169	r_dcache_cleanup_line = (addr_40) victim_index;
1170
1171	r_dcache_fsm = DCACHE_IDLE;
1172	delete [] buf;
1173	break;
1174	}
1175	if( r_dcache_inval_rsp ){
1176	r_dcache_inval_rsp = false;
1177	r_dcache_fsm = DCACHE_CC_CLEANUP;
1178	break;
1179	}
1180	break;
1181	}
1182	////////////////////
1183	case DCACHE_UNC_WAIT:
1184	{
1185	if ( dreq.valid ) m_cost_unc_read_frz++;
1186	if ( r_tgt_dcache_req ) { // external request
1187	r_dcache_fsm = DCACHE_CC_CHECK;
1188	r_dcache_fsm_save = r_dcache_fsm;
1189	break;
1190	}
1191	if ( !r_dcache_unc_req ) {
1192	if ( r_vci_rsp_data_error ) {
1193	r_dcache_fsm = DCACHE_ERROR;
1194	} else {
1195	r_dcache_fsm = DCACHE_IDLE;
1196	// If request was a DATA_SC we need to invalidate the corresponding cache line,
1197	// so that subsequent access to this line are read from RAM
1198	if (dreq.type == iss_t::DATA_SC) {
1199	r_dcache_fsm = DCACHE_INVAL;
1200	}
1201	r_dcache_buf_unc_valid = true;
1202	}
1203	}
1204	break;
1205	}
1206	//////////////////
1207	case DCACHE_ERROR:
1208	{
1209	r_dcache_fsm = DCACHE_IDLE;
1210	r_vci_rsp_data_error = false;
1211	drsp.error = true;
1212	drsp.valid = true;
1213	break;
1214	}
1215	/////////////////
1216	case DCACHE_INVAL:
1217	{
1218	if ( r_tgt_dcache_req.read() ) { // external request
1219	r_dcache_fsm = DCACHE_CC_CHECK;
1220	r_dcache_fsm_save = r_dcache_fsm;
1221	break;
1222	}
1223	if( !r_dcache_cleanup_req.read() ){
1224	m_cpt_dcache_dir_read += m_dcache_ways;
1225	vci_addr_t ad = r_dcache_addr_save.read();
1226	r_dcache_cleanup_req = r_dcache.inval(ad);
1227	r_dcache_cleanup_line = r_dcache_addr_save.read() >> (uint32_log2(m_dcache_words)+2);
1228
1229	r_dcache_fsm = DCACHE_IDLE;
1230	}
1231	break;
1232	}
1233	/////////////////////
1234	case DCACHE_CC_CHECK: // read directory in case of invalidate or update request
1235	{
1236
1237	m_cpt_dcache_dir_read += m_dcache_ways;
1238	m_cpt_dcache_data_read += m_dcache_ways;
1239	addr_40 ad = r_tgt_addr;
1240	data_t dcache_rdata = 0;
1241
1242	if(( ( r_dcache_fsm_save == DCACHE_MISS_WAIT ) \|\| ( r_dcache_fsm_save == DCACHE_MISS_UPDT ) ) &&
1243	( (r_dcache_addr_save.read() & ~((m_dcache_words<<2)-1)) == (ad & ~((m_dcache_words<<2)-1)))) {
1244	r_dcache_inval_rsp = true;
1245	r_tgt_dcache_req = false;
1246	if(r_tgt_update){ // Also send a cleanup and answer
1247	r_tgt_dcache_rsp = true;
1248	} else { // Also send a cleanup but don't answer
1249	r_tgt_dcache_rsp = false;
1250	}
1251	r_dcache_fsm = r_dcache_fsm_save;
1252	} else {
1253	bool dcache_hit = r_dcache.read(ad, &dcache_rdata);
1254	if ( dcache_hit && r_tgt_update ) {
1255	r_dcache_fsm = DCACHE_CC_UPDT;
1256	// complete the line buffer in case of update
1257	for ( size_t word = 0 ; word < m_dcache_words ; word++ ) {
1258	addr_40 ad = addr_40 (r_tgt_addr.read() + word*4); //(addr_40)word;
1259	data_t mask = vci_param::be2mask(r_tgt_be[word]);
1260	r_dcache.read(ad, &dcache_rdata);
1261	r_tgt_buf[word] = (mask & r_tgt_buf[word]) \| (~mask & dcache_rdata);
1262	}
1263	} else if ( dcache_hit && !r_tgt_update ) {
1264	r_dcache_fsm = DCACHE_CC_INVAL;
1265	} else { // data not found (can happen)
1266	if(r_tgt_update){
1267	r_tgt_dcache_rsp = true;
1268	} else {
1269	r_tgt_dcache_rsp = false;
1270	}
1271	r_tgt_dcache_req = false;
1272	r_dcache_fsm = r_dcache_fsm_save;
1273	}
1274	}
1275	break;
1276	}
1277	///////////////////
1278	case DCACHE_CC_UPDT: // update directory and data cache
1279	{
1280	m_cpt_dcache_dir_write++;
1281	m_cpt_dcache_data_write++;
1282	addr_40 ad = r_tgt_addr;
1283	data_t* buf = r_tgt_buf;
1284	for(size_t i=0; i<m_dcache_words; i++){
1285	if(r_tgt_be[i]) r_dcache.write( ad + i*4, buf[i]);
1286	}
1287	r_tgt_dcache_req = false;
1288	r_tgt_dcache_rsp = true;
1289	r_dcache_fsm = r_dcache_fsm_save;
1290	break;
1291	}
1292	/////////////////////
1293	case DCACHE_CC_INVAL: // invalidate a cache line
1294	{
1295	addr_40 ad = r_tgt_addr;
1296	r_tgt_dcache_rsp = r_dcache.inval(ad);
1297	r_tgt_dcache_req = false;
1298	r_dcache_fsm = r_dcache_fsm_save;
1299	break;
1300	}
1301	///////////////////
1302	case DCACHE_CC_CLEANUP:
1303	{
1304	// external cache invalidate request
1305	if ( r_tgt_dcache_req )
1306	{
1307	r_dcache_fsm = DCACHE_CC_CHECK;
1308	r_dcache_fsm_save = r_dcache_fsm;
1309	break;
1310	}
1311	// cleanup
1312	if(!r_dcache_cleanup_req){
1313	r_dcache_cleanup_req = true;
1314	r_dcache_cleanup_line = r_dcache_addr_save.read() >> (uint32_log2(m_dcache_words) + 2);
1315	r_dcache_fsm = DCACHE_IDLE;
1316	}
1317	break;
1318	}
1319
1320	} // end switch r_dcache_fsm
1321
1322	#if DEBUG_CC_XCACHE_WRAPPER
1323	std::cout << " Data Response: " << drsp << std::endl;
1324	#endif
1325
1326	/////////// execute one iss cycle /////////////////////////////////////////////
1327	{
1328	uint32_t it = 0;
1329	for (size_t i=0; i<(size_t)iss_t::n_irq; i++)
1330	if(p_irq[i].read()) it \|= (1<<i);
1331	m_iss.executeNCycles(1, irsp, drsp, it);
1332	}
1333
1334	if ( (ireq.valid && !irsp.valid) \|\| (dreq.valid && !drsp.valid) ) m_cpt_frz_cycles++;
1335
1336
1337	////////////////////////////////////////////////////////////////////////////
1338	// The VCI_CMD FSM controls the following ressources:
1339	// - r_vci_cmd_fsm
1340	// - r_vci_cmd_min
1341	// - r_vci_cmd_max
1342	// - r_vci_cmd_cpt
1343	// - wbuf reset
1344	//
1345	// This FSM handles requests from both the DCACHE FSM & the ICACHE FSM.
1346	// There is 7 request types, with the following priorities :
1347	// 1 - Instruction Miss : r_icache_miss_req
1348	// 2 - Data Write : r_dcache_write_req
1349	// 3 - Data Read Miss : r_dcache_miss_req
1350	// 4 - Data Read Uncached : r_dcache_unc_req
1351	// 5 - Instruction Cleanup : r_icache_cleanup_req
1352	// 6 - Data Cleanup : r_dcache_cleanup_req
1353	// There is at most one (CMD/RSP) VCI transaction, as both CMD_FSM
1354	// and RSP_FSM exit simultaneously the IDLE state.
1355	//
1356	// VCI formats:
1357	// According to the VCI advanced specification, all read requests packets
1358	// (read Uncached, Miss data, Miss instruction) are one word packets.
1359	// For write burst packets, all words must be in the same cache line,
1360	// and addresses must be contiguous (the BE field is 0 in case of "holes").
1361	//////////////////////////////////////////////////////////////////////////////
1362
1363	switch (r_vci_cmd_fsm) {
1364
1365	case CMD_IDLE:
1366	if (r_vci_rsp_fsm != RSP_IDLE) break;
1367
1368	r_vci_cmd_cpt = 0;
1369	if ( r_icache_cleanup_req ) {
1370	r_vci_cmd_fsm = CMD_INS_CLEANUP;
1371	} else if ( r_dcache_cleanup_req ) {
1372	r_vci_cmd_fsm = CMD_DATA_CLEANUP;
1373	} else if ( r_icache_miss_req ) {
1374	r_vci_cmd_fsm = CMD_INS_MISS;
1375	m_cpt_imiss_transaction++;
1376	} else if ( r_icache_unc_req ) {
1377	r_vci_cmd_fsm = CMD_INS_UNC;
1378	m_cpt_imiss_transaction++;
1379	} else if ( r_dcache_write_req ) {
1380	r_vci_cmd_fsm = CMD_DATA_WRITE;
1381	r_vci_cmd_cpt = r_wbuf.getMin();
1382	r_vci_cmd_min = r_wbuf.getMin();
1383	r_vci_cmd_max = r_wbuf.getMax();
1384	m_cpt_write_transaction++;
1385	m_length_write_transaction += (r_wbuf.getMax() - r_wbuf.getMin() + 1);
1386	} else if ( r_dcache_miss_req ) {
1387	r_vci_cmd_fsm = CMD_DATA_MISS;
1388	m_cpt_dmiss_transaction++;
1389	} else if ( r_dcache_unc_req ) {
1390	r_vci_cmd_fsm = CMD_DATA_UNC;
1391	m_cpt_unc_transaction++;
1392	}
1393	break;
1394
1395	case CMD_DATA_WRITE:
1396	if ( p_vci_ini_rw.cmdack.read() ) {
1397	r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
1398	if (r_vci_cmd_cpt == r_vci_cmd_max) {
1399	r_vci_cmd_fsm = CMD_IDLE ;
1400	r_wbuf.reset() ;
1401	}
1402	}
1403	break;
1404
1405	case CMD_INS_MISS:
1406	case CMD_INS_UNC:
1407	case CMD_DATA_MISS:
1408	case CMD_DATA_UNC:
1409	if ( p_vci_ini_rw.cmdack.read() ) {
1410	r_vci_cmd_fsm = CMD_IDLE;
1411	}
1412	break;
1413	case CMD_INS_CLEANUP:
1414	case CMD_DATA_CLEANUP:
1415	if ( p_vci_ini_c.cmdack.read() ) {
1416	r_vci_cmd_fsm = CMD_IDLE;
1417	}
1418	break;
1419
1420	} // end switch r_vci_cmd_fsm
1421
1422	//////////////////////////////////////////////////////////////////////////
1423	// The VCI_RSP FSM controls the following ressources:
1424	// - r_vci_rsp_fsm:
1425	// - r_icache_miss_buf[m_icache_words]
1426	// - r_dcache_miss_buf[m_dcache_words]
1427	// - r_icache_miss_req reset
1428	// - r_icache_unc_req reset
1429	// - r_dcache_miss_req reset
1430	// - r_icache_cleanup_req reset
1431	// - r_dcache_cleanup_req reset
1432	// - r_vci_rsp_data_error set
1433	// - r_vci_rsp_ins_error set
1434	// - r_vci_rsp_cpt
1435	// In order to have only one active VCI transaction, this VCI_RSP_FSM
1436	// is synchronized with the VCI_CMD FSM, and both FSMs exit the
1437	// IDLE state simultaneously.
1438	//
1439	// VCI formats:
1440	// This component accepts single word or multi-word response packets for
1441	// write response packets.
1442	//
1443	// Error handling:
1444	// This FSM analyzes the VCI error code and signals directly the
1445	// Write Bus Error.
1446	// In case of Read Data Error, the VCI_RSP FSM sets the r_vci_rsp_data_error
1447	// flip_flop and the error is signaled by the DCACHE FSM.
1448	// In case of Instruction Error, the VCI_RSP FSM sets the r_vci_rsp_ins_error
1449	// flip_flop and the error is signaled by the DCACHE FSM.
1450	// In case of Cleanup Error, the simulation stops with an error message...
1451	//////////////////////////////////////////////////////////////////////////
1452
1453	switch (r_vci_rsp_fsm) {
1454
1455	case RSP_IDLE:
1456	if(p_vci_ini_rw.rspval.read()\|\|
1457	p_vci_ini_c.rspval.read())
1458	{
1459	std::cout << "CC_XCache " << m_srcid_rw << " Unexpected response" << std::endl;
1460	}
1461	assert( ! p_vci_ini_rw.rspval.read() && ! p_vci_ini_c.rspval.read() && "Unexpected response" );
1462	if (r_vci_cmd_fsm != CMD_IDLE) break;
1463
1464	r_vci_rsp_cpt = 0;
1465	if ( r_icache_cleanup_req ) r_vci_rsp_fsm = RSP_INS_CLEANUP;
1466	else if ( r_dcache_cleanup_req ) r_vci_rsp_fsm = RSP_DATA_CLEANUP;
1467	else if ( r_icache_miss_req ) r_vci_rsp_fsm = RSP_INS_MISS;
1468	else if ( r_icache_unc_req ) r_vci_rsp_fsm = RSP_INS_UNC;
1469	else if ( r_dcache_write_req ) r_vci_rsp_fsm = RSP_DATA_WRITE;
1470	else if ( r_dcache_miss_req ) r_vci_rsp_fsm = RSP_DATA_MISS;
1471	else if ( r_dcache_unc_req ) r_vci_rsp_fsm = RSP_DATA_UNC;
1472	break;
1473
1474	case RSP_INS_MISS:
1475	m_cost_imiss_transaction++;
1476	if ( ! p_vci_ini_rw.rspval.read() )
1477	break;
1478	assert( (r_vci_rsp_cpt < m_icache_words) &&
1479	"The VCI response packet for instruction miss is too long" );
1480	r_vci_rsp_cpt = r_vci_rsp_cpt + 1;
1481	r_icache_miss_buf[r_vci_rsp_cpt] = (data_t)p_vci_ini_rw.rdata.read();
1482
1483	if ( p_vci_ini_rw.reop.read() ) {
1484	assert( (r_vci_rsp_cpt == m_icache_words - 1) &&
1485	"The VCI response packet for instruction miss is too short");
1486	r_icache_miss_req = false;
1487	r_vci_rsp_fsm = RSP_IDLE;
1488	}
1489	if ( (p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL ) r_vci_rsp_ins_error = true;
1490	break;
1491
1492	case RSP_INS_UNC:
1493	m_cost_imiss_transaction++;
1494	if ( ! p_vci_ini_rw.rspval.read() )
1495	break;
1496	assert(p_vci_ini_rw.reop.read() &&
1497	"illegal VCI response packet for uncached instruction");
1498	r_icache_miss_buf[0] = (data_t)p_vci_ini_rw.rdata.read();
1499	r_vci_rsp_fsm = RSP_IDLE;
1500	r_icache_unc_req = false;
1501	if ( (p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL ) r_vci_rsp_ins_error = true;
1502	break;
1503
1504	case RSP_DATA_MISS:
1505	m_cost_dmiss_transaction++;
1506	if ( ! p_vci_ini_rw.rspval.read() )
1507	break;
1508	assert(r_vci_rsp_cpt != m_dcache_words &&
1509	"illegal VCI response packet for data read miss");
1510	r_vci_rsp_cpt = r_vci_rsp_cpt + 1;
1511	r_dcache_miss_buf[r_vci_rsp_cpt] = (data_t)p_vci_ini_rw.rdata.read();
1512	if ( p_vci_ini_rw.reop.read() ) {
1513	assert(r_vci_rsp_cpt == m_dcache_words - 1 &&
1514	"illegal VCI response packet for data read miss");
1515	r_dcache_miss_req = false;
1516	r_vci_rsp_fsm = RSP_IDLE;
1517	}
1518	if ( (p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL ) r_vci_rsp_data_error = true;
1519	break;
1520
1521	case RSP_DATA_WRITE:
1522	m_cost_write_transaction++;
1523	if ( ! p_vci_ini_rw.rspval.read() )
1524	break;
1525	if ( p_vci_ini_rw.reop.read() ) {
1526	r_vci_rsp_fsm = RSP_IDLE;
1527	r_dcache_write_req = false;
1528	}
1529	if ( (p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL ) m_iss.setWriteBerr();
1530	break;
1531
1532	case RSP_DATA_UNC:
1533	m_cost_unc_transaction++;
1534	if ( ! p_vci_ini_rw.rspval.read() )
1535	break;
1536	assert(p_vci_ini_rw.reop.read() &&
1537	"illegal VCI response packet for data read uncached");
1538	r_dcache_miss_buf[0] = (data_t)p_vci_ini_rw.rdata.read();
1539	r_vci_rsp_fsm = RSP_IDLE;
1540	r_dcache_unc_req = false;
1541	if ( (p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL ) r_vci_rsp_data_error = true;
1542	break;
1543
1544	case RSP_INS_CLEANUP:
1545	case RSP_DATA_CLEANUP:
1546	if ( ! p_vci_ini_c.rspval.read() )
1547	break;
1548	assert( p_vci_ini_c.reop.read() &&
1549	"illegal VCI response packet for icache cleanup");
1550	assert( ((p_vci_ini_c.rerror.read()&0x1) == vci_param::ERR_NORMAL) &&
1551	"error in response packet for icache cleanup");
1552	if ( r_vci_rsp_fsm == RSP_INS_CLEANUP ) r_icache_cleanup_req = false;
1553	else r_dcache_cleanup_req = false;
1554	r_vci_rsp_fsm = RSP_IDLE;
1555	break;
1556
1557	} // end switch r_vci_rsp_fsm
1558
1559	} // end transition()
1560
1561	//////////////////////////////////////////////////////////////////////////////////
1562	tmpl(void)::genMoore()
1563	//////////////////////////////////////////////////////////////////////////////////
1564	{
1565	// VCI initiator response
1566
1567	p_vci_ini_rw.rspack = true;
1568	p_vci_ini_c.rspack = true;
1569
1570	// VCI initiator command
1571
1572	switch (r_vci_cmd_fsm.read() ) {
1573
1574	case CMD_IDLE:
1575	p_vci_ini_rw.cmdval = false;
1576	p_vci_ini_rw.address = 0;
1577	p_vci_ini_rw.wdata = 0;
1578	p_vci_ini_rw.be = 0;
1579	p_vci_ini_rw.plen = 0;
1580	p_vci_ini_rw.cmd = vci_param::CMD_NOP;
1581	p_vci_ini_rw.trdid = 0;
1582	p_vci_ini_rw.pktid = 0;
1583	p_vci_ini_rw.srcid = 0;
1584	p_vci_ini_rw.cons = false;
1585	p_vci_ini_rw.wrap = false;
1586	p_vci_ini_rw.contig = false;
1587	p_vci_ini_rw.clen = 0;
1588	p_vci_ini_rw.cfixed = false;
1589	p_vci_ini_rw.eop = false;
1590
1591	p_vci_ini_c.cmdval = false;
1592	p_vci_ini_c.address = 0;
1593	p_vci_ini_c.wdata = 0;
1594	p_vci_ini_c.be = 0;
1595	p_vci_ini_c.plen = 0;
1596	p_vci_ini_c.cmd = vci_param::CMD_NOP;
1597	p_vci_ini_c.trdid = 0;
1598	p_vci_ini_c.pktid = 0;
1599	p_vci_ini_c.srcid = 0;
1600	p_vci_ini_c.cons = false;
1601	p_vci_ini_c.wrap = false;
1602	p_vci_ini_c.contig = false;
1603	p_vci_ini_c.clen = 0;
1604	p_vci_ini_c.cfixed = false;
1605	p_vci_ini_c.eop = false;
1606
1607	break;
1608
1609	case CMD_DATA_UNC:
1610	p_vci_ini_rw.cmdval = true;
1611	p_vci_ini_rw.address = (addr_40) r_dcache_addr_save.read() & ~0x3;
1612	switch( r_dcache_type_save ) {
1613	case iss_t::DATA_READ:
1614	p_vci_ini_rw.wdata = 0;
1615	p_vci_ini_rw.be = r_dcache_be_save.read();
1616	p_vci_ini_rw.cmd = vci_param::CMD_READ;
1617	break;
1618	case iss_t::DATA_LL:
1619	p_vci_ini_rw.wdata = 0;
1620	p_vci_ini_rw.be = 0xF;
1621	p_vci_ini_rw.cmd = vci_param::CMD_LOCKED_READ;
1622	break;
1623	case iss_t::DATA_SC:
1624	p_vci_ini_rw.wdata = r_dcache_wdata_save.read();
1625	p_vci_ini_rw.be = 0xF;
1626	p_vci_ini_rw.cmd = vci_param::CMD_STORE_COND;
1627	break;
1628	default:
1629	assert("this should not happen");
1630	}
1631	p_vci_ini_rw.plen = 4;
1632	p_vci_ini_rw.trdid = 0; // data cache uncached read
1633	p_vci_ini_rw.pktid = 0;
1634	p_vci_ini_rw.srcid = m_srcid_rw;
1635	p_vci_ini_rw.cons = false;
1636	p_vci_ini_rw.wrap = false;
1637	p_vci_ini_rw.contig = true;
1638	p_vci_ini_rw.clen = 0;
1639	p_vci_ini_rw.cfixed = false;
1640	p_vci_ini_rw.eop = true;
1641
1642	p_vci_ini_c.cmdval = false;
1643	p_vci_ini_c.address = 0;
1644	p_vci_ini_c.wdata = 0;
1645	p_vci_ini_c.be = 0;
1646	p_vci_ini_c.plen = 0;
1647	p_vci_ini_c.cmd = vci_param::CMD_NOP;
1648	p_vci_ini_c.trdid = 0;
1649	p_vci_ini_c.pktid = 0;
1650	p_vci_ini_c.srcid = 0;
1651	p_vci_ini_c.cons = false;
1652	p_vci_ini_c.wrap = false;
1653	p_vci_ini_c.contig = false;
1654	p_vci_ini_c.clen = 0;
1655	p_vci_ini_c.cfixed = false;
1656	p_vci_ini_c.eop = false;
1657
1658	break;
1659
1660	case CMD_DATA_WRITE:
1661	p_vci_ini_rw.cmdval = true;
1662	p_vci_ini_rw.address = r_wbuf.getAddress(r_vci_cmd_cpt)&~0x3;
1663	p_vci_ini_rw.wdata = r_wbuf.getData(r_vci_cmd_cpt);
1664	p_vci_ini_rw.be = r_wbuf.getBe(r_vci_cmd_cpt);
1665	p_vci_ini_rw.plen = (r_vci_cmd_max - r_vci_cmd_min + 1)<<2;
1666	p_vci_ini_rw.cmd = vci_param::CMD_WRITE;
1667	p_vci_ini_rw.trdid = 0; // data cache write
1668	p_vci_ini_rw.pktid = 0;
1669	p_vci_ini_rw.srcid = m_srcid_rw;
1670	p_vci_ini_rw.cons = false;
1671	p_vci_ini_rw.wrap = false;
1672	p_vci_ini_rw.contig = true;
1673	p_vci_ini_rw.clen = 0;
1674	p_vci_ini_rw.cfixed = false;
1675	p_vci_ini_rw.eop = (r_vci_cmd_cpt == r_vci_cmd_max);
1676
1677	p_vci_ini_c.cmdval = false;
1678	p_vci_ini_c.address = 0;
1679	p_vci_ini_c.wdata = 0;
1680	p_vci_ini_c.be = 0;
1681	p_vci_ini_c.plen = 0;
1682	p_vci_ini_c.cmd = vci_param::CMD_NOP;
1683	p_vci_ini_c.trdid = 0;
1684	p_vci_ini_c.pktid = 0;
1685	p_vci_ini_c.srcid = 0;
1686	p_vci_ini_c.cons = false;
1687	p_vci_ini_c.wrap = false;
1688	p_vci_ini_c.contig = false;
1689	p_vci_ini_c.clen = 0;
1690	p_vci_ini_c.cfixed = false;
1691	p_vci_ini_c.eop = false;
1692
1693	break;
1694
1695	case CMD_DATA_MISS:
1696	p_vci_ini_rw.cmdval = true;
1697	p_vci_ini_rw.address = r_dcache_addr_save.read() & (addr_40) m_dcache_yzmask;
1698	p_vci_ini_rw.be = 0xF;
1699	p_vci_ini_rw.plen = m_dcache_words << 2;
1700	p_vci_ini_rw.cmd = vci_param::CMD_READ;
1701	p_vci_ini_rw.trdid = 1; // data cache cached read
1702	p_vci_ini_rw.pktid = 0;
1703	p_vci_ini_rw.srcid = m_srcid_rw;
1704	p_vci_ini_rw.cons = false;
1705	p_vci_ini_rw.wrap = false;
1706	p_vci_ini_rw.contig = true;
1707	p_vci_ini_rw.clen = 0;
1708	p_vci_ini_rw.cfixed = false;
1709	p_vci_ini_rw.eop = true;
1710
1711	p_vci_ini_c.cmdval = false;
1712	p_vci_ini_c.address = 0;
1713	p_vci_ini_c.wdata = 0;
1714	p_vci_ini_c.be = 0;
1715	p_vci_ini_c.plen = 0;
1716	p_vci_ini_c.cmd = vci_param::CMD_NOP;
1717	p_vci_ini_c.trdid = 0;
1718	p_vci_ini_c.pktid = 0;
1719	p_vci_ini_c.srcid = 0;
1720	p_vci_ini_c.cons = false;
1721	p_vci_ini_c.wrap = false;
1722	p_vci_ini_c.contig = false;
1723	p_vci_ini_c.clen = 0;
1724	p_vci_ini_c.cfixed = false;
1725	p_vci_ini_c.eop = false;
1726
1727	break;
1728
1729	case CMD_INS_MISS:
1730	p_vci_ini_rw.cmdval = true;
1731	p_vci_ini_rw.address = r_icache_addr_save.read() & (addr_40) m_icache_yzmask;
1732	p_vci_ini_rw.be = 0xF;
1733	p_vci_ini_rw.plen = m_icache_words << 2;
1734	p_vci_ini_rw.cmd = vci_param::CMD_READ;
1735	p_vci_ini_rw.trdid = 3; // ins cache cached read
1736	p_vci_ini_rw.pktid = 0;
1737	p_vci_ini_rw.srcid = m_srcid_rw;
1738	p_vci_ini_rw.cons = false;
1739	p_vci_ini_rw.wrap = false;
1740	p_vci_ini_rw.contig = true;
1741	p_vci_ini_rw.clen = 0;
1742	p_vci_ini_rw.cfixed = false;
1743	p_vci_ini_rw.eop = true;
1744
1745	p_vci_ini_c.cmdval = false;
1746	p_vci_ini_c.address = 0;
1747	p_vci_ini_c.wdata = 0;
1748	p_vci_ini_c.be = 0;
1749	p_vci_ini_c.plen = 0;
1750	p_vci_ini_c.cmd = vci_param::CMD_NOP;
1751	p_vci_ini_c.trdid = 0;
1752	p_vci_ini_c.pktid = 0;
1753	p_vci_ini_c.srcid = 0;
1754	p_vci_ini_c.cons = false;
1755	p_vci_ini_c.wrap = false;
1756	p_vci_ini_c.contig = false;
1757	p_vci_ini_c.clen = 0;
1758	p_vci_ini_c.cfixed = false;
1759	p_vci_ini_c.eop = false;
1760
1761	break;
1762
1763	case CMD_INS_UNC:
1764	p_vci_ini_rw.cmdval = true;
1765	p_vci_ini_rw.address = r_icache_addr_save.read() & ~0x3;
1766	p_vci_ini_rw.be = 0xF;
1767	p_vci_ini_rw.plen = 4;
1768	p_vci_ini_rw.cmd = vci_param::CMD_READ;
1769	p_vci_ini_rw.trdid = 2; // ins cache uncached read
1770	p_vci_ini_rw.pktid = 0;
1771	p_vci_ini_rw.srcid = m_srcid_rw;
1772	p_vci_ini_rw.cons = false;
1773	p_vci_ini_rw.wrap = false;
1774	p_vci_ini_rw.contig = true;
1775	p_vci_ini_rw.clen = 0;
1776	p_vci_ini_rw.cfixed = false;
1777	p_vci_ini_rw.eop = true;
1778
1779	p_vci_ini_c.cmdval = false;
1780	p_vci_ini_c.address = 0;
1781	p_vci_ini_c.wdata = 0;
1782	p_vci_ini_c.be = 0;
1783	p_vci_ini_c.plen = 0;
1784	p_vci_ini_c.cmd = vci_param::CMD_NOP;
1785	p_vci_ini_c.trdid = 0;
1786	p_vci_ini_c.pktid = 0;
1787	p_vci_ini_c.srcid = 0;
1788	p_vci_ini_c.cons = false;
1789	p_vci_ini_c.wrap = false;
1790	p_vci_ini_c.contig = false;
1791	p_vci_ini_c.clen = 0;
1792	p_vci_ini_c.cfixed = false;
1793	p_vci_ini_c.eop = false;
1794
1795
1796	break;
1797
1798	case CMD_INS_CLEANUP:
1799	p_vci_ini_rw.cmdval = false;
1800	p_vci_ini_rw.address = 0;
1801	p_vci_ini_rw.wdata = 0;
1802	p_vci_ini_rw.be = 0;
1803	p_vci_ini_rw.plen = 0;
1804	p_vci_ini_rw.cmd = vci_param::CMD_NOP;
1805	p_vci_ini_rw.trdid = 0;
1806	p_vci_ini_rw.pktid = 0;
1807	p_vci_ini_rw.srcid = 0;
1808	p_vci_ini_rw.cons = false;
1809	p_vci_ini_rw.wrap = false;
1810	p_vci_ini_rw.contig = false;
1811	p_vci_ini_rw.clen = 0;
1812	p_vci_ini_rw.cfixed = false;
1813	p_vci_ini_rw.eop = false;
1814
1815	p_vci_ini_c.cmdval = true;
1816	p_vci_ini_c.address = r_icache_cleanup_line.read() * (m_icache_words<<2);
1817	p_vci_ini_c.wdata = 0;
1818	p_vci_ini_c.be = 0;
1819	p_vci_ini_c.plen = 4;
1820	p_vci_ini_c.cmd = vci_param::CMD_WRITE;
1821	p_vci_ini_c.trdid = 1; // cleanup instruction
1822	p_vci_ini_c.pktid = 0;
1823	p_vci_ini_c.srcid = m_srcid_c;
1824	p_vci_ini_c.cons = false;
1825	p_vci_ini_c.wrap = false;
1826	p_vci_ini_c.contig = false;
1827	p_vci_ini_c.clen = 0;
1828	p_vci_ini_c.cfixed = false;
1829	p_vci_ini_c.eop = true;
1830
1831	break;
1832
1833
1834	case CMD_DATA_CLEANUP:
1835	p_vci_ini_rw.cmdval = false;
1836	p_vci_ini_rw.address = 0;
1837	p_vci_ini_rw.wdata = 0;
1838	p_vci_ini_rw.be = 0;
1839	p_vci_ini_rw.plen = 0;
1840	p_vci_ini_rw.cmd = vci_param::CMD_NOP;
1841	p_vci_ini_rw.trdid = 0;
1842	p_vci_ini_rw.pktid = 0;
1843	p_vci_ini_rw.srcid = 0;
1844	p_vci_ini_rw.cons = false;
1845	p_vci_ini_rw.wrap = false;
1846	p_vci_ini_rw.contig = false;
1847	p_vci_ini_rw.clen = 0;
1848	p_vci_ini_rw.cfixed = false;
1849	p_vci_ini_rw.eop = false;
1850
1851	p_vci_ini_c.cmdval = true;
1852	p_vci_ini_c.address = r_dcache_cleanup_line.read() * (m_dcache_words<<2);
1853	p_vci_ini_c.wdata = 0;
1854	p_vci_ini_c.be = 0;
1855	p_vci_ini_c.plen = 4;
1856	p_vci_ini_c.cmd = vci_param::CMD_WRITE;
1857	p_vci_ini_c.trdid = 0; // cleanup data
1858	p_vci_ini_c.pktid = 0;
1859	p_vci_ini_c.srcid = m_srcid_c;
1860	p_vci_ini_c.cons = false;
1861	p_vci_ini_c.wrap = false;
1862	p_vci_ini_c.contig = false;
1863	p_vci_ini_c.clen = 0;
1864	p_vci_ini_c.cfixed = false;
1865	p_vci_ini_c.eop = true;
1866
1867	break;
1868
1869	} // end switch r_vci_cmd_fsm
1870
1871	// VCI_TGT
1872
1873	switch ( r_vci_tgt_fsm.read() ) {
1874
1875	case TGT_IDLE:
1876	case TGT_UPDT_WORD:
1877	case TGT_UPDT_DATA:
1878	p_vci_tgt.cmdack = true;
1879	p_vci_tgt.rspval = false;
1880	break;
1881
1882	case TGT_RSP_BROADCAST:
1883	p_vci_tgt.cmdack = false;
1884	p_vci_tgt.rspval = !r_tgt_icache_req.read() && !r_tgt_dcache_req.read() && ( r_tgt_icache_rsp \| r_tgt_dcache_rsp );
1885	p_vci_tgt.rsrcid = r_tgt_srcid.read();
1886	p_vci_tgt.rpktid = r_tgt_pktid.read();
1887	p_vci_tgt.rtrdid = r_tgt_trdid.read();
1888	p_vci_tgt.rdata = 0;
1889	p_vci_tgt.rerror = 0x2 & ( (1 << vci_param::E) - 1); // Write OK
1890	p_vci_tgt.reop = true;
1891	break;
1892
1893	case TGT_RSP_ICACHE:
1894	p_vci_tgt.cmdack = false;
1895	p_vci_tgt.rspval = !r_tgt_icache_req.read() && r_tgt_icache_rsp.read();
1896	p_vci_tgt.rsrcid = r_tgt_srcid.read();
1897	p_vci_tgt.rpktid = r_tgt_pktid.read();
1898	p_vci_tgt.rtrdid = r_tgt_trdid.read();
1899	p_vci_tgt.rdata = 0;
1900	p_vci_tgt.rerror = 0x2 & ( (1 << vci_param::E) - 1); // Write OK
1901	p_vci_tgt.reop = true;
1902	break;
1903
1904	case TGT_RSP_DCACHE:
1905	p_vci_tgt.cmdack = false;
1906	p_vci_tgt.rspval = !r_tgt_dcache_req.read() && r_tgt_dcache_rsp.read();
1907	p_vci_tgt.rsrcid = r_tgt_srcid.read();
1908	p_vci_tgt.rpktid = r_tgt_pktid.read();
1909	p_vci_tgt.rtrdid = r_tgt_trdid.read();
1910	p_vci_tgt.rdata = 0;
1911	p_vci_tgt.rerror = 0x2 & ( (1 << vci_param::E) - 1); // Write OK
1912	p_vci_tgt.reop = true;
1913	break;
1914
1915	case TGT_REQ_BROADCAST:
1916	case TGT_REQ_ICACHE:
1917	case TGT_REQ_DCACHE:
1918	p_vci_tgt.cmdack = false;
1919	p_vci_tgt.rspval = false;
1920	break;
1921
1922	} // end switch TGT_FSM
1923	} // end genMoore()
1924
1925	}} // end namespace
1926
1927	// Local Variables:
1928	// tab-width: 4
1929	// c-basic-offset: 4
1930	// c-file-offsets:((innamespace . 0)(inline-open . 0))
1931	// indent-tabs-mode: nil
1932	// End:
1933
1934	// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
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