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vci_cc_xcache_wrapper_v4.h @ 175

Last change on this file since 175 was 175, checked in by kane, 13 years ago
vci_cc_xcache_wrapper_v4 : suppress one state (CC_UPDATE)
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1	/* -- c++ --
2	*
3	* SOCLIB_LGPL_HEADER_BEGIN
4	*
5	* This file is part of SoCLib, GNU LGPLv2.1.
6	*
7	* SoCLib is free software; you can redistribute it and/or modify it
8	* under the terms of the GNU Lesser General Public License as published
9	* by the Free Software Foundation; version 2.1 of the License.
10	*
11	* SoCLib is distributed in the hope that it will be useful, but
12	* WITHOUT ANY WARRANTY; without even the implied warranty of
13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14	* Lesser General Public License for more details.
15	*
16	* You should have received a copy of the GNU Lesser General Public
17	* License along with SoCLib; if not, write to the Free Software
18	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
19	* 02110-1301 USA
20	*
21	* SOCLIB_LGPL_HEADER_END
22	*
23	* Copyright (c) UPMC, Lip6, SoC
24	* Alain Greiner <alain.greiner@lip6.fr>, 2008
25	*
26	* Maintainers: alain
27	*/
28
29	#ifndef SOCLIB_CABA_VCI_CC_XCACHE_WRAPPER_V4_H
30	#define SOCLIB_CABA_VCI_CC_XCACHE_WRAPPER_V4_H
31
32	#include <inttypes.h>
33	#include <fstream>
34	#include <systemc>
35	#include <queue>
36	#include "caba_base_module.h"
37	#include "multi_write_buffer.h"
38	#include "generic_cache.h"
39	#include "generic_fifo.h"
40	#include "vci_initiator.h"
41	#include "vci_target.h"
42	#include "mapping_table.h"
43	#include "static_assert.h"
44
45	/*
46	* ----------------------------------------------------------
47	* Implementation
48	* ----------------------------------------------------------
49	*
50	* CC_XCACHE_WRAPPER_MULTI_CACHE
51	* 1 - icache static partitionnement
52	* 2 - icache dedicated
53	*
54	* ----------------------------------------------------------
55	* Debug
56	* ----------------------------------------------------------
57	*
58	* CC_XCACHE_WRAPPER_STOP_SIMULATION
59	* stop simulation if processor is stall after a long time
60	* (configurable with "stop_simulation" function)
61	*
62	* CC_XCACHE_WRAPPER_DEBUG
63	* Add log to help the debugging
64	*
65	* CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN
66	* Number of cycle before to prinf debug message
67	*
68	* CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION
69	* Print transaction between :
70	* - the cpu and the cache (icache and dcache)
71	* - vci
72	* - cleanup
73	* - coherency
74	*
75	* MWBUF_VHDL_TESTBENCH
76	* generate a vhdl testbench for multi write buffer
77	*/
78
79	// implementation
80	#ifndef CC_XCACHE_WRAPPER_MULTI_CACHE
81	#define CC_XCACHE_WRAPPER_MULTI_CACHE 2
82	// if multi_cache :
83	// <tsar toplevel>/modules/vci_mem_cache_v4/caba/source/include/mem_cache_directory_v4.h : L1_MULTI_CACHE 1
84	#endif
85
86	// debug
87	#ifndef CC_XCACHE_WRAPPER_STOP_SIMULATION
88	#define CC_XCACHE_WRAPPER_STOP_SIMULATION 1
89	#endif
90	#ifndef CC_XCACHE_WRAPPER_DEBUG
91	#define CC_XCACHE_WRAPPER_DEBUG 0
92	#endif
93	#ifndef CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN
94	#define CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN 1013300
95	#endif
96	#ifndef CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION
97	#define CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 0
98	#define CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION_PATH "log"
99	#endif
100	#ifndef MWBUF_VHDL_TESTBENCH
101	#define MWBUF_VHDL_TESTBENCH 0
102	#endif
103
104	namespace soclib {
105	namespace caba {
106
107	using namespace sc_core;
108
109	////////////////////////////////////////////
110	template<typename vci_param, typename iss_t>
111	class VciCcXCacheWrapperV4
112	///////////////////////////////////////////
113	: public soclib::caba::BaseModule
114	{
115	typedef uint64_t vhdl_tb_t;
116	typedef sc_dt::sc_uint<40> addr_40;
117	typedef uint32_t data_t;
118	typedef uint32_t tag_t;
119	typedef uint32_t be_t;
120	typedef typename vci_param::fast_addr_t vci_addr_t;
121
122	enum dcache_fsm_state_e {
123	DCACHE_IDLE,
124	DCACHE_WRITE_UPDT,
125	DCACHE_MISS_VICTIM,
126	DCACHE_MISS_WAIT,
127	DCACHE_MISS_UPDT,
128	DCACHE_UNC_WAIT,
129	DCACHE_SC_WAIT,
130	DCACHE_INVAL,
131	DCACHE_SYNC,
132	DCACHE_ERROR,
133	DCACHE_CC_CHECK,
134	DCACHE_CC_INVAL,
135	DCACHE_CC_CLEANUP,
136	};
137
138	enum icache_fsm_state_e {
139	ICACHE_IDLE,
140	ICACHE_MISS_VICTIM,
141	ICACHE_MISS_WAIT,
142	ICACHE_MISS_UPDT,
143	ICACHE_UNC_WAIT,
144	ICACHE_ERROR,
145	ICACHE_CC_CLEANUP,
146	ICACHE_CC_CHECK,
147	ICACHE_CC_INVAL,
148	};
149
150	enum cmd_fsm_state_e {
151	CMD_IDLE,
152	CMD_INS_MISS,
153	CMD_INS_UNC,
154	CMD_DATA_MISS,
155	CMD_DATA_UNC,
156	CMD_DATA_WRITE,
157	CMD_DATA_SC,
158	};
159
160	enum rsp_fsm_state_e {
161	RSP_IDLE,
162	RSP_INS_MISS,
163	RSP_INS_UNC,
164	RSP_DATA_MISS,
165	RSP_DATA_UNC,
166	RSP_DATA_WRITE,
167	RSP_DATA_SC,
168	};
169
170	enum tgt_fsm_state_e {
171	TGT_IDLE,
172	TGT_UPDT_WORD,
173	TGT_UPDT_DATA,
174	TGT_REQ_BROADCAST,
175	TGT_REQ_ICACHE,
176	TGT_REQ_DCACHE,
177	TGT_RSP_BROADCAST,
178	TGT_RSP_ICACHE,
179	TGT_RSP_DCACHE,
180	};
181
182	enum cleanup_fsm_state_e {
183	CLEANUP_IDLE,
184	CLEANUP_REQ,
185	CLEANUP_RSP_DCACHE,
186	CLEANUP_RSP_ICACHE,
187	};
188
189	enum transaction_type_c_e {
190	// convention with memcache
191	TYPE_DATA_CLEANUP = 0x0,
192	TYPE_INS_CLEANUP = 0x1
193	};
194
195	enum transaction_type_rw_e {
196	// convention with memcache
197	// b0 : 1 if cached
198	// b1 : 1 if instruction
199	// b2 : 1 if sc
200	TYPE_DATA_UNC = 0x0,
201	TYPE_DATA_MISS = 0x1,
202	TYPE_INS_UNC = 0x2,
203	TYPE_INS_MISS = 0x3,
204	TYPE_DATA_SC = 0x4, // sc is data and no cached
205	};
206
207	public:
208
209	// PORTS
210	sc_in<bool> p_clk;
211	sc_in<bool> p_resetn;
212	sc_in<bool> ** p_irq;//[m_nb_cpu][iss_t::n_irq];
213	soclib::caba::VciInitiator<vci_param> p_vci_ini_rw;
214	soclib::caba::VciInitiator<vci_param> p_vci_ini_c;
215	soclib::caba::VciTarget<vci_param> p_vci_tgt;
216
217	private:
218
219	// STRUCTURAL PARAMETERS
220	const soclib::common::AddressDecodingTable<vci_addr_t, bool> m_cacheability_table;
221	const soclib::common::Segment m_segment;
222	iss_t ** m_iss; //[m_nb_cpu]
223	const uint32_t m_srcid_rw;
224	const uint32_t m_srcid_c;
225
226	const size_t m_nb_cpu;
227	const size_t m_nb_icache;
228	const size_t m_nb_dcache;
229	const size_t m_nb_cache;
230	const size_t m_dcache_ways;
231	const size_t m_dcache_words;
232	const uint32_t m_dcache_words_shift;
233	const size_t m_dcache_yzmask;
234	const size_t m_icache_ways;
235	const size_t m_icache_words;
236	const uint32_t m_icache_words_shift;
237	const size_t m_icache_yzmask;
238	const size_t m_cache_words; // max between m_dcache_words and m_icache_words
239
240	#if CC_XCACHE_WRAPPER_STOP_SIMULATION
241	bool m_stop_simulation;
242	uint32_t m_stop_simulation_nb_frz_cycles_max;
243	uint32_t * m_stop_simulation_nb_frz_cycles; //[m_nb_cpu]
244	#endif // CC_XCACHE_WRAPPER_STOP_SIMULATION
245
246	// REGISTERS
247	sc_signal<uint32_t> r_cpu_prior;
248	sc_signal<uint32_t> * r_icache_lock;//[m_nb_icache]
249	sc_signal<uint32_t> * r_dcache_lock;//[m_nb_dcache]
250	sc_signal<bool> * r_dcache_sync;//[m_nb_dcache]
251
252	sc_signal<int> * r_dcache_fsm; //[m_nb_dcache]
253	sc_signal<int> * r_dcache_fsm_save; //[m_nb_dcache]
254	sc_signal<addr_40> * r_dcache_addr_save; //[m_nb_dcache]
255	sc_signal<data_t> * r_dcache_wdata_save; //[m_nb_dcache]
256	sc_signal<data_t> * r_dcache_rdata_save; //[m_nb_dcache]
257	sc_signal<int> * r_dcache_type_save; //[m_nb_dcache]
258	sc_signal<be_t> * r_dcache_be_save; //[m_nb_dcache]
259	sc_signal<bool> * r_dcache_cached_save; //[m_nb_dcache]
260	sc_signal<uint32_t> * r_dcache_num_cpu_save; //[m_nb_dcache]
261	sc_signal<bool> * r_dcache_cleanup_req; //[m_nb_dcache]
262	sc_signal<addr_40> * r_dcache_cleanup_line; //[m_nb_dcache]
263	sc_signal<bool> * r_dcache_miss_req; //[m_nb_dcache]
264	sc_signal<size_t> * r_dcache_miss_way; //[m_nb_dcache]
265	sc_signal<size_t> * r_dcache_miss_set; //[m_nb_dcache]
266	sc_signal<bool> * r_dcache_unc_req; //[m_nb_dcache]
267	sc_signal<bool> * r_dcache_sc_req; //[m_nb_dcache]
268	sc_signal<bool> * r_dcache_inval_rsp; //[m_nb_dcache]
269	sc_signal<size_t> * r_dcache_update_addr; //[m_nb_dcache]
270	sc_signal<data_t> ** r_dcache_ll_data; //[m_nb_dcache][m_nb_cpu]
271	sc_signal<addr_40> ** r_dcache_ll_addr; //[m_nb_dcache][m_nb_cpu]
272	sc_signal<bool> ** r_dcache_ll_valid; //[m_nb_dcache][m_nb_cpu]
273	sc_signal<bool> * r_dcache_previous_unc; //[m_nb_dcache]
274
275	sc_signal<int> * r_icache_fsm; //[m_nb_icache]
276	sc_signal<int> * r_icache_fsm_save; //[m_nb_icache]
277	sc_signal<addr_40> * r_icache_addr_save; //[m_nb_icache]
278	sc_signal<bool> * r_icache_miss_req; //[m_nb_icache]
279	sc_signal<size_t> * r_icache_miss_way; //[m_nb_icache]
280	sc_signal<size_t> * r_icache_miss_set; //[m_nb_icache]
281	sc_signal<bool> * r_icache_unc_req; //[m_nb_icache]
282	sc_signal<bool> * r_icache_cleanup_req; //[m_nb_icache]
283	sc_signal<addr_40> * r_icache_cleanup_line; //[m_nb_icache]
284	sc_signal<bool> * r_icache_inval_rsp; //[m_nb_icache]
285	sc_signal<size_t> * r_icache_update_addr; //[m_nb_icache]
286	sc_signal<bool> * r_icache_buf_unc_valid;//[m_nb_icache]
287
288	sc_signal<int> r_vci_cmd_fsm;
289	sc_signal<size_t> r_vci_cmd_min;
290	sc_signal<size_t> r_vci_cmd_max;
291	sc_signal<size_t> r_vci_cmd_cpt;
292	sc_signal<bool> r_vci_cmd_dcache_prior;
293	sc_signal<uint32_t> r_vci_cmd_num_icache_prior;
294	sc_signal<uint32_t> r_vci_cmd_num_dcache_prior;
295	sc_signal<uint32_t> r_vci_cmd_num_cache;
296
297	sc_signal<int> r_vci_rsp_fsm;
298	sc_signal<size_t> r_vci_rsp_cpt;
299	sc_signal<uint32_t> r_vci_rsp_num_cache;
300	sc_signal<bool> * r_vci_rsp_ins_error; //[m_nb_icache]
301	sc_signal<bool> * r_vci_rsp_data_error; //[m_nb_dcache]
302
303	GenericFifo<data_t> r_vci_rsp_fifo_icache_data;
304	GenericFifo<uint32_t> r_vci_rsp_fifo_icache_num_cache;
305	GenericFifo<data_t> r_vci_rsp_fifo_dcache_data;
306	GenericFifo<uint32_t> r_vci_rsp_fifo_dcache_num_cache;
307
308	data_t * r_tgt_buf; //[m_cache_words]
309	be_t * r_tgt_be; //[m_cache_words]
310	sc_signal<uint32_t> r_cache_word;
311
312	sc_signal<int> r_vci_tgt_fsm;
313	sc_signal<addr_40> r_tgt_iaddr;
314	sc_signal<addr_40> r_tgt_daddr;
315	sc_signal<size_t> r_tgt_word;
316	sc_signal<bool> r_tgt_update;
317	sc_signal<bool> r_tgt_update_data;
318	//sc_signal<bool> r_tgt_brdcast;
319	sc_signal<size_t> r_tgt_srcid;
320	sc_signal<size_t> r_tgt_pktid;
321	sc_signal<size_t> r_tgt_trdid;
322	//sc_signal<size_t> r_tgt_plen;
323	sc_signal<uint32_t> r_tgt_num_cache;
324	sc_signal<bool> * r_tgt_icache_req; //[m_nb_icache]
325	sc_signal<bool> * r_tgt_icache_rsp; //[m_nb_icache]
326	sc_signal<bool> * r_tgt_dcache_req; //[m_nb_dcache]
327	sc_signal<bool> * r_tgt_dcache_rsp; //[m_nb_dcache]
328
329	sc_signal<int> r_cleanup_fsm; // controls initiator port of the coherence network
330	sc_signal<uint32_t> r_cleanup_num_cache;
331	sc_signal<bool> r_cleanup_icache;
332
333	MultiWriteBuffer<addr_40>** r_wbuf;
334	GenericCache<vci_addr_t> ** r_icache;
335	GenericCache<vci_addr_t> ** r_dcache;
336
337	#if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION
338	bool generate_log_transaction_file_icache;
339	bool generate_log_transaction_file_dcache;
340	bool generate_log_transaction_file_cmd;
341	bool generate_log_transaction_file_tgt;
342	bool generate_log_transaction_file_cleanup;
343
344	std::ofstream * log_transaction_file_icache; //[m_nb_cpu]
345	std::ofstream * log_transaction_file_dcache; //[m_nb_cpu]
346	std::ofstream log_transaction_file_cmd;
347	std::ofstream log_transaction_file_tgt;
348	std::ofstream log_transaction_file_cleanup;
349	#endif
350
351	#if MWBUF_VHDL_TESTBENCH
352	bool simulation_started;
353	bool generate_vhdl_testbench_mwbuf;
354	std::ofstream * vhdl_testbench_mwbuf; //[m_nb_dcache]
355	#endif
356
357	// Activity counters
358	uint32_t m_cpt_dcache_data_read; // * DCACHE DATA READ
359	uint32_t m_cpt_dcache_data_write; // * DCACHE DATA WRITE
360	uint32_t m_cpt_dcache_dir_read; // * DCACHE DIR READ
361	uint32_t m_cpt_dcache_dir_write; // * DCACHE DIR WRITE
362
363	uint32_t m_cpt_icache_data_read; // * ICACHE DATA READ
364	uint32_t m_cpt_icache_data_write; // * ICACHE DATA WRITE
365	uint32_t m_cpt_icache_dir_read; // * ICACHE DIR READ
366	uint32_t m_cpt_icache_dir_write; // * ICACHE DIR WRITE
367
368	uint32_t m_cpt_cc_update_icache; // number of coherence update packets (for icache)
369	uint32_t m_cpt_cc_update_dcache; // number of coherence update packets (for dcache)
370	uint32_t m_cpt_cc_inval_broadcast; // number of coherence inval packets
371	uint32_t m_cpt_cc_inval_icache; // number of coherence inval packets
372	uint32_t m_cpt_cc_inval_dcache; // number of coherence inval packets
373	uint32_t m_cpt_cc_update_icache_word_useful; // number of valid word in coherence update packets
374	uint32_t m_cpt_cc_update_dcache_word_useful; // number of valid word in coherence update packets
375
376	uint32_t * m_cpt_frz_cycles; // * number of cycles where the cpu is frozen
377	uint32_t m_cpt_total_cycles; // total number of cycles
378
379	uint32_t m_cpt_data_read; // number of data read
380	uint32_t m_cpt_data_read_miss; // number of data read miss
381	uint32_t m_cpt_data_read_uncached; // number of data read uncached
382	uint32_t m_cpt_data_write; // number of data write
383	uint32_t m_cpt_data_write_miss; // number of data write miss
384	uint32_t m_cpt_data_write_uncached; // number of data write uncached
385	uint32_t m_cpt_ins_miss; // * number of instruction miss
386
387	uint32_t m_cost_write_frz; // * number of frozen cycles related to write buffer
388	uint32_t m_cost_data_miss_frz; // * number of frozen cycles related to data miss
389	uint32_t m_cost_unc_read_frz; // * number of frozen cycles related to uncached read
390	uint32_t m_cost_ins_miss_frz; // * number of frozen cycles related to ins miss
391
392	uint32_t m_cpt_imiss_transaction; // * number of VCI instruction miss transactions
393	uint32_t m_cpt_dmiss_transaction; // * number of VCI data miss transactions
394	uint32_t m_cpt_unc_transaction; // * number of VCI uncached read transactions
395	uint32_t m_cpt_data_write_transaction; // * number of VCI write transactions
396
397	uint32_t m_cost_imiss_transaction; // * cumulated duration for VCI IMISS transactions
398	uint32_t m_cost_dmiss_transaction; // * cumulated duration for VCI DMISS transactions
399	uint32_t m_cost_unc_transaction; // * cumulated duration for VCI UNC transactions
400	uint32_t m_cost_write_transaction; // * cumulated duration for VCI WRITE transactions
401	uint32_t m_length_write_transaction; // * cumulated length for VCI WRITE transactions
402
403	uint32_t * m_cpt_icache_access; //[m_nb_icache]
404	uint32_t * m_cpt_dcache_access; //[m_nb_dcache]
405	uint32_t * m_cpt_dcache_hit_after_miss_read; //[m_nb_dcache]
406	uint32_t * m_cpt_dcache_hit_after_miss_write; //[m_nb_dcache]
407	uint32_t * m_cpt_dcache_store_after_store; //[m_nb_dcache]
408	uint32_t * m_cpt_icache_miss_victim_wait; //[m_nb_icache]
409	uint32_t * m_cpt_dcache_miss_victim_wait; //[m_nb_dcache]
410
411	uint32_t ** m_cpt_fsm_dcache; //[m_nb_dcache]
412	uint32_t ** m_cpt_fsm_icache; //[m_nb_icache]
413	uint32_t * m_cpt_fsm_cmd;
414	uint32_t * m_cpt_fsm_rsp;
415	uint32_t * m_cpt_fsm_tgt;
416	uint32_t * m_cpt_fsm_cleanup;
417
418	// Non blocking multi-cache
419	typename iss_t::InstructionRequest * ireq ; //[m_nb_icache]
420	typename iss_t::InstructionResponse * irsp ; //[m_nb_icache]
421	bool * ireq_cached ; //[m_nb_icache]
422	uint32_t * ireq_num_cpu; //[m_nb_dcache]
423	typename iss_t::DataRequest * dreq ; //[m_nb_dcache]
424	typename iss_t::DataResponse * drsp ; //[m_nb_dcache]
425	bool * dreq_cached ; //[m_nb_dcache]
426	uint32_t * dreq_num_cpu; //[m_nb_dcache]
427
428	const uint32_t m_num_cache_LSB;
429	const uint32_t m_num_cache_MSB;
430	addr_40 m_num_cache_LSB_mask;
431	addr_40 m_num_cache_mask;
432
433	protected:
434	SC_HAS_PROCESS(VciCcXCacheWrapperV4);
435
436	public:
437
438	VciCcXCacheWrapperV4(
439	sc_module_name insname,
440	int proc_id,
441	const soclib::common::MappingTable &mtp,
442	const soclib::common::MappingTable &mtc,
443	const soclib::common::IntTab &initiator_index_rw,
444	const soclib::common::IntTab &initiator_index_c,
445	const soclib::common::IntTab &target_index,
446	size_t nb_cpu,
447	size_t nb_dcache,
448	size_t icache_ways,
449	size_t icache_sets,
450	size_t icache_words,
451	size_t dcache_ways,
452	size_t dcache_sets,
453	size_t dcache_words,
454	size_t wbuf_nwords,
455	size_t wbuf_nlines
456	);
457
458	~VciCcXCacheWrapperV4();
459
460	void print_trace(size_t mode = 0);
461	void print_cpi();
462	void print_stats(bool print_wbuf=true, bool print_fsm=true);
463
464	void stop_simulation (uint32_t);
465	void log_transaction ( bool generate_file_icache
466	,bool generate_file_dcache
467	,bool generate_file_cmd
468	,bool generate_file_tgt
469	,bool generate_file_cleanup);
470
471	void vhdl_testbench (bool generate_file_mwbuf);
472
473	private:
474
475	void transition();
476	void genMoore();
477
478	uint32_t get_num_cache (addr_40 & addr);
479	uint32_t get_num_cache_only(addr_40 addr);
480	void set_num_cache (addr_40 & addr, uint32_t num_cache);
481	addr_40 set_num_cache_only(addr_40 addr, uint32_t num_cache);
482
483	soclib_static_assert((int)iss_t::SC_ATOMIC == (int)vci_param::STORE_COND_ATOMIC);
484	soclib_static_assert((int)iss_t::SC_NOT_ATOMIC == (int)vci_param::STORE_COND_NOT_ATOMIC);
485	};
486
487	}}
488
489	#endif /* SOCLIB_CABA_VCI_CC_XCACHE_WRAPPER_V4_H */
490
491	// Local Variables:
492	// tab-width: 4
493	// c-basic-offset: 4
494	// c-file-offsets:((innamespace . 0)(inline-open . 0))
495	// indent-tabs-mode: nil
496	// End:
497
498	// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4

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