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vci_cc_xcache_wrapper_v4.h @ 188

Last change on this file since 188 was 188, checked in by alain, 12 years ago
A maitainable version removing the multi-caches feature.
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1	/* -- c++ --
2	* File : vci_cc_xcache_wrapper_v4.h
3	* Copyright (c) UPMC, Lip6, SoC
4	* Authors : Alain GREINER
5	* Date : 27/11/2011
6	*
7	* SOCLIB_LGPL_HEADER_BEGIN
8	*
9	* This file is part of SoCLib, GNU LGPLv2.1.
10	*
11	* SoCLib is free software; you can redistribute it and/or modify it
12	* under the terms of the GNU Lesser General Public License as published
13	* by the Free Software Foundation; version 2.1 of the License.
14	*
15	* SoCLib is distributed in the hope that it will be useful, but
16	* WITHOUT ANY WARRANTY; without even the implied warranty of
17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18	* Lesser General Public License for more details.
19	*
20	* You should have received a copy of the GNU Lesser General Public
21	* License along with SoCLib; if not, write to the Free Software
22	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
23	* 02110-1301 USA
24	*
25	* SOCLIB_LGPL_HEADER_END
26	*/
27
28	#ifndef SOCLIB_CABA_VCI_CC_XCACHE_WRAPPER_V4_H
29	#define SOCLIB_CABA_VCI_CC_XCACHE_WRAPPER_V4_H
30
31	#include <inttypes.h>
32	#include <fstream>
33	#include <systemc>
34	#include <queue>
35	#include "caba_base_module.h"
36	#include "multi_write_buffer.h"
37	#include "generic_cache.h"
38	#include "generic_fifo.h"
39	#include "generic_cam.h"
40	#include "vci_initiator.h"
41	#include "vci_target.h"
42	#include "mapping_table.h"
43	#include "static_assert.h"
44	#include "iss2.h"
45
46	namespace soclib {
47	namespace caba {
48
49	using namespace sc_core;
50
51	////////////////////////////////////////////
52	template<typename vci_param, typename iss_t>
53	class VciCcXCacheWrapperV4
54	///////////////////////////////////////////
55	: public soclib::caba::BaseModule
56	{
57	typedef uint32_t data_t;
58	typedef uint32_t tag_t;
59	typedef uint32_t be_t;
60	typedef typename vci_param::fast_addr_t vci_addr_t;
61
62	enum dcache_fsm_state_e
63	{
64	DCACHE_IDLE,
65	DCACHE_WRITE_UPDT,
66	DCACHE_MISS_VICTIM,
67	DCACHE_MISS_WAIT,
68	DCACHE_MISS_UPDT,
69	DCACHE_UNC_WAIT,
70	DCACHE_INVAL,
71	DCACHE_INVAL_GO,
72	DCACHE_SYNC,
73	DCACHE_ERROR,
74	DCACHE_CC_CHECK,
75	DCACHE_CC_INVAL,
76	DCACHE_CC_UPDT,
77	};
78
79	enum icache_fsm_state_e
80	{
81	ICACHE_IDLE,
82	ICACHE_MISS_VICTIM,
83	ICACHE_MISS_WAIT,
84	ICACHE_MISS_UPDT,
85	ICACHE_UNC_WAIT,
86	ICACHE_ERROR,
87	ICACHE_CC_CHECK,
88	ICACHE_CC_INVAL,
89	ICACHE_CC_UPDT,
90	};
91
92	enum cmd_fsm_state_e
93	{
94	CMD_IDLE,
95	CMD_INS_MISS,
96	CMD_INS_UNC,
97	CMD_DATA_MISS,
98	CMD_DATA_UNC,
99	CMD_DATA_WRITE,
100	CMD_DATA_SC,
101	};
102
103	enum rsp_fsm_state_e
104	{
105	RSP_IDLE,
106	RSP_INS_MISS,
107	RSP_INS_UNC,
108	RSP_DATA_MISS,
109	RSP_DATA_UNC,
110	RSP_DATA_WRITE,
111	RSP_DATA_SC,
112	};
113
114	enum tgt_fsm_state_e
115	{
116	TGT_IDLE,
117	TGT_UPDT_WORD,
118	TGT_UPDT_DATA,
119	TGT_REQ_BROADCAST,
120	TGT_REQ_ICACHE,
121	TGT_REQ_DCACHE,
122	TGT_RSP_BROADCAST,
123	TGT_RSP_ICACHE,
124	TGT_RSP_DCACHE,
125	};
126
127	enum cleanup_cmd_fsm_state_e
128	{
129	CLEANUP_DATA_IDLE,
130	CLEANUP_INS_IDLE,
131	CLEANUP_DATA_GO,
132	CLEANUP_INS_GO,
133	};
134
135	enum transaction_type_d_e
136	{
137	// convention with memcache
138	// b0 : 1 if cached
139	// b1 : 1 if instruction
140	// b2 : 1 if sc
141	TYPE_DATA_UNC = 0x0,
142	TYPE_DATA_MISS = 0x1,
143	TYPE_INS_UNC = 0x2,
144	TYPE_INS_MISS = 0x3,
145	};
146
147	public:
148
149	// PORTS
150	sc_in<bool> p_clk;
151	sc_in<bool> p_resetn;
152	sc_in<bool> * p_irq; // [iss_t::n_irq];
153	soclib::caba::VciInitiator<vci_param> p_vci_ini_d;
154	soclib::caba::VciInitiator<vci_param> p_vci_ini_c;
155	soclib::caba::VciTarget<vci_param> p_vci_tgt_c;
156
157	private:
158
159	// STRUCTURAL PARAMETERS
160	const soclib::common::AddressDecodingTable<vci_addr_t, bool> m_cacheability_table;
161	const soclib::common::Segment m_segment;
162
163	const uint32_t m_srcid_d;
164	const uint32_t m_srcid_c;
165
166	const size_t m_dcache_ways;
167	const size_t m_icache_ways;
168
169	const size_t m_cache_words;
170	const size_t m_cache_words_shift;
171	const vci_addr_t m_cache_yzmask;
172
173	const uint32_t m_max_frozen_cycles;
174
175	iss_t * r_iss;
176	MultiWriteBuffer<vci_addr_t> * r_wbuf;
177	GenericCache<vci_addr_t> * r_icache;
178	GenericCache<vci_addr_t> * r_dcache;
179
180	sc_signal<int> r_icache_fsm;
181	sc_signal<int> r_icache_fsm_save; // return state for coherence request
182	sc_signal<vci_addr_t> r_icache_addr_save; // address requested by proc
183	sc_signal<bool> r_icache_miss_req; // set by icache_fsm / reset by cmd_fsm
184	sc_signal<bool> r_icache_unc_req; // set by icache_fsm / reset by cmd_fsm
185	sc_signal<bool> r_icache_cleanup_req; // a victim line must be evicted
186	sc_signal<vci_addr_t> r_icache_cleanup_line; // address of the selected victim line
187	sc_signal<size_t> r_icache_cleanup_way; // way of the selected victim line
188	sc_signal<size_t> r_icache_cleanup_set; // set of the selected victim line
189	sc_signal<bool> r_icache_miss_inval; // cancellation request for pending miss
190	sc_signal<size_t> r_icache_update_word; // word index for update (intern/extern)
191	sc_signal<data_t> r_icache_unc_buf; // Non cacheable read buffer (one word)
192	sc_signal<bool> r_icache_unc_valid; // Non cacheable read buffer valid
193	sc_signal<size_t> r_icache_cc_way; // way index for coherence request
194	sc_signal<size_t> r_icache_cc_set; // set index for coherence request
195
196	sc_signal<int> r_dcache_fsm;
197	sc_signal<int> r_dcache_fsm_save; // return state when coherence request
198	sc_signal<vci_addr_t> r_dcache_addr_save; // address requested by proc
199	sc_signal<data_t> r_dcache_wdata_save; // data written (for dcache update)
200	sc_signal<be_t> r_dcache_be_save; // byte enable (for dcache update)
201	sc_signal<be_t> r_dcache_way_save; // selected way (in case of hit)
202	sc_signal<be_t> r_dcache_set_save; // selected set (in case of hit)
203	sc_signal<be_t> r_dcache_word_save; // selected word (in case of hit)
204	sc_signal<bool> r_dcache_cleanup_req; // a victim line must be evicted
205	sc_signal<vci_addr_t> r_dcache_cleanup_line; // address of the selected victim line
206	sc_signal<size_t> r_dcache_cleanup_way; // way of the selected victim line
207	sc_signal<size_t> r_dcache_cleanup_set; // set of the selected victim line
208	sc_signal<bool> r_dcache_miss_req; // set by dcache_fsm / reset by cmd_fsm
209	sc_signal<bool> r_dcache_unc_req; // set by dcache_fsm / reset by cmd_fsm
210	sc_signal<bool> r_dcache_sc_req; // set by dcache_fsm / reset by cmd_fsm
211	sc_signal<bool> r_dcache_miss_inval; // cancellation of a pending miss
212	sc_signal<size_t> r_dcache_update_word; // word index for update (intern/extern)
213	sc_signal<data_t> r_dcache_ll_data; // LL reservation data
214	sc_signal<vci_addr_t> r_dcache_ll_addr; // ll reservation address
215	sc_signal<bool> r_dcache_ll_valid; // ll reservation valid
216	sc_signal<bool> r_dcache_pending_unc_write; // Non cacheable write pending
217	sc_signal<data_t> r_dcache_unc_buf; // Non cacheable read buffer (one word)
218	sc_signal<bool> r_dcache_unc_valid; // Non cacheable read buffer valid
219	sc_signal<size_t> r_dcache_cc_way; // way index for coherence request
220	sc_signal<size_t> r_dcache_cc_set; // set index for coherence request
221
222	sc_signal<int> r_vci_cmd_fsm;
223	sc_signal<size_t> r_vci_cmd_min; // min word index for a write burst
224	sc_signal<size_t> r_vci_cmd_max; // max word index for a write burst
225	sc_signal<size_t> r_vci_cmd_cpt;
226	sc_signal<bool> r_vci_cmd_imiss_prio; // round-robin flip-flop to access wbuf
227
228	sc_signal<int> r_vci_rsp_fsm;
229	sc_signal<size_t> r_vci_rsp_cpt;
230	sc_signal<bool> r_vci_rsp_ins_error; // set by rsp_fsm / reset by icache_fsm
231	sc_signal<bool> r_vci_rsp_data_error; // set by rsp_fsm / reset by dcache_fsm
232	GenericFifo<data_t> r_vci_rsp_fifo_icache; // response fifo to ICACHE FSM
233	GenericFifo<data_t> r_vci_rsp_fifo_dcache; // response FIFO to DCACHE FSM
234
235	sc_signal<int> r_tgt_fsm; // target port on coherence network
236	sc_signal<bool> r_tgt_icache_rsp; // VCI response required when true
237	sc_signal<bool> r_tgt_dcache_rsp; // VCI response required when true
238	sc_signal<vci_addr_t> r_tgt_addr; // address of the target line
239	sc_signal<size_t> r_tgt_word_min; // index of the first word to be updated
240	sc_signal<size_t> r_tgt_word_max; // index of the last word to be updated
241	sc_signal<size_t> r_tgt_word_count; // word counter to fill the tgt_buf
242	sc_signal<bool> r_tgt_update; // update request when true
243	sc_signal<bool> r_tgt_update_data; // update_data request when true
244	sc_signal<size_t> r_tgt_srcid;
245	sc_signal<size_t> r_tgt_pktid;
246	sc_signal<size_t> r_tgt_trdid;
247	sc_signal<bool> r_tgt_icache_req; // coherence request to ICACHE
248	sc_signal<bool> r_tgt_dcache_req; // coherence request to DCACHE
249	sc_signal<data_t> * r_tgt_buf; // [m_cache_words]
250	sc_signal<be_t> * r_tgt_be; // [m_cache_words]
251
252	sc_signal<int> r_cleanup_fsm; // send cleanup commands
253	sc_signal<size_t> r_cleanup_trdid; // index for trdid
254	GenericCam<vci_addr_t> r_cleanup_buffer; // registration buffer for cleanups
255
256	// ISS interface variables (used for communication
257	// between transition() and print_trace() functions
258	bool m_ireq_valid;
259	uint32_t m_ireq_addr;
260	soclib::common::Iss2::ExecMode m_ireq_mode;
261
262	bool m_irsp_valid;
263	uint32_t m_irsp_instruction;
264	bool m_irsp_error;
265
266	bool m_dreq_valid;
267	uint32_t m_dreq_addr;
268	soclib::common::Iss2::ExecMode m_dreq_mode;
269	soclib::common::Iss2::DataOperationType m_dreq_type;
270	uint32_t m_dreq_wdata;
271	uint8_t m_dreq_be;
272
273	bool m_drsp_valid;
274	uint32_t m_drsp_rdata;
275	bool m_drsp_error;
276
277	// Activity counters (for power consumption evaluation)
278	uint32_t m_conso_dcache_data_read; // DCACHE DATA READ activity
279	uint32_t m_conso_dcache_data_write; // DCACHE DATA WRITE activity
280	uint32_t m_conso_dcache_dir_read; // DCACHE DIR READ activity
281	uint32_t m_conso_dcache_dir_write; // DCACHE DIR WRITE activity
282
283	uint32_t m_conso_icache_data_read; // ICACHE DATA READ activity
284	uint32_t m_conso_icache_data_write; // ICACHE DATA WRITE activity
285	uint32_t m_conso_icache_dir_read; // ICACHE DIR READ activity
286	uint32_t m_conso_icache_dir_write; // ICACHE DIR WRITE activity
287
288	uint32_t m_conso_wbuf_read; // WBUF READ activity
289	uint32_t m_conso_wbuf_write; // WBUF WRITE activity
290
291	uint32_t m_cpt_cc_update_icache; // number of coherence update packets for icache
292	uint32_t m_cpt_cc_update_dcache; // number of coherence update packets for dcache
293	uint32_t m_cpt_cc_inval_icache; // number of coherence inval packets for icache
294	uint32_t m_cpt_cc_inval_dcache; // number of coherence inval packets for dcache
295	uint32_t m_cpt_cc_inval_broadcast; // number of coherence broadcast packets
296
297	uint32_t m_cpt_frz_cycles; // total number of cpu frozen cycles
298	uint32_t m_cpt_total_cycles; // total number of cycles from reset
299	uint32_t m_cpt_stop_simulation; // consecutive frozen cycles counter
300
301	uint32_t m_cpt_ins_cacheable; // number of cacheable instructions
302	uint32_t m_cpt_ins_uncacheable; // number of non cacheable instructions
303	uint32_t m_cpt_ins_miss; // number of cacheable instruction miss
304
305	uint32_t m_cpt_data_read_cacheable; // number of cacheable data read
306	uint32_t m_cpt_data_read_miss; // number of cacheable data read miss
307	uint32_t m_cpt_data_read_uncacheable; // number of non cacheable data read
308	uint32_t m_cpt_data_write_cacheable; // number of cacheable write
309	uint32_t m_cpt_data_write_uncacheable; // number of non cacheable write
310	uint32_t m_cpt_data_write_hit; // number of cacheable write making hit
311	uint32_t m_cpt_data_ll; // number of LL requests
312	uint32_t m_cpt_data_sc; // number of SC requests
313
314	uint32_t m_cpt_xtn_dcache_inval; // dcache line invalidation request
315	uint32_t m_cpt_xtn_sync; // write buffer flush request
316
317	uint32_t m_cost_write_frz; // number of frozen cycles related to write buffer
318	uint32_t m_cost_data_miss_frz; // number of frozen cycles related to data miss
319	uint32_t m_cost_ins_miss_frz; // number of frozen cycles related to ins miss
320
321	uint32_t m_cpt_imiss_transaction; // number of VCI inst read miss transactions
322	uint32_t m_cpt_dmiss_transaction; // number of VCI data read miss transactions
323	uint32_t m_cpt_iunc_transaction; // number of VCI uncacheable inst read transactions
324	uint32_t m_cpt_dunc_transaction; // number of VCI uncacheable data read transactions
325	uint32_t m_cpt_write_transaction; // number of VCI write transactions
326	uint32_t m_cpt_sc_transaction; // number of VCI sc transactions
327
328	uint32_t m_cost_imiss_transaction; // cumulated duration for VCI IMISS transactions
329	uint32_t m_cost_dmiss_transaction; // cumulated duration for VCI DMISS transactions
330	uint32_t m_cost_unc_transaction; // cumulated duration for VCI UNC transactions
331	uint32_t m_cost_write_transaction; // cumulated duration for VCI WRITE transactions
332	uint32_t m_length_write_transaction; // cumulated length for VCI WRITE transactions
333
334
335	uint32_t * m_cpt_fsm_dcache; // array of number of cycles per state
336	uint32_t * m_cpt_fsm_icache; // array of number of cycles per state
337	uint32_t * m_cpt_fsm_cmd; // array of number of cycles per state
338	uint32_t * m_cpt_fsm_rsp; // array of number of cycles per state
339	uint32_t * m_cpt_fsm_tgt; // array of number of cycles per state
340	uint32_t * m_cpt_fsm_cleanup; // array of number of cycles per state
341
342	protected:
343	SC_HAS_PROCESS(VciCcXCacheWrapperV4);
344
345	public:
346
347	VciCcXCacheWrapperV4(
348	sc_module_name insname,
349	int proc_id,
350	const soclib::common::MappingTable &mtd,
351	const soclib::common::MappingTable &mtc,
352	const soclib::common::IntTab &initiator_index_d,
353	const soclib::common::IntTab &initiator_index_c,
354	const soclib::common::IntTab &target_index_c,
355	size_t icache_ways,
356	size_t icache_sets,
357	size_t icache_words,
358	size_t dcache_ways,
359	size_t dcache_sets,
360	size_t dcache_words,
361	size_t wbuf_nwords,
362	size_t wbuf_nlines,
363	uint32_t max_frozen_cycles = 1000);
364
365	~VciCcXCacheWrapperV4();
366
367	void print_trace(size_t mode = 0);
368	void print_cpi();
369	void print_stats(bool print_wbuf=true, bool print_fsm=true);
370
371	private:
372
373	void transition();
374	void genMoore();
375
376	soclib_static_assert((int)iss_t::SC_ATOMIC == (int)vci_param::STORE_COND_ATOMIC);
377	soclib_static_assert((int)iss_t::SC_NOT_ATOMIC == (int)vci_param::STORE_COND_NOT_ATOMIC);
378	};
379
380	}}
381
382	#endif /* SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER_V4_H */
383
384	// Local Variables:
385	// tab-width: 4
386	// c-basic-offset: 4
387	// c-file-offsets:((innamespace . 0)(inline-open . 0))
388	// indent-tabs-mode: nil
389	// End:
390
391	// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4

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