source: trunk/modules/vci_cc_xcache_wrapper_v4/caba/source/include/vci_cc_xcache_wrapper_v4.h @ 2

Last change on this file since 2 was 2, checked in by nipo, 14 years ago

Import TSAR modules in TSAR's own svn
  • Property svn:eol-style set to native
  • Property svn:keywords set to "Author Date Id Rev URL Revision"
  • Property svn:mime-type set to text/plain
File size: 10.2 KB
Line 
1/* -*- c++ -*-
2 *
3 * SOCLIB_LGPL_HEADER_BEGIN
4 *
5 * This file is part of SoCLib, GNU LGPLv2.1.
6 *
7 * SoCLib is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU Lesser General Public License as published
9 * by the Free Software Foundation; version 2.1 of the License.
10 *
11 * SoCLib is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with SoCLib; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
19 * 02110-1301 USA
20 *
21 * SOCLIB_LGPL_HEADER_END
22 *
23 * Copyright (c) UPMC, Lip6, SoC
24 *         Alain Greiner <alain.greiner@lip6.fr>, 2008
25 *
26 * Maintainers: alain
27 */
28 
29#ifndef SOCLIB_CABA_VCI_CC_XCACHE_WRAPPER_V4_H
30#define SOCLIB_CABA_VCI_CC_XCACHE_WRAPPER_V4_H
31
32#include <inttypes.h>
33#include <systemc>
34#include "caba_base_module.h"
35#include "write_buffer.h"
36#include "generic_cache.h"
37#include "vci_initiator.h"
38#include "vci_target.h"
39#include "mapping_table.h"
40#include "static_assert.h"
41
42
43namespace soclib {
44namespace caba {
45
46using namespace sc_core;
47
48////////////////////////////////////////////
49template<typename vci_param, typename iss_t>
50class VciCcXCacheWrapperV4
51///////////////////////////////////////////
52    : public soclib::caba::BaseModule
53{
54    typedef sc_dt::sc_uint<40> addr_40;
55    typedef uint32_t    data_t;
56    typedef uint32_t    tag_t;
57    typedef uint32_t    be_t;
58    typedef typename vci_param::fast_addr_t vci_addr_t;
59    enum dcache_fsm_state_e {
60        DCACHE_IDLE,
61        DCACHE_WRITE_UPDT,
62        DCACHE_WRITE_REQ,
63        DCACHE_MISS_WAIT,
64        DCACHE_MISS_UPDT,
65        DCACHE_UNC_WAIT,
66        DCACHE_SC_WAIT,
67        DCACHE_INVAL,
68        DCACHE_ERROR,
69        DCACHE_CC_CHECK,
70        DCACHE_CC_INVAL,
71        DCACHE_CC_UPDT,
72        DCACHE_CC_CLEANUP,
73    };
74
75    enum icache_fsm_state_e {
76        ICACHE_IDLE,
77        ICACHE_MISS_WAIT,
78        ICACHE_MISS_UPDT,
79        ICACHE_UNC_WAIT,
80        ICACHE_ERROR,
81        ICACHE_CC_CLEANUP,
82        ICACHE_CC_CHECK,
83        ICACHE_CC_INVAL,
84        ICACHE_CC_UPDT,
85    };
86
87    enum cmd_fsm_state_e {
88        CMD_IDLE,
89        CMD_INS_MISS,
90        CMD_INS_UNC,
91        CMD_DATA_MISS,
92        CMD_DATA_UNC,
93        CMD_DATA_WRITE,
94        CMD_DATA_SC,
95        CMD_INS_CLEANUP,
96        CMD_DATA_CLEANUP,
97    };
98
99    enum rsp_fsm_state_e {
100        RSP_IDLE,
101        RSP_INS_MISS,
102        RSP_INS_UNC,
103        RSP_DATA_MISS,
104        RSP_DATA_UNC,
105        RSP_DATA_WRITE,
106        RSP_DATA_SC,
107        RSP_INS_CLEANUP,
108        RSP_DATA_CLEANUP,
109    };
110
111    enum tgt_fsm_state_e {
112        TGT_IDLE,
113        TGT_UPDT_WORD,
114        TGT_UPDT_DATA,
115        TGT_REQ_BROADCAST,
116        TGT_REQ_ICACHE,
117        TGT_REQ_DCACHE,
118        TGT_RSP_BROADCAST,
119        TGT_RSP_ICACHE,
120        TGT_RSP_DCACHE,
121    };
122
123public:
124
125    // PORTS
126    sc_in<bool>                             p_clk;
127    sc_in<bool>                             p_resetn;
128    sc_in<bool>                             p_irq[iss_t::n_irq];
129    soclib::caba::VciInitiator<vci_param>   p_vci_ini_rw;
130    soclib::caba::VciInitiator<vci_param>   p_vci_ini_c;
131    soclib::caba::VciTarget<vci_param>      p_vci_tgt;
132
133private:
134
135    // STRUCTURAL PARAMETERS
136    const soclib::common::AddressDecodingTable<vci_addr_t, bool>    m_cacheability_table;
137    const soclib::common::Segment                                   m_segment;
138    iss_t               m_iss;
139    const uint32_t      m_srcid_rw;   
140    const uint32_t      m_srcid_c;   
141   
142    const size_t        m_dcache_ways;
143    const size_t        m_dcache_words;
144    const size_t        m_dcache_yzmask;
145    const size_t        m_icache_ways;
146    const size_t        m_icache_words;
147    const size_t        m_icache_yzmask;
148
149    // REGISTERS
150    sc_signal<int>          r_dcache_fsm;
151    sc_signal<int>          r_dcache_fsm_save;
152    sc_signal<addr_40>      r_dcache_addr_save;
153    sc_signal<data_t>       r_dcache_wdata_save;
154    sc_signal<data_t>       r_dcache_rdata_save;
155    sc_signal<uint64_t>     r_dcache_ll_data;
156    sc_signal<addr_40>      r_dcache_ll_addr;
157    sc_signal<bool>         r_dcache_ll_valid;
158    sc_signal<int>          r_dcache_type_save;
159    sc_signal<be_t>         r_dcache_be_save;
160    sc_signal<bool>         r_dcache_cached_save;
161    sc_signal<bool>         r_dcache_cleanup_req;
162    sc_signal<addr_40>      r_dcache_cleanup_line;
163    sc_signal<bool>         r_dcache_miss_req;
164    sc_signal<bool>         r_dcache_unc_req;
165    sc_signal<bool>         r_dcache_sc_req;
166    sc_signal<bool>         r_dcache_write_req;
167    sc_signal<bool>         r_dcache_inval_rsp;
168
169    sc_signal<int>          r_icache_fsm;
170    sc_signal<int>          r_icache_fsm_save;
171    sc_signal<addr_40>      r_icache_addr_save;
172    sc_signal<bool>         r_icache_miss_req;
173    sc_signal<bool>         r_icache_unc_req;
174    sc_signal<bool>         r_icache_cleanup_req;
175    sc_signal<addr_40>      r_icache_cleanup_line;
176    sc_signal<bool>         r_icache_inval_rsp;
177
178    sc_signal<int>          r_vci_cmd_fsm;
179    sc_signal<size_t>       r_vci_cmd_min;       
180    sc_signal<size_t>       r_vci_cmd_max;       
181    sc_signal<size_t>       r_vci_cmd_cpt;       
182     
183    sc_signal<int>          r_vci_rsp_fsm;
184    sc_signal<bool>         r_vci_rsp_ins_error;   
185    sc_signal<bool>         r_vci_rsp_data_error;   
186    sc_signal<size_t>       r_vci_rsp_cpt; 
187
188    data_t                  *r_icache_miss_buf;   
189    data_t                  *r_dcache_miss_buf;   
190    sc_signal<bool>         r_icache_buf_unc_valid;
191
192    data_t                  *r_tgt_buf;
193    be_t                    *r_tgt_be;
194
195    sc_signal<int>          r_vci_tgt_fsm;
196    sc_signal<addr_40>       r_tgt_addr;
197    sc_signal<size_t>       r_tgt_word;
198    sc_signal<bool>         r_tgt_update;
199    sc_signal<bool>         r_tgt_update_data;
200    sc_signal<bool>         r_tgt_brdcast;
201    sc_signal<size_t>       r_tgt_srcid;
202    sc_signal<size_t>       r_tgt_pktid;
203    sc_signal<size_t>       r_tgt_trdid;
204    sc_signal<size_t>       r_tgt_plen;
205    sc_signal<bool>         r_tgt_icache_req;
206    sc_signal<bool>         r_tgt_dcache_req;
207    sc_signal<bool>         r_tgt_icache_rsp;
208    sc_signal<bool>         r_tgt_dcache_rsp;
209
210    WriteBuffer<addr_40>        r_wbuf;
211    GenericCache<vci_addr_t>    r_icache;
212    GenericCache<vci_addr_t>    r_dcache;
213
214    // Activity counters
215    uint32_t m_cpt_dcache_data_read;        // DCACHE DATA READ
216    uint32_t m_cpt_dcache_data_write;       // DCACHE DATA WRITE
217    uint32_t m_cpt_dcache_dir_read;         // DCACHE DIR READ
218    uint32_t m_cpt_dcache_dir_write;        // DCACHE DIR WRITE
219
220    uint32_t m_cpt_icache_data_read;        // ICACHE DATA READ
221    uint32_t m_cpt_icache_data_write;       // ICACHE DATA WRITE
222    uint32_t m_cpt_icache_dir_read;         // ICACHE DIR READ
223    uint32_t m_cpt_icache_dir_write;        // ICACHE DIR WRITE
224
225    uint32_t m_cpt_cc_update;               // number of coherence update packets
226    uint32_t m_cpt_cc_inval;                // number of coherence inval packets
227
228    uint32_t m_cpt_frz_cycles;              // number of cycles where the cpu is frozen
229    uint32_t m_cpt_total_cycles;                // total number of cycles
230
231    uint32_t m_cpt_read;                    // total number of read instructions
232    uint32_t m_cpt_write;                   // total number of write instructions
233    uint32_t m_cpt_data_miss;               // number of read miss
234    uint32_t m_cpt_ins_miss;                // number of instruction miss
235    uint32_t m_cpt_unc_read;                // number of read uncached
236    uint32_t m_cpt_write_cached;            // number of cached write
237
238    uint32_t m_cost_write_frz;              // number of frozen cycles related to write buffer         
239    uint32_t m_cost_data_miss_frz;          // number of frozen cycles related to data miss
240    uint32_t m_cost_unc_read_frz;           // number of frozen cycles related to uncached read
241    uint32_t m_cost_ins_miss_frz;           // number of frozen cycles related to ins miss
242
243    uint32_t m_cpt_imiss_transaction;       // number of VCI instruction miss transactions
244    uint32_t m_cpt_dmiss_transaction;       // number of VCI data miss transactions
245    uint32_t m_cpt_unc_transaction;         // number of VCI uncached read transactions
246    uint32_t m_cpt_write_transaction;       // number of VCI write transactions
247
248    uint32_t m_cost_imiss_transaction;      // cumulated duration for VCI IMISS transactions
249    uint32_t m_cost_dmiss_transaction;      // cumulated duration for VCI DMISS transactions
250    uint32_t m_cost_unc_transaction;        // cumulated duration for VCI UNC transactions
251    uint32_t m_cost_write_transaction;      // cumulated duration for VCI WRITE transactions
252    uint32_t m_length_write_transaction;    // cumulated length for VCI WRITE transactions
253
254protected:
255    SC_HAS_PROCESS(VciCcXCacheWrapperV4);
256
257public:
258
259    VciCcXCacheWrapperV4(
260                       sc_module_name insname,
261                       int proc_id,
262                       const soclib::common::MappingTable &mtp,
263                       const soclib::common::MappingTable &mtc,
264                       const soclib::common::IntTab &initiator_index_rw,
265                       const soclib::common::IntTab &initiator_index_c,
266                       const soclib::common::IntTab &target_index,
267                       size_t icache_ways,
268                       size_t icache_sets,
269                       size_t icache_words,
270                       size_t dcache_ways,
271                       size_t dcache_sets,
272                       size_t dcache_words );
273
274    ~VciCcXCacheWrapperV4();
275
276    void print_cpi();
277    void print_stats();
278
279private:
280
281    void transition();
282    void genMoore();
283
284    soclib_static_assert((int)iss_t::SC_ATOMIC == (int)vci_param::STORE_COND_ATOMIC);
285    soclib_static_assert((int)iss_t::SC_NOT_ATOMIC == (int)vci_param::STORE_COND_NOT_ATOMIC);
286};
287
288}}
289
290#endif /* SOCLIB_CABA_VCI_CC_XCACHE_WRAPPER_V4_H */
291
292// Local Variables:
293// tab-width: 4
294// c-basic-offset: 4
295// c-file-offsets:((innamespace . 0)(inline-open . 0))
296// indent-tabs-mode: nil
297// End:
298
299// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
300
301
302
Note: See TracBrowser for help on using the repository browser.