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vci_mem_cache.h @ 2

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1	/* -- c++ --
2	* File : vci_mem_cache.h
3	* Date : 26/10/2008
4	* Copyright : UPMC / LIP6
5	* Authors : Alain Greiner / Eric Guthmuller
6	*
7	* SOCLIB_LGPL_HEADER_BEGIN
8	*
9	* This file is part of SoCLib, GNU LGPLv2.1.
10	*
11	* SoCLib is free software; you can redistribute it and/or modify it
12	* under the terms of the GNU Lesser General Public License as published
13	* by the Free Software Foundation; version 2.1 of the License.
14	*
15	* SoCLib is distributed in the hope that it will be useful, but
16	* WITHOUT ANY WARRANTY; without even the implied warranty of
17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18	* Lesser General Public License for more details.
19	*
20	* You should have received a copy of the GNU Lesser General Public
21	* License along with SoCLib; if not, write to the Free Software
22	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
23	* 02110-1301 USA
24	*
25	* SOCLIB_LGPL_HEADER_END
26	*
27	* Maintainers: alain eric.guthmuller@polytechnique.edu
28	*/
29
30	#ifndef SOCLIB_CABA_MEM_CACHE_H
31	#define SOCLIB_CABA_MEM_CACHE_H
32
33	#include <inttypes.h>
34	#include <systemc>
35	#include <list>
36	#include <cassert>
37	#include "arithmetics.h"
38	#include "alloc_elems.h"
39	#include "caba_base_module.h"
40	#include "vci_target.h"
41	#include "vci_initiator.h"
42	#include "generic_fifo.h"
43	#include "mapping_table.h"
44	#include "int_tab.h"
45	#include "mem_cache_directory.h"
46	#include "xram_transaction.h"
47	#include "update_tab.h"
48	#include "atomic_tab.h"
49
50	#define TRANSACTION_TAB_LINES 4 // Number of lines in the transaction tab
51	#define UPDATE_TAB_LINES 4 // Number of lines in the update tab
52
53	namespace soclib { namespace caba {
54	using namespace sc_core;
55
56	template<typename vci_param>
57	class VciMemCache
58	: public soclib::caba::BaseModule
59	{
60	typedef uint32_t addr_t;
61	typedef uint32_t data_t;
62	typedef uint32_t tag_t;
63	typedef uint32_t size_t;
64	typedef uint32_t be_t;
65	typedef uint32_t copy_t;
66
67	/* States of the TGT_CMD fsm */
68	enum tgt_cmd_fsm_state_e{
69	TGT_CMD_IDLE,
70	TGT_CMD_READ,
71	TGT_CMD_READ_EOP,
72	TGT_CMD_WRITE,
73	TGT_CMD_ATOMIC,
74	TGT_CMD_CLEANUP,
75	};
76
77	/* States of the TGT_RSP fsm */
78	enum tgt_rsp_fsm_state_e{
79	TGT_RSP_READ_IDLE,
80	TGT_RSP_WRITE_IDLE,
81	TGT_RSP_LLSC_IDLE,
82	TGT_RSP_CLEANUP_IDLE,
83	TGT_RSP_XRAM_IDLE,
84	TGT_RSP_INIT_IDLE,
85	TGT_RSP_READ_TEST,
86	TGT_RSP_READ_WORD,
87	TGT_RSP_READ_LINE,
88	TGT_RSP_WRITE,
89	TGT_RSP_LLSC,
90	TGT_RSP_CLEANUP,
91	TGT_RSP_XRAM_TEST,
92	TGT_RSP_XRAM_WORD,
93	TGT_RSP_XRAM_LINE,
94	TGT_RSP_INIT,
95	};
96
97	/* States of the INIT_CMD fsm */
98	enum init_cmd_fsm_state_e{
99	INIT_CMD_INVAL_IDLE,
100	INIT_CMD_INVAL_SEL,
101	INIT_CMD_INVAL_NLINE,
102	INIT_CMD_UPDT_IDLE,
103	INIT_CMD_UPDT_SEL,
104	INIT_CMD_UPDT_NLINE,
105	INIT_CMD_UPDT_INDEX,
106	INIT_CMD_UPDT_DATA,
107	};
108
109	/* States of the INIT_RSP fsm */
110	enum init_rsp_fsm_state_e{
111	INIT_RSP_IDLE,
112	INIT_RSP_UPT_LOCK,
113	INIT_RSP_UPT_CLEAR,
114	INIT_RSP_END,
115	};
116
117	/* States of the READ fsm */
118	enum read_fsm_state_e{
119	READ_IDLE,
120	READ_DIR_LOCK,
121	READ_DIR_HIT,
122	READ_RSP,
123	READ_TRT_LOCK,
124	READ_TRT_SET,
125	READ_XRAM_REQ,
126	};
127
128	/* States of the WRITE fsm */
129	enum write_fsm_state_e{
130	WRITE_IDLE,
131	WRITE_NEXT,
132	WRITE_DIR_LOCK,
133	WRITE_DIR_HIT_READ,
134	WRITE_DIR_HIT,
135	WRITE_UPT_LOCK,
136	WRITE_WAIT_UPT,
137	WRITE_UPDATE,
138	WRITE_RSP,
139	WRITE_TRT_LOCK,
140	WRITE_TRT_DATA,
141	WRITE_TRT_SET,
142	WRITE_WAIT_TRT,
143	WRITE_XRAM_REQ,
144	};
145
146	/* States of the IXR_RSP fsm */
147	enum ixr_rsp_fsm_state_e{
148	IXR_RSP_IDLE,
149	IXR_RSP_ACK,
150	IXR_RSP_TRT_ERASE,
151	IXR_RSP_TRT_READ,
152	};
153
154	/* States of the XRAM_RSP fsm */
155	enum xram_rsp_fsm_state_e{
156	XRAM_RSP_IDLE,
157	XRAM_RSP_TRT_COPY,
158	XRAM_RSP_TRT_DIRTY,
159	XRAM_RSP_DIR_LOCK,
160	XRAM_RSP_DIR_UPDT,
161	XRAM_RSP_DIR_RSP,
162	XRAM_RSP_UPT_LOCK,
163	XRAM_RSP_WAIT,
164	XRAM_RSP_INVAL,
165	XRAM_RSP_WRITE_DIRTY,
166	};
167
168	/* States of the XRAM_CMD fsm */
169	enum xram_cmd_fsm_state_e{
170	XRAM_CMD_READ_IDLE,
171	XRAM_CMD_WRITE_IDLE,
172	XRAM_CMD_LLSC_IDLE,
173	XRAM_CMD_XRAM_IDLE,
174	XRAM_CMD_READ_NLINE,
175	XRAM_CMD_WRITE_NLINE,
176	XRAM_CMD_LLSC_NLINE,
177	XRAM_CMD_XRAM_DATA,
178	};
179
180	/* States of the LLSC fsm */
181	enum llsc_fsm_state_e{
182	LLSC_IDLE,
183	LL_DIR_LOCK,
184	LL_DIR_HIT,
185	LL_RSP,
186	SC_DIR_LOCK,
187	SC_DIR_HIT,
188	SC_RSP_FALSE,
189	SC_RSP_TRUE,
190	LLSC_TRT_LOCK,
191	LLSC_TRT_SET,
192	LLSC_XRAM_REQ,
193	};
194
195	/* States of the CLEANUP fsm */
196	enum cleanup_fsm_state_e{
197	CLEANUP_IDLE,
198	CLEANUP_DIR_LOCK,
199	CLEANUP_DIR_WRITE,
200	CLEANUP_RSP,
201	};
202
203	/* States of the ALLOC_DIR fsm */
204	enum alloc_dir_fsm_state_e{
205	ALLOC_DIR_READ,
206	ALLOC_DIR_WRITE,
207	ALLOC_DIR_LLSC,
208	ALLOC_DIR_CLEANUP,
209	ALLOC_DIR_XRAM_RSP,
210	};
211
212	/* States of the ALLOC_TRT fsm */
213	enum alloc_trt_fsm_state_e{
214	ALLOC_TRT_READ,
215	ALLOC_TRT_WRITE,
216	ALLOC_TRT_LLSC,
217	ALLOC_TRT_XRAM_RSP,
218	ALLOC_TRT_IXR_RSP,
219	};
220
221	/* States of the ALLOC_UPT fsm */
222	enum alloc_upt_fsm_state_e{
223	ALLOC_UPT_WRITE,
224	ALLOC_UPT_XRAM_RSP,
225	ALLOC_UPT_INIT_RSP,
226	};
227
228	uint32_t m_cpt_cycles; // Counter of cycles
229	uint32_t m_cpt_read; // Number of READ transactions
230	uint32_t m_cpt_read_miss; // Number of MISS READ
231	uint32_t m_cpt_write; // Number of WRITE transactions
232	uint32_t m_cpt_write_miss; // Number of MISS WRITE
233	uint32_t m_cpt_write_cells; // Cumulated length for WRITE transactions
234	uint32_t m_cpt_write_dirty; // Cumulated length for WRITE transactions
235	uint32_t m_cpt_update; // Number of UPDATE transactions
236	uint32_t m_cpt_update_mult; // Number of targets for UPDATE
237	uint32_t m_cpt_inval; // Number of INVAL transactions
238	uint32_t m_cpt_inval_mult; // Number of targets for INVAL
239	uint32_t m_cpt_cleanup; // Number of CLEANUP transactions
240	uint32_t m_cpt_ll; // Number of LL transactions
241	uint32_t m_cpt_sc; // Number of SC transactions
242
243	protected:
244
245	SC_HAS_PROCESS(VciMemCache);
246
247	public:
248	sc_in<bool> p_clk;
249	sc_in<bool> p_resetn;
250	soclib::caba::VciTarget<vci_param> p_vci_tgt;
251	soclib::caba::VciInitiator<vci_param> p_vci_ini;
252	soclib::caba::VciInitiator<vci_param> p_vci_ixr;
253
254	VciMemCache(
255	sc_module_name name, // Instance Name
256	const soclib::common::MappingTable &mtp, // Mapping table for primary requets
257	const soclib::common::MappingTable &mtc, // Mapping table for coherence requets
258	const soclib::common::MappingTable &mtx, // Mapping table for XRAM
259	const soclib::common::IntTab &vci_ixr_index, // VCI port to XRAM (initiator)
260	const soclib::common::IntTab &vci_ini_index, // VCI port to PROC (initiator)
261	const soclib::common::IntTab &vci_tgt_index, // VCI port to PROC (target)
262	size_t nways, // Number of ways per set
263	size_t nsets, // Number of sets
264	size_t nwords); // Number of words per line
265
266	~VciMemCache();
267
268	void transition();
269
270	void genMoore();
271
272	void print_stats();
273
274	private:
275
276	// Component attributes
277	const size_t m_initiators; // Number of initiators
278	const size_t m_ways; // Number of ways in a set
279	const size_t m_sets; // Number of cache sets
280	const size_t m_words; // Number of words in a line
281	const size_t m_srcid_ixr; // Srcid for requests to XRAM
282	const size_t m_srcid_ini; // Srcid for requests to processors
283	//soclib::common::Segment m_mem_segment; // memory cached into the cache
284	std::list<soclib::common::Segment> m_seglist; // memory cached into the cache
285	soclib::common::Segment m_reg_segment; // memory cache mapped registers
286	addr_t *m_coherence_table; // address(srcid)
287	AtomicTab m_atomic_tab; // atomic access table
288	TransactionTab m_transaction_tab; // xram transaction table
289	UpdateTab m_update_tab; // pending update & invalidate
290	CacheDirectory m_cache_directory; // data cache directory
291
292	data_t ***m_cache_data; // data array[set][way][word]
293
294	// adress masks
295	const soclib::common::AddressMaskingTable<addr_t> m_x;
296	const soclib::common::AddressMaskingTable<addr_t> m_y;
297	const soclib::common::AddressMaskingTable<addr_t> m_z;
298	const soclib::common::AddressMaskingTable<addr_t> m_nline;
299
300	//////////////////////////////////////////////////
301	// Registers controlled by the TGT_CMD fsm
302	//////////////////////////////////////////////////
303
304	// Fifo between TGT_CMD fsm and READ fsm
305	GenericFifo<addr_t> m_cmd_read_addr_fifo;
306	GenericFifo<bool> m_cmd_read_word_fifo;
307	GenericFifo<size_t> m_cmd_read_srcid_fifo;
308	GenericFifo<size_t> m_cmd_read_trdid_fifo;
309	GenericFifo<size_t> m_cmd_read_pktid_fifo;
310
311	// Fifo between TGT_CMD fsm and WRITE fsm
312	GenericFifo<addr_t> m_cmd_write_addr_fifo;
313	GenericFifo<bool> m_cmd_write_eop_fifo;
314	GenericFifo<size_t> m_cmd_write_srcid_fifo;
315	GenericFifo<size_t> m_cmd_write_trdid_fifo;
316	GenericFifo<size_t> m_cmd_write_pktid_fifo;
317	GenericFifo<data_t> m_cmd_write_data_fifo;
318	GenericFifo<be_t> m_cmd_write_be_fifo;
319
320	// Fifo between TGT_CMD fsm and LLSC fsm
321	GenericFifo<addr_t> m_cmd_llsc_addr_fifo;
322	GenericFifo<bool> m_cmd_llsc_sc_fifo;
323	GenericFifo<size_t> m_cmd_llsc_srcid_fifo;
324	GenericFifo<size_t> m_cmd_llsc_trdid_fifo;
325	GenericFifo<size_t> m_cmd_llsc_pktid_fifo;
326	GenericFifo<data_t> m_cmd_llsc_wdata_fifo;
327
328	// Fifo between TGT_CMD fsm and CLEANUP fsm
329	GenericFifo<size_t> m_cmd_cleanup_srcid_fifo;
330	GenericFifo<size_t> m_cmd_cleanup_trdid_fifo;
331	GenericFifo<size_t> m_cmd_cleanup_pktid_fifo;
332	GenericFifo<data_t> m_cmd_cleanup_nline_fifo;
333
334	sc_signal<int> r_tgt_cmd_fsm;
335
336	sc_signal<size_t> r_index;
337	size_t nseg;
338	soclib::common::Segment **m_seg;
339	///////////////////////////////////////////////////////
340	// Registers controlled by the READ fsm
341	///////////////////////////////////////////////////////
342
343	sc_signal<int> r_read_fsm; // FSM state
344	sc_signal<copy_t> r_read_copies; // bit-vector of copies
345	sc_signal<tag_t> r_read_tag; // cache line tag (in directory)
346	sc_signal<bool> r_read_lock; // lock bit (in directory)
347	sc_signal<bool> r_read_dirty; // dirty bit (in directory)
348	sc_signal<data_t> *r_read_data; // data (one cache line)
349	sc_signal<bool> r_read_word; // single word read
350	sc_signal<size_t> r_read_way; // associative way (in cache)
351	sc_signal<size_t> r_read_trt_index; // Transaction Table index
352
353	// Buffer between READ fsm and XRAM_CMD fsm (ask a missing cache line to XRAM)
354	sc_signal<bool> r_read_to_xram_cmd_req; // valid request
355	sc_signal<data_t> r_read_to_xram_cmd_nline; // cache line index
356	sc_signal<size_t> r_read_to_xram_cmd_trdid; // index in Transaction Table
357
358	// Buffer between READ fsm and TGT_RSP fsm (send a hit read response to L1 cache)
359	sc_signal<bool> r_read_to_tgt_rsp_req; // valid request
360	sc_signal<size_t> r_read_to_tgt_rsp_srcid; // Transaction srcid
361	sc_signal<size_t> r_read_to_tgt_rsp_trdid; // Transaction trdid
362	sc_signal<size_t> r_read_to_tgt_rsp_pktid; // Transaction pktid
363	sc_signal<data_t> *r_read_to_tgt_rsp_data; // data (one cache line)
364	sc_signal<bool> *r_read_to_tgt_rsp_val; // valid bit (for single_word)
365
366	///////////////////////////////////////////////////////////////
367	// Registers controlled by the WRITE fsm
368	///////////////////////////////////////////////////////////////
369
370	sc_signal<int> r_write_fsm; // FSM state
371	sc_signal<addr_t> r_write_address; // first word address
372	sc_signal<size_t> r_write_word_index; // first word index in line
373	sc_signal<size_t> r_write_word_count; // number of words in line
374	sc_signal<size_t> r_write_srcid; // transaction srcid
375	sc_signal<size_t> r_write_trdid; // transaction trdid
376	sc_signal<size_t> r_write_pktid; // transaction pktid
377	sc_signal<data_t> *r_write_data; // data (one cache line)
378	sc_signal<be_t> *r_write_be; // one byte enable per word
379	sc_signal<bool> r_write_byte; // is it a byte write
380	sc_signal<bool> r_write_lock; // lock bit (in directory)
381	sc_signal<tag_t> r_write_tag; // cache line tag (in directory)
382	sc_signal<copy_t> r_write_copies; // bit vector of copies
383	sc_signal<size_t> r_write_nb_copies; // number of copies
384	sc_signal<size_t> r_write_way; // way of the line
385	sc_signal<size_t> r_write_trt_index; // index in Transaction Table
386	sc_signal<size_t> r_write_upt_index; // index in Update Table
387
388	// Buffer between WRITE fsm and TGT_RSP fsm (acknowledge a write command from L1)
389	sc_signal<bool> r_write_to_tgt_rsp_req; // valid request
390	sc_signal<size_t> r_write_to_tgt_rsp_srcid; // transaction srcid
391	sc_signal<size_t> r_write_to_tgt_rsp_trdid; // transaction trdid
392	sc_signal<size_t> r_write_to_tgt_rsp_pktid; // transaction pktid
393
394	// Buffer between WRITE fsm and XRAM_CMD fsm (ask a missing cache line to XRAM)
395	sc_signal<bool> r_write_to_xram_cmd_req; // valid request
396	sc_signal<data_t> r_write_to_xram_cmd_nline; // cache line index
397	sc_signal<size_t> r_write_to_xram_cmd_trdid; // index in Transaction Table
398
399	// Buffer between WRITE fsm and INIT_CMD fsm (Update L1 caches)
400	sc_signal<bool> r_write_to_init_cmd_req; // valid request
401	sc_signal<data_t> r_write_to_init_cmd_nline; // cache line index
402	sc_signal<size_t> r_write_to_init_cmd_trdid; // index in Update Table
403	sc_signal<copy_t> r_write_to_init_cmd_copies; // bit_vector of L1 to update
404	sc_signal<data_t> *r_write_to_init_cmd_data; // data (one cache line)
405	sc_signal<bool> *r_write_to_init_cmd_we; // word enable
406	sc_signal<size_t> r_write_to_init_cmd_count; // number of words in line
407	sc_signal<size_t> r_write_to_init_cmd_index; // index of first word in line
408
409	/////////////////////////////////////////////////////////
410	// Registers controlled by INIT_RSP fsm
411	//////////////////////////////////////////////////////////
412
413	sc_signal<int> r_init_rsp_fsm; // FSM state
414	sc_signal<size_t> r_init_rsp_upt_index; // index in the Update Table
415	sc_signal<size_t> r_init_rsp_srcid; // pending write srcid
416	sc_signal<size_t> r_init_rsp_trdid; // pending write trdid
417	sc_signal<size_t> r_init_rsp_pktid; // pending write pktid
418
419	// Buffer between INIT_RSP fsm and TGT_RSP fsm (complete write/update transaction)
420	sc_signal<bool> r_init_rsp_to_tgt_rsp_req; // valid request
421	sc_signal<size_t> r_init_rsp_to_tgt_rsp_srcid; // Transaction srcid
422	sc_signal<size_t> r_init_rsp_to_tgt_rsp_trdid; // Transaction trdid
423	sc_signal<size_t> r_init_rsp_to_tgt_rsp_pktid; // Transaction pktid
424
425	///////////////////////////////////////////////////////
426	// Registers controlled by CLEANUP fsm
427	///////////////////////////////////////////////////////
428
429	sc_signal<int> r_cleanup_fsm; // FSM state
430	sc_signal<size_t> r_cleanup_srcid; // transaction srcid
431	sc_signal<size_t> r_cleanup_trdid; // transaction trdid
432	sc_signal<size_t> r_cleanup_pktid; // transaction pktid
433	sc_signal<data_t> r_cleanup_nline; // cache line index
434
435	sc_signal<copy_t> r_cleanup_copies; // bit-vector of copies
436	sc_signal<tag_t> r_cleanup_tag; // cache line tag (in directory)
437	sc_signal<bool> r_cleanup_lock; // lock bit (in directory)
438	sc_signal<bool> r_cleanup_dirty; // dirty bit (in directory)
439	sc_signal<size_t> r_cleanup_way; // associative way (in cache)
440
441	// Buffer between CLEANUP fsm and TGT_RSP fsm (acknowledge a cleanup command from L1)
442	sc_signal<bool> r_cleanup_to_tgt_rsp_req; // valid request
443	sc_signal<size_t> r_cleanup_to_tgt_rsp_srcid; // transaction srcid
444	sc_signal<size_t> r_cleanup_to_tgt_rsp_trdid; // transaction trdid
445	sc_signal<size_t> r_cleanup_to_tgt_rsp_pktid; // transaction pktid
446
447	///////////////////////////////////////////////////////
448	// Registers controlled by LLSC fsm
449	///////////////////////////////////////////////////////
450
451	sc_signal<int> r_llsc_fsm; // FSM state
452	sc_signal<data_t> r_llsc_data; // read data word
453	sc_signal<copy_t> r_llsc_copies; // bit_vector of copies
454	sc_signal<bool> r_llsc_dirty; // dirty bit (in directory)
455	sc_signal<size_t> r_llsc_way; // way in directory
456	sc_signal<size_t> r_llsc_set; // set in directory
457	sc_signal<data_t> r_llsc_tag; // cache line tag (in directory)
458	sc_signal<size_t> r_llsc_trt_index; // Transaction Table index
459
460	// Buffer between LLSC fsm and INIT_CMD fsm (XRAM read)
461	sc_signal<bool> r_llsc_to_xram_cmd_req; // valid request
462	sc_signal<data_t> r_llsc_to_xram_cmd_nline; // cache line index
463	sc_signal<size_t> r_llsc_to_xram_cmd_trdid; // index in Transaction Table
464
465	// Buffer between LLSC fsm and TGT_RSP fsm
466	sc_signal<bool> r_llsc_to_tgt_rsp_req; // valid request
467	sc_signal<data_t> r_llsc_to_tgt_rsp_data; // read data word
468	sc_signal<size_t> r_llsc_to_tgt_rsp_srcid; // Transaction srcid
469	sc_signal<size_t> r_llsc_to_tgt_rsp_trdid; // Transaction trdid
470	sc_signal<size_t> r_llsc_to_tgt_rsp_pktid; // Transaction pktid
471
472	////////////////////////////////////////////////////
473	// Registers controlled by the IXR_RSP fsm
474	////////////////////////////////////////////////////
475
476	sc_signal<int> r_ixr_rsp_fsm; // FSM state
477	sc_signal<size_t> r_ixr_rsp_trt_index; // TRT entry index
478	sc_signal<size_t> r_ixr_rsp_cpt; // word counter
479
480	// Buffer between IXR_RSP fsm and XRAM_RSP fsm (response from the XRAM)
481	sc_signal<bool> *r_ixr_rsp_to_xram_rsp_rok; // A xram response is ready
482
483	////////////////////////////////////////////////////
484	// Registers controlled by the XRAM_RSP fsm
485	////////////////////////////////////////////////////
486
487	sc_signal<int> r_xram_rsp_fsm; // FSM state
488	sc_signal<size_t> r_xram_rsp_trt_index; // TRT entry index
489	TransactionTabEntry r_xram_rsp_trt_buf; // TRT entry local buffer
490	sc_signal<bool> r_xram_rsp_victim_inval; // victim line invalidate
491	sc_signal<bool> r_xram_rsp_victim_dirty; // victim line dirty bit
492	sc_signal<size_t> r_xram_rsp_victim_way; // victim line way
493	sc_signal<size_t> r_xram_rsp_victim_set; // victim line set
494	sc_signal<data_t> r_xram_rsp_victim_nline; // victim line index
495	sc_signal<copy_t> r_xram_rsp_victim_copies; // victim line copies
496	sc_signal<data_t> *r_xram_rsp_victim_data; // victim line data
497	sc_signal<size_t> r_xram_rsp_upt_index; // UPT entry index
498
499	// Buffer between XRAM_RSP fsm and TGT_RSP fsm (response to L1 cache)
500	sc_signal<bool> r_xram_rsp_to_tgt_rsp_req; // Valid request
501	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_srcid; // Transaction srcid
502	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_trdid; // Transaction trdid
503	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_pktid; // Transaction pktid
504	sc_signal<data_t> *r_xram_rsp_to_tgt_rsp_data; // data (one cache line)
505	sc_signal<bool> *r_xram_rsp_to_tgt_rsp_val; // valid bit (for single word)
506
507	// Buffer between XRAM_RSP fsm and INIT_CMD fsm (Inval L1 Caches)
508	sc_signal<bool> r_xram_rsp_to_init_cmd_req; // Valid request
509	sc_signal<data_t> r_xram_rsp_to_init_cmd_nline; // cache line index;
510	sc_signal<size_t> r_xram_rsp_to_init_cmd_trdid; // index of UPT entry
511	sc_signal<copy_t> r_xram_rsp_to_init_cmd_copies; // bit_vector of copies
512
513	// Buffer between XRAM_RSP fsm and XRAM_CMD fsm (XRAM write)
514	sc_signal<bool> r_xram_rsp_to_xram_cmd_req; // Valid request
515	sc_signal<data_t> r_xram_rsp_to_xram_cmd_nline; // cache line index
516	sc_signal<data_t> *r_xram_rsp_to_xram_cmd_data; // cache line data
517	sc_signal<size_t> r_xram_rsp_to_xram_cmd_trdid; // index in transaction table
518
519	////////////////////////////////////////////////////
520	// Registers controlled by the XRAM_CMD fsm
521	////////////////////////////////////////////////////
522
523	sc_signal<int> r_xram_cmd_fsm;
524	sc_signal<size_t> r_xram_cmd_cpt;
525
526	////////////////////////////////////////////////////
527	// Registers controlled by TGT_RSP fsm
528	////////////////////////////////////////////////////
529
530	sc_signal<int> r_tgt_rsp_fsm;
531	sc_signal<size_t> r_tgt_rsp_cpt;
532
533	////////////////////////////////////////////////////
534	// Registers controlled by INIT_CMD fsm
535	////////////////////////////////////////////////////
536
537	sc_signal<int> r_init_cmd_fsm;
538	sc_signal<size_t> r_init_cmd_cpt;
539	sc_signal<size_t> r_init_cmd_target;
540
541	////////////////////////////////////////////////////
542	// Registers controlled by ALLOC_DIR fsm
543	////////////////////////////////////////////////////
544
545	sc_signal<int> r_alloc_dir_fsm;
546
547	////////////////////////////////////////////////////
548	// Registers controlled by ALLOC_TRT fsm
549	////////////////////////////////////////////////////
550
551	sc_signal<int> r_alloc_trt_fsm;
552
553	////////////////////////////////////////////////////
554	// Registers controlled by ALLOC_UPT fsm
555	////////////////////////////////////////////////////
556
557	sc_signal<int> r_alloc_upt_fsm;
558
559	}; // end class VciMemCache
560
561	}}
562
563	#endif

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