source: trunk/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h @ 385

Last change on this file since 385 was 385, checked in by alain, 11 years ago

VCI port to XRAM switched to DATA == 64 bits
=> two template parameters vci_param_int & vci_param_ext
This has been validated in tsar_generic_xbar platform...

File size: 35.8 KB
Line 
1/* -*- c++ -*-
2 * File         : vci_mem_cache.h
3 * Date         : 26/10/2008
4 * Copyright    : UPMC / LIP6
5 * Authors      : Alain Greiner / Eric Guthmuller
6 *
7 * SOCLIB_LGPL_HEADER_BEGIN
8 *
9 * This file is part of SoCLib, GNU LGPLv2.1.
10 *
11 * SoCLib is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU Lesser General Public License as published
13 * by the Free Software Foundation; version 2.1 of the License.
14 *
15 * SoCLib is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
18 * Lesser General Public License for more details.
19 *
20 * You should have received a copy of the GNU Lesser General Public
21 * License along with SoCLib; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
23 * 02110-1301 USA
24 *
25 * SOCLIB_LGPL_HEADER_END
26 *
27 * Maintainers: alain eric.guthmuller@polytechnique.edu
28 *              cesar.fuguet-tortolero@lip6.fr
29 *              alexandre.joannou@lip6.fr
30 */
31
32#ifndef SOCLIB_CABA_MEM_CACHE_H
33#define SOCLIB_CABA_MEM_CACHE_H
34
35#include <inttypes.h>
36#include <systemc>
37#include <list>
38#include <cassert>
39#include "arithmetics.h"
40#include "alloc_elems.h"
41#include "caba_base_module.h"
42#include "vci_target.h"
43#include "vci_initiator.h"
44#include "generic_fifo.h"
45#include "mapping_table.h"
46#include "int_tab.h"
47#include "generic_llsc_global_table.h"
48#include "mem_cache_directory.h"
49#include "xram_transaction.h"
50#include "update_tab.h"
51#include "dspin_interface.h"
52#include "dspin_dhccp_param.h"
53
54#define TRANSACTION_TAB_LINES 4 // Number of lines in the transaction tab
55#define UPDATE_TAB_LINES      4 // Number of lines in the update tab
56
57namespace soclib {  namespace caba {
58  using namespace sc_core;
59
60  template<typename vci_param_int, 
61           typename vci_param_ext,
62           size_t   dspin_in_width,
63           size_t   dspin_out_width>
64    class VciMemCache
65    : public soclib::caba::BaseModule
66    {
67      typedef typename vci_param_int::fast_addr_t  addr_t;
68
69      typedef typename sc_dt::sc_uint<64>          wide_data_t;
70
71      typedef uint32_t data_t;
72      typedef uint32_t tag_t;
73      typedef uint32_t be_t;
74      typedef uint32_t copy_t;
75
76      /* States of the TGT_CMD fsm */
77      enum tgt_cmd_fsm_state_e{
78        TGT_CMD_IDLE,
79        TGT_CMD_READ,
80        TGT_CMD_WRITE,
81        TGT_CMD_CAS
82      };
83
84      /* States of the TGT_RSP fsm */
85      enum tgt_rsp_fsm_state_e{
86        TGT_RSP_READ_IDLE,
87        TGT_RSP_WRITE_IDLE,
88        TGT_RSP_CAS_IDLE,
89        TGT_RSP_XRAM_IDLE,
90        TGT_RSP_INIT_IDLE,
91        TGT_RSP_CLEANUP_IDLE,
92        TGT_RSP_READ,
93        TGT_RSP_WRITE,
94        TGT_RSP_CAS,
95        TGT_RSP_XRAM,
96        TGT_RSP_INIT,
97        TGT_RSP_CLEANUP
98      };
99
100      /* States of the DSPIN_TGT fsm */
101      enum cc_receive_fsm_state_e{
102        CC_RECEIVE_IDLE,
103        CC_RECEIVE_CLEANUP,
104        CC_RECEIVE_MULTI_ACK
105      };
106
107      /* States of the CC_SEND fsm */
108      enum cc_send_fsm_state_e{
109        CC_SEND_XRAM_RSP_IDLE,
110        CC_SEND_WRITE_IDLE,
111        CC_SEND_CAS_IDLE,
112        CC_SEND_CLEANUP_IDLE,
113        CC_SEND_CLEANUP_ACK,
114        CC_SEND_XRAM_RSP_BRDCAST_HEADER,
115        CC_SEND_XRAM_RSP_BRDCAST_NLINE,
116        CC_SEND_XRAM_RSP_INVAL_HEADER,
117        CC_SEND_XRAM_RSP_INVAL_NLINE,
118        CC_SEND_WRITE_BRDCAST_HEADER,
119        CC_SEND_WRITE_BRDCAST_NLINE,
120        CC_SEND_WRITE_UPDT_HEADER,
121        CC_SEND_WRITE_UPDT_NLINE,
122        CC_SEND_WRITE_UPDT_DATA,
123        CC_SEND_CAS_BRDCAST_HEADER,
124        CC_SEND_CAS_BRDCAST_NLINE,
125        CC_SEND_CAS_UPDT_HEADER,
126        CC_SEND_CAS_UPDT_NLINE,
127        CC_SEND_CAS_UPDT_DATA,
128        CC_SEND_CAS_UPDT_DATA_HIGH
129      };
130
131      /* States of the MULTI_ACK fsm */
132      enum multi_ack_fsm_state_e{
133        MULTI_ACK_IDLE,
134        MULTI_ACK_UPT_LOCK,
135        MULTI_ACK_UPT_CLEAR,
136        MULTI_ACK_WRITE_RSP
137      };
138
139      /* States of the READ fsm */
140      enum read_fsm_state_e{
141        READ_IDLE,
142        READ_DIR_REQ,
143        READ_DIR_LOCK,
144        READ_DIR_HIT,
145        READ_HEAP_REQ,
146        READ_HEAP_LOCK,
147        READ_HEAP_WRITE,
148        READ_HEAP_ERASE,
149        READ_HEAP_LAST,
150        READ_RSP,
151        READ_TRT_LOCK,
152        READ_TRT_SET,
153        READ_TRT_REQ
154      };
155
156      /* States of the WRITE fsm */
157      enum write_fsm_state_e{
158        WRITE_IDLE,
159        WRITE_NEXT,
160        WRITE_DIR_REQ,
161        WRITE_DIR_LOCK,
162        WRITE_DIR_READ,
163        WRITE_DIR_HIT,
164        WRITE_UPT_LOCK,
165        WRITE_UPT_HEAP_LOCK,
166        WRITE_UPT_REQ,
167        WRITE_UPT_NEXT,
168        WRITE_UPT_DEC,
169        WRITE_RSP,
170        WRITE_MISS_TRT_LOCK,
171        WRITE_MISS_TRT_DATA,
172        WRITE_MISS_TRT_SET,
173        WRITE_MISS_XRAM_REQ,
174        WRITE_BC_TRT_LOCK,
175        WRITE_BC_UPT_LOCK,
176        WRITE_BC_DIR_INVAL,
177        WRITE_BC_CC_SEND,
178        WRITE_BC_XRAM_REQ,
179        WRITE_WAIT
180      };
181
182      /* States of the IXR_RSP fsm */
183      enum ixr_rsp_fsm_state_e{
184        IXR_RSP_IDLE,
185        IXR_RSP_ACK,
186        IXR_RSP_TRT_ERASE,
187        IXR_RSP_TRT_READ
188      };
189
190      /* States of the XRAM_RSP fsm */
191      enum xram_rsp_fsm_state_e{
192        XRAM_RSP_IDLE,
193        XRAM_RSP_TRT_COPY,
194        XRAM_RSP_TRT_DIRTY,
195        XRAM_RSP_DIR_LOCK,
196        XRAM_RSP_DIR_UPDT,
197        XRAM_RSP_DIR_RSP,
198        XRAM_RSP_INVAL_LOCK,
199        XRAM_RSP_INVAL_WAIT,
200        XRAM_RSP_INVAL,
201        XRAM_RSP_WRITE_DIRTY,
202        XRAM_RSP_HEAP_REQ,
203        XRAM_RSP_HEAP_ERASE,
204        XRAM_RSP_HEAP_LAST,
205        XRAM_RSP_ERROR_ERASE,
206        XRAM_RSP_ERROR_RSP
207      };
208
209      /* States of the IXR_CMD fsm */
210      enum ixr_cmd_fsm_state_e{
211        IXR_CMD_READ_IDLE,
212        IXR_CMD_WRITE_IDLE,
213        IXR_CMD_CAS_IDLE,
214        IXR_CMD_XRAM_IDLE,
215        IXR_CMD_READ_NLINE,
216        IXR_CMD_WRITE_NLINE,
217        IXR_CMD_CAS_NLINE,
218        IXR_CMD_XRAM_DATA
219      };
220
221      /* States of the CAS fsm */
222      enum cas_fsm_state_e{
223        CAS_IDLE,
224        CAS_DIR_REQ,
225        CAS_DIR_LOCK,
226        CAS_DIR_HIT_READ,
227        CAS_DIR_HIT_COMPARE,
228        CAS_DIR_HIT_WRITE,
229        CAS_UPT_LOCK,
230        CAS_UPT_HEAP_LOCK,
231        CAS_UPT_REQ,
232        CAS_UPT_NEXT,
233        CAS_BC_TRT_LOCK,
234        CAS_BC_UPT_LOCK,
235        CAS_BC_DIR_INVAL,
236        CAS_BC_CC_SEND,
237        CAS_BC_XRAM_REQ,
238        CAS_RSP_FAIL,
239        CAS_RSP_SUCCESS,
240        CAS_MISS_TRT_LOCK,
241        CAS_MISS_TRT_SET,
242        CAS_MISS_XRAM_REQ,
243        CAS_WAIT
244      };
245
246      /* States of the CLEANUP fsm */
247      enum cleanup_fsm_state_e{
248        CLEANUP_IDLE,
249        CLEANUP_GET_NLINE,
250        CLEANUP_DIR_REQ,
251        CLEANUP_DIR_LOCK,
252        CLEANUP_DIR_WRITE,
253        CLEANUP_HEAP_REQ,
254        CLEANUP_HEAP_LOCK,
255        CLEANUP_HEAP_SEARCH,
256        CLEANUP_HEAP_CLEAN,
257        CLEANUP_HEAP_FREE,
258        CLEANUP_UPT_LOCK,
259        CLEANUP_UPT_DECREMENT,
260        CLEANUP_UPT_CLEAR,
261        CLEANUP_WRITE_RSP,
262        CLEANUP_SEND_ACK
263      };
264
265      /* States of the ALLOC_DIR fsm */
266      enum alloc_dir_fsm_state_e{
267        ALLOC_DIR_RESET,
268        ALLOC_DIR_READ,
269        ALLOC_DIR_WRITE,
270        ALLOC_DIR_CAS,
271        ALLOC_DIR_CLEANUP,
272        ALLOC_DIR_XRAM_RSP
273      };
274
275      /* States of the ALLOC_TRT fsm */
276      enum alloc_trt_fsm_state_e{
277        ALLOC_TRT_READ,
278        ALLOC_TRT_WRITE,
279        ALLOC_TRT_CAS,
280        ALLOC_TRT_XRAM_RSP,
281        ALLOC_TRT_IXR_RSP
282      };
283
284      /* States of the ALLOC_UPT fsm */
285      enum alloc_upt_fsm_state_e{
286        ALLOC_UPT_WRITE,
287        ALLOC_UPT_XRAM_RSP,
288        ALLOC_UPT_MULTI_ACK,
289        ALLOC_UPT_CLEANUP,
290        ALLOC_UPT_CAS
291      };
292
293      /* States of the ALLOC_HEAP fsm */
294      enum alloc_heap_fsm_state_e{
295        ALLOC_HEAP_RESET,
296        ALLOC_HEAP_READ,
297        ALLOC_HEAP_WRITE,
298        ALLOC_HEAP_CAS,
299        ALLOC_HEAP_CLEANUP,
300        ALLOC_HEAP_XRAM_RSP
301      };
302
303      /* transaction type, pktid field */
304      enum transaction_type_e
305      {
306          // b3 unused
307          // b2 READ / NOT READ
308          // Si READ
309          //  b1 DATA / INS
310          //  b0 UNC / MISS
311          // Si NOT READ
312          //  b1 accÚs table llsc type SW / other
313          //  b2 WRITE/CAS/LL/SC
314          TYPE_READ_DATA_UNC          = 0x0,
315          TYPE_READ_DATA_MISS         = 0x1,
316          TYPE_READ_INS_UNC           = 0x2,
317          TYPE_READ_INS_MISS          = 0x3,
318          TYPE_WRITE                  = 0x4,
319          TYPE_CAS                    = 0x5,
320          TYPE_LL                     = 0x6,
321          TYPE_SC                     = 0x7
322      };
323
324      /* SC return values */
325      enum sc_status_type_e
326      {
327          SC_SUCCESS  =   0x00000000,
328          SC_FAIL     =   0x00000001
329      };
330
331      // debug variables (for each FSM)
332      bool         m_debug_global;
333      bool         m_debug_tgt_cmd_fsm;
334      bool         m_debug_tgt_rsp_fsm;
335      bool         m_debug_cc_send_fsm;
336      bool         m_debug_cc_receive_fsm;
337      bool         m_debug_multi_ack_fsm;
338      bool         m_debug_read_fsm;
339      bool         m_debug_write_fsm;
340      bool         m_debug_cas_fsm;
341      bool         m_debug_cleanup_fsm;
342      bool         m_debug_ixr_cmd_fsm;
343      bool         m_debug_ixr_rsp_fsm;
344      bool         m_debug_xram_rsp_fsm;
345      bool         m_debug_previous_hit;
346      size_t       m_debug_previous_count;
347
348      bool         m_monitor_ok;
349      addr_t       m_monitor_base;
350      addr_t       m_monitor_length;
351
352      // instrumentation counters
353      uint32_t     m_cpt_cycles;        // Counter of cycles
354      uint32_t     m_cpt_read;          // Number of READ transactions
355      uint32_t     m_cpt_read_miss;     // Number of MISS READ
356      uint32_t     m_cpt_write;         // Number of WRITE transactions
357      uint32_t     m_cpt_write_miss;    // Number of MISS WRITE
358      uint32_t     m_cpt_write_cells;   // Cumulated length for WRITE transactions
359      uint32_t     m_cpt_write_dirty;   // Cumulated length for WRITE transactions
360      uint32_t     m_cpt_update;        // Number of UPDATE transactions
361      uint32_t     m_cpt_trt_rb;        // Read blocked by a hit in trt
362      uint32_t     m_cpt_trt_full;      // Transaction blocked due to a full trt
363      uint32_t     m_cpt_update_mult;   // Number of targets for UPDATE
364      uint32_t     m_cpt_inval;         // Number of INVAL  transactions
365      uint32_t     m_cpt_inval_mult;    // Number of targets for INVAL
366      uint32_t     m_cpt_inval_brdcast; // Number of BROADCAST INVAL
367      uint32_t     m_cpt_cleanup;       // Number of CLEANUP transactions
368      uint32_t     m_cpt_ll;            // Number of LL transactions
369      uint32_t     m_cpt_sc;            // Number of SC transactions
370      uint32_t     m_cpt_cas;           // Number of CAS transactions
371
372      size_t       m_prev_count;
373
374      protected:
375
376      SC_HAS_PROCESS(VciMemCache);
377
378      public:
379      sc_in<bool>                                 p_clk;
380      sc_in<bool>                                 p_resetn;
381      soclib::caba::VciTarget<vci_param_int>      p_vci_tgt;
382      soclib::caba::VciInitiator<vci_param_ext>   p_vci_ixr;
383      soclib::caba::DspinInput<dspin_in_width>    p_dspin_in;
384      soclib::caba::DspinOutput<dspin_out_width>  p_dspin_out;
385
386      VciMemCache(
387          sc_module_name name,                                // Instance Name
388          const soclib::common::MappingTable &mtp,            // Mapping table for direct network
389          const soclib::common::MappingTable &mtx,            // Mapping table for external network
390          const soclib::common::IntTab       &srcid_x,        // global index on external network
391          const soclib::common::IntTab       &tgtid_d,        // global index on direct network
392          const size_t                       cc_global_id,    // global index on cc network
393          const size_t                       nways,           // Number of ways per set
394          const size_t                       nsets,           // Number of sets
395          const size_t                       nwords,          // Number of words per line
396          const size_t                       max_copies,      // max number of copies in heap
397          const size_t                       heap_size=1024,  // number of heap entries
398          const size_t                       trt_lines=TRANSACTION_TAB_LINES, 
399          const size_t                       upt_lines=UPDATE_TAB_LINES,       
400          const size_t                       debug_start_cycle=0,
401          const bool                         debug_ok=false );
402
403      ~VciMemCache();
404
405      void print_stats();
406      void print_trace();
407      void copies_monitor(addr_t addr);
408      void start_monitor(addr_t addr, addr_t length);
409      void stop_monitor();
410
411      private:
412
413      void transition();
414      void genMoore();
415      void check_monitor( const char *buf, addr_t addr, data_t data, bool read);
416
417      // Component attributes
418      std::list<soclib::common::Segment> m_seglist;          // segments allocated to memcache
419      size_t                             m_nseg;             // number of segments
420      soclib::common::Segment            **m_seg;            // array of segments pointers
421      const size_t                       m_srcid_x;          // global index on external network
422      const size_t                       m_initiators;       // Number of initiators
423      const size_t                       m_heap_size;        // Size of the heap
424      const size_t                       m_ways;             // Number of ways in a set
425      const size_t                       m_sets;             // Number of cache sets
426      const size_t                       m_words;            // Number of words in a line
427      const size_t                       m_cc_global_id;     // global_index on cc network
428      size_t                             m_debug_start_cycle;
429      bool                               m_debug_ok;
430      uint32_t                           m_trt_lines;
431      TransactionTab                     m_trt;              // xram transaction table
432      uint32_t                           m_upt_lines;
433      UpdateTab                          m_upt;              // pending update & invalidate
434      CacheDirectory                     m_cache_directory;  // data cache directory
435      CacheData                          m_cache_data;       // data array[set][way][word]
436      HeapDirectory                      m_heap;             // heap for copies
437      size_t                             m_max_copies;       // max number of copies in heap
438      GenericLLSCGlobalTable
439      < 32  ,                              // number of slots
440        4096,                              // number of processors in the system
441        8000,                              // registration life (# of LL operations)
442        addr_t >  m_llsc_table;            // ll/sc global registration table
443
444      // adress masks
445      const soclib::common::AddressMaskingTable<addr_t>   m_x;
446      const soclib::common::AddressMaskingTable<addr_t>   m_y;
447      const soclib::common::AddressMaskingTable<addr_t>   m_z;
448      const soclib::common::AddressMaskingTable<addr_t>   m_nline;
449
450      // broadcast address
451      uint32_t                                                m_broadcast_address;
452
453      //////////////////////////////////////////////////
454      // Registers controlled by the TGT_CMD fsm
455      //////////////////////////////////////////////////
456
457      // Fifo between TGT_CMD fsm and READ fsm
458      GenericFifo<addr_t>    m_cmd_read_addr_fifo;
459      GenericFifo<size_t>    m_cmd_read_length_fifo;
460      GenericFifo<size_t>    m_cmd_read_srcid_fifo;
461      GenericFifo<size_t>    m_cmd_read_trdid_fifo;
462      GenericFifo<size_t>    m_cmd_read_pktid_fifo;
463
464      // Fifo between TGT_CMD fsm and WRITE fsm
465      GenericFifo<addr_t>    m_cmd_write_addr_fifo;
466      GenericFifo<bool>      m_cmd_write_eop_fifo;
467      GenericFifo<size_t>    m_cmd_write_srcid_fifo;
468      GenericFifo<size_t>    m_cmd_write_trdid_fifo;
469      GenericFifo<size_t>    m_cmd_write_pktid_fifo;
470      GenericFifo<data_t>    m_cmd_write_data_fifo;
471      GenericFifo<be_t>      m_cmd_write_be_fifo;
472
473      // Fifo between TGT_CMD fsm and CAS fsm
474      GenericFifo<addr_t>    m_cmd_cas_addr_fifo;
475      GenericFifo<bool>      m_cmd_cas_eop_fifo;
476      GenericFifo<size_t>    m_cmd_cas_srcid_fifo;
477      GenericFifo<size_t>    m_cmd_cas_trdid_fifo;
478      GenericFifo<size_t>    m_cmd_cas_pktid_fifo;
479      GenericFifo<data_t>    m_cmd_cas_wdata_fifo;
480
481      // Fifo between INIT_RSP fsm and CLEANUP fsm
482      GenericFifo<uint64_t>  m_cc_receive_to_cleanup_fifo;
483     
484      // Fifo between INIT_RSP fsm and MULTI_ACK fsm
485      GenericFifo<uint64_t>  m_cc_receive_to_multi_ack_fifo;
486
487      sc_signal<int>         r_tgt_cmd_fsm;
488
489      ///////////////////////////////////////////////////////
490      // Registers controlled by the READ fsm
491      ///////////////////////////////////////////////////////
492
493      sc_signal<int>      r_read_fsm;        // FSM state
494      sc_signal<size_t>   r_read_copy;       // Srcid of the first copy
495      sc_signal<size_t>   r_read_copy_cache; // Srcid of the first copy
496      sc_signal<bool>     r_read_copy_inst;  // Type of the first copy
497      sc_signal<tag_t>    r_read_tag;        // cache line tag (in directory)
498      sc_signal<bool>     r_read_is_cnt;     // is_cnt bit (in directory)
499      sc_signal<bool>     r_read_lock;       // lock bit (in directory)
500      sc_signal<bool>     r_read_dirty;      // dirty bit (in directory)
501      sc_signal<size_t>   r_read_count;      // number of copies
502      sc_signal<size_t>   r_read_ptr;        // pointer to the heap
503      sc_signal<data_t> * r_read_data;       // data (one cache line)
504      sc_signal<size_t>   r_read_way;        // associative way (in cache)
505      sc_signal<size_t>   r_read_trt_index;  // Transaction Table index
506      sc_signal<size_t>   r_read_next_ptr;   // Next entry to point to
507      sc_signal<bool>     r_read_last_free;  // Last free entry
508      sc_signal<addr_t>   r_read_ll_key;     // LL key from the llsc_global_table
509
510      // Buffer between READ fsm and IXR_CMD fsm (ask a missing cache line to XRAM)
511      sc_signal<bool>     r_read_to_ixr_cmd_req;    // valid request
512      sc_signal<addr_t>   r_read_to_ixr_cmd_nline;  // cache line index
513      sc_signal<size_t>   r_read_to_ixr_cmd_trdid;  // index in Transaction Table
514
515      // Buffer between READ fsm and TGT_RSP fsm (send a hit read response to L1 cache)
516      sc_signal<bool>     r_read_to_tgt_rsp_req;    // valid request
517      sc_signal<size_t>   r_read_to_tgt_rsp_srcid;  // Transaction srcid
518      sc_signal<size_t>   r_read_to_tgt_rsp_trdid;  // Transaction trdid
519      sc_signal<size_t>   r_read_to_tgt_rsp_pktid;  // Transaction pktid
520      sc_signal<data_t> * r_read_to_tgt_rsp_data;   // data (one cache line)
521      sc_signal<size_t>   r_read_to_tgt_rsp_word;   // first word of the response
522      sc_signal<size_t>   r_read_to_tgt_rsp_length; // length of the response
523      sc_signal<addr_t>   r_read_to_tgt_rsp_ll_key; // LL key from the llsc_global_table
524
525      ///////////////////////////////////////////////////////////////
526      // Registers controlled by the WRITE fsm
527      ///////////////////////////////////////////////////////////////
528
529      sc_signal<int>      r_write_fsm;        // FSM state
530      sc_signal<addr_t>   r_write_address;    // first word address
531      sc_signal<size_t>   r_write_word_index; // first word index in line
532      sc_signal<size_t>   r_write_word_count; // number of words in line
533      sc_signal<size_t>   r_write_srcid;      // transaction srcid
534      sc_signal<size_t>   r_write_trdid;      // transaction trdid
535      sc_signal<size_t>   r_write_pktid;      // transaction pktid
536      sc_signal<data_t> * r_write_data;       // data (one cache line)
537      sc_signal<be_t>   * r_write_be;         // one byte enable per word
538      sc_signal<bool>     r_write_byte;       // (BE != 0X0) and (BE != 0xF)
539      sc_signal<bool>     r_write_is_cnt;     // is_cnt bit (in directory)
540      sc_signal<bool>     r_write_lock;       // lock bit (in directory)
541      sc_signal<tag_t>    r_write_tag;        // cache line tag (in directory)
542      sc_signal<size_t>   r_write_copy;       // first owner of the line
543      sc_signal<size_t>   r_write_copy_cache; // first owner of the line
544      sc_signal<bool>     r_write_copy_inst;  // is this owner a ICache ?
545      sc_signal<size_t>   r_write_count;      // number of copies
546      sc_signal<size_t>   r_write_ptr;        // pointer to the heap
547      sc_signal<size_t>   r_write_next_ptr;   // next pointer to the heap
548      sc_signal<bool>     r_write_to_dec;     // need to decrement update counter
549      sc_signal<size_t>   r_write_way;        // way of the line
550      sc_signal<size_t>   r_write_trt_index;  // index in Transaction Table
551      sc_signal<size_t>   r_write_upt_index;  // index in Update Table
552      sc_signal<bool>     r_write_sc_fail;    // sc command failed
553      sc_signal<bool>     r_write_pending_sc; // sc command pending
554
555      // Buffer between WRITE fsm and TGT_RSP fsm (acknowledge a write command from L1)
556      sc_signal<bool>     r_write_to_tgt_rsp_req;     // valid request
557      sc_signal<size_t>   r_write_to_tgt_rsp_srcid;   // transaction srcid
558      sc_signal<size_t>   r_write_to_tgt_rsp_trdid;   // transaction trdid
559      sc_signal<size_t>   r_write_to_tgt_rsp_pktid;   // transaction pktid
560      sc_signal<bool>     r_write_to_tgt_rsp_sc_fail; // sc command failed
561
562      // Buffer between WRITE fsm and IXR_CMD fsm (ask a missing cache line to XRAM)
563      sc_signal<bool>     r_write_to_ixr_cmd_req;   // valid request
564      sc_signal<bool>     r_write_to_ixr_cmd_write; // write request
565      sc_signal<addr_t>   r_write_to_ixr_cmd_nline; // cache line index
566      sc_signal<data_t> * r_write_to_ixr_cmd_data;  // cache line data
567      sc_signal<size_t>   r_write_to_ixr_cmd_trdid; // index in Transaction Table
568
569      // Buffer between WRITE fsm and CC_SEND fsm (Update/Invalidate L1 caches)
570      sc_signal<bool>     r_write_to_cc_send_multi_req;     // valid multicast request
571      sc_signal<bool>     r_write_to_cc_send_brdcast_req;   // valid brdcast request
572      sc_signal<addr_t>   r_write_to_cc_send_nline;         // cache line index
573      sc_signal<size_t>   r_write_to_cc_send_trdid;         // index in Update Table
574      sc_signal<data_t> * r_write_to_cc_send_data;          // data (one cache line)
575      sc_signal<be_t>   * r_write_to_cc_send_be;            // word enable
576      sc_signal<size_t>   r_write_to_cc_send_count;         // number of words in line
577      sc_signal<size_t>   r_write_to_cc_send_index;         // index of first word in line
578      GenericFifo<bool>   m_write_to_cc_send_inst_fifo;     // fifo for the L1 type
579      GenericFifo<size_t> m_write_to_cc_send_srcid_fifo;    // fifo for srcids
580
581#if L1_MULTI_CACHE
582      GenericFifo<size_t> m_write_to_cc_send_cache_id_fifo; // fifo for srcids
583#endif
584
585      // Buffer between WRITE fsm and MULTI_ACK fsm (Decrement UPT entry)
586      sc_signal<bool>     r_write_to_multi_ack_req;       // valid request
587      sc_signal<size_t>   r_write_to_multi_ack_upt_index; // index in update table
588
589      /////////////////////////////////////////////////////////
590      // Registers controlled by MULTI_ACK fsm
591      //////////////////////////////////////////////////////////
592
593      sc_signal<int>      r_multi_ack_fsm;       // FSM state
594      sc_signal<size_t>   r_multi_ack_upt_index; // index in the Update Table
595      sc_signal<size_t>   r_multi_ack_srcid;     // pending write srcid
596      sc_signal<size_t>   r_multi_ack_trdid;     // pending write trdid
597      sc_signal<size_t>   r_multi_ack_pktid;     // pending write pktid
598      sc_signal<addr_t>   r_multi_ack_nline;     // pending write nline
599
600      // Buffer between MULTI_ACK fsm and TGT_RSP fsm (complete write/update transaction)
601      sc_signal<bool>     r_multi_ack_to_tgt_rsp_req;   // valid request
602      sc_signal<size_t>   r_multi_ack_to_tgt_rsp_srcid; // Transaction srcid
603      sc_signal<size_t>   r_multi_ack_to_tgt_rsp_trdid; // Transaction trdid
604      sc_signal<size_t>   r_multi_ack_to_tgt_rsp_pktid; // Transaction pktid
605
606      ///////////////////////////////////////////////////////
607      // Registers controlled by CLEANUP fsm
608      ///////////////////////////////////////////////////////
609
610      sc_signal<int>      r_cleanup_fsm;           // FSM state
611      sc_signal<size_t>   r_cleanup_srcid;         // transaction srcid
612      sc_signal<bool>     r_cleanup_inst;          // Instruction or Data ?
613      sc_signal<size_t>   r_cleanup_way_index;     // L1 Cache Way index
614      sc_signal<addr_t>   r_cleanup_nline;         // cache line index
615
616#if L1_MULTI_CACHE
617      sc_signal<size_t>   r_cleanup_pktid;         // transaction pktid
618#endif
619
620      sc_signal<copy_t>   r_cleanup_copy;          // first copy
621      sc_signal<copy_t>   r_cleanup_copy_cache;    // first copy
622      sc_signal<size_t>   r_cleanup_copy_inst;     // type of the first copy
623      sc_signal<copy_t>   r_cleanup_count;         // number of copies
624      sc_signal<size_t>   r_cleanup_ptr;           // pointer to the heap
625      sc_signal<size_t>   r_cleanup_prev_ptr;      // previous pointer to the heap
626      sc_signal<size_t>   r_cleanup_prev_srcid;    // srcid of previous heap entry
627      sc_signal<size_t>   r_cleanup_prev_cache_id; // srcid of previous heap entry
628      sc_signal<bool>     r_cleanup_prev_inst;     // inst bit of previous heap entry
629      sc_signal<size_t>   r_cleanup_next_ptr;      // next pointer to the heap
630      sc_signal<tag_t>    r_cleanup_tag;           // cache line tag (in directory)
631      sc_signal<bool>     r_cleanup_is_cnt;        // inst bit (in directory)
632      sc_signal<bool>     r_cleanup_lock;          // lock bit (in directory)
633      sc_signal<bool>     r_cleanup_dirty;         // dirty bit (in directory)
634      sc_signal<size_t>   r_cleanup_way;           // associative way (in cache)
635
636      sc_signal<size_t>   r_cleanup_write_srcid;   // srcid of write response
637      sc_signal<size_t>   r_cleanup_write_trdid;   // trdid of write rsp
638      sc_signal<size_t>   r_cleanup_write_pktid;   // pktid of write rsp
639      sc_signal<bool>     r_cleanup_write_need_rsp;// needs a write rsp
640
641      sc_signal<size_t>   r_cleanup_index;         // index of the INVAL line (in the UPT)
642
643      // Buffer between CLEANUP fsm and TGT_RSP fsm (acknowledge a write command from L1)
644      sc_signal<bool>     r_cleanup_to_tgt_rsp_req;   // valid request
645      sc_signal<size_t>   r_cleanup_to_tgt_rsp_srcid; // transaction srcid
646      sc_signal<size_t>   r_cleanup_to_tgt_rsp_trdid; // transaction trdid
647      sc_signal<size_t>   r_cleanup_to_tgt_rsp_pktid; // transaction pktid
648
649      // Buffer between CLEANUP fsm and CC_SEND fsm (acknowledge a cleanup command from L1)
650      sc_signal<bool>     r_cleanup_to_cc_send_req;       // valid request
651      sc_signal<size_t>   r_cleanup_to_cc_send_srcid;     // L1 srcid
652      sc_signal<size_t>   r_cleanup_to_cc_send_set_index; // L1 set index
653      sc_signal<size_t>   r_cleanup_to_cc_send_way_index; // L1 way index
654      sc_signal<bool>     r_cleanup_to_cc_send_inst;      // Instruction Cleanup Ack
655
656      ///////////////////////////////////////////////////////
657      // Registers controlled by CAS fsm
658      ///////////////////////////////////////////////////////
659
660      sc_signal<int>      r_cas_fsm;        // FSM state
661      sc_signal<data_t>   r_cas_wdata;      // write data word
662      sc_signal<data_t> * r_cas_rdata;      // read data word
663      sc_signal<uint32_t> r_cas_lfsr;       // lfsr for random introducing
664      sc_signal<size_t>   r_cas_cpt;        // size of command
665      sc_signal<copy_t>   r_cas_copy;       // Srcid of the first copy
666      sc_signal<copy_t>   r_cas_copy_cache; // Srcid of the first copy
667      sc_signal<bool>     r_cas_copy_inst;  // Type of the first copy
668      sc_signal<size_t>   r_cas_count;      // number of copies
669      sc_signal<size_t>   r_cas_ptr;        // pointer to the heap
670      sc_signal<size_t>   r_cas_next_ptr;   // next pointer to the heap
671      sc_signal<bool>     r_cas_is_cnt;     // is_cnt bit (in directory)
672      sc_signal<bool>     r_cas_dirty;      // dirty bit (in directory)
673      sc_signal<size_t>   r_cas_way;        // way in directory
674      sc_signal<size_t>   r_cas_set;        // set in directory
675      sc_signal<data_t>   r_cas_tag;        // cache line tag (in directory)
676      sc_signal<size_t>   r_cas_trt_index;  // Transaction Table index
677      sc_signal<size_t>   r_cas_upt_index;  // Update Table index
678      sc_signal<data_t> * r_cas_data;       // cache line data
679
680      // Buffer between CAS fsm and IXR_CMD fsm (XRAM write)
681      sc_signal<bool>     r_cas_to_ixr_cmd_req;   // valid request
682      sc_signal<addr_t>   r_cas_to_ixr_cmd_nline; // cache line index
683      sc_signal<size_t>   r_cas_to_ixr_cmd_trdid; // index in Transaction Table
684      sc_signal<bool>     r_cas_to_ixr_cmd_write; // write request
685      sc_signal<data_t> * r_cas_to_ixr_cmd_data;  // cache line data
686
687
688      // Buffer between CAS fsm and TGT_RSP fsm
689      sc_signal<bool>     r_cas_to_tgt_rsp_req;   // valid request
690      sc_signal<data_t>   r_cas_to_tgt_rsp_data;  // read data word
691      sc_signal<size_t>   r_cas_to_tgt_rsp_srcid; // Transaction srcid
692      sc_signal<size_t>   r_cas_to_tgt_rsp_trdid; // Transaction trdid
693      sc_signal<size_t>   r_cas_to_tgt_rsp_pktid; // Transaction pktid
694
695      // Buffer between CAS fsm and CC_SEND fsm (Update/Invalidate L1 caches)
696      sc_signal<bool>     r_cas_to_cc_send_multi_req;     // valid request
697      sc_signal<bool>     r_cas_to_cc_send_brdcast_req;   // brdcast request
698      sc_signal<addr_t>   r_cas_to_cc_send_nline;         // cache line index
699      sc_signal<size_t>   r_cas_to_cc_send_trdid;         // index in Update Table
700      sc_signal<data_t>   r_cas_to_cc_send_wdata;         // data (one word)
701      sc_signal<bool>     r_cas_to_cc_send_is_long;       // it is a 64 bits CAS
702      sc_signal<data_t>   r_cas_to_cc_send_wdata_high;    // data high (one word)
703      sc_signal<size_t>   r_cas_to_cc_send_index;         // index of the word in line
704      GenericFifo<bool>   m_cas_to_cc_send_inst_fifo;     // fifo for the L1 type
705      GenericFifo<size_t> m_cas_to_cc_send_srcid_fifo;    // fifo for srcids
706
707#if L1_MULTI_CACHE
708      GenericFifo<size_t> m_cas_to_cc_send_cache_id_fifo; // fifo for srcids
709#endif
710
711      ////////////////////////////////////////////////////
712      // Registers controlled by the IXR_RSP fsm
713      ////////////////////////////////////////////////////
714
715      sc_signal<int>      r_ixr_rsp_fsm;       // FSM state
716      sc_signal<size_t>   r_ixr_rsp_trt_index; // TRT entry index
717      sc_signal<size_t>   r_ixr_rsp_cpt;       // word counter
718
719      // Buffer between IXR_RSP fsm and XRAM_RSP fsm  (response from the XRAM)
720      sc_signal<bool>   * r_ixr_rsp_to_xram_rsp_rok; // A xram response is ready
721
722      ////////////////////////////////////////////////////
723      // Registers controlled by the XRAM_RSP fsm
724      ////////////////////////////////////////////////////
725
726      sc_signal<int>      r_xram_rsp_fsm;               // FSM state
727      sc_signal<size_t>   r_xram_rsp_trt_index;         // TRT entry index
728      TransactionTabEntry r_xram_rsp_trt_buf;           // TRT entry local buffer
729      sc_signal<bool>     r_xram_rsp_victim_inval;      // victim line invalidate
730      sc_signal<bool>     r_xram_rsp_victim_is_cnt;     // victim line inst bit
731      sc_signal<bool>     r_xram_rsp_victim_dirty;      // victim line dirty bit
732      sc_signal<size_t>   r_xram_rsp_victim_way;        // victim line way
733      sc_signal<size_t>   r_xram_rsp_victim_set;        // victim line set
734      sc_signal<addr_t>   r_xram_rsp_victim_nline;      // victim line index
735      sc_signal<copy_t>   r_xram_rsp_victim_copy;       // victim line first copy
736      sc_signal<copy_t>   r_xram_rsp_victim_copy_cache; // victim line first copy
737      sc_signal<bool>     r_xram_rsp_victim_copy_inst;  // victim line type of first copy
738      sc_signal<size_t>   r_xram_rsp_victim_count;      // victim line number of copies
739      sc_signal<size_t>   r_xram_rsp_victim_ptr;        // victim line pointer to the heap
740      sc_signal<data_t> * r_xram_rsp_victim_data;       // victim line data
741      sc_signal<size_t>   r_xram_rsp_upt_index;         // UPT entry index
742      sc_signal<size_t>   r_xram_rsp_next_ptr;          // Next pointer to the heap
743
744      // Buffer between XRAM_RSP fsm and TGT_RSP fsm  (response to L1 cache)
745      sc_signal<bool>     r_xram_rsp_to_tgt_rsp_req;    // Valid request
746      sc_signal<size_t>   r_xram_rsp_to_tgt_rsp_srcid;  // Transaction srcid
747      sc_signal<size_t>   r_xram_rsp_to_tgt_rsp_trdid;  // Transaction trdid
748      sc_signal<size_t>   r_xram_rsp_to_tgt_rsp_pktid;  // Transaction pktid
749      sc_signal<data_t> * r_xram_rsp_to_tgt_rsp_data;   // data (one cache line)
750      sc_signal<size_t>   r_xram_rsp_to_tgt_rsp_word;   // first word index
751      sc_signal<size_t>   r_xram_rsp_to_tgt_rsp_length; // length of the response
752      sc_signal<bool>     r_xram_rsp_to_tgt_rsp_rerror; // send error to requester
753      sc_signal<addr_t>   r_xram_rsp_to_tgt_rsp_ll_key; // LL key from llsc_global_table
754
755      // Buffer between XRAM_RSP fsm and CC_SEND fsm (Inval L1 Caches)
756      sc_signal<bool>     r_xram_rsp_to_cc_send_multi_req;     // Valid request
757      sc_signal<bool>     r_xram_rsp_to_cc_send_brdcast_req;   // Broadcast request
758      sc_signal<addr_t>   r_xram_rsp_to_cc_send_nline;         // cache line index;
759      sc_signal<size_t>   r_xram_rsp_to_cc_send_trdid;         // index of UPT entry
760      GenericFifo<bool>   m_xram_rsp_to_cc_send_inst_fifo;     // fifo for the L1 type
761      GenericFifo<size_t> m_xram_rsp_to_cc_send_srcid_fifo;    // fifo for srcids
762
763#if L1_MULTI_CACHE
764      GenericFifo<size_t> m_xram_rsp_to_cc_send_cache_id_fifo; // fifo for srcids
765#endif
766
767      // Buffer between XRAM_RSP fsm and IXR_CMD fsm (XRAM write)
768      sc_signal<bool>     r_xram_rsp_to_ixr_cmd_req;   // Valid request
769      sc_signal<addr_t>   r_xram_rsp_to_ixr_cmd_nline; // cache line index
770      sc_signal<data_t> * r_xram_rsp_to_ixr_cmd_data;  // cache line data
771      sc_signal<size_t>   r_xram_rsp_to_ixr_cmd_trdid; // index in transaction table
772
773      ////////////////////////////////////////////////////
774      // Registers controlled by the IXR_CMD fsm
775      ////////////////////////////////////////////////////
776
777      sc_signal<int>      r_ixr_cmd_fsm;
778      sc_signal<size_t>   r_ixr_cmd_cpt;
779
780      ////////////////////////////////////////////////////
781      // Registers controlled by TGT_RSP fsm
782      ////////////////////////////////////////////////////
783
784      sc_signal<int>      r_tgt_rsp_fsm;
785      sc_signal<size_t>   r_tgt_rsp_cpt;
786      sc_signal<bool>     r_tgt_rsp_key_sent;
787
788      ////////////////////////////////////////////////////
789      // Registers controlled by CC_SEND fsm
790      ////////////////////////////////////////////////////
791
792      sc_signal<int>      r_cc_send_fsm;
793      sc_signal<size_t>   r_cc_send_cpt;
794      sc_signal<bool>     r_cc_send_inst;
795
796      ////////////////////////////////////////////////////
797      // Registers controlled by CC_RECEIVE fsm
798      ////////////////////////////////////////////////////
799
800      sc_signal<int>      r_cc_receive_fsm;
801
802      ////////////////////////////////////////////////////
803      // Registers controlled by ALLOC_DIR fsm
804      ////////////////////////////////////////////////////
805
806      sc_signal<int>      r_alloc_dir_fsm;
807      sc_signal<unsigned> r_alloc_dir_reset_cpt;
808
809      ////////////////////////////////////////////////////
810      // Registers controlled by ALLOC_TRT fsm
811      ////////////////////////////////////////////////////
812
813      sc_signal<int>      r_alloc_trt_fsm;
814
815      ////////////////////////////////////////////////////
816      // Registers controlled by ALLOC_UPT fsm
817      ////////////////////////////////////////////////////
818
819      sc_signal<int>      r_alloc_upt_fsm;
820
821      ////////////////////////////////////////////////////
822      // Registers controlled by ALLOC_HEAP fsm
823      ////////////////////////////////////////////////////
824
825      sc_signal<int>      r_alloc_heap_fsm;
826      sc_signal<unsigned> r_alloc_heap_reset_cpt;
827    }; // end class VciMemCache
828
829}}
830
831#endif
832
833// Local Variables:
834// tab-width: 2
835// c-basic-offset: 2
836// c-file-offsets:((innamespace . 0)(inline-open . 0))
837// indent-tabs-mode: nil
838// End:
839
840// vim: filetype=cpp:expandtab:shiftwidth=2:tabstop=2:softtabstop=2
841
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