source: trunk/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h @ 403

Last change on this file since 403 was 403, checked in by alain, 11 years ago

Updating vci_cc_vcache_wrapper and vci_mem_cache to comply with the new DSPIN signals (explcit EOP).

File size: 35.9 KB
Line 
1/* -*- c++ -*-
2 * File         : vci_mem_cache.h
3 * Date         : 26/10/2008
4 * Copyright    : UPMC / LIP6
5 * Authors      : Alain Greiner / Eric Guthmuller
6 *
7 * SOCLIB_LGPL_HEADER_BEGIN
8 *
9 * This file is part of SoCLib, GNU LGPLv2.1.
10 *
11 * SoCLib is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU Lesser General Public License as published
13 * by the Free Software Foundation; version 2.1 of the License.
14 *
15 * SoCLib is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
18 * Lesser General Public License for more details.
19 *
20 * You should have received a copy of the GNU Lesser General Public
21 * License along with SoCLib; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
23 * 02110-1301 USA
24 *
25 * SOCLIB_LGPL_HEADER_END
26 *
27 * Maintainers: alain eric.guthmuller@polytechnique.edu
28 *              cesar.fuguet-tortolero@lip6.fr
29 *              alexandre.joannou@lip6.fr
30 */
31
32#ifndef SOCLIB_CABA_MEM_CACHE_H
33#define SOCLIB_CABA_MEM_CACHE_H
34
35#include <inttypes.h>
36#include <systemc>
37#include <list>
38#include <cassert>
39#include "arithmetics.h"
40#include "alloc_elems.h"
41#include "caba_base_module.h"
42#include "vci_target.h"
43#include "vci_initiator.h"
44#include "generic_fifo.h"
45#include "mapping_table.h"
46#include "int_tab.h"
47#include "generic_llsc_global_table.h"
48#include "mem_cache_directory.h"
49#include "xram_transaction.h"
50#include "update_tab.h"
51#include "dspin_interface.h"
52#include "dspin_dhccp_param.h"
53
54#define TRT_ENTRIES      4      // Number of entries in TRT
55#define UPT_ENTRIES      4      // Number of entries in UPT
56#define HEAP_ENTRIES     1024   // Number of entries in HEAP
57
58namespace soclib {  namespace caba {
59
60  using namespace sc_core;
61
62  template<typename vci_param_int, 
63           typename vci_param_ext,
64           size_t   dspin_in_width,
65           size_t   dspin_out_width>
66    class VciMemCache
67    : public soclib::caba::BaseModule
68    {
69      typedef typename vci_param_int::fast_addr_t  addr_t;
70
71      typedef typename sc_dt::sc_uint<64>          wide_data_t;
72
73      typedef uint32_t data_t;
74      typedef uint32_t tag_t;
75      typedef uint32_t be_t;
76      typedef uint32_t copy_t;
77
78      /* States of the TGT_CMD fsm */
79      enum tgt_cmd_fsm_state_e{
80        TGT_CMD_IDLE,
81        TGT_CMD_READ,
82        TGT_CMD_WRITE,
83        TGT_CMD_CAS
84      };
85
86      /* States of the TGT_RSP fsm */
87      enum tgt_rsp_fsm_state_e
88      {
89        TGT_RSP_READ_IDLE,
90        TGT_RSP_WRITE_IDLE,
91        TGT_RSP_CAS_IDLE,
92        TGT_RSP_XRAM_IDLE,
93        TGT_RSP_INIT_IDLE,
94        TGT_RSP_CLEANUP_IDLE,
95        TGT_RSP_READ,
96        TGT_RSP_WRITE,
97        TGT_RSP_CAS,
98        TGT_RSP_XRAM,
99        TGT_RSP_INIT,
100        TGT_RSP_CLEANUP
101      };
102
103      /* States of the DSPIN_TGT fsm */
104      enum cc_receive_fsm_state_e
105      {
106        CC_RECEIVE_IDLE,
107        CC_RECEIVE_CLEANUP,
108        CC_RECEIVE_CLEANUP_EOP,
109        CC_RECEIVE_MULTI_ACK
110      };
111
112      /* States of the CC_SEND fsm */
113      enum cc_send_fsm_state_e
114      {
115        CC_SEND_XRAM_RSP_IDLE,
116        CC_SEND_WRITE_IDLE,
117        CC_SEND_CAS_IDLE,
118        CC_SEND_CLEANUP_IDLE,
119        CC_SEND_CLEANUP_ACK,
120        CC_SEND_XRAM_RSP_BRDCAST_HEADER,
121        CC_SEND_XRAM_RSP_BRDCAST_NLINE,
122        CC_SEND_XRAM_RSP_INVAL_HEADER,
123        CC_SEND_XRAM_RSP_INVAL_NLINE,
124        CC_SEND_WRITE_BRDCAST_HEADER,
125        CC_SEND_WRITE_BRDCAST_NLINE,
126        CC_SEND_WRITE_UPDT_HEADER,
127        CC_SEND_WRITE_UPDT_NLINE,
128        CC_SEND_WRITE_UPDT_DATA,
129        CC_SEND_CAS_BRDCAST_HEADER,
130        CC_SEND_CAS_BRDCAST_NLINE,
131        CC_SEND_CAS_UPDT_HEADER,
132        CC_SEND_CAS_UPDT_NLINE,
133        CC_SEND_CAS_UPDT_DATA,
134        CC_SEND_CAS_UPDT_DATA_HIGH
135      };
136
137      /* States of the MULTI_ACK fsm */
138      enum multi_ack_fsm_state_e
139      {
140        MULTI_ACK_IDLE,
141        MULTI_ACK_UPT_LOCK,
142        MULTI_ACK_UPT_CLEAR,
143        MULTI_ACK_WRITE_RSP
144      };
145
146      /* States of the READ fsm */
147      enum read_fsm_state_e
148      {
149        READ_IDLE,
150        READ_DIR_REQ,
151        READ_DIR_LOCK,
152        READ_DIR_HIT,
153        READ_HEAP_REQ,
154        READ_HEAP_LOCK,
155        READ_HEAP_WRITE,
156        READ_HEAP_ERASE,
157        READ_HEAP_LAST,
158        READ_RSP,
159        READ_TRT_LOCK,
160        READ_TRT_SET,
161        READ_TRT_REQ
162      };
163
164      /* States of the WRITE fsm */
165      enum write_fsm_state_e
166      {
167        WRITE_IDLE,
168        WRITE_NEXT,
169        WRITE_DIR_REQ,
170        WRITE_DIR_LOCK,
171        WRITE_DIR_READ,
172        WRITE_DIR_HIT,
173        WRITE_UPT_LOCK,
174        WRITE_UPT_HEAP_LOCK,
175        WRITE_UPT_REQ,
176        WRITE_UPT_NEXT,
177        WRITE_UPT_DEC,
178        WRITE_RSP,
179        WRITE_MISS_TRT_LOCK,
180        WRITE_MISS_TRT_DATA,
181        WRITE_MISS_TRT_SET,
182        WRITE_MISS_XRAM_REQ,
183        WRITE_BC_TRT_LOCK,
184        WRITE_BC_UPT_LOCK,
185        WRITE_BC_DIR_INVAL,
186        WRITE_BC_CC_SEND,
187        WRITE_BC_XRAM_REQ,
188        WRITE_WAIT
189      };
190
191      /* States of the IXR_RSP fsm */
192      enum ixr_rsp_fsm_state_e
193      {
194        IXR_RSP_IDLE,
195        IXR_RSP_ACK,
196        IXR_RSP_TRT_ERASE,
197        IXR_RSP_TRT_READ
198      };
199
200      /* States of the XRAM_RSP fsm */
201      enum xram_rsp_fsm_state_e
202      {
203        XRAM_RSP_IDLE,
204        XRAM_RSP_TRT_COPY,
205        XRAM_RSP_TRT_DIRTY,
206        XRAM_RSP_DIR_LOCK,
207        XRAM_RSP_DIR_UPDT,
208        XRAM_RSP_DIR_RSP,
209        XRAM_RSP_INVAL_LOCK,
210        XRAM_RSP_INVAL_WAIT,
211        XRAM_RSP_INVAL,
212        XRAM_RSP_WRITE_DIRTY,
213        XRAM_RSP_HEAP_REQ,
214        XRAM_RSP_HEAP_ERASE,
215        XRAM_RSP_HEAP_LAST,
216        XRAM_RSP_ERROR_ERASE,
217        XRAM_RSP_ERROR_RSP
218      };
219
220      /* States of the IXR_CMD fsm */
221      enum ixr_cmd_fsm_state_e
222      {
223        IXR_CMD_READ_IDLE,
224        IXR_CMD_WRITE_IDLE,
225        IXR_CMD_CAS_IDLE,
226        IXR_CMD_XRAM_IDLE,
227        IXR_CMD_READ,
228        IXR_CMD_WRITE,
229        IXR_CMD_CAS,
230        IXR_CMD_XRAM
231      };
232
233      /* States of the CAS fsm */
234      enum cas_fsm_state_e
235      {
236        CAS_IDLE,
237        CAS_DIR_REQ,
238        CAS_DIR_LOCK,
239        CAS_DIR_HIT_READ,
240        CAS_DIR_HIT_COMPARE,
241        CAS_DIR_HIT_WRITE,
242        CAS_UPT_LOCK,
243        CAS_UPT_HEAP_LOCK,
244        CAS_UPT_REQ,
245        CAS_UPT_NEXT,
246        CAS_BC_TRT_LOCK,
247        CAS_BC_UPT_LOCK,
248        CAS_BC_DIR_INVAL,
249        CAS_BC_CC_SEND,
250        CAS_BC_XRAM_REQ,
251        CAS_RSP_FAIL,
252        CAS_RSP_SUCCESS,
253        CAS_MISS_TRT_LOCK,
254        CAS_MISS_TRT_SET,
255        CAS_MISS_XRAM_REQ,
256        CAS_WAIT
257      };
258
259      /* States of the CLEANUP fsm */
260      enum cleanup_fsm_state_e
261      {
262        CLEANUP_IDLE,
263        CLEANUP_GET_NLINE,
264        CLEANUP_DIR_REQ,
265        CLEANUP_DIR_LOCK,
266        CLEANUP_DIR_WRITE,
267        CLEANUP_HEAP_REQ,
268        CLEANUP_HEAP_LOCK,
269        CLEANUP_HEAP_SEARCH,
270        CLEANUP_HEAP_CLEAN,
271        CLEANUP_HEAP_FREE,
272        CLEANUP_UPT_LOCK,
273        CLEANUP_UPT_DECREMENT,
274        CLEANUP_UPT_CLEAR,
275        CLEANUP_WRITE_RSP,
276        CLEANUP_SEND_ACK
277      };
278
279      /* States of the ALLOC_DIR fsm */
280      enum alloc_dir_fsm_state_e
281      {
282        ALLOC_DIR_RESET,
283        ALLOC_DIR_READ,
284        ALLOC_DIR_WRITE,
285        ALLOC_DIR_CAS,
286        ALLOC_DIR_CLEANUP,
287        ALLOC_DIR_XRAM_RSP
288      };
289
290      /* States of the ALLOC_TRT fsm */
291      enum alloc_trt_fsm_state_e
292      {
293        ALLOC_TRT_READ,
294        ALLOC_TRT_WRITE,
295        ALLOC_TRT_CAS,
296        ALLOC_TRT_XRAM_RSP,
297        ALLOC_TRT_IXR_RSP
298      };
299
300      /* States of the ALLOC_UPT fsm */
301      enum alloc_upt_fsm_state_e
302      {
303        ALLOC_UPT_WRITE,
304        ALLOC_UPT_XRAM_RSP,
305        ALLOC_UPT_MULTI_ACK,
306        ALLOC_UPT_CLEANUP,
307        ALLOC_UPT_CAS
308      };
309
310      /* States of the ALLOC_HEAP fsm */
311      enum alloc_heap_fsm_state_e
312      {
313        ALLOC_HEAP_RESET,
314        ALLOC_HEAP_READ,
315        ALLOC_HEAP_WRITE,
316        ALLOC_HEAP_CAS,
317        ALLOC_HEAP_CLEANUP,
318        ALLOC_HEAP_XRAM_RSP
319      };
320
321      /* transaction type, pktid field */
322      enum transaction_type_e
323      {
324          // b3 unused
325          // b2 READ / NOT READ
326          // Si READ
327          //  b1 DATA / INS
328          //  b0 UNC / MISS
329          // Si NOT READ
330          //  b1 accÚs table llsc type SW / other
331          //  b2 WRITE/CAS/LL/SC
332          TYPE_READ_DATA_UNC          = 0x0,
333          TYPE_READ_DATA_MISS         = 0x1,
334          TYPE_READ_INS_UNC           = 0x2,
335          TYPE_READ_INS_MISS          = 0x3,
336          TYPE_WRITE                  = 0x4,
337          TYPE_CAS                    = 0x5,
338          TYPE_LL                     = 0x6,
339          TYPE_SC                     = 0x7
340      };
341
342      /* SC return values */
343      enum sc_status_type_e
344      {
345          SC_SUCCESS  =   0x00000000,
346          SC_FAIL     =   0x00000001
347      };
348
349      // debug variables (for each FSM)
350      bool         m_debug_global;
351      bool         m_debug_tgt_cmd_fsm;
352      bool         m_debug_tgt_rsp_fsm;
353      bool         m_debug_cc_send_fsm;
354      bool         m_debug_cc_receive_fsm;
355      bool         m_debug_multi_ack_fsm;
356      bool         m_debug_read_fsm;
357      bool         m_debug_write_fsm;
358      bool         m_debug_cas_fsm;
359      bool         m_debug_cleanup_fsm;
360      bool         m_debug_ixr_cmd_fsm;
361      bool         m_debug_ixr_rsp_fsm;
362      bool         m_debug_xram_rsp_fsm;
363      bool         m_debug_previous_hit;
364      size_t       m_debug_previous_count;
365
366      bool         m_monitor_ok;
367      addr_t       m_monitor_base;
368      addr_t       m_monitor_length;
369
370      // instrumentation counters
371      uint32_t     m_cpt_cycles;        // Counter of cycles
372      uint32_t     m_cpt_read;          // Number of READ transactions
373      uint32_t     m_cpt_read_miss;     // Number of MISS READ
374      uint32_t     m_cpt_write;         // Number of WRITE transactions
375      uint32_t     m_cpt_write_miss;    // Number of MISS WRITE
376      uint32_t     m_cpt_write_cells;   // Cumulated length for WRITE transactions
377      uint32_t     m_cpt_write_dirty;   // Cumulated length for WRITE transactions
378      uint32_t     m_cpt_update;        // Number of UPDATE transactions
379      uint32_t     m_cpt_trt_rb;        // Read blocked by a hit in trt
380      uint32_t     m_cpt_trt_full;      // Transaction blocked due to a full trt
381      uint32_t     m_cpt_update_mult;   // Number of targets for UPDATE
382      uint32_t     m_cpt_inval;         // Number of INVAL  transactions
383      uint32_t     m_cpt_inval_mult;    // Number of targets for INVAL
384      uint32_t     m_cpt_inval_brdcast; // Number of BROADCAST INVAL
385      uint32_t     m_cpt_cleanup;       // Number of CLEANUP transactions
386      uint32_t     m_cpt_ll;            // Number of LL transactions
387      uint32_t     m_cpt_sc;            // Number of SC transactions
388      uint32_t     m_cpt_cas;           // Number of CAS transactions
389
390      size_t       m_prev_count;
391
392      protected:
393
394      SC_HAS_PROCESS(VciMemCache);
395
396      public:
397      sc_in<bool>                                 p_clk;
398      sc_in<bool>                                 p_resetn;
399      soclib::caba::VciTarget<vci_param_int>      p_vci_tgt;
400      soclib::caba::VciInitiator<vci_param_ext>   p_vci_ixr;
401      soclib::caba::DspinInput<dspin_in_width>    p_dspin_in;
402      soclib::caba::DspinOutput<dspin_out_width>  p_dspin_out;
403
404      VciMemCache(
405          sc_module_name name,                                // Instance Name
406          const soclib::common::MappingTable &mtp,            // Mapping table direct network
407          const soclib::common::MappingTable &mtx,            // Mapping table external network
408          const soclib::common::IntTab       &srcid_x,        // global index on external network
409          const soclib::common::IntTab       &tgtid_d,        // global index on direct network
410          const size_t                       cc_global_id,    // global index on cc network
411          const size_t                       nways,           // Number of ways per set
412          const size_t                       nsets,           // Number of sets
413          const size_t                       nwords,          // Number of words per line
414          const size_t                       max_copies,      // max number of copies in heap
415          const size_t                       heap_size=HEAP_ENTRIES,
416          const size_t                       trt_lines=TRT_ENTRIES, 
417          const size_t                       upt_lines=UPT_ENTRIES,     
418          const size_t                       debug_start_cycle=0,
419          const bool                         debug_ok=false );
420
421      ~VciMemCache();
422
423      void print_stats();
424      void print_trace();
425      void copies_monitor(addr_t addr);
426      void start_monitor(addr_t addr, addr_t length);
427      void stop_monitor();
428
429      private:
430
431      void transition();
432      void genMoore();
433      void check_monitor( const char *buf, addr_t addr, data_t data, bool read);
434
435      // Component attributes
436      std::list<soclib::common::Segment> m_seglist;          // segments allocated to memcache
437      size_t                             m_nseg;             // number of segments
438      soclib::common::Segment            **m_seg;            // array of segments pointers
439      const size_t                       m_srcid_x;          // global index on external network
440      const size_t                       m_initiators;       // Number of initiators
441      const size_t                       m_heap_size;        // Size of the heap
442      const size_t                       m_ways;             // Number of ways in a set
443      const size_t                       m_sets;             // Number of cache sets
444      const size_t                       m_words;            // Number of words in a line
445      const size_t                       m_cc_global_id;     // global_index on cc network
446      size_t                             m_debug_start_cycle;
447      bool                               m_debug_ok;
448      uint32_t                           m_trt_lines;
449      TransactionTab                     m_trt;              // xram transaction table
450      uint32_t                           m_upt_lines;
451      UpdateTab                          m_upt;              // pending update & invalidate
452      CacheDirectory                     m_cache_directory;  // data cache directory
453      CacheData                          m_cache_data;       // data array[set][way][word]
454      HeapDirectory                      m_heap;             // heap for copies
455      size_t                             m_max_copies;       // max number of copies in heap
456      GenericLLSCGlobalTable
457      < 32  ,                              // number of slots
458        4096,                              // number of processors in the system
459        8000,                              // registration life (# of LL operations)
460        addr_t >  m_llsc_table;            // ll/sc global registration table
461
462      // adress masks
463      const soclib::common::AddressMaskingTable<addr_t>   m_x;
464      const soclib::common::AddressMaskingTable<addr_t>   m_y;
465      const soclib::common::AddressMaskingTable<addr_t>   m_z;
466      const soclib::common::AddressMaskingTable<addr_t>   m_nline;
467
468      // broadcast address
469      uint32_t                           m_broadcast_boundaries;
470
471      //////////////////////////////////////////////////
472      // Registers controlled by the TGT_CMD fsm
473      //////////////////////////////////////////////////
474
475      // Fifo between TGT_CMD fsm and READ fsm
476      GenericFifo<addr_t>    m_cmd_read_addr_fifo;
477      GenericFifo<size_t>    m_cmd_read_length_fifo;
478      GenericFifo<size_t>    m_cmd_read_srcid_fifo;
479      GenericFifo<size_t>    m_cmd_read_trdid_fifo;
480      GenericFifo<size_t>    m_cmd_read_pktid_fifo;
481
482      // Fifo between TGT_CMD fsm and WRITE fsm
483      GenericFifo<addr_t>    m_cmd_write_addr_fifo;
484      GenericFifo<bool>      m_cmd_write_eop_fifo;
485      GenericFifo<size_t>    m_cmd_write_srcid_fifo;
486      GenericFifo<size_t>    m_cmd_write_trdid_fifo;
487      GenericFifo<size_t>    m_cmd_write_pktid_fifo;
488      GenericFifo<data_t>    m_cmd_write_data_fifo;
489      GenericFifo<be_t>      m_cmd_write_be_fifo;
490
491      // Fifo between TGT_CMD fsm and CAS fsm
492      GenericFifo<addr_t>    m_cmd_cas_addr_fifo;
493      GenericFifo<bool>      m_cmd_cas_eop_fifo;
494      GenericFifo<size_t>    m_cmd_cas_srcid_fifo;
495      GenericFifo<size_t>    m_cmd_cas_trdid_fifo;
496      GenericFifo<size_t>    m_cmd_cas_pktid_fifo;
497      GenericFifo<data_t>    m_cmd_cas_wdata_fifo;
498
499      // Fifo between CC_RECEIVE fsm and CLEANUP fsm
500      GenericFifo<uint64_t>  m_cc_receive_to_cleanup_fifo;
501     
502      // Fifo between CC_RECEIVE fsm and MULTI_ACK fsm
503      GenericFifo<uint64_t>  m_cc_receive_to_multi_ack_fifo;
504
505      sc_signal<int>         r_tgt_cmd_fsm;
506
507      ///////////////////////////////////////////////////////
508      // Registers controlled by the READ fsm
509      ///////////////////////////////////////////////////////
510
511      sc_signal<int>      r_read_fsm;        // FSM state
512      sc_signal<size_t>   r_read_copy;       // Srcid of the first copy
513      sc_signal<size_t>   r_read_copy_cache; // Srcid of the first copy
514      sc_signal<bool>     r_read_copy_inst;  // Type of the first copy
515      sc_signal<tag_t>    r_read_tag;        // cache line tag (in directory)
516      sc_signal<bool>     r_read_is_cnt;     // is_cnt bit (in directory)
517      sc_signal<bool>     r_read_lock;       // lock bit (in directory)
518      sc_signal<bool>     r_read_dirty;      // dirty bit (in directory)
519      sc_signal<size_t>   r_read_count;      // number of copies
520      sc_signal<size_t>   r_read_ptr;        // pointer to the heap
521      sc_signal<data_t> * r_read_data;       // data (one cache line)
522      sc_signal<size_t>   r_read_way;        // associative way (in cache)
523      sc_signal<size_t>   r_read_trt_index;  // Transaction Table index
524      sc_signal<size_t>   r_read_next_ptr;   // Next entry to point to
525      sc_signal<bool>     r_read_last_free;  // Last free entry
526      sc_signal<addr_t>   r_read_ll_key;     // LL key from the llsc_global_table
527
528      // Buffer between READ fsm and IXR_CMD fsm (ask a missing cache line to XRAM)
529      sc_signal<bool>     r_read_to_ixr_cmd_req;    // valid request
530      sc_signal<addr_t>   r_read_to_ixr_cmd_nline;  // cache line index
531      sc_signal<size_t>   r_read_to_ixr_cmd_trdid;  // index in Transaction Table
532
533      // Buffer between READ fsm and TGT_RSP fsm (send a hit read response to L1 cache)
534      sc_signal<bool>     r_read_to_tgt_rsp_req;    // valid request
535      sc_signal<size_t>   r_read_to_tgt_rsp_srcid;  // Transaction srcid
536      sc_signal<size_t>   r_read_to_tgt_rsp_trdid;  // Transaction trdid
537      sc_signal<size_t>   r_read_to_tgt_rsp_pktid;  // Transaction pktid
538      sc_signal<data_t> * r_read_to_tgt_rsp_data;   // data (one cache line)
539      sc_signal<size_t>   r_read_to_tgt_rsp_word;   // first word of the response
540      sc_signal<size_t>   r_read_to_tgt_rsp_length; // length of the response
541      sc_signal<addr_t>   r_read_to_tgt_rsp_ll_key; // LL key from the llsc_global_table
542
543      ///////////////////////////////////////////////////////////////
544      // Registers controlled by the WRITE fsm
545      ///////////////////////////////////////////////////////////////
546
547      sc_signal<int>      r_write_fsm;        // FSM state
548      sc_signal<addr_t>   r_write_address;    // first word address
549      sc_signal<size_t>   r_write_word_index; // first word index in line
550      sc_signal<size_t>   r_write_word_count; // number of words in line
551      sc_signal<size_t>   r_write_srcid;      // transaction srcid
552      sc_signal<size_t>   r_write_trdid;      // transaction trdid
553      sc_signal<size_t>   r_write_pktid;      // transaction pktid
554      sc_signal<data_t> * r_write_data;       // data (one cache line)
555      sc_signal<be_t>   * r_write_be;         // one byte enable per word
556      sc_signal<bool>     r_write_byte;       // (BE != 0X0) and (BE != 0xF)
557      sc_signal<bool>     r_write_is_cnt;     // is_cnt bit (in directory)
558      sc_signal<bool>     r_write_lock;       // lock bit (in directory)
559      sc_signal<tag_t>    r_write_tag;        // cache line tag (in directory)
560      sc_signal<size_t>   r_write_copy;       // first owner of the line
561      sc_signal<size_t>   r_write_copy_cache; // first owner of the line
562      sc_signal<bool>     r_write_copy_inst;  // is this owner a ICache ?
563      sc_signal<size_t>   r_write_count;      // number of copies
564      sc_signal<size_t>   r_write_ptr;        // pointer to the heap
565      sc_signal<size_t>   r_write_next_ptr;   // next pointer to the heap
566      sc_signal<bool>     r_write_to_dec;     // need to decrement update counter
567      sc_signal<size_t>   r_write_way;        // way of the line
568      sc_signal<size_t>   r_write_trt_index;  // index in Transaction Table
569      sc_signal<size_t>   r_write_upt_index;  // index in Update Table
570      sc_signal<bool>     r_write_sc_fail;    // sc command failed
571      sc_signal<bool>     r_write_pending_sc; // sc command pending
572
573      // Buffer between WRITE fsm and TGT_RSP fsm (acknowledge a write command from L1)
574      sc_signal<bool>     r_write_to_tgt_rsp_req;     // valid request
575      sc_signal<size_t>   r_write_to_tgt_rsp_srcid;   // transaction srcid
576      sc_signal<size_t>   r_write_to_tgt_rsp_trdid;   // transaction trdid
577      sc_signal<size_t>   r_write_to_tgt_rsp_pktid;   // transaction pktid
578      sc_signal<bool>     r_write_to_tgt_rsp_sc_fail; // sc command failed
579
580      // Buffer between WRITE fsm and IXR_CMD fsm (ask a missing cache line to XRAM)
581      sc_signal<bool>     r_write_to_ixr_cmd_req;   // valid request
582      sc_signal<bool>     r_write_to_ixr_cmd_write; // write request
583      sc_signal<addr_t>   r_write_to_ixr_cmd_nline; // cache line index
584      sc_signal<data_t> * r_write_to_ixr_cmd_data;  // cache line data
585      sc_signal<size_t>   r_write_to_ixr_cmd_trdid; // index in Transaction Table
586
587      // Buffer between WRITE fsm and CC_SEND fsm (Update/Invalidate L1 caches)
588      sc_signal<bool>     r_write_to_cc_send_multi_req;     // valid multicast request
589      sc_signal<bool>     r_write_to_cc_send_brdcast_req;   // valid brdcast request
590      sc_signal<addr_t>   r_write_to_cc_send_nline;         // cache line index
591      sc_signal<size_t>   r_write_to_cc_send_trdid;         // index in Update Table
592      sc_signal<data_t> * r_write_to_cc_send_data;          // data (one cache line)
593      sc_signal<be_t>   * r_write_to_cc_send_be;            // word enable
594      sc_signal<size_t>   r_write_to_cc_send_count;         // number of words in line
595      sc_signal<size_t>   r_write_to_cc_send_index;         // index of first word in line
596      GenericFifo<bool>   m_write_to_cc_send_inst_fifo;     // fifo for the L1 type
597      GenericFifo<size_t> m_write_to_cc_send_srcid_fifo;    // fifo for srcids
598
599#if L1_MULTI_CACHE
600      GenericFifo<size_t> m_write_to_cc_send_cache_id_fifo; // fifo for srcids
601#endif
602
603      // Buffer between WRITE fsm and MULTI_ACK fsm (Decrement UPT entry)
604      sc_signal<bool>     r_write_to_multi_ack_req;       // valid request
605      sc_signal<size_t>   r_write_to_multi_ack_upt_index; // index in update table
606
607      /////////////////////////////////////////////////////////
608      // Registers controlled by MULTI_ACK fsm
609      //////////////////////////////////////////////////////////
610
611      sc_signal<int>      r_multi_ack_fsm;       // FSM state
612      sc_signal<size_t>   r_multi_ack_upt_index; // index in the Update Table
613      sc_signal<size_t>   r_multi_ack_srcid;     // pending write srcid
614      sc_signal<size_t>   r_multi_ack_trdid;     // pending write trdid
615      sc_signal<size_t>   r_multi_ack_pktid;     // pending write pktid
616      sc_signal<addr_t>   r_multi_ack_nline;     // pending write nline
617
618      // Buffer between MULTI_ACK fsm and TGT_RSP fsm (complete write/update transaction)
619      sc_signal<bool>     r_multi_ack_to_tgt_rsp_req;   // valid request
620      sc_signal<size_t>   r_multi_ack_to_tgt_rsp_srcid; // Transaction srcid
621      sc_signal<size_t>   r_multi_ack_to_tgt_rsp_trdid; // Transaction trdid
622      sc_signal<size_t>   r_multi_ack_to_tgt_rsp_pktid; // Transaction pktid
623
624      ///////////////////////////////////////////////////////
625      // Registers controlled by CLEANUP fsm
626      ///////////////////////////////////////////////////////
627
628      sc_signal<int>      r_cleanup_fsm;           // FSM state
629      sc_signal<size_t>   r_cleanup_srcid;         // transaction srcid
630      sc_signal<bool>     r_cleanup_inst;          // Instruction or Data ?
631      sc_signal<size_t>   r_cleanup_way_index;     // L1 Cache Way index
632      sc_signal<addr_t>   r_cleanup_nline;         // cache line index
633
634#if L1_MULTI_CACHE
635      sc_signal<size_t>   r_cleanup_pktid;         // transaction pktid
636#endif
637
638      sc_signal<copy_t>   r_cleanup_copy;          // first copy
639      sc_signal<copy_t>   r_cleanup_copy_cache;    // first copy
640      sc_signal<size_t>   r_cleanup_copy_inst;     // type of the first copy
641      sc_signal<copy_t>   r_cleanup_count;         // number of copies
642      sc_signal<size_t>   r_cleanup_ptr;           // pointer to the heap
643      sc_signal<size_t>   r_cleanup_prev_ptr;      // previous pointer to the heap
644      sc_signal<size_t>   r_cleanup_prev_srcid;    // srcid of previous heap entry
645      sc_signal<size_t>   r_cleanup_prev_cache_id; // srcid of previous heap entry
646      sc_signal<bool>     r_cleanup_prev_inst;     // inst bit of previous heap entry
647      sc_signal<size_t>   r_cleanup_next_ptr;      // next pointer to the heap
648      sc_signal<tag_t>    r_cleanup_tag;           // cache line tag (in directory)
649      sc_signal<bool>     r_cleanup_is_cnt;        // inst bit (in directory)
650      sc_signal<bool>     r_cleanup_lock;          // lock bit (in directory)
651      sc_signal<bool>     r_cleanup_dirty;         // dirty bit (in directory)
652      sc_signal<size_t>   r_cleanup_way;           // associative way (in cache)
653
654      sc_signal<size_t>   r_cleanup_write_srcid;   // srcid of write response
655      sc_signal<size_t>   r_cleanup_write_trdid;   // trdid of write rsp
656      sc_signal<size_t>   r_cleanup_write_pktid;   // pktid of write rsp
657      sc_signal<bool>     r_cleanup_write_need_rsp;// needs a write rsp
658
659      sc_signal<size_t>   r_cleanup_index;         // index of the INVAL line (in the UPT)
660
661      // Buffer between CLEANUP fsm and TGT_RSP fsm (acknowledge a write command from L1)
662      sc_signal<bool>     r_cleanup_to_tgt_rsp_req;   // valid request
663      sc_signal<size_t>   r_cleanup_to_tgt_rsp_srcid; // transaction srcid
664      sc_signal<size_t>   r_cleanup_to_tgt_rsp_trdid; // transaction trdid
665      sc_signal<size_t>   r_cleanup_to_tgt_rsp_pktid; // transaction pktid
666
667      // Buffer between CLEANUP fsm and CC_SEND fsm (acknowledge a cleanup command from L1)
668      sc_signal<bool>     r_cleanup_to_cc_send_req;       // valid request
669      sc_signal<size_t>   r_cleanup_to_cc_send_srcid;     // L1 srcid
670      sc_signal<size_t>   r_cleanup_to_cc_send_set_index; // L1 set index
671      sc_signal<size_t>   r_cleanup_to_cc_send_way_index; // L1 way index
672      sc_signal<bool>     r_cleanup_to_cc_send_inst;      // Instruction Cleanup Ack
673
674      ///////////////////////////////////////////////////////
675      // Registers controlled by CAS fsm
676      ///////////////////////////////////////////////////////
677
678      sc_signal<int>      r_cas_fsm;        // FSM state
679      sc_signal<data_t>   r_cas_wdata;      // write data word
680      sc_signal<data_t> * r_cas_rdata;      // read data word
681      sc_signal<uint32_t> r_cas_lfsr;       // lfsr for random introducing
682      sc_signal<size_t>   r_cas_cpt;        // size of command
683      sc_signal<copy_t>   r_cas_copy;       // Srcid of the first copy
684      sc_signal<copy_t>   r_cas_copy_cache; // Srcid of the first copy
685      sc_signal<bool>     r_cas_copy_inst;  // Type of the first copy
686      sc_signal<size_t>   r_cas_count;      // number of copies
687      sc_signal<size_t>   r_cas_ptr;        // pointer to the heap
688      sc_signal<size_t>   r_cas_next_ptr;   // next pointer to the heap
689      sc_signal<bool>     r_cas_is_cnt;     // is_cnt bit (in directory)
690      sc_signal<bool>     r_cas_dirty;      // dirty bit (in directory)
691      sc_signal<size_t>   r_cas_way;        // way in directory
692      sc_signal<size_t>   r_cas_set;        // set in directory
693      sc_signal<data_t>   r_cas_tag;        // cache line tag (in directory)
694      sc_signal<size_t>   r_cas_trt_index;  // Transaction Table index
695      sc_signal<size_t>   r_cas_upt_index;  // Update Table index
696      sc_signal<data_t> * r_cas_data;       // cache line data
697
698      // Buffer between CAS fsm and IXR_CMD fsm (XRAM write)
699      sc_signal<bool>     r_cas_to_ixr_cmd_req;   // valid request
700      sc_signal<addr_t>   r_cas_to_ixr_cmd_nline; // cache line index
701      sc_signal<size_t>   r_cas_to_ixr_cmd_trdid; // index in Transaction Table
702      sc_signal<bool>     r_cas_to_ixr_cmd_write; // write request
703      sc_signal<data_t> * r_cas_to_ixr_cmd_data;  // cache line data
704
705
706      // Buffer between CAS fsm and TGT_RSP fsm
707      sc_signal<bool>     r_cas_to_tgt_rsp_req;   // valid request
708      sc_signal<data_t>   r_cas_to_tgt_rsp_data;  // read data word
709      sc_signal<size_t>   r_cas_to_tgt_rsp_srcid; // Transaction srcid
710      sc_signal<size_t>   r_cas_to_tgt_rsp_trdid; // Transaction trdid
711      sc_signal<size_t>   r_cas_to_tgt_rsp_pktid; // Transaction pktid
712
713      // Buffer between CAS fsm and CC_SEND fsm (Update/Invalidate L1 caches)
714      sc_signal<bool>     r_cas_to_cc_send_multi_req;     // valid request
715      sc_signal<bool>     r_cas_to_cc_send_brdcast_req;   // brdcast request
716      sc_signal<addr_t>   r_cas_to_cc_send_nline;         // cache line index
717      sc_signal<size_t>   r_cas_to_cc_send_trdid;         // index in Update Table
718      sc_signal<data_t>   r_cas_to_cc_send_wdata;         // data (one word)
719      sc_signal<bool>     r_cas_to_cc_send_is_long;       // it is a 64 bits CAS
720      sc_signal<data_t>   r_cas_to_cc_send_wdata_high;    // data high (one word)
721      sc_signal<size_t>   r_cas_to_cc_send_index;         // index of the word in line
722      GenericFifo<bool>   m_cas_to_cc_send_inst_fifo;     // fifo for the L1 type
723      GenericFifo<size_t> m_cas_to_cc_send_srcid_fifo;    // fifo for srcids
724
725#if L1_MULTI_CACHE
726      GenericFifo<size_t> m_cas_to_cc_send_cache_id_fifo; // fifo for srcids
727#endif
728
729      ////////////////////////////////////////////////////
730      // Registers controlled by the IXR_RSP fsm
731      ////////////////////////////////////////////////////
732
733      sc_signal<int>      r_ixr_rsp_fsm;       // FSM state
734      sc_signal<size_t>   r_ixr_rsp_trt_index; // TRT entry index
735      sc_signal<size_t>   r_ixr_rsp_cpt;       // word counter
736
737      // Buffer between IXR_RSP fsm and XRAM_RSP fsm  (response from the XRAM)
738      sc_signal<bool>   * r_ixr_rsp_to_xram_rsp_rok; // A xram response is ready
739
740      ////////////////////////////////////////////////////
741      // Registers controlled by the XRAM_RSP fsm
742      ////////////////////////////////////////////////////
743
744      sc_signal<int>      r_xram_rsp_fsm;               // FSM state
745      sc_signal<size_t>   r_xram_rsp_trt_index;         // TRT entry index
746      TransactionTabEntry r_xram_rsp_trt_buf;           // TRT entry local buffer
747      sc_signal<bool>     r_xram_rsp_victim_inval;      // victim line invalidate
748      sc_signal<bool>     r_xram_rsp_victim_is_cnt;     // victim line inst bit
749      sc_signal<bool>     r_xram_rsp_victim_dirty;      // victim line dirty bit
750      sc_signal<size_t>   r_xram_rsp_victim_way;        // victim line way
751      sc_signal<size_t>   r_xram_rsp_victim_set;        // victim line set
752      sc_signal<addr_t>   r_xram_rsp_victim_nline;      // victim line index
753      sc_signal<copy_t>   r_xram_rsp_victim_copy;       // victim line first copy
754      sc_signal<copy_t>   r_xram_rsp_victim_copy_cache; // victim line first copy
755      sc_signal<bool>     r_xram_rsp_victim_copy_inst;  // victim line type of first copy
756      sc_signal<size_t>   r_xram_rsp_victim_count;      // victim line number of copies
757      sc_signal<size_t>   r_xram_rsp_victim_ptr;        // victim line pointer to the heap
758      sc_signal<data_t> * r_xram_rsp_victim_data;       // victim line data
759      sc_signal<size_t>   r_xram_rsp_upt_index;         // UPT entry index
760      sc_signal<size_t>   r_xram_rsp_next_ptr;          // Next pointer to the heap
761
762      // Buffer between XRAM_RSP fsm and TGT_RSP fsm  (response to L1 cache)
763      sc_signal<bool>     r_xram_rsp_to_tgt_rsp_req;    // Valid request
764      sc_signal<size_t>   r_xram_rsp_to_tgt_rsp_srcid;  // Transaction srcid
765      sc_signal<size_t>   r_xram_rsp_to_tgt_rsp_trdid;  // Transaction trdid
766      sc_signal<size_t>   r_xram_rsp_to_tgt_rsp_pktid;  // Transaction pktid
767      sc_signal<data_t> * r_xram_rsp_to_tgt_rsp_data;   // data (one cache line)
768      sc_signal<size_t>   r_xram_rsp_to_tgt_rsp_word;   // first word index
769      sc_signal<size_t>   r_xram_rsp_to_tgt_rsp_length; // length of the response
770      sc_signal<bool>     r_xram_rsp_to_tgt_rsp_rerror; // send error to requester
771      sc_signal<addr_t>   r_xram_rsp_to_tgt_rsp_ll_key; // LL key from llsc_global_table
772
773      // Buffer between XRAM_RSP fsm and CC_SEND fsm (Inval L1 Caches)
774      sc_signal<bool>     r_xram_rsp_to_cc_send_multi_req;     // Valid request
775      sc_signal<bool>     r_xram_rsp_to_cc_send_brdcast_req;   // Broadcast request
776      sc_signal<addr_t>   r_xram_rsp_to_cc_send_nline;         // cache line index;
777      sc_signal<size_t>   r_xram_rsp_to_cc_send_trdid;         // index of UPT entry
778      GenericFifo<bool>   m_xram_rsp_to_cc_send_inst_fifo;     // fifo for the L1 type
779      GenericFifo<size_t> m_xram_rsp_to_cc_send_srcid_fifo;    // fifo for srcids
780
781#if L1_MULTI_CACHE
782      GenericFifo<size_t> m_xram_rsp_to_cc_send_cache_id_fifo; // fifo for srcids
783#endif
784
785      // Buffer between XRAM_RSP fsm and IXR_CMD fsm (XRAM write)
786      sc_signal<bool>     r_xram_rsp_to_ixr_cmd_req;   // Valid request
787      sc_signal<addr_t>   r_xram_rsp_to_ixr_cmd_nline; // cache line index
788      sc_signal<data_t> * r_xram_rsp_to_ixr_cmd_data;  // cache line data
789      sc_signal<size_t>   r_xram_rsp_to_ixr_cmd_trdid; // index in transaction table
790
791      ////////////////////////////////////////////////////
792      // Registers controlled by the IXR_CMD fsm
793      ////////////////////////////////////////////////////
794
795      sc_signal<int>      r_ixr_cmd_fsm;
796      sc_signal<size_t>   r_ixr_cmd_cpt;
797
798      ////////////////////////////////////////////////////
799      // Registers controlled by TGT_RSP fsm
800      ////////////////////////////////////////////////////
801
802      sc_signal<int>      r_tgt_rsp_fsm;
803      sc_signal<size_t>   r_tgt_rsp_cpt;
804      sc_signal<bool>     r_tgt_rsp_key_sent;
805
806      ////////////////////////////////////////////////////
807      // Registers controlled by CC_SEND fsm
808      ////////////////////////////////////////////////////
809
810      sc_signal<int>      r_cc_send_fsm;
811      sc_signal<size_t>   r_cc_send_cpt;
812      sc_signal<bool>     r_cc_send_inst;
813
814      ////////////////////////////////////////////////////
815      // Registers controlled by CC_RECEIVE fsm
816      ////////////////////////////////////////////////////
817
818      sc_signal<int>      r_cc_receive_fsm;
819
820      ////////////////////////////////////////////////////
821      // Registers controlled by ALLOC_DIR fsm
822      ////////////////////////////////////////////////////
823
824      sc_signal<int>      r_alloc_dir_fsm;
825      sc_signal<unsigned> r_alloc_dir_reset_cpt;
826
827      ////////////////////////////////////////////////////
828      // Registers controlled by ALLOC_TRT fsm
829      ////////////////////////////////////////////////////
830
831      sc_signal<int>      r_alloc_trt_fsm;
832
833      ////////////////////////////////////////////////////
834      // Registers controlled by ALLOC_UPT fsm
835      ////////////////////////////////////////////////////
836
837      sc_signal<int>      r_alloc_upt_fsm;
838
839      ////////////////////////////////////////////////////
840      // Registers controlled by ALLOC_HEAP fsm
841      ////////////////////////////////////////////////////
842
843      sc_signal<int>      r_alloc_heap_fsm;
844      sc_signal<unsigned> r_alloc_heap_reset_cpt;
845    }; // end class VciMemCache
846
847}}
848
849#endif
850
851// Local Variables:
852// tab-width: 2
853// c-basic-offset: 2
854// c-file-offsets:((innamespace . 0)(inline-open . 0))
855// indent-tabs-mode: nil
856// End:
857
858// vim: filetype=cpp:expandtab:shiftwidth=2:tabstop=2:softtabstop=2
859
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