source: trunk/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h @ 430

Last change on this file since 430 was 430, checked in by cfuguet, 11 years ago

Modifications in vci_mem_cache:

  • Adding error treatment for segmentation violation in memory cache. The assert was replaced by a VCI error response to the faulty commmand initiator.

To do so, a communication buffer have been introduced between the
TGT_CMD FSM and the TGT_RSP FSM. The TGT_CMD FSM makes the
segmentation violation verification and if one is detected, the
TGT_CMD FSM makes a request to the TGT_RSP FSM.

File size: 36.3 KB
Line 
1/* -*- c++ -*-
2 * File         : vci_mem_cache.h
3 * Date         : 26/10/2008
4 * Copyright    : UPMC / LIP6
5 * Authors      : Alain Greiner / Eric Guthmuller
6 *
7 * SOCLIB_LGPL_HEADER_BEGIN
8 *
9 * This file is part of SoCLib, GNU LGPLv2.1.
10 *
11 * SoCLib is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU Lesser General Public License as published
13 * by the Free Software Foundation; version 2.1 of the License.
14 *
15 * SoCLib is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
18 * Lesser General Public License for more details.
19 *
20 * You should have received a copy of the GNU Lesser General Public
21 * License along with SoCLib; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
23 * 02110-1301 USA
24 *
25 * SOCLIB_LGPL_HEADER_END
26 *
27 * Maintainers: alain eric.guthmuller@polytechnique.edu
28 *              cesar.fuguet-tortolero@lip6.fr
29 *              alexandre.joannou@lip6.fr
30 */
31
32#ifndef SOCLIB_CABA_MEM_CACHE_H
33#define SOCLIB_CABA_MEM_CACHE_H
34
35#include <inttypes.h>
36#include <systemc>
37#include <list>
38#include <cassert>
39#include "arithmetics.h"
40#include "alloc_elems.h"
41#include "caba_base_module.h"
42#include "vci_target.h"
43#include "vci_initiator.h"
44#include "generic_fifo.h"
45#include "mapping_table.h"
46#include "int_tab.h"
47#include "generic_llsc_global_table.h"
48#include "mem_cache_directory.h"
49#include "xram_transaction.h"
50#include "update_tab.h"
51#include "dspin_interface.h"
52#include "dspin_dhccp_param.h"
53
54#define TRT_ENTRIES      4      // Number of entries in TRT
55#define UPT_ENTRIES      4      // Number of entries in UPT
56#define HEAP_ENTRIES     1024   // Number of entries in HEAP
57
58namespace soclib {  namespace caba {
59
60  using namespace sc_core;
61
62  template<typename vci_param_int, 
63           typename vci_param_ext,
64           size_t   dspin_in_width,
65           size_t   dspin_out_width>
66    class VciMemCache
67    : public soclib::caba::BaseModule
68    {
69      typedef typename vci_param_int::fast_addr_t  addr_t;
70
71      typedef typename sc_dt::sc_uint<64>          wide_data_t;
72
73      typedef uint32_t data_t;
74      typedef uint32_t tag_t;
75      typedef uint32_t be_t;
76      typedef uint32_t copy_t;
77
78      /* States of the TGT_CMD fsm */
79      enum tgt_cmd_fsm_state_e{
80        TGT_CMD_IDLE,
81        TGT_CMD_ERROR,
82        TGT_CMD_READ,
83        TGT_CMD_WRITE,
84        TGT_CMD_CAS
85      };
86
87      /* States of the TGT_RSP fsm */
88      enum tgt_rsp_fsm_state_e
89      {
90        TGT_RSP_TGT_CMD_IDLE,
91        TGT_RSP_READ_IDLE,
92        TGT_RSP_WRITE_IDLE,
93        TGT_RSP_CAS_IDLE,
94        TGT_RSP_XRAM_IDLE,
95        TGT_RSP_MULTI_ACK_IDLE,
96        TGT_RSP_CLEANUP_IDLE,
97        TGT_RSP_TGT_CMD,
98        TGT_RSP_READ,
99        TGT_RSP_WRITE,
100        TGT_RSP_CAS,
101        TGT_RSP_XRAM,
102        TGT_RSP_MULTI_ACK,
103        TGT_RSP_CLEANUP
104      };
105
106      /* States of the DSPIN_TGT fsm */
107      enum cc_receive_fsm_state_e
108      {
109        CC_RECEIVE_IDLE,
110        CC_RECEIVE_CLEANUP,
111        CC_RECEIVE_CLEANUP_EOP,
112        CC_RECEIVE_MULTI_ACK
113      };
114
115      /* States of the CC_SEND fsm */
116      enum cc_send_fsm_state_e
117      {
118        CC_SEND_XRAM_RSP_IDLE,
119        CC_SEND_WRITE_IDLE,
120        CC_SEND_CAS_IDLE,
121        CC_SEND_CLEANUP_IDLE,
122        CC_SEND_CLEANUP_ACK,
123        CC_SEND_XRAM_RSP_BRDCAST_HEADER,
124        CC_SEND_XRAM_RSP_BRDCAST_NLINE,
125        CC_SEND_XRAM_RSP_INVAL_HEADER,
126        CC_SEND_XRAM_RSP_INVAL_NLINE,
127        CC_SEND_WRITE_BRDCAST_HEADER,
128        CC_SEND_WRITE_BRDCAST_NLINE,
129        CC_SEND_WRITE_UPDT_HEADER,
130        CC_SEND_WRITE_UPDT_NLINE,
131        CC_SEND_WRITE_UPDT_DATA,
132        CC_SEND_CAS_BRDCAST_HEADER,
133        CC_SEND_CAS_BRDCAST_NLINE,
134        CC_SEND_CAS_UPDT_HEADER,
135        CC_SEND_CAS_UPDT_NLINE,
136        CC_SEND_CAS_UPDT_DATA,
137        CC_SEND_CAS_UPDT_DATA_HIGH
138      };
139
140      /* States of the MULTI_ACK fsm */
141      enum multi_ack_fsm_state_e
142      {
143        MULTI_ACK_IDLE,
144        MULTI_ACK_UPT_LOCK,
145        MULTI_ACK_UPT_CLEAR,
146        MULTI_ACK_WRITE_RSP
147      };
148
149      /* States of the READ fsm */
150      enum read_fsm_state_e
151      {
152        READ_IDLE,
153        READ_DIR_REQ,
154        READ_DIR_LOCK,
155        READ_DIR_HIT,
156        READ_HEAP_REQ,
157        READ_HEAP_LOCK,
158        READ_HEAP_WRITE,
159        READ_HEAP_ERASE,
160        READ_HEAP_LAST,
161        READ_RSP,
162        READ_TRT_LOCK,
163        READ_TRT_SET,
164        READ_TRT_REQ
165      };
166
167      /* States of the WRITE fsm */
168      enum write_fsm_state_e
169      {
170        WRITE_IDLE,
171        WRITE_NEXT,
172        WRITE_DIR_REQ,
173        WRITE_DIR_LOCK,
174        WRITE_DIR_READ,
175        WRITE_DIR_HIT,
176        WRITE_UPT_LOCK,
177        WRITE_UPT_HEAP_LOCK,
178        WRITE_UPT_REQ,
179        WRITE_UPT_NEXT,
180        WRITE_UPT_DEC,
181        WRITE_RSP,
182        WRITE_MISS_TRT_LOCK,
183        WRITE_MISS_TRT_DATA,
184        WRITE_MISS_TRT_SET,
185        WRITE_MISS_XRAM_REQ,
186        WRITE_BC_TRT_LOCK,
187        WRITE_BC_UPT_LOCK,
188        WRITE_BC_DIR_INVAL,
189        WRITE_BC_CC_SEND,
190        WRITE_BC_XRAM_REQ,
191        WRITE_WAIT
192      };
193
194      /* States of the IXR_RSP fsm */
195      enum ixr_rsp_fsm_state_e
196      {
197        IXR_RSP_IDLE,
198        IXR_RSP_ACK,
199        IXR_RSP_TRT_ERASE,
200        IXR_RSP_TRT_READ
201      };
202
203      /* States of the XRAM_RSP fsm */
204      enum xram_rsp_fsm_state_e
205      {
206        XRAM_RSP_IDLE,
207        XRAM_RSP_TRT_COPY,
208        XRAM_RSP_TRT_DIRTY,
209        XRAM_RSP_DIR_LOCK,
210        XRAM_RSP_DIR_UPDT,
211        XRAM_RSP_DIR_RSP,
212        XRAM_RSP_INVAL_LOCK,
213        XRAM_RSP_INVAL_WAIT,
214        XRAM_RSP_INVAL,
215        XRAM_RSP_WRITE_DIRTY,
216        XRAM_RSP_HEAP_REQ,
217        XRAM_RSP_HEAP_ERASE,
218        XRAM_RSP_HEAP_LAST,
219        XRAM_RSP_ERROR_ERASE,
220        XRAM_RSP_ERROR_RSP
221      };
222
223      /* States of the IXR_CMD fsm */
224      enum ixr_cmd_fsm_state_e
225      {
226        IXR_CMD_READ_IDLE,
227        IXR_CMD_WRITE_IDLE,
228        IXR_CMD_CAS_IDLE,
229        IXR_CMD_XRAM_IDLE,
230        IXR_CMD_READ,
231        IXR_CMD_WRITE,
232        IXR_CMD_CAS,
233        IXR_CMD_XRAM
234      };
235
236      /* States of the CAS fsm */
237      enum cas_fsm_state_e
238      {
239        CAS_IDLE,
240        CAS_DIR_REQ,
241        CAS_DIR_LOCK,
242        CAS_DIR_HIT_READ,
243        CAS_DIR_HIT_COMPARE,
244        CAS_DIR_HIT_WRITE,
245        CAS_UPT_LOCK,
246        CAS_UPT_HEAP_LOCK,
247        CAS_UPT_REQ,
248        CAS_UPT_NEXT,
249        CAS_BC_TRT_LOCK,
250        CAS_BC_UPT_LOCK,
251        CAS_BC_DIR_INVAL,
252        CAS_BC_CC_SEND,
253        CAS_BC_XRAM_REQ,
254        CAS_RSP_FAIL,
255        CAS_RSP_SUCCESS,
256        CAS_MISS_TRT_LOCK,
257        CAS_MISS_TRT_SET,
258        CAS_MISS_XRAM_REQ,
259        CAS_WAIT
260      };
261
262      /* States of the CLEANUP fsm */
263      enum cleanup_fsm_state_e
264      {
265        CLEANUP_IDLE,
266        CLEANUP_GET_NLINE,
267        CLEANUP_DIR_REQ,
268        CLEANUP_DIR_LOCK,
269        CLEANUP_DIR_WRITE,
270        CLEANUP_HEAP_REQ,
271        CLEANUP_HEAP_LOCK,
272        CLEANUP_HEAP_SEARCH,
273        CLEANUP_HEAP_CLEAN,
274        CLEANUP_HEAP_FREE,
275        CLEANUP_UPT_LOCK,
276        CLEANUP_UPT_DECREMENT,
277        CLEANUP_UPT_CLEAR,
278        CLEANUP_WRITE_RSP,
279        CLEANUP_SEND_ACK
280      };
281
282      /* States of the ALLOC_DIR fsm */
283      enum alloc_dir_fsm_state_e
284      {
285        ALLOC_DIR_RESET,
286        ALLOC_DIR_READ,
287        ALLOC_DIR_WRITE,
288        ALLOC_DIR_CAS,
289        ALLOC_DIR_CLEANUP,
290        ALLOC_DIR_XRAM_RSP
291      };
292
293      /* States of the ALLOC_TRT fsm */
294      enum alloc_trt_fsm_state_e
295      {
296        ALLOC_TRT_READ,
297        ALLOC_TRT_WRITE,
298        ALLOC_TRT_CAS,
299        ALLOC_TRT_XRAM_RSP,
300        ALLOC_TRT_IXR_RSP
301      };
302
303      /* States of the ALLOC_UPT fsm */
304      enum alloc_upt_fsm_state_e
305      {
306        ALLOC_UPT_WRITE,
307        ALLOC_UPT_XRAM_RSP,
308        ALLOC_UPT_MULTI_ACK,
309        ALLOC_UPT_CLEANUP,
310        ALLOC_UPT_CAS
311      };
312
313      /* States of the ALLOC_HEAP fsm */
314      enum alloc_heap_fsm_state_e
315      {
316        ALLOC_HEAP_RESET,
317        ALLOC_HEAP_READ,
318        ALLOC_HEAP_WRITE,
319        ALLOC_HEAP_CAS,
320        ALLOC_HEAP_CLEANUP,
321        ALLOC_HEAP_XRAM_RSP
322      };
323
324      /* transaction type, pktid field */
325      enum transaction_type_e
326      {
327          // b3 unused
328          // b2 READ / NOT READ
329          // Si READ
330          //  b1 DATA / INS
331          //  b0 UNC / MISS
332          // Si NOT READ
333          //  b1 accÚs table llsc type SW / other
334          //  b2 WRITE/CAS/LL/SC
335          TYPE_READ_DATA_UNC          = 0x0,
336          TYPE_READ_DATA_MISS         = 0x1,
337          TYPE_READ_INS_UNC           = 0x2,
338          TYPE_READ_INS_MISS          = 0x3,
339          TYPE_WRITE                  = 0x4,
340          TYPE_CAS                    = 0x5,
341          TYPE_LL                     = 0x6,
342          TYPE_SC                     = 0x7
343      };
344
345      /* SC return values */
346      enum sc_status_type_e
347      {
348          SC_SUCCESS  =   0x00000000,
349          SC_FAIL     =   0x00000001
350      };
351
352      // debug variables (for each FSM)
353      bool         m_debug_global;
354      bool         m_debug_tgt_cmd_fsm;
355      bool         m_debug_tgt_rsp_fsm;
356      bool         m_debug_cc_send_fsm;
357      bool         m_debug_cc_receive_fsm;
358      bool         m_debug_multi_ack_fsm;
359      bool         m_debug_read_fsm;
360      bool         m_debug_write_fsm;
361      bool         m_debug_cas_fsm;
362      bool         m_debug_cleanup_fsm;
363      bool         m_debug_ixr_cmd_fsm;
364      bool         m_debug_ixr_rsp_fsm;
365      bool         m_debug_xram_rsp_fsm;
366      bool         m_debug_previous_hit;
367      size_t       m_debug_previous_count;
368
369      bool         m_monitor_ok;
370      addr_t       m_monitor_base;
371      addr_t       m_monitor_length;
372
373      // instrumentation counters
374      uint32_t     m_cpt_cycles;        // Counter of cycles
375      uint32_t     m_cpt_read;          // Number of READ transactions
376      uint32_t     m_cpt_read_miss;     // Number of MISS READ
377      uint32_t     m_cpt_write;         // Number of WRITE transactions
378      uint32_t     m_cpt_write_miss;    // Number of MISS WRITE
379      uint32_t     m_cpt_write_cells;   // Cumulated length for WRITE transactions
380      uint32_t     m_cpt_write_dirty;   // Cumulated length for WRITE transactions
381      uint32_t     m_cpt_update;        // Number of UPDATE transactions
382      uint32_t     m_cpt_trt_rb;        // Read blocked by a hit in trt
383      uint32_t     m_cpt_trt_full;      // Transaction blocked due to a full trt
384      uint32_t     m_cpt_update_mult;   // Number of targets for UPDATE
385      uint32_t     m_cpt_inval;         // Number of INVAL  transactions
386      uint32_t     m_cpt_inval_mult;    // Number of targets for INVAL
387      uint32_t     m_cpt_inval_brdcast; // Number of BROADCAST INVAL
388      uint32_t     m_cpt_cleanup;       // Number of CLEANUP transactions
389      uint32_t     m_cpt_ll;            // Number of LL transactions
390      uint32_t     m_cpt_sc;            // Number of SC transactions
391      uint32_t     m_cpt_cas;           // Number of CAS transactions
392
393      size_t       m_prev_count;
394
395      protected:
396
397      SC_HAS_PROCESS(VciMemCache);
398
399      public:
400      sc_in<bool>                                 p_clk;
401      sc_in<bool>                                 p_resetn;
402      soclib::caba::VciTarget<vci_param_int>      p_vci_tgt;
403      soclib::caba::VciInitiator<vci_param_ext>   p_vci_ixr;
404      soclib::caba::DspinInput<dspin_in_width>    p_dspin_in;
405      soclib::caba::DspinOutput<dspin_out_width>  p_dspin_out;
406
407      VciMemCache(
408          sc_module_name name,                                // Instance Name
409          const soclib::common::MappingTable &mtp,            // Mapping table direct network
410          const soclib::common::MappingTable &mtx,            // Mapping table external network
411          const soclib::common::IntTab       &srcid_x,        // global index on external network
412          const soclib::common::IntTab       &tgtid_d,        // global index on direct network
413          const size_t                       cc_global_id,    // global index on cc network
414          const size_t                       nways,           // Number of ways per set
415          const size_t                       nsets,           // Number of sets
416          const size_t                       nwords,          // Number of words per line
417          const size_t                       max_copies,      // max number of copies in heap
418          const size_t                       heap_size=HEAP_ENTRIES,
419          const size_t                       trt_lines=TRT_ENTRIES, 
420          const size_t                       upt_lines=UPT_ENTRIES,     
421          const size_t                       debug_start_cycle=0,
422          const bool                         debug_ok=false );
423
424      ~VciMemCache();
425
426      void print_stats();
427      void print_trace();
428      void copies_monitor(addr_t addr);
429      void start_monitor(addr_t addr, addr_t length);
430      void stop_monitor();
431
432      private:
433
434      void transition();
435      void genMoore();
436      void check_monitor( const char *buf, addr_t addr, data_t data, bool read);
437
438      // Component attributes
439      std::list<soclib::common::Segment> m_seglist;          // segments allocated to memcache
440      size_t                             m_nseg;             // number of segments
441      soclib::common::Segment            **m_seg;            // array of segments pointers
442      const size_t                       m_srcid_x;          // global index on external network
443      const size_t                       m_initiators;       // Number of initiators
444      const size_t                       m_heap_size;        // Size of the heap
445      const size_t                       m_ways;             // Number of ways in a set
446      const size_t                       m_sets;             // Number of cache sets
447      const size_t                       m_words;            // Number of words in a line
448      const size_t                       m_cc_global_id;     // global_index on cc network
449      size_t                             m_debug_start_cycle;
450      bool                               m_debug_ok;
451      uint32_t                           m_trt_lines;
452      TransactionTab                     m_trt;              // xram transaction table
453      uint32_t                           m_upt_lines;
454      UpdateTab                          m_upt;              // pending update & invalidate
455      CacheDirectory                     m_cache_directory;  // data cache directory
456      CacheData                          m_cache_data;       // data array[set][way][word]
457      HeapDirectory                      m_heap;             // heap for copies
458      size_t                             m_max_copies;       // max number of copies in heap
459      GenericLLSCGlobalTable
460      < 32  ,                              // number of slots
461        4096,                              // number of processors in the system
462        8000,                              // registration life (# of LL operations)
463        addr_t >  m_llsc_table;            // ll/sc global registration table
464
465      // adress masks
466      const soclib::common::AddressMaskingTable<addr_t>   m_x;
467      const soclib::common::AddressMaskingTable<addr_t>   m_y;
468      const soclib::common::AddressMaskingTable<addr_t>   m_z;
469      const soclib::common::AddressMaskingTable<addr_t>   m_nline;
470
471      // broadcast address
472      uint32_t                           m_broadcast_boundaries;
473
474      //////////////////////////////////////////////////
475      // Registers controlled by the TGT_CMD fsm
476      //////////////////////////////////////////////////
477
478      sc_signal<int>         r_tgt_cmd_fsm;
479
480      // Fifo between TGT_CMD fsm and READ fsm
481      GenericFifo<addr_t>    m_cmd_read_addr_fifo;
482      GenericFifo<size_t>    m_cmd_read_length_fifo;
483      GenericFifo<size_t>    m_cmd_read_srcid_fifo;
484      GenericFifo<size_t>    m_cmd_read_trdid_fifo;
485      GenericFifo<size_t>    m_cmd_read_pktid_fifo;
486
487      // Fifo between TGT_CMD fsm and WRITE fsm
488      GenericFifo<addr_t>    m_cmd_write_addr_fifo;
489      GenericFifo<bool>      m_cmd_write_eop_fifo;
490      GenericFifo<size_t>    m_cmd_write_srcid_fifo;
491      GenericFifo<size_t>    m_cmd_write_trdid_fifo;
492      GenericFifo<size_t>    m_cmd_write_pktid_fifo;
493      GenericFifo<data_t>    m_cmd_write_data_fifo;
494      GenericFifo<be_t>      m_cmd_write_be_fifo;
495
496      // Fifo between TGT_CMD fsm and CAS fsm
497      GenericFifo<addr_t>    m_cmd_cas_addr_fifo;
498      GenericFifo<bool>      m_cmd_cas_eop_fifo;
499      GenericFifo<size_t>    m_cmd_cas_srcid_fifo;
500      GenericFifo<size_t>    m_cmd_cas_trdid_fifo;
501      GenericFifo<size_t>    m_cmd_cas_pktid_fifo;
502      GenericFifo<data_t>    m_cmd_cas_wdata_fifo;
503
504      // Fifo between CC_RECEIVE fsm and CLEANUP fsm
505      GenericFifo<uint64_t>  m_cc_receive_to_cleanup_fifo;
506     
507      // Fifo between CC_RECEIVE fsm and MULTI_ACK fsm
508      GenericFifo<uint64_t>  m_cc_receive_to_multi_ack_fifo;
509
510      // Buffer between TGT_CMD fsm and TGT_RSP fsm
511      // (segmentation violation response request)
512      sc_signal<bool>     r_tgt_cmd_to_tgt_rsp_req;
513      sc_signal<size_t>   r_tgt_cmd_to_tgt_rsp_srcid;
514      sc_signal<size_t>   r_tgt_cmd_to_tgt_rsp_trdid;
515      sc_signal<size_t>   r_tgt_cmd_to_tgt_rsp_pktid;
516
517      ///////////////////////////////////////////////////////
518      // Registers controlled by the READ fsm
519      ///////////////////////////////////////////////////////
520
521      sc_signal<int>      r_read_fsm;        // FSM state
522      sc_signal<size_t>   r_read_copy;       // Srcid of the first copy
523      sc_signal<size_t>   r_read_copy_cache; // Srcid of the first copy
524      sc_signal<bool>     r_read_copy_inst;  // Type of the first copy
525      sc_signal<tag_t>    r_read_tag;        // cache line tag (in directory)
526      sc_signal<bool>     r_read_is_cnt;     // is_cnt bit (in directory)
527      sc_signal<bool>     r_read_lock;       // lock bit (in directory)
528      sc_signal<bool>     r_read_dirty;      // dirty bit (in directory)
529      sc_signal<size_t>   r_read_count;      // number of copies
530      sc_signal<size_t>   r_read_ptr;        // pointer to the heap
531      sc_signal<data_t> * r_read_data;       // data (one cache line)
532      sc_signal<size_t>   r_read_way;        // associative way (in cache)
533      sc_signal<size_t>   r_read_trt_index;  // Transaction Table index
534      sc_signal<size_t>   r_read_next_ptr;   // Next entry to point to
535      sc_signal<bool>     r_read_last_free;  // Last free entry
536      sc_signal<addr_t>   r_read_ll_key;     // LL key from the llsc_global_table
537
538      // Buffer between READ fsm and IXR_CMD fsm (ask a missing cache line to XRAM)
539      sc_signal<bool>     r_read_to_ixr_cmd_req;    // valid request
540      sc_signal<addr_t>   r_read_to_ixr_cmd_nline;  // cache line index
541      sc_signal<size_t>   r_read_to_ixr_cmd_trdid;  // index in Transaction Table
542
543      // Buffer between READ fsm and TGT_RSP fsm (send a hit read response to L1 cache)
544      sc_signal<bool>     r_read_to_tgt_rsp_req;    // valid request
545      sc_signal<size_t>   r_read_to_tgt_rsp_srcid;  // Transaction srcid
546      sc_signal<size_t>   r_read_to_tgt_rsp_trdid;  // Transaction trdid
547      sc_signal<size_t>   r_read_to_tgt_rsp_pktid;  // Transaction pktid
548      sc_signal<data_t> * r_read_to_tgt_rsp_data;   // data (one cache line)
549      sc_signal<size_t>   r_read_to_tgt_rsp_word;   // first word of the response
550      sc_signal<size_t>   r_read_to_tgt_rsp_length; // length of the response
551      sc_signal<addr_t>   r_read_to_tgt_rsp_ll_key; // LL key from the llsc_global_table
552
553      ///////////////////////////////////////////////////////////////
554      // Registers controlled by the WRITE fsm
555      ///////////////////////////////////////////////////////////////
556
557      sc_signal<int>      r_write_fsm;        // FSM state
558      sc_signal<addr_t>   r_write_address;    // first word address
559      sc_signal<size_t>   r_write_word_index; // first word index in line
560      sc_signal<size_t>   r_write_word_count; // number of words in line
561      sc_signal<size_t>   r_write_srcid;      // transaction srcid
562      sc_signal<size_t>   r_write_trdid;      // transaction trdid
563      sc_signal<size_t>   r_write_pktid;      // transaction pktid
564      sc_signal<data_t> * r_write_data;       // data (one cache line)
565      sc_signal<be_t>   * r_write_be;         // one byte enable per word
566      sc_signal<bool>     r_write_byte;       // (BE != 0X0) and (BE != 0xF)
567      sc_signal<bool>     r_write_is_cnt;     // is_cnt bit (in directory)
568      sc_signal<bool>     r_write_lock;       // lock bit (in directory)
569      sc_signal<tag_t>    r_write_tag;        // cache line tag (in directory)
570      sc_signal<size_t>   r_write_copy;       // first owner of the line
571      sc_signal<size_t>   r_write_copy_cache; // first owner of the line
572      sc_signal<bool>     r_write_copy_inst;  // is this owner a ICache ?
573      sc_signal<size_t>   r_write_count;      // number of copies
574      sc_signal<size_t>   r_write_ptr;        // pointer to the heap
575      sc_signal<size_t>   r_write_next_ptr;   // next pointer to the heap
576      sc_signal<bool>     r_write_to_dec;     // need to decrement update counter
577      sc_signal<size_t>   r_write_way;        // way of the line
578      sc_signal<size_t>   r_write_trt_index;  // index in Transaction Table
579      sc_signal<size_t>   r_write_upt_index;  // index in Update Table
580      sc_signal<bool>     r_write_sc_fail;    // sc command failed
581      sc_signal<bool>     r_write_pending_sc; // sc command pending
582
583      // Buffer between WRITE fsm and TGT_RSP fsm (acknowledge a write command from L1)
584      sc_signal<bool>     r_write_to_tgt_rsp_req;     // valid request
585      sc_signal<size_t>   r_write_to_tgt_rsp_srcid;   // transaction srcid
586      sc_signal<size_t>   r_write_to_tgt_rsp_trdid;   // transaction trdid
587      sc_signal<size_t>   r_write_to_tgt_rsp_pktid;   // transaction pktid
588      sc_signal<bool>     r_write_to_tgt_rsp_sc_fail; // sc command failed
589
590      // Buffer between WRITE fsm and IXR_CMD fsm (ask a missing cache line to XRAM)
591      sc_signal<bool>     r_write_to_ixr_cmd_req;   // valid request
592      sc_signal<bool>     r_write_to_ixr_cmd_write; // write request
593      sc_signal<addr_t>   r_write_to_ixr_cmd_nline; // cache line index
594      sc_signal<data_t> * r_write_to_ixr_cmd_data;  // cache line data
595      sc_signal<size_t>   r_write_to_ixr_cmd_trdid; // index in Transaction Table
596
597      // Buffer between WRITE fsm and CC_SEND fsm (Update/Invalidate L1 caches)
598      sc_signal<bool>     r_write_to_cc_send_multi_req;     // valid multicast request
599      sc_signal<bool>     r_write_to_cc_send_brdcast_req;   // valid brdcast request
600      sc_signal<addr_t>   r_write_to_cc_send_nline;         // cache line index
601      sc_signal<size_t>   r_write_to_cc_send_trdid;         // index in Update Table
602      sc_signal<data_t> * r_write_to_cc_send_data;          // data (one cache line)
603      sc_signal<be_t>   * r_write_to_cc_send_be;            // word enable
604      sc_signal<size_t>   r_write_to_cc_send_count;         // number of words in line
605      sc_signal<size_t>   r_write_to_cc_send_index;         // index of first word in line
606      GenericFifo<bool>   m_write_to_cc_send_inst_fifo;     // fifo for the L1 type
607      GenericFifo<size_t> m_write_to_cc_send_srcid_fifo;    // fifo for srcids
608
609#if L1_MULTI_CACHE
610      GenericFifo<size_t> m_write_to_cc_send_cache_id_fifo; // fifo for srcids
611#endif
612
613      // Buffer between WRITE fsm and MULTI_ACK fsm (Decrement UPT entry)
614      sc_signal<bool>     r_write_to_multi_ack_req;       // valid request
615      sc_signal<size_t>   r_write_to_multi_ack_upt_index; // index in update table
616
617      /////////////////////////////////////////////////////////
618      // Registers controlled by MULTI_ACK fsm
619      //////////////////////////////////////////////////////////
620
621      sc_signal<int>      r_multi_ack_fsm;       // FSM state
622      sc_signal<size_t>   r_multi_ack_upt_index; // index in the Update Table
623      sc_signal<size_t>   r_multi_ack_srcid;     // pending write srcid
624      sc_signal<size_t>   r_multi_ack_trdid;     // pending write trdid
625      sc_signal<size_t>   r_multi_ack_pktid;     // pending write pktid
626      sc_signal<addr_t>   r_multi_ack_nline;     // pending write nline
627
628      // Buffer between MULTI_ACK fsm and TGT_RSP fsm (complete write/update transaction)
629      sc_signal<bool>     r_multi_ack_to_tgt_rsp_req;   // valid request
630      sc_signal<size_t>   r_multi_ack_to_tgt_rsp_srcid; // Transaction srcid
631      sc_signal<size_t>   r_multi_ack_to_tgt_rsp_trdid; // Transaction trdid
632      sc_signal<size_t>   r_multi_ack_to_tgt_rsp_pktid; // Transaction pktid
633
634      ///////////////////////////////////////////////////////
635      // Registers controlled by CLEANUP fsm
636      ///////////////////////////////////////////////////////
637
638      sc_signal<int>      r_cleanup_fsm;           // FSM state
639      sc_signal<size_t>   r_cleanup_srcid;         // transaction srcid
640      sc_signal<bool>     r_cleanup_inst;          // Instruction or Data ?
641      sc_signal<size_t>   r_cleanup_way_index;     // L1 Cache Way index
642      sc_signal<addr_t>   r_cleanup_nline;         // cache line index
643
644#if L1_MULTI_CACHE
645      sc_signal<size_t>   r_cleanup_pktid;         // transaction pktid
646#endif
647
648      sc_signal<copy_t>   r_cleanup_copy;          // first copy
649      sc_signal<copy_t>   r_cleanup_copy_cache;    // first copy
650      sc_signal<size_t>   r_cleanup_copy_inst;     // type of the first copy
651      sc_signal<copy_t>   r_cleanup_count;         // number of copies
652      sc_signal<size_t>   r_cleanup_ptr;           // pointer to the heap
653      sc_signal<size_t>   r_cleanup_prev_ptr;      // previous pointer to the heap
654      sc_signal<size_t>   r_cleanup_prev_srcid;    // srcid of previous heap entry
655      sc_signal<size_t>   r_cleanup_prev_cache_id; // srcid of previous heap entry
656      sc_signal<bool>     r_cleanup_prev_inst;     // inst bit of previous heap entry
657      sc_signal<size_t>   r_cleanup_next_ptr;      // next pointer to the heap
658      sc_signal<tag_t>    r_cleanup_tag;           // cache line tag (in directory)
659      sc_signal<bool>     r_cleanup_is_cnt;        // inst bit (in directory)
660      sc_signal<bool>     r_cleanup_lock;          // lock bit (in directory)
661      sc_signal<bool>     r_cleanup_dirty;         // dirty bit (in directory)
662      sc_signal<size_t>   r_cleanup_way;           // associative way (in cache)
663
664      sc_signal<size_t>   r_cleanup_write_srcid;   // srcid of write response
665      sc_signal<size_t>   r_cleanup_write_trdid;   // trdid of write rsp
666      sc_signal<size_t>   r_cleanup_write_pktid;   // pktid of write rsp
667      sc_signal<bool>     r_cleanup_write_need_rsp;// needs a write rsp
668
669      sc_signal<size_t>   r_cleanup_index;         // index of the INVAL line (in the UPT)
670
671      // Buffer between CLEANUP fsm and TGT_RSP fsm (acknowledge a write command from L1)
672      sc_signal<bool>     r_cleanup_to_tgt_rsp_req;   // valid request
673      sc_signal<size_t>   r_cleanup_to_tgt_rsp_srcid; // transaction srcid
674      sc_signal<size_t>   r_cleanup_to_tgt_rsp_trdid; // transaction trdid
675      sc_signal<size_t>   r_cleanup_to_tgt_rsp_pktid; // transaction pktid
676
677      // Buffer between CLEANUP fsm and CC_SEND fsm (acknowledge a cleanup command from L1)
678      sc_signal<bool>     r_cleanup_to_cc_send_req;       // valid request
679      sc_signal<size_t>   r_cleanup_to_cc_send_srcid;     // L1 srcid
680      sc_signal<size_t>   r_cleanup_to_cc_send_set_index; // L1 set index
681      sc_signal<size_t>   r_cleanup_to_cc_send_way_index; // L1 way index
682      sc_signal<bool>     r_cleanup_to_cc_send_inst;      // Instruction Cleanup Ack
683
684      ///////////////////////////////////////////////////////
685      // Registers controlled by CAS fsm
686      ///////////////////////////////////////////////////////
687
688      sc_signal<int>      r_cas_fsm;        // FSM state
689      sc_signal<data_t>   r_cas_wdata;      // write data word
690      sc_signal<data_t> * r_cas_rdata;      // read data word
691      sc_signal<uint32_t> r_cas_lfsr;       // lfsr for random introducing
692      sc_signal<size_t>   r_cas_cpt;        // size of command
693      sc_signal<copy_t>   r_cas_copy;       // Srcid of the first copy
694      sc_signal<copy_t>   r_cas_copy_cache; // Srcid of the first copy
695      sc_signal<bool>     r_cas_copy_inst;  // Type of the first copy
696      sc_signal<size_t>   r_cas_count;      // number of copies
697      sc_signal<size_t>   r_cas_ptr;        // pointer to the heap
698      sc_signal<size_t>   r_cas_next_ptr;   // next pointer to the heap
699      sc_signal<bool>     r_cas_is_cnt;     // is_cnt bit (in directory)
700      sc_signal<bool>     r_cas_dirty;      // dirty bit (in directory)
701      sc_signal<size_t>   r_cas_way;        // way in directory
702      sc_signal<size_t>   r_cas_set;        // set in directory
703      sc_signal<data_t>   r_cas_tag;        // cache line tag (in directory)
704      sc_signal<size_t>   r_cas_trt_index;  // Transaction Table index
705      sc_signal<size_t>   r_cas_upt_index;  // Update Table index
706      sc_signal<data_t> * r_cas_data;       // cache line data
707
708      // Buffer between CAS fsm and IXR_CMD fsm (XRAM write)
709      sc_signal<bool>     r_cas_to_ixr_cmd_req;   // valid request
710      sc_signal<addr_t>   r_cas_to_ixr_cmd_nline; // cache line index
711      sc_signal<size_t>   r_cas_to_ixr_cmd_trdid; // index in Transaction Table
712      sc_signal<bool>     r_cas_to_ixr_cmd_write; // write request
713      sc_signal<data_t> * r_cas_to_ixr_cmd_data;  // cache line data
714
715
716      // Buffer between CAS fsm and TGT_RSP fsm
717      sc_signal<bool>     r_cas_to_tgt_rsp_req;   // valid request
718      sc_signal<data_t>   r_cas_to_tgt_rsp_data;  // read data word
719      sc_signal<size_t>   r_cas_to_tgt_rsp_srcid; // Transaction srcid
720      sc_signal<size_t>   r_cas_to_tgt_rsp_trdid; // Transaction trdid
721      sc_signal<size_t>   r_cas_to_tgt_rsp_pktid; // Transaction pktid
722
723      // Buffer between CAS fsm and CC_SEND fsm (Update/Invalidate L1 caches)
724      sc_signal<bool>     r_cas_to_cc_send_multi_req;     // valid request
725      sc_signal<bool>     r_cas_to_cc_send_brdcast_req;   // brdcast request
726      sc_signal<addr_t>   r_cas_to_cc_send_nline;         // cache line index
727      sc_signal<size_t>   r_cas_to_cc_send_trdid;         // index in Update Table
728      sc_signal<data_t>   r_cas_to_cc_send_wdata;         // data (one word)
729      sc_signal<bool>     r_cas_to_cc_send_is_long;       // it is a 64 bits CAS
730      sc_signal<data_t>   r_cas_to_cc_send_wdata_high;    // data high (one word)
731      sc_signal<size_t>   r_cas_to_cc_send_index;         // index of the word in line
732      GenericFifo<bool>   m_cas_to_cc_send_inst_fifo;     // fifo for the L1 type
733      GenericFifo<size_t> m_cas_to_cc_send_srcid_fifo;    // fifo for srcids
734
735#if L1_MULTI_CACHE
736      GenericFifo<size_t> m_cas_to_cc_send_cache_id_fifo; // fifo for srcids
737#endif
738
739      ////////////////////////////////////////////////////
740      // Registers controlled by the IXR_RSP fsm
741      ////////////////////////////////////////////////////
742
743      sc_signal<int>      r_ixr_rsp_fsm;       // FSM state
744      sc_signal<size_t>   r_ixr_rsp_trt_index; // TRT entry index
745      sc_signal<size_t>   r_ixr_rsp_cpt;       // word counter
746
747      // Buffer between IXR_RSP fsm and XRAM_RSP fsm  (response from the XRAM)
748      sc_signal<bool>   * r_ixr_rsp_to_xram_rsp_rok; // A xram response is ready
749
750      ////////////////////////////////////////////////////
751      // Registers controlled by the XRAM_RSP fsm
752      ////////////////////////////////////////////////////
753
754      sc_signal<int>      r_xram_rsp_fsm;               // FSM state
755      sc_signal<size_t>   r_xram_rsp_trt_index;         // TRT entry index
756      TransactionTabEntry r_xram_rsp_trt_buf;           // TRT entry local buffer
757      sc_signal<bool>     r_xram_rsp_victim_inval;      // victim line invalidate
758      sc_signal<bool>     r_xram_rsp_victim_is_cnt;     // victim line inst bit
759      sc_signal<bool>     r_xram_rsp_victim_dirty;      // victim line dirty bit
760      sc_signal<size_t>   r_xram_rsp_victim_way;        // victim line way
761      sc_signal<size_t>   r_xram_rsp_victim_set;        // victim line set
762      sc_signal<addr_t>   r_xram_rsp_victim_nline;      // victim line index
763      sc_signal<copy_t>   r_xram_rsp_victim_copy;       // victim line first copy
764      sc_signal<copy_t>   r_xram_rsp_victim_copy_cache; // victim line first copy
765      sc_signal<bool>     r_xram_rsp_victim_copy_inst;  // victim line type of first copy
766      sc_signal<size_t>   r_xram_rsp_victim_count;      // victim line number of copies
767      sc_signal<size_t>   r_xram_rsp_victim_ptr;        // victim line pointer to the heap
768      sc_signal<data_t> * r_xram_rsp_victim_data;       // victim line data
769      sc_signal<size_t>   r_xram_rsp_upt_index;         // UPT entry index
770      sc_signal<size_t>   r_xram_rsp_next_ptr;          // Next pointer to the heap
771
772      // Buffer between XRAM_RSP fsm and TGT_RSP fsm  (response to L1 cache)
773      sc_signal<bool>     r_xram_rsp_to_tgt_rsp_req;    // Valid request
774      sc_signal<size_t>   r_xram_rsp_to_tgt_rsp_srcid;  // Transaction srcid
775      sc_signal<size_t>   r_xram_rsp_to_tgt_rsp_trdid;  // Transaction trdid
776      sc_signal<size_t>   r_xram_rsp_to_tgt_rsp_pktid;  // Transaction pktid
777      sc_signal<data_t> * r_xram_rsp_to_tgt_rsp_data;   // data (one cache line)
778      sc_signal<size_t>   r_xram_rsp_to_tgt_rsp_word;   // first word index
779      sc_signal<size_t>   r_xram_rsp_to_tgt_rsp_length; // length of the response
780      sc_signal<bool>     r_xram_rsp_to_tgt_rsp_rerror; // send error to requester
781      sc_signal<addr_t>   r_xram_rsp_to_tgt_rsp_ll_key; // LL key from llsc_global_table
782
783      // Buffer between XRAM_RSP fsm and CC_SEND fsm (Inval L1 Caches)
784      sc_signal<bool>     r_xram_rsp_to_cc_send_multi_req;     // Valid request
785      sc_signal<bool>     r_xram_rsp_to_cc_send_brdcast_req;   // Broadcast request
786      sc_signal<addr_t>   r_xram_rsp_to_cc_send_nline;         // cache line index;
787      sc_signal<size_t>   r_xram_rsp_to_cc_send_trdid;         // index of UPT entry
788      GenericFifo<bool>   m_xram_rsp_to_cc_send_inst_fifo;     // fifo for the L1 type
789      GenericFifo<size_t> m_xram_rsp_to_cc_send_srcid_fifo;    // fifo for srcids
790
791#if L1_MULTI_CACHE
792      GenericFifo<size_t> m_xram_rsp_to_cc_send_cache_id_fifo; // fifo for srcids
793#endif
794
795      // Buffer between XRAM_RSP fsm and IXR_CMD fsm (XRAM write)
796      sc_signal<bool>     r_xram_rsp_to_ixr_cmd_req;   // Valid request
797      sc_signal<addr_t>   r_xram_rsp_to_ixr_cmd_nline; // cache line index
798      sc_signal<data_t> * r_xram_rsp_to_ixr_cmd_data;  // cache line data
799      sc_signal<size_t>   r_xram_rsp_to_ixr_cmd_trdid; // index in transaction table
800
801      ////////////////////////////////////////////////////
802      // Registers controlled by the IXR_CMD fsm
803      ////////////////////////////////////////////////////
804
805      sc_signal<int>      r_ixr_cmd_fsm;
806      sc_signal<size_t>   r_ixr_cmd_cpt;
807
808      ////////////////////////////////////////////////////
809      // Registers controlled by TGT_RSP fsm
810      ////////////////////////////////////////////////////
811
812      sc_signal<int>      r_tgt_rsp_fsm;
813      sc_signal<size_t>   r_tgt_rsp_cpt;
814      sc_signal<bool>     r_tgt_rsp_key_sent;
815
816      ////////////////////////////////////////////////////
817      // Registers controlled by CC_SEND fsm
818      ////////////////////////////////////////////////////
819
820      sc_signal<int>      r_cc_send_fsm;
821      sc_signal<size_t>   r_cc_send_cpt;
822      sc_signal<bool>     r_cc_send_inst;
823
824      ////////////////////////////////////////////////////
825      // Registers controlled by CC_RECEIVE fsm
826      ////////////////////////////////////////////////////
827
828      sc_signal<int>      r_cc_receive_fsm;
829
830      ////////////////////////////////////////////////////
831      // Registers controlled by ALLOC_DIR fsm
832      ////////////////////////////////////////////////////
833
834      sc_signal<int>      r_alloc_dir_fsm;
835      sc_signal<unsigned> r_alloc_dir_reset_cpt;
836
837      ////////////////////////////////////////////////////
838      // Registers controlled by ALLOC_TRT fsm
839      ////////////////////////////////////////////////////
840
841      sc_signal<int>      r_alloc_trt_fsm;
842
843      ////////////////////////////////////////////////////
844      // Registers controlled by ALLOC_UPT fsm
845      ////////////////////////////////////////////////////
846
847      sc_signal<int>      r_alloc_upt_fsm;
848
849      ////////////////////////////////////////////////////
850      // Registers controlled by ALLOC_HEAP fsm
851      ////////////////////////////////////////////////////
852
853      sc_signal<int>      r_alloc_heap_fsm;
854      sc_signal<unsigned> r_alloc_heap_reset_cpt;
855    }; // end class VciMemCache
856
857}}
858
859#endif
860
861// Local Variables:
862// tab-width: 2
863// c-basic-offset: 2
864// c-file-offsets:((innamespace . 0)(inline-open . 0))
865// indent-tabs-mode: nil
866// End:
867
868// vim: filetype=cpp:expandtab:shiftwidth=2:tabstop=2:softtabstop=2
869
Note: See TracBrowser for help on using the repository browser.