source: trunk/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h @ 434

Last change on this file since 434 was 434, checked in by alain, 11 years ago

Introducing a preliminary configuration interface in vci_mem_cache.

File size: 39.7 KB
Line 
1/* -*- c++ -*-
2 * File         : vci_mem_cache.h
3 * Date         : 26/10/2008
4 * Copyright    : UPMC / LIP6
5 * Authors      : Alain Greiner / Eric Guthmuller
6 *
7 * SOCLIB_LGPL_HEADER_BEGIN
8 *
9 * This file is part of SoCLib, GNU LGPLv2.1.
10 *
11 * SoCLib is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU Lesser General Public License as published
13 * by the Free Software Foundation; version 2.1 of the License.
14 *
15 * SoCLib is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
18 * Lesser General Public License for more details.
19 *
20 * You should have received a copy of the GNU Lesser General Public
21 * License along with SoCLib; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
23 * 02110-1301 USA
24 *
25 * SOCLIB_LGPL_HEADER_END
26 *
27 * Maintainers: alain eric.guthmuller@polytechnique.edu
28 *              cesar.fuguet-tortolero@lip6.fr
29 *              alexandre.joannou@lip6.fr
30 */
31
32#ifndef SOCLIB_CABA_MEM_CACHE_H
33#define SOCLIB_CABA_MEM_CACHE_H
34
35#include <inttypes.h>
36#include <systemc>
37#include <list>
38#include <cassert>
39#include "arithmetics.h"
40#include "alloc_elems.h"
41#include "caba_base_module.h"
42#include "vci_target.h"
43#include "vci_initiator.h"
44#include "generic_fifo.h"
45#include "mapping_table.h"
46#include "int_tab.h"
47#include "generic_llsc_global_table.h"
48#include "mem_cache_directory.h"
49#include "xram_transaction.h"
50#include "update_tab.h"
51#include "dspin_interface.h"
52#include "dspin_dhccp_param.h"
53
54#define TRT_ENTRIES      4      // Number of entries in TRT
55#define UPT_ENTRIES      4      // Number of entries in UPT
56#define HEAP_ENTRIES     1024   // Number of entries in HEAP
57
58namespace soclib {  namespace caba {
59
60  using namespace sc_core;
61
62  template<typename vci_param_int, 
63           typename vci_param_ext,
64           size_t   dspin_in_width,
65           size_t   dspin_out_width>
66    class VciMemCache
67    : public soclib::caba::BaseModule
68    {
69      typedef typename vci_param_int::fast_addr_t  addr_t;
70
71      typedef typename sc_dt::sc_uint<64>          wide_data_t;
72
73      typedef uint32_t data_t;
74      typedef uint32_t tag_t;
75      typedef uint32_t be_t;
76      typedef uint32_t copy_t;
77
78      /* States of the TGT_CMD fsm */
79      enum tgt_cmd_fsm_state_e
80      {
81        TGT_CMD_IDLE,
82        TGT_CMD_ERROR,
83        TGT_CMD_READ,
84        TGT_CMD_WRITE,
85        TGT_CMD_CAS,
86        TGT_CMD_CONFIG
87      };
88
89      /* States of the TGT_RSP fsm */
90      enum tgt_rsp_fsm_state_e
91      {
92        TGT_RSP_TGT_CMD_IDLE,
93        TGT_RSP_READ_IDLE,
94        TGT_RSP_WRITE_IDLE,
95        TGT_RSP_CAS_IDLE,
96        TGT_RSP_XRAM_IDLE,
97        TGT_RSP_MULTI_ACK_IDLE,
98        TGT_RSP_CLEANUP_IDLE,
99        TGT_RSP_TGT_CMD,
100        TGT_RSP_READ,
101        TGT_RSP_WRITE,
102        TGT_RSP_CAS,
103        TGT_RSP_XRAM,
104        TGT_RSP_MULTI_ACK,
105        TGT_RSP_CLEANUP
106      };
107
108      /* States of the DSPIN_TGT fsm */
109      enum cc_receive_fsm_state_e
110      {
111        CC_RECEIVE_IDLE,
112        CC_RECEIVE_CLEANUP,
113        CC_RECEIVE_CLEANUP_EOP,
114        CC_RECEIVE_MULTI_ACK
115      };
116
117      /* States of the CC_SEND fsm */
118      enum cc_send_fsm_state_e
119      {
120        CC_SEND_XRAM_RSP_IDLE,
121        CC_SEND_WRITE_IDLE,
122        CC_SEND_CAS_IDLE,
123        CC_SEND_CLEANUP_IDLE,
124        CC_SEND_CLEANUP_ACK,
125        CC_SEND_XRAM_RSP_BRDCAST_HEADER,
126        CC_SEND_XRAM_RSP_BRDCAST_NLINE,
127        CC_SEND_XRAM_RSP_INVAL_HEADER,
128        CC_SEND_XRAM_RSP_INVAL_NLINE,
129        CC_SEND_WRITE_BRDCAST_HEADER,
130        CC_SEND_WRITE_BRDCAST_NLINE,
131        CC_SEND_WRITE_UPDT_HEADER,
132        CC_SEND_WRITE_UPDT_NLINE,
133        CC_SEND_WRITE_UPDT_DATA,
134        CC_SEND_CAS_BRDCAST_HEADER,
135        CC_SEND_CAS_BRDCAST_NLINE,
136        CC_SEND_CAS_UPDT_HEADER,
137        CC_SEND_CAS_UPDT_NLINE,
138        CC_SEND_CAS_UPDT_DATA,
139        CC_SEND_CAS_UPDT_DATA_HIGH
140      };
141
142      /* States of the MULTI_ACK fsm */
143      enum multi_ack_fsm_state_e
144      {
145        MULTI_ACK_IDLE,
146        MULTI_ACK_UPT_LOCK,
147        MULTI_ACK_UPT_CLEAR,
148        MULTI_ACK_WRITE_RSP,
149        MULTI_ACK_CONFIG_ACK
150      };
151
152      /* States of the CONFIG fsm */
153      enum config_fsm_state_e
154      {
155        CONFIG_IDLE,
156        CONFIG_LOOP,
157        CONFIG_RSP,
158        CONFIG_DIR_REQ,
159        CONFIG_DIR_ACCESS,
160        CONFIG_DIR_INVAL,
161        CONFIG_BC_UPT_LOCK,
162        CONFIG_BC_SEND,
163        CONFIG_BC_WAIT,
164       
165        CONFIG_UPT_WAIT,
166
167        CONFIG_UPT_LOCK,
168
169        CONFIG_HEAP_REQ
170      };
171
172      /* States of the READ fsm */
173      enum read_fsm_state_e
174      {
175        READ_IDLE,
176        READ_DIR_REQ,
177        READ_DIR_LOCK,
178        READ_DIR_HIT,
179        READ_HEAP_REQ,
180        READ_HEAP_LOCK,
181        READ_HEAP_WRITE,
182        READ_HEAP_ERASE,
183        READ_HEAP_LAST,
184        READ_RSP,
185        READ_TRT_LOCK,
186        READ_TRT_SET,
187        READ_TRT_REQ
188      };
189
190      /* States of the WRITE fsm */
191      enum write_fsm_state_e
192      {
193        WRITE_IDLE,
194        WRITE_NEXT,
195        WRITE_DIR_REQ,
196        WRITE_DIR_LOCK,
197        WRITE_DIR_READ,
198        WRITE_DIR_HIT,
199        WRITE_UPT_LOCK,
200        WRITE_UPT_HEAP_LOCK,
201        WRITE_UPT_REQ,
202        WRITE_UPT_NEXT,
203        WRITE_UPT_DEC,
204        WRITE_RSP,
205        WRITE_MISS_TRT_LOCK,
206        WRITE_MISS_TRT_DATA,
207        WRITE_MISS_TRT_SET,
208        WRITE_MISS_XRAM_REQ,
209        WRITE_BC_TRT_LOCK,
210        WRITE_BC_UPT_LOCK,
211        WRITE_BC_DIR_INVAL,
212        WRITE_BC_CC_SEND,
213        WRITE_BC_XRAM_REQ,
214        WRITE_WAIT
215      };
216
217      /* States of the IXR_RSP fsm */
218      enum ixr_rsp_fsm_state_e
219      {
220        IXR_RSP_IDLE,
221        IXR_RSP_ACK,
222        IXR_RSP_TRT_ERASE,
223        IXR_RSP_TRT_READ
224      };
225
226      /* States of the XRAM_RSP fsm */
227      enum xram_rsp_fsm_state_e
228      {
229        XRAM_RSP_IDLE,
230        XRAM_RSP_TRT_COPY,
231        XRAM_RSP_TRT_DIRTY,
232        XRAM_RSP_DIR_LOCK,
233        XRAM_RSP_DIR_UPDT,
234        XRAM_RSP_DIR_RSP,
235        XRAM_RSP_INVAL_LOCK,
236        XRAM_RSP_INVAL_WAIT,
237        XRAM_RSP_INVAL,
238        XRAM_RSP_WRITE_DIRTY,
239        XRAM_RSP_HEAP_REQ,
240        XRAM_RSP_HEAP_ERASE,
241        XRAM_RSP_HEAP_LAST,
242        XRAM_RSP_ERROR_ERASE,
243        XRAM_RSP_ERROR_RSP
244      };
245
246      /* States of the IXR_CMD fsm */
247      enum ixr_cmd_fsm_state_e
248      {
249        IXR_CMD_READ_IDLE,
250        IXR_CMD_WRITE_IDLE,
251        IXR_CMD_CAS_IDLE,
252        IXR_CMD_XRAM_IDLE,
253        IXR_CMD_READ,
254        IXR_CMD_WRITE,
255        IXR_CMD_CAS,
256        IXR_CMD_XRAM
257      };
258
259      /* States of the CAS fsm */
260      enum cas_fsm_state_e
261      {
262        CAS_IDLE,
263        CAS_DIR_REQ,
264        CAS_DIR_LOCK,
265        CAS_DIR_HIT_READ,
266        CAS_DIR_HIT_COMPARE,
267        CAS_DIR_HIT_WRITE,
268        CAS_UPT_LOCK,
269        CAS_UPT_HEAP_LOCK,
270        CAS_UPT_REQ,
271        CAS_UPT_NEXT,
272        CAS_BC_TRT_LOCK,
273        CAS_BC_UPT_LOCK,
274        CAS_BC_DIR_INVAL,
275        CAS_BC_CC_SEND,
276        CAS_BC_XRAM_REQ,
277        CAS_RSP_FAIL,
278        CAS_RSP_SUCCESS,
279        CAS_MISS_TRT_LOCK,
280        CAS_MISS_TRT_SET,
281        CAS_MISS_XRAM_REQ,
282        CAS_WAIT
283      };
284
285      /* States of the CLEANUP fsm */
286      enum cleanup_fsm_state_e
287      {
288        CLEANUP_IDLE,
289        CLEANUP_GET_NLINE,
290        CLEANUP_DIR_REQ,
291        CLEANUP_DIR_LOCK,
292        CLEANUP_DIR_WRITE,
293        CLEANUP_HEAP_REQ,
294        CLEANUP_HEAP_LOCK,
295        CLEANUP_HEAP_SEARCH,
296        CLEANUP_HEAP_CLEAN,
297        CLEANUP_HEAP_FREE,
298        CLEANUP_UPT_LOCK,
299        CLEANUP_UPT_DECREMENT,
300        CLEANUP_UPT_CLEAR,
301        CLEANUP_WRITE_RSP,
302        CLEANUP_CONFIG_ACK,
303        CLEANUP_SEND_CLACK
304      };
305
306      /* States of the ALLOC_DIR fsm */
307      enum alloc_dir_fsm_state_e
308      {
309        ALLOC_DIR_RESET,
310        ALLOC_DIR_CONFIG,
311        ALLOC_DIR_READ,
312        ALLOC_DIR_WRITE,
313        ALLOC_DIR_CAS,
314        ALLOC_DIR_CLEANUP,
315        ALLOC_DIR_XRAM_RSP
316      };
317
318      /* States of the ALLOC_TRT fsm */
319      enum alloc_trt_fsm_state_e
320      {
321        ALLOC_TRT_READ,
322        ALLOC_TRT_WRITE,
323        ALLOC_TRT_CAS,
324        ALLOC_TRT_XRAM_RSP,
325        ALLOC_TRT_IXR_RSP
326      };
327
328      /* States of the ALLOC_UPT fsm */
329      enum alloc_upt_fsm_state_e
330      {
331        ALLOC_UPT_CONFIG,
332        ALLOC_UPT_WRITE,
333        ALLOC_UPT_XRAM_RSP,
334        ALLOC_UPT_MULTI_ACK,
335        ALLOC_UPT_CLEANUP,
336        ALLOC_UPT_CAS
337      };
338
339      /* States of the ALLOC_HEAP fsm */
340      enum alloc_heap_fsm_state_e
341      {
342        ALLOC_HEAP_RESET,
343        ALLOC_HEAP_READ,
344        ALLOC_HEAP_WRITE,
345        ALLOC_HEAP_CAS,
346        ALLOC_HEAP_CLEANUP,
347        ALLOC_HEAP_XRAM_RSP
348      };
349
350      /* transaction type, pktid field */
351      enum transaction_type_e
352      {
353          // b3 unused
354          // b2 READ / NOT READ
355          // Si READ
356          //  b1 DATA / INS
357          //  b0 UNC / MISS
358          // Si NOT READ
359          //  b1 accÚs table llsc type SW / other
360          //  b2 WRITE/CAS/LL/SC
361          TYPE_READ_DATA_UNC          = 0x0,
362          TYPE_READ_DATA_MISS         = 0x1,
363          TYPE_READ_INS_UNC           = 0x2,
364          TYPE_READ_INS_MISS          = 0x3,
365          TYPE_WRITE                  = 0x4,
366          TYPE_CAS                    = 0x5,
367          TYPE_LL                     = 0x6,
368          TYPE_SC                     = 0x7
369      };
370
371      /* SC return values */
372      enum sc_status_type_e
373      {
374          SC_SUCCESS  =   0x00000000,
375          SC_FAIL     =   0x00000001
376      };
377
378      /* Configuration commands */
379      enum cmd_config_type_e
380      {
381          CMD_CONFIG_INVAL = 0,
382          CMD_CONFIG_SYNC  = 1
383      };
384
385      // debug variables (for each FSM)
386      bool         m_debug;
387      bool         m_debug_previous_hit;
388      size_t       m_debug_previous_count;
389
390      bool         m_monitor_ok;
391      addr_t       m_monitor_base;
392      addr_t       m_monitor_length;
393
394      // instrumentation counters
395      uint32_t     m_cpt_cycles;        // Counter of cycles
396
397      uint32_t     m_cpt_read;          // Number of READ transactions
398      uint32_t     m_cpt_read_remote;   // number of remote READ transactions
399      uint32_t     m_cpt_read_flits;    // number of flits for READs
400      uint32_t     m_cpt_read_cost;     // Number of (flits * distance) for READs
401
402      uint32_t     m_cpt_read_miss;     // Number of MISS READ
403
404      uint32_t     m_cpt_write;         // Number of WRITE transactions
405      uint32_t     m_cpt_write_remote;  // number of remote WRITE transactions
406      uint32_t     m_cpt_write_flits;   // number of flits for WRITEs
407      uint32_t     m_cpt_write_cost;    // Number of (flits * distance) for WRITEs
408
409      uint32_t     m_cpt_write_miss;    // Number of MISS WRITE
410      uint32_t     m_cpt_write_cells;   // Cumulated length for WRITE transactions
411      uint32_t     m_cpt_write_dirty;   // Cumulated length for WRITE transactions
412      uint32_t     m_cpt_update;        // Number of UPDATE transactions
413      uint32_t     m_cpt_trt_rb;        // Read blocked by a hit in trt
414      uint32_t     m_cpt_trt_full;      // Transaction blocked due to a full trt
415      uint32_t     m_cpt_update_mult;   // Number of targets for UPDATE
416      uint32_t     m_cpt_inval;         // Number of INVAL  transactions
417      uint32_t     m_cpt_inval_mult;    // Number of targets for INVAL
418      uint32_t     m_cpt_inval_brdcast; // Number of BROADCAST INVAL
419      uint32_t     m_cpt_cleanup;       // Number of CLEANUP transactions
420      uint32_t     m_cpt_ll;            // Number of LL transactions
421      uint32_t     m_cpt_sc;            // Number of SC transactions
422      uint32_t     m_cpt_cas;           // Number of CAS transactions
423
424      uint32_t     m_cpt_cleanup_cost;  // Number of (flits * distance) for CLEANUPs
425
426      uint32_t     m_cpt_update_flits;  // Number of flits for UPDATEs
427      uint32_t     m_cpt_update_cost;   // Number of (flits * distance) for UPDATEs
428
429      uint32_t     m_cpt_inval_cost;    // Number of (flits * distance) for INVALs
430
431      uint32_t     m_cpt_get;
432
433      uint32_t     m_cpt_put;
434
435      size_t       m_prev_count;
436
437      protected:
438
439      SC_HAS_PROCESS(VciMemCache);
440
441      public:
442      sc_in<bool>                                 p_clk;
443      sc_in<bool>                                 p_resetn;
444      soclib::caba::VciTarget<vci_param_int>      p_vci_tgt;
445      soclib::caba::VciInitiator<vci_param_ext>   p_vci_ixr;
446      soclib::caba::DspinInput<dspin_in_width>    p_dspin_in;
447      soclib::caba::DspinOutput<dspin_out_width>  p_dspin_out;
448
449      VciMemCache(
450          sc_module_name name,                                // Instance Name
451          const soclib::common::MappingTable &mtp,            // Mapping table INT network
452          const soclib::common::MappingTable &mtx,            // Mapping table RAM network
453          const soclib::common::IntTab       &srcid_x,        // global index RAM network
454          const soclib::common::IntTab       &tgtid_d,        // global index INT network
455          const size_t                       cc_global_id,    // global index CC network
456          const size_t                       nways,           // Number of ways per set
457          const size_t                       nsets,           // Number of sets
458          const size_t                       nwords,          // Number of words per line
459          const size_t                       max_copies,      // max number of copies
460          const size_t                       heap_size=HEAP_ENTRIES,
461          const size_t                       trt_lines=TRT_ENTRIES, 
462          const size_t                       upt_lines=UPT_ENTRIES,     
463          const size_t                       debug_start_cycle=0,
464          const bool                         debug_ok=false );
465
466      ~VciMemCache();
467
468      void print_stats();
469      void print_trace();
470      void copies_monitor(addr_t addr);
471      void start_monitor(addr_t addr, addr_t length);
472      void stop_monitor();
473
474      private:
475
476      void transition();
477      void genMoore();
478      void check_monitor( const char *buf, addr_t addr, data_t data, bool read);
479
480      // Component attributes
481      std::list<soclib::common::Segment> m_seglist;          // segments allocated
482      size_t                             m_nseg;             // number of segments
483      soclib::common::Segment            **m_seg;            // array of segments pointers
484      size_t                             m_seg_config;       // config segment index
485      const size_t                       m_srcid_x;          // global index on RAM network
486      const size_t                       m_initiators;       // Number of initiators
487      const size_t                       m_heap_size;        // Size of the heap
488      const size_t                       m_ways;             // Number of ways in a set
489      const size_t                       m_sets;             // Number of cache sets
490      const size_t                       m_words;            // Number of words in a line
491      const size_t                       m_cc_global_id;     // global_index on cc network
492      size_t                             m_debug_start_cycle;
493      bool                               m_debug_ok;
494      uint32_t                           m_trt_lines;
495      TransactionTab                     m_trt;              // xram transaction table
496      uint32_t                           m_upt_lines;
497      UpdateTab                          m_upt;              // pending update & invalidate
498      CacheDirectory                     m_cache_directory;  // data cache directory
499      CacheData                          m_cache_data;       // data array[set][way][word]
500      HeapDirectory                      m_heap;             // heap for copies
501      size_t                             m_max_copies;       // max number of copies in heap
502      GenericLLSCGlobalTable
503      < 32  ,    // number of slots
504        4096,    // number of processors in the system
505        8000,    // registration life (# of LL operations)
506        addr_t >                         m_llsc_table;       // ll/sc registration table
507
508      // adress masks
509      const soclib::common::AddressMaskingTable<addr_t>   m_x;
510      const soclib::common::AddressMaskingTable<addr_t>   m_y;
511      const soclib::common::AddressMaskingTable<addr_t>   m_z;
512      const soclib::common::AddressMaskingTable<addr_t>   m_nline;
513
514      // broadcast address
515      uint32_t                           m_broadcast_boundaries;
516
517      //////////////////////////////////////////////////
518      // Registers controlled by the TGT_CMD fsm
519      //////////////////////////////////////////////////
520
521      sc_signal<int>         r_tgt_cmd_fsm;
522
523      // Fifo between TGT_CMD fsm and READ fsm
524      GenericFifo<addr_t>    m_cmd_read_addr_fifo;
525      GenericFifo<size_t>    m_cmd_read_length_fifo;
526      GenericFifo<size_t>    m_cmd_read_srcid_fifo;
527      GenericFifo<size_t>    m_cmd_read_trdid_fifo;
528      GenericFifo<size_t>    m_cmd_read_pktid_fifo;
529
530      // Fifo between TGT_CMD fsm and WRITE fsm
531      GenericFifo<addr_t>    m_cmd_write_addr_fifo;
532      GenericFifo<bool>      m_cmd_write_eop_fifo;
533      GenericFifo<size_t>    m_cmd_write_srcid_fifo;
534      GenericFifo<size_t>    m_cmd_write_trdid_fifo;
535      GenericFifo<size_t>    m_cmd_write_pktid_fifo;
536      GenericFifo<data_t>    m_cmd_write_data_fifo;
537      GenericFifo<be_t>      m_cmd_write_be_fifo;
538
539      // Fifo between TGT_CMD fsm and CAS fsm
540      GenericFifo<addr_t>    m_cmd_cas_addr_fifo;
541      GenericFifo<bool>      m_cmd_cas_eop_fifo;
542      GenericFifo<size_t>    m_cmd_cas_srcid_fifo;
543      GenericFifo<size_t>    m_cmd_cas_trdid_fifo;
544      GenericFifo<size_t>    m_cmd_cas_pktid_fifo;
545      GenericFifo<data_t>    m_cmd_cas_wdata_fifo;
546
547      // Fifo between CC_RECEIVE fsm and CLEANUP fsm
548      GenericFifo<uint64_t>  m_cc_receive_to_cleanup_fifo;
549     
550      // Fifo between CC_RECEIVE fsm and MULTI_ACK fsm
551      GenericFifo<uint64_t>  m_cc_receive_to_multi_ack_fifo;
552
553      // Buffer between TGT_CMD fsm and TGT_RSP fsm
554      // (segmentation violation response request)
555      sc_signal<bool>     r_tgt_cmd_to_tgt_rsp_req;
556
557      sc_signal<uint32_t> r_tgt_cmd_to_tgt_rsp_rdata;
558      sc_signal<size_t>   r_tgt_cmd_to_tgt_rsp_error;
559      sc_signal<size_t>   r_tgt_cmd_to_tgt_rsp_srcid;
560      sc_signal<size_t>   r_tgt_cmd_to_tgt_rsp_trdid;
561      sc_signal<size_t>   r_tgt_cmd_to_tgt_rsp_pktid;
562
563      sc_signal<addr_t>   r_tgt_cmd_config_addr;
564      sc_signal<size_t>   r_tgt_cmd_config_cmd;
565
566      ///////////////////////////////////////////////////////
567      // Registers controlled by the CONFIG fsm
568      ///////////////////////////////////////////////////////
569
570      sc_signal<int>      r_config_fsm;        // FSM state
571      sc_signal<bool>     r_config_lock;       // lock protecting exclusive access
572      sc_signal<int>      r_config_cmd;        // config request status
573      sc_signal<addr_t>   r_config_address;    // target buffer physical address
574      sc_signal<size_t>   r_config_srcid;      // config request srcid
575      sc_signal<size_t>   r_config_trdid;      // config request trdid
576      sc_signal<size_t>   r_config_pktid;      // config request pktid
577      sc_signal<size_t>   r_config_nlines;     // number of lines covering the buffer
578      sc_signal<size_t>   r_config_way;        // selected way
579      sc_signal<size_t>   r_config_count;      // number of copies
580      sc_signal<size_t>   r_config_upt_index;  // UPT index
581      sc_signal<bool>     r_config_is_cnt;     // counter mode (broadcast required)
582
583      // Buffer between CONFIG fsm and TGT_RSP fsm (send a done response to L1 cache)
584      sc_signal<bool>     r_config_to_tgt_rsp_req;    // valid request
585      sc_signal<bool>     r_config_to_tgt_rsp_error;  // error response
586      sc_signal<size_t>   r_config_to_tgt_rsp_srcid;  // Transaction srcid
587      sc_signal<size_t>   r_config_to_tgt_rsp_trdid;  // Transaction trdid
588      sc_signal<size_t>   r_config_to_tgt_rsp_pktid;  // Transaction pktid
589
590      // Buffer between CONFIG fsm and CC_SEND fsm (multi-inval / broadcast-inval)
591      sc_signal<bool>     r_config_to_cc_send_multi_req;    // multi-inval request
592      sc_signal<bool>     r_config_to_cc_send_brdcast_req;  // broadcast-inval request
593      sc_signal<size_t>   r_config_to_cc_send_nline;        // line index
594      sc_signal<size_t>   r_config_to_cc_send_trdid;        // UPT index
595
596      ///////////////////////////////////////////////////////
597      // Registers controlled by the READ fsm
598      ///////////////////////////////////////////////////////
599
600      sc_signal<int>      r_read_fsm;          // FSM state
601      sc_signal<size_t>   r_read_copy;         // Srcid of the first copy
602      sc_signal<size_t>   r_read_copy_cache;   // Srcid of the first copy
603      sc_signal<bool>     r_read_copy_inst;    // Type of the first copy
604      sc_signal<tag_t>    r_read_tag;          // cache line tag (in directory)
605      sc_signal<bool>     r_read_is_cnt;       // is_cnt bit (in directory)
606      sc_signal<bool>     r_read_lock;         // lock bit (in directory)
607      sc_signal<bool>     r_read_dirty;        // dirty bit (in directory)
608      sc_signal<size_t>   r_read_count;        // number of copies
609      sc_signal<size_t>   r_read_ptr;          // pointer to the heap
610      sc_signal<data_t> * r_read_data;         // data (one cache line)
611      sc_signal<size_t>   r_read_way;          // associative way (in cache)
612      sc_signal<size_t>   r_read_trt_index;    // Transaction Table index
613      sc_signal<size_t>   r_read_next_ptr;     // Next entry to point to
614      sc_signal<bool>     r_read_last_free;    // Last free entry
615      sc_signal<addr_t>   r_read_ll_key;       // LL key from the llsc_global_table
616
617      // Buffer between READ fsm and IXR_CMD fsm (ask a missing cache line to XRAM)
618      sc_signal<bool>     r_read_to_ixr_cmd_req;    // valid request
619      sc_signal<addr_t>   r_read_to_ixr_cmd_nline;  // cache line index
620      sc_signal<size_t>   r_read_to_ixr_cmd_trdid;  // index in Transaction Table
621
622      // Buffer between READ fsm and TGT_RSP fsm (send a hit read response to L1 cache)
623      sc_signal<bool>     r_read_to_tgt_rsp_req;    // valid request
624      sc_signal<size_t>   r_read_to_tgt_rsp_srcid;  // Transaction srcid
625      sc_signal<size_t>   r_read_to_tgt_rsp_trdid;  // Transaction trdid
626      sc_signal<size_t>   r_read_to_tgt_rsp_pktid;  // Transaction pktid
627      sc_signal<data_t> * r_read_to_tgt_rsp_data;   // data (one cache line)
628      sc_signal<size_t>   r_read_to_tgt_rsp_word;   // first word of the response
629      sc_signal<size_t>   r_read_to_tgt_rsp_length; // length of the response
630      sc_signal<addr_t>   r_read_to_tgt_rsp_ll_key; // LL key from the llsc_global_table
631
632      ///////////////////////////////////////////////////////////////
633      // Registers controlled by the WRITE fsm
634      ///////////////////////////////////////////////////////////////
635
636      sc_signal<int>      r_write_fsm;        // FSM state
637      sc_signal<addr_t>   r_write_address;    // first word address
638      sc_signal<size_t>   r_write_word_index; // first word index in line
639      sc_signal<size_t>   r_write_word_count; // number of words in line
640      sc_signal<size_t>   r_write_srcid;      // transaction srcid
641      sc_signal<size_t>   r_write_trdid;      // transaction trdid
642      sc_signal<size_t>   r_write_pktid;      // transaction pktid
643      sc_signal<data_t> * r_write_data;       // data (one cache line)
644      sc_signal<be_t>   * r_write_be;         // one byte enable per word
645      sc_signal<bool>     r_write_byte;       // (BE != 0X0) and (BE != 0xF)
646      sc_signal<bool>     r_write_is_cnt;     // is_cnt bit (in directory)
647      sc_signal<bool>     r_write_lock;       // lock bit (in directory)
648      sc_signal<tag_t>    r_write_tag;        // cache line tag (in directory)
649      sc_signal<size_t>   r_write_copy;       // first owner of the line
650      sc_signal<size_t>   r_write_copy_cache; // first owner of the line
651      sc_signal<bool>     r_write_copy_inst;  // is this owner a ICache ?
652      sc_signal<size_t>   r_write_count;      // number of copies
653      sc_signal<size_t>   r_write_ptr;        // pointer to the heap
654      sc_signal<size_t>   r_write_next_ptr;   // next pointer to the heap
655      sc_signal<bool>     r_write_to_dec;     // need to decrement update counter
656      sc_signal<size_t>   r_write_way;        // way of the line
657      sc_signal<size_t>   r_write_trt_index;  // index in Transaction Table
658      sc_signal<size_t>   r_write_upt_index;  // index in Update Table
659      sc_signal<bool>     r_write_sc_fail;    // sc command failed
660      sc_signal<bool>     r_write_pending_sc; // sc command pending
661
662      // Buffer between WRITE fsm and TGT_RSP fsm (acknowledge a write command from L1)
663      sc_signal<bool>     r_write_to_tgt_rsp_req;     // valid request
664      sc_signal<size_t>   r_write_to_tgt_rsp_srcid;   // transaction srcid
665      sc_signal<size_t>   r_write_to_tgt_rsp_trdid;   // transaction trdid
666      sc_signal<size_t>   r_write_to_tgt_rsp_pktid;   // transaction pktid
667      sc_signal<bool>     r_write_to_tgt_rsp_sc_fail; // sc command failed
668
669      // Buffer between WRITE fsm and IXR_CMD fsm (ask a missing cache line to XRAM)
670      sc_signal<bool>     r_write_to_ixr_cmd_req;   // valid request
671      sc_signal<bool>     r_write_to_ixr_cmd_write; // write request
672      sc_signal<addr_t>   r_write_to_ixr_cmd_nline; // cache line index
673      sc_signal<data_t> * r_write_to_ixr_cmd_data;  // cache line data
674      sc_signal<size_t>   r_write_to_ixr_cmd_trdid; // index in Transaction Table
675
676      // Buffer between WRITE fsm and CC_SEND fsm (Update/Invalidate L1 caches)
677      sc_signal<bool>     r_write_to_cc_send_multi_req;     // valid multicast request
678      sc_signal<bool>     r_write_to_cc_send_brdcast_req;   // valid brdcast request
679      sc_signal<addr_t>   r_write_to_cc_send_nline;         // cache line index
680      sc_signal<size_t>   r_write_to_cc_send_trdid;         // index in Update Table
681      sc_signal<data_t> * r_write_to_cc_send_data;          // data (one cache line)
682      sc_signal<be_t>   * r_write_to_cc_send_be;            // word enable
683      sc_signal<size_t>   r_write_to_cc_send_count;         // number of words in line
684      sc_signal<size_t>   r_write_to_cc_send_index;         // index of first word in line
685      GenericFifo<bool>   m_write_to_cc_send_inst_fifo;     // fifo for the L1 type
686      GenericFifo<size_t> m_write_to_cc_send_srcid_fifo;    // fifo for srcids
687
688#if L1_MULTI_CACHE
689      GenericFifo<size_t> m_write_to_cc_send_cache_id_fifo; // fifo for srcids
690#endif
691
692      // Buffer between WRITE fsm and MULTI_ACK fsm (Decrement UPT entry)
693      sc_signal<bool>     r_write_to_multi_ack_req;       // valid request
694      sc_signal<size_t>   r_write_to_multi_ack_upt_index; // index in update table
695
696      /////////////////////////////////////////////////////////
697      // Registers controlled by MULTI_ACK fsm
698      //////////////////////////////////////////////////////////
699
700      sc_signal<int>      r_multi_ack_fsm;       // FSM state
701      sc_signal<size_t>   r_multi_ack_upt_index; // index in the Update Table
702      sc_signal<size_t>   r_multi_ack_srcid;     // pending write srcid
703      sc_signal<size_t>   r_multi_ack_trdid;     // pending write trdid
704      sc_signal<size_t>   r_multi_ack_pktid;     // pending write pktid
705      sc_signal<addr_t>   r_multi_ack_nline;     // pending write nline
706
707      // signaling completion of multi-inval to CONFIG fsm
708      sc_signal<bool>     r_multi_ack_to_config_ack; 
709
710      // Buffer between MULTI_ACK fsm and TGT_RSP fsm (complete write/update transaction)
711      sc_signal<bool>     r_multi_ack_to_tgt_rsp_req;   // valid request
712      sc_signal<size_t>   r_multi_ack_to_tgt_rsp_srcid; // Transaction srcid
713      sc_signal<size_t>   r_multi_ack_to_tgt_rsp_trdid; // Transaction trdid
714      sc_signal<size_t>   r_multi_ack_to_tgt_rsp_pktid; // Transaction pktid
715
716      ///////////////////////////////////////////////////////
717      // Registers controlled by CLEANUP fsm
718      ///////////////////////////////////////////////////////
719
720      sc_signal<int>      r_cleanup_fsm;           // FSM state
721      sc_signal<size_t>   r_cleanup_srcid;         // transaction srcid
722      sc_signal<bool>     r_cleanup_inst;          // Instruction or Data ?
723      sc_signal<size_t>   r_cleanup_way_index;     // L1 Cache Way index
724      sc_signal<addr_t>   r_cleanup_nline;         // cache line index
725
726#if L1_MULTI_CACHE
727      sc_signal<size_t>   r_cleanup_pktid;         // transaction pktid
728#endif
729
730      sc_signal<copy_t>   r_cleanup_copy;          // first copy
731      sc_signal<copy_t>   r_cleanup_copy_cache;    // first copy
732      sc_signal<size_t>   r_cleanup_copy_inst;     // type of the first copy
733      sc_signal<copy_t>   r_cleanup_count;         // number of copies
734      sc_signal<size_t>   r_cleanup_ptr;           // pointer to the heap
735      sc_signal<size_t>   r_cleanup_prev_ptr;      // previous pointer to the heap
736      sc_signal<size_t>   r_cleanup_prev_srcid;    // srcid of previous heap entry
737      sc_signal<size_t>   r_cleanup_prev_cache_id; // srcid of previous heap entry
738      sc_signal<bool>     r_cleanup_prev_inst;     // inst bit of previous heap entry
739      sc_signal<size_t>   r_cleanup_next_ptr;      // next pointer to the heap
740      sc_signal<tag_t>    r_cleanup_tag;           // cache line tag (in directory)
741      sc_signal<bool>     r_cleanup_is_cnt;        // inst bit (in directory)
742      sc_signal<bool>     r_cleanup_lock;          // lock bit (in directory)
743      sc_signal<bool>     r_cleanup_dirty;         // dirty bit (in directory)
744      sc_signal<size_t>   r_cleanup_way;           // associative way (in cache)
745
746      sc_signal<size_t>   r_cleanup_write_srcid;   // srcid of write rsp
747      sc_signal<size_t>   r_cleanup_write_trdid;   // trdid of write rsp
748      sc_signal<size_t>   r_cleanup_write_pktid;   // pktid of write rsp
749
750      sc_signal<bool>     r_cleanup_need_rsp;      // write response required
751      sc_signal<bool>     r_cleanup_need_ack;      // config acknowledge required
752
753      sc_signal<size_t>   r_cleanup_index;         // index of the INVAL line (in the UPT)
754
755      // signaling completion of broadcast-inval to CONFIG fsm
756      sc_signal<bool>     r_cleanup_to_config_ack; 
757       
758      // Buffer between CLEANUP fsm and TGT_RSP fsm (acknowledge a write command from L1)
759      sc_signal<bool>     r_cleanup_to_tgt_rsp_req;   // valid request
760      sc_signal<size_t>   r_cleanup_to_tgt_rsp_srcid; // transaction srcid
761      sc_signal<size_t>   r_cleanup_to_tgt_rsp_trdid; // transaction trdid
762      sc_signal<size_t>   r_cleanup_to_tgt_rsp_pktid; // transaction pktid
763
764      // Buffer between CLEANUP fsm and CC_SEND fsm (acknowledge a cleanup command from L1)
765      sc_signal<bool>     r_cleanup_to_cc_send_req;       // valid request
766      sc_signal<size_t>   r_cleanup_to_cc_send_srcid;     // L1 srcid
767      sc_signal<size_t>   r_cleanup_to_cc_send_set_index; // L1 set index
768      sc_signal<size_t>   r_cleanup_to_cc_send_way_index; // L1 way index
769      sc_signal<bool>     r_cleanup_to_cc_send_inst;      // Instruction Cleanup Ack
770
771      ///////////////////////////////////////////////////////
772      // Registers controlled by CAS fsm
773      ///////////////////////////////////////////////////////
774
775      sc_signal<int>      r_cas_fsm;        // FSM state
776      sc_signal<data_t>   r_cas_wdata;      // write data word
777      sc_signal<data_t> * r_cas_rdata;      // read data word
778      sc_signal<uint32_t> r_cas_lfsr;       // lfsr for random introducing
779      sc_signal<size_t>   r_cas_cpt;        // size of command
780      sc_signal<copy_t>   r_cas_copy;       // Srcid of the first copy
781      sc_signal<copy_t>   r_cas_copy_cache; // Srcid of the first copy
782      sc_signal<bool>     r_cas_copy_inst;  // Type of the first copy
783      sc_signal<size_t>   r_cas_count;      // number of copies
784      sc_signal<size_t>   r_cas_ptr;        // pointer to the heap
785      sc_signal<size_t>   r_cas_next_ptr;   // next pointer to the heap
786      sc_signal<bool>     r_cas_is_cnt;     // is_cnt bit (in directory)
787      sc_signal<bool>     r_cas_dirty;      // dirty bit (in directory)
788      sc_signal<size_t>   r_cas_way;        // way in directory
789      sc_signal<size_t>   r_cas_set;        // set in directory
790      sc_signal<data_t>   r_cas_tag;        // cache line tag (in directory)
791      sc_signal<size_t>   r_cas_trt_index;  // Transaction Table index
792      sc_signal<size_t>   r_cas_upt_index;  // Update Table index
793      sc_signal<data_t> * r_cas_data;       // cache line data
794
795      // Buffer between CAS fsm and IXR_CMD fsm (XRAM write)
796      sc_signal<bool>     r_cas_to_ixr_cmd_req;   // valid request
797      sc_signal<addr_t>   r_cas_to_ixr_cmd_nline; // cache line index
798      sc_signal<size_t>   r_cas_to_ixr_cmd_trdid; // index in Transaction Table
799      sc_signal<bool>     r_cas_to_ixr_cmd_write; // write request
800      sc_signal<data_t> * r_cas_to_ixr_cmd_data;  // cache line data
801
802
803      // Buffer between CAS fsm and TGT_RSP fsm
804      sc_signal<bool>     r_cas_to_tgt_rsp_req;   // valid request
805      sc_signal<data_t>   r_cas_to_tgt_rsp_data;  // read data word
806      sc_signal<size_t>   r_cas_to_tgt_rsp_srcid; // Transaction srcid
807      sc_signal<size_t>   r_cas_to_tgt_rsp_trdid; // Transaction trdid
808      sc_signal<size_t>   r_cas_to_tgt_rsp_pktid; // Transaction pktid
809
810      // Buffer between CAS fsm and CC_SEND fsm (Update/Invalidate L1 caches)
811      sc_signal<bool>     r_cas_to_cc_send_multi_req;     // valid request
812      sc_signal<bool>     r_cas_to_cc_send_brdcast_req;   // brdcast request
813      sc_signal<addr_t>   r_cas_to_cc_send_nline;         // cache line index
814      sc_signal<size_t>   r_cas_to_cc_send_trdid;         // index in Update Table
815      sc_signal<data_t>   r_cas_to_cc_send_wdata;         // data (one word)
816      sc_signal<bool>     r_cas_to_cc_send_is_long;       // it is a 64 bits CAS
817      sc_signal<data_t>   r_cas_to_cc_send_wdata_high;    // data high (one word)
818      sc_signal<size_t>   r_cas_to_cc_send_index;         // index of the word in line
819      GenericFifo<bool>   m_cas_to_cc_send_inst_fifo;     // fifo for the L1 type
820      GenericFifo<size_t> m_cas_to_cc_send_srcid_fifo;    // fifo for srcids
821
822#if L1_MULTI_CACHE
823      GenericFifo<size_t> m_cas_to_cc_send_cache_id_fifo; // fifo for srcids
824#endif
825
826      ////////////////////////////////////////////////////
827      // Registers controlled by the IXR_RSP fsm
828      ////////////////////////////////////////////////////
829
830      sc_signal<int>      r_ixr_rsp_fsm;       // FSM state
831      sc_signal<size_t>   r_ixr_rsp_trt_index; // TRT entry index
832      sc_signal<size_t>   r_ixr_rsp_cpt;       // word counter
833
834      // Buffer between IXR_RSP fsm and XRAM_RSP fsm  (response from the XRAM)
835      sc_signal<bool>   * r_ixr_rsp_to_xram_rsp_rok; // A xram response is ready
836
837      ////////////////////////////////////////////////////
838      // Registers controlled by the XRAM_RSP fsm
839      ////////////////////////////////////////////////////
840
841      sc_signal<int>      r_xram_rsp_fsm;               // FSM state
842      sc_signal<size_t>   r_xram_rsp_trt_index;         // TRT entry index
843      TransactionTabEntry r_xram_rsp_trt_buf;           // TRT entry local buffer
844      sc_signal<bool>     r_xram_rsp_victim_inval;      // victim line invalidate
845      sc_signal<bool>     r_xram_rsp_victim_is_cnt;     // victim line inst bit
846      sc_signal<bool>     r_xram_rsp_victim_dirty;      // victim line dirty bit
847      sc_signal<size_t>   r_xram_rsp_victim_way;        // victim line way
848      sc_signal<size_t>   r_xram_rsp_victim_set;        // victim line set
849      sc_signal<addr_t>   r_xram_rsp_victim_nline;      // victim line index
850      sc_signal<copy_t>   r_xram_rsp_victim_copy;       // victim line first copy
851      sc_signal<copy_t>   r_xram_rsp_victim_copy_cache; // victim line first copy
852      sc_signal<bool>     r_xram_rsp_victim_copy_inst;  // victim line type of first copy
853      sc_signal<size_t>   r_xram_rsp_victim_count;      // victim line number of copies
854      sc_signal<size_t>   r_xram_rsp_victim_ptr;        // victim line pointer to the heap
855      sc_signal<data_t> * r_xram_rsp_victim_data;       // victim line data
856      sc_signal<size_t>   r_xram_rsp_upt_index;         // UPT entry index
857      sc_signal<size_t>   r_xram_rsp_next_ptr;          // Next pointer to the heap
858
859      // Buffer between XRAM_RSP fsm and TGT_RSP fsm  (response to L1 cache)
860      sc_signal<bool>     r_xram_rsp_to_tgt_rsp_req;    // Valid request
861      sc_signal<size_t>   r_xram_rsp_to_tgt_rsp_srcid;  // Transaction srcid
862      sc_signal<size_t>   r_xram_rsp_to_tgt_rsp_trdid;  // Transaction trdid
863      sc_signal<size_t>   r_xram_rsp_to_tgt_rsp_pktid;  // Transaction pktid
864      sc_signal<data_t> * r_xram_rsp_to_tgt_rsp_data;   // data (one cache line)
865      sc_signal<size_t>   r_xram_rsp_to_tgt_rsp_word;   // first word index
866      sc_signal<size_t>   r_xram_rsp_to_tgt_rsp_length; // length of the response
867      sc_signal<bool>     r_xram_rsp_to_tgt_rsp_rerror; // send error to requester
868      sc_signal<addr_t>   r_xram_rsp_to_tgt_rsp_ll_key; // LL key from llsc_global_table
869
870      // Buffer between XRAM_RSP fsm and CC_SEND fsm (Inval L1 Caches)
871      sc_signal<bool>     r_xram_rsp_to_cc_send_multi_req;     // Valid request
872      sc_signal<bool>     r_xram_rsp_to_cc_send_brdcast_req;   // Broadcast request
873      sc_signal<addr_t>   r_xram_rsp_to_cc_send_nline;         // cache line index;
874      sc_signal<size_t>   r_xram_rsp_to_cc_send_trdid;         // index of UPT entry
875      GenericFifo<bool>   m_xram_rsp_to_cc_send_inst_fifo;     // fifo for the L1 type
876      GenericFifo<size_t> m_xram_rsp_to_cc_send_srcid_fifo;    // fifo for srcids
877
878#if L1_MULTI_CACHE
879      GenericFifo<size_t> m_xram_rsp_to_cc_send_cache_id_fifo; // fifo for srcids
880#endif
881
882      // Buffer between XRAM_RSP fsm and IXR_CMD fsm (XRAM write)
883      sc_signal<bool>     r_xram_rsp_to_ixr_cmd_req;   // Valid request
884      sc_signal<addr_t>   r_xram_rsp_to_ixr_cmd_nline; // cache line index
885      sc_signal<data_t> * r_xram_rsp_to_ixr_cmd_data;  // cache line data
886      sc_signal<size_t>   r_xram_rsp_to_ixr_cmd_trdid; // index in transaction table
887
888      ////////////////////////////////////////////////////
889      // Registers controlled by the IXR_CMD fsm
890      ////////////////////////////////////////////////////
891
892      sc_signal<int>      r_ixr_cmd_fsm;
893      sc_signal<size_t>   r_ixr_cmd_cpt;
894
895      ////////////////////////////////////////////////////
896      // Registers controlled by TGT_RSP fsm
897      ////////////////////////////////////////////////////
898
899      sc_signal<int>      r_tgt_rsp_fsm;
900      sc_signal<size_t>   r_tgt_rsp_cpt;
901      sc_signal<bool>     r_tgt_rsp_key_sent;
902
903      ////////////////////////////////////////////////////
904      // Registers controlled by CC_SEND fsm
905      ////////////////////////////////////////////////////
906
907      sc_signal<int>      r_cc_send_fsm;
908      sc_signal<size_t>   r_cc_send_cpt;
909      sc_signal<bool>     r_cc_send_inst;
910
911      ////////////////////////////////////////////////////
912      // Registers controlled by CC_RECEIVE fsm
913      ////////////////////////////////////////////////////
914
915      sc_signal<int>      r_cc_receive_fsm;
916
917      ////////////////////////////////////////////////////
918      // Registers controlled by ALLOC_DIR fsm
919      ////////////////////////////////////////////////////
920
921      sc_signal<int>      r_alloc_dir_fsm;
922      sc_signal<unsigned> r_alloc_dir_reset_cpt;
923
924      ////////////////////////////////////////////////////
925      // Registers controlled by ALLOC_TRT fsm
926      ////////////////////////////////////////////////////
927
928      sc_signal<int>      r_alloc_trt_fsm;
929
930      ////////////////////////////////////////////////////
931      // Registers controlled by ALLOC_UPT fsm
932      ////////////////////////////////////////////////////
933
934      sc_signal<int>      r_alloc_upt_fsm;
935
936      ////////////////////////////////////////////////////
937      // Registers controlled by ALLOC_HEAP fsm
938      ////////////////////////////////////////////////////
939
940      sc_signal<int>      r_alloc_heap_fsm;
941      sc_signal<unsigned> r_alloc_heap_reset_cpt;
942    }; // end class VciMemCache
943
944}}
945
946#endif
947
948// Local Variables:
949// tab-width: 2
950// c-basic-offset: 2
951// c-file-offsets:((innamespace . 0)(inline-open . 0))
952// indent-tabs-mode: nil
953// End:
954
955// vim: filetype=cpp:expandtab:shiftwidth=2:tabstop=2:softtabstop=2
956
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