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Last change
on this file since 601 was
601,
checked in by cfuguet, 9 years ago
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Modifications in vci_mem_cache:
- The out of segment read or write does not activate any more
an assert on the memory cache. Instead, the request is sent
to the XRAM and the error from the XRAM will be propagated
to the processor doing the access.
The propagation of the error is done in two different ways:
- When is a READ MISS: The error is propagated through the
VCI rerror to the processor doing the read.
- When is a WRITE MISS: The error is propagated through an
IRQ which normally is connected to the local XICU.
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